drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/reporter.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65
  66
  67 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  68 {
  69         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  70                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  71                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  72         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  73         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  74
  75         if (!striding_rq_umr)
  76                 return false;
  77         if (!inline_umr) {
  78                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  79                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  80                 return false;
  81         }
  82         return true;
  83 }
  84
  85 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  86                                struct mlx5e_params *params)
  87 {
  88         params->log_rq_mtu_frames = is_kdump_kernel() ?
  89                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  90                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  91
  92         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  93                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  94                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  95                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  96                        BIT(params->log_rq_mtu_frames),
  97                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
  98                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
  99 }
 100
 101 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 102                                 struct mlx5e_params *params)
 103 {
 104         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 105                 return false;
 106
 107         if (MLX5_IPSEC_DEV(mdev))
 108                 return false;
 109
 110         if (params->xdp_prog) {
 111                 /* XSK params are not considered here. If striding RQ is in use,
 112                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 113                  * be called with the known XSK params.
 114                  */
 115                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 116                         return false;
 117         }
 118
 119         return true;
 120 }
 121
 122 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 123 {
 124         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 125                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 126                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 127                 MLX5_WQ_TYPE_CYCLIC;
 128 }
 129
 130 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 131 {
 132         struct mlx5_core_dev *mdev = priv->mdev;
 133         u8 port_state;
 134
 135         port_state = mlx5_query_vport_state(mdev,
 136                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 137                                             0);
 138
 139         if (port_state == VPORT_STATE_UP) {
 140                 netdev_info(priv->netdev, "Link up\n");
 141                 netif_carrier_on(priv->netdev);
 142         } else {
 143                 netdev_info(priv->netdev, "Link down\n");
 144                 netif_carrier_off(priv->netdev);
 145         }
 146 }
 147
 148 static void mlx5e_update_carrier_work(struct work_struct *work)
 149 {
 150         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 151                                                update_carrier_work);
 152
 153         mutex_lock(&priv->state_lock);
 154         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 155                 if (priv->profile->update_carrier)
 156                         priv->profile->update_carrier(priv);
 157         mutex_unlock(&priv->state_lock);
 158 }
 159
 160 void mlx5e_update_stats(struct mlx5e_priv *priv)
 161 {
 162         int i;
 163
 164         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 165                 if (mlx5e_stats_grps[i].update_stats)
 166                         mlx5e_stats_grps[i].update_stats(priv);
 167 }
 168
 169 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 170 {
 171         int i;
 172
 173         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 174                 if (mlx5e_stats_grps[i].update_stats_mask &
 175                     MLX5E_NDO_UPDATE_STATS)
 176                         mlx5e_stats_grps[i].update_stats(priv);
 177 }
 178
 179 static void mlx5e_update_stats_work(struct work_struct *work)
 180 {
 181         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 182                                                update_stats_work);
 183
 184         mutex_lock(&priv->state_lock);
 185         priv->profile->update_stats(priv);
 186         mutex_unlock(&priv->state_lock);
 187 }
 188
 189 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 190 {
 191         if (!priv->profile->update_stats)
 192                 return;
 193
 194         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 195                 return;
 196
 197         queue_work(priv->wq, &priv->update_stats_work);
 198 }
 199
 200 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 201 {
 202         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 203         struct mlx5_eqe   *eqe = data;
 204
 205         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 206                 return NOTIFY_DONE;
 207
 208         switch (eqe->sub_type) {
 209         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 210         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 211                 queue_work(priv->wq, &priv->update_carrier_work);
 212                 break;
 213         default:
 214                 return NOTIFY_DONE;
 215         }
 216
 217         return NOTIFY_OK;
 218 }
 219
 220 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 221 {
 222         priv->events_nb.notifier_call = async_event;
 223         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 224 }
 225
 226 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 227 {
 228         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 229 }
 230
 231 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 232                                        struct mlx5e_icosq *sq,
 233                                        struct mlx5e_umr_wqe *wqe)
 234 {
 235         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 236         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 237         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 238
 239         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 240                                       ds_cnt);
 241         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 242         cseg->imm       = rq->mkey_be;
 243
 244         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 245         ucseg->xlt_octowords =
 246                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 247         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 248 }
 249
 250 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 251 {
 252         switch (rq->wq_type) {
 253         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 254                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 255         default:
 256                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 257         }
 258 }
 259
 260 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 261 {
 262         switch (rq->wq_type) {
 263         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 264                 return rq->mpwqe.wq.cur_sz;
 265         default:
 266                 return rq->wqe.wq.cur_sz;
 267         }
 268 }
 269
 270 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 271                                      struct mlx5e_channel *c)
 272 {
 273         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 274
 275         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 276                                                   sizeof(*rq->mpwqe.info)),
 277                                        GFP_KERNEL, cpu_to_node(c->cpu));
 278         if (!rq->mpwqe.info)
 279                 return -ENOMEM;
 280
 281         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 282
 283         return 0;
 284 }
 285
 286 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 287                                  u64 npages, u8 page_shift,
 288                                  struct mlx5_core_mkey *umr_mkey)
 289 {
 290         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 291         void *mkc;
 292         u32 *in;
 293         int err;
 294
 295         in = kvzalloc(inlen, GFP_KERNEL);
 296         if (!in)
 297                 return -ENOMEM;
 298
 299         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 300
 301         MLX5_SET(mkc, mkc, free, 1);
 302         MLX5_SET(mkc, mkc, umr_en, 1);
 303         MLX5_SET(mkc, mkc, lw, 1);
 304         MLX5_SET(mkc, mkc, lr, 1);
 305         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 306
 307         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 308         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 309         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 310         MLX5_SET(mkc, mkc, translations_octword_size,
 311                  MLX5_MTT_OCTW(npages));
 312         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 313
 314         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 315
 316         kvfree(in);
 317         return err;
 318 }
 319
 320 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 321 {
 322         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 323
 324         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 325 }
 326
 327 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 328 {
 329         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 330 }
 331
 332 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 333 {
 334         struct mlx5e_wqe_frag_info next_frag, *prev;
 335         int i;
 336
 337         next_frag.di = &rq->wqe.di[0];
 338         next_frag.offset = 0;
 339         prev = NULL;
 340
 341         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 342                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 343                 struct mlx5e_wqe_frag_info *frag =
 344                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 345                 int f;
 346
 347                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 348                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 349                                 next_frag.di++;
 350                                 next_frag.offset = 0;
 351                                 if (prev)
 352                                         prev->last_in_page = true;
 353                         }
 354                         *frag = next_frag;
 355
 356                         /* prepare next */
 357                         next_frag.offset += frag_info[f].frag_stride;
 358                         prev = frag;
 359                 }
 360         }
 361
 362         if (prev)
 363                 prev->last_in_page = true;
 364 }
 365
 366 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 367                               int wq_sz, int cpu)
 368 {
 369         int len = wq_sz << rq->wqe.info.log_num_frags;
 370
 371         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 372                                    GFP_KERNEL, cpu_to_node(cpu));
 373         if (!rq->wqe.di)
 374                 return -ENOMEM;
 375
 376         mlx5e_init_frags_partition(rq);
 377
 378         return 0;
 379 }
 380
 381 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 382 {
 383         kvfree(rq->wqe.di);
 384 }
 385
 386 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 387                           struct mlx5e_params *params,
 388                           struct mlx5e_xsk_param *xsk,
 389                           struct xdp_umem *umem,
 390                           struct mlx5e_rq_param *rqp,
 391                           struct mlx5e_rq *rq)
 392 {
 393         struct page_pool_params pp_params = { 0 };
 394         struct mlx5_core_dev *mdev = c->mdev;
 395         void *rqc = rqp->rqc;
 396         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 397         u32 num_xsk_frames = 0;
 398         u32 rq_xdp_ix;
 399         u32 pool_size;
 400         int wq_sz;
 401         int err;
 402         int i;
 403
 404         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 405
 406         rq->wq_type = params->rq_wq_type;
 407         rq->pdev    = c->pdev;
 408         rq->netdev  = c->netdev;
 409         rq->tstamp  = c->tstamp;
 410         rq->clock   = &mdev->clock;
 411         rq->channel = c;
 412         rq->ix      = c->ix;
 413         rq->mdev    = mdev;
 414         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 415         rq->xdpsq   = &c->rq_xdpsq;
 416         rq->umem    = umem;
 417
 418         if (rq->umem)
 419                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 420         else
 421                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 422
 423         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 424         if (IS_ERR(rq->xdp_prog)) {
 425                 err = PTR_ERR(rq->xdp_prog);
 426                 rq->xdp_prog = NULL;
 427                 goto err_rq_wq_destroy;
 428         }
 429
 430         rq_xdp_ix = rq->ix;
 431         if (xsk)
 432                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 433         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 434         if (err < 0)
 435                 goto err_rq_wq_destroy;
 436
 437         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 438         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 439         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 440         pool_size = 1 << params->log_rq_mtu_frames;
 441
 442         switch (rq->wq_type) {
 443         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 444                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 445                                         &rq->wq_ctrl);
 446                 if (err)
 447                         return err;
 448
 449                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 450
 451                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 452
 453                 if (xsk)
 454                         num_xsk_frames = wq_sz <<
 455                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 456
 457                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 458                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 459
 460                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 461                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 462
 463                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 464 #ifdef CONFIG_MLX5_EN_IPSEC
 465                 if (MLX5_IPSEC_DEV(mdev)) {
 466                         err = -EINVAL;
 467                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 468                         goto err_rq_wq_destroy;
 469                 }
 470 #endif
 471                 if (!rq->handle_rx_cqe) {
 472                         err = -EINVAL;
 473                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 474                         goto err_rq_wq_destroy;
 475                 }
 476
 477                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 478                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 479                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 480                                 mlx5e_skb_from_cqe_mpwrq_linear :
 481                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 482
 483                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 484                 rq->mpwqe.num_strides =
 485                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 486
 487                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 488                 if (err)
 489                         goto err_rq_wq_destroy;
 490                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 491
 492                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 493                 if (err)
 494                         goto err_free;
 495                 break;
 496         default: /* MLX5_WQ_TYPE_CYCLIC */
 497                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 498                                          &rq->wq_ctrl);
 499                 if (err)
 500                         return err;
 501
 502                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 503
 504                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 505
 506                 if (xsk)
 507                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 508
 509                 rq->wqe.info = rqp->frags_info;
 510                 rq->wqe.frags =
 511                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 512                                         (wq_sz << rq->wqe.info.log_num_frags)),
 513                                       GFP_KERNEL, cpu_to_node(c->cpu));
 514                 if (!rq->wqe.frags) {
 515                         err = -ENOMEM;
 516                         goto err_free;
 517                 }
 518
 519                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 520                 if (err)
 521                         goto err_free;
 522
 523                 rq->post_wqes = mlx5e_post_rx_wqes;
 524                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 525
 526 #ifdef CONFIG_MLX5_EN_IPSEC
 527                 if (c->priv->ipsec)
 528                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 529                 else
 530 #endif
 531                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 532                 if (!rq->handle_rx_cqe) {
 533                         err = -EINVAL;
 534                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 535                         goto err_free;
 536                 }
 537
 538                 rq->wqe.skb_from_cqe = xsk ?
 539                         mlx5e_xsk_skb_from_cqe_linear :
 540                         mlx5e_rx_is_linear_skb(params, NULL) ?
 541                                 mlx5e_skb_from_cqe_linear :
 542                                 mlx5e_skb_from_cqe_nonlinear;
 543                 rq->mkey_be = c->mkey_be;
 544         }
 545
 546         if (xsk) {
 547                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 548                 if (unlikely(err)) {
 549                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 550                                       num_xsk_frames);
 551                         goto err_free;
 552                 }
 553
 554                 rq->zca.free = mlx5e_xsk_zca_free;
 555                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 556                                                  MEM_TYPE_ZERO_COPY,
 557                                                  &rq->zca);
 558         } else {
 559                 /* Create a page_pool and register it with rxq */
 560                 pp_params.order     = 0;
 561                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 562                 pp_params.pool_size = pool_size;
 563                 pp_params.nid       = cpu_to_node(c->cpu);
 564                 pp_params.dev       = c->pdev;
 565                 pp_params.dma_dir   = rq->buff.map_dir;
 566
 567                 /* page_pool can be used even when there is no rq->xdp_prog,
 568                  * given page_pool does not handle DMA mapping there is no
 569                  * required state to clear. And page_pool gracefully handle
 570                  * elevated refcnt.
 571                  */
 572                 rq->page_pool = page_pool_create(&pp_params);
 573                 if (IS_ERR(rq->page_pool)) {
 574                         err = PTR_ERR(rq->page_pool);
 575                         rq->page_pool = NULL;
 576                         goto err_free;
 577                 }
 578                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 579                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 580                 if (err)
 581                         page_pool_free(rq->page_pool);
 582         }
 583         if (err)
 584                 goto err_free;
 585
 586         for (i = 0; i < wq_sz; i++) {
 587                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 588                         struct mlx5e_rx_wqe_ll *wqe =
 589                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 590                         u32 byte_count =
 591                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 592                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 593
 594                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 595                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 596                         wqe->data[0].lkey = rq->mkey_be;
 597                 } else {
 598                         struct mlx5e_rx_wqe_cyc *wqe =
 599                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 600                         int f;
 601
 602                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 603                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 604                                         MLX5_HW_START_PADDING;
 605
 606                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 607                                 wqe->data[f].lkey = rq->mkey_be;
 608                         }
 609                         /* check if num_frags is not a pow of two */
 610                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 611                                 wqe->data[f].byte_count = 0;
 612                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 613                                 wqe->data[f].addr = 0;
 614                         }
 615                 }
 616         }
 617
 618         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 619
 620         switch (params->rx_cq_moderation.cq_period_mode) {
 621         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 622                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 623                 break;
 624         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 625         default:
 626                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 627         }
 628
 629         rq->page_cache.head = 0;
 630         rq->page_cache.tail = 0;
 631
 632         return 0;
 633
 634 err_free:
 635         switch (rq->wq_type) {
 636         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 637                 kvfree(rq->mpwqe.info);
 638                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 639                 break;
 640         default: /* MLX5_WQ_TYPE_CYCLIC */
 641                 kvfree(rq->wqe.frags);
 642                 mlx5e_free_di_list(rq);
 643         }
 644
 645 err_rq_wq_destroy:
 646         if (rq->xdp_prog)
 647                 bpf_prog_put(rq->xdp_prog);
 648         xdp_rxq_info_unreg(&rq->xdp_rxq);
 649         mlx5_wq_destroy(&rq->wq_ctrl);
 650
 651         return err;
 652 }
 653
 654 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 655 {
 656         int i;
 657
 658         if (rq->xdp_prog)
 659                 bpf_prog_put(rq->xdp_prog);
 660
 661         switch (rq->wq_type) {
 662         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 663                 kvfree(rq->mpwqe.info);
 664                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 665                 break;
 666         default: /* MLX5_WQ_TYPE_CYCLIC */
 667                 kvfree(rq->wqe.frags);
 668                 mlx5e_free_di_list(rq);
 669         }
 670
 671         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 672              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 673                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 674
 675                 /* With AF_XDP, page_cache is not used, so this loop is not
 676                  * entered, and it's safe to call mlx5e_page_release_dynamic
 677                  * directly.
 678                  */
 679                 mlx5e_page_release_dynamic(rq, dma_info, false);
 680         }
 681
 682         xdp_rxq_info_unreg(&rq->xdp_rxq);
 683         mlx5_wq_destroy(&rq->wq_ctrl);
 684 }
 685
 686 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 687                            struct mlx5e_rq_param *param)
 688 {
 689         struct mlx5_core_dev *mdev = rq->mdev;
 690
 691         void *in;
 692         void *rqc;
 693         void *wq;
 694         int inlen;
 695         int err;
 696
 697         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 698                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 699         in = kvzalloc(inlen, GFP_KERNEL);
 700         if (!in)
 701                 return -ENOMEM;
 702
 703         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 704         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 705
 706         memcpy(rqc, param->rqc, sizeof(param->rqc));
 707
 708         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 709         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 710         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 711                                                 MLX5_ADAPTER_PAGE_SHIFT);
 712         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 713
 714         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 715                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 716
 717         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 718
 719         kvfree(in);
 720
 721         return err;
 722 }
 723
 724 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 725                                  int next_state)
 726 {
 727         struct mlx5_core_dev *mdev = rq->mdev;
 728
 729         void *in;
 730         void *rqc;
 731         int inlen;
 732         int err;
 733
 734         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 735         in = kvzalloc(inlen, GFP_KERNEL);
 736         if (!in)
 737                 return -ENOMEM;
 738
 739         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 740
 741         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 742         MLX5_SET(rqc, rqc, state, next_state);
 743
 744         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 745
 746         kvfree(in);
 747
 748         return err;
 749 }
 750
 751 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 752 {
 753         struct mlx5e_channel *c = rq->channel;
 754         struct mlx5e_priv *priv = c->priv;
 755         struct mlx5_core_dev *mdev = priv->mdev;
 756
 757         void *in;
 758         void *rqc;
 759         int inlen;
 760         int err;
 761
 762         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 763         in = kvzalloc(inlen, GFP_KERNEL);
 764         if (!in)
 765                 return -ENOMEM;
 766
 767         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 768
 769         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 770         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 771                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 772         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 773         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 774
 775         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 776
 777         kvfree(in);
 778
 779         return err;
 780 }
 781
 782 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 783 {
 784         struct mlx5e_channel *c = rq->channel;
 785         struct mlx5_core_dev *mdev = c->mdev;
 786         void *in;
 787         void *rqc;
 788         int inlen;
 789         int err;
 790
 791         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 792         in = kvzalloc(inlen, GFP_KERNEL);
 793         if (!in)
 794                 return -ENOMEM;
 795
 796         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 797
 798         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 799         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 800                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 801         MLX5_SET(rqc, rqc, vsd, vsd);
 802         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 803
 804         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 805
 806         kvfree(in);
 807
 808         return err;
 809 }
 810
 811 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 812 {
 813         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 814 }
 815
 816 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 817 {
 818         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 819         struct mlx5e_channel *c = rq->channel;
 820
 821         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 822
 823         do {
 824                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 825                         return 0;
 826
 827                 msleep(20);
 828         } while (time_before(jiffies, exp_time));
 829
 830         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 831                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 832
 833         return -ETIMEDOUT;
 834 }
 835
 836 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 837 {
 838         __be16 wqe_ix_be;
 839         u16 wqe_ix;
 840
 841         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 842                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 843                 u16 head = wq->head;
 844                 int i;
 845
 846                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 847                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 848                         rq->dealloc_wqe(rq, head);
 849                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 850                 }
 851
 852                 while (!mlx5_wq_ll_is_empty(wq)) {
 853                         struct mlx5e_rx_wqe_ll *wqe;
 854
 855                         wqe_ix_be = *wq->tail_next;
 856                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 857                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 858                         rq->dealloc_wqe(rq, wqe_ix);
 859                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 860                                        &wqe->next.next_wqe_index);
 861                 }
 862         } else {
 863                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 864
 865                 while (!mlx5_wq_cyc_is_empty(wq)) {
 866                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 867                         rq->dealloc_wqe(rq, wqe_ix);
 868                         mlx5_wq_cyc_pop(wq);
 869                 }
 870         }
 871
 872 }
 873
 874 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 875                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 876                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 877 {
 878         int err;
 879
 880         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 881         if (err)
 882                 return err;
 883
 884         err = mlx5e_create_rq(rq, param);
 885         if (err)
 886                 goto err_free_rq;
 887
 888         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 889         if (err)
 890                 goto err_destroy_rq;
 891
 892         if (params->rx_dim_enabled)
 893                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 894
 895         /* We disable csum_complete when XDP is enabled since
 896          * XDP programs might manipulate packets which will render
 897          * skb->checksum incorrect.
 898          */
 899         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 900                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 901
 902         return 0;
 903
 904 err_destroy_rq:
 905         mlx5e_destroy_rq(rq);
 906 err_free_rq:
 907         mlx5e_free_rq(rq);
 908
 909         return err;
 910 }
 911
 912 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 913 {
 914         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 915         mlx5e_trigger_irq(&rq->channel->icosq);
 916 }
 917
 918 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 919 {
 920         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 921         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 922 }
 923
 924 void mlx5e_close_rq(struct mlx5e_rq *rq)
 925 {
 926         cancel_work_sync(&rq->dim.work);
 927         mlx5e_destroy_rq(rq);
 928         mlx5e_free_rx_descs(rq);
 929         mlx5e_free_rq(rq);
 930 }
 931
 932 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 933 {
 934         kvfree(sq->db.xdpi_fifo.xi);
 935         kvfree(sq->db.wqe_info);
 936 }
 937
 938 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 939 {
 940         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 941         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 942         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 943
 944         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 945                                       GFP_KERNEL, numa);
 946         if (!xdpi_fifo->xi)
 947                 return -ENOMEM;
 948
 949         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 950         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 951         xdpi_fifo->mask = dsegs_per_wq - 1;
 952
 953         return 0;
 954 }
 955
 956 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 957 {
 958         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 959         int err;
 960
 961         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 962                                         GFP_KERNEL, numa);
 963         if (!sq->db.wqe_info)
 964                 return -ENOMEM;
 965
 966         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 967         if (err) {
 968                 mlx5e_free_xdpsq_db(sq);
 969                 return err;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 976                              struct mlx5e_params *params,
 977                              struct xdp_umem *umem,
 978                              struct mlx5e_sq_param *param,
 979                              struct mlx5e_xdpsq *sq,
 980                              bool is_redirect)
 981 {
 982         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 983         struct mlx5_core_dev *mdev = c->mdev;
 984         struct mlx5_wq_cyc *wq = &sq->wq;
 985         int err;
 986
 987         sq->pdev      = c->pdev;
 988         sq->mkey_be   = c->mkey_be;
 989         sq->channel   = c;
 990         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 991         sq->min_inline_mode = params->tx_min_inline_mode;
 992         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 993         sq->umem      = umem;
 994
 995         sq->stats = sq->umem ?
 996                 &c->priv->channel_stats[c->ix].xsksq :
 997                 is_redirect ?
 998                         &c->priv->channel_stats[c->ix].xdpsq :
 999                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1000
1001         param->wq.db_numa_node = cpu_to_node(c->cpu);
1002         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1003         if (err)
1004                 return err;
1005         wq->db = &wq->db[MLX5_SND_DBR];
1006
1007         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1008         if (err)
1009                 goto err_sq_wq_destroy;
1010
1011         return 0;
1012
1013 err_sq_wq_destroy:
1014         mlx5_wq_destroy(&sq->wq_ctrl);
1015
1016         return err;
1017 }
1018
1019 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1020 {
1021         mlx5e_free_xdpsq_db(sq);
1022         mlx5_wq_destroy(&sq->wq_ctrl);
1023 }
1024
1025 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1026 {
1027         kvfree(sq->db.ico_wqe);
1028 }
1029
1030 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1031 {
1032         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1033
1034         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1035                                                   sizeof(*sq->db.ico_wqe)),
1036                                        GFP_KERNEL, numa);
1037         if (!sq->db.ico_wqe)
1038                 return -ENOMEM;
1039
1040         return 0;
1041 }
1042
1043 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1044                              struct mlx5e_sq_param *param,
1045                              struct mlx5e_icosq *sq)
1046 {
1047         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1048         struct mlx5_core_dev *mdev = c->mdev;
1049         struct mlx5_wq_cyc *wq = &sq->wq;
1050         int err;
1051
1052         sq->channel   = c;
1053         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1054
1055         param->wq.db_numa_node = cpu_to_node(c->cpu);
1056         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1057         if (err)
1058                 return err;
1059         wq->db = &wq->db[MLX5_SND_DBR];
1060
1061         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1062         if (err)
1063                 goto err_sq_wq_destroy;
1064
1065         return 0;
1066
1067 err_sq_wq_destroy:
1068         mlx5_wq_destroy(&sq->wq_ctrl);
1069
1070         return err;
1071 }
1072
1073 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1074 {
1075         mlx5e_free_icosq_db(sq);
1076         mlx5_wq_destroy(&sq->wq_ctrl);
1077 }
1078
1079 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1080 {
1081         kvfree(sq->db.wqe_info);
1082         kvfree(sq->db.dma_fifo);
1083 }
1084
1085 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1086 {
1087         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1088         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1089
1090         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1091                                                    sizeof(*sq->db.dma_fifo)),
1092                                         GFP_KERNEL, numa);
1093         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1094                                                    sizeof(*sq->db.wqe_info)),
1095                                         GFP_KERNEL, numa);
1096         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1097                 mlx5e_free_txqsq_db(sq);
1098                 return -ENOMEM;
1099         }
1100
1101         sq->dma_fifo_mask = df_sz - 1;
1102
1103         return 0;
1104 }
1105
1106 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1107 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1108                              int txq_ix,
1109                              struct mlx5e_params *params,
1110                              struct mlx5e_sq_param *param,
1111                              struct mlx5e_txqsq *sq,
1112                              int tc)
1113 {
1114         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1115         struct mlx5_core_dev *mdev = c->mdev;
1116         struct mlx5_wq_cyc *wq = &sq->wq;
1117         int err;
1118
1119         sq->pdev      = c->pdev;
1120         sq->tstamp    = c->tstamp;
1121         sq->clock     = &mdev->clock;
1122         sq->mkey_be   = c->mkey_be;
1123         sq->channel   = c;
1124         sq->ch_ix     = c->ix;
1125         sq->txq_ix    = txq_ix;
1126         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1127         sq->min_inline_mode = params->tx_min_inline_mode;
1128         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1129         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1130         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1131         if (MLX5_IPSEC_DEV(c->priv->mdev))
1132                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1133         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1134                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1135                 sq->stop_room += MLX5E_SQ_TLS_ROOM;
1136         }
1137
1138         param->wq.db_numa_node = cpu_to_node(c->cpu);
1139         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1140         if (err)
1141                 return err;
1142         wq->db    = &wq->db[MLX5_SND_DBR];
1143
1144         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1145         if (err)
1146                 goto err_sq_wq_destroy;
1147
1148         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1149         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1150
1151         return 0;
1152
1153 err_sq_wq_destroy:
1154         mlx5_wq_destroy(&sq->wq_ctrl);
1155
1156         return err;
1157 }
1158
1159 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1160 {
1161         mlx5e_free_txqsq_db(sq);
1162         mlx5_wq_destroy(&sq->wq_ctrl);
1163 }
1164
1165 struct mlx5e_create_sq_param {
1166         struct mlx5_wq_ctrl        *wq_ctrl;
1167         u32                         cqn;
1168         u32                         tisn;
1169         u8                          tis_lst_sz;
1170         u8                          min_inline_mode;
1171 };
1172
1173 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1174                            struct mlx5e_sq_param *param,
1175                            struct mlx5e_create_sq_param *csp,
1176                            u32 *sqn)
1177 {
1178         void *in;
1179         void *sqc;
1180         void *wq;
1181         int inlen;
1182         int err;
1183
1184         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1185                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1186         in = kvzalloc(inlen, GFP_KERNEL);
1187         if (!in)
1188                 return -ENOMEM;
1189
1190         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1191         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1192
1193         memcpy(sqc, param->sqc, sizeof(param->sqc));
1194         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1195         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1196         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1197
1198         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1199                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1200
1201         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1202         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1203
1204         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1205         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1206         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1207                                           MLX5_ADAPTER_PAGE_SHIFT);
1208         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1209
1210         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1211                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1212
1213         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1214
1215         kvfree(in);
1216
1217         return err;
1218 }
1219
1220 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1221                     struct mlx5e_modify_sq_param *p)
1222 {
1223         void *in;
1224         void *sqc;
1225         int inlen;
1226         int err;
1227
1228         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1229         in = kvzalloc(inlen, GFP_KERNEL);
1230         if (!in)
1231                 return -ENOMEM;
1232
1233         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1234
1235         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1236         MLX5_SET(sqc, sqc, state, p->next_state);
1237         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1238                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1239                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1240         }
1241
1242         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1243
1244         kvfree(in);
1245
1246         return err;
1247 }
1248
1249 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1250 {
1251         mlx5_core_destroy_sq(mdev, sqn);
1252 }
1253
1254 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1255                                struct mlx5e_sq_param *param,
1256                                struct mlx5e_create_sq_param *csp,
1257                                u32 *sqn)
1258 {
1259         struct mlx5e_modify_sq_param msp = {0};
1260         int err;
1261
1262         err = mlx5e_create_sq(mdev, param, csp, sqn);
1263         if (err)
1264                 return err;
1265
1266         msp.curr_state = MLX5_SQC_STATE_RST;
1267         msp.next_state = MLX5_SQC_STATE_RDY;
1268         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1269         if (err)
1270                 mlx5e_destroy_sq(mdev, *sqn);
1271
1272         return err;
1273 }
1274
1275 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1276                                 struct mlx5e_txqsq *sq, u32 rate);
1277
1278 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1279                             u32 tisn,
1280                             int txq_ix,
1281                             struct mlx5e_params *params,
1282                             struct mlx5e_sq_param *param,
1283                             struct mlx5e_txqsq *sq,
1284                             int tc)
1285 {
1286         struct mlx5e_create_sq_param csp = {};
1287         u32 tx_rate;
1288         int err;
1289
1290         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1291         if (err)
1292                 return err;
1293
1294         csp.tisn            = tisn;
1295         csp.tis_lst_sz      = 1;
1296         csp.cqn             = sq->cq.mcq.cqn;
1297         csp.wq_ctrl         = &sq->wq_ctrl;
1298         csp.min_inline_mode = sq->min_inline_mode;
1299         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1300         if (err)
1301                 goto err_free_txqsq;
1302
1303         tx_rate = c->priv->tx_rates[sq->txq_ix];
1304         if (tx_rate)
1305                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1306
1307         if (params->tx_dim_enabled)
1308                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1309
1310         return 0;
1311
1312 err_free_txqsq:
1313         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1314         mlx5e_free_txqsq(sq);
1315
1316         return err;
1317 }
1318
1319 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1320 {
1321         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1322         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1323         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1324         netdev_tx_reset_queue(sq->txq);
1325         netif_tx_start_queue(sq->txq);
1326 }
1327
1328 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1329 {
1330         __netif_tx_lock_bh(txq);
1331         netif_tx_stop_queue(txq);
1332         __netif_tx_unlock_bh(txq);
1333 }
1334
1335 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1336 {
1337         struct mlx5e_channel *c = sq->channel;
1338         struct mlx5_wq_cyc *wq = &sq->wq;
1339
1340         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1341         /* prevent netif_tx_wake_queue */
1342         napi_synchronize(&c->napi);
1343
1344         mlx5e_tx_disable_queue(sq->txq);
1345
1346         /* last doorbell out, godspeed .. */
1347         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1348                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1349                 struct mlx5e_tx_wqe *nop;
1350
1351                 sq->db.wqe_info[pi].skb = NULL;
1352                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1353                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1354         }
1355 }
1356
1357 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1358 {
1359         struct mlx5e_channel *c = sq->channel;
1360         struct mlx5_core_dev *mdev = c->mdev;
1361         struct mlx5_rate_limit rl = {0};
1362
1363         cancel_work_sync(&sq->dim.work);
1364         cancel_work_sync(&sq->recover_work);
1365         mlx5e_destroy_sq(mdev, sq->sqn);
1366         if (sq->rate_limit) {
1367                 rl.rate = sq->rate_limit;
1368                 mlx5_rl_remove_rate(mdev, &rl);
1369         }
1370         mlx5e_free_txqsq_descs(sq);
1371         mlx5e_free_txqsq(sq);
1372 }
1373
1374 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1375 {
1376         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1377                                               recover_work);
1378
1379         mlx5e_tx_reporter_err_cqe(sq);
1380 }
1381
1382 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1383                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1384 {
1385         struct mlx5e_create_sq_param csp = {};
1386         int err;
1387
1388         err = mlx5e_alloc_icosq(c, param, sq);
1389         if (err)
1390                 return err;
1391
1392         csp.cqn             = sq->cq.mcq.cqn;
1393         csp.wq_ctrl         = &sq->wq_ctrl;
1394         csp.min_inline_mode = params->tx_min_inline_mode;
1395         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1396         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1397         if (err)
1398                 goto err_free_icosq;
1399
1400         return 0;
1401
1402 err_free_icosq:
1403         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1404         mlx5e_free_icosq(sq);
1405
1406         return err;
1407 }
1408
1409 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1410 {
1411         struct mlx5e_channel *c = sq->channel;
1412
1413         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1414         napi_synchronize(&c->napi);
1415
1416         mlx5e_destroy_sq(c->mdev, sq->sqn);
1417         mlx5e_free_icosq(sq);
1418 }
1419
1420 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1421                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1422                      struct mlx5e_xdpsq *sq, bool is_redirect)
1423 {
1424         struct mlx5e_create_sq_param csp = {};
1425         int err;
1426
1427         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1428         if (err)
1429                 return err;
1430
1431         csp.tis_lst_sz      = 1;
1432         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1433         csp.cqn             = sq->cq.mcq.cqn;
1434         csp.wq_ctrl         = &sq->wq_ctrl;
1435         csp.min_inline_mode = sq->min_inline_mode;
1436         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1437         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1438         if (err)
1439                 goto err_free_xdpsq;
1440
1441         mlx5e_set_xmit_fp(sq, param->is_mpw);
1442
1443         if (!param->is_mpw) {
1444                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1445                 unsigned int inline_hdr_sz = 0;
1446                 int i;
1447
1448                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1449                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1450                         ds_cnt++;
1451                 }
1452
1453                 /* Pre initialize fixed WQE fields */
1454                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1455                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1456                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1457                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1458                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1459                         struct mlx5_wqe_data_seg *dseg;
1460
1461                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1462                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1463
1464                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1465                         dseg->lkey = sq->mkey_be;
1466
1467                         wi->num_wqebbs = 1;
1468                         wi->num_pkts   = 1;
1469                 }
1470         }
1471
1472         return 0;
1473
1474 err_free_xdpsq:
1475         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1476         mlx5e_free_xdpsq(sq);
1477
1478         return err;
1479 }
1480
1481 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1482 {
1483         struct mlx5e_channel *c = sq->channel;
1484
1485         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1486         napi_synchronize(&c->napi);
1487
1488         mlx5e_destroy_sq(c->mdev, sq->sqn);
1489         mlx5e_free_xdpsq_descs(sq);
1490         mlx5e_free_xdpsq(sq);
1491 }
1492
1493 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1494                                  struct mlx5e_cq_param *param,
1495                                  struct mlx5e_cq *cq)
1496 {
1497         struct mlx5_core_cq *mcq = &cq->mcq;
1498         int eqn_not_used;
1499         unsigned int irqn;
1500         int err;
1501         u32 i;
1502
1503         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1504         if (err)
1505                 return err;
1506
1507         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1508                                &cq->wq_ctrl);
1509         if (err)
1510                 return err;
1511
1512         mcq->cqe_sz     = 64;
1513         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1514         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1515         *mcq->set_ci_db = 0;
1516         *mcq->arm_db    = 0;
1517         mcq->vector     = param->eq_ix;
1518         mcq->comp       = mlx5e_completion_event;
1519         mcq->event      = mlx5e_cq_error_event;
1520         mcq->irqn       = irqn;
1521
1522         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1523                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1524
1525                 cqe->op_own = 0xf1;
1526         }
1527
1528         cq->mdev = mdev;
1529
1530         return 0;
1531 }
1532
1533 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1534                           struct mlx5e_cq_param *param,
1535                           struct mlx5e_cq *cq)
1536 {
1537         struct mlx5_core_dev *mdev = c->priv->mdev;
1538         int err;
1539
1540         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1541         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1542         param->eq_ix   = c->ix;
1543
1544         err = mlx5e_alloc_cq_common(mdev, param, cq);
1545
1546         cq->napi    = &c->napi;
1547         cq->channel = c;
1548
1549         return err;
1550 }
1551
1552 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1553 {
1554         mlx5_wq_destroy(&cq->wq_ctrl);
1555 }
1556
1557 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1558 {
1559         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1560         struct mlx5_core_dev *mdev = cq->mdev;
1561         struct mlx5_core_cq *mcq = &cq->mcq;
1562
1563         void *in;
1564         void *cqc;
1565         int inlen;
1566         unsigned int irqn_not_used;
1567         int eqn;
1568         int err;
1569
1570         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1571         if (err)
1572                 return err;
1573
1574         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1575                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1576         in = kvzalloc(inlen, GFP_KERNEL);
1577         if (!in)
1578                 return -ENOMEM;
1579
1580         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1581
1582         memcpy(cqc, param->cqc, sizeof(param->cqc));
1583
1584         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1585                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1586
1587         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1588         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1589         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1590         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1591                                             MLX5_ADAPTER_PAGE_SHIFT);
1592         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1593
1594         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1595
1596         kvfree(in);
1597
1598         if (err)
1599                 return err;
1600
1601         mlx5e_cq_arm(cq);
1602
1603         return 0;
1604 }
1605
1606 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1607 {
1608         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1609 }
1610
1611 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1612                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1613 {
1614         struct mlx5_core_dev *mdev = c->mdev;
1615         int err;
1616
1617         err = mlx5e_alloc_cq(c, param, cq);
1618         if (err)
1619                 return err;
1620
1621         err = mlx5e_create_cq(cq, param);
1622         if (err)
1623                 goto err_free_cq;
1624
1625         if (MLX5_CAP_GEN(mdev, cq_moderation))
1626                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1627         return 0;
1628
1629 err_free_cq:
1630         mlx5e_free_cq(cq);
1631
1632         return err;
1633 }
1634
1635 void mlx5e_close_cq(struct mlx5e_cq *cq)
1636 {
1637         mlx5e_destroy_cq(cq);
1638         mlx5e_free_cq(cq);
1639 }
1640
1641 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1642                              struct mlx5e_params *params,
1643                              struct mlx5e_channel_param *cparam)
1644 {
1645         int err;
1646         int tc;
1647
1648         for (tc = 0; tc < c->num_tc; tc++) {
1649                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1650                                     &cparam->tx_cq, &c->sq[tc].cq);
1651                 if (err)
1652                         goto err_close_tx_cqs;
1653         }
1654
1655         return 0;
1656
1657 err_close_tx_cqs:
1658         for (tc--; tc >= 0; tc--)
1659                 mlx5e_close_cq(&c->sq[tc].cq);
1660
1661         return err;
1662 }
1663
1664 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1665 {
1666         int tc;
1667
1668         for (tc = 0; tc < c->num_tc; tc++)
1669                 mlx5e_close_cq(&c->sq[tc].cq);
1670 }
1671
1672 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1673                           struct mlx5e_params *params,
1674                           struct mlx5e_channel_param *cparam)
1675 {
1676         struct mlx5e_priv *priv = c->priv;
1677         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1678
1679         for (tc = 0; tc < params->num_tc; tc++) {
1680                 int txq_ix = c->ix + tc * max_nch;
1681
1682                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1683                                        params, &cparam->sq, &c->sq[tc], tc);
1684                 if (err)
1685                         goto err_close_sqs;
1686         }
1687
1688         return 0;
1689
1690 err_close_sqs:
1691         for (tc--; tc >= 0; tc--)
1692                 mlx5e_close_txqsq(&c->sq[tc]);
1693
1694         return err;
1695 }
1696
1697 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1698 {
1699         int tc;
1700
1701         for (tc = 0; tc < c->num_tc; tc++)
1702                 mlx5e_close_txqsq(&c->sq[tc]);
1703 }
1704
1705 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1706                                 struct mlx5e_txqsq *sq, u32 rate)
1707 {
1708         struct mlx5e_priv *priv = netdev_priv(dev);
1709         struct mlx5_core_dev *mdev = priv->mdev;
1710         struct mlx5e_modify_sq_param msp = {0};
1711         struct mlx5_rate_limit rl = {0};
1712         u16 rl_index = 0;
1713         int err;
1714
1715         if (rate == sq->rate_limit)
1716                 /* nothing to do */
1717                 return 0;
1718
1719         if (sq->rate_limit) {
1720                 rl.rate = sq->rate_limit;
1721                 /* remove current rl index to free space to next ones */
1722                 mlx5_rl_remove_rate(mdev, &rl);
1723         }
1724
1725         sq->rate_limit = 0;
1726
1727         if (rate) {
1728                 rl.rate = rate;
1729                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1730                 if (err) {
1731                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1732                                    rate, err);
1733                         return err;
1734                 }
1735         }
1736
1737         msp.curr_state = MLX5_SQC_STATE_RDY;
1738         msp.next_state = MLX5_SQC_STATE_RDY;
1739         msp.rl_index   = rl_index;
1740         msp.rl_update  = true;
1741         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1742         if (err) {
1743                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1744                            rate, err);
1745                 /* remove the rate from the table */
1746                 if (rate)
1747                         mlx5_rl_remove_rate(mdev, &rl);
1748                 return err;
1749         }
1750
1751         sq->rate_limit = rate;
1752         return 0;
1753 }
1754
1755 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1756 {
1757         struct mlx5e_priv *priv = netdev_priv(dev);
1758         struct mlx5_core_dev *mdev = priv->mdev;
1759         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1760         int err = 0;
1761
1762         if (!mlx5_rl_is_supported(mdev)) {
1763                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1764                 return -EINVAL;
1765         }
1766
1767         /* rate is given in Mb/sec, HW config is in Kb/sec */
1768         rate = rate << 10;
1769
1770         /* Check whether rate in valid range, 0 is always valid */
1771         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1772                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1773                 return -ERANGE;
1774         }
1775
1776         mutex_lock(&priv->state_lock);
1777         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1778                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1779         if (!err)
1780                 priv->tx_rates[index] = rate;
1781         mutex_unlock(&priv->state_lock);
1782
1783         return err;
1784 }
1785
1786 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1787                                    struct mlx5e_params *params)
1788 {
1789         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1790         int irq;
1791
1792         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1793                 return -ENOMEM;
1794
1795         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1796                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1797
1798                 cpumask_set_cpu(cpu, c->xps_cpumask);
1799         }
1800
1801         return 0;
1802 }
1803
1804 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1805 {
1806         free_cpumask_var(c->xps_cpumask);
1807 }
1808
1809 static int mlx5e_open_queues(struct mlx5e_channel *c,
1810                              struct mlx5e_params *params,
1811                              struct mlx5e_channel_param *cparam)
1812 {
1813         struct dim_cq_moder icocq_moder = {0, 0};
1814         int err;
1815
1816         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1817         if (err)
1818                 return err;
1819
1820         err = mlx5e_open_tx_cqs(c, params, cparam);
1821         if (err)
1822                 goto err_close_icosq_cq;
1823
1824         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1825         if (err)
1826                 goto err_close_tx_cqs;
1827
1828         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1829         if (err)
1830                 goto err_close_xdp_tx_cqs;
1831
1832         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1833         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1834                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1835         if (err)
1836                 goto err_close_rx_cq;
1837
1838         napi_enable(&c->napi);
1839
1840         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1841         if (err)
1842                 goto err_disable_napi;
1843
1844         err = mlx5e_open_sqs(c, params, cparam);
1845         if (err)
1846                 goto err_close_icosq;
1847
1848         if (c->xdp) {
1849                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1850                                        &c->rq_xdpsq, false);
1851                 if (err)
1852                         goto err_close_sqs;
1853         }
1854
1855         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1856         if (err)
1857                 goto err_close_xdp_sq;
1858
1859         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1860         if (err)
1861                 goto err_close_rq;
1862
1863         return 0;
1864
1865 err_close_rq:
1866         mlx5e_close_rq(&c->rq);
1867
1868 err_close_xdp_sq:
1869         if (c->xdp)
1870                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1871
1872 err_close_sqs:
1873         mlx5e_close_sqs(c);
1874
1875 err_close_icosq:
1876         mlx5e_close_icosq(&c->icosq);
1877
1878 err_disable_napi:
1879         napi_disable(&c->napi);
1880
1881         if (c->xdp)
1882                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1883
1884 err_close_rx_cq:
1885         mlx5e_close_cq(&c->rq.cq);
1886
1887 err_close_xdp_tx_cqs:
1888         mlx5e_close_cq(&c->xdpsq.cq);
1889
1890 err_close_tx_cqs:
1891         mlx5e_close_tx_cqs(c);
1892
1893 err_close_icosq_cq:
1894         mlx5e_close_cq(&c->icosq.cq);
1895
1896         return err;
1897 }
1898
1899 static void mlx5e_close_queues(struct mlx5e_channel *c)
1900 {
1901         mlx5e_close_xdpsq(&c->xdpsq);
1902         mlx5e_close_rq(&c->rq);
1903         if (c->xdp)
1904                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1905         mlx5e_close_sqs(c);
1906         mlx5e_close_icosq(&c->icosq);
1907         napi_disable(&c->napi);
1908         if (c->xdp)
1909                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1910         mlx5e_close_cq(&c->rq.cq);
1911         mlx5e_close_cq(&c->xdpsq.cq);
1912         mlx5e_close_tx_cqs(c);
1913         mlx5e_close_cq(&c->icosq.cq);
1914 }
1915
1916 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1917                               struct mlx5e_params *params,
1918                               struct mlx5e_channel_param *cparam,
1919                               struct xdp_umem *umem,
1920                               struct mlx5e_channel **cp)
1921 {
1922         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1923         struct net_device *netdev = priv->netdev;
1924         struct mlx5e_xsk_param xsk;
1925         struct mlx5e_channel *c;
1926         unsigned int irq;
1927         int err;
1928         int eqn;
1929
1930         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1931         if (err)
1932                 return err;
1933
1934         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1935         if (!c)
1936                 return -ENOMEM;
1937
1938         c->priv     = priv;
1939         c->mdev     = priv->mdev;
1940         c->tstamp   = &priv->tstamp;
1941         c->ix       = ix;
1942         c->cpu      = cpu;
1943         c->pdev     = priv->mdev->device;
1944         c->netdev   = priv->netdev;
1945         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1946         c->num_tc   = params->num_tc;
1947         c->xdp      = !!params->xdp_prog;
1948         c->stats    = &priv->channel_stats[ix].ch;
1949         c->irq_desc = irq_to_desc(irq);
1950
1951         err = mlx5e_alloc_xps_cpumask(c, params);
1952         if (err)
1953                 goto err_free_channel;
1954
1955         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1956
1957         err = mlx5e_open_queues(c, params, cparam);
1958         if (unlikely(err))
1959                 goto err_napi_del;
1960
1961         if (umem) {
1962                 mlx5e_build_xsk_param(umem, &xsk);
1963                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1964                 if (unlikely(err))
1965                         goto err_close_queues;
1966         }
1967
1968         *cp = c;
1969
1970         return 0;
1971
1972 err_close_queues:
1973         mlx5e_close_queues(c);
1974
1975 err_napi_del:
1976         netif_napi_del(&c->napi);
1977         mlx5e_free_xps_cpumask(c);
1978
1979 err_free_channel:
1980         kvfree(c);
1981
1982         return err;
1983 }
1984
1985 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1986 {
1987         int tc;
1988
1989         for (tc = 0; tc < c->num_tc; tc++)
1990                 mlx5e_activate_txqsq(&c->sq[tc]);
1991         mlx5e_activate_rq(&c->rq);
1992         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
1993
1994         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
1995                 mlx5e_activate_xsk(c);
1996 }
1997
1998 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1999 {
2000         int tc;
2001
2002         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2003                 mlx5e_deactivate_xsk(c);
2004
2005         mlx5e_deactivate_rq(&c->rq);
2006         for (tc = 0; tc < c->num_tc; tc++)
2007                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2008 }
2009
2010 static void mlx5e_close_channel(struct mlx5e_channel *c)
2011 {
2012         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2013                 mlx5e_close_xsk(c);
2014         mlx5e_close_queues(c);
2015         netif_napi_del(&c->napi);
2016         mlx5e_free_xps_cpumask(c);
2017
2018         kvfree(c);
2019 }
2020
2021 #define DEFAULT_FRAG_SIZE (2048)
2022
2023 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2024                                       struct mlx5e_params *params,
2025                                       struct mlx5e_xsk_param *xsk,
2026                                       struct mlx5e_rq_frags_info *info)
2027 {
2028         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2029         int frag_size_max = DEFAULT_FRAG_SIZE;
2030         u32 buf_size = 0;
2031         int i;
2032
2033 #ifdef CONFIG_MLX5_EN_IPSEC
2034         if (MLX5_IPSEC_DEV(mdev))
2035                 byte_count += MLX5E_METADATA_ETHER_LEN;
2036 #endif
2037
2038         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2039                 int frag_stride;
2040
2041                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2042                 frag_stride = roundup_pow_of_two(frag_stride);
2043
2044                 info->arr[0].frag_size = byte_count;
2045                 info->arr[0].frag_stride = frag_stride;
2046                 info->num_frags = 1;
2047                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2048                 goto out;
2049         }
2050
2051         if (byte_count > PAGE_SIZE +
2052             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2053                 frag_size_max = PAGE_SIZE;
2054
2055         i = 0;
2056         while (buf_size < byte_count) {
2057                 int frag_size = byte_count - buf_size;
2058
2059                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2060                         frag_size = min(frag_size, frag_size_max);
2061
2062                 info->arr[i].frag_size = frag_size;
2063                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2064
2065                 buf_size += frag_size;
2066                 i++;
2067         }
2068         info->num_frags = i;
2069         /* number of different wqes sharing a page */
2070         info->wqe_bulk = 1 + (info->num_frags % 2);
2071
2072 out:
2073         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2074         info->log_num_frags = order_base_2(info->num_frags);
2075 }
2076
2077 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2078 {
2079         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2080
2081         switch (wq_type) {
2082         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2083                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2084                 break;
2085         default: /* MLX5_WQ_TYPE_CYCLIC */
2086                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2087         }
2088
2089         return order_base_2(sz);
2090 }
2091
2092 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2093 {
2094         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2095
2096         return MLX5_GET(wq, wq, log_wq_sz);
2097 }
2098
2099 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2100                           struct mlx5e_params *params,
2101                           struct mlx5e_xsk_param *xsk,
2102                           struct mlx5e_rq_param *param)
2103 {
2104         struct mlx5_core_dev *mdev = priv->mdev;
2105         void *rqc = param->rqc;
2106         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2107         int ndsegs = 1;
2108
2109         switch (params->rq_wq_type) {
2110         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2111                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2112                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2113                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2114                 MLX5_SET(wq, wq, log_wqe_stride_size,
2115                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2116                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2117                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2118                 break;
2119         default: /* MLX5_WQ_TYPE_CYCLIC */
2120                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2121                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2122                 ndsegs = param->frags_info.num_frags;
2123         }
2124
2125         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2126         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2127         MLX5_SET(wq, wq, log_wq_stride,
2128                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2129         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2130         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2131         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2132         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2133
2134         param->wq.buf_numa_node = dev_to_node(mdev->device);
2135 }
2136
2137 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2138                                       struct mlx5e_rq_param *param)
2139 {
2140         struct mlx5_core_dev *mdev = priv->mdev;
2141         void *rqc = param->rqc;
2142         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2143
2144         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2145         MLX5_SET(wq, wq, log_wq_stride,
2146                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2147         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2148
2149         param->wq.buf_numa_node = dev_to_node(mdev->device);
2150 }
2151
2152 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2153                                  struct mlx5e_sq_param *param)
2154 {
2155         void *sqc = param->sqc;
2156         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2157
2158         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2159         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2160
2161         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2162 }
2163
2164 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2165                                  struct mlx5e_params *params,
2166                                  struct mlx5e_sq_param *param)
2167 {
2168         void *sqc = param->sqc;
2169         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2170         bool allow_swp;
2171
2172         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2173                     !!MLX5_IPSEC_DEV(priv->mdev);
2174         mlx5e_build_sq_param_common(priv, param);
2175         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2176         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2177 }
2178
2179 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2180                                         struct mlx5e_cq_param *param)
2181 {
2182         void *cqc = param->cqc;
2183
2184         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2185         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2186                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2187 }
2188
2189 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2190                              struct mlx5e_params *params,
2191                              struct mlx5e_xsk_param *xsk,
2192                              struct mlx5e_cq_param *param)
2193 {
2194         struct mlx5_core_dev *mdev = priv->mdev;
2195         void *cqc = param->cqc;
2196         u8 log_cq_size;
2197
2198         switch (params->rq_wq_type) {
2199         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2200                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2201                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2202                 break;
2203         default: /* MLX5_WQ_TYPE_CYCLIC */
2204                 log_cq_size = params->log_rq_mtu_frames;
2205         }
2206
2207         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2208         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2209                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2210                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2211         }
2212
2213         mlx5e_build_common_cq_param(priv, param);
2214         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2215 }
2216
2217 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2218                              struct mlx5e_params *params,
2219                              struct mlx5e_cq_param *param)
2220 {
2221         void *cqc = param->cqc;
2222
2223         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2224
2225         mlx5e_build_common_cq_param(priv, param);
2226         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2227 }
2228
2229 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2230                               u8 log_wq_size,
2231                               struct mlx5e_cq_param *param)
2232 {
2233         void *cqc = param->cqc;
2234
2235         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2236
2237         mlx5e_build_common_cq_param(priv, param);
2238
2239         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2240 }
2241
2242 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2243                              u8 log_wq_size,
2244                              struct mlx5e_sq_param *param)
2245 {
2246         void *sqc = param->sqc;
2247         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2248
2249         mlx5e_build_sq_param_common(priv, param);
2250
2251         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2252         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2253 }
2254
2255 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2256                              struct mlx5e_params *params,
2257                              struct mlx5e_sq_param *param)
2258 {
2259         void *sqc = param->sqc;
2260         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2261
2262         mlx5e_build_sq_param_common(priv, param);
2263         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2264         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2265 }
2266
2267 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2268                                       struct mlx5e_rq_param *rqp)
2269 {
2270         switch (params->rq_wq_type) {
2271         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2272                 return order_base_2(MLX5E_UMR_WQEBBS) +
2273                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2274         default: /* MLX5_WQ_TYPE_CYCLIC */
2275                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2276         }
2277 }
2278
2279 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2280                                       struct mlx5e_params *params,
2281                                       struct mlx5e_channel_param *cparam)
2282 {
2283         u8 icosq_log_wq_sz;
2284
2285         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2286
2287         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2288
2289         mlx5e_build_sq_param(priv, params, &cparam->sq);
2290         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2291         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2292         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2293         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2294         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2295 }
2296
2297 int mlx5e_open_channels(struct mlx5e_priv *priv,
2298                         struct mlx5e_channels *chs)
2299 {
2300         struct mlx5e_channel_param *cparam;
2301         int err = -ENOMEM;
2302         int i;
2303
2304         chs->num = chs->params.num_channels;
2305
2306         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2307         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2308         if (!chs->c || !cparam)
2309                 goto err_free;
2310
2311         mlx5e_build_channel_param(priv, &chs->params, cparam);
2312         for (i = 0; i < chs->num; i++) {
2313                 struct xdp_umem *umem = NULL;
2314
2315                 if (chs->params.xdp_prog)
2316                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2317
2318                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2319                 if (err)
2320                         goto err_close_channels;
2321         }
2322
2323         if (!IS_ERR_OR_NULL(priv->tx_reporter))
2324                 devlink_health_reporter_state_update(priv->tx_reporter,
2325                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2326
2327         kvfree(cparam);
2328         return 0;
2329
2330 err_close_channels:
2331         for (i--; i >= 0; i--)
2332                 mlx5e_close_channel(chs->c[i]);
2333
2334 err_free:
2335         kfree(chs->c);
2336         kvfree(cparam);
2337         chs->num = 0;
2338         return err;
2339 }
2340
2341 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2342 {
2343         int i;
2344
2345         for (i = 0; i < chs->num; i++)
2346                 mlx5e_activate_channel(chs->c[i]);
2347 }
2348
2349 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2350
2351 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2352 {
2353         int err = 0;
2354         int i;
2355
2356         for (i = 0; i < chs->num; i++) {
2357                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2358
2359                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2360
2361                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2362                  * doesn't provide any Fill Ring entries at the setup stage.
2363                  */
2364         }
2365
2366         return err ? -ETIMEDOUT : 0;
2367 }
2368
2369 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2370 {
2371         int i;
2372
2373         for (i = 0; i < chs->num; i++)
2374                 mlx5e_deactivate_channel(chs->c[i]);
2375 }
2376
2377 void mlx5e_close_channels(struct mlx5e_channels *chs)
2378 {
2379         int i;
2380
2381         for (i = 0; i < chs->num; i++)
2382                 mlx5e_close_channel(chs->c[i]);
2383
2384         kfree(chs->c);
2385         chs->num = 0;
2386 }
2387
2388 static int
2389 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2390 {
2391         struct mlx5_core_dev *mdev = priv->mdev;
2392         void *rqtc;
2393         int inlen;
2394         int err;
2395         u32 *in;
2396         int i;
2397
2398         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2399         in = kvzalloc(inlen, GFP_KERNEL);
2400         if (!in)
2401                 return -ENOMEM;
2402
2403         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2404
2405         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2406         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2407
2408         for (i = 0; i < sz; i++)
2409                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2410
2411         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2412         if (!err)
2413                 rqt->enabled = true;
2414
2415         kvfree(in);
2416         return err;
2417 }
2418
2419 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2420 {
2421         rqt->enabled = false;
2422         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2423 }
2424
2425 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2426 {
2427         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2428         int err;
2429
2430         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2431         if (err)
2432                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2433         return err;
2434 }
2435
2436 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2437 {
2438         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2439         int err;
2440         int ix;
2441
2442         for (ix = 0; ix < max_nch; ix++) {
2443                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2444                 if (unlikely(err))
2445                         goto err_destroy_rqts;
2446         }
2447
2448         return 0;
2449
2450 err_destroy_rqts:
2451         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2452         for (ix--; ix >= 0; ix--)
2453                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2454
2455         return err;
2456 }
2457
2458 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2459 {
2460         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2461         int i;
2462
2463         for (i = 0; i < max_nch; i++)
2464                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2465 }
2466
2467 static int mlx5e_rx_hash_fn(int hfunc)
2468 {
2469         return (hfunc == ETH_RSS_HASH_TOP) ?
2470                MLX5_RX_HASH_FN_TOEPLITZ :
2471                MLX5_RX_HASH_FN_INVERTED_XOR8;
2472 }
2473
2474 int mlx5e_bits_invert(unsigned long a, int size)
2475 {
2476         int inv = 0;
2477         int i;
2478
2479         for (i = 0; i < size; i++)
2480                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2481
2482         return inv;
2483 }
2484
2485 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2486                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2487 {
2488         int i;
2489
2490         for (i = 0; i < sz; i++) {
2491                 u32 rqn;
2492
2493                 if (rrp.is_rss) {
2494                         int ix = i;
2495
2496                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2497                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2498
2499                         ix = priv->rss_params.indirection_rqt[ix];
2500                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2501                 } else {
2502                         rqn = rrp.rqn;
2503                 }
2504                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2505         }
2506 }
2507
2508 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2509                        struct mlx5e_redirect_rqt_param rrp)
2510 {
2511         struct mlx5_core_dev *mdev = priv->mdev;
2512         void *rqtc;
2513         int inlen;
2514         u32 *in;
2515         int err;
2516
2517         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2518         in = kvzalloc(inlen, GFP_KERNEL);
2519         if (!in)
2520                 return -ENOMEM;
2521
2522         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2523
2524         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2525         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2526         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2527         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2528
2529         kvfree(in);
2530         return err;
2531 }
2532
2533 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2534                                 struct mlx5e_redirect_rqt_param rrp)
2535 {
2536         if (!rrp.is_rss)
2537                 return rrp.rqn;
2538
2539         if (ix >= rrp.rss.channels->num)
2540                 return priv->drop_rq.rqn;
2541
2542         return rrp.rss.channels->c[ix]->rq.rqn;
2543 }
2544
2545 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2546                                 struct mlx5e_redirect_rqt_param rrp)
2547 {
2548         u32 rqtn;
2549         int ix;
2550
2551         if (priv->indir_rqt.enabled) {
2552                 /* RSS RQ table */
2553                 rqtn = priv->indir_rqt.rqtn;
2554                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2555         }
2556
2557         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2558                 struct mlx5e_redirect_rqt_param direct_rrp = {
2559                         .is_rss = false,
2560                         {
2561                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2562                         },
2563                 };
2564
2565                 /* Direct RQ Tables */
2566                 if (!priv->direct_tir[ix].rqt.enabled)
2567                         continue;
2568
2569                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2570                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2571         }
2572 }
2573
2574 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2575                                             struct mlx5e_channels *chs)
2576 {
2577         struct mlx5e_redirect_rqt_param rrp = {
2578                 .is_rss        = true,
2579                 {
2580                         .rss = {
2581                                 .channels  = chs,
2582                                 .hfunc     = priv->rss_params.hfunc,
2583                         }
2584                 },
2585         };
2586
2587         mlx5e_redirect_rqts(priv, rrp);
2588 }
2589
2590 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2591 {
2592         struct mlx5e_redirect_rqt_param drop_rrp = {
2593                 .is_rss = false,
2594                 {
2595                         .rqn = priv->drop_rq.rqn,
2596                 },
2597         };
2598
2599         mlx5e_redirect_rqts(priv, drop_rrp);
2600 }
2601
2602 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2603         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2604                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2605                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2606         },
2607         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2608                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2609                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2610         },
2611         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2612                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2613                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2614         },
2615         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2616                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2617                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2618         },
2619         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2620                                      .l4_prot_type = 0,
2621                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2622         },
2623         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2624                                      .l4_prot_type = 0,
2625                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2626         },
2627         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2628                                       .l4_prot_type = 0,
2629                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2630         },
2631         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2632                                       .l4_prot_type = 0,
2633                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2634         },
2635         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2636                             .l4_prot_type = 0,
2637                             .rx_hash_fields = MLX5_HASH_IP,
2638         },
2639         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2640                             .l4_prot_type = 0,
2641                             .rx_hash_fields = MLX5_HASH_IP,
2642         },
2643 };
2644
2645 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2646 {
2647         return tirc_default_config[tt];
2648 }
2649
2650 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2651 {
2652         if (!params->lro_en)
2653                 return;
2654
2655 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2656
2657         MLX5_SET(tirc, tirc, lro_enable_mask,
2658                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2659                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2660         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2661                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2662         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2663 }
2664
2665 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2666                                     const struct mlx5e_tirc_config *ttconfig,
2667                                     void *tirc, bool inner)
2668 {
2669         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2670                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2671
2672         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2673         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2674                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2675                                              rx_hash_toeplitz_key);
2676                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2677                                                rx_hash_toeplitz_key);
2678
2679                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2680                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2681         }
2682         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2683                  ttconfig->l3_prot_type);
2684         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2685                  ttconfig->l4_prot_type);
2686         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2687                  ttconfig->rx_hash_fields);
2688 }
2689
2690 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2691                                         enum mlx5e_traffic_types tt,
2692                                         u32 rx_hash_fields)
2693 {
2694         *ttconfig                = tirc_default_config[tt];
2695         ttconfig->rx_hash_fields = rx_hash_fields;
2696 }
2697
2698 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2699 {
2700         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2701         struct mlx5e_rss_params *rss = &priv->rss_params;
2702         struct mlx5_core_dev *mdev = priv->mdev;
2703         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2704         struct mlx5e_tirc_config ttconfig;
2705         int tt;
2706
2707         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2708
2709         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2710                 memset(tirc, 0, ctxlen);
2711                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2712                                             rss->rx_hash_fields[tt]);
2713                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2714                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2715         }
2716
2717         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2718                 return;
2719
2720         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2721                 memset(tirc, 0, ctxlen);
2722                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2723                                             rss->rx_hash_fields[tt]);
2724                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2725                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2726                                      inlen);
2727         }
2728 }
2729
2730 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2731 {
2732         struct mlx5_core_dev *mdev = priv->mdev;
2733
2734         void *in;
2735         void *tirc;
2736         int inlen;
2737         int err;
2738         int tt;
2739         int ix;
2740
2741         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2742         in = kvzalloc(inlen, GFP_KERNEL);
2743         if (!in)
2744                 return -ENOMEM;
2745
2746         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2747         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2748
2749         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2750
2751         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2752                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2753                                            inlen);
2754                 if (err)
2755                         goto free_in;
2756         }
2757
2758         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2759                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2760                                            in, inlen);
2761                 if (err)
2762                         goto free_in;
2763         }
2764
2765 free_in:
2766         kvfree(in);
2767
2768         return err;
2769 }
2770
2771 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2772                          struct mlx5e_params *params, u16 mtu)
2773 {
2774         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2775         int err;
2776
2777         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2778         if (err)
2779                 return err;
2780
2781         /* Update vport context MTU */
2782         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2783         return 0;
2784 }
2785
2786 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2787                             struct mlx5e_params *params, u16 *mtu)
2788 {
2789         u16 hw_mtu = 0;
2790         int err;
2791
2792         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2793         if (err || !hw_mtu) /* fallback to port oper mtu */
2794                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2795
2796         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2797 }
2798
2799 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2800 {
2801         struct mlx5e_params *params = &priv->channels.params;
2802         struct net_device *netdev = priv->netdev;
2803         struct mlx5_core_dev *mdev = priv->mdev;
2804         u16 mtu;
2805         int err;
2806
2807         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2808         if (err)
2809                 return err;
2810
2811         mlx5e_query_mtu(mdev, params, &mtu);
2812         if (mtu != params->sw_mtu)
2813                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2814                             __func__, mtu, params->sw_mtu);
2815
2816         params->sw_mtu = mtu;
2817         return 0;
2818 }
2819
2820 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2821 {
2822         struct mlx5e_params *params = &priv->channels.params;
2823         struct net_device *netdev   = priv->netdev;
2824         struct mlx5_core_dev *mdev  = priv->mdev;
2825         u16 max_mtu;
2826
2827         /* MTU range: 68 - hw-specific max */
2828         netdev->min_mtu = ETH_MIN_MTU;
2829
2830         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2831         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2832                                 ETH_MAX_MTU);
2833 }
2834
2835 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2836 {
2837         struct mlx5e_priv *priv = netdev_priv(netdev);
2838         int nch = priv->channels.params.num_channels;
2839         int ntc = priv->channels.params.num_tc;
2840         int tc;
2841
2842         netdev_reset_tc(netdev);
2843
2844         if (ntc == 1)
2845                 return;
2846
2847         netdev_set_num_tc(netdev, ntc);
2848
2849         /* Map netdev TCs to offset 0
2850          * We have our own UP to TXQ mapping for QoS
2851          */
2852         for (tc = 0; tc < ntc; tc++)
2853                 netdev_set_tc_queue(netdev, tc, nch, 0);
2854 }
2855
2856 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2857 {
2858         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2859         int i, tc;
2860
2861         for (i = 0; i < max_nch; i++)
2862                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2863                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2864 }
2865
2866 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2867 {
2868         struct mlx5e_channel *c;
2869         struct mlx5e_txqsq *sq;
2870         int i, tc;
2871
2872         for (i = 0; i < priv->channels.num; i++) {
2873                 c = priv->channels.c[i];
2874                 for (tc = 0; tc < c->num_tc; tc++) {
2875                         sq = &c->sq[tc];
2876                         priv->txq2sq[sq->txq_ix] = sq;
2877                 }
2878         }
2879 }
2880
2881 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2882 {
2883         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2884         int num_rxqs = priv->channels.num * MLX5E_NUM_RQ_GROUPS;
2885         struct net_device *netdev = priv->netdev;
2886
2887         mlx5e_netdev_set_tcs(netdev);
2888         netif_set_real_num_tx_queues(netdev, num_txqs);
2889         netif_set_real_num_rx_queues(netdev, num_rxqs);
2890
2891         mlx5e_build_tx2sq_maps(priv);
2892         mlx5e_activate_channels(&priv->channels);
2893         mlx5e_xdp_tx_enable(priv);
2894         netif_tx_start_all_queues(priv->netdev);
2895
2896         if (mlx5e_is_vport_rep(priv))
2897                 mlx5e_add_sqs_fwd_rules(priv);
2898
2899         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2900         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2901
2902         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2903 }
2904
2905 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2906 {
2907         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2908
2909         mlx5e_redirect_rqts_to_drop(priv);
2910
2911         if (mlx5e_is_vport_rep(priv))
2912                 mlx5e_remove_sqs_fwd_rules(priv);
2913
2914         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2915          * polling for inactive tx queues.
2916          */
2917         netif_tx_stop_all_queues(priv->netdev);
2918         netif_tx_disable(priv->netdev);
2919         mlx5e_xdp_tx_disable(priv);
2920         mlx5e_deactivate_channels(&priv->channels);
2921 }
2922
2923 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2924                                        struct mlx5e_channels *new_chs,
2925                                        mlx5e_fp_hw_modify hw_modify)
2926 {
2927         struct net_device *netdev = priv->netdev;
2928         int new_num_txqs;
2929         int carrier_ok;
2930
2931         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2932
2933         carrier_ok = netif_carrier_ok(netdev);
2934         netif_carrier_off(netdev);
2935
2936         if (new_num_txqs < netdev->real_num_tx_queues)
2937                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2938
2939         mlx5e_deactivate_priv_channels(priv);
2940         mlx5e_close_channels(&priv->channels);
2941
2942         priv->channels = *new_chs;
2943
2944         /* New channels are ready to roll, modify HW settings if needed */
2945         if (hw_modify)
2946                 hw_modify(priv);
2947
2948         priv->profile->update_rx(priv);
2949         mlx5e_activate_priv_channels(priv);
2950
2951         /* return carrier back if needed */
2952         if (carrier_ok)
2953                 netif_carrier_on(netdev);
2954 }
2955
2956 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2957                                struct mlx5e_channels *new_chs,
2958                                mlx5e_fp_hw_modify hw_modify)
2959 {
2960         int err;
2961
2962         err = mlx5e_open_channels(priv, new_chs);
2963         if (err)
2964                 return err;
2965
2966         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2967         return 0;
2968 }
2969
2970 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2971 {
2972         struct mlx5e_channels new_channels = {};
2973
2974         new_channels.params = priv->channels.params;
2975         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2976 }
2977
2978 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2979 {
2980         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2981         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2982 }
2983
2984 int mlx5e_open_locked(struct net_device *netdev)
2985 {
2986         struct mlx5e_priv *priv = netdev_priv(netdev);
2987         bool is_xdp = priv->channels.params.xdp_prog;
2988         int err;
2989
2990         set_bit(MLX5E_STATE_OPENED, &priv->state);
2991         if (is_xdp)
2992                 mlx5e_xdp_set_open(priv);
2993
2994         err = mlx5e_open_channels(priv, &priv->channels);
2995         if (err)
2996                 goto err_clear_state_opened_flag;
2997
2998         priv->profile->update_rx(priv);
2999         mlx5e_activate_priv_channels(priv);
3000         if (priv->profile->update_carrier)
3001                 priv->profile->update_carrier(priv);
3002
3003         mlx5e_queue_update_stats(priv);
3004         return 0;
3005
3006 err_clear_state_opened_flag:
3007         if (is_xdp)
3008                 mlx5e_xdp_set_closed(priv);
3009         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3010         return err;
3011 }
3012
3013 int mlx5e_open(struct net_device *netdev)
3014 {
3015         struct mlx5e_priv *priv = netdev_priv(netdev);
3016         int err;
3017
3018         mutex_lock(&priv->state_lock);
3019         err = mlx5e_open_locked(netdev);
3020         if (!err)
3021                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3022         mutex_unlock(&priv->state_lock);
3023
3024         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3025                 udp_tunnel_get_rx_info(netdev);
3026
3027         return err;
3028 }
3029
3030 int mlx5e_close_locked(struct net_device *netdev)
3031 {
3032         struct mlx5e_priv *priv = netdev_priv(netdev);
3033
3034         /* May already be CLOSED in case a previous configuration operation
3035          * (e.g RX/TX queue size change) that involves close&open failed.
3036          */
3037         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3038                 return 0;
3039
3040         if (priv->channels.params.xdp_prog)
3041                 mlx5e_xdp_set_closed(priv);
3042         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3043
3044         netif_carrier_off(priv->netdev);
3045         mlx5e_deactivate_priv_channels(priv);
3046         mlx5e_close_channels(&priv->channels);
3047
3048         return 0;
3049 }
3050
3051 int mlx5e_close(struct net_device *netdev)
3052 {
3053         struct mlx5e_priv *priv = netdev_priv(netdev);
3054         int err;
3055
3056         if (!netif_device_present(netdev))
3057                 return -ENODEV;
3058
3059         mutex_lock(&priv->state_lock);
3060         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3061         err = mlx5e_close_locked(netdev);
3062         mutex_unlock(&priv->state_lock);
3063
3064         return err;
3065 }
3066
3067 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3068                                struct mlx5e_rq *rq,
3069                                struct mlx5e_rq_param *param)
3070 {
3071         void *rqc = param->rqc;
3072         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3073         int err;
3074
3075         param->wq.db_numa_node = param->wq.buf_numa_node;
3076
3077         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3078                                  &rq->wq_ctrl);
3079         if (err)
3080                 return err;
3081
3082         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3083         xdp_rxq_info_unused(&rq->xdp_rxq);
3084
3085         rq->mdev = mdev;
3086
3087         return 0;
3088 }
3089
3090 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3091                                struct mlx5e_cq *cq,
3092                                struct mlx5e_cq_param *param)
3093 {
3094         param->wq.buf_numa_node = dev_to_node(mdev->device);
3095         param->wq.db_numa_node  = dev_to_node(mdev->device);
3096
3097         return mlx5e_alloc_cq_common(mdev, param, cq);
3098 }
3099
3100 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3101                        struct mlx5e_rq *drop_rq)
3102 {
3103         struct mlx5_core_dev *mdev = priv->mdev;
3104         struct mlx5e_cq_param cq_param = {};
3105         struct mlx5e_rq_param rq_param = {};
3106         struct mlx5e_cq *cq = &drop_rq->cq;
3107         int err;
3108
3109         mlx5e_build_drop_rq_param(priv, &rq_param);
3110
3111         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3112         if (err)
3113                 return err;
3114
3115         err = mlx5e_create_cq(cq, &cq_param);
3116         if (err)
3117                 goto err_free_cq;
3118
3119         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3120         if (err)
3121                 goto err_destroy_cq;
3122
3123         err = mlx5e_create_rq(drop_rq, &rq_param);
3124         if (err)
3125                 goto err_free_rq;
3126
3127         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3128         if (err)
3129                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3130
3131         return 0;
3132
3133 err_free_rq:
3134         mlx5e_free_rq(drop_rq);
3135
3136 err_destroy_cq:
3137         mlx5e_destroy_cq(cq);
3138
3139 err_free_cq:
3140         mlx5e_free_cq(cq);
3141
3142         return err;
3143 }
3144
3145 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3146 {
3147         mlx5e_destroy_rq(drop_rq);
3148         mlx5e_free_rq(drop_rq);
3149         mlx5e_destroy_cq(&drop_rq->cq);
3150         mlx5e_free_cq(&drop_rq->cq);
3151 }
3152
3153 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3154 {
3155         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3156
3157         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3158
3159         if (MLX5_GET(tisc, tisc, tls_en))
3160                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3161
3162         if (mlx5_lag_is_lacp_owner(mdev))
3163                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3164
3165         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3166 }
3167
3168 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3169 {
3170         mlx5_core_destroy_tis(mdev, tisn);
3171 }
3172
3173 int mlx5e_create_tises(struct mlx5e_priv *priv)
3174 {
3175         int err;
3176         int tc;
3177
3178         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3179                 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3180                 void *tisc;
3181
3182                 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3183
3184                 MLX5_SET(tisc, tisc, prio, tc << 1);
3185
3186                 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[tc]);
3187                 if (err)
3188                         goto err_close_tises;
3189         }
3190
3191         return 0;
3192
3193 err_close_tises:
3194         for (tc--; tc >= 0; tc--)
3195                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3196
3197         return err;
3198 }
3199
3200 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3201 {
3202         int tc;
3203
3204         mlx5e_tx_reporter_destroy(priv);
3205         for (tc = 0; tc < priv->profile->max_tc; tc++)
3206                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3207 }
3208
3209 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3210                                              u32 rqtn, u32 *tirc)
3211 {
3212         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3213         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3214         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3215         MLX5_SET(tirc, tirc, tunneled_offload_en,
3216                  priv->channels.params.tunneled_offload_en);
3217
3218         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3219 }
3220
3221 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3222                                       enum mlx5e_traffic_types tt,
3223                                       u32 *tirc)
3224 {
3225         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3226         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3227                                        &tirc_default_config[tt], tirc, false);
3228 }
3229
3230 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3231 {
3232         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3233         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3234 }
3235
3236 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3237                                             enum mlx5e_traffic_types tt,
3238                                             u32 *tirc)
3239 {
3240         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3241         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3242                                        &tirc_default_config[tt], tirc, true);
3243 }
3244
3245 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3246 {
3247         struct mlx5e_tir *tir;
3248         void *tirc;
3249         int inlen;
3250         int i = 0;
3251         int err;
3252         u32 *in;
3253         int tt;
3254
3255         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3256         in = kvzalloc(inlen, GFP_KERNEL);
3257         if (!in)
3258                 return -ENOMEM;
3259
3260         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3261                 memset(in, 0, inlen);
3262                 tir = &priv->indir_tir[tt];
3263                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3264                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3265                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3266                 if (err) {
3267                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3268                         goto err_destroy_inner_tirs;
3269                 }
3270         }
3271
3272         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3273                 goto out;
3274
3275         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3276                 memset(in, 0, inlen);
3277                 tir = &priv->inner_indir_tir[i];
3278                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3279                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3280                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3281                 if (err) {
3282                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3283                         goto err_destroy_inner_tirs;
3284                 }
3285         }
3286
3287 out:
3288         kvfree(in);
3289
3290         return 0;
3291
3292 err_destroy_inner_tirs:
3293         for (i--; i >= 0; i--)
3294                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3295
3296         for (tt--; tt >= 0; tt--)
3297                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3298
3299         kvfree(in);
3300
3301         return err;
3302 }
3303
3304 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3305 {
3306         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
3307         struct mlx5e_tir *tir;
3308         void *tirc;
3309         int inlen;
3310         int err = 0;
3311         u32 *in;
3312         int ix;
3313
3314         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3315         in = kvzalloc(inlen, GFP_KERNEL);
3316         if (!in)
3317                 return -ENOMEM;
3318
3319         for (ix = 0; ix < max_nch; ix++) {
3320                 memset(in, 0, inlen);
3321                 tir = &tirs[ix];
3322                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3323                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3324                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3325                 if (unlikely(err))
3326                         goto err_destroy_ch_tirs;
3327         }
3328
3329         goto out;
3330
3331 err_destroy_ch_tirs:
3332         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3333         for (ix--; ix >= 0; ix--)
3334                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3335
3336 out:
3337         kvfree(in);
3338
3339         return err;
3340 }
3341
3342 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3343 {
3344         int i;
3345
3346         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3347                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3348
3349         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3350                 return;
3351
3352         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3353                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3354 }
3355
3356 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3357 {
3358         const int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
3359         int i;
3360
3361         for (i = 0; i < max_nch; i++)
3362                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3363 }
3364
3365 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3366 {
3367         int err = 0;
3368         int i;
3369
3370         for (i = 0; i < chs->num; i++) {
3371                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3372                 if (err)
3373                         return err;
3374         }
3375
3376         return 0;
3377 }
3378
3379 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3380 {
3381         int err = 0;
3382         int i;
3383
3384         for (i = 0; i < chs->num; i++) {
3385                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3386                 if (err)
3387                         return err;
3388         }
3389
3390         return 0;
3391 }
3392
3393 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3394                                  struct tc_mqprio_qopt *mqprio)
3395 {
3396         struct mlx5e_priv *priv = netdev_priv(netdev);
3397         struct mlx5e_channels new_channels = {};
3398         u8 tc = mqprio->num_tc;
3399         int err = 0;
3400
3401         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3402
3403         if (tc && tc != MLX5E_MAX_NUM_TC)
3404                 return -EINVAL;
3405
3406         mutex_lock(&priv->state_lock);
3407
3408         new_channels.params = priv->channels.params;
3409         new_channels.params.num_tc = tc ? tc : 1;
3410
3411         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3412                 priv->channels.params = new_channels.params;
3413                 goto out;
3414         }
3415
3416         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3417         if (err)
3418                 goto out;
3419
3420         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3421                                     new_channels.params.num_tc);
3422 out:
3423         mutex_unlock(&priv->state_lock);
3424         return err;
3425 }
3426
3427 #ifdef CONFIG_MLX5_ESWITCH
3428 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3429                                      struct tc_cls_flower_offload *cls_flower,
3430                                      int flags)
3431 {
3432         switch (cls_flower->command) {
3433         case TC_CLSFLOWER_REPLACE:
3434                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3435                                               flags);
3436         case TC_CLSFLOWER_DESTROY:
3437                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3438                                            flags);
3439         case TC_CLSFLOWER_STATS:
3440                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3441                                           flags);
3442         default:
3443                 return -EOPNOTSUPP;
3444         }
3445 }
3446
3447 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3448                                    void *cb_priv)
3449 {
3450         struct mlx5e_priv *priv = cb_priv;
3451
3452         switch (type) {
3453         case TC_SETUP_CLSFLOWER:
3454                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3455                                                  MLX5E_TC_NIC_OFFLOAD);
3456         default:
3457                 return -EOPNOTSUPP;
3458         }
3459 }
3460
3461 static int mlx5e_setup_tc_block(struct net_device *dev,
3462                                 struct tc_block_offload *f)
3463 {
3464         struct mlx5e_priv *priv = netdev_priv(dev);
3465
3466         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3467                 return -EOPNOTSUPP;
3468
3469         switch (f->command) {
3470         case TC_BLOCK_BIND:
3471                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3472                                              priv, priv, f->extack);
3473         case TC_BLOCK_UNBIND:
3474                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3475                                         priv);
3476                 return 0;
3477         default:
3478                 return -EOPNOTSUPP;
3479         }
3480 }
3481 #endif
3482
3483 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3484                           void *type_data)
3485 {
3486         switch (type) {
3487 #ifdef CONFIG_MLX5_ESWITCH
3488         case TC_SETUP_BLOCK:
3489                 return mlx5e_setup_tc_block(dev, type_data);
3490 #endif
3491         case TC_SETUP_QDISC_MQPRIO:
3492                 return mlx5e_setup_tc_mqprio(dev, type_data);
3493         default:
3494                 return -EOPNOTSUPP;
3495         }
3496 }
3497
3498 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3499 {
3500         int i;
3501
3502         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
3503                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3504                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3505                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3506                 int j;
3507
3508                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3509                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3510
3511                 for (j = 0; j < priv->max_opened_tc; j++) {
3512                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3513
3514                         s->tx_packets    += sq_stats->packets;
3515                         s->tx_bytes      += sq_stats->bytes;
3516                         s->tx_dropped    += sq_stats->dropped;
3517                 }
3518         }
3519 }
3520
3521 void
3522 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3523 {
3524         struct mlx5e_priv *priv = netdev_priv(dev);
3525         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3526         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3527
3528         if (!mlx5e_monitor_counter_supported(priv)) {
3529                 /* update HW stats in background for next time */
3530                 mlx5e_queue_update_stats(priv);
3531         }
3532
3533         if (mlx5e_is_uplink_rep(priv)) {
3534                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3535                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3536                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3537                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3538         } else {
3539                 mlx5e_fold_sw_stats64(priv, stats);
3540         }
3541
3542         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3543
3544         stats->rx_length_errors =
3545                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3546                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3547                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3548         stats->rx_crc_errors =
3549                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3550         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3551         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3552         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3553                            stats->rx_frame_errors;
3554         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3555
3556         /* vport multicast also counts packets that are dropped due to steering
3557          * or rx out of buffer
3558          */
3559         stats->multicast =
3560                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3561 }
3562
3563 static void mlx5e_set_rx_mode(struct net_device *dev)
3564 {
3565         struct mlx5e_priv *priv = netdev_priv(dev);
3566
3567         queue_work(priv->wq, &priv->set_rx_mode_work);
3568 }
3569
3570 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3571 {
3572         struct mlx5e_priv *priv = netdev_priv(netdev);
3573         struct sockaddr *saddr = addr;
3574
3575         if (!is_valid_ether_addr(saddr->sa_data))
3576                 return -EADDRNOTAVAIL;
3577
3578         netif_addr_lock_bh(netdev);
3579         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3580         netif_addr_unlock_bh(netdev);
3581
3582         queue_work(priv->wq, &priv->set_rx_mode_work);
3583
3584         return 0;
3585 }
3586
3587 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3588         do {                                            \
3589                 if (enable)                             \
3590                         *features |= feature;           \
3591                 else                                    \
3592                         *features &= ~feature;          \
3593         } while (0)
3594
3595 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3596
3597 static int set_feature_lro(struct net_device *netdev, bool enable)
3598 {
3599         struct mlx5e_priv *priv = netdev_priv(netdev);
3600         struct mlx5_core_dev *mdev = priv->mdev;
3601         struct mlx5e_channels new_channels = {};
3602         struct mlx5e_params *old_params;
3603         int err = 0;
3604         bool reset;
3605
3606         mutex_lock(&priv->state_lock);
3607
3608         if (enable && priv->xsk.refcnt) {
3609                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3610                             priv->xsk.refcnt);
3611                 err = -EINVAL;
3612                 goto out;
3613         }
3614
3615         old_params = &priv->channels.params;
3616         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3617                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3618                 err = -EINVAL;
3619                 goto out;
3620         }
3621
3622         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3623
3624         new_channels.params = *old_params;
3625         new_channels.params.lro_en = enable;
3626
3627         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3628                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3629                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3630                         reset = false;
3631         }
3632
3633         if (!reset) {
3634                 *old_params = new_channels.params;
3635                 err = mlx5e_modify_tirs_lro(priv);
3636                 goto out;
3637         }
3638
3639         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3640 out:
3641         mutex_unlock(&priv->state_lock);
3642         return err;
3643 }
3644
3645 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3646 {
3647         struct mlx5e_priv *priv = netdev_priv(netdev);
3648
3649         if (enable)
3650                 mlx5e_enable_cvlan_filter(priv);
3651         else
3652                 mlx5e_disable_cvlan_filter(priv);
3653
3654         return 0;
3655 }
3656
3657 #ifdef CONFIG_MLX5_ESWITCH
3658 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3659 {
3660         struct mlx5e_priv *priv = netdev_priv(netdev);
3661
3662         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3663                 netdev_err(netdev,
3664                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3665                 return -EINVAL;
3666         }
3667
3668         return 0;
3669 }
3670 #endif
3671
3672 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3673 {
3674         struct mlx5e_priv *priv = netdev_priv(netdev);
3675         struct mlx5_core_dev *mdev = priv->mdev;
3676
3677         return mlx5_set_port_fcs(mdev, !enable);
3678 }
3679
3680 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3681 {
3682         struct mlx5e_priv *priv = netdev_priv(netdev);
3683         int err;
3684
3685         mutex_lock(&priv->state_lock);
3686
3687         priv->channels.params.scatter_fcs_en = enable;
3688         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3689         if (err)
3690                 priv->channels.params.scatter_fcs_en = !enable;
3691
3692         mutex_unlock(&priv->state_lock);
3693
3694         return err;
3695 }
3696
3697 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3698 {
3699         struct mlx5e_priv *priv = netdev_priv(netdev);
3700         int err = 0;
3701
3702         mutex_lock(&priv->state_lock);
3703
3704         priv->channels.params.vlan_strip_disable = !enable;
3705         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3706                 goto unlock;
3707
3708         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3709         if (err)
3710                 priv->channels.params.vlan_strip_disable = enable;
3711
3712 unlock:
3713         mutex_unlock(&priv->state_lock);
3714
3715         return err;
3716 }
3717
3718 #ifdef CONFIG_MLX5_EN_ARFS
3719 static int set_feature_arfs(struct net_device *netdev, bool enable)
3720 {
3721         struct mlx5e_priv *priv = netdev_priv(netdev);
3722         int err;
3723
3724         if (enable)
3725                 err = mlx5e_arfs_enable(priv);
3726         else
3727                 err = mlx5e_arfs_disable(priv);
3728
3729         return err;
3730 }
3731 #endif
3732
3733 static int mlx5e_handle_feature(struct net_device *netdev,
3734                                 netdev_features_t *features,
3735                                 netdev_features_t wanted_features,
3736                                 netdev_features_t feature,
3737                                 mlx5e_feature_handler feature_handler)
3738 {
3739         netdev_features_t changes = wanted_features ^ netdev->features;
3740         bool enable = !!(wanted_features & feature);
3741         int err;
3742
3743         if (!(changes & feature))
3744                 return 0;
3745
3746         err = feature_handler(netdev, enable);
3747         if (err) {
3748                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3749                            enable ? "Enable" : "Disable", &feature, err);
3750                 return err;
3751         }
3752
3753         MLX5E_SET_FEATURE(features, feature, enable);
3754         return 0;
3755 }
3756
3757 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3758 {
3759         netdev_features_t oper_features = netdev->features;
3760         int err = 0;
3761
3762 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3763         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3764
3765         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3766         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3767                                     set_feature_cvlan_filter);
3768 #ifdef CONFIG_MLX5_ESWITCH
3769         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3770 #endif
3771         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3772         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3773         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3774 #ifdef CONFIG_MLX5_EN_ARFS
3775         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3776 #endif
3777
3778         if (err) {
3779                 netdev->features = oper_features;
3780                 return -EINVAL;
3781         }
3782
3783         return 0;
3784 }
3785
3786 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3787                                             netdev_features_t features)
3788 {
3789         struct mlx5e_priv *priv = netdev_priv(netdev);
3790         struct mlx5e_params *params;
3791
3792         mutex_lock(&priv->state_lock);
3793         params = &priv->channels.params;
3794         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3795                 /* HW strips the outer C-tag header, this is a problem
3796                  * for S-tag traffic.
3797                  */
3798                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3799                 if (!params->vlan_strip_disable)
3800                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3801         }
3802         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3803                 features &= ~NETIF_F_LRO;
3804                 if (params->lro_en)
3805                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3806         }
3807
3808         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3809                 features &= ~NETIF_F_RXHASH;
3810                 if (netdev->features & NETIF_F_RXHASH)
3811                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3812         }
3813
3814         mutex_unlock(&priv->state_lock);
3815
3816         return features;
3817 }
3818
3819 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3820                                    struct mlx5e_channels *chs,
3821                                    struct mlx5e_params *new_params,
3822                                    struct mlx5_core_dev *mdev)
3823 {
3824         u16 ix;
3825
3826         for (ix = 0; ix < chs->params.num_channels; ix++) {
3827                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3828                 struct mlx5e_xsk_param xsk;
3829
3830                 if (!umem)
3831                         continue;
3832
3833                 mlx5e_build_xsk_param(umem, &xsk);
3834
3835                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3836                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3837                         int max_mtu_frame, max_mtu_page, max_mtu;
3838
3839                         /* Two criteria must be met:
3840                          * 1. HW MTU + all headrooms <= XSK frame size.
3841                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3842                          */
3843                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3844                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3845                         max_mtu = min(max_mtu_frame, max_mtu_page);
3846
3847                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3848                                    new_params->sw_mtu, ix, max_mtu);
3849                         return false;
3850                 }
3851         }
3852
3853         return true;
3854 }
3855
3856 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3857                      change_hw_mtu_cb set_mtu_cb)
3858 {
3859         struct mlx5e_priv *priv = netdev_priv(netdev);
3860         struct mlx5e_channels new_channels = {};
3861         struct mlx5e_params *params;
3862         int err = 0;
3863         bool reset;
3864
3865         mutex_lock(&priv->state_lock);
3866
3867         params = &priv->channels.params;
3868
3869         reset = !params->lro_en;
3870         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3871
3872         new_channels.params = *params;
3873         new_channels.params.sw_mtu = new_mtu;
3874
3875         if (params->xdp_prog &&
3876             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3877                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3878                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3879                 err = -EINVAL;
3880                 goto out;
3881         }
3882
3883         if (priv->xsk.refcnt &&
3884             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3885                                     &new_channels.params, priv->mdev)) {
3886                 err = -EINVAL;
3887                 goto out;
3888         }
3889
3890         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3891                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3892                                                               &new_channels.params,
3893                                                               NULL);
3894                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3895                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3896
3897                 /* If XSK is active, XSK RQs are linear. */
3898                 is_linear |= priv->xsk.refcnt;
3899
3900                 /* Always reset in linear mode - hw_mtu is used in data path. */
3901                 reset = reset && (is_linear || (ppw_old != ppw_new));
3902         }
3903
3904         if (!reset) {
3905                 params->sw_mtu = new_mtu;
3906                 if (set_mtu_cb)
3907                         set_mtu_cb(priv);
3908                 netdev->mtu = params->sw_mtu;
3909                 goto out;
3910         }
3911
3912         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3913         if (err)
3914                 goto out;
3915
3916         netdev->mtu = new_channels.params.sw_mtu;
3917
3918 out:
3919         mutex_unlock(&priv->state_lock);
3920         return err;
3921 }
3922
3923 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3924 {
3925         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3926 }
3927
3928 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3929 {
3930         struct hwtstamp_config config;
3931         int err;
3932
3933         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3934             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3935                 return -EOPNOTSUPP;
3936
3937         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3938                 return -EFAULT;
3939
3940         /* TX HW timestamp */
3941         switch (config.tx_type) {
3942         case HWTSTAMP_TX_OFF:
3943         case HWTSTAMP_TX_ON:
3944                 break;
3945         default:
3946                 return -ERANGE;
3947         }
3948
3949         mutex_lock(&priv->state_lock);
3950         /* RX HW timestamp */
3951         switch (config.rx_filter) {
3952         case HWTSTAMP_FILTER_NONE:
3953                 /* Reset CQE compression to Admin default */
3954                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3955                 break;
3956         case HWTSTAMP_FILTER_ALL:
3957         case HWTSTAMP_FILTER_SOME:
3958         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3959         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3960         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3961         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3962         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3963         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3964         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3965         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3966         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3967         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3968         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3969         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3970         case HWTSTAMP_FILTER_NTP_ALL:
3971                 /* Disable CQE compression */
3972                 netdev_warn(priv->netdev, "Disabling cqe compression");
3973                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3974                 if (err) {
3975                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3976                         mutex_unlock(&priv->state_lock);
3977                         return err;
3978                 }
3979                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3980                 break;
3981         default:
3982                 mutex_unlock(&priv->state_lock);
3983                 return -ERANGE;
3984         }
3985
3986         memcpy(&priv->tstamp, &config, sizeof(config));
3987         mutex_unlock(&priv->state_lock);
3988
3989         /* might need to fix some features */
3990         netdev_update_features(priv->netdev);
3991
3992         return copy_to_user(ifr->ifr_data, &config,
3993                             sizeof(config)) ? -EFAULT : 0;
3994 }
3995
3996 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3997 {
3998         struct hwtstamp_config *cfg = &priv->tstamp;
3999
4000         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4001                 return -EOPNOTSUPP;
4002
4003         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4004 }
4005
4006 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4007 {
4008         struct mlx5e_priv *priv = netdev_priv(dev);
4009
4010         switch (cmd) {
4011         case SIOCSHWTSTAMP:
4012                 return mlx5e_hwstamp_set(priv, ifr);
4013         case SIOCGHWTSTAMP:
4014                 return mlx5e_hwstamp_get(priv, ifr);
4015         default:
4016                 return -EOPNOTSUPP;
4017         }
4018 }
4019
4020 #ifdef CONFIG_MLX5_ESWITCH
4021 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4022 {
4023         struct mlx5e_priv *priv = netdev_priv(dev);
4024         struct mlx5_core_dev *mdev = priv->mdev;
4025
4026         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4027 }
4028
4029 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4030                              __be16 vlan_proto)
4031 {
4032         struct mlx5e_priv *priv = netdev_priv(dev);
4033         struct mlx5_core_dev *mdev = priv->mdev;
4034
4035         if (vlan_proto != htons(ETH_P_8021Q))
4036                 return -EPROTONOSUPPORT;
4037
4038         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4039                                            vlan, qos);
4040 }
4041
4042 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4043 {
4044         struct mlx5e_priv *priv = netdev_priv(dev);
4045         struct mlx5_core_dev *mdev = priv->mdev;
4046
4047         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4048 }
4049
4050 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4051 {
4052         struct mlx5e_priv *priv = netdev_priv(dev);
4053         struct mlx5_core_dev *mdev = priv->mdev;
4054
4055         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4056 }
4057
4058 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4059                       int max_tx_rate)
4060 {
4061         struct mlx5e_priv *priv = netdev_priv(dev);
4062         struct mlx5_core_dev *mdev = priv->mdev;
4063
4064         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4065                                            max_tx_rate, min_tx_rate);
4066 }
4067
4068 static int mlx5_vport_link2ifla(u8 esw_link)
4069 {
4070         switch (esw_link) {
4071         case MLX5_VPORT_ADMIN_STATE_DOWN:
4072                 return IFLA_VF_LINK_STATE_DISABLE;
4073         case MLX5_VPORT_ADMIN_STATE_UP:
4074                 return IFLA_VF_LINK_STATE_ENABLE;
4075         }
4076         return IFLA_VF_LINK_STATE_AUTO;
4077 }
4078
4079 static int mlx5_ifla_link2vport(u8 ifla_link)
4080 {
4081         switch (ifla_link) {
4082         case IFLA_VF_LINK_STATE_DISABLE:
4083                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4084         case IFLA_VF_LINK_STATE_ENABLE:
4085                 return MLX5_VPORT_ADMIN_STATE_UP;
4086         }
4087         return MLX5_VPORT_ADMIN_STATE_AUTO;
4088 }
4089
4090 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4091                                    int link_state)
4092 {
4093         struct mlx5e_priv *priv = netdev_priv(dev);
4094         struct mlx5_core_dev *mdev = priv->mdev;
4095
4096         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4097                                             mlx5_ifla_link2vport(link_state));
4098 }
4099
4100 int mlx5e_get_vf_config(struct net_device *dev,
4101                         int vf, struct ifla_vf_info *ivi)
4102 {
4103         struct mlx5e_priv *priv = netdev_priv(dev);
4104         struct mlx5_core_dev *mdev = priv->mdev;
4105         int err;
4106
4107         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4108         if (err)
4109                 return err;
4110         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4111         return 0;
4112 }
4113
4114 int mlx5e_get_vf_stats(struct net_device *dev,
4115                        int vf, struct ifla_vf_stats *vf_stats)
4116 {
4117         struct mlx5e_priv *priv = netdev_priv(dev);
4118         struct mlx5_core_dev *mdev = priv->mdev;
4119
4120         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4121                                             vf_stats);
4122 }
4123 #endif
4124
4125 struct mlx5e_vxlan_work {
4126         struct work_struct      work;
4127         struct mlx5e_priv       *priv;
4128         u16                     port;
4129 };
4130
4131 static void mlx5e_vxlan_add_work(struct work_struct *work)
4132 {
4133         struct mlx5e_vxlan_work *vxlan_work =
4134                 container_of(work, struct mlx5e_vxlan_work, work);
4135         struct mlx5e_priv *priv = vxlan_work->priv;
4136         u16 port = vxlan_work->port;
4137
4138         mutex_lock(&priv->state_lock);
4139         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4140         mutex_unlock(&priv->state_lock);
4141
4142         kfree(vxlan_work);
4143 }
4144
4145 static void mlx5e_vxlan_del_work(struct work_struct *work)
4146 {
4147         struct mlx5e_vxlan_work *vxlan_work =
4148                 container_of(work, struct mlx5e_vxlan_work, work);
4149         struct mlx5e_priv *priv         = vxlan_work->priv;
4150         u16 port = vxlan_work->port;
4151
4152         mutex_lock(&priv->state_lock);
4153         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4154         mutex_unlock(&priv->state_lock);
4155         kfree(vxlan_work);
4156 }
4157
4158 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4159 {
4160         struct mlx5e_vxlan_work *vxlan_work;
4161
4162         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4163         if (!vxlan_work)
4164                 return;
4165
4166         if (add)
4167                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4168         else
4169                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4170
4171         vxlan_work->priv = priv;
4172         vxlan_work->port = port;
4173         queue_work(priv->wq, &vxlan_work->work);
4174 }
4175
4176 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4177 {
4178         struct mlx5e_priv *priv = netdev_priv(netdev);
4179
4180         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4181                 return;
4182
4183         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4184                 return;
4185
4186         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4187 }
4188
4189 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4190 {
4191         struct mlx5e_priv *priv = netdev_priv(netdev);
4192
4193         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4194                 return;
4195
4196         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4197                 return;
4198
4199         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4200 }
4201
4202 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4203                                                      struct sk_buff *skb,
4204                                                      netdev_features_t features)
4205 {
4206         unsigned int offset = 0;
4207         struct udphdr *udph;
4208         u8 proto;
4209         u16 port;
4210
4211         switch (vlan_get_protocol(skb)) {
4212         case htons(ETH_P_IP):
4213                 proto = ip_hdr(skb)->protocol;
4214                 break;
4215         case htons(ETH_P_IPV6):
4216                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4217                 break;
4218         default:
4219                 goto out;
4220         }
4221
4222         switch (proto) {
4223         case IPPROTO_GRE:
4224                 return features;
4225         case IPPROTO_UDP:
4226                 udph = udp_hdr(skb);
4227                 port = be16_to_cpu(udph->dest);
4228
4229                 /* Verify if UDP port is being offloaded by HW */
4230                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4231                         return features;
4232
4233 #if IS_ENABLED(CONFIG_GENEVE)
4234                 /* Support Geneve offload for default UDP port */
4235                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4236                         return features;
4237 #endif
4238         }
4239
4240 out:
4241         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4242         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4243 }
4244
4245 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4246                                        struct net_device *netdev,
4247                                        netdev_features_t features)
4248 {
4249         struct mlx5e_priv *priv = netdev_priv(netdev);
4250
4251         features = vlan_features_check(skb, features);
4252         features = vxlan_features_check(skb, features);
4253
4254 #ifdef CONFIG_MLX5_EN_IPSEC
4255         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4256                 return features;
4257 #endif
4258
4259         /* Validate if the tunneled packet is being offloaded by HW */
4260         if (skb->encapsulation &&
4261             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4262                 return mlx5e_tunnel_features_check(priv, skb, features);
4263
4264         return features;
4265 }
4266
4267 static void mlx5e_tx_timeout_work(struct work_struct *work)
4268 {
4269         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4270                                                tx_timeout_work);
4271         bool report_failed = false;
4272         int err;
4273         int i;
4274
4275         rtnl_lock();
4276         mutex_lock(&priv->state_lock);
4277
4278         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4279                 goto unlock;
4280
4281         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4282                 struct netdev_queue *dev_queue =
4283                         netdev_get_tx_queue(priv->netdev, i);
4284                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4285
4286                 if (!netif_xmit_stopped(dev_queue))
4287                         continue;
4288
4289                 if (mlx5e_tx_reporter_timeout(sq))
4290                         report_failed = true;
4291         }
4292
4293         if (!report_failed)
4294                 goto unlock;
4295
4296         err = mlx5e_safe_reopen_channels(priv);
4297         if (err)
4298                 netdev_err(priv->netdev,
4299                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4300                            err);
4301
4302 unlock:
4303         mutex_unlock(&priv->state_lock);
4304         rtnl_unlock();
4305 }
4306
4307 static void mlx5e_tx_timeout(struct net_device *dev)
4308 {
4309         struct mlx5e_priv *priv = netdev_priv(dev);
4310
4311         netdev_err(dev, "TX timeout detected\n");
4312         queue_work(priv->wq, &priv->tx_timeout_work);
4313 }
4314
4315 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4316 {
4317         struct net_device *netdev = priv->netdev;
4318         struct mlx5e_channels new_channels = {};
4319
4320         if (priv->channels.params.lro_en) {
4321                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4322                 return -EINVAL;
4323         }
4324
4325         if (MLX5_IPSEC_DEV(priv->mdev)) {
4326                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4327                 return -EINVAL;
4328         }
4329
4330         new_channels.params = priv->channels.params;
4331         new_channels.params.xdp_prog = prog;
4332
4333         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4334          * the XDP program.
4335          */
4336         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4337                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4338                             new_channels.params.sw_mtu,
4339                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4340                 return -EINVAL;
4341         }
4342
4343         return 0;
4344 }
4345
4346 static int mlx5e_xdp_update_state(struct mlx5e_priv *priv)
4347 {
4348         if (priv->channels.params.xdp_prog)
4349                 mlx5e_xdp_set_open(priv);
4350         else
4351                 mlx5e_xdp_set_closed(priv);
4352
4353         return 0;
4354 }
4355
4356 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4357 {
4358         struct mlx5e_priv *priv = netdev_priv(netdev);
4359         struct bpf_prog *old_prog;
4360         bool reset, was_opened;
4361         int err = 0;
4362         int i;
4363
4364         mutex_lock(&priv->state_lock);
4365
4366         if (prog) {
4367                 err = mlx5e_xdp_allowed(priv, prog);
4368                 if (err)
4369                         goto unlock;
4370         }
4371
4372         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4373         /* no need for full reset when exchanging programs */
4374         reset = (!priv->channels.params.xdp_prog || !prog);
4375
4376         if (was_opened && !reset) {
4377                 /* num_channels is invariant here, so we can take the
4378                  * batched reference right upfront.
4379                  */
4380                 prog = bpf_prog_add(prog, priv->channels.num);
4381                 if (IS_ERR(prog)) {
4382                         err = PTR_ERR(prog);
4383                         goto unlock;
4384                 }
4385         }
4386
4387         if (was_opened && reset) {
4388                 struct mlx5e_channels new_channels = {};
4389
4390                 new_channels.params = priv->channels.params;
4391                 new_channels.params.xdp_prog = prog;
4392                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4393                 old_prog = priv->channels.params.xdp_prog;
4394
4395                 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_xdp_update_state);
4396                 if (err)
4397                         goto unlock;
4398         } else {
4399                 /* exchange programs, extra prog reference we got from caller
4400                  * as long as we don't fail from this point onwards.
4401                  */
4402                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4403         }
4404
4405         if (old_prog)
4406                 bpf_prog_put(old_prog);
4407
4408         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4409                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4410
4411         if (!was_opened || reset)
4412                 goto unlock;
4413
4414         /* exchanging programs w/o reset, we update ref counts on behalf
4415          * of the channels RQs here.
4416          */
4417         for (i = 0; i < priv->channels.num; i++) {
4418                 struct mlx5e_channel *c = priv->channels.c[i];
4419                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4420
4421                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4422                 if (xsk_open)
4423                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4424                 napi_synchronize(&c->napi);
4425                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4426
4427                 old_prog = xchg(&c->rq.xdp_prog, prog);
4428                 if (old_prog)
4429                         bpf_prog_put(old_prog);
4430
4431                 if (xsk_open) {
4432                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4433                         if (old_prog)
4434                                 bpf_prog_put(old_prog);
4435                 }
4436
4437                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4438                 if (xsk_open)
4439                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4440                 /* napi_schedule in case we have missed anything */
4441                 napi_schedule(&c->napi);
4442         }
4443
4444 unlock:
4445         mutex_unlock(&priv->state_lock);
4446         return err;
4447 }
4448
4449 static u32 mlx5e_xdp_query(struct net_device *dev)
4450 {
4451         struct mlx5e_priv *priv = netdev_priv(dev);
4452         const struct bpf_prog *xdp_prog;
4453         u32 prog_id = 0;
4454
4455         mutex_lock(&priv->state_lock);
4456         xdp_prog = priv->channels.params.xdp_prog;
4457         if (xdp_prog)
4458                 prog_id = xdp_prog->aux->id;
4459         mutex_unlock(&priv->state_lock);
4460
4461         return prog_id;
4462 }
4463
4464 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4465 {
4466         switch (xdp->command) {
4467         case XDP_SETUP_PROG:
4468                 return mlx5e_xdp_set(dev, xdp->prog);
4469         case XDP_QUERY_PROG:
4470                 xdp->prog_id = mlx5e_xdp_query(dev);
4471                 return 0;
4472         case XDP_SETUP_XSK_UMEM:
4473                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4474                                             xdp->xsk.queue_id);
4475         default:
4476                 return -EINVAL;
4477         }
4478 }
4479
4480 #ifdef CONFIG_MLX5_ESWITCH
4481 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4482                                 struct net_device *dev, u32 filter_mask,
4483                                 int nlflags)
4484 {
4485         struct mlx5e_priv *priv = netdev_priv(dev);
4486         struct mlx5_core_dev *mdev = priv->mdev;
4487         u8 mode, setting;
4488         int err;
4489
4490         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4491         if (err)
4492                 return err;
4493         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4494         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4495                                        mode,
4496                                        0, 0, nlflags, filter_mask, NULL);
4497 }
4498
4499 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4500                                 u16 flags, struct netlink_ext_ack *extack)
4501 {
4502         struct mlx5e_priv *priv = netdev_priv(dev);
4503         struct mlx5_core_dev *mdev = priv->mdev;
4504         struct nlattr *attr, *br_spec;
4505         u16 mode = BRIDGE_MODE_UNDEF;
4506         u8 setting;
4507         int rem;
4508
4509         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4510         if (!br_spec)
4511                 return -EINVAL;
4512
4513         nla_for_each_nested(attr, br_spec, rem) {
4514                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4515                         continue;
4516
4517                 if (nla_len(attr) < sizeof(mode))
4518                         return -EINVAL;
4519
4520                 mode = nla_get_u16(attr);
4521                 if (mode > BRIDGE_MODE_VEPA)
4522                         return -EINVAL;
4523
4524                 break;
4525         }
4526
4527         if (mode == BRIDGE_MODE_UNDEF)
4528                 return -EINVAL;
4529
4530         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4531         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4532 }
4533 #endif
4534
4535 const struct net_device_ops mlx5e_netdev_ops = {
4536         .ndo_open                = mlx5e_open,
4537         .ndo_stop                = mlx5e_close,
4538         .ndo_start_xmit          = mlx5e_xmit,
4539         .ndo_setup_tc            = mlx5e_setup_tc,
4540         .ndo_select_queue        = mlx5e_select_queue,
4541         .ndo_get_stats64         = mlx5e_get_stats,
4542         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4543         .ndo_set_mac_address     = mlx5e_set_mac,
4544         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4545         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4546         .ndo_set_features        = mlx5e_set_features,
4547         .ndo_fix_features        = mlx5e_fix_features,
4548         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4549         .ndo_do_ioctl            = mlx5e_ioctl,
4550         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4551         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4552         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4553         .ndo_features_check      = mlx5e_features_check,
4554         .ndo_tx_timeout          = mlx5e_tx_timeout,
4555         .ndo_bpf                 = mlx5e_xdp,
4556         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4557         .ndo_xsk_async_xmit      = mlx5e_xsk_async_xmit,
4558 #ifdef CONFIG_MLX5_EN_ARFS
4559         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4560 #endif
4561 #ifdef CONFIG_MLX5_ESWITCH
4562         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4563         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4564
4565         /* SRIOV E-Switch NDOs */
4566         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4567         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4568         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4569         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4570         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4571         .ndo_get_vf_config       = mlx5e_get_vf_config,
4572         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4573         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4574 #endif
4575 };
4576
4577 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4578 {
4579         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4580                 return -EOPNOTSUPP;
4581         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4582             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4583             !MLX5_CAP_ETH(mdev, csum_cap) ||
4584             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4585             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4586             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4587             MLX5_CAP_FLOWTABLE(mdev,
4588                                flow_table_properties_nic_receive.max_ft_level)
4589                                < 3) {
4590                 mlx5_core_warn(mdev,
4591                                "Not creating net device, some required device capabilities are missing\n");
4592                 return -EOPNOTSUPP;
4593         }
4594         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4595                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4596         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4597                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4598
4599         return 0;
4600 }
4601
4602 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4603                                    int num_channels)
4604 {
4605         int i;
4606
4607         for (i = 0; i < len; i++)
4608                 indirection_rqt[i] = i % num_channels;
4609 }
4610
4611 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4612 {
4613         u32 link_speed = 0;
4614         u32 pci_bw = 0;
4615
4616         mlx5e_port_max_linkspeed(mdev, &link_speed);
4617         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4618         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4619                            link_speed, pci_bw);
4620
4621 #define MLX5E_SLOW_PCI_RATIO (2)
4622
4623         return link_speed && pci_bw &&
4624                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4625 }
4626
4627 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4628 {
4629         struct dim_cq_moder moder;
4630
4631         moder.cq_period_mode = cq_period_mode;
4632         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4633         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4634         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4635                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4636
4637         return moder;
4638 }
4639
4640 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4641 {
4642         struct dim_cq_moder moder;
4643
4644         moder.cq_period_mode = cq_period_mode;
4645         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4646         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4647         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4648                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4649
4650         return moder;
4651 }
4652
4653 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4654 {
4655         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4656                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4657                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4658 }
4659
4660 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4661 {
4662         if (params->tx_dim_enabled) {
4663                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4664
4665                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4666         } else {
4667                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4668         }
4669
4670         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4671                         params->tx_cq_moderation.cq_period_mode ==
4672                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4673 }
4674
4675 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4676 {
4677         if (params->rx_dim_enabled) {
4678                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4679
4680                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4681         } else {
4682                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4683         }
4684
4685         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4686                         params->rx_cq_moderation.cq_period_mode ==
4687                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4688 }
4689
4690 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4691 {
4692         int i;
4693
4694         /* The supported periods are organized in ascending order */
4695         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4696                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4697                         break;
4698
4699         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4700 }
4701
4702 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4703                            struct mlx5e_params *params)
4704 {
4705         /* Prefer Striding RQ, unless any of the following holds:
4706          * - Striding RQ configuration is not possible/supported.
4707          * - Slow PCI heuristic.
4708          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4709          *
4710          * No XSK params: checking the availability of striding RQ in general.
4711          */
4712         if (!slow_pci_heuristic(mdev) &&
4713             mlx5e_striding_rq_possible(mdev, params) &&
4714             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4715              !mlx5e_rx_is_linear_skb(params, NULL)))
4716                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4717         mlx5e_set_rq_type(mdev, params);
4718         mlx5e_init_rq_type_params(mdev, params);
4719 }
4720
4721 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4722                             u16 num_channels)
4723 {
4724         enum mlx5e_traffic_types tt;
4725
4726         rss_params->hfunc = ETH_RSS_HASH_TOP;
4727         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4728                             sizeof(rss_params->toeplitz_hash_key));
4729         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4730                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4731         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4732                 rss_params->rx_hash_fields[tt] =
4733                         tirc_default_config[tt].rx_hash_fields;
4734 }
4735
4736 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4737                             struct mlx5e_xsk *xsk,
4738                             struct mlx5e_rss_params *rss_params,
4739                             struct mlx5e_params *params,
4740                             u16 max_channels, u16 mtu)
4741 {
4742         u8 rx_cq_period_mode;
4743
4744         params->sw_mtu = mtu;
4745         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4746         params->num_channels = max_channels;
4747         params->num_tc       = 1;
4748
4749         /* SQ */
4750         params->log_sq_size = is_kdump_kernel() ?
4751                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4752                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4753
4754         /* XDP SQ */
4755         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4756                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4757
4758         /* set CQE compression */
4759         params->rx_cqe_compress_def = false;
4760         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4761             MLX5_CAP_GEN(mdev, vport_group_manager))
4762                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4763
4764         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4765         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4766
4767         /* RQ */
4768         mlx5e_build_rq_params(mdev, params);
4769
4770         /* HW LRO */
4771
4772         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4773         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4774                 /* No XSK params: checking the availability of striding RQ in general. */
4775                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4776                         params->lro_en = !slow_pci_heuristic(mdev);
4777         }
4778         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4779
4780         /* CQ moderation params */
4781         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4782                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4783                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4784         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4785         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4786         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4787         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4788
4789         /* TX inline */
4790         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4791
4792         /* RSS */
4793         mlx5e_build_rss_params(rss_params, params->num_channels);
4794         params->tunneled_offload_en =
4795                 mlx5e_tunnel_inner_ft_supported(mdev);
4796
4797         /* AF_XDP */
4798         params->xsk = xsk;
4799 }
4800
4801 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4802 {
4803         struct mlx5e_priv *priv = netdev_priv(netdev);
4804
4805         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4806         if (is_zero_ether_addr(netdev->dev_addr) &&
4807             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4808                 eth_hw_addr_random(netdev);
4809                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4810         }
4811 }
4812
4813 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4814 {
4815         struct mlx5e_priv *priv = netdev_priv(netdev);
4816         struct mlx5_core_dev *mdev = priv->mdev;
4817         bool fcs_supported;
4818         bool fcs_enabled;
4819
4820         SET_NETDEV_DEV(netdev, mdev->device);
4821
4822         netdev->netdev_ops = &mlx5e_netdev_ops;
4823
4824 #ifdef CONFIG_MLX5_CORE_EN_DCB
4825         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4826                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4827 #endif
4828
4829         netdev->watchdog_timeo    = 15 * HZ;
4830
4831         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4832
4833         netdev->vlan_features    |= NETIF_F_SG;
4834         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4835         netdev->vlan_features    |= NETIF_F_GRO;
4836         netdev->vlan_features    |= NETIF_F_TSO;
4837         netdev->vlan_features    |= NETIF_F_TSO6;
4838         netdev->vlan_features    |= NETIF_F_RXCSUM;
4839         netdev->vlan_features    |= NETIF_F_RXHASH;
4840
4841         netdev->mpls_features    |= NETIF_F_SG;
4842         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4843         netdev->mpls_features    |= NETIF_F_TSO;
4844         netdev->mpls_features    |= NETIF_F_TSO6;
4845
4846         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4847         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4848
4849         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4850             mlx5e_check_fragmented_striding_rq_cap(mdev))
4851                 netdev->vlan_features    |= NETIF_F_LRO;
4852
4853         netdev->hw_features       = netdev->vlan_features;
4854         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4855         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4856         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4857         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4858
4859         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4860             MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4861                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4862                 netdev->hw_enc_features |= NETIF_F_TSO;
4863                 netdev->hw_enc_features |= NETIF_F_TSO6;
4864                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4865         }
4866
4867         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4868                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4869                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4870                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4871                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4872                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4873         }
4874
4875         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4876                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4877                                            NETIF_F_GSO_GRE_CSUM;
4878                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4879                                            NETIF_F_GSO_GRE_CSUM;
4880                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4881                                                 NETIF_F_GSO_GRE_CSUM;
4882         }
4883
4884         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4885         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4886         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4887         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4888
4889         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4890
4891         if (fcs_supported)
4892                 netdev->hw_features |= NETIF_F_RXALL;
4893
4894         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4895                 netdev->hw_features |= NETIF_F_RXFCS;
4896
4897         netdev->features          = netdev->hw_features;
4898         if (!priv->channels.params.lro_en)
4899                 netdev->features  &= ~NETIF_F_LRO;
4900
4901         if (fcs_enabled)
4902                 netdev->features  &= ~NETIF_F_RXALL;
4903
4904         if (!priv->channels.params.scatter_fcs_en)
4905                 netdev->features  &= ~NETIF_F_RXFCS;
4906
4907         /* prefere CQE compression over rxhash */
4908         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4909                 netdev->features &= ~NETIF_F_RXHASH;
4910
4911 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4912         if (FT_CAP(flow_modify_en) &&
4913             FT_CAP(modify_root) &&
4914             FT_CAP(identified_miss_table_mode) &&
4915             FT_CAP(flow_table_modify)) {
4916 #ifdef CONFIG_MLX5_ESWITCH
4917                 netdev->hw_features      |= NETIF_F_HW_TC;
4918 #endif
4919 #ifdef CONFIG_MLX5_EN_ARFS
4920                 netdev->hw_features      |= NETIF_F_NTUPLE;
4921 #endif
4922         }
4923
4924         netdev->features         |= NETIF_F_HIGHDMA;
4925         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4926
4927         netdev->priv_flags       |= IFF_UNICAST_FLT;
4928
4929         mlx5e_set_netdev_dev_addr(netdev);
4930         mlx5e_ipsec_build_netdev(priv);
4931         mlx5e_tls_build_netdev(priv);
4932 }
4933
4934 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4935 {
4936         struct mlx5_core_dev *mdev = priv->mdev;
4937         int err;
4938
4939         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4940         if (err) {
4941                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4942                 priv->q_counter = 0;
4943         }
4944
4945         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4946         if (err) {
4947                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4948                 priv->drop_rq_q_counter = 0;
4949         }
4950 }
4951
4952 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4953 {
4954         if (priv->q_counter)
4955                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4956
4957         if (priv->drop_rq_q_counter)
4958                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4959 }
4960
4961 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4962                           struct net_device *netdev,
4963                           const struct mlx5e_profile *profile,
4964                           void *ppriv)
4965 {
4966         struct mlx5e_priv *priv = netdev_priv(netdev);
4967         struct mlx5e_rss_params *rss = &priv->rss_params;
4968         int err;
4969
4970         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4971         if (err)
4972                 return err;
4973
4974         mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
4975                                mlx5e_get_netdev_max_channels(netdev),
4976                                netdev->mtu);
4977
4978         mlx5e_timestamp_init(priv);
4979
4980         err = mlx5e_ipsec_init(priv);
4981         if (err)
4982                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4983         err = mlx5e_tls_init(priv);
4984         if (err)
4985                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4986         mlx5e_build_nic_netdev(netdev);
4987         mlx5e_build_tc2txq_maps(priv);
4988
4989         return 0;
4990 }
4991
4992 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4993 {
4994         mlx5e_tls_cleanup(priv);
4995         mlx5e_ipsec_cleanup(priv);
4996         mlx5e_netdev_cleanup(priv->netdev, priv);
4997 }
4998
4999 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5000 {
5001         struct mlx5_core_dev *mdev = priv->mdev;
5002         int err;
5003
5004         mlx5e_create_q_counters(priv);
5005
5006         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5007         if (err) {
5008                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5009                 goto err_destroy_q_counters;
5010         }
5011
5012         err = mlx5e_create_indirect_rqt(priv);
5013         if (err)
5014                 goto err_close_drop_rq;
5015
5016         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5017         if (err)
5018                 goto err_destroy_indirect_rqts;
5019
5020         err = mlx5e_create_indirect_tirs(priv, true);
5021         if (err)
5022                 goto err_destroy_direct_rqts;
5023
5024         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5025         if (err)
5026                 goto err_destroy_indirect_tirs;
5027
5028         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5029         if (unlikely(err))
5030                 goto err_destroy_direct_tirs;
5031
5032         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5033         if (unlikely(err))
5034                 goto err_destroy_xsk_rqts;
5035
5036         err = mlx5e_create_flow_steering(priv);
5037         if (err) {
5038                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5039                 goto err_destroy_xsk_tirs;
5040         }
5041
5042         err = mlx5e_tc_nic_init(priv);
5043         if (err)
5044                 goto err_destroy_flow_steering;
5045
5046         return 0;
5047
5048 err_destroy_flow_steering:
5049         mlx5e_destroy_flow_steering(priv);
5050 err_destroy_xsk_tirs:
5051         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5052 err_destroy_xsk_rqts:
5053         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5054 err_destroy_direct_tirs:
5055         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5056 err_destroy_indirect_tirs:
5057         mlx5e_destroy_indirect_tirs(priv, true);
5058 err_destroy_direct_rqts:
5059         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5060 err_destroy_indirect_rqts:
5061         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5062 err_close_drop_rq:
5063         mlx5e_close_drop_rq(&priv->drop_rq);
5064 err_destroy_q_counters:
5065         mlx5e_destroy_q_counters(priv);
5066         return err;
5067 }
5068
5069 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5070 {
5071         mlx5e_tc_nic_cleanup(priv);
5072         mlx5e_destroy_flow_steering(priv);
5073         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5074         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5075         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5076         mlx5e_destroy_indirect_tirs(priv, true);
5077         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5078         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5079         mlx5e_close_drop_rq(&priv->drop_rq);
5080         mlx5e_destroy_q_counters(priv);
5081 }
5082
5083 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5084 {
5085         int err;
5086
5087         err = mlx5e_create_tises(priv);
5088         if (err) {
5089                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5090                 return err;
5091         }
5092
5093 #ifdef CONFIG_MLX5_CORE_EN_DCB
5094         mlx5e_dcbnl_initialize(priv);
5095 #endif
5096         mlx5e_tx_reporter_create(priv);
5097         return 0;
5098 }
5099
5100 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5101 {
5102         struct net_device *netdev = priv->netdev;
5103         struct mlx5_core_dev *mdev = priv->mdev;
5104
5105         mlx5e_init_l2_addr(priv);
5106
5107         /* Marking the link as currently not needed by the Driver */
5108         if (!netif_running(netdev))
5109                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5110
5111         mlx5e_set_netdev_mtu_boundaries(priv);
5112         mlx5e_set_dev_port_mtu(priv);
5113
5114         mlx5_lag_add(mdev, netdev);
5115
5116         mlx5e_enable_async_events(priv);
5117         if (mlx5e_monitor_counter_supported(priv))
5118                 mlx5e_monitor_counter_init(priv);
5119
5120         if (netdev->reg_state != NETREG_REGISTERED)
5121                 return;
5122 #ifdef CONFIG_MLX5_CORE_EN_DCB
5123         mlx5e_dcbnl_init_app(priv);
5124 #endif
5125
5126         queue_work(priv->wq, &priv->set_rx_mode_work);
5127
5128         rtnl_lock();
5129         if (netif_running(netdev))
5130                 mlx5e_open(netdev);
5131         netif_device_attach(netdev);
5132         rtnl_unlock();
5133 }
5134
5135 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5136 {
5137         struct mlx5_core_dev *mdev = priv->mdev;
5138
5139 #ifdef CONFIG_MLX5_CORE_EN_DCB
5140         if (priv->netdev->reg_state == NETREG_REGISTERED)
5141                 mlx5e_dcbnl_delete_app(priv);
5142 #endif
5143
5144         rtnl_lock();
5145         if (netif_running(priv->netdev))
5146                 mlx5e_close(priv->netdev);
5147         netif_device_detach(priv->netdev);
5148         rtnl_unlock();
5149
5150         queue_work(priv->wq, &priv->set_rx_mode_work);
5151
5152         if (mlx5e_monitor_counter_supported(priv))
5153                 mlx5e_monitor_counter_cleanup(priv);
5154
5155         mlx5e_disable_async_events(priv);
5156         mlx5_lag_remove(mdev);
5157 }
5158
5159 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5160 {
5161         return mlx5e_refresh_tirs(priv, false);
5162 }
5163
5164 static const struct mlx5e_profile mlx5e_nic_profile = {
5165         .init              = mlx5e_nic_init,
5166         .cleanup           = mlx5e_nic_cleanup,
5167         .init_rx           = mlx5e_init_nic_rx,
5168         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5169         .init_tx           = mlx5e_init_nic_tx,
5170         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5171         .enable            = mlx5e_nic_enable,
5172         .disable           = mlx5e_nic_disable,
5173         .update_rx         = mlx5e_update_nic_rx,
5174         .update_stats      = mlx5e_update_ndo_stats,
5175         .update_carrier    = mlx5e_update_carrier,
5176         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5177         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5178         .max_tc            = MLX5E_MAX_NUM_TC,
5179 };
5180
5181 /* mlx5e generic netdev management API (move to en_common.c) */
5182
5183 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5184 int mlx5e_netdev_init(struct net_device *netdev,
5185                       struct mlx5e_priv *priv,
5186                       struct mlx5_core_dev *mdev,
5187                       const struct mlx5e_profile *profile,
5188                       void *ppriv)
5189 {
5190         /* priv init */
5191         priv->mdev        = mdev;
5192         priv->netdev      = netdev;
5193         priv->profile     = profile;
5194         priv->ppriv       = ppriv;
5195         priv->msglevel    = MLX5E_MSG_LEVEL;
5196         priv->max_opened_tc = 1;
5197
5198         mutex_init(&priv->state_lock);
5199         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5200         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5201         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5202         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5203
5204         priv->wq = create_singlethread_workqueue("mlx5e");
5205         if (!priv->wq)
5206                 return -ENOMEM;
5207
5208         /* netdev init */
5209         netif_carrier_off(netdev);
5210
5211 #ifdef CONFIG_MLX5_EN_ARFS
5212         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5213 #endif
5214
5215         return 0;
5216 }
5217
5218 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5219 {
5220         destroy_workqueue(priv->wq);
5221 }
5222
5223 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5224                                        const struct mlx5e_profile *profile,
5225                                        int nch,
5226                                        void *ppriv)
5227 {
5228         struct net_device *netdev;
5229         int err;
5230
5231         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5232                                     nch * profile->max_tc,
5233                                     nch * MLX5E_NUM_RQ_GROUPS);
5234         if (!netdev) {
5235                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5236                 return NULL;
5237         }
5238
5239         err = profile->init(mdev, netdev, profile, ppriv);
5240         if (err) {
5241                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5242                 goto err_free_netdev;
5243         }
5244
5245         return netdev;
5246
5247 err_free_netdev:
5248         free_netdev(netdev);
5249
5250         return NULL;
5251 }
5252
5253 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5254 {
5255         const struct mlx5e_profile *profile;
5256         int max_nch;
5257         int err;
5258
5259         profile = priv->profile;
5260         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5261
5262         /* max number of channels may have changed */
5263         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5264         if (priv->channels.params.num_channels > max_nch) {
5265                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5266                 priv->channels.params.num_channels = max_nch;
5267                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5268                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5269         }
5270
5271         err = profile->init_tx(priv);
5272         if (err)
5273                 goto out;
5274
5275         err = profile->init_rx(priv);
5276         if (err)
5277                 goto err_cleanup_tx;
5278
5279         if (profile->enable)
5280                 profile->enable(priv);
5281
5282         return 0;
5283
5284 err_cleanup_tx:
5285         profile->cleanup_tx(priv);
5286
5287 out:
5288         return err;
5289 }
5290
5291 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5292 {
5293         const struct mlx5e_profile *profile = priv->profile;
5294
5295         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5296
5297         if (profile->disable)
5298                 profile->disable(priv);
5299         flush_workqueue(priv->wq);
5300
5301         profile->cleanup_rx(priv);
5302         profile->cleanup_tx(priv);
5303         cancel_work_sync(&priv->update_stats_work);
5304 }
5305
5306 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5307 {
5308         const struct mlx5e_profile *profile = priv->profile;
5309         struct net_device *netdev = priv->netdev;
5310
5311         if (profile->cleanup)
5312                 profile->cleanup(priv);
5313         free_netdev(netdev);
5314 }
5315
5316 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5317  * hardware contexts and to connect it to the current netdev.
5318  */
5319 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5320 {
5321         struct mlx5e_priv *priv = vpriv;
5322         struct net_device *netdev = priv->netdev;
5323         int err;
5324
5325         if (netif_device_present(netdev))
5326                 return 0;
5327
5328         err = mlx5e_create_mdev_resources(mdev);
5329         if (err)
5330                 return err;
5331
5332         err = mlx5e_attach_netdev(priv);
5333         if (err) {
5334                 mlx5e_destroy_mdev_resources(mdev);
5335                 return err;
5336         }
5337
5338         return 0;
5339 }
5340
5341 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5342 {
5343         struct mlx5e_priv *priv = vpriv;
5344         struct net_device *netdev = priv->netdev;
5345
5346 #ifdef CONFIG_MLX5_ESWITCH
5347         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5348                 return;
5349 #endif
5350
5351         if (!netif_device_present(netdev))
5352                 return;
5353
5354         mlx5e_detach_netdev(priv);
5355         mlx5e_destroy_mdev_resources(mdev);
5356 }
5357
5358 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5359 {
5360         struct net_device *netdev;
5361         void *priv;
5362         int err;
5363         int nch;
5364
5365         err = mlx5e_check_required_hca_cap(mdev);
5366         if (err)
5367                 return NULL;
5368
5369 #ifdef CONFIG_MLX5_ESWITCH
5370         if (MLX5_ESWITCH_MANAGER(mdev) &&
5371             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5372                 mlx5e_rep_register_vport_reps(mdev);
5373                 return mdev;
5374         }
5375 #endif
5376
5377         nch = mlx5e_get_max_num_channels(mdev);
5378         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5379         if (!netdev) {
5380                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5381                 return NULL;
5382         }
5383
5384         priv = netdev_priv(netdev);
5385
5386         err = mlx5e_attach(mdev, priv);
5387         if (err) {
5388                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5389                 goto err_destroy_netdev;
5390         }
5391
5392         err = register_netdev(netdev);
5393         if (err) {
5394                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5395                 goto err_detach;
5396         }
5397
5398 #ifdef CONFIG_MLX5_CORE_EN_DCB
5399         mlx5e_dcbnl_init_app(priv);
5400 #endif
5401         return priv;
5402
5403 err_detach:
5404         mlx5e_detach(mdev, priv);
5405 err_destroy_netdev:
5406         mlx5e_destroy_netdev(priv);
5407         return NULL;
5408 }
5409
5410 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5411 {
5412         struct mlx5e_priv *priv;
5413
5414 #ifdef CONFIG_MLX5_ESWITCH
5415         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5416                 mlx5e_rep_unregister_vport_reps(mdev);
5417                 return;
5418         }
5419 #endif
5420         priv = vpriv;
5421 #ifdef CONFIG_MLX5_CORE_EN_DCB
5422         mlx5e_dcbnl_delete_app(priv);
5423 #endif
5424         unregister_netdev(priv->netdev);
5425         mlx5e_detach(mdev, vpriv);
5426         mlx5e_destroy_netdev(priv);
5427 }
5428
5429 static struct mlx5_interface mlx5e_interface = {
5430         .add       = mlx5e_add,
5431         .remove    = mlx5e_remove,
5432         .attach    = mlx5e_attach,
5433         .detach    = mlx5e_detach,
5434         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5435 };
5436
5437 void mlx5e_init(void)
5438 {
5439         mlx5e_ipsec_build_inverse_table();
5440         mlx5e_build_ptys2ethtool_map();
5441         mlx5_register_interface(&mlx5e_interface);
5442 }
5443
5444 void mlx5e_cleanup(void)
5445 {
5446         mlx5_unregister_interface(&mlx5e_interface);
5447 }