drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/reporter.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65
  66
  67 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  68 {
  69         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  70                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  71                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  72         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  73         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  74
  75         if (!striding_rq_umr)
  76                 return false;
  77         if (!inline_umr) {
  78                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  79                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  80                 return false;
  81         }
  82         return true;
  83 }
  84
  85 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  86                                struct mlx5e_params *params)
  87 {
  88         params->log_rq_mtu_frames = is_kdump_kernel() ?
  89                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  90                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  91
  92         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  93                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  94                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  95                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  96                        BIT(params->log_rq_mtu_frames),
  97                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
  98                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
  99 }
 100
 101 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 102                                 struct mlx5e_params *params)
 103 {
 104         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 105                 return false;
 106
 107         if (MLX5_IPSEC_DEV(mdev))
 108                 return false;
 109
 110         if (params->xdp_prog) {
 111                 /* XSK params are not considered here. If striding RQ is in use,
 112                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 113                  * be called with the known XSK params.
 114                  */
 115                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 116                         return false;
 117         }
 118
 119         return true;
 120 }
 121
 122 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 123 {
 124         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 125                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 126                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 127                 MLX5_WQ_TYPE_CYCLIC;
 128 }
 129
 130 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 131 {
 132         struct mlx5_core_dev *mdev = priv->mdev;
 133         u8 port_state;
 134
 135         port_state = mlx5_query_vport_state(mdev,
 136                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 137                                             0);
 138
 139         if (port_state == VPORT_STATE_UP) {
 140                 netdev_info(priv->netdev, "Link up\n");
 141                 netif_carrier_on(priv->netdev);
 142         } else {
 143                 netdev_info(priv->netdev, "Link down\n");
 144                 netif_carrier_off(priv->netdev);
 145         }
 146 }
 147
 148 static void mlx5e_update_carrier_work(struct work_struct *work)
 149 {
 150         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 151                                                update_carrier_work);
 152
 153         mutex_lock(&priv->state_lock);
 154         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 155                 if (priv->profile->update_carrier)
 156                         priv->profile->update_carrier(priv);
 157         mutex_unlock(&priv->state_lock);
 158 }
 159
 160 void mlx5e_update_stats(struct mlx5e_priv *priv)
 161 {
 162         int i;
 163
 164         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 165                 if (mlx5e_stats_grps[i].update_stats)
 166                         mlx5e_stats_grps[i].update_stats(priv);
 167 }
 168
 169 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 170 {
 171         int i;
 172
 173         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 174                 if (mlx5e_stats_grps[i].update_stats_mask &
 175                     MLX5E_NDO_UPDATE_STATS)
 176                         mlx5e_stats_grps[i].update_stats(priv);
 177 }
 178
 179 static void mlx5e_update_stats_work(struct work_struct *work)
 180 {
 181         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 182                                                update_stats_work);
 183
 184         mutex_lock(&priv->state_lock);
 185         priv->profile->update_stats(priv);
 186         mutex_unlock(&priv->state_lock);
 187 }
 188
 189 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 190 {
 191         if (!priv->profile->update_stats)
 192                 return;
 193
 194         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 195                 return;
 196
 197         queue_work(priv->wq, &priv->update_stats_work);
 198 }
 199
 200 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 201 {
 202         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 203         struct mlx5_eqe   *eqe = data;
 204
 205         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 206                 return NOTIFY_DONE;
 207
 208         switch (eqe->sub_type) {
 209         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 210         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 211                 queue_work(priv->wq, &priv->update_carrier_work);
 212                 break;
 213         default:
 214                 return NOTIFY_DONE;
 215         }
 216
 217         return NOTIFY_OK;
 218 }
 219
 220 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 221 {
 222         priv->events_nb.notifier_call = async_event;
 223         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 224 }
 225
 226 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 227 {
 228         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 229 }
 230
 231 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 232                                        struct mlx5e_icosq *sq,
 233                                        struct mlx5e_umr_wqe *wqe)
 234 {
 235         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 236         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 237         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 238
 239         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 240                                       ds_cnt);
 241         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 242         cseg->imm       = rq->mkey_be;
 243
 244         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 245         ucseg->xlt_octowords =
 246                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 247         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 248 }
 249
 250 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 251 {
 252         switch (rq->wq_type) {
 253         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 254                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 255         default:
 256                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 257         }
 258 }
 259
 260 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 261 {
 262         switch (rq->wq_type) {
 263         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 264                 return rq->mpwqe.wq.cur_sz;
 265         default:
 266                 return rq->wqe.wq.cur_sz;
 267         }
 268 }
 269
 270 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 271                                      struct mlx5e_channel *c)
 272 {
 273         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 274
 275         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 276                                                   sizeof(*rq->mpwqe.info)),
 277                                        GFP_KERNEL, cpu_to_node(c->cpu));
 278         if (!rq->mpwqe.info)
 279                 return -ENOMEM;
 280
 281         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 282
 283         return 0;
 284 }
 285
 286 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 287                                  u64 npages, u8 page_shift,
 288                                  struct mlx5_core_mkey *umr_mkey)
 289 {
 290         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 291         void *mkc;
 292         u32 *in;
 293         int err;
 294
 295         in = kvzalloc(inlen, GFP_KERNEL);
 296         if (!in)
 297                 return -ENOMEM;
 298
 299         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 300
 301         MLX5_SET(mkc, mkc, free, 1);
 302         MLX5_SET(mkc, mkc, umr_en, 1);
 303         MLX5_SET(mkc, mkc, lw, 1);
 304         MLX5_SET(mkc, mkc, lr, 1);
 305         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 306
 307         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 308         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 309         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 310         MLX5_SET(mkc, mkc, translations_octword_size,
 311                  MLX5_MTT_OCTW(npages));
 312         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 313
 314         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 315
 316         kvfree(in);
 317         return err;
 318 }
 319
 320 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 321 {
 322         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 323
 324         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 325 }
 326
 327 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 328 {
 329         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 330 }
 331
 332 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 333 {
 334         struct mlx5e_wqe_frag_info next_frag = {};
 335         struct mlx5e_wqe_frag_info *prev = NULL;
 336         int i;
 337
 338         next_frag.di = &rq->wqe.di[0];
 339
 340         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 341                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 342                 struct mlx5e_wqe_frag_info *frag =
 343                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 344                 int f;
 345
 346                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 347                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 348                                 next_frag.di++;
 349                                 next_frag.offset = 0;
 350                                 if (prev)
 351                                         prev->last_in_page = true;
 352                         }
 353                         *frag = next_frag;
 354
 355                         /* prepare next */
 356                         next_frag.offset += frag_info[f].frag_stride;
 357                         prev = frag;
 358                 }
 359         }
 360
 361         if (prev)
 362                 prev->last_in_page = true;
 363 }
 364
 365 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 366                               int wq_sz, int cpu)
 367 {
 368         int len = wq_sz << rq->wqe.info.log_num_frags;
 369
 370         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 371                                    GFP_KERNEL, cpu_to_node(cpu));
 372         if (!rq->wqe.di)
 373                 return -ENOMEM;
 374
 375         mlx5e_init_frags_partition(rq);
 376
 377         return 0;
 378 }
 379
 380 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 381 {
 382         kvfree(rq->wqe.di);
 383 }
 384
 385 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 386                           struct mlx5e_params *params,
 387                           struct mlx5e_xsk_param *xsk,
 388                           struct xdp_umem *umem,
 389                           struct mlx5e_rq_param *rqp,
 390                           struct mlx5e_rq *rq)
 391 {
 392         struct page_pool_params pp_params = { 0 };
 393         struct mlx5_core_dev *mdev = c->mdev;
 394         void *rqc = rqp->rqc;
 395         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 396         u32 num_xsk_frames = 0;
 397         u32 rq_xdp_ix;
 398         u32 pool_size;
 399         int wq_sz;
 400         int err;
 401         int i;
 402
 403         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 404
 405         rq->wq_type = params->rq_wq_type;
 406         rq->pdev    = c->pdev;
 407         rq->netdev  = c->netdev;
 408         rq->tstamp  = c->tstamp;
 409         rq->clock   = &mdev->clock;
 410         rq->channel = c;
 411         rq->ix      = c->ix;
 412         rq->mdev    = mdev;
 413         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 414         rq->xdpsq   = &c->rq_xdpsq;
 415         rq->umem    = umem;
 416
 417         if (rq->umem)
 418                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 419         else
 420                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 421
 422         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 423         if (IS_ERR(rq->xdp_prog)) {
 424                 err = PTR_ERR(rq->xdp_prog);
 425                 rq->xdp_prog = NULL;
 426                 goto err_rq_wq_destroy;
 427         }
 428
 429         rq_xdp_ix = rq->ix;
 430         if (xsk)
 431                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 432         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 433         if (err < 0)
 434                 goto err_rq_wq_destroy;
 435
 436         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 437         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 438         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 439         pool_size = 1 << params->log_rq_mtu_frames;
 440
 441         switch (rq->wq_type) {
 442         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 443                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 444                                         &rq->wq_ctrl);
 445                 if (err)
 446                         return err;
 447
 448                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 449
 450                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 451
 452                 if (xsk)
 453                         num_xsk_frames = wq_sz <<
 454                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 455
 456                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 457                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 458
 459                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 460                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 461
 462                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 463 #ifdef CONFIG_MLX5_EN_IPSEC
 464                 if (MLX5_IPSEC_DEV(mdev)) {
 465                         err = -EINVAL;
 466                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 467                         goto err_rq_wq_destroy;
 468                 }
 469 #endif
 470                 if (!rq->handle_rx_cqe) {
 471                         err = -EINVAL;
 472                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 473                         goto err_rq_wq_destroy;
 474                 }
 475
 476                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 477                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 478                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 479                                 mlx5e_skb_from_cqe_mpwrq_linear :
 480                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 481
 482                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 483                 rq->mpwqe.num_strides =
 484                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 485
 486                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 487                 if (err)
 488                         goto err_rq_wq_destroy;
 489                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 490
 491                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 492                 if (err)
 493                         goto err_free;
 494                 break;
 495         default: /* MLX5_WQ_TYPE_CYCLIC */
 496                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 497                                          &rq->wq_ctrl);
 498                 if (err)
 499                         return err;
 500
 501                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 502
 503                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 504
 505                 if (xsk)
 506                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 507
 508                 rq->wqe.info = rqp->frags_info;
 509                 rq->wqe.frags =
 510                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 511                                         (wq_sz << rq->wqe.info.log_num_frags)),
 512                                       GFP_KERNEL, cpu_to_node(c->cpu));
 513                 if (!rq->wqe.frags) {
 514                         err = -ENOMEM;
 515                         goto err_free;
 516                 }
 517
 518                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 519                 if (err)
 520                         goto err_free;
 521
 522                 rq->post_wqes = mlx5e_post_rx_wqes;
 523                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 524
 525 #ifdef CONFIG_MLX5_EN_IPSEC
 526                 if (c->priv->ipsec)
 527                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 528                 else
 529 #endif
 530                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 531                 if (!rq->handle_rx_cqe) {
 532                         err = -EINVAL;
 533                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 534                         goto err_free;
 535                 }
 536
 537                 rq->wqe.skb_from_cqe = xsk ?
 538                         mlx5e_xsk_skb_from_cqe_linear :
 539                         mlx5e_rx_is_linear_skb(params, NULL) ?
 540                                 mlx5e_skb_from_cqe_linear :
 541                                 mlx5e_skb_from_cqe_nonlinear;
 542                 rq->mkey_be = c->mkey_be;
 543         }
 544
 545         if (xsk) {
 546                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 547                 if (unlikely(err)) {
 548                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 549                                       num_xsk_frames);
 550                         goto err_free;
 551                 }
 552
 553                 rq->zca.free = mlx5e_xsk_zca_free;
 554                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 555                                                  MEM_TYPE_ZERO_COPY,
 556                                                  &rq->zca);
 557         } else {
 558                 /* Create a page_pool and register it with rxq */
 559                 pp_params.order     = 0;
 560                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 561                 pp_params.pool_size = pool_size;
 562                 pp_params.nid       = cpu_to_node(c->cpu);
 563                 pp_params.dev       = c->pdev;
 564                 pp_params.dma_dir   = rq->buff.map_dir;
 565
 566                 /* page_pool can be used even when there is no rq->xdp_prog,
 567                  * given page_pool does not handle DMA mapping there is no
 568                  * required state to clear. And page_pool gracefully handle
 569                  * elevated refcnt.
 570                  */
 571                 rq->page_pool = page_pool_create(&pp_params);
 572                 if (IS_ERR(rq->page_pool)) {
 573                         err = PTR_ERR(rq->page_pool);
 574                         rq->page_pool = NULL;
 575                         goto err_free;
 576                 }
 577                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 578                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 579         }
 580         if (err)
 581                 goto err_free;
 582
 583         for (i = 0; i < wq_sz; i++) {
 584                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 585                         struct mlx5e_rx_wqe_ll *wqe =
 586                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 587                         u32 byte_count =
 588                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 589                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 590
 591                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 592                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 593                         wqe->data[0].lkey = rq->mkey_be;
 594                 } else {
 595                         struct mlx5e_rx_wqe_cyc *wqe =
 596                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 597                         int f;
 598
 599                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 600                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 601                                         MLX5_HW_START_PADDING;
 602
 603                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 604                                 wqe->data[f].lkey = rq->mkey_be;
 605                         }
 606                         /* check if num_frags is not a pow of two */
 607                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 608                                 wqe->data[f].byte_count = 0;
 609                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 610                                 wqe->data[f].addr = 0;
 611                         }
 612                 }
 613         }
 614
 615         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 616
 617         switch (params->rx_cq_moderation.cq_period_mode) {
 618         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 619                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 620                 break;
 621         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 622         default:
 623                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 624         }
 625
 626         rq->page_cache.head = 0;
 627         rq->page_cache.tail = 0;
 628
 629         return 0;
 630
 631 err_free:
 632         switch (rq->wq_type) {
 633         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 634                 kvfree(rq->mpwqe.info);
 635                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 636                 break;
 637         default: /* MLX5_WQ_TYPE_CYCLIC */
 638                 kvfree(rq->wqe.frags);
 639                 mlx5e_free_di_list(rq);
 640         }
 641
 642 err_rq_wq_destroy:
 643         if (rq->xdp_prog)
 644                 bpf_prog_put(rq->xdp_prog);
 645         xdp_rxq_info_unreg(&rq->xdp_rxq);
 646         page_pool_destroy(rq->page_pool);
 647         mlx5_wq_destroy(&rq->wq_ctrl);
 648
 649         return err;
 650 }
 651
 652 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 653 {
 654         int i;
 655
 656         if (rq->xdp_prog)
 657                 bpf_prog_put(rq->xdp_prog);
 658
 659         switch (rq->wq_type) {
 660         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 661                 kvfree(rq->mpwqe.info);
 662                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 663                 break;
 664         default: /* MLX5_WQ_TYPE_CYCLIC */
 665                 kvfree(rq->wqe.frags);
 666                 mlx5e_free_di_list(rq);
 667         }
 668
 669         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 670              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 671                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 672
 673                 /* With AF_XDP, page_cache is not used, so this loop is not
 674                  * entered, and it's safe to call mlx5e_page_release_dynamic
 675                  * directly.
 676                  */
 677                 mlx5e_page_release_dynamic(rq, dma_info, false);
 678         }
 679
 680         xdp_rxq_info_unreg(&rq->xdp_rxq);
 681         page_pool_destroy(rq->page_pool);
 682         mlx5_wq_destroy(&rq->wq_ctrl);
 683 }
 684
 685 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 686                            struct mlx5e_rq_param *param)
 687 {
 688         struct mlx5_core_dev *mdev = rq->mdev;
 689
 690         void *in;
 691         void *rqc;
 692         void *wq;
 693         int inlen;
 694         int err;
 695
 696         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 697                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 698         in = kvzalloc(inlen, GFP_KERNEL);
 699         if (!in)
 700                 return -ENOMEM;
 701
 702         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 703         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 704
 705         memcpy(rqc, param->rqc, sizeof(param->rqc));
 706
 707         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 708         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 709         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 710                                                 MLX5_ADAPTER_PAGE_SHIFT);
 711         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 712
 713         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 714                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 715
 716         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 717
 718         kvfree(in);
 719
 720         return err;
 721 }
 722
 723 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 724                                  int next_state)
 725 {
 726         struct mlx5_core_dev *mdev = rq->mdev;
 727
 728         void *in;
 729         void *rqc;
 730         int inlen;
 731         int err;
 732
 733         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 734         in = kvzalloc(inlen, GFP_KERNEL);
 735         if (!in)
 736                 return -ENOMEM;
 737
 738         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 739
 740         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 741         MLX5_SET(rqc, rqc, state, next_state);
 742
 743         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 744
 745         kvfree(in);
 746
 747         return err;
 748 }
 749
 750 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 751 {
 752         struct mlx5e_channel *c = rq->channel;
 753         struct mlx5e_priv *priv = c->priv;
 754         struct mlx5_core_dev *mdev = priv->mdev;
 755
 756         void *in;
 757         void *rqc;
 758         int inlen;
 759         int err;
 760
 761         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 762         in = kvzalloc(inlen, GFP_KERNEL);
 763         if (!in)
 764                 return -ENOMEM;
 765
 766         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 767
 768         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 769         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 770                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 771         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 772         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 773
 774         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 775
 776         kvfree(in);
 777
 778         return err;
 779 }
 780
 781 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 782 {
 783         struct mlx5e_channel *c = rq->channel;
 784         struct mlx5_core_dev *mdev = c->mdev;
 785         void *in;
 786         void *rqc;
 787         int inlen;
 788         int err;
 789
 790         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 791         in = kvzalloc(inlen, GFP_KERNEL);
 792         if (!in)
 793                 return -ENOMEM;
 794
 795         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 796
 797         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 798         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 799                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 800         MLX5_SET(rqc, rqc, vsd, vsd);
 801         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 802
 803         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 804
 805         kvfree(in);
 806
 807         return err;
 808 }
 809
 810 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 811 {
 812         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 813 }
 814
 815 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 816 {
 817         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 818         struct mlx5e_channel *c = rq->channel;
 819
 820         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 821
 822         do {
 823                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 824                         return 0;
 825
 826                 msleep(20);
 827         } while (time_before(jiffies, exp_time));
 828
 829         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 830                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 831
 832         return -ETIMEDOUT;
 833 }
 834
 835 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 836 {
 837         __be16 wqe_ix_be;
 838         u16 wqe_ix;
 839
 840         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 841                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 842                 u16 head = wq->head;
 843                 int i;
 844
 845                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 846                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 847                         rq->dealloc_wqe(rq, head);
 848                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 849                 }
 850
 851                 while (!mlx5_wq_ll_is_empty(wq)) {
 852                         struct mlx5e_rx_wqe_ll *wqe;
 853
 854                         wqe_ix_be = *wq->tail_next;
 855                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 856                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 857                         rq->dealloc_wqe(rq, wqe_ix);
 858                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 859                                        &wqe->next.next_wqe_index);
 860                 }
 861         } else {
 862                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 863
 864                 while (!mlx5_wq_cyc_is_empty(wq)) {
 865                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 866                         rq->dealloc_wqe(rq, wqe_ix);
 867                         mlx5_wq_cyc_pop(wq);
 868                 }
 869         }
 870
 871 }
 872
 873 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 874                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 875                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 876 {
 877         int err;
 878
 879         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 880         if (err)
 881                 return err;
 882
 883         err = mlx5e_create_rq(rq, param);
 884         if (err)
 885                 goto err_free_rq;
 886
 887         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 888         if (err)
 889                 goto err_destroy_rq;
 890
 891         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 892                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 893
 894         if (params->rx_dim_enabled)
 895                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 896
 897         /* We disable csum_complete when XDP is enabled since
 898          * XDP programs might manipulate packets which will render
 899          * skb->checksum incorrect.
 900          */
 901         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 902                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 903
 904         return 0;
 905
 906 err_destroy_rq:
 907         mlx5e_destroy_rq(rq);
 908 err_free_rq:
 909         mlx5e_free_rq(rq);
 910
 911         return err;
 912 }
 913
 914 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 915 {
 916         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 917         mlx5e_trigger_irq(&rq->channel->icosq);
 918 }
 919
 920 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 921 {
 922         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 923         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 924 }
 925
 926 void mlx5e_close_rq(struct mlx5e_rq *rq)
 927 {
 928         cancel_work_sync(&rq->dim.work);
 929         mlx5e_destroy_rq(rq);
 930         mlx5e_free_rx_descs(rq);
 931         mlx5e_free_rq(rq);
 932 }
 933
 934 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 935 {
 936         kvfree(sq->db.xdpi_fifo.xi);
 937         kvfree(sq->db.wqe_info);
 938 }
 939
 940 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 941 {
 942         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 943         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 944         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 945
 946         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 947                                       GFP_KERNEL, numa);
 948         if (!xdpi_fifo->xi)
 949                 return -ENOMEM;
 950
 951         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 952         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 953         xdpi_fifo->mask = dsegs_per_wq - 1;
 954
 955         return 0;
 956 }
 957
 958 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 959 {
 960         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 961         int err;
 962
 963         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 964                                         GFP_KERNEL, numa);
 965         if (!sq->db.wqe_info)
 966                 return -ENOMEM;
 967
 968         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 969         if (err) {
 970                 mlx5e_free_xdpsq_db(sq);
 971                 return err;
 972         }
 973
 974         return 0;
 975 }
 976
 977 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 978                              struct mlx5e_params *params,
 979                              struct xdp_umem *umem,
 980                              struct mlx5e_sq_param *param,
 981                              struct mlx5e_xdpsq *sq,
 982                              bool is_redirect)
 983 {
 984         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 985         struct mlx5_core_dev *mdev = c->mdev;
 986         struct mlx5_wq_cyc *wq = &sq->wq;
 987         int err;
 988
 989         sq->pdev      = c->pdev;
 990         sq->mkey_be   = c->mkey_be;
 991         sq->channel   = c;
 992         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 993         sq->min_inline_mode = params->tx_min_inline_mode;
 994         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 995         sq->umem      = umem;
 996
 997         sq->stats = sq->umem ?
 998                 &c->priv->channel_stats[c->ix].xsksq :
 999                 is_redirect ?
1000                         &c->priv->channel_stats[c->ix].xdpsq :
1001                         &c->priv->channel_stats[c->ix].rq_xdpsq;
1002
1003         param->wq.db_numa_node = cpu_to_node(c->cpu);
1004         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1005         if (err)
1006                 return err;
1007         wq->db = &wq->db[MLX5_SND_DBR];
1008
1009         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1010         if (err)
1011                 goto err_sq_wq_destroy;
1012
1013         return 0;
1014
1015 err_sq_wq_destroy:
1016         mlx5_wq_destroy(&sq->wq_ctrl);
1017
1018         return err;
1019 }
1020
1021 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1022 {
1023         mlx5e_free_xdpsq_db(sq);
1024         mlx5_wq_destroy(&sq->wq_ctrl);
1025 }
1026
1027 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1028 {
1029         kvfree(sq->db.ico_wqe);
1030 }
1031
1032 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1033 {
1034         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1035
1036         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1037                                                   sizeof(*sq->db.ico_wqe)),
1038                                        GFP_KERNEL, numa);
1039         if (!sq->db.ico_wqe)
1040                 return -ENOMEM;
1041
1042         return 0;
1043 }
1044
1045 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1046                              struct mlx5e_sq_param *param,
1047                              struct mlx5e_icosq *sq)
1048 {
1049         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1050         struct mlx5_core_dev *mdev = c->mdev;
1051         struct mlx5_wq_cyc *wq = &sq->wq;
1052         int err;
1053
1054         sq->channel   = c;
1055         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1056
1057         param->wq.db_numa_node = cpu_to_node(c->cpu);
1058         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1059         if (err)
1060                 return err;
1061         wq->db = &wq->db[MLX5_SND_DBR];
1062
1063         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1064         if (err)
1065                 goto err_sq_wq_destroy;
1066
1067         return 0;
1068
1069 err_sq_wq_destroy:
1070         mlx5_wq_destroy(&sq->wq_ctrl);
1071
1072         return err;
1073 }
1074
1075 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1076 {
1077         mlx5e_free_icosq_db(sq);
1078         mlx5_wq_destroy(&sq->wq_ctrl);
1079 }
1080
1081 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1082 {
1083         kvfree(sq->db.wqe_info);
1084         kvfree(sq->db.dma_fifo);
1085 }
1086
1087 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1088 {
1089         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1090         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1091
1092         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1093                                                    sizeof(*sq->db.dma_fifo)),
1094                                         GFP_KERNEL, numa);
1095         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1096                                                    sizeof(*sq->db.wqe_info)),
1097                                         GFP_KERNEL, numa);
1098         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1099                 mlx5e_free_txqsq_db(sq);
1100                 return -ENOMEM;
1101         }
1102
1103         sq->dma_fifo_mask = df_sz - 1;
1104
1105         return 0;
1106 }
1107
1108 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1109 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1110                              int txq_ix,
1111                              struct mlx5e_params *params,
1112                              struct mlx5e_sq_param *param,
1113                              struct mlx5e_txqsq *sq,
1114                              int tc)
1115 {
1116         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1117         struct mlx5_core_dev *mdev = c->mdev;
1118         struct mlx5_wq_cyc *wq = &sq->wq;
1119         int err;
1120
1121         sq->pdev      = c->pdev;
1122         sq->tstamp    = c->tstamp;
1123         sq->clock     = &mdev->clock;
1124         sq->mkey_be   = c->mkey_be;
1125         sq->channel   = c;
1126         sq->ch_ix     = c->ix;
1127         sq->txq_ix    = txq_ix;
1128         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1129         sq->min_inline_mode = params->tx_min_inline_mode;
1130         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1131         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1132         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1133         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1134                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1135         if (MLX5_IPSEC_DEV(c->priv->mdev))
1136                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1137         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1138                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1139                 sq->stop_room += MLX5E_SQ_TLS_ROOM;
1140         }
1141
1142         param->wq.db_numa_node = cpu_to_node(c->cpu);
1143         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1144         if (err)
1145                 return err;
1146         wq->db    = &wq->db[MLX5_SND_DBR];
1147
1148         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1149         if (err)
1150                 goto err_sq_wq_destroy;
1151
1152         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1153         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1154
1155         return 0;
1156
1157 err_sq_wq_destroy:
1158         mlx5_wq_destroy(&sq->wq_ctrl);
1159
1160         return err;
1161 }
1162
1163 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1164 {
1165         mlx5e_free_txqsq_db(sq);
1166         mlx5_wq_destroy(&sq->wq_ctrl);
1167 }
1168
1169 struct mlx5e_create_sq_param {
1170         struct mlx5_wq_ctrl        *wq_ctrl;
1171         u32                         cqn;
1172         u32                         tisn;
1173         u8                          tis_lst_sz;
1174         u8                          min_inline_mode;
1175 };
1176
1177 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1178                            struct mlx5e_sq_param *param,
1179                            struct mlx5e_create_sq_param *csp,
1180                            u32 *sqn)
1181 {
1182         void *in;
1183         void *sqc;
1184         void *wq;
1185         int inlen;
1186         int err;
1187
1188         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1189                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1190         in = kvzalloc(inlen, GFP_KERNEL);
1191         if (!in)
1192                 return -ENOMEM;
1193
1194         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1195         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1196
1197         memcpy(sqc, param->sqc, sizeof(param->sqc));
1198         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1199         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1200         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1201
1202         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1203                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1204
1205         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1206         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1207
1208         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1209         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1210         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1211                                           MLX5_ADAPTER_PAGE_SHIFT);
1212         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1213
1214         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1215                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1216
1217         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1218
1219         kvfree(in);
1220
1221         return err;
1222 }
1223
1224 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1225                     struct mlx5e_modify_sq_param *p)
1226 {
1227         void *in;
1228         void *sqc;
1229         int inlen;
1230         int err;
1231
1232         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1233         in = kvzalloc(inlen, GFP_KERNEL);
1234         if (!in)
1235                 return -ENOMEM;
1236
1237         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1238
1239         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1240         MLX5_SET(sqc, sqc, state, p->next_state);
1241         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1242                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1243                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1244         }
1245
1246         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1247
1248         kvfree(in);
1249
1250         return err;
1251 }
1252
1253 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1254 {
1255         mlx5_core_destroy_sq(mdev, sqn);
1256 }
1257
1258 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1259                                struct mlx5e_sq_param *param,
1260                                struct mlx5e_create_sq_param *csp,
1261                                u32 *sqn)
1262 {
1263         struct mlx5e_modify_sq_param msp = {0};
1264         int err;
1265
1266         err = mlx5e_create_sq(mdev, param, csp, sqn);
1267         if (err)
1268                 return err;
1269
1270         msp.curr_state = MLX5_SQC_STATE_RST;
1271         msp.next_state = MLX5_SQC_STATE_RDY;
1272         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1273         if (err)
1274                 mlx5e_destroy_sq(mdev, *sqn);
1275
1276         return err;
1277 }
1278
1279 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1280                                 struct mlx5e_txqsq *sq, u32 rate);
1281
1282 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1283                             u32 tisn,
1284                             int txq_ix,
1285                             struct mlx5e_params *params,
1286                             struct mlx5e_sq_param *param,
1287                             struct mlx5e_txqsq *sq,
1288                             int tc)
1289 {
1290         struct mlx5e_create_sq_param csp = {};
1291         u32 tx_rate;
1292         int err;
1293
1294         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1295         if (err)
1296                 return err;
1297
1298         csp.tisn            = tisn;
1299         csp.tis_lst_sz      = 1;
1300         csp.cqn             = sq->cq.mcq.cqn;
1301         csp.wq_ctrl         = &sq->wq_ctrl;
1302         csp.min_inline_mode = sq->min_inline_mode;
1303         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1304         if (err)
1305                 goto err_free_txqsq;
1306
1307         tx_rate = c->priv->tx_rates[sq->txq_ix];
1308         if (tx_rate)
1309                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1310
1311         if (params->tx_dim_enabled)
1312                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1313
1314         return 0;
1315
1316 err_free_txqsq:
1317         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1318         mlx5e_free_txqsq(sq);
1319
1320         return err;
1321 }
1322
1323 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1324 {
1325         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1326         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1327         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1328         netdev_tx_reset_queue(sq->txq);
1329         netif_tx_start_queue(sq->txq);
1330 }
1331
1332 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1333 {
1334         __netif_tx_lock_bh(txq);
1335         netif_tx_stop_queue(txq);
1336         __netif_tx_unlock_bh(txq);
1337 }
1338
1339 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1340 {
1341         struct mlx5e_channel *c = sq->channel;
1342         struct mlx5_wq_cyc *wq = &sq->wq;
1343
1344         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1345         /* prevent netif_tx_wake_queue */
1346         napi_synchronize(&c->napi);
1347
1348         mlx5e_tx_disable_queue(sq->txq);
1349
1350         /* last doorbell out, godspeed .. */
1351         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1352                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1353                 struct mlx5e_tx_wqe *nop;
1354
1355                 sq->db.wqe_info[pi].skb = NULL;
1356                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1357                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1358         }
1359 }
1360
1361 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1362 {
1363         struct mlx5e_channel *c = sq->channel;
1364         struct mlx5_core_dev *mdev = c->mdev;
1365         struct mlx5_rate_limit rl = {0};
1366
1367         cancel_work_sync(&sq->dim.work);
1368         cancel_work_sync(&sq->recover_work);
1369         mlx5e_destroy_sq(mdev, sq->sqn);
1370         if (sq->rate_limit) {
1371                 rl.rate = sq->rate_limit;
1372                 mlx5_rl_remove_rate(mdev, &rl);
1373         }
1374         mlx5e_free_txqsq_descs(sq);
1375         mlx5e_free_txqsq(sq);
1376 }
1377
1378 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1379 {
1380         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1381                                               recover_work);
1382
1383         mlx5e_tx_reporter_err_cqe(sq);
1384 }
1385
1386 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1387                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1388 {
1389         struct mlx5e_create_sq_param csp = {};
1390         int err;
1391
1392         err = mlx5e_alloc_icosq(c, param, sq);
1393         if (err)
1394                 return err;
1395
1396         csp.cqn             = sq->cq.mcq.cqn;
1397         csp.wq_ctrl         = &sq->wq_ctrl;
1398         csp.min_inline_mode = params->tx_min_inline_mode;
1399         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1400         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1401         if (err)
1402                 goto err_free_icosq;
1403
1404         return 0;
1405
1406 err_free_icosq:
1407         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1408         mlx5e_free_icosq(sq);
1409
1410         return err;
1411 }
1412
1413 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1414 {
1415         struct mlx5e_channel *c = sq->channel;
1416
1417         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1418         napi_synchronize(&c->napi);
1419
1420         mlx5e_destroy_sq(c->mdev, sq->sqn);
1421         mlx5e_free_icosq(sq);
1422 }
1423
1424 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1425                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1426                      struct mlx5e_xdpsq *sq, bool is_redirect)
1427 {
1428         struct mlx5e_create_sq_param csp = {};
1429         int err;
1430
1431         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1432         if (err)
1433                 return err;
1434
1435         csp.tis_lst_sz      = 1;
1436         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1437         csp.cqn             = sq->cq.mcq.cqn;
1438         csp.wq_ctrl         = &sq->wq_ctrl;
1439         csp.min_inline_mode = sq->min_inline_mode;
1440         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1441         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1442         if (err)
1443                 goto err_free_xdpsq;
1444
1445         mlx5e_set_xmit_fp(sq, param->is_mpw);
1446
1447         if (!param->is_mpw) {
1448                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1449                 unsigned int inline_hdr_sz = 0;
1450                 int i;
1451
1452                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1453                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1454                         ds_cnt++;
1455                 }
1456
1457                 /* Pre initialize fixed WQE fields */
1458                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1459                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1460                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1461                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1462                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1463                         struct mlx5_wqe_data_seg *dseg;
1464
1465                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1466                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1467
1468                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1469                         dseg->lkey = sq->mkey_be;
1470
1471                         wi->num_wqebbs = 1;
1472                         wi->num_pkts   = 1;
1473                 }
1474         }
1475
1476         return 0;
1477
1478 err_free_xdpsq:
1479         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1480         mlx5e_free_xdpsq(sq);
1481
1482         return err;
1483 }
1484
1485 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1486 {
1487         struct mlx5e_channel *c = sq->channel;
1488
1489         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1490         napi_synchronize(&c->napi);
1491
1492         mlx5e_destroy_sq(c->mdev, sq->sqn);
1493         mlx5e_free_xdpsq_descs(sq);
1494         mlx5e_free_xdpsq(sq);
1495 }
1496
1497 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1498                                  struct mlx5e_cq_param *param,
1499                                  struct mlx5e_cq *cq)
1500 {
1501         struct mlx5_core_cq *mcq = &cq->mcq;
1502         int eqn_not_used;
1503         unsigned int irqn;
1504         int err;
1505         u32 i;
1506
1507         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1508         if (err)
1509                 return err;
1510
1511         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1512                                &cq->wq_ctrl);
1513         if (err)
1514                 return err;
1515
1516         mcq->cqe_sz     = 64;
1517         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1518         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1519         *mcq->set_ci_db = 0;
1520         *mcq->arm_db    = 0;
1521         mcq->vector     = param->eq_ix;
1522         mcq->comp       = mlx5e_completion_event;
1523         mcq->event      = mlx5e_cq_error_event;
1524         mcq->irqn       = irqn;
1525
1526         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1527                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1528
1529                 cqe->op_own = 0xf1;
1530         }
1531
1532         cq->mdev = mdev;
1533
1534         return 0;
1535 }
1536
1537 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1538                           struct mlx5e_cq_param *param,
1539                           struct mlx5e_cq *cq)
1540 {
1541         struct mlx5_core_dev *mdev = c->priv->mdev;
1542         int err;
1543
1544         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1545         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1546         param->eq_ix   = c->ix;
1547
1548         err = mlx5e_alloc_cq_common(mdev, param, cq);
1549
1550         cq->napi    = &c->napi;
1551         cq->channel = c;
1552
1553         return err;
1554 }
1555
1556 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1557 {
1558         mlx5_wq_destroy(&cq->wq_ctrl);
1559 }
1560
1561 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1562 {
1563         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1564         struct mlx5_core_dev *mdev = cq->mdev;
1565         struct mlx5_core_cq *mcq = &cq->mcq;
1566
1567         void *in;
1568         void *cqc;
1569         int inlen;
1570         unsigned int irqn_not_used;
1571         int eqn;
1572         int err;
1573
1574         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1575         if (err)
1576                 return err;
1577
1578         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1579                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1580         in = kvzalloc(inlen, GFP_KERNEL);
1581         if (!in)
1582                 return -ENOMEM;
1583
1584         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1585
1586         memcpy(cqc, param->cqc, sizeof(param->cqc));
1587
1588         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1589                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1590
1591         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1592         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1593         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1594         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1595                                             MLX5_ADAPTER_PAGE_SHIFT);
1596         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1597
1598         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1599
1600         kvfree(in);
1601
1602         if (err)
1603                 return err;
1604
1605         mlx5e_cq_arm(cq);
1606
1607         return 0;
1608 }
1609
1610 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1611 {
1612         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1613 }
1614
1615 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1616                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1617 {
1618         struct mlx5_core_dev *mdev = c->mdev;
1619         int err;
1620
1621         err = mlx5e_alloc_cq(c, param, cq);
1622         if (err)
1623                 return err;
1624
1625         err = mlx5e_create_cq(cq, param);
1626         if (err)
1627                 goto err_free_cq;
1628
1629         if (MLX5_CAP_GEN(mdev, cq_moderation))
1630                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1631         return 0;
1632
1633 err_free_cq:
1634         mlx5e_free_cq(cq);
1635
1636         return err;
1637 }
1638
1639 void mlx5e_close_cq(struct mlx5e_cq *cq)
1640 {
1641         mlx5e_destroy_cq(cq);
1642         mlx5e_free_cq(cq);
1643 }
1644
1645 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1646                              struct mlx5e_params *params,
1647                              struct mlx5e_channel_param *cparam)
1648 {
1649         int err;
1650         int tc;
1651
1652         for (tc = 0; tc < c->num_tc; tc++) {
1653                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1654                                     &cparam->tx_cq, &c->sq[tc].cq);
1655                 if (err)
1656                         goto err_close_tx_cqs;
1657         }
1658
1659         return 0;
1660
1661 err_close_tx_cqs:
1662         for (tc--; tc >= 0; tc--)
1663                 mlx5e_close_cq(&c->sq[tc].cq);
1664
1665         return err;
1666 }
1667
1668 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1669 {
1670         int tc;
1671
1672         for (tc = 0; tc < c->num_tc; tc++)
1673                 mlx5e_close_cq(&c->sq[tc].cq);
1674 }
1675
1676 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1677                           struct mlx5e_params *params,
1678                           struct mlx5e_channel_param *cparam)
1679 {
1680         struct mlx5e_priv *priv = c->priv;
1681         int err, tc;
1682
1683         for (tc = 0; tc < params->num_tc; tc++) {
1684                 int txq_ix = c->ix + tc * priv->max_nch;
1685
1686                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1687                                        params, &cparam->sq, &c->sq[tc], tc);
1688                 if (err)
1689                         goto err_close_sqs;
1690         }
1691
1692         return 0;
1693
1694 err_close_sqs:
1695         for (tc--; tc >= 0; tc--)
1696                 mlx5e_close_txqsq(&c->sq[tc]);
1697
1698         return err;
1699 }
1700
1701 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1702 {
1703         int tc;
1704
1705         for (tc = 0; tc < c->num_tc; tc++)
1706                 mlx5e_close_txqsq(&c->sq[tc]);
1707 }
1708
1709 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1710                                 struct mlx5e_txqsq *sq, u32 rate)
1711 {
1712         struct mlx5e_priv *priv = netdev_priv(dev);
1713         struct mlx5_core_dev *mdev = priv->mdev;
1714         struct mlx5e_modify_sq_param msp = {0};
1715         struct mlx5_rate_limit rl = {0};
1716         u16 rl_index = 0;
1717         int err;
1718
1719         if (rate == sq->rate_limit)
1720                 /* nothing to do */
1721                 return 0;
1722
1723         if (sq->rate_limit) {
1724                 rl.rate = sq->rate_limit;
1725                 /* remove current rl index to free space to next ones */
1726                 mlx5_rl_remove_rate(mdev, &rl);
1727         }
1728
1729         sq->rate_limit = 0;
1730
1731         if (rate) {
1732                 rl.rate = rate;
1733                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1734                 if (err) {
1735                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1736                                    rate, err);
1737                         return err;
1738                 }
1739         }
1740
1741         msp.curr_state = MLX5_SQC_STATE_RDY;
1742         msp.next_state = MLX5_SQC_STATE_RDY;
1743         msp.rl_index   = rl_index;
1744         msp.rl_update  = true;
1745         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1746         if (err) {
1747                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1748                            rate, err);
1749                 /* remove the rate from the table */
1750                 if (rate)
1751                         mlx5_rl_remove_rate(mdev, &rl);
1752                 return err;
1753         }
1754
1755         sq->rate_limit = rate;
1756         return 0;
1757 }
1758
1759 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1760 {
1761         struct mlx5e_priv *priv = netdev_priv(dev);
1762         struct mlx5_core_dev *mdev = priv->mdev;
1763         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1764         int err = 0;
1765
1766         if (!mlx5_rl_is_supported(mdev)) {
1767                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1768                 return -EINVAL;
1769         }
1770
1771         /* rate is given in Mb/sec, HW config is in Kb/sec */
1772         rate = rate << 10;
1773
1774         /* Check whether rate in valid range, 0 is always valid */
1775         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1776                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1777                 return -ERANGE;
1778         }
1779
1780         mutex_lock(&priv->state_lock);
1781         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1782                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1783         if (!err)
1784                 priv->tx_rates[index] = rate;
1785         mutex_unlock(&priv->state_lock);
1786
1787         return err;
1788 }
1789
1790 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1791                                    struct mlx5e_params *params)
1792 {
1793         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1794         int irq;
1795
1796         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1797                 return -ENOMEM;
1798
1799         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1800                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1801
1802                 cpumask_set_cpu(cpu, c->xps_cpumask);
1803         }
1804
1805         return 0;
1806 }
1807
1808 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1809 {
1810         free_cpumask_var(c->xps_cpumask);
1811 }
1812
1813 static int mlx5e_open_queues(struct mlx5e_channel *c,
1814                              struct mlx5e_params *params,
1815                              struct mlx5e_channel_param *cparam)
1816 {
1817         struct dim_cq_moder icocq_moder = {0, 0};
1818         int err;
1819
1820         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1821         if (err)
1822                 return err;
1823
1824         err = mlx5e_open_tx_cqs(c, params, cparam);
1825         if (err)
1826                 goto err_close_icosq_cq;
1827
1828         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1829         if (err)
1830                 goto err_close_tx_cqs;
1831
1832         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1833         if (err)
1834                 goto err_close_xdp_tx_cqs;
1835
1836         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1837         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1838                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1839         if (err)
1840                 goto err_close_rx_cq;
1841
1842         napi_enable(&c->napi);
1843
1844         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1845         if (err)
1846                 goto err_disable_napi;
1847
1848         err = mlx5e_open_sqs(c, params, cparam);
1849         if (err)
1850                 goto err_close_icosq;
1851
1852         if (c->xdp) {
1853                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1854                                        &c->rq_xdpsq, false);
1855                 if (err)
1856                         goto err_close_sqs;
1857         }
1858
1859         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1860         if (err)
1861                 goto err_close_xdp_sq;
1862
1863         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1864         if (err)
1865                 goto err_close_rq;
1866
1867         return 0;
1868
1869 err_close_rq:
1870         mlx5e_close_rq(&c->rq);
1871
1872 err_close_xdp_sq:
1873         if (c->xdp)
1874                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1875
1876 err_close_sqs:
1877         mlx5e_close_sqs(c);
1878
1879 err_close_icosq:
1880         mlx5e_close_icosq(&c->icosq);
1881
1882 err_disable_napi:
1883         napi_disable(&c->napi);
1884
1885         if (c->xdp)
1886                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1887
1888 err_close_rx_cq:
1889         mlx5e_close_cq(&c->rq.cq);
1890
1891 err_close_xdp_tx_cqs:
1892         mlx5e_close_cq(&c->xdpsq.cq);
1893
1894 err_close_tx_cqs:
1895         mlx5e_close_tx_cqs(c);
1896
1897 err_close_icosq_cq:
1898         mlx5e_close_cq(&c->icosq.cq);
1899
1900         return err;
1901 }
1902
1903 static void mlx5e_close_queues(struct mlx5e_channel *c)
1904 {
1905         mlx5e_close_xdpsq(&c->xdpsq);
1906         mlx5e_close_rq(&c->rq);
1907         if (c->xdp)
1908                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1909         mlx5e_close_sqs(c);
1910         mlx5e_close_icosq(&c->icosq);
1911         napi_disable(&c->napi);
1912         if (c->xdp)
1913                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1914         mlx5e_close_cq(&c->rq.cq);
1915         mlx5e_close_cq(&c->xdpsq.cq);
1916         mlx5e_close_tx_cqs(c);
1917         mlx5e_close_cq(&c->icosq.cq);
1918 }
1919
1920 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1921                               struct mlx5e_params *params,
1922                               struct mlx5e_channel_param *cparam,
1923                               struct xdp_umem *umem,
1924                               struct mlx5e_channel **cp)
1925 {
1926         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1927         struct net_device *netdev = priv->netdev;
1928         struct mlx5e_xsk_param xsk;
1929         struct mlx5e_channel *c;
1930         unsigned int irq;
1931         int err;
1932         int eqn;
1933
1934         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1935         if (err)
1936                 return err;
1937
1938         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1939         if (!c)
1940                 return -ENOMEM;
1941
1942         c->priv     = priv;
1943         c->mdev     = priv->mdev;
1944         c->tstamp   = &priv->tstamp;
1945         c->ix       = ix;
1946         c->cpu      = cpu;
1947         c->pdev     = priv->mdev->device;
1948         c->netdev   = priv->netdev;
1949         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1950         c->num_tc   = params->num_tc;
1951         c->xdp      = !!params->xdp_prog;
1952         c->stats    = &priv->channel_stats[ix].ch;
1953         c->irq_desc = irq_to_desc(irq);
1954
1955         err = mlx5e_alloc_xps_cpumask(c, params);
1956         if (err)
1957                 goto err_free_channel;
1958
1959         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1960
1961         err = mlx5e_open_queues(c, params, cparam);
1962         if (unlikely(err))
1963                 goto err_napi_del;
1964
1965         if (umem) {
1966                 mlx5e_build_xsk_param(umem, &xsk);
1967                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1968                 if (unlikely(err))
1969                         goto err_close_queues;
1970         }
1971
1972         *cp = c;
1973
1974         return 0;
1975
1976 err_close_queues:
1977         mlx5e_close_queues(c);
1978
1979 err_napi_del:
1980         netif_napi_del(&c->napi);
1981         mlx5e_free_xps_cpumask(c);
1982
1983 err_free_channel:
1984         kvfree(c);
1985
1986         return err;
1987 }
1988
1989 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1990 {
1991         int tc;
1992
1993         for (tc = 0; tc < c->num_tc; tc++)
1994                 mlx5e_activate_txqsq(&c->sq[tc]);
1995         mlx5e_activate_rq(&c->rq);
1996         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
1997
1998         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
1999                 mlx5e_activate_xsk(c);
2000 }
2001
2002 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2003 {
2004         int tc;
2005
2006         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2007                 mlx5e_deactivate_xsk(c);
2008
2009         mlx5e_deactivate_rq(&c->rq);
2010         for (tc = 0; tc < c->num_tc; tc++)
2011                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2012 }
2013
2014 static void mlx5e_close_channel(struct mlx5e_channel *c)
2015 {
2016         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2017                 mlx5e_close_xsk(c);
2018         mlx5e_close_queues(c);
2019         netif_napi_del(&c->napi);
2020         mlx5e_free_xps_cpumask(c);
2021
2022         kvfree(c);
2023 }
2024
2025 #define DEFAULT_FRAG_SIZE (2048)
2026
2027 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2028                                       struct mlx5e_params *params,
2029                                       struct mlx5e_xsk_param *xsk,
2030                                       struct mlx5e_rq_frags_info *info)
2031 {
2032         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2033         int frag_size_max = DEFAULT_FRAG_SIZE;
2034         u32 buf_size = 0;
2035         int i;
2036
2037 #ifdef CONFIG_MLX5_EN_IPSEC
2038         if (MLX5_IPSEC_DEV(mdev))
2039                 byte_count += MLX5E_METADATA_ETHER_LEN;
2040 #endif
2041
2042         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2043                 int frag_stride;
2044
2045                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2046                 frag_stride = roundup_pow_of_two(frag_stride);
2047
2048                 info->arr[0].frag_size = byte_count;
2049                 info->arr[0].frag_stride = frag_stride;
2050                 info->num_frags = 1;
2051                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2052                 goto out;
2053         }
2054
2055         if (byte_count > PAGE_SIZE +
2056             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2057                 frag_size_max = PAGE_SIZE;
2058
2059         i = 0;
2060         while (buf_size < byte_count) {
2061                 int frag_size = byte_count - buf_size;
2062
2063                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2064                         frag_size = min(frag_size, frag_size_max);
2065
2066                 info->arr[i].frag_size = frag_size;
2067                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2068
2069                 buf_size += frag_size;
2070                 i++;
2071         }
2072         info->num_frags = i;
2073         /* number of different wqes sharing a page */
2074         info->wqe_bulk = 1 + (info->num_frags % 2);
2075
2076 out:
2077         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2078         info->log_num_frags = order_base_2(info->num_frags);
2079 }
2080
2081 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2082 {
2083         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2084
2085         switch (wq_type) {
2086         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2087                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2088                 break;
2089         default: /* MLX5_WQ_TYPE_CYCLIC */
2090                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2091         }
2092
2093         return order_base_2(sz);
2094 }
2095
2096 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2097 {
2098         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2099
2100         return MLX5_GET(wq, wq, log_wq_sz);
2101 }
2102
2103 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2104                           struct mlx5e_params *params,
2105                           struct mlx5e_xsk_param *xsk,
2106                           struct mlx5e_rq_param *param)
2107 {
2108         struct mlx5_core_dev *mdev = priv->mdev;
2109         void *rqc = param->rqc;
2110         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2111         int ndsegs = 1;
2112
2113         switch (params->rq_wq_type) {
2114         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2115                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2116                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2117                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2118                 MLX5_SET(wq, wq, log_wqe_stride_size,
2119                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2120                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2121                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2122                 break;
2123         default: /* MLX5_WQ_TYPE_CYCLIC */
2124                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2125                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2126                 ndsegs = param->frags_info.num_frags;
2127         }
2128
2129         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2130         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2131         MLX5_SET(wq, wq, log_wq_stride,
2132                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2133         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2134         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2135         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2136         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2137
2138         param->wq.buf_numa_node = dev_to_node(mdev->device);
2139 }
2140
2141 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2142                                       struct mlx5e_rq_param *param)
2143 {
2144         struct mlx5_core_dev *mdev = priv->mdev;
2145         void *rqc = param->rqc;
2146         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2147
2148         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2149         MLX5_SET(wq, wq, log_wq_stride,
2150                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2151         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2152
2153         param->wq.buf_numa_node = dev_to_node(mdev->device);
2154 }
2155
2156 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2157                                  struct mlx5e_sq_param *param)
2158 {
2159         void *sqc = param->sqc;
2160         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2161
2162         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2163         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2164
2165         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2166 }
2167
2168 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2169                                  struct mlx5e_params *params,
2170                                  struct mlx5e_sq_param *param)
2171 {
2172         void *sqc = param->sqc;
2173         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2174         bool allow_swp;
2175
2176         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2177                     !!MLX5_IPSEC_DEV(priv->mdev);
2178         mlx5e_build_sq_param_common(priv, param);
2179         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2180         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2181 }
2182
2183 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2184                                         struct mlx5e_cq_param *param)
2185 {
2186         void *cqc = param->cqc;
2187
2188         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2189         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2190                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2191 }
2192
2193 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2194                              struct mlx5e_params *params,
2195                              struct mlx5e_xsk_param *xsk,
2196                              struct mlx5e_cq_param *param)
2197 {
2198         struct mlx5_core_dev *mdev = priv->mdev;
2199         void *cqc = param->cqc;
2200         u8 log_cq_size;
2201
2202         switch (params->rq_wq_type) {
2203         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2204                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2205                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2206                 break;
2207         default: /* MLX5_WQ_TYPE_CYCLIC */
2208                 log_cq_size = params->log_rq_mtu_frames;
2209         }
2210
2211         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2212         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2213                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2214                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2215         }
2216
2217         mlx5e_build_common_cq_param(priv, param);
2218         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2219 }
2220
2221 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2222                              struct mlx5e_params *params,
2223                              struct mlx5e_cq_param *param)
2224 {
2225         void *cqc = param->cqc;
2226
2227         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2228
2229         mlx5e_build_common_cq_param(priv, param);
2230         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2231 }
2232
2233 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2234                               u8 log_wq_size,
2235                               struct mlx5e_cq_param *param)
2236 {
2237         void *cqc = param->cqc;
2238
2239         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2240
2241         mlx5e_build_common_cq_param(priv, param);
2242
2243         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2244 }
2245
2246 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2247                              u8 log_wq_size,
2248                              struct mlx5e_sq_param *param)
2249 {
2250         void *sqc = param->sqc;
2251         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2252
2253         mlx5e_build_sq_param_common(priv, param);
2254
2255         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2256         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2257 }
2258
2259 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2260                              struct mlx5e_params *params,
2261                              struct mlx5e_sq_param *param)
2262 {
2263         void *sqc = param->sqc;
2264         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2265
2266         mlx5e_build_sq_param_common(priv, param);
2267         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2268         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2269 }
2270
2271 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2272                                       struct mlx5e_rq_param *rqp)
2273 {
2274         switch (params->rq_wq_type) {
2275         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2276                 return order_base_2(MLX5E_UMR_WQEBBS) +
2277                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2278         default: /* MLX5_WQ_TYPE_CYCLIC */
2279                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2280         }
2281 }
2282
2283 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2284                                       struct mlx5e_params *params,
2285                                       struct mlx5e_channel_param *cparam)
2286 {
2287         u8 icosq_log_wq_sz;
2288
2289         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2290
2291         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2292
2293         mlx5e_build_sq_param(priv, params, &cparam->sq);
2294         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2295         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2296         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2297         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2298         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2299 }
2300
2301 int mlx5e_open_channels(struct mlx5e_priv *priv,
2302                         struct mlx5e_channels *chs)
2303 {
2304         struct mlx5e_channel_param *cparam;
2305         int err = -ENOMEM;
2306         int i;
2307
2308         chs->num = chs->params.num_channels;
2309
2310         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2311         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2312         if (!chs->c || !cparam)
2313                 goto err_free;
2314
2315         mlx5e_build_channel_param(priv, &chs->params, cparam);
2316         for (i = 0; i < chs->num; i++) {
2317                 struct xdp_umem *umem = NULL;
2318
2319                 if (chs->params.xdp_prog)
2320                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2321
2322                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2323                 if (err)
2324                         goto err_close_channels;
2325         }
2326
2327         if (priv->tx_reporter)
2328                 devlink_health_reporter_state_update(priv->tx_reporter,
2329                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2330
2331         kvfree(cparam);
2332         return 0;
2333
2334 err_close_channels:
2335         for (i--; i >= 0; i--)
2336                 mlx5e_close_channel(chs->c[i]);
2337
2338 err_free:
2339         kfree(chs->c);
2340         kvfree(cparam);
2341         chs->num = 0;
2342         return err;
2343 }
2344
2345 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2346 {
2347         int i;
2348
2349         for (i = 0; i < chs->num; i++)
2350                 mlx5e_activate_channel(chs->c[i]);
2351 }
2352
2353 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2354
2355 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2356 {
2357         int err = 0;
2358         int i;
2359
2360         for (i = 0; i < chs->num; i++) {
2361                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2362
2363                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2364
2365                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2366                  * doesn't provide any Fill Ring entries at the setup stage.
2367                  */
2368         }
2369
2370         return err ? -ETIMEDOUT : 0;
2371 }
2372
2373 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2374 {
2375         int i;
2376
2377         for (i = 0; i < chs->num; i++)
2378                 mlx5e_deactivate_channel(chs->c[i]);
2379 }
2380
2381 void mlx5e_close_channels(struct mlx5e_channels *chs)
2382 {
2383         int i;
2384
2385         for (i = 0; i < chs->num; i++)
2386                 mlx5e_close_channel(chs->c[i]);
2387
2388         kfree(chs->c);
2389         chs->num = 0;
2390 }
2391
2392 static int
2393 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2394 {
2395         struct mlx5_core_dev *mdev = priv->mdev;
2396         void *rqtc;
2397         int inlen;
2398         int err;
2399         u32 *in;
2400         int i;
2401
2402         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2403         in = kvzalloc(inlen, GFP_KERNEL);
2404         if (!in)
2405                 return -ENOMEM;
2406
2407         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2408
2409         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2410         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2411
2412         for (i = 0; i < sz; i++)
2413                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2414
2415         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2416         if (!err)
2417                 rqt->enabled = true;
2418
2419         kvfree(in);
2420         return err;
2421 }
2422
2423 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2424 {
2425         rqt->enabled = false;
2426         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2427 }
2428
2429 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2430 {
2431         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2432         int err;
2433
2434         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2435         if (err)
2436                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2437         return err;
2438 }
2439
2440 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2441 {
2442         int err;
2443         int ix;
2444
2445         for (ix = 0; ix < priv->max_nch; ix++) {
2446                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2447                 if (unlikely(err))
2448                         goto err_destroy_rqts;
2449         }
2450
2451         return 0;
2452
2453 err_destroy_rqts:
2454         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2455         for (ix--; ix >= 0; ix--)
2456                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2457
2458         return err;
2459 }
2460
2461 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2462 {
2463         int i;
2464
2465         for (i = 0; i < priv->max_nch; i++)
2466                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2467 }
2468
2469 static int mlx5e_rx_hash_fn(int hfunc)
2470 {
2471         return (hfunc == ETH_RSS_HASH_TOP) ?
2472                MLX5_RX_HASH_FN_TOEPLITZ :
2473                MLX5_RX_HASH_FN_INVERTED_XOR8;
2474 }
2475
2476 int mlx5e_bits_invert(unsigned long a, int size)
2477 {
2478         int inv = 0;
2479         int i;
2480
2481         for (i = 0; i < size; i++)
2482                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2483
2484         return inv;
2485 }
2486
2487 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2488                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2489 {
2490         int i;
2491
2492         for (i = 0; i < sz; i++) {
2493                 u32 rqn;
2494
2495                 if (rrp.is_rss) {
2496                         int ix = i;
2497
2498                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2499                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2500
2501                         ix = priv->rss_params.indirection_rqt[ix];
2502                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2503                 } else {
2504                         rqn = rrp.rqn;
2505                 }
2506                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2507         }
2508 }
2509
2510 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2511                        struct mlx5e_redirect_rqt_param rrp)
2512 {
2513         struct mlx5_core_dev *mdev = priv->mdev;
2514         void *rqtc;
2515         int inlen;
2516         u32 *in;
2517         int err;
2518
2519         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2520         in = kvzalloc(inlen, GFP_KERNEL);
2521         if (!in)
2522                 return -ENOMEM;
2523
2524         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2525
2526         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2527         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2528         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2529         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2530
2531         kvfree(in);
2532         return err;
2533 }
2534
2535 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2536                                 struct mlx5e_redirect_rqt_param rrp)
2537 {
2538         if (!rrp.is_rss)
2539                 return rrp.rqn;
2540
2541         if (ix >= rrp.rss.channels->num)
2542                 return priv->drop_rq.rqn;
2543
2544         return rrp.rss.channels->c[ix]->rq.rqn;
2545 }
2546
2547 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2548                                 struct mlx5e_redirect_rqt_param rrp)
2549 {
2550         u32 rqtn;
2551         int ix;
2552
2553         if (priv->indir_rqt.enabled) {
2554                 /* RSS RQ table */
2555                 rqtn = priv->indir_rqt.rqtn;
2556                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2557         }
2558
2559         for (ix = 0; ix < priv->max_nch; ix++) {
2560                 struct mlx5e_redirect_rqt_param direct_rrp = {
2561                         .is_rss = false,
2562                         {
2563                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2564                         },
2565                 };
2566
2567                 /* Direct RQ Tables */
2568                 if (!priv->direct_tir[ix].rqt.enabled)
2569                         continue;
2570
2571                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2572                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2573         }
2574 }
2575
2576 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2577                                             struct mlx5e_channels *chs)
2578 {
2579         struct mlx5e_redirect_rqt_param rrp = {
2580                 .is_rss        = true,
2581                 {
2582                         .rss = {
2583                                 .channels  = chs,
2584                                 .hfunc     = priv->rss_params.hfunc,
2585                         }
2586                 },
2587         };
2588
2589         mlx5e_redirect_rqts(priv, rrp);
2590 }
2591
2592 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2593 {
2594         struct mlx5e_redirect_rqt_param drop_rrp = {
2595                 .is_rss = false,
2596                 {
2597                         .rqn = priv->drop_rq.rqn,
2598                 },
2599         };
2600
2601         mlx5e_redirect_rqts(priv, drop_rrp);
2602 }
2603
2604 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2605         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2606                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2607                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2608         },
2609         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2610                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2611                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2612         },
2613         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2614                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2615                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2616         },
2617         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2618                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2619                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2620         },
2621         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2622                                      .l4_prot_type = 0,
2623                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2624         },
2625         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2626                                      .l4_prot_type = 0,
2627                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2628         },
2629         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2630                                       .l4_prot_type = 0,
2631                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2632         },
2633         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2634                                       .l4_prot_type = 0,
2635                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2636         },
2637         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2638                             .l4_prot_type = 0,
2639                             .rx_hash_fields = MLX5_HASH_IP,
2640         },
2641         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2642                             .l4_prot_type = 0,
2643                             .rx_hash_fields = MLX5_HASH_IP,
2644         },
2645 };
2646
2647 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2648 {
2649         return tirc_default_config[tt];
2650 }
2651
2652 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2653 {
2654         if (!params->lro_en)
2655                 return;
2656
2657 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2658
2659         MLX5_SET(tirc, tirc, lro_enable_mask,
2660                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2661                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2662         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2663                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2664         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2665 }
2666
2667 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2668                                     const struct mlx5e_tirc_config *ttconfig,
2669                                     void *tirc, bool inner)
2670 {
2671         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2672                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2673
2674         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2675         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2676                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2677                                              rx_hash_toeplitz_key);
2678                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2679                                                rx_hash_toeplitz_key);
2680
2681                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2682                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2683         }
2684         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2685                  ttconfig->l3_prot_type);
2686         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2687                  ttconfig->l4_prot_type);
2688         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2689                  ttconfig->rx_hash_fields);
2690 }
2691
2692 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2693                                         enum mlx5e_traffic_types tt,
2694                                         u32 rx_hash_fields)
2695 {
2696         *ttconfig                = tirc_default_config[tt];
2697         ttconfig->rx_hash_fields = rx_hash_fields;
2698 }
2699
2700 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2701 {
2702         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2703         struct mlx5e_rss_params *rss = &priv->rss_params;
2704         struct mlx5_core_dev *mdev = priv->mdev;
2705         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2706         struct mlx5e_tirc_config ttconfig;
2707         int tt;
2708
2709         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2710
2711         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2712                 memset(tirc, 0, ctxlen);
2713                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2714                                             rss->rx_hash_fields[tt]);
2715                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2716                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2717         }
2718
2719         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2720                 return;
2721
2722         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2723                 memset(tirc, 0, ctxlen);
2724                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2725                                             rss->rx_hash_fields[tt]);
2726                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2727                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2728                                      inlen);
2729         }
2730 }
2731
2732 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2733 {
2734         struct mlx5_core_dev *mdev = priv->mdev;
2735
2736         void *in;
2737         void *tirc;
2738         int inlen;
2739         int err;
2740         int tt;
2741         int ix;
2742
2743         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2744         in = kvzalloc(inlen, GFP_KERNEL);
2745         if (!in)
2746                 return -ENOMEM;
2747
2748         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2749         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2750
2751         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2752
2753         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2754                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2755                                            inlen);
2756                 if (err)
2757                         goto free_in;
2758         }
2759
2760         for (ix = 0; ix < priv->max_nch; ix++) {
2761                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2762                                            in, inlen);
2763                 if (err)
2764                         goto free_in;
2765         }
2766
2767 free_in:
2768         kvfree(in);
2769
2770         return err;
2771 }
2772
2773 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2774                          struct mlx5e_params *params, u16 mtu)
2775 {
2776         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2777         int err;
2778
2779         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2780         if (err)
2781                 return err;
2782
2783         /* Update vport context MTU */
2784         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2785         return 0;
2786 }
2787
2788 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2789                             struct mlx5e_params *params, u16 *mtu)
2790 {
2791         u16 hw_mtu = 0;
2792         int err;
2793
2794         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2795         if (err || !hw_mtu) /* fallback to port oper mtu */
2796                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2797
2798         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2799 }
2800
2801 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2802 {
2803         struct mlx5e_params *params = &priv->channels.params;
2804         struct net_device *netdev = priv->netdev;
2805         struct mlx5_core_dev *mdev = priv->mdev;
2806         u16 mtu;
2807         int err;
2808
2809         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2810         if (err)
2811                 return err;
2812
2813         mlx5e_query_mtu(mdev, params, &mtu);
2814         if (mtu != params->sw_mtu)
2815                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2816                             __func__, mtu, params->sw_mtu);
2817
2818         params->sw_mtu = mtu;
2819         return 0;
2820 }
2821
2822 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2823 {
2824         struct mlx5e_params *params = &priv->channels.params;
2825         struct net_device *netdev   = priv->netdev;
2826         struct mlx5_core_dev *mdev  = priv->mdev;
2827         u16 max_mtu;
2828
2829         /* MTU range: 68 - hw-specific max */
2830         netdev->min_mtu = ETH_MIN_MTU;
2831
2832         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2833         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2834                                 ETH_MAX_MTU);
2835 }
2836
2837 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2838 {
2839         struct mlx5e_priv *priv = netdev_priv(netdev);
2840         int nch = priv->channels.params.num_channels;
2841         int ntc = priv->channels.params.num_tc;
2842         int tc;
2843
2844         netdev_reset_tc(netdev);
2845
2846         if (ntc == 1)
2847                 return;
2848
2849         netdev_set_num_tc(netdev, ntc);
2850
2851         /* Map netdev TCs to offset 0
2852          * We have our own UP to TXQ mapping for QoS
2853          */
2854         for (tc = 0; tc < ntc; tc++)
2855                 netdev_set_tc_queue(netdev, tc, nch, 0);
2856 }
2857
2858 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2859 {
2860         int i, tc;
2861
2862         for (i = 0; i < priv->max_nch; i++)
2863                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2864                         priv->channel_tc2txq[i][tc] = i + tc * priv->max_nch;
2865 }
2866
2867 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2868 {
2869         struct mlx5e_channel *c;
2870         struct mlx5e_txqsq *sq;
2871         int i, tc;
2872
2873         for (i = 0; i < priv->channels.num; i++) {
2874                 c = priv->channels.c[i];
2875                 for (tc = 0; tc < c->num_tc; tc++) {
2876                         sq = &c->sq[tc];
2877                         priv->txq2sq[sq->txq_ix] = sq;
2878                 }
2879         }
2880 }
2881
2882 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2883 {
2884         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2885         int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2886         struct net_device *netdev = priv->netdev;
2887
2888         mlx5e_netdev_set_tcs(netdev);
2889         netif_set_real_num_tx_queues(netdev, num_txqs);
2890         netif_set_real_num_rx_queues(netdev, num_rxqs);
2891
2892         mlx5e_build_tx2sq_maps(priv);
2893         mlx5e_activate_channels(&priv->channels);
2894         mlx5e_xdp_tx_enable(priv);
2895         netif_tx_start_all_queues(priv->netdev);
2896
2897         if (mlx5e_is_vport_rep(priv))
2898                 mlx5e_add_sqs_fwd_rules(priv);
2899
2900         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2901         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2902
2903         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2904 }
2905
2906 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2907 {
2908         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2909
2910         mlx5e_redirect_rqts_to_drop(priv);
2911
2912         if (mlx5e_is_vport_rep(priv))
2913                 mlx5e_remove_sqs_fwd_rules(priv);
2914
2915         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2916          * polling for inactive tx queues.
2917          */
2918         netif_tx_stop_all_queues(priv->netdev);
2919         netif_tx_disable(priv->netdev);
2920         mlx5e_xdp_tx_disable(priv);
2921         mlx5e_deactivate_channels(&priv->channels);
2922 }
2923
2924 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2925                                        struct mlx5e_channels *new_chs,
2926                                        mlx5e_fp_hw_modify hw_modify)
2927 {
2928         struct net_device *netdev = priv->netdev;
2929         int new_num_txqs;
2930         int carrier_ok;
2931
2932         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2933
2934         carrier_ok = netif_carrier_ok(netdev);
2935         netif_carrier_off(netdev);
2936
2937         if (new_num_txqs < netdev->real_num_tx_queues)
2938                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2939
2940         mlx5e_deactivate_priv_channels(priv);
2941         mlx5e_close_channels(&priv->channels);
2942
2943         priv->channels = *new_chs;
2944
2945         /* New channels are ready to roll, modify HW settings if needed */
2946         if (hw_modify)
2947                 hw_modify(priv);
2948
2949         priv->profile->update_rx(priv);
2950         mlx5e_activate_priv_channels(priv);
2951
2952         /* return carrier back if needed */
2953         if (carrier_ok)
2954                 netif_carrier_on(netdev);
2955 }
2956
2957 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2958                                struct mlx5e_channels *new_chs,
2959                                mlx5e_fp_hw_modify hw_modify)
2960 {
2961         int err;
2962
2963         err = mlx5e_open_channels(priv, new_chs);
2964         if (err)
2965                 return err;
2966
2967         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2968         return 0;
2969 }
2970
2971 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2972 {
2973         struct mlx5e_channels new_channels = {};
2974
2975         new_channels.params = priv->channels.params;
2976         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2977 }
2978
2979 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2980 {
2981         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2982         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2983 }
2984
2985 int mlx5e_open_locked(struct net_device *netdev)
2986 {
2987         struct mlx5e_priv *priv = netdev_priv(netdev);
2988         bool is_xdp = priv->channels.params.xdp_prog;
2989         int err;
2990
2991         set_bit(MLX5E_STATE_OPENED, &priv->state);
2992         if (is_xdp)
2993                 mlx5e_xdp_set_open(priv);
2994
2995         err = mlx5e_open_channels(priv, &priv->channels);
2996         if (err)
2997                 goto err_clear_state_opened_flag;
2998
2999         priv->profile->update_rx(priv);
3000         mlx5e_activate_priv_channels(priv);
3001         if (priv->profile->update_carrier)
3002                 priv->profile->update_carrier(priv);
3003
3004         mlx5e_queue_update_stats(priv);
3005         return 0;
3006
3007 err_clear_state_opened_flag:
3008         if (is_xdp)
3009                 mlx5e_xdp_set_closed(priv);
3010         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3011         return err;
3012 }
3013
3014 int mlx5e_open(struct net_device *netdev)
3015 {
3016         struct mlx5e_priv *priv = netdev_priv(netdev);
3017         int err;
3018
3019         mutex_lock(&priv->state_lock);
3020         err = mlx5e_open_locked(netdev);
3021         if (!err)
3022                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3023         mutex_unlock(&priv->state_lock);
3024
3025         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3026                 udp_tunnel_get_rx_info(netdev);
3027
3028         return err;
3029 }
3030
3031 int mlx5e_close_locked(struct net_device *netdev)
3032 {
3033         struct mlx5e_priv *priv = netdev_priv(netdev);
3034
3035         /* May already be CLOSED in case a previous configuration operation
3036          * (e.g RX/TX queue size change) that involves close&open failed.
3037          */
3038         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3039                 return 0;
3040
3041         if (priv->channels.params.xdp_prog)
3042                 mlx5e_xdp_set_closed(priv);
3043         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3044
3045         netif_carrier_off(priv->netdev);
3046         mlx5e_deactivate_priv_channels(priv);
3047         mlx5e_close_channels(&priv->channels);
3048
3049         return 0;
3050 }
3051
3052 int mlx5e_close(struct net_device *netdev)
3053 {
3054         struct mlx5e_priv *priv = netdev_priv(netdev);
3055         int err;
3056
3057         if (!netif_device_present(netdev))
3058                 return -ENODEV;
3059
3060         mutex_lock(&priv->state_lock);
3061         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3062         err = mlx5e_close_locked(netdev);
3063         mutex_unlock(&priv->state_lock);
3064
3065         return err;
3066 }
3067
3068 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3069                                struct mlx5e_rq *rq,
3070                                struct mlx5e_rq_param *param)
3071 {
3072         void *rqc = param->rqc;
3073         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3074         int err;
3075
3076         param->wq.db_numa_node = param->wq.buf_numa_node;
3077
3078         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3079                                  &rq->wq_ctrl);
3080         if (err)
3081                 return err;
3082
3083         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3084         xdp_rxq_info_unused(&rq->xdp_rxq);
3085
3086         rq->mdev = mdev;
3087
3088         return 0;
3089 }
3090
3091 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3092                                struct mlx5e_cq *cq,
3093                                struct mlx5e_cq_param *param)
3094 {
3095         param->wq.buf_numa_node = dev_to_node(mdev->device);
3096         param->wq.db_numa_node  = dev_to_node(mdev->device);
3097
3098         return mlx5e_alloc_cq_common(mdev, param, cq);
3099 }
3100
3101 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3102                        struct mlx5e_rq *drop_rq)
3103 {
3104         struct mlx5_core_dev *mdev = priv->mdev;
3105         struct mlx5e_cq_param cq_param = {};
3106         struct mlx5e_rq_param rq_param = {};
3107         struct mlx5e_cq *cq = &drop_rq->cq;
3108         int err;
3109
3110         mlx5e_build_drop_rq_param(priv, &rq_param);
3111
3112         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3113         if (err)
3114                 return err;
3115
3116         err = mlx5e_create_cq(cq, &cq_param);
3117         if (err)
3118                 goto err_free_cq;
3119
3120         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3121         if (err)
3122                 goto err_destroy_cq;
3123
3124         err = mlx5e_create_rq(drop_rq, &rq_param);
3125         if (err)
3126                 goto err_free_rq;
3127
3128         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3129         if (err)
3130                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3131
3132         return 0;
3133
3134 err_free_rq:
3135         mlx5e_free_rq(drop_rq);
3136
3137 err_destroy_cq:
3138         mlx5e_destroy_cq(cq);
3139
3140 err_free_cq:
3141         mlx5e_free_cq(cq);
3142
3143         return err;
3144 }
3145
3146 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3147 {
3148         mlx5e_destroy_rq(drop_rq);
3149         mlx5e_free_rq(drop_rq);
3150         mlx5e_destroy_cq(&drop_rq->cq);
3151         mlx5e_free_cq(&drop_rq->cq);
3152 }
3153
3154 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3155 {
3156         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3157
3158         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3159
3160         if (MLX5_GET(tisc, tisc, tls_en))
3161                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3162
3163         if (mlx5_lag_is_lacp_owner(mdev))
3164                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3165
3166         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3167 }
3168
3169 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3170 {
3171         mlx5_core_destroy_tis(mdev, tisn);
3172 }
3173
3174 int mlx5e_create_tises(struct mlx5e_priv *priv)
3175 {
3176         int err;
3177         int tc;
3178
3179         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3180                 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3181                 void *tisc;
3182
3183                 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3184
3185                 MLX5_SET(tisc, tisc, prio, tc << 1);
3186
3187                 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[tc]);
3188                 if (err)
3189                         goto err_close_tises;
3190         }
3191
3192         return 0;
3193
3194 err_close_tises:
3195         for (tc--; tc >= 0; tc--)
3196                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3197
3198         return err;
3199 }
3200
3201 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3202 {
3203         int tc;
3204
3205         mlx5e_tx_reporter_destroy(priv);
3206         for (tc = 0; tc < priv->profile->max_tc; tc++)
3207                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3208 }
3209
3210 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3211                                              u32 rqtn, u32 *tirc)
3212 {
3213         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3214         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3215         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3216         MLX5_SET(tirc, tirc, tunneled_offload_en,
3217                  priv->channels.params.tunneled_offload_en);
3218
3219         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3220 }
3221
3222 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3223                                       enum mlx5e_traffic_types tt,
3224                                       u32 *tirc)
3225 {
3226         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3227         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3228                                        &tirc_default_config[tt], tirc, false);
3229 }
3230
3231 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3232 {
3233         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3234         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3235 }
3236
3237 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3238                                             enum mlx5e_traffic_types tt,
3239                                             u32 *tirc)
3240 {
3241         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3242         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3243                                        &tirc_default_config[tt], tirc, true);
3244 }
3245
3246 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3247 {
3248         struct mlx5e_tir *tir;
3249         void *tirc;
3250         int inlen;
3251         int i = 0;
3252         int err;
3253         u32 *in;
3254         int tt;
3255
3256         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3257         in = kvzalloc(inlen, GFP_KERNEL);
3258         if (!in)
3259                 return -ENOMEM;
3260
3261         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3262                 memset(in, 0, inlen);
3263                 tir = &priv->indir_tir[tt];
3264                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3265                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3266                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3267                 if (err) {
3268                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3269                         goto err_destroy_inner_tirs;
3270                 }
3271         }
3272
3273         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3274                 goto out;
3275
3276         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3277                 memset(in, 0, inlen);
3278                 tir = &priv->inner_indir_tir[i];
3279                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3280                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3281                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3282                 if (err) {
3283                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3284                         goto err_destroy_inner_tirs;
3285                 }
3286         }
3287
3288 out:
3289         kvfree(in);
3290
3291         return 0;
3292
3293 err_destroy_inner_tirs:
3294         for (i--; i >= 0; i--)
3295                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3296
3297         for (tt--; tt >= 0; tt--)
3298                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3299
3300         kvfree(in);
3301
3302         return err;
3303 }
3304
3305 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3306 {
3307         struct mlx5e_tir *tir;
3308         void *tirc;
3309         int inlen;
3310         int err = 0;
3311         u32 *in;
3312         int ix;
3313
3314         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3315         in = kvzalloc(inlen, GFP_KERNEL);
3316         if (!in)
3317                 return -ENOMEM;
3318
3319         for (ix = 0; ix < priv->max_nch; ix++) {
3320                 memset(in, 0, inlen);
3321                 tir = &tirs[ix];
3322                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3323                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3324                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3325                 if (unlikely(err))
3326                         goto err_destroy_ch_tirs;
3327         }
3328
3329         goto out;
3330
3331 err_destroy_ch_tirs:
3332         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3333         for (ix--; ix >= 0; ix--)
3334                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3335
3336 out:
3337         kvfree(in);
3338
3339         return err;
3340 }
3341
3342 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3343 {
3344         int i;
3345
3346         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3347                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3348
3349         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3350                 return;
3351
3352         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3353                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3354 }
3355
3356 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3357 {
3358         int i;
3359
3360         for (i = 0; i < priv->max_nch; i++)
3361                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3362 }
3363
3364 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3365 {
3366         int err = 0;
3367         int i;
3368
3369         for (i = 0; i < chs->num; i++) {
3370                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3371                 if (err)
3372                         return err;
3373         }
3374
3375         return 0;
3376 }
3377
3378 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3379 {
3380         int err = 0;
3381         int i;
3382
3383         for (i = 0; i < chs->num; i++) {
3384                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3385                 if (err)
3386                         return err;
3387         }
3388
3389         return 0;
3390 }
3391
3392 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3393                                  struct tc_mqprio_qopt *mqprio)
3394 {
3395         struct mlx5e_channels new_channels = {};
3396         u8 tc = mqprio->num_tc;
3397         int err = 0;
3398
3399         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3400
3401         if (tc && tc != MLX5E_MAX_NUM_TC)
3402                 return -EINVAL;
3403
3404         mutex_lock(&priv->state_lock);
3405
3406         new_channels.params = priv->channels.params;
3407         new_channels.params.num_tc = tc ? tc : 1;
3408
3409         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3410                 priv->channels.params = new_channels.params;
3411                 goto out;
3412         }
3413
3414         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3415         if (err)
3416                 goto out;
3417
3418         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3419                                     new_channels.params.num_tc);
3420 out:
3421         mutex_unlock(&priv->state_lock);
3422         return err;
3423 }
3424
3425 #ifdef CONFIG_MLX5_ESWITCH
3426 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3427                                      struct flow_cls_offload *cls_flower,
3428                                      unsigned long flags)
3429 {
3430         switch (cls_flower->command) {
3431         case FLOW_CLS_REPLACE:
3432                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3433                                               flags);
3434         case FLOW_CLS_DESTROY:
3435                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3436                                            flags);
3437         case FLOW_CLS_STATS:
3438                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3439                                           flags);
3440         default:
3441                 return -EOPNOTSUPP;
3442         }
3443 }
3444
3445 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3446                                    void *cb_priv)
3447 {
3448         unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3449         struct mlx5e_priv *priv = cb_priv;
3450
3451         switch (type) {
3452         case TC_SETUP_CLSFLOWER:
3453                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3454         default:
3455                 return -EOPNOTSUPP;
3456         }
3457 }
3458 #endif
3459
3460 static LIST_HEAD(mlx5e_block_cb_list);
3461
3462 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3463                           void *type_data)
3464 {
3465         struct mlx5e_priv *priv = netdev_priv(dev);
3466
3467         switch (type) {
3468 #ifdef CONFIG_MLX5_ESWITCH
3469         case TC_SETUP_BLOCK:
3470                 return flow_block_cb_setup_simple(type_data,
3471                                                   &mlx5e_block_cb_list,
3472                                                   mlx5e_setup_tc_block_cb,
3473                                                   priv, priv, true);
3474 #endif
3475         case TC_SETUP_QDISC_MQPRIO:
3476                 return mlx5e_setup_tc_mqprio(priv, type_data);
3477         default:
3478                 return -EOPNOTSUPP;
3479         }
3480 }
3481
3482 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3483 {
3484         int i;
3485
3486         for (i = 0; i < priv->max_nch; i++) {
3487                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3488                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3489                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3490                 int j;
3491
3492                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3493                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3494
3495                 for (j = 0; j < priv->max_opened_tc; j++) {
3496                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3497
3498                         s->tx_packets    += sq_stats->packets;
3499                         s->tx_bytes      += sq_stats->bytes;
3500                         s->tx_dropped    += sq_stats->dropped;
3501                 }
3502         }
3503 }
3504
3505 void
3506 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3507 {
3508         struct mlx5e_priv *priv = netdev_priv(dev);
3509         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3510         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3511
3512         if (!mlx5e_monitor_counter_supported(priv)) {
3513                 /* update HW stats in background for next time */
3514                 mlx5e_queue_update_stats(priv);
3515         }
3516
3517         if (mlx5e_is_uplink_rep(priv)) {
3518                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3519                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3520                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3521                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3522         } else {
3523                 mlx5e_fold_sw_stats64(priv, stats);
3524         }
3525
3526         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3527
3528         stats->rx_length_errors =
3529                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3530                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3531                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3532         stats->rx_crc_errors =
3533                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3534         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3535         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3536         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3537                            stats->rx_frame_errors;
3538         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3539
3540         /* vport multicast also counts packets that are dropped due to steering
3541          * or rx out of buffer
3542          */
3543         stats->multicast =
3544                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3545 }
3546
3547 static void mlx5e_set_rx_mode(struct net_device *dev)
3548 {
3549         struct mlx5e_priv *priv = netdev_priv(dev);
3550
3551         queue_work(priv->wq, &priv->set_rx_mode_work);
3552 }
3553
3554 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3555 {
3556         struct mlx5e_priv *priv = netdev_priv(netdev);
3557         struct sockaddr *saddr = addr;
3558
3559         if (!is_valid_ether_addr(saddr->sa_data))
3560                 return -EADDRNOTAVAIL;
3561
3562         netif_addr_lock_bh(netdev);
3563         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3564         netif_addr_unlock_bh(netdev);
3565
3566         queue_work(priv->wq, &priv->set_rx_mode_work);
3567
3568         return 0;
3569 }
3570
3571 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3572         do {                                            \
3573                 if (enable)                             \
3574                         *features |= feature;           \
3575                 else                                    \
3576                         *features &= ~feature;          \
3577         } while (0)
3578
3579 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3580
3581 static int set_feature_lro(struct net_device *netdev, bool enable)
3582 {
3583         struct mlx5e_priv *priv = netdev_priv(netdev);
3584         struct mlx5_core_dev *mdev = priv->mdev;
3585         struct mlx5e_channels new_channels = {};
3586         struct mlx5e_params *old_params;
3587         int err = 0;
3588         bool reset;
3589
3590         mutex_lock(&priv->state_lock);
3591
3592         if (enable && priv->xsk.refcnt) {
3593                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3594                             priv->xsk.refcnt);
3595                 err = -EINVAL;
3596                 goto out;
3597         }
3598
3599         old_params = &priv->channels.params;
3600         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3601                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3602                 err = -EINVAL;
3603                 goto out;
3604         }
3605
3606         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3607
3608         new_channels.params = *old_params;
3609         new_channels.params.lro_en = enable;
3610
3611         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3612                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3613                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3614                         reset = false;
3615         }
3616
3617         if (!reset) {
3618                 *old_params = new_channels.params;
3619                 err = mlx5e_modify_tirs_lro(priv);
3620                 goto out;
3621         }
3622
3623         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3624 out:
3625         mutex_unlock(&priv->state_lock);
3626         return err;
3627 }
3628
3629 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3630 {
3631         struct mlx5e_priv *priv = netdev_priv(netdev);
3632
3633         if (enable)
3634                 mlx5e_enable_cvlan_filter(priv);
3635         else
3636                 mlx5e_disable_cvlan_filter(priv);
3637
3638         return 0;
3639 }
3640
3641 #ifdef CONFIG_MLX5_ESWITCH
3642 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3643 {
3644         struct mlx5e_priv *priv = netdev_priv(netdev);
3645
3646         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3647                 netdev_err(netdev,
3648                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3649                 return -EINVAL;
3650         }
3651
3652         return 0;
3653 }
3654 #endif
3655
3656 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3657 {
3658         struct mlx5e_priv *priv = netdev_priv(netdev);
3659         struct mlx5_core_dev *mdev = priv->mdev;
3660
3661         return mlx5_set_port_fcs(mdev, !enable);
3662 }
3663
3664 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3665 {
3666         struct mlx5e_priv *priv = netdev_priv(netdev);
3667         int err;
3668
3669         mutex_lock(&priv->state_lock);
3670
3671         priv->channels.params.scatter_fcs_en = enable;
3672         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3673         if (err)
3674                 priv->channels.params.scatter_fcs_en = !enable;
3675
3676         mutex_unlock(&priv->state_lock);
3677
3678         return err;
3679 }
3680
3681 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3682 {
3683         struct mlx5e_priv *priv = netdev_priv(netdev);
3684         int err = 0;
3685
3686         mutex_lock(&priv->state_lock);
3687
3688         priv->channels.params.vlan_strip_disable = !enable;
3689         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3690                 goto unlock;
3691
3692         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3693         if (err)
3694                 priv->channels.params.vlan_strip_disable = enable;
3695
3696 unlock:
3697         mutex_unlock(&priv->state_lock);
3698
3699         return err;
3700 }
3701
3702 #ifdef CONFIG_MLX5_EN_ARFS
3703 static int set_feature_arfs(struct net_device *netdev, bool enable)
3704 {
3705         struct mlx5e_priv *priv = netdev_priv(netdev);
3706         int err;
3707
3708         if (enable)
3709                 err = mlx5e_arfs_enable(priv);
3710         else
3711                 err = mlx5e_arfs_disable(priv);
3712
3713         return err;
3714 }
3715 #endif
3716
3717 static int mlx5e_handle_feature(struct net_device *netdev,
3718                                 netdev_features_t *features,
3719                                 netdev_features_t wanted_features,
3720                                 netdev_features_t feature,
3721                                 mlx5e_feature_handler feature_handler)
3722 {
3723         netdev_features_t changes = wanted_features ^ netdev->features;
3724         bool enable = !!(wanted_features & feature);
3725         int err;
3726
3727         if (!(changes & feature))
3728                 return 0;
3729
3730         err = feature_handler(netdev, enable);
3731         if (err) {
3732                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3733                            enable ? "Enable" : "Disable", &feature, err);
3734                 return err;
3735         }
3736
3737         MLX5E_SET_FEATURE(features, feature, enable);
3738         return 0;
3739 }
3740
3741 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3742 {
3743         netdev_features_t oper_features = netdev->features;
3744         int err = 0;
3745
3746 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3747         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3748
3749         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3750         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3751                                     set_feature_cvlan_filter);
3752 #ifdef CONFIG_MLX5_ESWITCH
3753         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3754 #endif
3755         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3756         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3757         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3758 #ifdef CONFIG_MLX5_EN_ARFS
3759         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3760 #endif
3761
3762         if (err) {
3763                 netdev->features = oper_features;
3764                 return -EINVAL;
3765         }
3766
3767         return 0;
3768 }
3769
3770 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3771                                             netdev_features_t features)
3772 {
3773         struct mlx5e_priv *priv = netdev_priv(netdev);
3774         struct mlx5e_params *params;
3775
3776         mutex_lock(&priv->state_lock);
3777         params = &priv->channels.params;
3778         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3779                 /* HW strips the outer C-tag header, this is a problem
3780                  * for S-tag traffic.
3781                  */
3782                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3783                 if (!params->vlan_strip_disable)
3784                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3785         }
3786         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3787                 if (features & NETIF_F_LRO) {
3788                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3789                         features &= ~NETIF_F_LRO;
3790                 }
3791         }
3792
3793         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3794                 features &= ~NETIF_F_RXHASH;
3795                 if (netdev->features & NETIF_F_RXHASH)
3796                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3797         }
3798
3799         mutex_unlock(&priv->state_lock);
3800
3801         return features;
3802 }
3803
3804 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3805                                    struct mlx5e_channels *chs,
3806                                    struct mlx5e_params *new_params,
3807                                    struct mlx5_core_dev *mdev)
3808 {
3809         u16 ix;
3810
3811         for (ix = 0; ix < chs->params.num_channels; ix++) {
3812                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3813                 struct mlx5e_xsk_param xsk;
3814
3815                 if (!umem)
3816                         continue;
3817
3818                 mlx5e_build_xsk_param(umem, &xsk);
3819
3820                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3821                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3822                         int max_mtu_frame, max_mtu_page, max_mtu;
3823
3824                         /* Two criteria must be met:
3825                          * 1. HW MTU + all headrooms <= XSK frame size.
3826                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3827                          */
3828                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3829                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3830                         max_mtu = min(max_mtu_frame, max_mtu_page);
3831
3832                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3833                                    new_params->sw_mtu, ix, max_mtu);
3834                         return false;
3835                 }
3836         }
3837
3838         return true;
3839 }
3840
3841 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3842                      change_hw_mtu_cb set_mtu_cb)
3843 {
3844         struct mlx5e_priv *priv = netdev_priv(netdev);
3845         struct mlx5e_channels new_channels = {};
3846         struct mlx5e_params *params;
3847         int err = 0;
3848         bool reset;
3849
3850         mutex_lock(&priv->state_lock);
3851
3852         params = &priv->channels.params;
3853
3854         reset = !params->lro_en;
3855         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3856
3857         new_channels.params = *params;
3858         new_channels.params.sw_mtu = new_mtu;
3859
3860         if (params->xdp_prog &&
3861             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3862                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3863                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3864                 err = -EINVAL;
3865                 goto out;
3866         }
3867
3868         if (priv->xsk.refcnt &&
3869             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3870                                     &new_channels.params, priv->mdev)) {
3871                 err = -EINVAL;
3872                 goto out;
3873         }
3874
3875         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3876                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3877                                                               &new_channels.params,
3878                                                               NULL);
3879                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3880                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3881
3882                 /* If XSK is active, XSK RQs are linear. */
3883                 is_linear |= priv->xsk.refcnt;
3884
3885                 /* Always reset in linear mode - hw_mtu is used in data path. */
3886                 reset = reset && (is_linear || (ppw_old != ppw_new));
3887         }
3888
3889         if (!reset) {
3890                 params->sw_mtu = new_mtu;
3891                 if (set_mtu_cb)
3892                         set_mtu_cb(priv);
3893                 netdev->mtu = params->sw_mtu;
3894                 goto out;
3895         }
3896
3897         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3898         if (err)
3899                 goto out;
3900
3901         netdev->mtu = new_channels.params.sw_mtu;
3902
3903 out:
3904         mutex_unlock(&priv->state_lock);
3905         return err;
3906 }
3907
3908 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3909 {
3910         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3911 }
3912
3913 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3914 {
3915         struct hwtstamp_config config;
3916         int err;
3917
3918         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3919             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3920                 return -EOPNOTSUPP;
3921
3922         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3923                 return -EFAULT;
3924
3925         /* TX HW timestamp */
3926         switch (config.tx_type) {
3927         case HWTSTAMP_TX_OFF:
3928         case HWTSTAMP_TX_ON:
3929                 break;
3930         default:
3931                 return -ERANGE;
3932         }
3933
3934         mutex_lock(&priv->state_lock);
3935         /* RX HW timestamp */
3936         switch (config.rx_filter) {
3937         case HWTSTAMP_FILTER_NONE:
3938                 /* Reset CQE compression to Admin default */
3939                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3940                 break;
3941         case HWTSTAMP_FILTER_ALL:
3942         case HWTSTAMP_FILTER_SOME:
3943         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3944         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3945         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3946         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3947         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3948         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3949         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3950         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3951         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3952         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3953         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3954         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3955         case HWTSTAMP_FILTER_NTP_ALL:
3956                 /* Disable CQE compression */
3957                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3958                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3959                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3960                 if (err) {
3961                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3962                         mutex_unlock(&priv->state_lock);
3963                         return err;
3964                 }
3965                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3966                 break;
3967         default:
3968                 mutex_unlock(&priv->state_lock);
3969                 return -ERANGE;
3970         }
3971
3972         memcpy(&priv->tstamp, &config, sizeof(config));
3973         mutex_unlock(&priv->state_lock);
3974
3975         /* might need to fix some features */
3976         netdev_update_features(priv->netdev);
3977
3978         return copy_to_user(ifr->ifr_data, &config,
3979                             sizeof(config)) ? -EFAULT : 0;
3980 }
3981
3982 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3983 {
3984         struct hwtstamp_config *cfg = &priv->tstamp;
3985
3986         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3987                 return -EOPNOTSUPP;
3988
3989         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3990 }
3991
3992 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3993 {
3994         struct mlx5e_priv *priv = netdev_priv(dev);
3995
3996         switch (cmd) {
3997         case SIOCSHWTSTAMP:
3998                 return mlx5e_hwstamp_set(priv, ifr);
3999         case SIOCGHWTSTAMP:
4000                 return mlx5e_hwstamp_get(priv, ifr);
4001         default:
4002                 return -EOPNOTSUPP;
4003         }
4004 }
4005
4006 #ifdef CONFIG_MLX5_ESWITCH
4007 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4008 {
4009         struct mlx5e_priv *priv = netdev_priv(dev);
4010         struct mlx5_core_dev *mdev = priv->mdev;
4011
4012         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4013 }
4014
4015 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4016                              __be16 vlan_proto)
4017 {
4018         struct mlx5e_priv *priv = netdev_priv(dev);
4019         struct mlx5_core_dev *mdev = priv->mdev;
4020
4021         if (vlan_proto != htons(ETH_P_8021Q))
4022                 return -EPROTONOSUPPORT;
4023
4024         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4025                                            vlan, qos);
4026 }
4027
4028 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4029 {
4030         struct mlx5e_priv *priv = netdev_priv(dev);
4031         struct mlx5_core_dev *mdev = priv->mdev;
4032
4033         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4034 }
4035
4036 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4037 {
4038         struct mlx5e_priv *priv = netdev_priv(dev);
4039         struct mlx5_core_dev *mdev = priv->mdev;
4040
4041         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4042 }
4043
4044 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4045                       int max_tx_rate)
4046 {
4047         struct mlx5e_priv *priv = netdev_priv(dev);
4048         struct mlx5_core_dev *mdev = priv->mdev;
4049
4050         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4051                                            max_tx_rate, min_tx_rate);
4052 }
4053
4054 static int mlx5_vport_link2ifla(u8 esw_link)
4055 {
4056         switch (esw_link) {
4057         case MLX5_VPORT_ADMIN_STATE_DOWN:
4058                 return IFLA_VF_LINK_STATE_DISABLE;
4059         case MLX5_VPORT_ADMIN_STATE_UP:
4060                 return IFLA_VF_LINK_STATE_ENABLE;
4061         }
4062         return IFLA_VF_LINK_STATE_AUTO;
4063 }
4064
4065 static int mlx5_ifla_link2vport(u8 ifla_link)
4066 {
4067         switch (ifla_link) {
4068         case IFLA_VF_LINK_STATE_DISABLE:
4069                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4070         case IFLA_VF_LINK_STATE_ENABLE:
4071                 return MLX5_VPORT_ADMIN_STATE_UP;
4072         }
4073         return MLX5_VPORT_ADMIN_STATE_AUTO;
4074 }
4075
4076 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4077                                    int link_state)
4078 {
4079         struct mlx5e_priv *priv = netdev_priv(dev);
4080         struct mlx5_core_dev *mdev = priv->mdev;
4081
4082         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4083                                             mlx5_ifla_link2vport(link_state));
4084 }
4085
4086 int mlx5e_get_vf_config(struct net_device *dev,
4087                         int vf, struct ifla_vf_info *ivi)
4088 {
4089         struct mlx5e_priv *priv = netdev_priv(dev);
4090         struct mlx5_core_dev *mdev = priv->mdev;
4091         int err;
4092
4093         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4094         if (err)
4095                 return err;
4096         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4097         return 0;
4098 }
4099
4100 int mlx5e_get_vf_stats(struct net_device *dev,
4101                        int vf, struct ifla_vf_stats *vf_stats)
4102 {
4103         struct mlx5e_priv *priv = netdev_priv(dev);
4104         struct mlx5_core_dev *mdev = priv->mdev;
4105
4106         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4107                                             vf_stats);
4108 }
4109 #endif
4110
4111 struct mlx5e_vxlan_work {
4112         struct work_struct      work;
4113         struct mlx5e_priv       *priv;
4114         u16                     port;
4115 };
4116
4117 static void mlx5e_vxlan_add_work(struct work_struct *work)
4118 {
4119         struct mlx5e_vxlan_work *vxlan_work =
4120                 container_of(work, struct mlx5e_vxlan_work, work);
4121         struct mlx5e_priv *priv = vxlan_work->priv;
4122         u16 port = vxlan_work->port;
4123
4124         mutex_lock(&priv->state_lock);
4125         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4126         mutex_unlock(&priv->state_lock);
4127
4128         kfree(vxlan_work);
4129 }
4130
4131 static void mlx5e_vxlan_del_work(struct work_struct *work)
4132 {
4133         struct mlx5e_vxlan_work *vxlan_work =
4134                 container_of(work, struct mlx5e_vxlan_work, work);
4135         struct mlx5e_priv *priv         = vxlan_work->priv;
4136         u16 port = vxlan_work->port;
4137
4138         mutex_lock(&priv->state_lock);
4139         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4140         mutex_unlock(&priv->state_lock);
4141         kfree(vxlan_work);
4142 }
4143
4144 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4145 {
4146         struct mlx5e_vxlan_work *vxlan_work;
4147
4148         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4149         if (!vxlan_work)
4150                 return;
4151
4152         if (add)
4153                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4154         else
4155                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4156
4157         vxlan_work->priv = priv;
4158         vxlan_work->port = port;
4159         queue_work(priv->wq, &vxlan_work->work);
4160 }
4161
4162 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4163 {
4164         struct mlx5e_priv *priv = netdev_priv(netdev);
4165
4166         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4167                 return;
4168
4169         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4170                 return;
4171
4172         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4173 }
4174
4175 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4176 {
4177         struct mlx5e_priv *priv = netdev_priv(netdev);
4178
4179         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4180                 return;
4181
4182         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4183                 return;
4184
4185         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4186 }
4187
4188 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4189                                                      struct sk_buff *skb,
4190                                                      netdev_features_t features)
4191 {
4192         unsigned int offset = 0;
4193         struct udphdr *udph;
4194         u8 proto;
4195         u16 port;
4196
4197         switch (vlan_get_protocol(skb)) {
4198         case htons(ETH_P_IP):
4199                 proto = ip_hdr(skb)->protocol;
4200                 break;
4201         case htons(ETH_P_IPV6):
4202                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4203                 break;
4204         default:
4205                 goto out;
4206         }
4207
4208         switch (proto) {
4209         case IPPROTO_GRE:
4210                 return features;
4211         case IPPROTO_UDP:
4212                 udph = udp_hdr(skb);
4213                 port = be16_to_cpu(udph->dest);
4214
4215                 /* Verify if UDP port is being offloaded by HW */
4216                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4217                         return features;
4218
4219 #if IS_ENABLED(CONFIG_GENEVE)
4220                 /* Support Geneve offload for default UDP port */
4221                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4222                         return features;
4223 #endif
4224         }
4225
4226 out:
4227         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4228         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4229 }
4230
4231 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4232                                        struct net_device *netdev,
4233                                        netdev_features_t features)
4234 {
4235         struct mlx5e_priv *priv = netdev_priv(netdev);
4236
4237         features = vlan_features_check(skb, features);
4238         features = vxlan_features_check(skb, features);
4239
4240 #ifdef CONFIG_MLX5_EN_IPSEC
4241         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4242                 return features;
4243 #endif
4244
4245         /* Validate if the tunneled packet is being offloaded by HW */
4246         if (skb->encapsulation &&
4247             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4248                 return mlx5e_tunnel_features_check(priv, skb, features);
4249
4250         return features;
4251 }
4252
4253 static void mlx5e_tx_timeout_work(struct work_struct *work)
4254 {
4255         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4256                                                tx_timeout_work);
4257         bool report_failed = false;
4258         int err;
4259         int i;
4260
4261         rtnl_lock();
4262         mutex_lock(&priv->state_lock);
4263
4264         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4265                 goto unlock;
4266
4267         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4268                 struct netdev_queue *dev_queue =
4269                         netdev_get_tx_queue(priv->netdev, i);
4270                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4271
4272                 if (!netif_xmit_stopped(dev_queue))
4273                         continue;
4274
4275                 if (mlx5e_tx_reporter_timeout(sq))
4276                         report_failed = true;
4277         }
4278
4279         if (!report_failed)
4280                 goto unlock;
4281
4282         err = mlx5e_safe_reopen_channels(priv);
4283         if (err)
4284                 netdev_err(priv->netdev,
4285                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4286                            err);
4287
4288 unlock:
4289         mutex_unlock(&priv->state_lock);
4290         rtnl_unlock();
4291 }
4292
4293 static void mlx5e_tx_timeout(struct net_device *dev)
4294 {
4295         struct mlx5e_priv *priv = netdev_priv(dev);
4296
4297         netdev_err(dev, "TX timeout detected\n");
4298         queue_work(priv->wq, &priv->tx_timeout_work);
4299 }
4300
4301 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4302 {
4303         struct net_device *netdev = priv->netdev;
4304         struct mlx5e_channels new_channels = {};
4305
4306         if (priv->channels.params.lro_en) {
4307                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4308                 return -EINVAL;
4309         }
4310
4311         if (MLX5_IPSEC_DEV(priv->mdev)) {
4312                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4313                 return -EINVAL;
4314         }
4315
4316         new_channels.params = priv->channels.params;
4317         new_channels.params.xdp_prog = prog;
4318
4319         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4320          * the XDP program.
4321          */
4322         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4323                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4324                             new_channels.params.sw_mtu,
4325                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4326                 return -EINVAL;
4327         }
4328
4329         return 0;
4330 }
4331
4332 static int mlx5e_xdp_update_state(struct mlx5e_priv *priv)
4333 {
4334         if (priv->channels.params.xdp_prog)
4335                 mlx5e_xdp_set_open(priv);
4336         else
4337                 mlx5e_xdp_set_closed(priv);
4338
4339         return 0;
4340 }
4341
4342 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4343 {
4344         struct mlx5e_priv *priv = netdev_priv(netdev);
4345         struct bpf_prog *old_prog;
4346         bool reset, was_opened;
4347         int err = 0;
4348         int i;
4349
4350         mutex_lock(&priv->state_lock);
4351
4352         if (prog) {
4353                 err = mlx5e_xdp_allowed(priv, prog);
4354                 if (err)
4355                         goto unlock;
4356         }
4357
4358         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4359         /* no need for full reset when exchanging programs */
4360         reset = (!priv->channels.params.xdp_prog || !prog);
4361
4362         if (was_opened && !reset) {
4363                 /* num_channels is invariant here, so we can take the
4364                  * batched reference right upfront.
4365                  */
4366                 prog = bpf_prog_add(prog, priv->channels.num);
4367                 if (IS_ERR(prog)) {
4368                         err = PTR_ERR(prog);
4369                         goto unlock;
4370                 }
4371         }
4372
4373         if (was_opened && reset) {
4374                 struct mlx5e_channels new_channels = {};
4375
4376                 new_channels.params = priv->channels.params;
4377                 new_channels.params.xdp_prog = prog;
4378                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4379                 old_prog = priv->channels.params.xdp_prog;
4380
4381                 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_xdp_update_state);
4382                 if (err)
4383                         goto unlock;
4384         } else {
4385                 /* exchange programs, extra prog reference we got from caller
4386                  * as long as we don't fail from this point onwards.
4387                  */
4388                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4389         }
4390
4391         if (old_prog)
4392                 bpf_prog_put(old_prog);
4393
4394         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4395                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4396
4397         if (!was_opened || reset)
4398                 goto unlock;
4399
4400         /* exchanging programs w/o reset, we update ref counts on behalf
4401          * of the channels RQs here.
4402          */
4403         for (i = 0; i < priv->channels.num; i++) {
4404                 struct mlx5e_channel *c = priv->channels.c[i];
4405                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4406
4407                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4408                 if (xsk_open)
4409                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4410                 napi_synchronize(&c->napi);
4411                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4412
4413                 old_prog = xchg(&c->rq.xdp_prog, prog);
4414                 if (old_prog)
4415                         bpf_prog_put(old_prog);
4416
4417                 if (xsk_open) {
4418                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4419                         if (old_prog)
4420                                 bpf_prog_put(old_prog);
4421                 }
4422
4423                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4424                 if (xsk_open)
4425                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4426                 /* napi_schedule in case we have missed anything */
4427                 napi_schedule(&c->napi);
4428         }
4429
4430 unlock:
4431         mutex_unlock(&priv->state_lock);
4432         return err;
4433 }
4434
4435 static u32 mlx5e_xdp_query(struct net_device *dev)
4436 {
4437         struct mlx5e_priv *priv = netdev_priv(dev);
4438         const struct bpf_prog *xdp_prog;
4439         u32 prog_id = 0;
4440
4441         mutex_lock(&priv->state_lock);
4442         xdp_prog = priv->channels.params.xdp_prog;
4443         if (xdp_prog)
4444                 prog_id = xdp_prog->aux->id;
4445         mutex_unlock(&priv->state_lock);
4446
4447         return prog_id;
4448 }
4449
4450 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4451 {
4452         switch (xdp->command) {
4453         case XDP_SETUP_PROG:
4454                 return mlx5e_xdp_set(dev, xdp->prog);
4455         case XDP_QUERY_PROG:
4456                 xdp->prog_id = mlx5e_xdp_query(dev);
4457                 return 0;
4458         case XDP_SETUP_XSK_UMEM:
4459                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4460                                             xdp->xsk.queue_id);
4461         default:
4462                 return -EINVAL;
4463         }
4464 }
4465
4466 #ifdef CONFIG_MLX5_ESWITCH
4467 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4468                                 struct net_device *dev, u32 filter_mask,
4469                                 int nlflags)
4470 {
4471         struct mlx5e_priv *priv = netdev_priv(dev);
4472         struct mlx5_core_dev *mdev = priv->mdev;
4473         u8 mode, setting;
4474         int err;
4475
4476         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4477         if (err)
4478                 return err;
4479         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4480         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4481                                        mode,
4482                                        0, 0, nlflags, filter_mask, NULL);
4483 }
4484
4485 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4486                                 u16 flags, struct netlink_ext_ack *extack)
4487 {
4488         struct mlx5e_priv *priv = netdev_priv(dev);
4489         struct mlx5_core_dev *mdev = priv->mdev;
4490         struct nlattr *attr, *br_spec;
4491         u16 mode = BRIDGE_MODE_UNDEF;
4492         u8 setting;
4493         int rem;
4494
4495         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4496         if (!br_spec)
4497                 return -EINVAL;
4498
4499         nla_for_each_nested(attr, br_spec, rem) {
4500                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4501                         continue;
4502
4503                 if (nla_len(attr) < sizeof(mode))
4504                         return -EINVAL;
4505
4506                 mode = nla_get_u16(attr);
4507                 if (mode > BRIDGE_MODE_VEPA)
4508                         return -EINVAL;
4509
4510                 break;
4511         }
4512
4513         if (mode == BRIDGE_MODE_UNDEF)
4514                 return -EINVAL;
4515
4516         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4517         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4518 }
4519 #endif
4520
4521 const struct net_device_ops mlx5e_netdev_ops = {
4522         .ndo_open                = mlx5e_open,
4523         .ndo_stop                = mlx5e_close,
4524         .ndo_start_xmit          = mlx5e_xmit,
4525         .ndo_setup_tc            = mlx5e_setup_tc,
4526         .ndo_select_queue        = mlx5e_select_queue,
4527         .ndo_get_stats64         = mlx5e_get_stats,
4528         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4529         .ndo_set_mac_address     = mlx5e_set_mac,
4530         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4531         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4532         .ndo_set_features        = mlx5e_set_features,
4533         .ndo_fix_features        = mlx5e_fix_features,
4534         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4535         .ndo_do_ioctl            = mlx5e_ioctl,
4536         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4537         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4538         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4539         .ndo_features_check      = mlx5e_features_check,
4540         .ndo_tx_timeout          = mlx5e_tx_timeout,
4541         .ndo_bpf                 = mlx5e_xdp,
4542         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4543         .ndo_xsk_async_xmit      = mlx5e_xsk_async_xmit,
4544 #ifdef CONFIG_MLX5_EN_ARFS
4545         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4546 #endif
4547 #ifdef CONFIG_MLX5_ESWITCH
4548         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4549         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4550
4551         /* SRIOV E-Switch NDOs */
4552         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4553         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4554         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4555         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4556         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4557         .ndo_get_vf_config       = mlx5e_get_vf_config,
4558         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4559         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4560 #endif
4561 };
4562
4563 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4564 {
4565         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4566                 return -EOPNOTSUPP;
4567         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4568             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4569             !MLX5_CAP_ETH(mdev, csum_cap) ||
4570             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4571             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4572             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4573             MLX5_CAP_FLOWTABLE(mdev,
4574                                flow_table_properties_nic_receive.max_ft_level)
4575                                < 3) {
4576                 mlx5_core_warn(mdev,
4577                                "Not creating net device, some required device capabilities are missing\n");
4578                 return -EOPNOTSUPP;
4579         }
4580         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4581                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4582         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4583                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4584
4585         return 0;
4586 }
4587
4588 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4589                                    int num_channels)
4590 {
4591         int i;
4592
4593         for (i = 0; i < len; i++)
4594                 indirection_rqt[i] = i % num_channels;
4595 }
4596
4597 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4598 {
4599         u32 link_speed = 0;
4600         u32 pci_bw = 0;
4601
4602         mlx5e_port_max_linkspeed(mdev, &link_speed);
4603         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4604         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4605                            link_speed, pci_bw);
4606
4607 #define MLX5E_SLOW_PCI_RATIO (2)
4608
4609         return link_speed && pci_bw &&
4610                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4611 }
4612
4613 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4614 {
4615         struct dim_cq_moder moder;
4616
4617         moder.cq_period_mode = cq_period_mode;
4618         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4619         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4620         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4621                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4622
4623         return moder;
4624 }
4625
4626 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4627 {
4628         struct dim_cq_moder moder;
4629
4630         moder.cq_period_mode = cq_period_mode;
4631         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4632         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4633         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4634                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4635
4636         return moder;
4637 }
4638
4639 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4640 {
4641         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4642                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4643                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4644 }
4645
4646 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4647 {
4648         if (params->tx_dim_enabled) {
4649                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4650
4651                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4652         } else {
4653                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4654         }
4655
4656         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4657                         params->tx_cq_moderation.cq_period_mode ==
4658                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4659 }
4660
4661 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4662 {
4663         if (params->rx_dim_enabled) {
4664                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4665
4666                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4667         } else {
4668                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4669         }
4670
4671         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4672                         params->rx_cq_moderation.cq_period_mode ==
4673                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4674 }
4675
4676 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4677 {
4678         int i;
4679
4680         /* The supported periods are organized in ascending order */
4681         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4682                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4683                         break;
4684
4685         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4686 }
4687
4688 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4689                            struct mlx5e_params *params)
4690 {
4691         /* Prefer Striding RQ, unless any of the following holds:
4692          * - Striding RQ configuration is not possible/supported.
4693          * - Slow PCI heuristic.
4694          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4695          *
4696          * No XSK params: checking the availability of striding RQ in general.
4697          */
4698         if (!slow_pci_heuristic(mdev) &&
4699             mlx5e_striding_rq_possible(mdev, params) &&
4700             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4701              !mlx5e_rx_is_linear_skb(params, NULL)))
4702                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4703         mlx5e_set_rq_type(mdev, params);
4704         mlx5e_init_rq_type_params(mdev, params);
4705 }
4706
4707 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4708                             u16 num_channels)
4709 {
4710         enum mlx5e_traffic_types tt;
4711
4712         rss_params->hfunc = ETH_RSS_HASH_TOP;
4713         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4714                             sizeof(rss_params->toeplitz_hash_key));
4715         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4716                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4717         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4718                 rss_params->rx_hash_fields[tt] =
4719                         tirc_default_config[tt].rx_hash_fields;
4720 }
4721
4722 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4723                             struct mlx5e_xsk *xsk,
4724                             struct mlx5e_rss_params *rss_params,
4725                             struct mlx5e_params *params,
4726                             u16 max_channels, u16 mtu)
4727 {
4728         u8 rx_cq_period_mode;
4729
4730         params->sw_mtu = mtu;
4731         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4732         params->num_channels = max_channels;
4733         params->num_tc       = 1;
4734
4735         /* SQ */
4736         params->log_sq_size = is_kdump_kernel() ?
4737                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4738                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4739
4740         /* XDP SQ */
4741         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4742                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4743
4744         /* set CQE compression */
4745         params->rx_cqe_compress_def = false;
4746         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4747             MLX5_CAP_GEN(mdev, vport_group_manager))
4748                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4749
4750         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4751         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4752
4753         /* RQ */
4754         mlx5e_build_rq_params(mdev, params);
4755
4756         /* HW LRO */
4757
4758         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4759         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4760                 /* No XSK params: checking the availability of striding RQ in general. */
4761                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4762                         params->lro_en = !slow_pci_heuristic(mdev);
4763         }
4764         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4765
4766         /* CQ moderation params */
4767         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4768                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4769                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4770         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4771         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4772         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4773         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4774
4775         /* TX inline */
4776         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4777
4778         /* RSS */
4779         mlx5e_build_rss_params(rss_params, params->num_channels);
4780         params->tunneled_offload_en =
4781                 mlx5e_tunnel_inner_ft_supported(mdev);
4782
4783         /* AF_XDP */
4784         params->xsk = xsk;
4785 }
4786
4787 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4788 {
4789         struct mlx5e_priv *priv = netdev_priv(netdev);
4790
4791         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4792         if (is_zero_ether_addr(netdev->dev_addr) &&
4793             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4794                 eth_hw_addr_random(netdev);
4795                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4796         }
4797 }
4798
4799 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4800 {
4801         struct mlx5e_priv *priv = netdev_priv(netdev);
4802         struct mlx5_core_dev *mdev = priv->mdev;
4803         bool fcs_supported;
4804         bool fcs_enabled;
4805
4806         SET_NETDEV_DEV(netdev, mdev->device);
4807
4808         netdev->netdev_ops = &mlx5e_netdev_ops;
4809
4810 #ifdef CONFIG_MLX5_CORE_EN_DCB
4811         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4812                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4813 #endif
4814
4815         netdev->watchdog_timeo    = 15 * HZ;
4816
4817         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4818
4819         netdev->vlan_features    |= NETIF_F_SG;
4820         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4821         netdev->vlan_features    |= NETIF_F_GRO;
4822         netdev->vlan_features    |= NETIF_F_TSO;
4823         netdev->vlan_features    |= NETIF_F_TSO6;
4824         netdev->vlan_features    |= NETIF_F_RXCSUM;
4825         netdev->vlan_features    |= NETIF_F_RXHASH;
4826
4827         netdev->mpls_features    |= NETIF_F_SG;
4828         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4829         netdev->mpls_features    |= NETIF_F_TSO;
4830         netdev->mpls_features    |= NETIF_F_TSO6;
4831
4832         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4833         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4834
4835         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4836             mlx5e_check_fragmented_striding_rq_cap(mdev))
4837                 netdev->vlan_features    |= NETIF_F_LRO;
4838
4839         netdev->hw_features       = netdev->vlan_features;
4840         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4841         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4842         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4843         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4844
4845         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4846             MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4847                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4848                 netdev->hw_enc_features |= NETIF_F_TSO;
4849                 netdev->hw_enc_features |= NETIF_F_TSO6;
4850                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4851         }
4852
4853         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4854                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4855                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4856                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4857                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4858                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4859         }
4860
4861         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4862                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4863                                            NETIF_F_GSO_GRE_CSUM;
4864                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4865                                            NETIF_F_GSO_GRE_CSUM;
4866                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4867                                                 NETIF_F_GSO_GRE_CSUM;
4868         }
4869
4870         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4871         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4872         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4873         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4874
4875         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4876
4877         if (fcs_supported)
4878                 netdev->hw_features |= NETIF_F_RXALL;
4879
4880         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4881                 netdev->hw_features |= NETIF_F_RXFCS;
4882
4883         netdev->features          = netdev->hw_features;
4884         if (!priv->channels.params.lro_en)
4885                 netdev->features  &= ~NETIF_F_LRO;
4886
4887         if (fcs_enabled)
4888                 netdev->features  &= ~NETIF_F_RXALL;
4889
4890         if (!priv->channels.params.scatter_fcs_en)
4891                 netdev->features  &= ~NETIF_F_RXFCS;
4892
4893         /* prefere CQE compression over rxhash */
4894         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4895                 netdev->features &= ~NETIF_F_RXHASH;
4896
4897 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4898         if (FT_CAP(flow_modify_en) &&
4899             FT_CAP(modify_root) &&
4900             FT_CAP(identified_miss_table_mode) &&
4901             FT_CAP(flow_table_modify)) {
4902 #ifdef CONFIG_MLX5_ESWITCH
4903                 netdev->hw_features      |= NETIF_F_HW_TC;
4904 #endif
4905 #ifdef CONFIG_MLX5_EN_ARFS
4906                 netdev->hw_features      |= NETIF_F_NTUPLE;
4907 #endif
4908         }
4909
4910         netdev->features         |= NETIF_F_HIGHDMA;
4911         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4912
4913         netdev->priv_flags       |= IFF_UNICAST_FLT;
4914
4915         mlx5e_set_netdev_dev_addr(netdev);
4916         mlx5e_ipsec_build_netdev(priv);
4917         mlx5e_tls_build_netdev(priv);
4918 }
4919
4920 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4921 {
4922         struct mlx5_core_dev *mdev = priv->mdev;
4923         int err;
4924
4925         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4926         if (err) {
4927                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4928                 priv->q_counter = 0;
4929         }
4930
4931         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4932         if (err) {
4933                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4934                 priv->drop_rq_q_counter = 0;
4935         }
4936 }
4937
4938 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4939 {
4940         if (priv->q_counter)
4941                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4942
4943         if (priv->drop_rq_q_counter)
4944                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4945 }
4946
4947 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4948                           struct net_device *netdev,
4949                           const struct mlx5e_profile *profile,
4950                           void *ppriv)
4951 {
4952         struct mlx5e_priv *priv = netdev_priv(netdev);
4953         struct mlx5e_rss_params *rss = &priv->rss_params;
4954         int err;
4955
4956         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4957         if (err)
4958                 return err;
4959
4960         mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
4961                                priv->max_nch, netdev->mtu);
4962
4963         mlx5e_timestamp_init(priv);
4964
4965         err = mlx5e_ipsec_init(priv);
4966         if (err)
4967                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4968         err = mlx5e_tls_init(priv);
4969         if (err)
4970                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4971         mlx5e_build_nic_netdev(netdev);
4972         mlx5e_build_tc2txq_maps(priv);
4973
4974         return 0;
4975 }
4976
4977 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4978 {
4979         mlx5e_tls_cleanup(priv);
4980         mlx5e_ipsec_cleanup(priv);
4981         mlx5e_netdev_cleanup(priv->netdev, priv);
4982 }
4983
4984 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4985 {
4986         struct mlx5_core_dev *mdev = priv->mdev;
4987         int err;
4988
4989         mlx5e_create_q_counters(priv);
4990
4991         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4992         if (err) {
4993                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4994                 goto err_destroy_q_counters;
4995         }
4996
4997         err = mlx5e_create_indirect_rqt(priv);
4998         if (err)
4999                 goto err_close_drop_rq;
5000
5001         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5002         if (err)
5003                 goto err_destroy_indirect_rqts;
5004
5005         err = mlx5e_create_indirect_tirs(priv, true);
5006         if (err)
5007                 goto err_destroy_direct_rqts;
5008
5009         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5010         if (err)
5011                 goto err_destroy_indirect_tirs;
5012
5013         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5014         if (unlikely(err))
5015                 goto err_destroy_direct_tirs;
5016
5017         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5018         if (unlikely(err))
5019                 goto err_destroy_xsk_rqts;
5020
5021         err = mlx5e_create_flow_steering(priv);
5022         if (err) {
5023                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5024                 goto err_destroy_xsk_tirs;
5025         }
5026
5027         err = mlx5e_tc_nic_init(priv);
5028         if (err)
5029                 goto err_destroy_flow_steering;
5030
5031         return 0;
5032
5033 err_destroy_flow_steering:
5034         mlx5e_destroy_flow_steering(priv);
5035 err_destroy_xsk_tirs:
5036         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5037 err_destroy_xsk_rqts:
5038         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5039 err_destroy_direct_tirs:
5040         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5041 err_destroy_indirect_tirs:
5042         mlx5e_destroy_indirect_tirs(priv, true);
5043 err_destroy_direct_rqts:
5044         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5045 err_destroy_indirect_rqts:
5046         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5047 err_close_drop_rq:
5048         mlx5e_close_drop_rq(&priv->drop_rq);
5049 err_destroy_q_counters:
5050         mlx5e_destroy_q_counters(priv);
5051         return err;
5052 }
5053
5054 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5055 {
5056         mlx5e_tc_nic_cleanup(priv);
5057         mlx5e_destroy_flow_steering(priv);
5058         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5059         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5060         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5061         mlx5e_destroy_indirect_tirs(priv, true);
5062         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5063         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5064         mlx5e_close_drop_rq(&priv->drop_rq);
5065         mlx5e_destroy_q_counters(priv);
5066 }
5067
5068 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5069 {
5070         int err;
5071
5072         err = mlx5e_create_tises(priv);
5073         if (err) {
5074                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5075                 return err;
5076         }
5077
5078 #ifdef CONFIG_MLX5_CORE_EN_DCB
5079         mlx5e_dcbnl_initialize(priv);
5080 #endif
5081         mlx5e_tx_reporter_create(priv);
5082         return 0;
5083 }
5084
5085 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5086 {
5087         struct net_device *netdev = priv->netdev;
5088         struct mlx5_core_dev *mdev = priv->mdev;
5089
5090         mlx5e_init_l2_addr(priv);
5091
5092         /* Marking the link as currently not needed by the Driver */
5093         if (!netif_running(netdev))
5094                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5095
5096         mlx5e_set_netdev_mtu_boundaries(priv);
5097         mlx5e_set_dev_port_mtu(priv);
5098
5099         mlx5_lag_add(mdev, netdev);
5100
5101         mlx5e_enable_async_events(priv);
5102         if (mlx5e_monitor_counter_supported(priv))
5103                 mlx5e_monitor_counter_init(priv);
5104
5105         if (netdev->reg_state != NETREG_REGISTERED)
5106                 return;
5107 #ifdef CONFIG_MLX5_CORE_EN_DCB
5108         mlx5e_dcbnl_init_app(priv);
5109 #endif
5110
5111         queue_work(priv->wq, &priv->set_rx_mode_work);
5112
5113         rtnl_lock();
5114         if (netif_running(netdev))
5115                 mlx5e_open(netdev);
5116         netif_device_attach(netdev);
5117         rtnl_unlock();
5118 }
5119
5120 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5121 {
5122         struct mlx5_core_dev *mdev = priv->mdev;
5123
5124 #ifdef CONFIG_MLX5_CORE_EN_DCB
5125         if (priv->netdev->reg_state == NETREG_REGISTERED)
5126                 mlx5e_dcbnl_delete_app(priv);
5127 #endif
5128
5129         rtnl_lock();
5130         if (netif_running(priv->netdev))
5131                 mlx5e_close(priv->netdev);
5132         netif_device_detach(priv->netdev);
5133         rtnl_unlock();
5134
5135         queue_work(priv->wq, &priv->set_rx_mode_work);
5136
5137         if (mlx5e_monitor_counter_supported(priv))
5138                 mlx5e_monitor_counter_cleanup(priv);
5139
5140         mlx5e_disable_async_events(priv);
5141         mlx5_lag_remove(mdev);
5142 }
5143
5144 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5145 {
5146         return mlx5e_refresh_tirs(priv, false);
5147 }
5148
5149 static const struct mlx5e_profile mlx5e_nic_profile = {
5150         .init              = mlx5e_nic_init,
5151         .cleanup           = mlx5e_nic_cleanup,
5152         .init_rx           = mlx5e_init_nic_rx,
5153         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5154         .init_tx           = mlx5e_init_nic_tx,
5155         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5156         .enable            = mlx5e_nic_enable,
5157         .disable           = mlx5e_nic_disable,
5158         .update_rx         = mlx5e_update_nic_rx,
5159         .update_stats      = mlx5e_update_ndo_stats,
5160         .update_carrier    = mlx5e_update_carrier,
5161         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5162         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5163         .max_tc            = MLX5E_MAX_NUM_TC,
5164         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5165 };
5166
5167 /* mlx5e generic netdev management API (move to en_common.c) */
5168
5169 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5170 int mlx5e_netdev_init(struct net_device *netdev,
5171                       struct mlx5e_priv *priv,
5172                       struct mlx5_core_dev *mdev,
5173                       const struct mlx5e_profile *profile,
5174                       void *ppriv)
5175 {
5176         /* priv init */
5177         priv->mdev        = mdev;
5178         priv->netdev      = netdev;
5179         priv->profile     = profile;
5180         priv->ppriv       = ppriv;
5181         priv->msglevel    = MLX5E_MSG_LEVEL;
5182         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5183         priv->max_opened_tc = 1;
5184
5185         mutex_init(&priv->state_lock);
5186         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5187         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5188         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5189         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5190
5191         priv->wq = create_singlethread_workqueue("mlx5e");
5192         if (!priv->wq)
5193                 return -ENOMEM;
5194
5195         /* netdev init */
5196         netif_carrier_off(netdev);
5197
5198 #ifdef CONFIG_MLX5_EN_ARFS
5199         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5200 #endif
5201
5202         return 0;
5203 }
5204
5205 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5206 {
5207         destroy_workqueue(priv->wq);
5208 }
5209
5210 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5211                                        const struct mlx5e_profile *profile,
5212                                        int nch,
5213                                        void *ppriv)
5214 {
5215         struct net_device *netdev;
5216         int err;
5217
5218         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5219                                     nch * profile->max_tc,
5220                                     nch * profile->rq_groups);
5221         if (!netdev) {
5222                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5223                 return NULL;
5224         }
5225
5226         err = profile->init(mdev, netdev, profile, ppriv);
5227         if (err) {
5228                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5229                 goto err_free_netdev;
5230         }
5231
5232         return netdev;
5233
5234 err_free_netdev:
5235         free_netdev(netdev);
5236
5237         return NULL;
5238 }
5239
5240 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5241 {
5242         const struct mlx5e_profile *profile;
5243         int max_nch;
5244         int err;
5245
5246         profile = priv->profile;
5247         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5248
5249         /* max number of channels may have changed */
5250         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5251         if (priv->channels.params.num_channels > max_nch) {
5252                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5253                 priv->channels.params.num_channels = max_nch;
5254                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5255                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5256         }
5257
5258         err = profile->init_tx(priv);
5259         if (err)
5260                 goto out;
5261
5262         err = profile->init_rx(priv);
5263         if (err)
5264                 goto err_cleanup_tx;
5265
5266         if (profile->enable)
5267                 profile->enable(priv);
5268
5269         return 0;
5270
5271 err_cleanup_tx:
5272         profile->cleanup_tx(priv);
5273
5274 out:
5275         return err;
5276 }
5277
5278 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5279 {
5280         const struct mlx5e_profile *profile = priv->profile;
5281
5282         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5283
5284         if (profile->disable)
5285                 profile->disable(priv);
5286         flush_workqueue(priv->wq);
5287
5288         profile->cleanup_rx(priv);
5289         profile->cleanup_tx(priv);
5290         cancel_work_sync(&priv->update_stats_work);
5291 }
5292
5293 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5294 {
5295         const struct mlx5e_profile *profile = priv->profile;
5296         struct net_device *netdev = priv->netdev;
5297
5298         if (profile->cleanup)
5299                 profile->cleanup(priv);
5300         free_netdev(netdev);
5301 }
5302
5303 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5304  * hardware contexts and to connect it to the current netdev.
5305  */
5306 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5307 {
5308         struct mlx5e_priv *priv = vpriv;
5309         struct net_device *netdev = priv->netdev;
5310         int err;
5311
5312         if (netif_device_present(netdev))
5313                 return 0;
5314
5315         err = mlx5e_create_mdev_resources(mdev);
5316         if (err)
5317                 return err;
5318
5319         err = mlx5e_attach_netdev(priv);
5320         if (err) {
5321                 mlx5e_destroy_mdev_resources(mdev);
5322                 return err;
5323         }
5324
5325         return 0;
5326 }
5327
5328 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5329 {
5330         struct mlx5e_priv *priv = vpriv;
5331         struct net_device *netdev = priv->netdev;
5332
5333 #ifdef CONFIG_MLX5_ESWITCH
5334         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5335                 return;
5336 #endif
5337
5338         if (!netif_device_present(netdev))
5339                 return;
5340
5341         mlx5e_detach_netdev(priv);
5342         mlx5e_destroy_mdev_resources(mdev);
5343 }
5344
5345 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5346 {
5347         struct net_device *netdev;
5348         void *priv;
5349         int err;
5350         int nch;
5351
5352         err = mlx5e_check_required_hca_cap(mdev);
5353         if (err)
5354                 return NULL;
5355
5356 #ifdef CONFIG_MLX5_ESWITCH
5357         if (MLX5_ESWITCH_MANAGER(mdev) &&
5358             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5359                 mlx5e_rep_register_vport_reps(mdev);
5360                 return mdev;
5361         }
5362 #endif
5363
5364         nch = mlx5e_get_max_num_channels(mdev);
5365         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5366         if (!netdev) {
5367                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5368                 return NULL;
5369         }
5370
5371         priv = netdev_priv(netdev);
5372
5373         err = mlx5e_attach(mdev, priv);
5374         if (err) {
5375                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5376                 goto err_destroy_netdev;
5377         }
5378
5379         err = register_netdev(netdev);
5380         if (err) {
5381                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5382                 goto err_detach;
5383         }
5384
5385 #ifdef CONFIG_MLX5_CORE_EN_DCB
5386         mlx5e_dcbnl_init_app(priv);
5387 #endif
5388         return priv;
5389
5390 err_detach:
5391         mlx5e_detach(mdev, priv);
5392 err_destroy_netdev:
5393         mlx5e_destroy_netdev(priv);
5394         return NULL;
5395 }
5396
5397 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5398 {
5399         struct mlx5e_priv *priv;
5400
5401 #ifdef CONFIG_MLX5_ESWITCH
5402         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5403                 mlx5e_rep_unregister_vport_reps(mdev);
5404                 return;
5405         }
5406 #endif
5407         priv = vpriv;
5408 #ifdef CONFIG_MLX5_CORE_EN_DCB
5409         mlx5e_dcbnl_delete_app(priv);
5410 #endif
5411         unregister_netdev(priv->netdev);
5412         mlx5e_detach(mdev, vpriv);
5413         mlx5e_destroy_netdev(priv);
5414 }
5415
5416 static struct mlx5_interface mlx5e_interface = {
5417         .add       = mlx5e_add,
5418         .remove    = mlx5e_remove,
5419         .attach    = mlx5e_attach,
5420         .detach    = mlx5e_detach,
5421         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5422 };
5423
5424 void mlx5e_init(void)
5425 {
5426         mlx5e_ipsec_build_inverse_table();
5427         mlx5e_build_ptys2ethtool_map();
5428         mlx5_register_interface(&mlx5e_interface);
5429 }
5430
5431 void mlx5e_cleanup(void)
5432 {
5433         mlx5_unregister_interface(&mlx5e_interface);
5434 }