drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "lib/vxlan.h"
  49 #include "lib/clock.h"
  50 #include "en/port.h"
  51 #include "en/xdp.h"
  52
  53 struct mlx5e_rq_param {
  54         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  55         struct mlx5_wq_param    wq;
  56         struct mlx5e_rq_frags_info frags_info;
  57 };
  58
  59 struct mlx5e_sq_param {
  60         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  61         struct mlx5_wq_param       wq;
  62 };
  63
  64 struct mlx5e_cq_param {
  65         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  66         struct mlx5_wq_param       wq;
  67         u16                        eq_ix;
  68         u8                         cq_period_mode;
  69 };
  70
  71 struct mlx5e_channel_param {
  72         struct mlx5e_rq_param      rq;
  73         struct mlx5e_sq_param      sq;
  74         struct mlx5e_sq_param      xdp_sq;
  75         struct mlx5e_sq_param      icosq;
  76         struct mlx5e_cq_param      rx_cq;
  77         struct mlx5e_cq_param      tx_cq;
  78         struct mlx5e_cq_param      icosq_cq;
  79 };
  80
  81 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  82 {
  83         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  84                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  85                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  86         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  87         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  88
  89         if (!striding_rq_umr)
  90                 return false;
  91         if (!inline_umr) {
  92                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  93                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  94                 return false;
  95         }
  96         return true;
  97 }
  98
  99 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
 100 {
 101         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 102         u16 linear_rq_headroom = params->xdp_prog ?
 103                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 104         u32 frag_sz;
 105
 106         linear_rq_headroom += NET_IP_ALIGN;
 107
 108         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 109
 110         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 111                 frag_sz = PAGE_SIZE;
 112
 113         return frag_sz;
 114 }
 115
 116 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 117 {
 118         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 119
 120         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 121 }
 122
 123 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 124                                    struct mlx5e_params *params)
 125 {
 126         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 127
 128         return !params->lro_en && frag_sz <= PAGE_SIZE;
 129 }
 130
 131 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 132                                          struct mlx5e_params *params)
 133 {
 134         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 135         s8 signed_log_num_strides_param;
 136         u8 log_num_strides;
 137
 138         if (!mlx5e_rx_is_linear_skb(mdev, params))
 139                 return false;
 140
 141         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 142                 return true;
 143
 144         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 145         signed_log_num_strides_param =
 146                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 147
 148         return signed_log_num_strides_param >= 0;
 149 }
 150
 151 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 152 {
 153         if (params->log_rq_mtu_frames <
 154             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 155                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 156
 157         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 158 }
 159
 160 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 161                                           struct mlx5e_params *params)
 162 {
 163         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 164                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 165
 166         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 167                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 168 }
 169
 170 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 171                                           struct mlx5e_params *params)
 172 {
 173         return MLX5_MPWRQ_LOG_WQE_SZ -
 174                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 175 }
 176
 177 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 178                                  struct mlx5e_params *params)
 179 {
 180         u16 linear_rq_headroom = params->xdp_prog ?
 181                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 182         bool is_linear_skb;
 183
 184         linear_rq_headroom += NET_IP_ALIGN;
 185
 186         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 187                 mlx5e_rx_is_linear_skb(mdev, params) :
 188                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 189
 190         return is_linear_skb ? linear_rq_headroom : 0;
 191 }
 192
 193 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 194                                struct mlx5e_params *params)
 195 {
 196         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 197         params->log_rq_mtu_frames = is_kdump_kernel() ?
 198                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 199                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 200
 201         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 202                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 203                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 204                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 205                        BIT(params->log_rq_mtu_frames),
 206                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 207                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 208 }
 209
 210 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 211                                 struct mlx5e_params *params)
 212 {
 213         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 214                 !MLX5_IPSEC_DEV(mdev) &&
 215                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 216 }
 217
 218 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 219 {
 220         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 221                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 222                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 223                 MLX5_WQ_TYPE_CYCLIC;
 224 }
 225
 226 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 227 {
 228         struct mlx5_core_dev *mdev = priv->mdev;
 229         u8 port_state;
 230
 231         port_state = mlx5_query_vport_state(mdev,
 232                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 233                                             0);
 234
 235         if (port_state == VPORT_STATE_UP) {
 236                 netdev_info(priv->netdev, "Link up\n");
 237                 netif_carrier_on(priv->netdev);
 238         } else {
 239                 netdev_info(priv->netdev, "Link down\n");
 240                 netif_carrier_off(priv->netdev);
 241         }
 242 }
 243
 244 static void mlx5e_update_carrier_work(struct work_struct *work)
 245 {
 246         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 247                                                update_carrier_work);
 248
 249         mutex_lock(&priv->state_lock);
 250         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 251                 if (priv->profile->update_carrier)
 252                         priv->profile->update_carrier(priv);
 253         mutex_unlock(&priv->state_lock);
 254 }
 255
 256 void mlx5e_update_stats(struct mlx5e_priv *priv)
 257 {
 258         int i;
 259
 260         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 261                 if (mlx5e_stats_grps[i].update_stats)
 262                         mlx5e_stats_grps[i].update_stats(priv);
 263 }
 264
 265 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 266 {
 267         int i;
 268
 269         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 270                 if (mlx5e_stats_grps[i].update_stats_mask &
 271                     MLX5E_NDO_UPDATE_STATS)
 272                         mlx5e_stats_grps[i].update_stats(priv);
 273 }
 274
 275 static void mlx5e_update_stats_work(struct work_struct *work)
 276 {
 277         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 278                                                update_stats_work);
 279
 280         mutex_lock(&priv->state_lock);
 281         priv->profile->update_stats(priv);
 282         mutex_unlock(&priv->state_lock);
 283 }
 284
 285 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 286 {
 287         if (!priv->profile->update_stats)
 288                 return;
 289
 290         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 291                 return;
 292
 293         queue_work(priv->wq, &priv->update_stats_work);
 294 }
 295
 296 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 297                               enum mlx5_dev_event event, unsigned long param)
 298 {
 299         struct mlx5e_priv *priv = vpriv;
 300
 301         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 302                 return;
 303
 304         switch (event) {
 305         case MLX5_DEV_EVENT_PORT_UP:
 306         case MLX5_DEV_EVENT_PORT_DOWN:
 307                 queue_work(priv->wq, &priv->update_carrier_work);
 308                 break;
 309         default:
 310                 break;
 311         }
 312 }
 313
 314 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 315 {
 316         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 317 }
 318
 319 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 320 {
 321         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 322         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 323 }
 324
 325 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 326                                        struct mlx5e_icosq *sq,
 327                                        struct mlx5e_umr_wqe *wqe)
 328 {
 329         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 330         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 331         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 332
 333         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 334                                       ds_cnt);
 335         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 336         cseg->imm       = rq->mkey_be;
 337
 338         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 339         ucseg->xlt_octowords =
 340                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 341         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 342 }
 343
 344 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 345 {
 346         switch (rq->wq_type) {
 347         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 348                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 349         default:
 350                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 351         }
 352 }
 353
 354 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 355 {
 356         switch (rq->wq_type) {
 357         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 358                 return rq->mpwqe.wq.cur_sz;
 359         default:
 360                 return rq->wqe.wq.cur_sz;
 361         }
 362 }
 363
 364 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 365                                      struct mlx5e_channel *c)
 366 {
 367         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 368
 369         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 370                                                   sizeof(*rq->mpwqe.info)),
 371                                        GFP_KERNEL, cpu_to_node(c->cpu));
 372         if (!rq->mpwqe.info)
 373                 return -ENOMEM;
 374
 375         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 376
 377         return 0;
 378 }
 379
 380 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 381                                  u64 npages, u8 page_shift,
 382                                  struct mlx5_core_mkey *umr_mkey)
 383 {
 384         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 385         void *mkc;
 386         u32 *in;
 387         int err;
 388
 389         in = kvzalloc(inlen, GFP_KERNEL);
 390         if (!in)
 391                 return -ENOMEM;
 392
 393         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 394
 395         MLX5_SET(mkc, mkc, free, 1);
 396         MLX5_SET(mkc, mkc, umr_en, 1);
 397         MLX5_SET(mkc, mkc, lw, 1);
 398         MLX5_SET(mkc, mkc, lr, 1);
 399         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 400
 401         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 402         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 403         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 404         MLX5_SET(mkc, mkc, translations_octword_size,
 405                  MLX5_MTT_OCTW(npages));
 406         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 407
 408         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 409
 410         kvfree(in);
 411         return err;
 412 }
 413
 414 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 415 {
 416         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 417
 418         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 419 }
 420
 421 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 422 {
 423         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 424 }
 425
 426 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 427 {
 428         struct mlx5e_wqe_frag_info next_frag, *prev;
 429         int i;
 430
 431         next_frag.di = &rq->wqe.di[0];
 432         next_frag.offset = 0;
 433         prev = NULL;
 434
 435         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 436                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 437                 struct mlx5e_wqe_frag_info *frag =
 438                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 439                 int f;
 440
 441                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 442                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 443                                 next_frag.di++;
 444                                 next_frag.offset = 0;
 445                                 if (prev)
 446                                         prev->last_in_page = true;
 447                         }
 448                         *frag = next_frag;
 449
 450                         /* prepare next */
 451                         next_frag.offset += frag_info[f].frag_stride;
 452                         prev = frag;
 453                 }
 454         }
 455
 456         if (prev)
 457                 prev->last_in_page = true;
 458 }
 459
 460 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 461                               struct mlx5e_params *params,
 462                               int wq_sz, int cpu)
 463 {
 464         int len = wq_sz << rq->wqe.info.log_num_frags;
 465
 466         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 467                                    GFP_KERNEL, cpu_to_node(cpu));
 468         if (!rq->wqe.di)
 469                 return -ENOMEM;
 470
 471         mlx5e_init_frags_partition(rq);
 472
 473         return 0;
 474 }
 475
 476 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 477 {
 478         kvfree(rq->wqe.di);
 479 }
 480
 481 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 482                           struct mlx5e_params *params,
 483                           struct mlx5e_rq_param *rqp,
 484                           struct mlx5e_rq *rq)
 485 {
 486         struct page_pool_params pp_params = { 0 };
 487         struct mlx5_core_dev *mdev = c->mdev;
 488         void *rqc = rqp->rqc;
 489         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 490         u32 pool_size;
 491         int wq_sz;
 492         int err;
 493         int i;
 494
 495         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 496
 497         rq->wq_type = params->rq_wq_type;
 498         rq->pdev    = c->pdev;
 499         rq->netdev  = c->netdev;
 500         rq->tstamp  = c->tstamp;
 501         rq->clock   = &mdev->clock;
 502         rq->channel = c;
 503         rq->ix      = c->ix;
 504         rq->mdev    = mdev;
 505         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 506         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 507
 508         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 509         if (IS_ERR(rq->xdp_prog)) {
 510                 err = PTR_ERR(rq->xdp_prog);
 511                 rq->xdp_prog = NULL;
 512                 goto err_rq_wq_destroy;
 513         }
 514
 515         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 516         if (err < 0)
 517                 goto err_rq_wq_destroy;
 518
 519         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 520         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 521         pool_size = 1 << params->log_rq_mtu_frames;
 522
 523         switch (rq->wq_type) {
 524         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 525                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 526                                         &rq->wq_ctrl);
 527                 if (err)
 528                         return err;
 529
 530                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 531
 532                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 533
 534                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 535
 536                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 537                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 538
 539                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 540 #ifdef CONFIG_MLX5_EN_IPSEC
 541                 if (MLX5_IPSEC_DEV(mdev)) {
 542                         err = -EINVAL;
 543                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 544                         goto err_rq_wq_destroy;
 545                 }
 546 #endif
 547                 if (!rq->handle_rx_cqe) {
 548                         err = -EINVAL;
 549                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 550                         goto err_rq_wq_destroy;
 551                 }
 552
 553                 rq->mpwqe.skb_from_cqe_mpwrq =
 554                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 555                         mlx5e_skb_from_cqe_mpwrq_linear :
 556                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 557                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 558                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 559
 560                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 561                 if (err)
 562                         goto err_rq_wq_destroy;
 563                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 564
 565                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 566                 if (err)
 567                         goto err_free;
 568                 break;
 569         default: /* MLX5_WQ_TYPE_CYCLIC */
 570                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 571                                          &rq->wq_ctrl);
 572                 if (err)
 573                         return err;
 574
 575                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 576
 577                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 578
 579                 rq->wqe.info = rqp->frags_info;
 580                 rq->wqe.frags =
 581                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 582                                         (wq_sz << rq->wqe.info.log_num_frags)),
 583                                       GFP_KERNEL, cpu_to_node(c->cpu));
 584                 if (!rq->wqe.frags) {
 585                         err = -ENOMEM;
 586                         goto err_free;
 587                 }
 588
 589                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 590                 if (err)
 591                         goto err_free;
 592                 rq->post_wqes = mlx5e_post_rx_wqes;
 593                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 594
 595 #ifdef CONFIG_MLX5_EN_IPSEC
 596                 if (c->priv->ipsec)
 597                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 598                 else
 599 #endif
 600                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 601                 if (!rq->handle_rx_cqe) {
 602                         err = -EINVAL;
 603                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 604                         goto err_free;
 605                 }
 606
 607                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 608                         mlx5e_skb_from_cqe_linear :
 609                         mlx5e_skb_from_cqe_nonlinear;
 610                 rq->mkey_be = c->mkey_be;
 611         }
 612
 613         /* Create a page_pool and register it with rxq */
 614         pp_params.order     = 0;
 615         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 616         pp_params.pool_size = pool_size;
 617         pp_params.nid       = cpu_to_node(c->cpu);
 618         pp_params.dev       = c->pdev;
 619         pp_params.dma_dir   = rq->buff.map_dir;
 620
 621         /* page_pool can be used even when there is no rq->xdp_prog,
 622          * given page_pool does not handle DMA mapping there is no
 623          * required state to clear. And page_pool gracefully handle
 624          * elevated refcnt.
 625          */
 626         rq->page_pool = page_pool_create(&pp_params);
 627         if (IS_ERR(rq->page_pool)) {
 628                 err = PTR_ERR(rq->page_pool);
 629                 rq->page_pool = NULL;
 630                 goto err_free;
 631         }
 632         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 633                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 634         if (err)
 635                 goto err_free;
 636
 637         for (i = 0; i < wq_sz; i++) {
 638                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 639                         struct mlx5e_rx_wqe_ll *wqe =
 640                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 641                         u32 byte_count =
 642                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 643                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 644
 645                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 646                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 647                         wqe->data[0].lkey = rq->mkey_be;
 648                 } else {
 649                         struct mlx5e_rx_wqe_cyc *wqe =
 650                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 651                         int f;
 652
 653                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 654                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 655                                         MLX5_HW_START_PADDING;
 656
 657                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 658                                 wqe->data[f].lkey = rq->mkey_be;
 659                         }
 660                         /* check if num_frags is not a pow of two */
 661                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 662                                 wqe->data[f].byte_count = 0;
 663                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 664                                 wqe->data[f].addr = 0;
 665                         }
 666                 }
 667         }
 668
 669         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 670
 671         switch (params->rx_cq_moderation.cq_period_mode) {
 672         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 673                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 674                 break;
 675         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 676         default:
 677                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 678         }
 679
 680         rq->page_cache.head = 0;
 681         rq->page_cache.tail = 0;
 682
 683         return 0;
 684
 685 err_free:
 686         switch (rq->wq_type) {
 687         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 688                 kvfree(rq->mpwqe.info);
 689                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 690                 break;
 691         default: /* MLX5_WQ_TYPE_CYCLIC */
 692                 kvfree(rq->wqe.frags);
 693                 mlx5e_free_di_list(rq);
 694         }
 695
 696 err_rq_wq_destroy:
 697         if (rq->xdp_prog)
 698                 bpf_prog_put(rq->xdp_prog);
 699         xdp_rxq_info_unreg(&rq->xdp_rxq);
 700         if (rq->page_pool)
 701                 page_pool_destroy(rq->page_pool);
 702         mlx5_wq_destroy(&rq->wq_ctrl);
 703
 704         return err;
 705 }
 706
 707 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 708 {
 709         int i;
 710
 711         if (rq->xdp_prog)
 712                 bpf_prog_put(rq->xdp_prog);
 713
 714         xdp_rxq_info_unreg(&rq->xdp_rxq);
 715         if (rq->page_pool)
 716                 page_pool_destroy(rq->page_pool);
 717
 718         switch (rq->wq_type) {
 719         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 720                 kvfree(rq->mpwqe.info);
 721                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 722                 break;
 723         default: /* MLX5_WQ_TYPE_CYCLIC */
 724                 kvfree(rq->wqe.frags);
 725                 mlx5e_free_di_list(rq);
 726         }
 727
 728         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 729              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 730                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 731
 732                 mlx5e_page_release(rq, dma_info, false);
 733         }
 734         mlx5_wq_destroy(&rq->wq_ctrl);
 735 }
 736
 737 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 738                            struct mlx5e_rq_param *param)
 739 {
 740         struct mlx5_core_dev *mdev = rq->mdev;
 741
 742         void *in;
 743         void *rqc;
 744         void *wq;
 745         int inlen;
 746         int err;
 747
 748         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 749                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 750         in = kvzalloc(inlen, GFP_KERNEL);
 751         if (!in)
 752                 return -ENOMEM;
 753
 754         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 755         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 756
 757         memcpy(rqc, param->rqc, sizeof(param->rqc));
 758
 759         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 760         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 761         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 762                                                 MLX5_ADAPTER_PAGE_SHIFT);
 763         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 764
 765         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 766                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 767
 768         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 769
 770         kvfree(in);
 771
 772         return err;
 773 }
 774
 775 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 776                                  int next_state)
 777 {
 778         struct mlx5_core_dev *mdev = rq->mdev;
 779
 780         void *in;
 781         void *rqc;
 782         int inlen;
 783         int err;
 784
 785         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 786         in = kvzalloc(inlen, GFP_KERNEL);
 787         if (!in)
 788                 return -ENOMEM;
 789
 790         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 791
 792         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 793         MLX5_SET(rqc, rqc, state, next_state);
 794
 795         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 796
 797         kvfree(in);
 798
 799         return err;
 800 }
 801
 802 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 803 {
 804         struct mlx5e_channel *c = rq->channel;
 805         struct mlx5e_priv *priv = c->priv;
 806         struct mlx5_core_dev *mdev = priv->mdev;
 807
 808         void *in;
 809         void *rqc;
 810         int inlen;
 811         int err;
 812
 813         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 814         in = kvzalloc(inlen, GFP_KERNEL);
 815         if (!in)
 816                 return -ENOMEM;
 817
 818         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 819
 820         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 821         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 822                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 823         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 824         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 825
 826         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 827
 828         kvfree(in);
 829
 830         return err;
 831 }
 832
 833 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 834 {
 835         struct mlx5e_channel *c = rq->channel;
 836         struct mlx5_core_dev *mdev = c->mdev;
 837         void *in;
 838         void *rqc;
 839         int inlen;
 840         int err;
 841
 842         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 843         in = kvzalloc(inlen, GFP_KERNEL);
 844         if (!in)
 845                 return -ENOMEM;
 846
 847         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 848
 849         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 850         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 851                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 852         MLX5_SET(rqc, rqc, vsd, vsd);
 853         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 854
 855         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 856
 857         kvfree(in);
 858
 859         return err;
 860 }
 861
 862 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 863 {
 864         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 865 }
 866
 867 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 868 {
 869         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 870         struct mlx5e_channel *c = rq->channel;
 871
 872         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 873
 874         do {
 875                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 876                         return 0;
 877
 878                 msleep(20);
 879         } while (time_before(jiffies, exp_time));
 880
 881         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 882                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 883
 884         return -ETIMEDOUT;
 885 }
 886
 887 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 888 {
 889         __be16 wqe_ix_be;
 890         u16 wqe_ix;
 891
 892         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 893                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 894
 895                 /* UMR WQE (if in progress) is always at wq->head */
 896                 if (rq->mpwqe.umr_in_progress)
 897                         rq->dealloc_wqe(rq, wq->head);
 898
 899                 while (!mlx5_wq_ll_is_empty(wq)) {
 900                         struct mlx5e_rx_wqe_ll *wqe;
 901
 902                         wqe_ix_be = *wq->tail_next;
 903                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 904                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 905                         rq->dealloc_wqe(rq, wqe_ix);
 906                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 907                                        &wqe->next.next_wqe_index);
 908                 }
 909         } else {
 910                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 911
 912                 while (!mlx5_wq_cyc_is_empty(wq)) {
 913                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 914                         rq->dealloc_wqe(rq, wqe_ix);
 915                         mlx5_wq_cyc_pop(wq);
 916                 }
 917         }
 918
 919 }
 920
 921 static int mlx5e_open_rq(struct mlx5e_channel *c,
 922                          struct mlx5e_params *params,
 923                          struct mlx5e_rq_param *param,
 924                          struct mlx5e_rq *rq)
 925 {
 926         int err;
 927
 928         err = mlx5e_alloc_rq(c, params, param, rq);
 929         if (err)
 930                 return err;
 931
 932         err = mlx5e_create_rq(rq, param);
 933         if (err)
 934                 goto err_free_rq;
 935
 936         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 937         if (err)
 938                 goto err_destroy_rq;
 939
 940         if (params->rx_dim_enabled)
 941                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 942
 943         if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE)
 944                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 945
 946         return 0;
 947
 948 err_destroy_rq:
 949         mlx5e_destroy_rq(rq);
 950 err_free_rq:
 951         mlx5e_free_rq(rq);
 952
 953         return err;
 954 }
 955
 956 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 957 {
 958         struct mlx5e_icosq *sq = &rq->channel->icosq;
 959         struct mlx5_wq_cyc *wq = &sq->wq;
 960         struct mlx5e_tx_wqe *nopwqe;
 961
 962         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 963
 964         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 965         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 966         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 967         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 968 }
 969
 970 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 971 {
 972         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 973         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 974 }
 975
 976 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 977 {
 978         cancel_work_sync(&rq->dim.work);
 979         mlx5e_destroy_rq(rq);
 980         mlx5e_free_rx_descs(rq);
 981         mlx5e_free_rq(rq);
 982 }
 983
 984 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 985 {
 986         kvfree(sq->db.xdpi);
 987 }
 988
 989 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 990 {
 991         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 992
 993         sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
 994                                     GFP_KERNEL, numa);
 995         if (!sq->db.xdpi) {
 996                 mlx5e_free_xdpsq_db(sq);
 997                 return -ENOMEM;
 998         }
 999
1000         return 0;
1001 }
1002
1003 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1004                              struct mlx5e_params *params,
1005                              struct mlx5e_sq_param *param,
1006                              struct mlx5e_xdpsq *sq,
1007                              bool is_redirect)
1008 {
1009         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1010         struct mlx5_core_dev *mdev = c->mdev;
1011         struct mlx5_wq_cyc *wq = &sq->wq;
1012         int err;
1013
1014         sq->pdev      = c->pdev;
1015         sq->mkey_be   = c->mkey_be;
1016         sq->channel   = c;
1017         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1018         sq->min_inline_mode = params->tx_min_inline_mode;
1019         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1020         sq->stats     = is_redirect ?
1021                 &c->priv->channel_stats[c->ix].xdpsq :
1022                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1023
1024         param->wq.db_numa_node = cpu_to_node(c->cpu);
1025         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1026         if (err)
1027                 return err;
1028         wq->db = &wq->db[MLX5_SND_DBR];
1029
1030         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1031         if (err)
1032                 goto err_sq_wq_destroy;
1033
1034         return 0;
1035
1036 err_sq_wq_destroy:
1037         mlx5_wq_destroy(&sq->wq_ctrl);
1038
1039         return err;
1040 }
1041
1042 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1043 {
1044         mlx5e_free_xdpsq_db(sq);
1045         mlx5_wq_destroy(&sq->wq_ctrl);
1046 }
1047
1048 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1049 {
1050         kvfree(sq->db.ico_wqe);
1051 }
1052
1053 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1054 {
1055         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1056
1057         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1058                                                   sizeof(*sq->db.ico_wqe)),
1059                                        GFP_KERNEL, numa);
1060         if (!sq->db.ico_wqe)
1061                 return -ENOMEM;
1062
1063         return 0;
1064 }
1065
1066 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1067                              struct mlx5e_sq_param *param,
1068                              struct mlx5e_icosq *sq)
1069 {
1070         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1071         struct mlx5_core_dev *mdev = c->mdev;
1072         struct mlx5_wq_cyc *wq = &sq->wq;
1073         int err;
1074
1075         sq->channel   = c;
1076         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1077
1078         param->wq.db_numa_node = cpu_to_node(c->cpu);
1079         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1080         if (err)
1081                 return err;
1082         wq->db = &wq->db[MLX5_SND_DBR];
1083
1084         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1085         if (err)
1086                 goto err_sq_wq_destroy;
1087
1088         return 0;
1089
1090 err_sq_wq_destroy:
1091         mlx5_wq_destroy(&sq->wq_ctrl);
1092
1093         return err;
1094 }
1095
1096 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1097 {
1098         mlx5e_free_icosq_db(sq);
1099         mlx5_wq_destroy(&sq->wq_ctrl);
1100 }
1101
1102 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1103 {
1104         kvfree(sq->db.wqe_info);
1105         kvfree(sq->db.dma_fifo);
1106 }
1107
1108 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1109 {
1110         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1111         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1112
1113         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1114                                                    sizeof(*sq->db.dma_fifo)),
1115                                         GFP_KERNEL, numa);
1116         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1117                                                    sizeof(*sq->db.wqe_info)),
1118                                         GFP_KERNEL, numa);
1119         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1120                 mlx5e_free_txqsq_db(sq);
1121                 return -ENOMEM;
1122         }
1123
1124         sq->dma_fifo_mask = df_sz - 1;
1125
1126         return 0;
1127 }
1128
1129 static void mlx5e_sq_recover(struct work_struct *work);
1130 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1131                              int txq_ix,
1132                              struct mlx5e_params *params,
1133                              struct mlx5e_sq_param *param,
1134                              struct mlx5e_txqsq *sq,
1135                              int tc)
1136 {
1137         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1138         struct mlx5_core_dev *mdev = c->mdev;
1139         struct mlx5_wq_cyc *wq = &sq->wq;
1140         int err;
1141
1142         sq->pdev      = c->pdev;
1143         sq->tstamp    = c->tstamp;
1144         sq->clock     = &mdev->clock;
1145         sq->mkey_be   = c->mkey_be;
1146         sq->channel   = c;
1147         sq->txq_ix    = txq_ix;
1148         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1149         sq->min_inline_mode = params->tx_min_inline_mode;
1150         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1151         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1152         if (MLX5_IPSEC_DEV(c->priv->mdev))
1153                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1154         if (mlx5_accel_is_tls_device(c->priv->mdev))
1155                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1156
1157         param->wq.db_numa_node = cpu_to_node(c->cpu);
1158         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1159         if (err)
1160                 return err;
1161         wq->db    = &wq->db[MLX5_SND_DBR];
1162
1163         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1164         if (err)
1165                 goto err_sq_wq_destroy;
1166
1167         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1168         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1169
1170         return 0;
1171
1172 err_sq_wq_destroy:
1173         mlx5_wq_destroy(&sq->wq_ctrl);
1174
1175         return err;
1176 }
1177
1178 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1179 {
1180         mlx5e_free_txqsq_db(sq);
1181         mlx5_wq_destroy(&sq->wq_ctrl);
1182 }
1183
1184 struct mlx5e_create_sq_param {
1185         struct mlx5_wq_ctrl        *wq_ctrl;
1186         u32                         cqn;
1187         u32                         tisn;
1188         u8                          tis_lst_sz;
1189         u8                          min_inline_mode;
1190 };
1191
1192 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1193                            struct mlx5e_sq_param *param,
1194                            struct mlx5e_create_sq_param *csp,
1195                            u32 *sqn)
1196 {
1197         void *in;
1198         void *sqc;
1199         void *wq;
1200         int inlen;
1201         int err;
1202
1203         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1204                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1205         in = kvzalloc(inlen, GFP_KERNEL);
1206         if (!in)
1207                 return -ENOMEM;
1208
1209         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1210         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1211
1212         memcpy(sqc, param->sqc, sizeof(param->sqc));
1213         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1214         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1215         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1216
1217         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1218                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1219
1220         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1221         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1222
1223         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1224         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1225         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1226                                           MLX5_ADAPTER_PAGE_SHIFT);
1227         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1228
1229         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1230                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1231
1232         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1233
1234         kvfree(in);
1235
1236         return err;
1237 }
1238
1239 struct mlx5e_modify_sq_param {
1240         int curr_state;
1241         int next_state;
1242         bool rl_update;
1243         int rl_index;
1244 };
1245
1246 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1247                            struct mlx5e_modify_sq_param *p)
1248 {
1249         void *in;
1250         void *sqc;
1251         int inlen;
1252         int err;
1253
1254         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1255         in = kvzalloc(inlen, GFP_KERNEL);
1256         if (!in)
1257                 return -ENOMEM;
1258
1259         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1260
1261         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1262         MLX5_SET(sqc, sqc, state, p->next_state);
1263         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1264                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1265                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1266         }
1267
1268         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1269
1270         kvfree(in);
1271
1272         return err;
1273 }
1274
1275 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1276 {
1277         mlx5_core_destroy_sq(mdev, sqn);
1278 }
1279
1280 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1281                                struct mlx5e_sq_param *param,
1282                                struct mlx5e_create_sq_param *csp,
1283                                u32 *sqn)
1284 {
1285         struct mlx5e_modify_sq_param msp = {0};
1286         int err;
1287
1288         err = mlx5e_create_sq(mdev, param, csp, sqn);
1289         if (err)
1290                 return err;
1291
1292         msp.curr_state = MLX5_SQC_STATE_RST;
1293         msp.next_state = MLX5_SQC_STATE_RDY;
1294         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1295         if (err)
1296                 mlx5e_destroy_sq(mdev, *sqn);
1297
1298         return err;
1299 }
1300
1301 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1302                                 struct mlx5e_txqsq *sq, u32 rate);
1303
1304 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1305                             u32 tisn,
1306                             int txq_ix,
1307                             struct mlx5e_params *params,
1308                             struct mlx5e_sq_param *param,
1309                             struct mlx5e_txqsq *sq,
1310                             int tc)
1311 {
1312         struct mlx5e_create_sq_param csp = {};
1313         u32 tx_rate;
1314         int err;
1315
1316         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1317         if (err)
1318                 return err;
1319
1320         csp.tisn            = tisn;
1321         csp.tis_lst_sz      = 1;
1322         csp.cqn             = sq->cq.mcq.cqn;
1323         csp.wq_ctrl         = &sq->wq_ctrl;
1324         csp.min_inline_mode = sq->min_inline_mode;
1325         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1326         if (err)
1327                 goto err_free_txqsq;
1328
1329         tx_rate = c->priv->tx_rates[sq->txq_ix];
1330         if (tx_rate)
1331                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1332
1333         if (params->tx_dim_enabled)
1334                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1335
1336         return 0;
1337
1338 err_free_txqsq:
1339         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1340         mlx5e_free_txqsq(sq);
1341
1342         return err;
1343 }
1344
1345 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1346 {
1347         WARN_ONCE(sq->cc != sq->pc,
1348                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1349                   sq->sqn, sq->cc, sq->pc);
1350         sq->cc = 0;
1351         sq->dma_fifo_cc = 0;
1352         sq->pc = 0;
1353 }
1354
1355 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1356 {
1357         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1358         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1359         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1360         netdev_tx_reset_queue(sq->txq);
1361         netif_tx_start_queue(sq->txq);
1362 }
1363
1364 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1365 {
1366         __netif_tx_lock_bh(txq);
1367         netif_tx_stop_queue(txq);
1368         __netif_tx_unlock_bh(txq);
1369 }
1370
1371 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1372 {
1373         struct mlx5e_channel *c = sq->channel;
1374         struct mlx5_wq_cyc *wq = &sq->wq;
1375
1376         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1377         /* prevent netif_tx_wake_queue */
1378         napi_synchronize(&c->napi);
1379
1380         netif_tx_disable_queue(sq->txq);
1381
1382         /* last doorbell out, godspeed .. */
1383         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1384                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1385                 struct mlx5e_tx_wqe *nop;
1386
1387                 sq->db.wqe_info[pi].skb = NULL;
1388                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1389                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1390         }
1391 }
1392
1393 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1394 {
1395         struct mlx5e_channel *c = sq->channel;
1396         struct mlx5_core_dev *mdev = c->mdev;
1397         struct mlx5_rate_limit rl = {0};
1398
1399         mlx5e_destroy_sq(mdev, sq->sqn);
1400         if (sq->rate_limit) {
1401                 rl.rate = sq->rate_limit;
1402                 mlx5_rl_remove_rate(mdev, &rl);
1403         }
1404         mlx5e_free_txqsq_descs(sq);
1405         mlx5e_free_txqsq(sq);
1406 }
1407
1408 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1409 {
1410         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1411
1412         while (time_before(jiffies, exp_time)) {
1413                 if (sq->cc == sq->pc)
1414                         return 0;
1415
1416                 msleep(20);
1417         }
1418
1419         netdev_err(sq->channel->netdev,
1420                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1421                    sq->sqn, sq->cc, sq->pc);
1422
1423         return -ETIMEDOUT;
1424 }
1425
1426 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1427 {
1428         struct mlx5_core_dev *mdev = sq->channel->mdev;
1429         struct net_device *dev = sq->channel->netdev;
1430         struct mlx5e_modify_sq_param msp = {0};
1431         int err;
1432
1433         msp.curr_state = curr_state;
1434         msp.next_state = MLX5_SQC_STATE_RST;
1435
1436         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1437         if (err) {
1438                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1439                 return err;
1440         }
1441
1442         memset(&msp, 0, sizeof(msp));
1443         msp.curr_state = MLX5_SQC_STATE_RST;
1444         msp.next_state = MLX5_SQC_STATE_RDY;
1445
1446         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1447         if (err) {
1448                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1449                 return err;
1450         }
1451
1452         return 0;
1453 }
1454
1455 static void mlx5e_sq_recover(struct work_struct *work)
1456 {
1457         struct mlx5e_txqsq_recover *recover =
1458                 container_of(work, struct mlx5e_txqsq_recover,
1459                              recover_work);
1460         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1461                                               recover);
1462         struct mlx5_core_dev *mdev = sq->channel->mdev;
1463         struct net_device *dev = sq->channel->netdev;
1464         u8 state;
1465         int err;
1466
1467         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1468         if (err) {
1469                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1470                            sq->sqn, err);
1471                 return;
1472         }
1473
1474         if (state != MLX5_RQC_STATE_ERR) {
1475                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1476                 return;
1477         }
1478
1479         netif_tx_disable_queue(sq->txq);
1480
1481         if (mlx5e_wait_for_sq_flush(sq))
1482                 return;
1483
1484         /* If the interval between two consecutive recovers per SQ is too
1485          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1486          * If we reached this state, there is probably a bug that needs to be
1487          * fixed. let's keep the queue close and let tx timeout cleanup.
1488          */
1489         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1490             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1491                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1492                            sq->sqn);
1493                 return;
1494         }
1495
1496         /* At this point, no new packets will arrive from the stack as TXQ is
1497          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1498          * pending WQEs.  SQ can safely reset the SQ.
1499          */
1500         if (mlx5e_sq_to_ready(sq, state))
1501                 return;
1502
1503         mlx5e_reset_txqsq_cc_pc(sq);
1504         sq->stats->recover++;
1505         recover->last_recover = jiffies;
1506         mlx5e_activate_txqsq(sq);
1507 }
1508
1509 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1510                             struct mlx5e_params *params,
1511                             struct mlx5e_sq_param *param,
1512                             struct mlx5e_icosq *sq)
1513 {
1514         struct mlx5e_create_sq_param csp = {};
1515         int err;
1516
1517         err = mlx5e_alloc_icosq(c, param, sq);
1518         if (err)
1519                 return err;
1520
1521         csp.cqn             = sq->cq.mcq.cqn;
1522         csp.wq_ctrl         = &sq->wq_ctrl;
1523         csp.min_inline_mode = params->tx_min_inline_mode;
1524         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1525         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1526         if (err)
1527                 goto err_free_icosq;
1528
1529         return 0;
1530
1531 err_free_icosq:
1532         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1533         mlx5e_free_icosq(sq);
1534
1535         return err;
1536 }
1537
1538 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1539 {
1540         struct mlx5e_channel *c = sq->channel;
1541
1542         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1543         napi_synchronize(&c->napi);
1544
1545         mlx5e_destroy_sq(c->mdev, sq->sqn);
1546         mlx5e_free_icosq(sq);
1547 }
1548
1549 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1550                             struct mlx5e_params *params,
1551                             struct mlx5e_sq_param *param,
1552                             struct mlx5e_xdpsq *sq,
1553                             bool is_redirect)
1554 {
1555         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1556         struct mlx5e_create_sq_param csp = {};
1557         unsigned int inline_hdr_sz = 0;
1558         int err;
1559         int i;
1560
1561         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1562         if (err)
1563                 return err;
1564
1565         csp.tis_lst_sz      = 1;
1566         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1567         csp.cqn             = sq->cq.mcq.cqn;
1568         csp.wq_ctrl         = &sq->wq_ctrl;
1569         csp.min_inline_mode = sq->min_inline_mode;
1570         if (is_redirect)
1571                 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1572         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1573         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1574         if (err)
1575                 goto err_free_xdpsq;
1576
1577         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1578                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1579                 ds_cnt++;
1580         }
1581
1582         /* Pre initialize fixed WQE fields */
1583         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1584                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1585                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1586                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1587                 struct mlx5_wqe_data_seg *dseg;
1588
1589                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1590                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1591
1592                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1593                 dseg->lkey = sq->mkey_be;
1594         }
1595
1596         return 0;
1597
1598 err_free_xdpsq:
1599         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1600         mlx5e_free_xdpsq(sq);
1601
1602         return err;
1603 }
1604
1605 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1606 {
1607         struct mlx5e_channel *c = sq->channel;
1608
1609         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1610         napi_synchronize(&c->napi);
1611
1612         mlx5e_destroy_sq(c->mdev, sq->sqn);
1613         mlx5e_free_xdpsq_descs(sq);
1614         mlx5e_free_xdpsq(sq);
1615 }
1616
1617 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1618                                  struct mlx5e_cq_param *param,
1619                                  struct mlx5e_cq *cq)
1620 {
1621         struct mlx5_core_cq *mcq = &cq->mcq;
1622         int eqn_not_used;
1623         unsigned int irqn;
1624         int err;
1625         u32 i;
1626
1627         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1628         if (err)
1629                 return err;
1630
1631         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1632                                &cq->wq_ctrl);
1633         if (err)
1634                 return err;
1635
1636         mcq->cqe_sz     = 64;
1637         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1638         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1639         *mcq->set_ci_db = 0;
1640         *mcq->arm_db    = 0;
1641         mcq->vector     = param->eq_ix;
1642         mcq->comp       = mlx5e_completion_event;
1643         mcq->event      = mlx5e_cq_error_event;
1644         mcq->irqn       = irqn;
1645
1646         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1647                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1648
1649                 cqe->op_own = 0xf1;
1650         }
1651
1652         cq->mdev = mdev;
1653
1654         return 0;
1655 }
1656
1657 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1658                           struct mlx5e_cq_param *param,
1659                           struct mlx5e_cq *cq)
1660 {
1661         struct mlx5_core_dev *mdev = c->priv->mdev;
1662         int err;
1663
1664         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1665         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1666         param->eq_ix   = c->ix;
1667
1668         err = mlx5e_alloc_cq_common(mdev, param, cq);
1669
1670         cq->napi    = &c->napi;
1671         cq->channel = c;
1672
1673         return err;
1674 }
1675
1676 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1677 {
1678         mlx5_wq_destroy(&cq->wq_ctrl);
1679 }
1680
1681 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1682 {
1683         struct mlx5_core_dev *mdev = cq->mdev;
1684         struct mlx5_core_cq *mcq = &cq->mcq;
1685
1686         void *in;
1687         void *cqc;
1688         int inlen;
1689         unsigned int irqn_not_used;
1690         int eqn;
1691         int err;
1692
1693         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1694         if (err)
1695                 return err;
1696
1697         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1698                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1699         in = kvzalloc(inlen, GFP_KERNEL);
1700         if (!in)
1701                 return -ENOMEM;
1702
1703         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1704
1705         memcpy(cqc, param->cqc, sizeof(param->cqc));
1706
1707         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1708                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1709
1710         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1711         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1712         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1713         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1714                                             MLX5_ADAPTER_PAGE_SHIFT);
1715         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1716
1717         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1718
1719         kvfree(in);
1720
1721         if (err)
1722                 return err;
1723
1724         mlx5e_cq_arm(cq);
1725
1726         return 0;
1727 }
1728
1729 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1730 {
1731         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1732 }
1733
1734 static int mlx5e_open_cq(struct mlx5e_channel *c,
1735                          struct net_dim_cq_moder moder,
1736                          struct mlx5e_cq_param *param,
1737                          struct mlx5e_cq *cq)
1738 {
1739         struct mlx5_core_dev *mdev = c->mdev;
1740         int err;
1741
1742         err = mlx5e_alloc_cq(c, param, cq);
1743         if (err)
1744                 return err;
1745
1746         err = mlx5e_create_cq(cq, param);
1747         if (err)
1748                 goto err_free_cq;
1749
1750         if (MLX5_CAP_GEN(mdev, cq_moderation))
1751                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1752         return 0;
1753
1754 err_free_cq:
1755         mlx5e_free_cq(cq);
1756
1757         return err;
1758 }
1759
1760 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1761 {
1762         mlx5e_destroy_cq(cq);
1763         mlx5e_free_cq(cq);
1764 }
1765
1766 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1767 {
1768         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1769 }
1770
1771 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1772                              struct mlx5e_params *params,
1773                              struct mlx5e_channel_param *cparam)
1774 {
1775         int err;
1776         int tc;
1777
1778         for (tc = 0; tc < c->num_tc; tc++) {
1779                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1780                                     &cparam->tx_cq, &c->sq[tc].cq);
1781                 if (err)
1782                         goto err_close_tx_cqs;
1783         }
1784
1785         return 0;
1786
1787 err_close_tx_cqs:
1788         for (tc--; tc >= 0; tc--)
1789                 mlx5e_close_cq(&c->sq[tc].cq);
1790
1791         return err;
1792 }
1793
1794 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1795 {
1796         int tc;
1797
1798         for (tc = 0; tc < c->num_tc; tc++)
1799                 mlx5e_close_cq(&c->sq[tc].cq);
1800 }
1801
1802 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1803                           struct mlx5e_params *params,
1804                           struct mlx5e_channel_param *cparam)
1805 {
1806         struct mlx5e_priv *priv = c->priv;
1807         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1808
1809         for (tc = 0; tc < params->num_tc; tc++) {
1810                 int txq_ix = c->ix + tc * max_nch;
1811
1812                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1813                                        params, &cparam->sq, &c->sq[tc], tc);
1814                 if (err)
1815                         goto err_close_sqs;
1816         }
1817
1818         return 0;
1819
1820 err_close_sqs:
1821         for (tc--; tc >= 0; tc--)
1822                 mlx5e_close_txqsq(&c->sq[tc]);
1823
1824         return err;
1825 }
1826
1827 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1828 {
1829         int tc;
1830
1831         for (tc = 0; tc < c->num_tc; tc++)
1832                 mlx5e_close_txqsq(&c->sq[tc]);
1833 }
1834
1835 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1836                                 struct mlx5e_txqsq *sq, u32 rate)
1837 {
1838         struct mlx5e_priv *priv = netdev_priv(dev);
1839         struct mlx5_core_dev *mdev = priv->mdev;
1840         struct mlx5e_modify_sq_param msp = {0};
1841         struct mlx5_rate_limit rl = {0};
1842         u16 rl_index = 0;
1843         int err;
1844
1845         if (rate == sq->rate_limit)
1846                 /* nothing to do */
1847                 return 0;
1848
1849         if (sq->rate_limit) {
1850                 rl.rate = sq->rate_limit;
1851                 /* remove current rl index to free space to next ones */
1852                 mlx5_rl_remove_rate(mdev, &rl);
1853         }
1854
1855         sq->rate_limit = 0;
1856
1857         if (rate) {
1858                 rl.rate = rate;
1859                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1860                 if (err) {
1861                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1862                                    rate, err);
1863                         return err;
1864                 }
1865         }
1866
1867         msp.curr_state = MLX5_SQC_STATE_RDY;
1868         msp.next_state = MLX5_SQC_STATE_RDY;
1869         msp.rl_index   = rl_index;
1870         msp.rl_update  = true;
1871         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1872         if (err) {
1873                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1874                            rate, err);
1875                 /* remove the rate from the table */
1876                 if (rate)
1877                         mlx5_rl_remove_rate(mdev, &rl);
1878                 return err;
1879         }
1880
1881         sq->rate_limit = rate;
1882         return 0;
1883 }
1884
1885 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1886 {
1887         struct mlx5e_priv *priv = netdev_priv(dev);
1888         struct mlx5_core_dev *mdev = priv->mdev;
1889         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1890         int err = 0;
1891
1892         if (!mlx5_rl_is_supported(mdev)) {
1893                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1894                 return -EINVAL;
1895         }
1896
1897         /* rate is given in Mb/sec, HW config is in Kb/sec */
1898         rate = rate << 10;
1899
1900         /* Check whether rate in valid range, 0 is always valid */
1901         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1902                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1903                 return -ERANGE;
1904         }
1905
1906         mutex_lock(&priv->state_lock);
1907         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1908                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1909         if (!err)
1910                 priv->tx_rates[index] = rate;
1911         mutex_unlock(&priv->state_lock);
1912
1913         return err;
1914 }
1915
1916 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1917                               struct mlx5e_params *params,
1918                               struct mlx5e_channel_param *cparam,
1919                               struct mlx5e_channel **cp)
1920 {
1921         struct net_dim_cq_moder icocq_moder = {0, 0};
1922         struct net_device *netdev = priv->netdev;
1923         int cpu = mlx5e_get_cpu(priv, ix);
1924         struct mlx5e_channel *c;
1925         unsigned int irq;
1926         int err;
1927         int eqn;
1928
1929         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1930         if (err)
1931                 return err;
1932
1933         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1934         if (!c)
1935                 return -ENOMEM;
1936
1937         c->priv     = priv;
1938         c->mdev     = priv->mdev;
1939         c->tstamp   = &priv->tstamp;
1940         c->ix       = ix;
1941         c->cpu      = cpu;
1942         c->pdev     = &priv->mdev->pdev->dev;
1943         c->netdev   = priv->netdev;
1944         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1945         c->num_tc   = params->num_tc;
1946         c->xdp      = !!params->xdp_prog;
1947         c->stats    = &priv->channel_stats[ix].ch;
1948
1949         c->irq_desc = irq_to_desc(irq);
1950
1951         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1952
1953         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1954         if (err)
1955                 goto err_napi_del;
1956
1957         err = mlx5e_open_tx_cqs(c, params, cparam);
1958         if (err)
1959                 goto err_close_icosq_cq;
1960
1961         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1962         if (err)
1963                 goto err_close_tx_cqs;
1964
1965         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1966         if (err)
1967                 goto err_close_xdp_tx_cqs;
1968
1969         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1970         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1971                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1972         if (err)
1973                 goto err_close_rx_cq;
1974
1975         napi_enable(&c->napi);
1976
1977         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1978         if (err)
1979                 goto err_disable_napi;
1980
1981         err = mlx5e_open_sqs(c, params, cparam);
1982         if (err)
1983                 goto err_close_icosq;
1984
1985         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1986         if (err)
1987                 goto err_close_sqs;
1988
1989         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1990         if (err)
1991                 goto err_close_xdp_sq;
1992
1993         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1994         if (err)
1995                 goto err_close_rq;
1996
1997         *cp = c;
1998
1999         return 0;
2000
2001 err_close_rq:
2002         mlx5e_close_rq(&c->rq);
2003
2004 err_close_xdp_sq:
2005         if (c->xdp)
2006                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2007
2008 err_close_sqs:
2009         mlx5e_close_sqs(c);
2010
2011 err_close_icosq:
2012         mlx5e_close_icosq(&c->icosq);
2013
2014 err_disable_napi:
2015         napi_disable(&c->napi);
2016         if (c->xdp)
2017                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2018
2019 err_close_rx_cq:
2020         mlx5e_close_cq(&c->rq.cq);
2021
2022 err_close_xdp_tx_cqs:
2023         mlx5e_close_cq(&c->xdpsq.cq);
2024
2025 err_close_tx_cqs:
2026         mlx5e_close_tx_cqs(c);
2027
2028 err_close_icosq_cq:
2029         mlx5e_close_cq(&c->icosq.cq);
2030
2031 err_napi_del:
2032         netif_napi_del(&c->napi);
2033         kvfree(c);
2034
2035         return err;
2036 }
2037
2038 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2039 {
2040         int tc;
2041
2042         for (tc = 0; tc < c->num_tc; tc++)
2043                 mlx5e_activate_txqsq(&c->sq[tc]);
2044         mlx5e_activate_rq(&c->rq);
2045         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2046 }
2047
2048 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2049 {
2050         int tc;
2051
2052         mlx5e_deactivate_rq(&c->rq);
2053         for (tc = 0; tc < c->num_tc; tc++)
2054                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2055 }
2056
2057 static void mlx5e_close_channel(struct mlx5e_channel *c)
2058 {
2059         mlx5e_close_xdpsq(&c->xdpsq);
2060         mlx5e_close_rq(&c->rq);
2061         if (c->xdp)
2062                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2063         mlx5e_close_sqs(c);
2064         mlx5e_close_icosq(&c->icosq);
2065         napi_disable(&c->napi);
2066         if (c->xdp)
2067                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2068         mlx5e_close_cq(&c->rq.cq);
2069         mlx5e_close_cq(&c->xdpsq.cq);
2070         mlx5e_close_tx_cqs(c);
2071         mlx5e_close_cq(&c->icosq.cq);
2072         netif_napi_del(&c->napi);
2073
2074         kvfree(c);
2075 }
2076
2077 #define DEFAULT_FRAG_SIZE (2048)
2078
2079 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2080                                       struct mlx5e_params *params,
2081                                       struct mlx5e_rq_frags_info *info)
2082 {
2083         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2084         int frag_size_max = DEFAULT_FRAG_SIZE;
2085         u32 buf_size = 0;
2086         int i;
2087
2088 #ifdef CONFIG_MLX5_EN_IPSEC
2089         if (MLX5_IPSEC_DEV(mdev))
2090                 byte_count += MLX5E_METADATA_ETHER_LEN;
2091 #endif
2092
2093         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2094                 int frag_stride;
2095
2096                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2097                 frag_stride = roundup_pow_of_two(frag_stride);
2098
2099                 info->arr[0].frag_size = byte_count;
2100                 info->arr[0].frag_stride = frag_stride;
2101                 info->num_frags = 1;
2102                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2103                 goto out;
2104         }
2105
2106         if (byte_count > PAGE_SIZE +
2107             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2108                 frag_size_max = PAGE_SIZE;
2109
2110         i = 0;
2111         while (buf_size < byte_count) {
2112                 int frag_size = byte_count - buf_size;
2113
2114                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2115                         frag_size = min(frag_size, frag_size_max);
2116
2117                 info->arr[i].frag_size = frag_size;
2118                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2119
2120                 buf_size += frag_size;
2121                 i++;
2122         }
2123         info->num_frags = i;
2124         /* number of different wqes sharing a page */
2125         info->wqe_bulk = 1 + (info->num_frags % 2);
2126
2127 out:
2128         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2129         info->log_num_frags = order_base_2(info->num_frags);
2130 }
2131
2132 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2133 {
2134         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2135
2136         switch (wq_type) {
2137         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2138                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2139                 break;
2140         default: /* MLX5_WQ_TYPE_CYCLIC */
2141                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2142         }
2143
2144         return order_base_2(sz);
2145 }
2146
2147 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2148                                  struct mlx5e_params *params,
2149                                  struct mlx5e_rq_param *param)
2150 {
2151         struct mlx5_core_dev *mdev = priv->mdev;
2152         void *rqc = param->rqc;
2153         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2154         int ndsegs = 1;
2155
2156         switch (params->rq_wq_type) {
2157         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2158                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2159                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2160                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2161                 MLX5_SET(wq, wq, log_wqe_stride_size,
2162                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2163                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2164                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2165                 break;
2166         default: /* MLX5_WQ_TYPE_CYCLIC */
2167                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2168                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2169                 ndsegs = param->frags_info.num_frags;
2170         }
2171
2172         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2173         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2174         MLX5_SET(wq, wq, log_wq_stride,
2175                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2176         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2177         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2178         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2179         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2180
2181         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2182 }
2183
2184 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2185                                       struct mlx5e_rq_param *param)
2186 {
2187         struct mlx5_core_dev *mdev = priv->mdev;
2188         void *rqc = param->rqc;
2189         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2190
2191         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2192         MLX5_SET(wq, wq, log_wq_stride,
2193                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2194         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2195
2196         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2197 }
2198
2199 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2200                                         struct mlx5e_sq_param *param)
2201 {
2202         void *sqc = param->sqc;
2203         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2204
2205         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2206         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2207
2208         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2209 }
2210
2211 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2212                                  struct mlx5e_params *params,
2213                                  struct mlx5e_sq_param *param)
2214 {
2215         void *sqc = param->sqc;
2216         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2217
2218         mlx5e_build_sq_param_common(priv, param);
2219         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2220         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2221 }
2222
2223 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2224                                         struct mlx5e_cq_param *param)
2225 {
2226         void *cqc = param->cqc;
2227
2228         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2229 }
2230
2231 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2232                                     struct mlx5e_params *params,
2233                                     struct mlx5e_cq_param *param)
2234 {
2235         struct mlx5_core_dev *mdev = priv->mdev;
2236         void *cqc = param->cqc;
2237         u8 log_cq_size;
2238
2239         switch (params->rq_wq_type) {
2240         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2241                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2242                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2243                 break;
2244         default: /* MLX5_WQ_TYPE_CYCLIC */
2245                 log_cq_size = params->log_rq_mtu_frames;
2246         }
2247
2248         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2249         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2250                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2251                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2252         }
2253
2254         mlx5e_build_common_cq_param(priv, param);
2255         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2256 }
2257
2258 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2259                                     struct mlx5e_params *params,
2260                                     struct mlx5e_cq_param *param)
2261 {
2262         void *cqc = param->cqc;
2263
2264         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2265
2266         mlx5e_build_common_cq_param(priv, param);
2267         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2268 }
2269
2270 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2271                                      u8 log_wq_size,
2272                                      struct mlx5e_cq_param *param)
2273 {
2274         void *cqc = param->cqc;
2275
2276         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2277
2278         mlx5e_build_common_cq_param(priv, param);
2279
2280         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2281 }
2282
2283 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2284                                     u8 log_wq_size,
2285                                     struct mlx5e_sq_param *param)
2286 {
2287         void *sqc = param->sqc;
2288         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2289
2290         mlx5e_build_sq_param_common(priv, param);
2291
2292         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2293         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2294 }
2295
2296 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2297                                     struct mlx5e_params *params,
2298                                     struct mlx5e_sq_param *param)
2299 {
2300         void *sqc = param->sqc;
2301         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2302
2303         mlx5e_build_sq_param_common(priv, param);
2304         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2305 }
2306
2307 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2308                                       struct mlx5e_params *params,
2309                                       struct mlx5e_channel_param *cparam)
2310 {
2311         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2312
2313         mlx5e_build_rq_param(priv, params, &cparam->rq);
2314         mlx5e_build_sq_param(priv, params, &cparam->sq);
2315         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2316         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2317         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2318         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2319         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2320 }
2321
2322 int mlx5e_open_channels(struct mlx5e_priv *priv,
2323                         struct mlx5e_channels *chs)
2324 {
2325         struct mlx5e_channel_param *cparam;
2326         int err = -ENOMEM;
2327         int i;
2328
2329         chs->num = chs->params.num_channels;
2330
2331         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2332         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2333         if (!chs->c || !cparam)
2334                 goto err_free;
2335
2336         mlx5e_build_channel_param(priv, &chs->params, cparam);
2337         for (i = 0; i < chs->num; i++) {
2338                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2339                 if (err)
2340                         goto err_close_channels;
2341         }
2342
2343         kvfree(cparam);
2344         return 0;
2345
2346 err_close_channels:
2347         for (i--; i >= 0; i--)
2348                 mlx5e_close_channel(chs->c[i]);
2349
2350 err_free:
2351         kfree(chs->c);
2352         kvfree(cparam);
2353         chs->num = 0;
2354         return err;
2355 }
2356
2357 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2358 {
2359         int i;
2360
2361         for (i = 0; i < chs->num; i++)
2362                 mlx5e_activate_channel(chs->c[i]);
2363 }
2364
2365 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2366 {
2367         int err = 0;
2368         int i;
2369
2370         for (i = 0; i < chs->num; i++)
2371                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2372                                                   err ? 0 : 20000);
2373
2374         return err ? -ETIMEDOUT : 0;
2375 }
2376
2377 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2378 {
2379         int i;
2380
2381         for (i = 0; i < chs->num; i++)
2382                 mlx5e_deactivate_channel(chs->c[i]);
2383 }
2384
2385 void mlx5e_close_channels(struct mlx5e_channels *chs)
2386 {
2387         int i;
2388
2389         for (i = 0; i < chs->num; i++)
2390                 mlx5e_close_channel(chs->c[i]);
2391
2392         kfree(chs->c);
2393         chs->num = 0;
2394 }
2395
2396 static int
2397 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2398 {
2399         struct mlx5_core_dev *mdev = priv->mdev;
2400         void *rqtc;
2401         int inlen;
2402         int err;
2403         u32 *in;
2404         int i;
2405
2406         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2407         in = kvzalloc(inlen, GFP_KERNEL);
2408         if (!in)
2409                 return -ENOMEM;
2410
2411         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2412
2413         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2414         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2415
2416         for (i = 0; i < sz; i++)
2417                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2418
2419         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2420         if (!err)
2421                 rqt->enabled = true;
2422
2423         kvfree(in);
2424         return err;
2425 }
2426
2427 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2428 {
2429         rqt->enabled = false;
2430         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2431 }
2432
2433 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2434 {
2435         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2436         int err;
2437
2438         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2439         if (err)
2440                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2441         return err;
2442 }
2443
2444 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2445 {
2446         struct mlx5e_rqt *rqt;
2447         int err;
2448         int ix;
2449
2450         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2451                 rqt = &priv->direct_tir[ix].rqt;
2452                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2453                 if (err)
2454                         goto err_destroy_rqts;
2455         }
2456
2457         return 0;
2458
2459 err_destroy_rqts:
2460         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2461         for (ix--; ix >= 0; ix--)
2462                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2463
2464         return err;
2465 }
2466
2467 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2468 {
2469         int i;
2470
2471         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2472                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2473 }
2474
2475 static int mlx5e_rx_hash_fn(int hfunc)
2476 {
2477         return (hfunc == ETH_RSS_HASH_TOP) ?
2478                MLX5_RX_HASH_FN_TOEPLITZ :
2479                MLX5_RX_HASH_FN_INVERTED_XOR8;
2480 }
2481
2482 int mlx5e_bits_invert(unsigned long a, int size)
2483 {
2484         int inv = 0;
2485         int i;
2486
2487         for (i = 0; i < size; i++)
2488                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2489
2490         return inv;
2491 }
2492
2493 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2494                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2495 {
2496         int i;
2497
2498         for (i = 0; i < sz; i++) {
2499                 u32 rqn;
2500
2501                 if (rrp.is_rss) {
2502                         int ix = i;
2503
2504                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2505                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2506
2507                         ix = priv->rss_params.indirection_rqt[ix];
2508                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2509                 } else {
2510                         rqn = rrp.rqn;
2511                 }
2512                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2513         }
2514 }
2515
2516 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2517                        struct mlx5e_redirect_rqt_param rrp)
2518 {
2519         struct mlx5_core_dev *mdev = priv->mdev;
2520         void *rqtc;
2521         int inlen;
2522         u32 *in;
2523         int err;
2524
2525         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2526         in = kvzalloc(inlen, GFP_KERNEL);
2527         if (!in)
2528                 return -ENOMEM;
2529
2530         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2531
2532         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2533         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2534         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2535         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2536
2537         kvfree(in);
2538         return err;
2539 }
2540
2541 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2542                                 struct mlx5e_redirect_rqt_param rrp)
2543 {
2544         if (!rrp.is_rss)
2545                 return rrp.rqn;
2546
2547         if (ix >= rrp.rss.channels->num)
2548                 return priv->drop_rq.rqn;
2549
2550         return rrp.rss.channels->c[ix]->rq.rqn;
2551 }
2552
2553 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2554                                 struct mlx5e_redirect_rqt_param rrp)
2555 {
2556         u32 rqtn;
2557         int ix;
2558
2559         if (priv->indir_rqt.enabled) {
2560                 /* RSS RQ table */
2561                 rqtn = priv->indir_rqt.rqtn;
2562                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2563         }
2564
2565         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2566                 struct mlx5e_redirect_rqt_param direct_rrp = {
2567                         .is_rss = false,
2568                         {
2569                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2570                         },
2571                 };
2572
2573                 /* Direct RQ Tables */
2574                 if (!priv->direct_tir[ix].rqt.enabled)
2575                         continue;
2576
2577                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2578                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2579         }
2580 }
2581
2582 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2583                                             struct mlx5e_channels *chs)
2584 {
2585         struct mlx5e_redirect_rqt_param rrp = {
2586                 .is_rss        = true,
2587                 {
2588                         .rss = {
2589                                 .channels  = chs,
2590                                 .hfunc     = priv->rss_params.hfunc,
2591                         }
2592                 },
2593         };
2594
2595         mlx5e_redirect_rqts(priv, rrp);
2596 }
2597
2598 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2599 {
2600         struct mlx5e_redirect_rqt_param drop_rrp = {
2601                 .is_rss = false,
2602                 {
2603                         .rqn = priv->drop_rq.rqn,
2604                 },
2605         };
2606
2607         mlx5e_redirect_rqts(priv, drop_rrp);
2608 }
2609
2610 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2611         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2612                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2613                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2614         },
2615         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2616                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2617                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2618         },
2619         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2620                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2621                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2622         },
2623         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2624                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2625                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2626         },
2627         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2628                                      .l4_prot_type = 0,
2629                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2630         },
2631         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2632                                      .l4_prot_type = 0,
2633                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2634         },
2635         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2636                                       .l4_prot_type = 0,
2637                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2638         },
2639         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2640                                       .l4_prot_type = 0,
2641                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2642         },
2643         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2644                             .l4_prot_type = 0,
2645                             .rx_hash_fields = MLX5_HASH_IP,
2646         },
2647         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2648                             .l4_prot_type = 0,
2649                             .rx_hash_fields = MLX5_HASH_IP,
2650         },
2651 };
2652
2653 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2654 {
2655         return tirc_default_config[tt];
2656 }
2657
2658 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2659 {
2660         if (!params->lro_en)
2661                 return;
2662
2663 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2664
2665         MLX5_SET(tirc, tirc, lro_enable_mask,
2666                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2667                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2668         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2669                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2670         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2671 }
2672
2673 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2674                                     const struct mlx5e_tirc_config *ttconfig,
2675                                     void *tirc, bool inner)
2676 {
2677         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2678                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2679
2680         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2681         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2682                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2683                                              rx_hash_toeplitz_key);
2684                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2685                                                rx_hash_toeplitz_key);
2686
2687                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2688                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2689         }
2690         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2691                  ttconfig->l3_prot_type);
2692         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2693                  ttconfig->l4_prot_type);
2694         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695                  ttconfig->rx_hash_fields);
2696 }
2697
2698 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2699 {
2700         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2701         struct mlx5_core_dev *mdev = priv->mdev;
2702         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2703         int tt;
2704
2705         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2706
2707         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2708                 memset(tirc, 0, ctxlen);
2709                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
2710                                                &tirc_default_config[tt],
2711                                                tirc, false);
2712                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2713         }
2714
2715         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2716                 return;
2717
2718         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2719                 memset(tirc, 0, ctxlen);
2720                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
2721                                                &tirc_default_config[tt],
2722                                                tirc, true);
2723                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2724                                      inlen);
2725         }
2726 }
2727
2728 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2729 {
2730         struct mlx5_core_dev *mdev = priv->mdev;
2731
2732         void *in;
2733         void *tirc;
2734         int inlen;
2735         int err;
2736         int tt;
2737         int ix;
2738
2739         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2740         in = kvzalloc(inlen, GFP_KERNEL);
2741         if (!in)
2742                 return -ENOMEM;
2743
2744         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2745         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2746
2747         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2748
2749         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2750                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2751                                            inlen);
2752                 if (err)
2753                         goto free_in;
2754         }
2755
2756         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2757                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2758                                            in, inlen);
2759                 if (err)
2760                         goto free_in;
2761         }
2762
2763 free_in:
2764         kvfree(in);
2765
2766         return err;
2767 }
2768
2769 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2770                                             enum mlx5e_traffic_types tt,
2771                                             u32 *tirc)
2772 {
2773         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2774
2775         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2776
2777         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2778         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2779         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2780
2781         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
2782                                        &tirc_default_config[tt], tirc, true);
2783 }
2784
2785 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2786                          struct mlx5e_params *params, u16 mtu)
2787 {
2788         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2789         int err;
2790
2791         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2792         if (err)
2793                 return err;
2794
2795         /* Update vport context MTU */
2796         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2797         return 0;
2798 }
2799
2800 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2801                             struct mlx5e_params *params, u16 *mtu)
2802 {
2803         u16 hw_mtu = 0;
2804         int err;
2805
2806         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2807         if (err || !hw_mtu) /* fallback to port oper mtu */
2808                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2809
2810         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2811 }
2812
2813 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2814 {
2815         struct mlx5e_params *params = &priv->channels.params;
2816         struct net_device *netdev = priv->netdev;
2817         struct mlx5_core_dev *mdev = priv->mdev;
2818         u16 mtu;
2819         int err;
2820
2821         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2822         if (err)
2823                 return err;
2824
2825         mlx5e_query_mtu(mdev, params, &mtu);
2826         if (mtu != params->sw_mtu)
2827                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2828                             __func__, mtu, params->sw_mtu);
2829
2830         params->sw_mtu = mtu;
2831         return 0;
2832 }
2833
2834 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2835 {
2836         struct mlx5e_priv *priv = netdev_priv(netdev);
2837         int nch = priv->channels.params.num_channels;
2838         int ntc = priv->channels.params.num_tc;
2839         int tc;
2840
2841         netdev_reset_tc(netdev);
2842
2843         if (ntc == 1)
2844                 return;
2845
2846         netdev_set_num_tc(netdev, ntc);
2847
2848         /* Map netdev TCs to offset 0
2849          * We have our own UP to TXQ mapping for QoS
2850          */
2851         for (tc = 0; tc < ntc; tc++)
2852                 netdev_set_tc_queue(netdev, tc, nch, 0);
2853 }
2854
2855 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2856 {
2857         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2858         int i, tc;
2859
2860         for (i = 0; i < max_nch; i++)
2861                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2862                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2863 }
2864
2865 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2866 {
2867         struct mlx5e_channel *c;
2868         struct mlx5e_txqsq *sq;
2869         int i, tc;
2870
2871         for (i = 0; i < priv->channels.num; i++) {
2872                 c = priv->channels.c[i];
2873                 for (tc = 0; tc < c->num_tc; tc++) {
2874                         sq = &c->sq[tc];
2875                         priv->txq2sq[sq->txq_ix] = sq;
2876                 }
2877         }
2878 }
2879
2880 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2881 {
2882         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2883         struct net_device *netdev = priv->netdev;
2884
2885         mlx5e_netdev_set_tcs(netdev);
2886         netif_set_real_num_tx_queues(netdev, num_txqs);
2887         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2888
2889         mlx5e_build_tx2sq_maps(priv);
2890         mlx5e_activate_channels(&priv->channels);
2891         netif_tx_start_all_queues(priv->netdev);
2892
2893         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2894                 mlx5e_add_sqs_fwd_rules(priv);
2895
2896         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2897         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2898 }
2899
2900 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2901 {
2902         mlx5e_redirect_rqts_to_drop(priv);
2903
2904         if (MLX5_ESWITCH_MANAGER(priv->mdev))
2905                 mlx5e_remove_sqs_fwd_rules(priv);
2906
2907         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2908          * polling for inactive tx queues.
2909          */
2910         netif_tx_stop_all_queues(priv->netdev);
2911         netif_tx_disable(priv->netdev);
2912         mlx5e_deactivate_channels(&priv->channels);
2913 }
2914
2915 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2916                                 struct mlx5e_channels *new_chs,
2917                                 mlx5e_fp_hw_modify hw_modify)
2918 {
2919         struct net_device *netdev = priv->netdev;
2920         int new_num_txqs;
2921         int carrier_ok;
2922         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2923
2924         carrier_ok = netif_carrier_ok(netdev);
2925         netif_carrier_off(netdev);
2926
2927         if (new_num_txqs < netdev->real_num_tx_queues)
2928                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2929
2930         mlx5e_deactivate_priv_channels(priv);
2931         mlx5e_close_channels(&priv->channels);
2932
2933         priv->channels = *new_chs;
2934
2935         /* New channels are ready to roll, modify HW settings if needed */
2936         if (hw_modify)
2937                 hw_modify(priv);
2938
2939         mlx5e_refresh_tirs(priv, false);
2940         mlx5e_activate_priv_channels(priv);
2941
2942         /* return carrier back if needed */
2943         if (carrier_ok)
2944                 netif_carrier_on(netdev);
2945 }
2946
2947 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2948 {
2949         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2950         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2951 }
2952
2953 int mlx5e_open_locked(struct net_device *netdev)
2954 {
2955         struct mlx5e_priv *priv = netdev_priv(netdev);
2956         int err;
2957
2958         set_bit(MLX5E_STATE_OPENED, &priv->state);
2959
2960         err = mlx5e_open_channels(priv, &priv->channels);
2961         if (err)
2962                 goto err_clear_state_opened_flag;
2963
2964         mlx5e_refresh_tirs(priv, false);
2965         mlx5e_activate_priv_channels(priv);
2966         if (priv->profile->update_carrier)
2967                 priv->profile->update_carrier(priv);
2968
2969         mlx5e_queue_update_stats(priv);
2970         return 0;
2971
2972 err_clear_state_opened_flag:
2973         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2974         return err;
2975 }
2976
2977 int mlx5e_open(struct net_device *netdev)
2978 {
2979         struct mlx5e_priv *priv = netdev_priv(netdev);
2980         int err;
2981
2982         mutex_lock(&priv->state_lock);
2983         err = mlx5e_open_locked(netdev);
2984         if (!err)
2985                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2986         mutex_unlock(&priv->state_lock);
2987
2988         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
2989                 udp_tunnel_get_rx_info(netdev);
2990
2991         return err;
2992 }
2993
2994 int mlx5e_close_locked(struct net_device *netdev)
2995 {
2996         struct mlx5e_priv *priv = netdev_priv(netdev);
2997
2998         /* May already be CLOSED in case a previous configuration operation
2999          * (e.g RX/TX queue size change) that involves close&open failed.
3000          */
3001         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3002                 return 0;
3003
3004         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3005
3006         netif_carrier_off(priv->netdev);
3007         mlx5e_deactivate_priv_channels(priv);
3008         mlx5e_close_channels(&priv->channels);
3009
3010         return 0;
3011 }
3012
3013 int mlx5e_close(struct net_device *netdev)
3014 {
3015         struct mlx5e_priv *priv = netdev_priv(netdev);
3016         int err;
3017
3018         if (!netif_device_present(netdev))
3019                 return -ENODEV;
3020
3021         mutex_lock(&priv->state_lock);
3022         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3023         err = mlx5e_close_locked(netdev);
3024         mutex_unlock(&priv->state_lock);
3025
3026         return err;
3027 }
3028
3029 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3030                                struct mlx5e_rq *rq,
3031                                struct mlx5e_rq_param *param)
3032 {
3033         void *rqc = param->rqc;
3034         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3035         int err;
3036
3037         param->wq.db_numa_node = param->wq.buf_numa_node;
3038
3039         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3040                                  &rq->wq_ctrl);
3041         if (err)
3042                 return err;
3043
3044         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3045         xdp_rxq_info_unused(&rq->xdp_rxq);
3046
3047         rq->mdev = mdev;
3048
3049         return 0;
3050 }
3051
3052 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3053                                struct mlx5e_cq *cq,
3054                                struct mlx5e_cq_param *param)
3055 {
3056         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3057         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3058
3059         return mlx5e_alloc_cq_common(mdev, param, cq);
3060 }
3061
3062 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3063                        struct mlx5e_rq *drop_rq)
3064 {
3065         struct mlx5_core_dev *mdev = priv->mdev;
3066         struct mlx5e_cq_param cq_param = {};
3067         struct mlx5e_rq_param rq_param = {};
3068         struct mlx5e_cq *cq = &drop_rq->cq;
3069         int err;
3070
3071         mlx5e_build_drop_rq_param(priv, &rq_param);
3072
3073         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3074         if (err)
3075                 return err;
3076
3077         err = mlx5e_create_cq(cq, &cq_param);
3078         if (err)
3079                 goto err_free_cq;
3080
3081         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3082         if (err)
3083                 goto err_destroy_cq;
3084
3085         err = mlx5e_create_rq(drop_rq, &rq_param);
3086         if (err)
3087                 goto err_free_rq;
3088
3089         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3090         if (err)
3091                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3092
3093         return 0;
3094
3095 err_free_rq:
3096         mlx5e_free_rq(drop_rq);
3097
3098 err_destroy_cq:
3099         mlx5e_destroy_cq(cq);
3100
3101 err_free_cq:
3102         mlx5e_free_cq(cq);
3103
3104         return err;
3105 }
3106
3107 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3108 {
3109         mlx5e_destroy_rq(drop_rq);
3110         mlx5e_free_rq(drop_rq);
3111         mlx5e_destroy_cq(&drop_rq->cq);
3112         mlx5e_free_cq(&drop_rq->cq);
3113 }
3114
3115 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3116                      u32 underlay_qpn, u32 *tisn)
3117 {
3118         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3119         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3120
3121         MLX5_SET(tisc, tisc, prio, tc << 1);
3122         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3123         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3124
3125         if (mlx5_lag_is_lacp_owner(mdev))
3126                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3127
3128         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3129 }
3130
3131 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3132 {
3133         mlx5_core_destroy_tis(mdev, tisn);
3134 }
3135
3136 int mlx5e_create_tises(struct mlx5e_priv *priv)
3137 {
3138         int err;
3139         int tc;
3140
3141         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3142                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3143                 if (err)
3144                         goto err_close_tises;
3145         }
3146
3147         return 0;
3148
3149 err_close_tises:
3150         for (tc--; tc >= 0; tc--)
3151                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3152
3153         return err;
3154 }
3155
3156 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3157 {
3158         int tc;
3159
3160         for (tc = 0; tc < priv->profile->max_tc; tc++)
3161                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3162 }
3163
3164 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3165                                       enum mlx5e_traffic_types tt,
3166                                       u32 *tirc)
3167 {
3168         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3169
3170         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3171
3172         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3173         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3174
3175         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3176                                        &tirc_default_config[tt], tirc, false);
3177 }
3178
3179 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3180 {
3181         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3182
3183         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3184
3185         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3186         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3187         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3188 }
3189
3190 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3191 {
3192         struct mlx5e_tir *tir;
3193         void *tirc;
3194         int inlen;
3195         int i = 0;
3196         int err;
3197         u32 *in;
3198         int tt;
3199
3200         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3201         in = kvzalloc(inlen, GFP_KERNEL);
3202         if (!in)
3203                 return -ENOMEM;
3204
3205         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3206                 memset(in, 0, inlen);
3207                 tir = &priv->indir_tir[tt];
3208                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3209                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3210                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3211                 if (err) {
3212                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3213                         goto err_destroy_inner_tirs;
3214                 }
3215         }
3216
3217         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3218                 goto out;
3219
3220         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3221                 memset(in, 0, inlen);
3222                 tir = &priv->inner_indir_tir[i];
3223                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3224                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3225                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3226                 if (err) {
3227                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3228                         goto err_destroy_inner_tirs;
3229                 }
3230         }
3231
3232 out:
3233         kvfree(in);
3234
3235         return 0;
3236
3237 err_destroy_inner_tirs:
3238         for (i--; i >= 0; i--)
3239                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3240
3241         for (tt--; tt >= 0; tt--)
3242                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3243
3244         kvfree(in);
3245
3246         return err;
3247 }
3248
3249 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3250 {
3251         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3252         struct mlx5e_tir *tir;
3253         void *tirc;
3254         int inlen;
3255         int err;
3256         u32 *in;
3257         int ix;
3258
3259         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3260         in = kvzalloc(inlen, GFP_KERNEL);
3261         if (!in)
3262                 return -ENOMEM;
3263
3264         for (ix = 0; ix < nch; ix++) {
3265                 memset(in, 0, inlen);
3266                 tir = &priv->direct_tir[ix];
3267                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3268                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3269                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3270                 if (err)
3271                         goto err_destroy_ch_tirs;
3272         }
3273
3274         kvfree(in);
3275
3276         return 0;
3277
3278 err_destroy_ch_tirs:
3279         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3280         for (ix--; ix >= 0; ix--)
3281                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3282
3283         kvfree(in);
3284
3285         return err;
3286 }
3287
3288 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3289 {
3290         int i;
3291
3292         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3293                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3294
3295         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3296                 return;
3297
3298         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3299                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3300 }
3301
3302 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3303 {
3304         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3305         int i;
3306
3307         for (i = 0; i < nch; i++)
3308                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3309 }
3310
3311 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3312 {
3313         int err = 0;
3314         int i;
3315
3316         for (i = 0; i < chs->num; i++) {
3317                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3318                 if (err)
3319                         return err;
3320         }
3321
3322         return 0;
3323 }
3324
3325 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3326 {
3327         int err = 0;
3328         int i;
3329
3330         for (i = 0; i < chs->num; i++) {
3331                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3332                 if (err)
3333                         return err;
3334         }
3335
3336         return 0;
3337 }
3338
3339 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3340                                  struct tc_mqprio_qopt *mqprio)
3341 {
3342         struct mlx5e_priv *priv = netdev_priv(netdev);
3343         struct mlx5e_channels new_channels = {};
3344         u8 tc = mqprio->num_tc;
3345         int err = 0;
3346
3347         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3348
3349         if (tc && tc != MLX5E_MAX_NUM_TC)
3350                 return -EINVAL;
3351
3352         mutex_lock(&priv->state_lock);
3353
3354         new_channels.params = priv->channels.params;
3355         new_channels.params.num_tc = tc ? tc : 1;
3356
3357         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3358                 priv->channels.params = new_channels.params;
3359                 goto out;
3360         }
3361
3362         err = mlx5e_open_channels(priv, &new_channels);
3363         if (err)
3364                 goto out;
3365
3366         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3367                                     new_channels.params.num_tc);
3368         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3369 out:
3370         mutex_unlock(&priv->state_lock);
3371         return err;
3372 }
3373
3374 #ifdef CONFIG_MLX5_ESWITCH
3375 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3376                                      struct tc_cls_flower_offload *cls_flower,
3377                                      int flags)
3378 {
3379         switch (cls_flower->command) {
3380         case TC_CLSFLOWER_REPLACE:
3381                 return mlx5e_configure_flower(priv, cls_flower, flags);
3382         case TC_CLSFLOWER_DESTROY:
3383                 return mlx5e_delete_flower(priv, cls_flower, flags);
3384         case TC_CLSFLOWER_STATS:
3385                 return mlx5e_stats_flower(priv, cls_flower, flags);
3386         default:
3387                 return -EOPNOTSUPP;
3388         }
3389 }
3390
3391 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3392                                    void *cb_priv)
3393 {
3394         struct mlx5e_priv *priv = cb_priv;
3395
3396         switch (type) {
3397         case TC_SETUP_CLSFLOWER:
3398                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS);
3399         default:
3400                 return -EOPNOTSUPP;
3401         }
3402 }
3403
3404 static int mlx5e_setup_tc_block(struct net_device *dev,
3405                                 struct tc_block_offload *f)
3406 {
3407         struct mlx5e_priv *priv = netdev_priv(dev);
3408
3409         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3410                 return -EOPNOTSUPP;
3411
3412         switch (f->command) {
3413         case TC_BLOCK_BIND:
3414                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3415                                              priv, priv, f->extack);
3416         case TC_BLOCK_UNBIND:
3417                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3418                                         priv);
3419                 return 0;
3420         default:
3421                 return -EOPNOTSUPP;
3422         }
3423 }
3424 #endif
3425
3426 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3427                           void *type_data)
3428 {
3429         switch (type) {
3430 #ifdef CONFIG_MLX5_ESWITCH
3431         case TC_SETUP_BLOCK:
3432                 return mlx5e_setup_tc_block(dev, type_data);
3433 #endif
3434         case TC_SETUP_QDISC_MQPRIO:
3435                 return mlx5e_setup_tc_mqprio(dev, type_data);
3436         default:
3437                 return -EOPNOTSUPP;
3438         }
3439 }
3440
3441 static void
3442 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3443 {
3444         struct mlx5e_priv *priv = netdev_priv(dev);
3445         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3446         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3447         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3448
3449         /* update HW stats in background for next time */
3450         mlx5e_queue_update_stats(priv);
3451
3452         if (mlx5e_is_uplink_rep(priv)) {
3453                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3454                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3455                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3456                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3457         } else {
3458                 mlx5e_grp_sw_update_stats(priv);
3459                 stats->rx_packets = sstats->rx_packets;
3460                 stats->rx_bytes   = sstats->rx_bytes;
3461                 stats->tx_packets = sstats->tx_packets;
3462                 stats->tx_bytes   = sstats->tx_bytes;
3463                 stats->tx_dropped = sstats->tx_queue_dropped;
3464         }
3465
3466         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3467
3468         stats->rx_length_errors =
3469                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3470                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3471                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3472         stats->rx_crc_errors =
3473                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3474         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3475         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3476         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3477                            stats->rx_frame_errors;
3478         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3479
3480         /* vport multicast also counts packets that are dropped due to steering
3481          * or rx out of buffer
3482          */
3483         stats->multicast =
3484                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3485 }
3486
3487 static void mlx5e_set_rx_mode(struct net_device *dev)
3488 {
3489         struct mlx5e_priv *priv = netdev_priv(dev);
3490
3491         queue_work(priv->wq, &priv->set_rx_mode_work);
3492 }
3493
3494 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3495 {
3496         struct mlx5e_priv *priv = netdev_priv(netdev);
3497         struct sockaddr *saddr = addr;
3498
3499         if (!is_valid_ether_addr(saddr->sa_data))
3500                 return -EADDRNOTAVAIL;
3501
3502         netif_addr_lock_bh(netdev);
3503         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3504         netif_addr_unlock_bh(netdev);
3505
3506         queue_work(priv->wq, &priv->set_rx_mode_work);
3507
3508         return 0;
3509 }
3510
3511 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3512         do {                                            \
3513                 if (enable)                             \
3514                         *features |= feature;           \
3515                 else                                    \
3516                         *features &= ~feature;          \
3517         } while (0)
3518
3519 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3520
3521 static int set_feature_lro(struct net_device *netdev, bool enable)
3522 {
3523         struct mlx5e_priv *priv = netdev_priv(netdev);
3524         struct mlx5_core_dev *mdev = priv->mdev;
3525         struct mlx5e_channels new_channels = {};
3526         struct mlx5e_params *old_params;
3527         int err = 0;
3528         bool reset;
3529
3530         mutex_lock(&priv->state_lock);
3531
3532         old_params = &priv->channels.params;
3533         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3534                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3535                 err = -EINVAL;
3536                 goto out;
3537         }
3538
3539         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3540
3541         new_channels.params = *old_params;
3542         new_channels.params.lro_en = enable;
3543
3544         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3545                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3546                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3547                         reset = false;
3548         }
3549
3550         if (!reset) {
3551                 *old_params = new_channels.params;
3552                 err = mlx5e_modify_tirs_lro(priv);
3553                 goto out;
3554         }
3555
3556         err = mlx5e_open_channels(priv, &new_channels);
3557         if (err)
3558                 goto out;
3559
3560         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3561 out:
3562         mutex_unlock(&priv->state_lock);
3563         return err;
3564 }
3565
3566 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3567 {
3568         struct mlx5e_priv *priv = netdev_priv(netdev);
3569
3570         if (enable)
3571                 mlx5e_enable_cvlan_filter(priv);
3572         else
3573                 mlx5e_disable_cvlan_filter(priv);
3574
3575         return 0;
3576 }
3577
3578 #ifdef CONFIG_MLX5_ESWITCH
3579 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3580 {
3581         struct mlx5e_priv *priv = netdev_priv(netdev);
3582
3583         if (!enable && mlx5e_tc_num_filters(priv)) {
3584                 netdev_err(netdev,
3585                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3586                 return -EINVAL;
3587         }
3588
3589         return 0;
3590 }
3591 #endif
3592
3593 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3594 {
3595         struct mlx5e_priv *priv = netdev_priv(netdev);
3596         struct mlx5_core_dev *mdev = priv->mdev;
3597
3598         return mlx5_set_port_fcs(mdev, !enable);
3599 }
3600
3601 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3602 {
3603         struct mlx5e_priv *priv = netdev_priv(netdev);
3604         int err;
3605
3606         mutex_lock(&priv->state_lock);
3607
3608         priv->channels.params.scatter_fcs_en = enable;
3609         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3610         if (err)
3611                 priv->channels.params.scatter_fcs_en = !enable;
3612
3613         mutex_unlock(&priv->state_lock);
3614
3615         return err;
3616 }
3617
3618 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3619 {
3620         struct mlx5e_priv *priv = netdev_priv(netdev);
3621         int err = 0;
3622
3623         mutex_lock(&priv->state_lock);
3624
3625         priv->channels.params.vlan_strip_disable = !enable;
3626         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3627                 goto unlock;
3628
3629         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3630         if (err)
3631                 priv->channels.params.vlan_strip_disable = enable;
3632
3633 unlock:
3634         mutex_unlock(&priv->state_lock);
3635
3636         return err;
3637 }
3638
3639 #ifdef CONFIG_MLX5_EN_ARFS
3640 static int set_feature_arfs(struct net_device *netdev, bool enable)
3641 {
3642         struct mlx5e_priv *priv = netdev_priv(netdev);
3643         int err;
3644
3645         if (enable)
3646                 err = mlx5e_arfs_enable(priv);
3647         else
3648                 err = mlx5e_arfs_disable(priv);
3649
3650         return err;
3651 }
3652 #endif
3653
3654 static int mlx5e_handle_feature(struct net_device *netdev,
3655                                 netdev_features_t *features,
3656                                 netdev_features_t wanted_features,
3657                                 netdev_features_t feature,
3658                                 mlx5e_feature_handler feature_handler)
3659 {
3660         netdev_features_t changes = wanted_features ^ netdev->features;
3661         bool enable = !!(wanted_features & feature);
3662         int err;
3663
3664         if (!(changes & feature))
3665                 return 0;
3666
3667         err = feature_handler(netdev, enable);
3668         if (err) {
3669                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3670                            enable ? "Enable" : "Disable", &feature, err);
3671                 return err;
3672         }
3673
3674         MLX5E_SET_FEATURE(features, feature, enable);
3675         return 0;
3676 }
3677
3678 static int mlx5e_set_features(struct net_device *netdev,
3679                               netdev_features_t features)
3680 {
3681         netdev_features_t oper_features = netdev->features;
3682         int err = 0;
3683
3684 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3685         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3686
3687         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3688         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3689                                     set_feature_cvlan_filter);
3690 #ifdef CONFIG_MLX5_ESWITCH
3691         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3692 #endif
3693         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3694         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3695         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3696 #ifdef CONFIG_MLX5_EN_ARFS
3697         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3698 #endif
3699
3700         if (err) {
3701                 netdev->features = oper_features;
3702                 return -EINVAL;
3703         }
3704
3705         return 0;
3706 }
3707
3708 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3709                                             netdev_features_t features)
3710 {
3711         struct mlx5e_priv *priv = netdev_priv(netdev);
3712         struct mlx5e_params *params;
3713
3714         mutex_lock(&priv->state_lock);
3715         params = &priv->channels.params;
3716         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3717                 /* HW strips the outer C-tag header, this is a problem
3718                  * for S-tag traffic.
3719                  */
3720                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3721                 if (!params->vlan_strip_disable)
3722                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3723         }
3724         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3725                 features &= ~NETIF_F_LRO;
3726                 if (params->lro_en)
3727                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3728         }
3729
3730         mutex_unlock(&priv->state_lock);
3731
3732         return features;
3733 }
3734
3735 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3736                      change_hw_mtu_cb set_mtu_cb)
3737 {
3738         struct mlx5e_priv *priv = netdev_priv(netdev);
3739         struct mlx5e_channels new_channels = {};
3740         struct mlx5e_params *params;
3741         int err = 0;
3742         bool reset;
3743
3744         mutex_lock(&priv->state_lock);
3745
3746         params = &priv->channels.params;
3747
3748         reset = !params->lro_en;
3749         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3750
3751         new_channels.params = *params;
3752         new_channels.params.sw_mtu = new_mtu;
3753
3754         if (params->xdp_prog &&
3755             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3756                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3757                            new_mtu, MLX5E_XDP_MAX_MTU);
3758                 err = -EINVAL;
3759                 goto out;
3760         }
3761
3762         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3763                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3764                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3765                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3766
3767                 reset = reset && (is_linear || (ppw_old != ppw_new));
3768         }
3769
3770         if (!reset) {
3771                 params->sw_mtu = new_mtu;
3772                 if (set_mtu_cb)
3773                         set_mtu_cb(priv);
3774                 netdev->mtu = params->sw_mtu;
3775                 goto out;
3776         }
3777
3778         err = mlx5e_open_channels(priv, &new_channels);
3779         if (err)
3780                 goto out;
3781
3782         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3783         netdev->mtu = new_channels.params.sw_mtu;
3784
3785 out:
3786         mutex_unlock(&priv->state_lock);
3787         return err;
3788 }
3789
3790 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3791 {
3792         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3793 }
3794
3795 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3796 {
3797         struct hwtstamp_config config;
3798         int err;
3799
3800         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3801             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3802                 return -EOPNOTSUPP;
3803
3804         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3805                 return -EFAULT;
3806
3807         /* TX HW timestamp */
3808         switch (config.tx_type) {
3809         case HWTSTAMP_TX_OFF:
3810         case HWTSTAMP_TX_ON:
3811                 break;
3812         default:
3813                 return -ERANGE;
3814         }
3815
3816         mutex_lock(&priv->state_lock);
3817         /* RX HW timestamp */
3818         switch (config.rx_filter) {
3819         case HWTSTAMP_FILTER_NONE:
3820                 /* Reset CQE compression to Admin default */
3821                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3822                 break;
3823         case HWTSTAMP_FILTER_ALL:
3824         case HWTSTAMP_FILTER_SOME:
3825         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3826         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3827         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3828         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3829         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3830         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3831         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3832         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3833         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3834         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3835         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3836         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3837         case HWTSTAMP_FILTER_NTP_ALL:
3838                 /* Disable CQE compression */
3839                 netdev_warn(priv->netdev, "Disabling cqe compression");
3840                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3841                 if (err) {
3842                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3843                         mutex_unlock(&priv->state_lock);
3844                         return err;
3845                 }
3846                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3847                 break;
3848         default:
3849                 mutex_unlock(&priv->state_lock);
3850                 return -ERANGE;
3851         }
3852
3853         memcpy(&priv->tstamp, &config, sizeof(config));
3854         mutex_unlock(&priv->state_lock);
3855
3856         return copy_to_user(ifr->ifr_data, &config,
3857                             sizeof(config)) ? -EFAULT : 0;
3858 }
3859
3860 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3861 {
3862         struct hwtstamp_config *cfg = &priv->tstamp;
3863
3864         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3865                 return -EOPNOTSUPP;
3866
3867         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3868 }
3869
3870 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3871 {
3872         struct mlx5e_priv *priv = netdev_priv(dev);
3873
3874         switch (cmd) {
3875         case SIOCSHWTSTAMP:
3876                 return mlx5e_hwstamp_set(priv, ifr);
3877         case SIOCGHWTSTAMP:
3878                 return mlx5e_hwstamp_get(priv, ifr);
3879         default:
3880                 return -EOPNOTSUPP;
3881         }
3882 }
3883
3884 #ifdef CONFIG_MLX5_ESWITCH
3885 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3886 {
3887         struct mlx5e_priv *priv = netdev_priv(dev);
3888         struct mlx5_core_dev *mdev = priv->mdev;
3889
3890         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3891 }
3892
3893 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3894                              __be16 vlan_proto)
3895 {
3896         struct mlx5e_priv *priv = netdev_priv(dev);
3897         struct mlx5_core_dev *mdev = priv->mdev;
3898
3899         if (vlan_proto != htons(ETH_P_8021Q))
3900                 return -EPROTONOSUPPORT;
3901
3902         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3903                                            vlan, qos);
3904 }
3905
3906 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3907 {
3908         struct mlx5e_priv *priv = netdev_priv(dev);
3909         struct mlx5_core_dev *mdev = priv->mdev;
3910
3911         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3912 }
3913
3914 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3915 {
3916         struct mlx5e_priv *priv = netdev_priv(dev);
3917         struct mlx5_core_dev *mdev = priv->mdev;
3918
3919         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3920 }
3921
3922 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3923                              int max_tx_rate)
3924 {
3925         struct mlx5e_priv *priv = netdev_priv(dev);
3926         struct mlx5_core_dev *mdev = priv->mdev;
3927
3928         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3929                                            max_tx_rate, min_tx_rate);
3930 }
3931
3932 static int mlx5_vport_link2ifla(u8 esw_link)
3933 {
3934         switch (esw_link) {
3935         case MLX5_VPORT_ADMIN_STATE_DOWN:
3936                 return IFLA_VF_LINK_STATE_DISABLE;
3937         case MLX5_VPORT_ADMIN_STATE_UP:
3938                 return IFLA_VF_LINK_STATE_ENABLE;
3939         }
3940         return IFLA_VF_LINK_STATE_AUTO;
3941 }
3942
3943 static int mlx5_ifla_link2vport(u8 ifla_link)
3944 {
3945         switch (ifla_link) {
3946         case IFLA_VF_LINK_STATE_DISABLE:
3947                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3948         case IFLA_VF_LINK_STATE_ENABLE:
3949                 return MLX5_VPORT_ADMIN_STATE_UP;
3950         }
3951         return MLX5_VPORT_ADMIN_STATE_AUTO;
3952 }
3953
3954 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3955                                    int link_state)
3956 {
3957         struct mlx5e_priv *priv = netdev_priv(dev);
3958         struct mlx5_core_dev *mdev = priv->mdev;
3959
3960         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3961                                             mlx5_ifla_link2vport(link_state));
3962 }
3963
3964 static int mlx5e_get_vf_config(struct net_device *dev,
3965                                int vf, struct ifla_vf_info *ivi)
3966 {
3967         struct mlx5e_priv *priv = netdev_priv(dev);
3968         struct mlx5_core_dev *mdev = priv->mdev;
3969         int err;
3970
3971         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3972         if (err)
3973                 return err;
3974         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3975         return 0;
3976 }
3977
3978 static int mlx5e_get_vf_stats(struct net_device *dev,
3979                               int vf, struct ifla_vf_stats *vf_stats)
3980 {
3981         struct mlx5e_priv *priv = netdev_priv(dev);
3982         struct mlx5_core_dev *mdev = priv->mdev;
3983
3984         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3985                                             vf_stats);
3986 }
3987 #endif
3988
3989 struct mlx5e_vxlan_work {
3990         struct work_struct      work;
3991         struct mlx5e_priv       *priv;
3992         u16                     port;
3993 };
3994
3995 static void mlx5e_vxlan_add_work(struct work_struct *work)
3996 {
3997         struct mlx5e_vxlan_work *vxlan_work =
3998                 container_of(work, struct mlx5e_vxlan_work, work);
3999         struct mlx5e_priv *priv = vxlan_work->priv;
4000         u16 port = vxlan_work->port;
4001
4002         mutex_lock(&priv->state_lock);
4003         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4004         mutex_unlock(&priv->state_lock);
4005
4006         kfree(vxlan_work);
4007 }
4008
4009 static void mlx5e_vxlan_del_work(struct work_struct *work)
4010 {
4011         struct mlx5e_vxlan_work *vxlan_work =
4012                 container_of(work, struct mlx5e_vxlan_work, work);
4013         struct mlx5e_priv *priv         = vxlan_work->priv;
4014         u16 port = vxlan_work->port;
4015
4016         mutex_lock(&priv->state_lock);
4017         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4018         mutex_unlock(&priv->state_lock);
4019         kfree(vxlan_work);
4020 }
4021
4022 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4023 {
4024         struct mlx5e_vxlan_work *vxlan_work;
4025
4026         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4027         if (!vxlan_work)
4028                 return;
4029
4030         if (add)
4031                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4032         else
4033                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4034
4035         vxlan_work->priv = priv;
4036         vxlan_work->port = port;
4037         queue_work(priv->wq, &vxlan_work->work);
4038 }
4039
4040 static void mlx5e_add_vxlan_port(struct net_device *netdev,
4041                                  struct udp_tunnel_info *ti)
4042 {
4043         struct mlx5e_priv *priv = netdev_priv(netdev);
4044
4045         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4046                 return;
4047
4048         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4049                 return;
4050
4051         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4052 }
4053
4054 static void mlx5e_del_vxlan_port(struct net_device *netdev,
4055                                  struct udp_tunnel_info *ti)
4056 {
4057         struct mlx5e_priv *priv = netdev_priv(netdev);
4058
4059         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4060                 return;
4061
4062         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4063                 return;
4064
4065         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4066 }
4067
4068 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4069                                                      struct sk_buff *skb,
4070                                                      netdev_features_t features)
4071 {
4072         unsigned int offset = 0;
4073         struct udphdr *udph;
4074         u8 proto;
4075         u16 port;
4076
4077         switch (vlan_get_protocol(skb)) {
4078         case htons(ETH_P_IP):
4079                 proto = ip_hdr(skb)->protocol;
4080                 break;
4081         case htons(ETH_P_IPV6):
4082                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4083                 break;
4084         default:
4085                 goto out;
4086         }
4087
4088         switch (proto) {
4089         case IPPROTO_GRE:
4090                 return features;
4091         case IPPROTO_UDP:
4092                 udph = udp_hdr(skb);
4093                 port = be16_to_cpu(udph->dest);
4094
4095                 /* Verify if UDP port is being offloaded by HW */
4096                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4097                         return features;
4098         }
4099
4100 out:
4101         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4102         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4103 }
4104
4105 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4106                                               struct net_device *netdev,
4107                                               netdev_features_t features)
4108 {
4109         struct mlx5e_priv *priv = netdev_priv(netdev);
4110
4111         features = vlan_features_check(skb, features);
4112         features = vxlan_features_check(skb, features);
4113
4114 #ifdef CONFIG_MLX5_EN_IPSEC
4115         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4116                 return features;
4117 #endif
4118
4119         /* Validate if the tunneled packet is being offloaded by HW */
4120         if (skb->encapsulation &&
4121             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4122                 return mlx5e_tunnel_features_check(priv, skb, features);
4123
4124         return features;
4125 }
4126
4127 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4128                                         struct mlx5e_txqsq *sq)
4129 {
4130         struct mlx5_eq *eq = sq->cq.mcq.eq;
4131         u32 eqe_count;
4132
4133         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4134                    eq->eqn, eq->cons_index, eq->irqn);
4135
4136         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4137         if (!eqe_count)
4138                 return false;
4139
4140         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
4141         sq->channel->stats->eq_rearm++;
4142         return true;
4143 }
4144
4145 static void mlx5e_tx_timeout_work(struct work_struct *work)
4146 {
4147         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4148                                                tx_timeout_work);
4149         struct net_device *dev = priv->netdev;
4150         bool reopen_channels = false;
4151         int i, err;
4152
4153         rtnl_lock();
4154         mutex_lock(&priv->state_lock);
4155
4156         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4157                 goto unlock;
4158
4159         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4160                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4161                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4162
4163                 if (!netif_xmit_stopped(dev_queue))
4164                         continue;
4165
4166                 netdev_err(dev,
4167                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4168                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4169                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4170
4171                 /* If we recover a lost interrupt, most likely TX timeout will
4172                  * be resolved, skip reopening channels
4173                  */
4174                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4175                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4176                         reopen_channels = true;
4177                 }
4178         }
4179
4180         if (!reopen_channels)
4181                 goto unlock;
4182
4183         mlx5e_close_locked(dev);
4184         err = mlx5e_open_locked(dev);
4185         if (err)
4186                 netdev_err(priv->netdev,
4187                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4188                            err);
4189
4190 unlock:
4191         mutex_unlock(&priv->state_lock);
4192         rtnl_unlock();
4193 }
4194
4195 static void mlx5e_tx_timeout(struct net_device *dev)
4196 {
4197         struct mlx5e_priv *priv = netdev_priv(dev);
4198
4199         netdev_err(dev, "TX timeout detected\n");
4200         queue_work(priv->wq, &priv->tx_timeout_work);
4201 }
4202
4203 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4204 {
4205         struct net_device *netdev = priv->netdev;
4206         struct mlx5e_channels new_channels = {};
4207
4208         if (priv->channels.params.lro_en) {
4209                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4210                 return -EINVAL;
4211         }
4212
4213         if (MLX5_IPSEC_DEV(priv->mdev)) {
4214                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4215                 return -EINVAL;
4216         }
4217
4218         new_channels.params = priv->channels.params;
4219         new_channels.params.xdp_prog = prog;
4220
4221         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4222                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4223                             new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4224                 return -EINVAL;
4225         }
4226
4227         return 0;
4228 }
4229
4230 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4231 {
4232         struct mlx5e_priv *priv = netdev_priv(netdev);
4233         struct bpf_prog *old_prog;
4234         bool reset, was_opened;
4235         int err = 0;
4236         int i;
4237
4238         mutex_lock(&priv->state_lock);
4239
4240         if (prog) {
4241                 err = mlx5e_xdp_allowed(priv, prog);
4242                 if (err)
4243                         goto unlock;
4244         }
4245
4246         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4247         /* no need for full reset when exchanging programs */
4248         reset = (!priv->channels.params.xdp_prog || !prog);
4249
4250         if (was_opened && reset)
4251                 mlx5e_close_locked(netdev);
4252         if (was_opened && !reset) {
4253                 /* num_channels is invariant here, so we can take the
4254                  * batched reference right upfront.
4255                  */
4256                 prog = bpf_prog_add(prog, priv->channels.num);
4257                 if (IS_ERR(prog)) {
4258                         err = PTR_ERR(prog);
4259                         goto unlock;
4260                 }
4261         }
4262
4263         /* exchange programs, extra prog reference we got from caller
4264          * as long as we don't fail from this point onwards.
4265          */
4266         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4267         if (old_prog)
4268                 bpf_prog_put(old_prog);
4269
4270         if (reset) /* change RQ type according to priv->xdp_prog */
4271                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4272
4273         if (was_opened && reset)
4274                 mlx5e_open_locked(netdev);
4275
4276         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4277                 goto unlock;
4278
4279         /* exchanging programs w/o reset, we update ref counts on behalf
4280          * of the channels RQs here.
4281          */
4282         for (i = 0; i < priv->channels.num; i++) {
4283                 struct mlx5e_channel *c = priv->channels.c[i];
4284
4285                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4286                 napi_synchronize(&c->napi);
4287                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4288
4289                 old_prog = xchg(&c->rq.xdp_prog, prog);
4290
4291                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4292                 /* napi_schedule in case we have missed anything */
4293                 napi_schedule(&c->napi);
4294
4295                 if (old_prog)
4296                         bpf_prog_put(old_prog);
4297         }
4298
4299 unlock:
4300         mutex_unlock(&priv->state_lock);
4301         return err;
4302 }
4303
4304 static u32 mlx5e_xdp_query(struct net_device *dev)
4305 {
4306         struct mlx5e_priv *priv = netdev_priv(dev);
4307         const struct bpf_prog *xdp_prog;
4308         u32 prog_id = 0;
4309
4310         mutex_lock(&priv->state_lock);
4311         xdp_prog = priv->channels.params.xdp_prog;
4312         if (xdp_prog)
4313                 prog_id = xdp_prog->aux->id;
4314         mutex_unlock(&priv->state_lock);
4315
4316         return prog_id;
4317 }
4318
4319 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4320 {
4321         switch (xdp->command) {
4322         case XDP_SETUP_PROG:
4323                 return mlx5e_xdp_set(dev, xdp->prog);
4324         case XDP_QUERY_PROG:
4325                 xdp->prog_id = mlx5e_xdp_query(dev);
4326                 return 0;
4327         default:
4328                 return -EINVAL;
4329         }
4330 }
4331
4332 const struct net_device_ops mlx5e_netdev_ops = {
4333         .ndo_open                = mlx5e_open,
4334         .ndo_stop                = mlx5e_close,
4335         .ndo_start_xmit          = mlx5e_xmit,
4336         .ndo_setup_tc            = mlx5e_setup_tc,
4337         .ndo_select_queue        = mlx5e_select_queue,
4338         .ndo_get_stats64         = mlx5e_get_stats,
4339         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4340         .ndo_set_mac_address     = mlx5e_set_mac,
4341         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4342         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4343         .ndo_set_features        = mlx5e_set_features,
4344         .ndo_fix_features        = mlx5e_fix_features,
4345         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4346         .ndo_do_ioctl            = mlx5e_ioctl,
4347         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4348         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4349         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4350         .ndo_features_check      = mlx5e_features_check,
4351         .ndo_tx_timeout          = mlx5e_tx_timeout,
4352         .ndo_bpf                 = mlx5e_xdp,
4353         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4354 #ifdef CONFIG_MLX5_EN_ARFS
4355         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4356 #endif
4357 #ifdef CONFIG_MLX5_ESWITCH
4358         /* SRIOV E-Switch NDOs */
4359         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4360         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4361         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4362         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4363         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4364         .ndo_get_vf_config       = mlx5e_get_vf_config,
4365         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4366         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4367         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4368         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4369 #endif
4370 };
4371
4372 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4373 {
4374         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4375                 return -EOPNOTSUPP;
4376         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4377             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4378             !MLX5_CAP_ETH(mdev, csum_cap) ||
4379             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4380             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4381             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4382             MLX5_CAP_FLOWTABLE(mdev,
4383                                flow_table_properties_nic_receive.max_ft_level)
4384                                < 3) {
4385                 mlx5_core_warn(mdev,
4386                                "Not creating net device, some required device capabilities are missing\n");
4387                 return -EOPNOTSUPP;
4388         }
4389         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4390                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4391         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4392                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4393
4394         return 0;
4395 }
4396
4397 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4398                                    int num_channels)
4399 {
4400         int i;
4401
4402         for (i = 0; i < len; i++)
4403                 indirection_rqt[i] = i % num_channels;
4404 }
4405
4406 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4407 {
4408         u32 link_speed = 0;
4409         u32 pci_bw = 0;
4410
4411         mlx5e_port_max_linkspeed(mdev, &link_speed);
4412         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4413         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4414                            link_speed, pci_bw);
4415
4416 #define MLX5E_SLOW_PCI_RATIO (2)
4417
4418         return link_speed && pci_bw &&
4419                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4420 }
4421
4422 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4423 {
4424         struct net_dim_cq_moder moder;
4425
4426         moder.cq_period_mode = cq_period_mode;
4427         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4428         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4429         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4430                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4431
4432         return moder;
4433 }
4434
4435 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4436 {
4437         struct net_dim_cq_moder moder;
4438
4439         moder.cq_period_mode = cq_period_mode;
4440         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4441         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4442         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4443                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4444
4445         return moder;
4446 }
4447
4448 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4449 {
4450         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4451                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4452                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4453 }
4454
4455 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4456 {
4457         if (params->tx_dim_enabled) {
4458                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4459
4460                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4461         } else {
4462                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4463         }
4464
4465         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4466                         params->tx_cq_moderation.cq_period_mode ==
4467                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4468 }
4469
4470 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4471 {
4472         if (params->rx_dim_enabled) {
4473                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4474
4475                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4476         } else {
4477                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4478         }
4479
4480         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4481                         params->rx_cq_moderation.cq_period_mode ==
4482                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4483 }
4484
4485 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4486 {
4487         int i;
4488
4489         /* The supported periods are organized in ascending order */
4490         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4491                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4492                         break;
4493
4494         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4495 }
4496
4497 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4498                            struct mlx5e_params *params)
4499 {
4500         /* Prefer Striding RQ, unless any of the following holds:
4501          * - Striding RQ configuration is not possible/supported.
4502          * - Slow PCI heuristic.
4503          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4504          */
4505         if (!slow_pci_heuristic(mdev) &&
4506             mlx5e_striding_rq_possible(mdev, params) &&
4507             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4508              !mlx5e_rx_is_linear_skb(mdev, params)))
4509                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4510         mlx5e_set_rq_type(mdev, params);
4511         mlx5e_init_rq_type_params(mdev, params);
4512 }
4513
4514 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4515                             u16 num_channels)
4516 {
4517         rss_params->hfunc = ETH_RSS_HASH_XOR;
4518         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4519                             sizeof(rss_params->toeplitz_hash_key));
4520         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4521                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4522 }
4523
4524 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4525                             struct mlx5e_rss_params *rss_params,
4526                             struct mlx5e_params *params,
4527                             u16 max_channels, u16 mtu)
4528 {
4529         u8 rx_cq_period_mode;
4530
4531         params->sw_mtu = mtu;
4532         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4533         params->num_channels = max_channels;
4534         params->num_tc       = 1;
4535
4536         /* SQ */
4537         params->log_sq_size = is_kdump_kernel() ?
4538                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4539                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4540
4541         /* set CQE compression */
4542         params->rx_cqe_compress_def = false;
4543         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4544             MLX5_CAP_GEN(mdev, vport_group_manager))
4545                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4546
4547         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4548         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4549
4550         /* RQ */
4551         mlx5e_build_rq_params(mdev, params);
4552
4553         /* HW LRO */
4554
4555         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4556         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4557                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4558                         params->lro_en = !slow_pci_heuristic(mdev);
4559         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4560
4561         /* CQ moderation params */
4562         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4563                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4564                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4565         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4566         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4567         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4568         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4569
4570         /* TX inline */
4571         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4572
4573         /* RSS */
4574         mlx5e_build_rss_params(rss_params, params->num_channels);
4575 }
4576
4577 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4578 {
4579         struct mlx5e_priv *priv = netdev_priv(netdev);
4580
4581         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4582         if (is_zero_ether_addr(netdev->dev_addr) &&
4583             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4584                 eth_hw_addr_random(netdev);
4585                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4586         }
4587 }
4588
4589 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4590 static const struct switchdev_ops mlx5e_switchdev_ops = {
4591         .switchdev_port_attr_get        = mlx5e_attr_get,
4592 };
4593 #endif
4594
4595 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4596 {
4597         struct mlx5e_priv *priv = netdev_priv(netdev);
4598         struct mlx5_core_dev *mdev = priv->mdev;
4599         bool fcs_supported;
4600         bool fcs_enabled;
4601
4602         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4603
4604         netdev->netdev_ops = &mlx5e_netdev_ops;
4605
4606 #ifdef CONFIG_MLX5_CORE_EN_DCB
4607         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4608                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4609 #endif
4610
4611         netdev->watchdog_timeo    = 15 * HZ;
4612
4613         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4614
4615         netdev->vlan_features    |= NETIF_F_SG;
4616         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4617         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4618         netdev->vlan_features    |= NETIF_F_GRO;
4619         netdev->vlan_features    |= NETIF_F_TSO;
4620         netdev->vlan_features    |= NETIF_F_TSO6;
4621         netdev->vlan_features    |= NETIF_F_RXCSUM;
4622         netdev->vlan_features    |= NETIF_F_RXHASH;
4623
4624         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4625         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4626
4627         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4628             mlx5e_check_fragmented_striding_rq_cap(mdev))
4629                 netdev->vlan_features    |= NETIF_F_LRO;
4630
4631         netdev->hw_features       = netdev->vlan_features;
4632         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4633         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4634         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4635         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4636
4637         if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4638                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4639                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4640                 netdev->hw_enc_features |= NETIF_F_TSO;
4641                 netdev->hw_enc_features |= NETIF_F_TSO6;
4642                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4643         }
4644
4645         if (mlx5_vxlan_allowed(mdev->vxlan)) {
4646                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4647                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4648                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4649                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4650                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4651         }
4652
4653         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4654                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4655                                            NETIF_F_GSO_GRE_CSUM;
4656                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4657                                            NETIF_F_GSO_GRE_CSUM;
4658                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4659                                                 NETIF_F_GSO_GRE_CSUM;
4660         }
4661
4662         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4663         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4664         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4665         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4666
4667         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4668
4669         if (fcs_supported)
4670                 netdev->hw_features |= NETIF_F_RXALL;
4671
4672         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4673                 netdev->hw_features |= NETIF_F_RXFCS;
4674
4675         netdev->features          = netdev->hw_features;
4676         if (!priv->channels.params.lro_en)
4677                 netdev->features  &= ~NETIF_F_LRO;
4678
4679         if (fcs_enabled)
4680                 netdev->features  &= ~NETIF_F_RXALL;
4681
4682         if (!priv->channels.params.scatter_fcs_en)
4683                 netdev->features  &= ~NETIF_F_RXFCS;
4684
4685 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4686         if (FT_CAP(flow_modify_en) &&
4687             FT_CAP(modify_root) &&
4688             FT_CAP(identified_miss_table_mode) &&
4689             FT_CAP(flow_table_modify)) {
4690 #ifdef CONFIG_MLX5_ESWITCH
4691                 netdev->hw_features      |= NETIF_F_HW_TC;
4692 #endif
4693 #ifdef CONFIG_MLX5_EN_ARFS
4694                 netdev->hw_features      |= NETIF_F_NTUPLE;
4695 #endif
4696         }
4697
4698         netdev->features         |= NETIF_F_HIGHDMA;
4699         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4700
4701         netdev->priv_flags       |= IFF_UNICAST_FLT;
4702
4703         mlx5e_set_netdev_dev_addr(netdev);
4704
4705 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4706         if (MLX5_ESWITCH_MANAGER(mdev))
4707                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4708 #endif
4709
4710         mlx5e_ipsec_build_netdev(priv);
4711         mlx5e_tls_build_netdev(priv);
4712 }
4713
4714 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4715 {
4716         struct mlx5_core_dev *mdev = priv->mdev;
4717         int err;
4718
4719         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4720         if (err) {
4721                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4722                 priv->q_counter = 0;
4723         }
4724
4725         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4726         if (err) {
4727                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4728                 priv->drop_rq_q_counter = 0;
4729         }
4730 }
4731
4732 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4733 {
4734         if (priv->q_counter)
4735                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4736
4737         if (priv->drop_rq_q_counter)
4738                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4739 }
4740
4741 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4742                           struct net_device *netdev,
4743                           const struct mlx5e_profile *profile,
4744                           void *ppriv)
4745 {
4746         struct mlx5e_priv *priv = netdev_priv(netdev);
4747         struct mlx5e_rss_params *rss = &priv->rss_params;
4748         int err;
4749
4750         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4751         if (err)
4752                 return err;
4753
4754         mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4755                                mlx5e_get_netdev_max_channels(netdev),
4756                                netdev->mtu);
4757
4758         mlx5e_timestamp_init(priv);
4759
4760         err = mlx5e_ipsec_init(priv);
4761         if (err)
4762                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4763         err = mlx5e_tls_init(priv);
4764         if (err)
4765                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4766         mlx5e_build_nic_netdev(netdev);
4767         mlx5e_build_tc2txq_maps(priv);
4768
4769         return 0;
4770 }
4771
4772 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4773 {
4774         mlx5e_tls_cleanup(priv);
4775         mlx5e_ipsec_cleanup(priv);
4776         mlx5e_netdev_cleanup(priv->netdev, priv);
4777 }
4778
4779 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4780 {
4781         struct mlx5_core_dev *mdev = priv->mdev;
4782         int err;
4783
4784         mlx5e_create_q_counters(priv);
4785
4786         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4787         if (err) {
4788                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4789                 goto err_destroy_q_counters;
4790         }
4791
4792         err = mlx5e_create_indirect_rqt(priv);
4793         if (err)
4794                 goto err_close_drop_rq;
4795
4796         err = mlx5e_create_direct_rqts(priv);
4797         if (err)
4798                 goto err_destroy_indirect_rqts;
4799
4800         err = mlx5e_create_indirect_tirs(priv, true);
4801         if (err)
4802                 goto err_destroy_direct_rqts;
4803
4804         err = mlx5e_create_direct_tirs(priv);
4805         if (err)
4806                 goto err_destroy_indirect_tirs;
4807
4808         err = mlx5e_create_flow_steering(priv);
4809         if (err) {
4810                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4811                 goto err_destroy_direct_tirs;
4812         }
4813
4814         err = mlx5e_tc_nic_init(priv);
4815         if (err)
4816                 goto err_destroy_flow_steering;
4817
4818         return 0;
4819
4820 err_destroy_flow_steering:
4821         mlx5e_destroy_flow_steering(priv);
4822 err_destroy_direct_tirs:
4823         mlx5e_destroy_direct_tirs(priv);
4824 err_destroy_indirect_tirs:
4825         mlx5e_destroy_indirect_tirs(priv, true);
4826 err_destroy_direct_rqts:
4827         mlx5e_destroy_direct_rqts(priv);
4828 err_destroy_indirect_rqts:
4829         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4830 err_close_drop_rq:
4831         mlx5e_close_drop_rq(&priv->drop_rq);
4832 err_destroy_q_counters:
4833         mlx5e_destroy_q_counters(priv);
4834         return err;
4835 }
4836
4837 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4838 {
4839         mlx5e_tc_nic_cleanup(priv);
4840         mlx5e_destroy_flow_steering(priv);
4841         mlx5e_destroy_direct_tirs(priv);
4842         mlx5e_destroy_indirect_tirs(priv, true);
4843         mlx5e_destroy_direct_rqts(priv);
4844         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4845         mlx5e_close_drop_rq(&priv->drop_rq);
4846         mlx5e_destroy_q_counters(priv);
4847 }
4848
4849 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4850 {
4851         int err;
4852
4853         err = mlx5e_create_tises(priv);
4854         if (err) {
4855                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4856                 return err;
4857         }
4858
4859 #ifdef CONFIG_MLX5_CORE_EN_DCB
4860         mlx5e_dcbnl_initialize(priv);
4861 #endif
4862         return 0;
4863 }
4864
4865 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4866 {
4867         struct net_device *netdev = priv->netdev;
4868         struct mlx5_core_dev *mdev = priv->mdev;
4869         u16 max_mtu;
4870
4871         mlx5e_init_l2_addr(priv);
4872
4873         /* Marking the link as currently not needed by the Driver */
4874         if (!netif_running(netdev))
4875                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4876
4877         /* MTU range: 68 - hw-specific max */
4878         netdev->min_mtu = ETH_MIN_MTU;
4879         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4880         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4881         mlx5e_set_dev_port_mtu(priv);
4882
4883         mlx5_lag_add(mdev, netdev);
4884
4885         mlx5e_enable_async_events(priv);
4886
4887         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4888                 mlx5e_register_vport_reps(priv);
4889
4890         if (netdev->reg_state != NETREG_REGISTERED)
4891                 return;
4892 #ifdef CONFIG_MLX5_CORE_EN_DCB
4893         mlx5e_dcbnl_init_app(priv);
4894 #endif
4895
4896         queue_work(priv->wq, &priv->set_rx_mode_work);
4897
4898         rtnl_lock();
4899         if (netif_running(netdev))
4900                 mlx5e_open(netdev);
4901         netif_device_attach(netdev);
4902         rtnl_unlock();
4903 }
4904
4905 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4906 {
4907         struct mlx5_core_dev *mdev = priv->mdev;
4908
4909 #ifdef CONFIG_MLX5_CORE_EN_DCB
4910         if (priv->netdev->reg_state == NETREG_REGISTERED)
4911                 mlx5e_dcbnl_delete_app(priv);
4912 #endif
4913
4914         rtnl_lock();
4915         if (netif_running(priv->netdev))
4916                 mlx5e_close(priv->netdev);
4917         netif_device_detach(priv->netdev);
4918         rtnl_unlock();
4919
4920         queue_work(priv->wq, &priv->set_rx_mode_work);
4921
4922         if (MLX5_ESWITCH_MANAGER(priv->mdev))
4923                 mlx5e_unregister_vport_reps(priv);
4924
4925         mlx5e_disable_async_events(priv);
4926         mlx5_lag_remove(mdev);
4927 }
4928
4929 static const struct mlx5e_profile mlx5e_nic_profile = {
4930         .init              = mlx5e_nic_init,
4931         .cleanup           = mlx5e_nic_cleanup,
4932         .init_rx           = mlx5e_init_nic_rx,
4933         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4934         .init_tx           = mlx5e_init_nic_tx,
4935         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4936         .enable            = mlx5e_nic_enable,
4937         .disable           = mlx5e_nic_disable,
4938         .update_stats      = mlx5e_update_ndo_stats,
4939         .update_carrier    = mlx5e_update_carrier,
4940         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4941         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4942         .max_tc            = MLX5E_MAX_NUM_TC,
4943 };
4944
4945 /* mlx5e generic netdev management API (move to en_common.c) */
4946
4947 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
4948 int mlx5e_netdev_init(struct net_device *netdev,
4949                       struct mlx5e_priv *priv,
4950                       struct mlx5_core_dev *mdev,
4951                       const struct mlx5e_profile *profile,
4952                       void *ppriv)
4953 {
4954         /* priv init */
4955         priv->mdev        = mdev;
4956         priv->netdev      = netdev;
4957         priv->profile     = profile;
4958         priv->ppriv       = ppriv;
4959         priv->msglevel    = MLX5E_MSG_LEVEL;
4960         priv->max_opened_tc = 1;
4961
4962         mutex_init(&priv->state_lock);
4963         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4964         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4965         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4966         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4967
4968         priv->wq = create_singlethread_workqueue("mlx5e");
4969         if (!priv->wq)
4970                 return -ENOMEM;
4971
4972         /* netdev init */
4973         netif_carrier_off(netdev);
4974
4975 #ifdef CONFIG_MLX5_EN_ARFS
4976         netdev->rx_cpu_rmap = mdev->rmap;
4977 #endif
4978
4979         return 0;
4980 }
4981
4982 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
4983 {
4984         destroy_workqueue(priv->wq);
4985 }
4986
4987 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4988                                        const struct mlx5e_profile *profile,
4989                                        int nch,
4990                                        void *ppriv)
4991 {
4992         struct net_device *netdev;
4993         int err;
4994
4995         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4996                                     nch * profile->max_tc,
4997                                     nch);
4998         if (!netdev) {
4999                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5000                 return NULL;
5001         }
5002
5003         err = profile->init(mdev, netdev, profile, ppriv);
5004         if (err) {
5005                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5006                 goto err_free_netdev;
5007         }
5008
5009         return netdev;
5010
5011 err_free_netdev:
5012         free_netdev(netdev);
5013
5014         return NULL;
5015 }
5016
5017 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5018 {
5019         const struct mlx5e_profile *profile;
5020         int max_nch;
5021         int err;
5022
5023         profile = priv->profile;
5024         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5025
5026         /* max number of channels may have changed */
5027         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5028         if (priv->channels.params.num_channels > max_nch) {
5029                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5030                 priv->channels.params.num_channels = max_nch;
5031                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5032                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5033         }
5034
5035         err = profile->init_tx(priv);
5036         if (err)
5037                 goto out;
5038
5039         err = profile->init_rx(priv);
5040         if (err)
5041                 goto err_cleanup_tx;
5042
5043         if (profile->enable)
5044                 profile->enable(priv);
5045
5046         return 0;
5047
5048 err_cleanup_tx:
5049         profile->cleanup_tx(priv);
5050
5051 out:
5052         return err;
5053 }
5054
5055 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5056 {
5057         const struct mlx5e_profile *profile = priv->profile;
5058
5059         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5060
5061         if (profile->disable)
5062                 profile->disable(priv);
5063         flush_workqueue(priv->wq);
5064
5065         profile->cleanup_rx(priv);
5066         profile->cleanup_tx(priv);
5067         cancel_work_sync(&priv->update_stats_work);
5068 }
5069
5070 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5071 {
5072         const struct mlx5e_profile *profile = priv->profile;
5073         struct net_device *netdev = priv->netdev;
5074
5075         if (profile->cleanup)
5076                 profile->cleanup(priv);
5077         free_netdev(netdev);
5078 }
5079
5080 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5081  * hardware contexts and to connect it to the current netdev.
5082  */
5083 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5084 {
5085         struct mlx5e_priv *priv = vpriv;
5086         struct net_device *netdev = priv->netdev;
5087         int err;
5088
5089         if (netif_device_present(netdev))
5090                 return 0;
5091
5092         err = mlx5e_create_mdev_resources(mdev);
5093         if (err)
5094                 return err;
5095
5096         err = mlx5e_attach_netdev(priv);
5097         if (err) {
5098                 mlx5e_destroy_mdev_resources(mdev);
5099                 return err;
5100         }
5101
5102         return 0;
5103 }
5104
5105 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5106 {
5107         struct mlx5e_priv *priv = vpriv;
5108         struct net_device *netdev = priv->netdev;
5109
5110         if (!netif_device_present(netdev))
5111                 return;
5112
5113         mlx5e_detach_netdev(priv);
5114         mlx5e_destroy_mdev_resources(mdev);
5115 }
5116
5117 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5118 {
5119         struct net_device *netdev;
5120         void *rpriv = NULL;
5121         void *priv;
5122         int err;
5123         int nch;
5124
5125         err = mlx5e_check_required_hca_cap(mdev);
5126         if (err)
5127                 return NULL;
5128
5129 #ifdef CONFIG_MLX5_ESWITCH
5130         if (MLX5_ESWITCH_MANAGER(mdev)) {
5131                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
5132                 if (!rpriv) {
5133                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
5134                         return NULL;
5135                 }
5136         }
5137 #endif
5138
5139         nch = mlx5e_get_max_num_channels(mdev);
5140         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, rpriv);
5141         if (!netdev) {
5142                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5143                 goto err_free_rpriv;
5144         }
5145
5146         priv = netdev_priv(netdev);
5147
5148         err = mlx5e_attach(mdev, priv);
5149         if (err) {
5150                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5151                 goto err_destroy_netdev;
5152         }
5153
5154         err = register_netdev(netdev);
5155         if (err) {
5156                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5157                 goto err_detach;
5158         }
5159
5160 #ifdef CONFIG_MLX5_CORE_EN_DCB
5161         mlx5e_dcbnl_init_app(priv);
5162 #endif
5163         return priv;
5164
5165 err_detach:
5166         mlx5e_detach(mdev, priv);
5167 err_destroy_netdev:
5168         mlx5e_destroy_netdev(priv);
5169 err_free_rpriv:
5170         kfree(rpriv);
5171         return NULL;
5172 }
5173
5174 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5175 {
5176         struct mlx5e_priv *priv = vpriv;
5177         void *ppriv = priv->ppriv;
5178
5179 #ifdef CONFIG_MLX5_CORE_EN_DCB
5180         mlx5e_dcbnl_delete_app(priv);
5181 #endif
5182         unregister_netdev(priv->netdev);
5183         mlx5e_detach(mdev, vpriv);
5184         mlx5e_destroy_netdev(priv);
5185         kfree(ppriv);
5186 }
5187
5188 static void *mlx5e_get_netdev(void *vpriv)
5189 {
5190         struct mlx5e_priv *priv = vpriv;
5191
5192         return priv->netdev;
5193 }
5194
5195 static struct mlx5_interface mlx5e_interface = {
5196         .add       = mlx5e_add,
5197         .remove    = mlx5e_remove,
5198         .attach    = mlx5e_attach,
5199         .detach    = mlx5e_detach,
5200         .event     = mlx5e_async_event,
5201         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5202         .get_dev   = mlx5e_get_netdev,
5203 };
5204
5205 void mlx5e_init(void)
5206 {
5207         mlx5e_ipsec_build_inverse_table();
5208         mlx5e_build_ptys2ethtool_map();
5209         mlx5_register_interface(&mlx5e_interface);
5210 }
5211
5212 void mlx5e_cleanup(void)
5213 {
5214         mlx5_unregister_interface(&mlx5e_interface);
5215 }