drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "accel/ipsec.h"
  46 #include "vxlan.h"
  47
  48 struct mlx5e_rq_param {
  49         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  50         struct mlx5_wq_param    wq;
  51 };
  52
  53 struct mlx5e_sq_param {
  54         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  55         struct mlx5_wq_param       wq;
  56 };
  57
  58 struct mlx5e_cq_param {
  59         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  60         struct mlx5_wq_param       wq;
  61         u16                        eq_ix;
  62         u8                         cq_period_mode;
  63 };
  64
  65 struct mlx5e_channel_param {
  66         struct mlx5e_rq_param      rq;
  67         struct mlx5e_sq_param      sq;
  68         struct mlx5e_sq_param      xdp_sq;
  69         struct mlx5e_sq_param      icosq;
  70         struct mlx5e_cq_param      rx_cq;
  71         struct mlx5e_cq_param      tx_cq;
  72         struct mlx5e_cq_param      icosq_cq;
  73 };
  74
  75 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  76 {
  77         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  78                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  79                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  80         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  81         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  82
  83         if (!striding_rq_umr)
  84                 return false;
  85         if (!inline_umr) {
  86                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  87                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  88                 return false;
  89         }
  90         return true;
  91 }
  92
  93 static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
  94 {
  95         if (!params->xdp_prog) {
  96                 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
  97                 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
  98
  99                 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
 100         }
 101
 102         return PAGE_SIZE;
 103 }
 104
 105 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 106 {
 107         u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 108
 109         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 110 }
 111
 112 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 113                                          struct mlx5e_params *params)
 114 {
 115         u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
 116         s8 signed_log_num_strides_param;
 117         u8 log_num_strides;
 118
 119         if (params->lro_en || frag_sz > PAGE_SIZE)
 120                 return false;
 121
 122         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 123                 return true;
 124
 125         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 126         signed_log_num_strides_param =
 127                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 128
 129         return signed_log_num_strides_param >= 0;
 130 }
 131
 132 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 133 {
 134         if (params->log_rq_mtu_frames <
 135             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 136                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 137
 138         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 139 }
 140
 141 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 142                                           struct mlx5e_params *params)
 143 {
 144         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 145                 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
 146
 147         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 148                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 149 }
 150
 151 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 152                                           struct mlx5e_params *params)
 153 {
 154         return MLX5_MPWRQ_LOG_WQE_SZ -
 155                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 156 }
 157
 158 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 159                                  struct mlx5e_params *params)
 160 {
 161         u16 linear_rq_headroom = params->xdp_prog ?
 162                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 163
 164         linear_rq_headroom += NET_IP_ALIGN;
 165
 166         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
 167                 return linear_rq_headroom;
 168
 169         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 170                 return linear_rq_headroom;
 171
 172         return 0;
 173 }
 174
 175 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 176                                struct mlx5e_params *params)
 177 {
 178         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 179         params->log_rq_mtu_frames = is_kdump_kernel() ?
 180                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 181                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 182         switch (params->rq_wq_type) {
 183         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 184                 break;
 185         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 186                 /* Extra room needed for build_skb */
 187                 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
 188                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 189         }
 190
 191         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 192                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 193                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 194                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 195                        BIT(params->log_rq_mtu_frames),
 196                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 197                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 198 }
 199
 200 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 201                                 struct mlx5e_params *params)
 202 {
 203         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 204                 !MLX5_IPSEC_DEV(mdev) &&
 205                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 206 }
 207
 208 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 209 {
 210         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 211                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 212                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 213                 MLX5_WQ_TYPE_LINKED_LIST;
 214 }
 215
 216 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
 217 {
 218         struct mlx5_core_dev *mdev = priv->mdev;
 219         u8 port_state;
 220
 221         port_state = mlx5_query_vport_state(mdev,
 222                                             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
 223                                             0);
 224
 225         if (port_state == VPORT_STATE_UP) {
 226                 netdev_info(priv->netdev, "Link up\n");
 227                 netif_carrier_on(priv->netdev);
 228         } else {
 229                 netdev_info(priv->netdev, "Link down\n");
 230                 netif_carrier_off(priv->netdev);
 231         }
 232 }
 233
 234 static void mlx5e_update_carrier_work(struct work_struct *work)
 235 {
 236         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 237                                                update_carrier_work);
 238
 239         mutex_lock(&priv->state_lock);
 240         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 241                 if (priv->profile->update_carrier)
 242                         priv->profile->update_carrier(priv);
 243         mutex_unlock(&priv->state_lock);
 244 }
 245
 246 void mlx5e_update_stats(struct mlx5e_priv *priv)
 247 {
 248         int i;
 249
 250         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 251                 if (mlx5e_stats_grps[i].update_stats)
 252                         mlx5e_stats_grps[i].update_stats(priv);
 253 }
 254
 255 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 256 {
 257         int i;
 258
 259         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 260                 if (mlx5e_stats_grps[i].update_stats_mask &
 261                     MLX5E_NDO_UPDATE_STATS)
 262                         mlx5e_stats_grps[i].update_stats(priv);
 263 }
 264
 265 void mlx5e_update_stats_work(struct work_struct *work)
 266 {
 267         struct delayed_work *dwork = to_delayed_work(work);
 268         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 269                                                update_stats_work);
 270         mutex_lock(&priv->state_lock);
 271         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 272                 priv->profile->update_stats(priv);
 273                 queue_delayed_work(priv->wq, dwork,
 274                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 275         }
 276         mutex_unlock(&priv->state_lock);
 277 }
 278
 279 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 280                               enum mlx5_dev_event event, unsigned long param)
 281 {
 282         struct mlx5e_priv *priv = vpriv;
 283
 284         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 285                 return;
 286
 287         switch (event) {
 288         case MLX5_DEV_EVENT_PORT_UP:
 289         case MLX5_DEV_EVENT_PORT_DOWN:
 290                 queue_work(priv->wq, &priv->update_carrier_work);
 291                 break;
 292         default:
 293                 break;
 294         }
 295 }
 296
 297 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 298 {
 299         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 300 }
 301
 302 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 303 {
 304         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 305         synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
 306 }
 307
 308 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 309                                        struct mlx5e_icosq *sq,
 310                                        struct mlx5e_umr_wqe *wqe)
 311 {
 312         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 313         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 314         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 315
 316         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 317                                       ds_cnt);
 318         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 319         cseg->imm       = rq->mkey_be;
 320
 321         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 322         ucseg->xlt_octowords =
 323                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 324         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 325 }
 326
 327 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 328                                      struct mlx5e_channel *c)
 329 {
 330         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 331
 332         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 333                                       GFP_KERNEL, cpu_to_node(c->cpu));
 334         if (!rq->mpwqe.info)
 335                 return -ENOMEM;
 336
 337         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 338
 339         return 0;
 340 }
 341
 342 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 343                                  u64 npages, u8 page_shift,
 344                                  struct mlx5_core_mkey *umr_mkey)
 345 {
 346         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 347         void *mkc;
 348         u32 *in;
 349         int err;
 350
 351         in = kvzalloc(inlen, GFP_KERNEL);
 352         if (!in)
 353                 return -ENOMEM;
 354
 355         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 356
 357         MLX5_SET(mkc, mkc, free, 1);
 358         MLX5_SET(mkc, mkc, umr_en, 1);
 359         MLX5_SET(mkc, mkc, lw, 1);
 360         MLX5_SET(mkc, mkc, lr, 1);
 361         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 362
 363         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 364         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 365         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 366         MLX5_SET(mkc, mkc, translations_octword_size,
 367                  MLX5_MTT_OCTW(npages));
 368         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 369
 370         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 371
 372         kvfree(in);
 373         return err;
 374 }
 375
 376 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 377 {
 378         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
 379
 380         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 381 }
 382
 383 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 384 {
 385         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 386 }
 387
 388 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 389                           struct mlx5e_params *params,
 390                           struct mlx5e_rq_param *rqp,
 391                           struct mlx5e_rq *rq)
 392 {
 393         struct page_pool_params pp_params = { 0 };
 394         struct mlx5_core_dev *mdev = c->mdev;
 395         void *rqc = rqp->rqc;
 396         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 397         u32 byte_count, pool_size;
 398         int npages;
 399         int wq_sz;
 400         int err;
 401         int i;
 402
 403         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 404
 405         err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
 406                                 &rq->wq_ctrl);
 407         if (err)
 408                 return err;
 409
 410         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 411
 412         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 413
 414         rq->wq_type = params->rq_wq_type;
 415         rq->pdev    = c->pdev;
 416         rq->netdev  = c->netdev;
 417         rq->tstamp  = c->tstamp;
 418         rq->clock   = &mdev->clock;
 419         rq->channel = c;
 420         rq->ix      = c->ix;
 421         rq->mdev    = mdev;
 422         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 423
 424         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 425         if (IS_ERR(rq->xdp_prog)) {
 426                 err = PTR_ERR(rq->xdp_prog);
 427                 rq->xdp_prog = NULL;
 428                 goto err_rq_wq_destroy;
 429         }
 430
 431         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 432         if (err < 0)
 433                 goto err_rq_wq_destroy;
 434
 435         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 436         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 437         pool_size = 1 << params->log_rq_mtu_frames;
 438
 439         switch (rq->wq_type) {
 440         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 441
 442                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 443                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 444                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 445
 446                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 447 #ifdef CONFIG_MLX5_EN_IPSEC
 448                 if (MLX5_IPSEC_DEV(mdev)) {
 449                         err = -EINVAL;
 450                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 451                         goto err_rq_wq_destroy;
 452                 }
 453 #endif
 454                 if (!rq->handle_rx_cqe) {
 455                         err = -EINVAL;
 456                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 457                         goto err_rq_wq_destroy;
 458                 }
 459
 460                 rq->mpwqe.skb_from_cqe_mpwrq =
 461                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 462                         mlx5e_skb_from_cqe_mpwrq_linear :
 463                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 464                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 465                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 466
 467                 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 468
 469                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 470                 if (err)
 471                         goto err_rq_wq_destroy;
 472                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 473
 474                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 475                 if (err)
 476                         goto err_destroy_umr_mkey;
 477                 break;
 478         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 479                 rq->wqe.frag_info =
 480                         kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
 481                                      GFP_KERNEL, cpu_to_node(c->cpu));
 482                 if (!rq->wqe.frag_info) {
 483                         err = -ENOMEM;
 484                         goto err_rq_wq_destroy;
 485                 }
 486                 rq->post_wqes = mlx5e_post_rx_wqes;
 487                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 488
 489 #ifdef CONFIG_MLX5_EN_IPSEC
 490                 if (c->priv->ipsec)
 491                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 492                 else
 493 #endif
 494                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 495                 if (!rq->handle_rx_cqe) {
 496                         kfree(rq->wqe.frag_info);
 497                         err = -EINVAL;
 498                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 499                         goto err_rq_wq_destroy;
 500                 }
 501
 502                 byte_count = params->lro_en  ?
 503                                 params->lro_wqe_sz :
 504                                 MLX5E_SW2HW_MTU(params, params->sw_mtu);
 505 #ifdef CONFIG_MLX5_EN_IPSEC
 506                 if (MLX5_IPSEC_DEV(mdev))
 507                         byte_count += MLX5E_METADATA_ETHER_LEN;
 508 #endif
 509                 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
 510
 511                 /* calc the required page order */
 512                 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
 513                 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
 514                 rq->buff.page_order = order_base_2(npages);
 515
 516                 byte_count |= MLX5_HW_START_PADDING;
 517                 rq->mkey_be = c->mkey_be;
 518         }
 519
 520         /* Create a page_pool and register it with rxq */
 521         pp_params.order     = rq->buff.page_order;
 522         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 523         pp_params.pool_size = pool_size;
 524         pp_params.nid       = cpu_to_node(c->cpu);
 525         pp_params.dev       = c->pdev;
 526         pp_params.dma_dir   = rq->buff.map_dir;
 527
 528         /* page_pool can be used even when there is no rq->xdp_prog,
 529          * given page_pool does not handle DMA mapping there is no
 530          * required state to clear. And page_pool gracefully handle
 531          * elevated refcnt.
 532          */
 533         rq->page_pool = page_pool_create(&pp_params);
 534         if (IS_ERR(rq->page_pool)) {
 535                 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 536                         kfree(rq->wqe.frag_info);
 537                 err = PTR_ERR(rq->page_pool);
 538                 rq->page_pool = NULL;
 539                 goto err_rq_wq_destroy;
 540         }
 541         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 542                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 543         if (err)
 544                 goto err_rq_wq_destroy;
 545
 546         for (i = 0; i < wq_sz; i++) {
 547                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 548
 549                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 550                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 551
 552                         wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 553                 }
 554
 555                 wqe->data.byte_count = cpu_to_be32(byte_count);
 556                 wqe->data.lkey = rq->mkey_be;
 557         }
 558
 559         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 560
 561         switch (params->rx_cq_moderation.cq_period_mode) {
 562         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 563                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 564                 break;
 565         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 566         default:
 567                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 568         }
 569
 570         rq->page_cache.head = 0;
 571         rq->page_cache.tail = 0;
 572
 573         return 0;
 574
 575 err_destroy_umr_mkey:
 576         mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 577
 578 err_rq_wq_destroy:
 579         if (rq->xdp_prog)
 580                 bpf_prog_put(rq->xdp_prog);
 581         xdp_rxq_info_unreg(&rq->xdp_rxq);
 582         if (rq->page_pool)
 583                 page_pool_destroy(rq->page_pool);
 584         mlx5_wq_destroy(&rq->wq_ctrl);
 585
 586         return err;
 587 }
 588
 589 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 590 {
 591         int i;
 592
 593         if (rq->xdp_prog)
 594                 bpf_prog_put(rq->xdp_prog);
 595
 596         xdp_rxq_info_unreg(&rq->xdp_rxq);
 597         if (rq->page_pool)
 598                 page_pool_destroy(rq->page_pool);
 599
 600         switch (rq->wq_type) {
 601         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 602                 kfree(rq->mpwqe.info);
 603                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 604                 break;
 605         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 606                 kfree(rq->wqe.frag_info);
 607         }
 608
 609         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 610              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 611                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 612
 613                 mlx5e_page_release(rq, dma_info, false);
 614         }
 615         mlx5_wq_destroy(&rq->wq_ctrl);
 616 }
 617
 618 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 619                            struct mlx5e_rq_param *param)
 620 {
 621         struct mlx5_core_dev *mdev = rq->mdev;
 622
 623         void *in;
 624         void *rqc;
 625         void *wq;
 626         int inlen;
 627         int err;
 628
 629         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 630                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 631         in = kvzalloc(inlen, GFP_KERNEL);
 632         if (!in)
 633                 return -ENOMEM;
 634
 635         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 636         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 637
 638         memcpy(rqc, param->rqc, sizeof(param->rqc));
 639
 640         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 641         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 642         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 643                                                 MLX5_ADAPTER_PAGE_SHIFT);
 644         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 645
 646         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 647                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 648
 649         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 650
 651         kvfree(in);
 652
 653         return err;
 654 }
 655
 656 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 657                                  int next_state)
 658 {
 659         struct mlx5_core_dev *mdev = rq->mdev;
 660
 661         void *in;
 662         void *rqc;
 663         int inlen;
 664         int err;
 665
 666         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 667         in = kvzalloc(inlen, GFP_KERNEL);
 668         if (!in)
 669                 return -ENOMEM;
 670
 671         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 672
 673         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 674         MLX5_SET(rqc, rqc, state, next_state);
 675
 676         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 677
 678         kvfree(in);
 679
 680         return err;
 681 }
 682
 683 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 684 {
 685         struct mlx5e_channel *c = rq->channel;
 686         struct mlx5e_priv *priv = c->priv;
 687         struct mlx5_core_dev *mdev = priv->mdev;
 688
 689         void *in;
 690         void *rqc;
 691         int inlen;
 692         int err;
 693
 694         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 695         in = kvzalloc(inlen, GFP_KERNEL);
 696         if (!in)
 697                 return -ENOMEM;
 698
 699         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 700
 701         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 702         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 703                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 704         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 705         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 706
 707         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 708
 709         kvfree(in);
 710
 711         return err;
 712 }
 713
 714 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 715 {
 716         struct mlx5e_channel *c = rq->channel;
 717         struct mlx5_core_dev *mdev = c->mdev;
 718         void *in;
 719         void *rqc;
 720         int inlen;
 721         int err;
 722
 723         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 724         in = kvzalloc(inlen, GFP_KERNEL);
 725         if (!in)
 726                 return -ENOMEM;
 727
 728         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 729
 730         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 731         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 732                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 733         MLX5_SET(rqc, rqc, vsd, vsd);
 734         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 735
 736         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 737
 738         kvfree(in);
 739
 740         return err;
 741 }
 742
 743 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 744 {
 745         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 746 }
 747
 748 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 749 {
 750         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 751         struct mlx5e_channel *c = rq->channel;
 752
 753         struct mlx5_wq_ll *wq = &rq->wq;
 754         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
 755
 756         while (time_before(jiffies, exp_time)) {
 757                 if (wq->cur_sz >= min_wqes)
 758                         return 0;
 759
 760                 msleep(20);
 761         }
 762
 763         netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 764                     rq->rqn, wq->cur_sz, min_wqes);
 765         return -ETIMEDOUT;
 766 }
 767
 768 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 769 {
 770         struct mlx5_wq_ll *wq = &rq->wq;
 771         struct mlx5e_rx_wqe *wqe;
 772         __be16 wqe_ix_be;
 773         u16 wqe_ix;
 774
 775         /* UMR WQE (if in progress) is always at wq->head */
 776         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 777             rq->mpwqe.umr_in_progress)
 778                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 779
 780         while (!mlx5_wq_ll_is_empty(wq)) {
 781                 wqe_ix_be = *wq->tail_next;
 782                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 783                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 784                 rq->dealloc_wqe(rq, wqe_ix);
 785                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 786                                &wqe->next.next_wqe_index);
 787         }
 788
 789         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
 790                 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
 791                  * but yet to be re-posted.
 792                  */
 793                 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 794
 795                 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
 796                         rq->dealloc_wqe(rq, wqe_ix);
 797         }
 798 }
 799
 800 static int mlx5e_open_rq(struct mlx5e_channel *c,
 801                          struct mlx5e_params *params,
 802                          struct mlx5e_rq_param *param,
 803                          struct mlx5e_rq *rq)
 804 {
 805         int err;
 806
 807         err = mlx5e_alloc_rq(c, params, param, rq);
 808         if (err)
 809                 return err;
 810
 811         err = mlx5e_create_rq(rq, param);
 812         if (err)
 813                 goto err_free_rq;
 814
 815         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 816         if (err)
 817                 goto err_destroy_rq;
 818
 819         if (params->rx_dim_enabled)
 820                 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
 821
 822         return 0;
 823
 824 err_destroy_rq:
 825         mlx5e_destroy_rq(rq);
 826 err_free_rq:
 827         mlx5e_free_rq(rq);
 828
 829         return err;
 830 }
 831
 832 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 833 {
 834         struct mlx5e_icosq *sq = &rq->channel->icosq;
 835         u16 pi = sq->pc & sq->wq.sz_m1;
 836         struct mlx5e_tx_wqe *nopwqe;
 837
 838         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 839         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 840         nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
 841         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 842 }
 843
 844 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 845 {
 846         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 847         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 848 }
 849
 850 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 851 {
 852         cancel_work_sync(&rq->dim.work);
 853         mlx5e_destroy_rq(rq);
 854         mlx5e_free_rx_descs(rq);
 855         mlx5e_free_rq(rq);
 856 }
 857
 858 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 859 {
 860         kfree(sq->db.di);
 861 }
 862
 863 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 864 {
 865         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 866
 867         sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
 868                                      GFP_KERNEL, numa);
 869         if (!sq->db.di) {
 870                 mlx5e_free_xdpsq_db(sq);
 871                 return -ENOMEM;
 872         }
 873
 874         return 0;
 875 }
 876
 877 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 878                              struct mlx5e_params *params,
 879                              struct mlx5e_sq_param *param,
 880                              struct mlx5e_xdpsq *sq)
 881 {
 882         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 883         struct mlx5_core_dev *mdev = c->mdev;
 884         int err;
 885
 886         sq->pdev      = c->pdev;
 887         sq->mkey_be   = c->mkey_be;
 888         sq->channel   = c;
 889         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 890         sq->min_inline_mode = params->tx_min_inline_mode;
 891
 892         param->wq.db_numa_node = cpu_to_node(c->cpu);
 893         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 894         if (err)
 895                 return err;
 896         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 897
 898         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 899         if (err)
 900                 goto err_sq_wq_destroy;
 901
 902         return 0;
 903
 904 err_sq_wq_destroy:
 905         mlx5_wq_destroy(&sq->wq_ctrl);
 906
 907         return err;
 908 }
 909
 910 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
 911 {
 912         mlx5e_free_xdpsq_db(sq);
 913         mlx5_wq_destroy(&sq->wq_ctrl);
 914 }
 915
 916 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
 917 {
 918         kfree(sq->db.ico_wqe);
 919 }
 920
 921 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
 922 {
 923         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 924
 925         sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
 926                                       GFP_KERNEL, numa);
 927         if (!sq->db.ico_wqe)
 928                 return -ENOMEM;
 929
 930         return 0;
 931 }
 932
 933 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
 934                              struct mlx5e_sq_param *param,
 935                              struct mlx5e_icosq *sq)
 936 {
 937         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 938         struct mlx5_core_dev *mdev = c->mdev;
 939         int err;
 940
 941         sq->channel   = c;
 942         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 943
 944         param->wq.db_numa_node = cpu_to_node(c->cpu);
 945         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
 946         if (err)
 947                 return err;
 948         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 949
 950         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
 951         if (err)
 952                 goto err_sq_wq_destroy;
 953
 954         sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
 955
 956         return 0;
 957
 958 err_sq_wq_destroy:
 959         mlx5_wq_destroy(&sq->wq_ctrl);
 960
 961         return err;
 962 }
 963
 964 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
 965 {
 966         mlx5e_free_icosq_db(sq);
 967         mlx5_wq_destroy(&sq->wq_ctrl);
 968 }
 969
 970 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
 971 {
 972         kfree(sq->db.wqe_info);
 973         kfree(sq->db.dma_fifo);
 974 }
 975
 976 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
 977 {
 978         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 979         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 980
 981         sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
 982                                            GFP_KERNEL, numa);
 983         sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
 984                                            GFP_KERNEL, numa);
 985         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
 986                 mlx5e_free_txqsq_db(sq);
 987                 return -ENOMEM;
 988         }
 989
 990         sq->dma_fifo_mask = df_sz - 1;
 991
 992         return 0;
 993 }
 994
 995 static void mlx5e_sq_recover(struct work_struct *work);
 996 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
 997                              int txq_ix,
 998                              struct mlx5e_params *params,
 999                              struct mlx5e_sq_param *param,
1000                              struct mlx5e_txqsq *sq)
1001 {
1002         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1003         struct mlx5_core_dev *mdev = c->mdev;
1004         int err;
1005
1006         sq->pdev      = c->pdev;
1007         sq->tstamp    = c->tstamp;
1008         sq->clock     = &mdev->clock;
1009         sq->mkey_be   = c->mkey_be;
1010         sq->channel   = c;
1011         sq->txq_ix    = txq_ix;
1012         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1013         sq->min_inline_mode = params->tx_min_inline_mode;
1014         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1015         if (MLX5_IPSEC_DEV(c->priv->mdev))
1016                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1017
1018         param->wq.db_numa_node = cpu_to_node(c->cpu);
1019         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1020         if (err)
1021                 return err;
1022         sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];
1023
1024         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1025         if (err)
1026                 goto err_sq_wq_destroy;
1027
1028         sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1029
1030         return 0;
1031
1032 err_sq_wq_destroy:
1033         mlx5_wq_destroy(&sq->wq_ctrl);
1034
1035         return err;
1036 }
1037
1038 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1039 {
1040         mlx5e_free_txqsq_db(sq);
1041         mlx5_wq_destroy(&sq->wq_ctrl);
1042 }
1043
1044 struct mlx5e_create_sq_param {
1045         struct mlx5_wq_ctrl        *wq_ctrl;
1046         u32                         cqn;
1047         u32                         tisn;
1048         u8                          tis_lst_sz;
1049         u8                          min_inline_mode;
1050 };
1051
1052 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1053                            struct mlx5e_sq_param *param,
1054                            struct mlx5e_create_sq_param *csp,
1055                            u32 *sqn)
1056 {
1057         void *in;
1058         void *sqc;
1059         void *wq;
1060         int inlen;
1061         int err;
1062
1063         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1064                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1065         in = kvzalloc(inlen, GFP_KERNEL);
1066         if (!in)
1067                 return -ENOMEM;
1068
1069         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1070         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1071
1072         memcpy(sqc, param->sqc, sizeof(param->sqc));
1073         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1074         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1075         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1076
1077         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1078                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1079
1080         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1081         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1082
1083         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1084         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1085         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1086                                           MLX5_ADAPTER_PAGE_SHIFT);
1087         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1088
1089         mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1090
1091         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1092
1093         kvfree(in);
1094
1095         return err;
1096 }
1097
1098 struct mlx5e_modify_sq_param {
1099         int curr_state;
1100         int next_state;
1101         bool rl_update;
1102         int rl_index;
1103 };
1104
1105 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1106                            struct mlx5e_modify_sq_param *p)
1107 {
1108         void *in;
1109         void *sqc;
1110         int inlen;
1111         int err;
1112
1113         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1114         in = kvzalloc(inlen, GFP_KERNEL);
1115         if (!in)
1116                 return -ENOMEM;
1117
1118         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1119
1120         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1121         MLX5_SET(sqc, sqc, state, p->next_state);
1122         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1123                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1124                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1125         }
1126
1127         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1128
1129         kvfree(in);
1130
1131         return err;
1132 }
1133
1134 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1135 {
1136         mlx5_core_destroy_sq(mdev, sqn);
1137 }
1138
1139 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1140                                struct mlx5e_sq_param *param,
1141                                struct mlx5e_create_sq_param *csp,
1142                                u32 *sqn)
1143 {
1144         struct mlx5e_modify_sq_param msp = {0};
1145         int err;
1146
1147         err = mlx5e_create_sq(mdev, param, csp, sqn);
1148         if (err)
1149                 return err;
1150
1151         msp.curr_state = MLX5_SQC_STATE_RST;
1152         msp.next_state = MLX5_SQC_STATE_RDY;
1153         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1154         if (err)
1155                 mlx5e_destroy_sq(mdev, *sqn);
1156
1157         return err;
1158 }
1159
1160 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1161                                 struct mlx5e_txqsq *sq, u32 rate);
1162
1163 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1164                             u32 tisn,
1165                             int txq_ix,
1166                             struct mlx5e_params *params,
1167                             struct mlx5e_sq_param *param,
1168                             struct mlx5e_txqsq *sq)
1169 {
1170         struct mlx5e_create_sq_param csp = {};
1171         u32 tx_rate;
1172         int err;
1173
1174         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1175         if (err)
1176                 return err;
1177
1178         csp.tisn            = tisn;
1179         csp.tis_lst_sz      = 1;
1180         csp.cqn             = sq->cq.mcq.cqn;
1181         csp.wq_ctrl         = &sq->wq_ctrl;
1182         csp.min_inline_mode = sq->min_inline_mode;
1183         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1184         if (err)
1185                 goto err_free_txqsq;
1186
1187         tx_rate = c->priv->tx_rates[sq->txq_ix];
1188         if (tx_rate)
1189                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1190
1191         return 0;
1192
1193 err_free_txqsq:
1194         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1195         mlx5e_free_txqsq(sq);
1196
1197         return err;
1198 }
1199
1200 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1201 {
1202         WARN_ONCE(sq->cc != sq->pc,
1203                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1204                   sq->sqn, sq->cc, sq->pc);
1205         sq->cc = 0;
1206         sq->dma_fifo_cc = 0;
1207         sq->pc = 0;
1208 }
1209
1210 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1211 {
1212         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1213         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1214         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1215         netdev_tx_reset_queue(sq->txq);
1216         netif_tx_start_queue(sq->txq);
1217 }
1218
1219 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1220 {
1221         __netif_tx_lock_bh(txq);
1222         netif_tx_stop_queue(txq);
1223         __netif_tx_unlock_bh(txq);
1224 }
1225
1226 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1227 {
1228         struct mlx5e_channel *c = sq->channel;
1229
1230         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1231         /* prevent netif_tx_wake_queue */
1232         napi_synchronize(&c->napi);
1233
1234         netif_tx_disable_queue(sq->txq);
1235
1236         /* last doorbell out, godspeed .. */
1237         if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1238                 struct mlx5e_tx_wqe *nop;
1239
1240                 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1241                 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1242                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1243         }
1244 }
1245
1246 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1247 {
1248         struct mlx5e_channel *c = sq->channel;
1249         struct mlx5_core_dev *mdev = c->mdev;
1250         struct mlx5_rate_limit rl = {0};
1251
1252         mlx5e_destroy_sq(mdev, sq->sqn);
1253         if (sq->rate_limit) {
1254                 rl.rate = sq->rate_limit;
1255                 mlx5_rl_remove_rate(mdev, &rl);
1256         }
1257         mlx5e_free_txqsq_descs(sq);
1258         mlx5e_free_txqsq(sq);
1259 }
1260
1261 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1262 {
1263         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1264
1265         while (time_before(jiffies, exp_time)) {
1266                 if (sq->cc == sq->pc)
1267                         return 0;
1268
1269                 msleep(20);
1270         }
1271
1272         netdev_err(sq->channel->netdev,
1273                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1274                    sq->sqn, sq->cc, sq->pc);
1275
1276         return -ETIMEDOUT;
1277 }
1278
1279 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1280 {
1281         struct mlx5_core_dev *mdev = sq->channel->mdev;
1282         struct net_device *dev = sq->channel->netdev;
1283         struct mlx5e_modify_sq_param msp = {0};
1284         int err;
1285
1286         msp.curr_state = curr_state;
1287         msp.next_state = MLX5_SQC_STATE_RST;
1288
1289         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1290         if (err) {
1291                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1292                 return err;
1293         }
1294
1295         memset(&msp, 0, sizeof(msp));
1296         msp.curr_state = MLX5_SQC_STATE_RST;
1297         msp.next_state = MLX5_SQC_STATE_RDY;
1298
1299         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1300         if (err) {
1301                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1302                 return err;
1303         }
1304
1305         return 0;
1306 }
1307
1308 static void mlx5e_sq_recover(struct work_struct *work)
1309 {
1310         struct mlx5e_txqsq_recover *recover =
1311                 container_of(work, struct mlx5e_txqsq_recover,
1312                              recover_work);
1313         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1314                                               recover);
1315         struct mlx5_core_dev *mdev = sq->channel->mdev;
1316         struct net_device *dev = sq->channel->netdev;
1317         u8 state;
1318         int err;
1319
1320         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1321         if (err) {
1322                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1323                            sq->sqn, err);
1324                 return;
1325         }
1326
1327         if (state != MLX5_RQC_STATE_ERR) {
1328                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1329                 return;
1330         }
1331
1332         netif_tx_disable_queue(sq->txq);
1333
1334         if (mlx5e_wait_for_sq_flush(sq))
1335                 return;
1336
1337         /* If the interval between two consecutive recovers per SQ is too
1338          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1339          * If we reached this state, there is probably a bug that needs to be
1340          * fixed. let's keep the queue close and let tx timeout cleanup.
1341          */
1342         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1343             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1344                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1345                            sq->sqn);
1346                 return;
1347         }
1348
1349         /* At this point, no new packets will arrive from the stack as TXQ is
1350          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1351          * pending WQEs.  SQ can safely reset the SQ.
1352          */
1353         if (mlx5e_sq_to_ready(sq, state))
1354                 return;
1355
1356         mlx5e_reset_txqsq_cc_pc(sq);
1357         sq->stats.recover++;
1358         recover->last_recover = jiffies;
1359         mlx5e_activate_txqsq(sq);
1360 }
1361
1362 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1363                             struct mlx5e_params *params,
1364                             struct mlx5e_sq_param *param,
1365                             struct mlx5e_icosq *sq)
1366 {
1367         struct mlx5e_create_sq_param csp = {};
1368         int err;
1369
1370         err = mlx5e_alloc_icosq(c, param, sq);
1371         if (err)
1372                 return err;
1373
1374         csp.cqn             = sq->cq.mcq.cqn;
1375         csp.wq_ctrl         = &sq->wq_ctrl;
1376         csp.min_inline_mode = params->tx_min_inline_mode;
1377         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1378         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1379         if (err)
1380                 goto err_free_icosq;
1381
1382         return 0;
1383
1384 err_free_icosq:
1385         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1386         mlx5e_free_icosq(sq);
1387
1388         return err;
1389 }
1390
1391 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1392 {
1393         struct mlx5e_channel *c = sq->channel;
1394
1395         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1396         napi_synchronize(&c->napi);
1397
1398         mlx5e_destroy_sq(c->mdev, sq->sqn);
1399         mlx5e_free_icosq(sq);
1400 }
1401
1402 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1403                             struct mlx5e_params *params,
1404                             struct mlx5e_sq_param *param,
1405                             struct mlx5e_xdpsq *sq)
1406 {
1407         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1408         struct mlx5e_create_sq_param csp = {};
1409         unsigned int inline_hdr_sz = 0;
1410         int err;
1411         int i;
1412
1413         err = mlx5e_alloc_xdpsq(c, params, param, sq);
1414         if (err)
1415                 return err;
1416
1417         csp.tis_lst_sz      = 1;
1418         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1419         csp.cqn             = sq->cq.mcq.cqn;
1420         csp.wq_ctrl         = &sq->wq_ctrl;
1421         csp.min_inline_mode = sq->min_inline_mode;
1422         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1423         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1424         if (err)
1425                 goto err_free_xdpsq;
1426
1427         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1428                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1429                 ds_cnt++;
1430         }
1431
1432         /* Pre initialize fixed WQE fields */
1433         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1434                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1435                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1436                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1437                 struct mlx5_wqe_data_seg *dseg;
1438
1439                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1440                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1441
1442                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1443                 dseg->lkey = sq->mkey_be;
1444         }
1445
1446         return 0;
1447
1448 err_free_xdpsq:
1449         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1450         mlx5e_free_xdpsq(sq);
1451
1452         return err;
1453 }
1454
1455 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1456 {
1457         struct mlx5e_channel *c = sq->channel;
1458
1459         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1460         napi_synchronize(&c->napi);
1461
1462         mlx5e_destroy_sq(c->mdev, sq->sqn);
1463         mlx5e_free_xdpsq_descs(sq);
1464         mlx5e_free_xdpsq(sq);
1465 }
1466
1467 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1468                                  struct mlx5e_cq_param *param,
1469                                  struct mlx5e_cq *cq)
1470 {
1471         struct mlx5_core_cq *mcq = &cq->mcq;
1472         int eqn_not_used;
1473         unsigned int irqn;
1474         int err;
1475         u32 i;
1476
1477         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1478                                &cq->wq_ctrl);
1479         if (err)
1480                 return err;
1481
1482         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1483
1484         mcq->cqe_sz     = 64;
1485         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1486         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1487         *mcq->set_ci_db = 0;
1488         *mcq->arm_db    = 0;
1489         mcq->vector     = param->eq_ix;
1490         mcq->comp       = mlx5e_completion_event;
1491         mcq->event      = mlx5e_cq_error_event;
1492         mcq->irqn       = irqn;
1493
1494         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1495                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1496
1497                 cqe->op_own = 0xf1;
1498         }
1499
1500         cq->mdev = mdev;
1501
1502         return 0;
1503 }
1504
1505 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1506                           struct mlx5e_cq_param *param,
1507                           struct mlx5e_cq *cq)
1508 {
1509         struct mlx5_core_dev *mdev = c->priv->mdev;
1510         int err;
1511
1512         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1513         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1514         param->eq_ix   = c->ix;
1515
1516         err = mlx5e_alloc_cq_common(mdev, param, cq);
1517
1518         cq->napi    = &c->napi;
1519         cq->channel = c;
1520
1521         return err;
1522 }
1523
1524 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1525 {
1526         mlx5_cqwq_destroy(&cq->wq_ctrl);
1527 }
1528
1529 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1530 {
1531         struct mlx5_core_dev *mdev = cq->mdev;
1532         struct mlx5_core_cq *mcq = &cq->mcq;
1533
1534         void *in;
1535         void *cqc;
1536         int inlen;
1537         unsigned int irqn_not_used;
1538         int eqn;
1539         int err;
1540
1541         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1542                 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1543         in = kvzalloc(inlen, GFP_KERNEL);
1544         if (!in)
1545                 return -ENOMEM;
1546
1547         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1548
1549         memcpy(cqc, param->cqc, sizeof(param->cqc));
1550
1551         mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1552                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1553
1554         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1555
1556         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1557         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1558         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1559         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1560                                             MLX5_ADAPTER_PAGE_SHIFT);
1561         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1562
1563         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1564
1565         kvfree(in);
1566
1567         if (err)
1568                 return err;
1569
1570         mlx5e_cq_arm(cq);
1571
1572         return 0;
1573 }
1574
1575 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1576 {
1577         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1578 }
1579
1580 static int mlx5e_open_cq(struct mlx5e_channel *c,
1581                          struct net_dim_cq_moder moder,
1582                          struct mlx5e_cq_param *param,
1583                          struct mlx5e_cq *cq)
1584 {
1585         struct mlx5_core_dev *mdev = c->mdev;
1586         int err;
1587
1588         err = mlx5e_alloc_cq(c, param, cq);
1589         if (err)
1590                 return err;
1591
1592         err = mlx5e_create_cq(cq, param);
1593         if (err)
1594                 goto err_free_cq;
1595
1596         if (MLX5_CAP_GEN(mdev, cq_moderation))
1597                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1598         return 0;
1599
1600 err_free_cq:
1601         mlx5e_free_cq(cq);
1602
1603         return err;
1604 }
1605
1606 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1607 {
1608         mlx5e_destroy_cq(cq);
1609         mlx5e_free_cq(cq);
1610 }
1611
1612 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1613 {
1614         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1615 }
1616
1617 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1618                              struct mlx5e_params *params,
1619                              struct mlx5e_channel_param *cparam)
1620 {
1621         int err;
1622         int tc;
1623
1624         for (tc = 0; tc < c->num_tc; tc++) {
1625                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1626                                     &cparam->tx_cq, &c->sq[tc].cq);
1627                 if (err)
1628                         goto err_close_tx_cqs;
1629         }
1630
1631         return 0;
1632
1633 err_close_tx_cqs:
1634         for (tc--; tc >= 0; tc--)
1635                 mlx5e_close_cq(&c->sq[tc].cq);
1636
1637         return err;
1638 }
1639
1640 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1641 {
1642         int tc;
1643
1644         for (tc = 0; tc < c->num_tc; tc++)
1645                 mlx5e_close_cq(&c->sq[tc].cq);
1646 }
1647
1648 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1649                           struct mlx5e_params *params,
1650                           struct mlx5e_channel_param *cparam)
1651 {
1652         int err;
1653         int tc;
1654
1655         for (tc = 0; tc < params->num_tc; tc++) {
1656                 int txq_ix = c->ix + tc * params->num_channels;
1657
1658                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1659                                        params, &cparam->sq, &c->sq[tc]);
1660                 if (err)
1661                         goto err_close_sqs;
1662         }
1663
1664         return 0;
1665
1666 err_close_sqs:
1667         for (tc--; tc >= 0; tc--)
1668                 mlx5e_close_txqsq(&c->sq[tc]);
1669
1670         return err;
1671 }
1672
1673 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1674 {
1675         int tc;
1676
1677         for (tc = 0; tc < c->num_tc; tc++)
1678                 mlx5e_close_txqsq(&c->sq[tc]);
1679 }
1680
1681 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1682                                 struct mlx5e_txqsq *sq, u32 rate)
1683 {
1684         struct mlx5e_priv *priv = netdev_priv(dev);
1685         struct mlx5_core_dev *mdev = priv->mdev;
1686         struct mlx5e_modify_sq_param msp = {0};
1687         struct mlx5_rate_limit rl = {0};
1688         u16 rl_index = 0;
1689         int err;
1690
1691         if (rate == sq->rate_limit)
1692                 /* nothing to do */
1693                 return 0;
1694
1695         if (sq->rate_limit) {
1696                 rl.rate = sq->rate_limit;
1697                 /* remove current rl index to free space to next ones */
1698                 mlx5_rl_remove_rate(mdev, &rl);
1699         }
1700
1701         sq->rate_limit = 0;
1702
1703         if (rate) {
1704                 rl.rate = rate;
1705                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1706                 if (err) {
1707                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1708                                    rate, err);
1709                         return err;
1710                 }
1711         }
1712
1713         msp.curr_state = MLX5_SQC_STATE_RDY;
1714         msp.next_state = MLX5_SQC_STATE_RDY;
1715         msp.rl_index   = rl_index;
1716         msp.rl_update  = true;
1717         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1718         if (err) {
1719                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1720                            rate, err);
1721                 /* remove the rate from the table */
1722                 if (rate)
1723                         mlx5_rl_remove_rate(mdev, &rl);
1724                 return err;
1725         }
1726
1727         sq->rate_limit = rate;
1728         return 0;
1729 }
1730
1731 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1732 {
1733         struct mlx5e_priv *priv = netdev_priv(dev);
1734         struct mlx5_core_dev *mdev = priv->mdev;
1735         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1736         int err = 0;
1737
1738         if (!mlx5_rl_is_supported(mdev)) {
1739                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1740                 return -EINVAL;
1741         }
1742
1743         /* rate is given in Mb/sec, HW config is in Kb/sec */
1744         rate = rate << 10;
1745
1746         /* Check whether rate in valid range, 0 is always valid */
1747         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1748                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1749                 return -ERANGE;
1750         }
1751
1752         mutex_lock(&priv->state_lock);
1753         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1754                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1755         if (!err)
1756                 priv->tx_rates[index] = rate;
1757         mutex_unlock(&priv->state_lock);
1758
1759         return err;
1760 }
1761
1762 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1763                               struct mlx5e_params *params,
1764                               struct mlx5e_channel_param *cparam,
1765                               struct mlx5e_channel **cp)
1766 {
1767         struct net_dim_cq_moder icocq_moder = {0, 0};
1768         struct net_device *netdev = priv->netdev;
1769         int cpu = mlx5e_get_cpu(priv, ix);
1770         struct mlx5e_channel *c;
1771         unsigned int irq;
1772         int err;
1773         int eqn;
1774
1775         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1776         if (!c)
1777                 return -ENOMEM;
1778
1779         c->priv     = priv;
1780         c->mdev     = priv->mdev;
1781         c->tstamp   = &priv->tstamp;
1782         c->ix       = ix;
1783         c->cpu      = cpu;
1784         c->pdev     = &priv->mdev->pdev->dev;
1785         c->netdev   = priv->netdev;
1786         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1787         c->num_tc   = params->num_tc;
1788         c->xdp      = !!params->xdp_prog;
1789
1790         mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1791         c->irq_desc = irq_to_desc(irq);
1792
1793         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1794
1795         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1796         if (err)
1797                 goto err_napi_del;
1798
1799         err = mlx5e_open_tx_cqs(c, params, cparam);
1800         if (err)
1801                 goto err_close_icosq_cq;
1802
1803         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1804         if (err)
1805                 goto err_close_tx_cqs;
1806
1807         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1808         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1809                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1810         if (err)
1811                 goto err_close_rx_cq;
1812
1813         napi_enable(&c->napi);
1814
1815         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1816         if (err)
1817                 goto err_disable_napi;
1818
1819         err = mlx5e_open_sqs(c, params, cparam);
1820         if (err)
1821                 goto err_close_icosq;
1822
1823         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1824         if (err)
1825                 goto err_close_sqs;
1826
1827         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1828         if (err)
1829                 goto err_close_xdp_sq;
1830
1831         *cp = c;
1832
1833         return 0;
1834 err_close_xdp_sq:
1835         if (c->xdp)
1836                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1837
1838 err_close_sqs:
1839         mlx5e_close_sqs(c);
1840
1841 err_close_icosq:
1842         mlx5e_close_icosq(&c->icosq);
1843
1844 err_disable_napi:
1845         napi_disable(&c->napi);
1846         if (c->xdp)
1847                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1848
1849 err_close_rx_cq:
1850         mlx5e_close_cq(&c->rq.cq);
1851
1852 err_close_tx_cqs:
1853         mlx5e_close_tx_cqs(c);
1854
1855 err_close_icosq_cq:
1856         mlx5e_close_cq(&c->icosq.cq);
1857
1858 err_napi_del:
1859         netif_napi_del(&c->napi);
1860         kfree(c);
1861
1862         return err;
1863 }
1864
1865 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1866 {
1867         int tc;
1868
1869         for (tc = 0; tc < c->num_tc; tc++)
1870                 mlx5e_activate_txqsq(&c->sq[tc]);
1871         mlx5e_activate_rq(&c->rq);
1872         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1873 }
1874
1875 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1876 {
1877         int tc;
1878
1879         mlx5e_deactivate_rq(&c->rq);
1880         for (tc = 0; tc < c->num_tc; tc++)
1881                 mlx5e_deactivate_txqsq(&c->sq[tc]);
1882 }
1883
1884 static void mlx5e_close_channel(struct mlx5e_channel *c)
1885 {
1886         mlx5e_close_rq(&c->rq);
1887         if (c->xdp)
1888                 mlx5e_close_xdpsq(&c->rq.xdpsq);
1889         mlx5e_close_sqs(c);
1890         mlx5e_close_icosq(&c->icosq);
1891         napi_disable(&c->napi);
1892         if (c->xdp)
1893                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1894         mlx5e_close_cq(&c->rq.cq);
1895         mlx5e_close_tx_cqs(c);
1896         mlx5e_close_cq(&c->icosq.cq);
1897         netif_napi_del(&c->napi);
1898
1899         kfree(c);
1900 }
1901
1902 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1903                                  struct mlx5e_params *params,
1904                                  struct mlx5e_rq_param *param)
1905 {
1906         struct mlx5_core_dev *mdev = priv->mdev;
1907         void *rqc = param->rqc;
1908         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1909
1910         switch (params->rq_wq_type) {
1911         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1912                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1913                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1914                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1915                 MLX5_SET(wq, wq, log_wqe_stride_size,
1916                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1917                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1918                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1919                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1920                 break;
1921         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1922                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1923                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1924         }
1925
1926         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1927         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1928         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
1929         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1930         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
1931         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
1932
1933         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1934         param->wq.linear = 1;
1935 }
1936
1937 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1938                                       struct mlx5e_rq_param *param)
1939 {
1940         struct mlx5_core_dev *mdev = priv->mdev;
1941         void *rqc = param->rqc;
1942         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1943
1944         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1945         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1946         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1947
1948         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1949 }
1950
1951 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1952                                         struct mlx5e_sq_param *param)
1953 {
1954         void *sqc = param->sqc;
1955         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1956
1957         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1958         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1959
1960         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1961 }
1962
1963 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1964                                  struct mlx5e_params *params,
1965                                  struct mlx5e_sq_param *param)
1966 {
1967         void *sqc = param->sqc;
1968         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1969
1970         mlx5e_build_sq_param_common(priv, param);
1971         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1972         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1973 }
1974
1975 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1976                                         struct mlx5e_cq_param *param)
1977 {
1978         void *cqc = param->cqc;
1979
1980         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1981 }
1982
1983 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1984                                     struct mlx5e_params *params,
1985                                     struct mlx5e_cq_param *param)
1986 {
1987         struct mlx5_core_dev *mdev = priv->mdev;
1988         void *cqc = param->cqc;
1989         u8 log_cq_size;
1990
1991         switch (params->rq_wq_type) {
1992         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1993                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
1994                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
1995                 break;
1996         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1997                 log_cq_size = params->log_rq_mtu_frames;
1998         }
1999
2000         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2001         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2002                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2003                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2004         }
2005
2006         mlx5e_build_common_cq_param(priv, param);
2007         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2008 }
2009
2010 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2011                                     struct mlx5e_params *params,
2012                                     struct mlx5e_cq_param *param)
2013 {
2014         void *cqc = param->cqc;
2015
2016         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2017
2018         mlx5e_build_common_cq_param(priv, param);
2019         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2020 }
2021
2022 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2023                                      u8 log_wq_size,
2024                                      struct mlx5e_cq_param *param)
2025 {
2026         void *cqc = param->cqc;
2027
2028         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2029
2030         mlx5e_build_common_cq_param(priv, param);
2031
2032         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2033 }
2034
2035 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2036                                     u8 log_wq_size,
2037                                     struct mlx5e_sq_param *param)
2038 {
2039         void *sqc = param->sqc;
2040         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2041
2042         mlx5e_build_sq_param_common(priv, param);
2043
2044         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2045         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2046 }
2047
2048 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2049                                     struct mlx5e_params *params,
2050                                     struct mlx5e_sq_param *param)
2051 {
2052         void *sqc = param->sqc;
2053         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2054
2055         mlx5e_build_sq_param_common(priv, param);
2056         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2057 }
2058
2059 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2060                                       struct mlx5e_params *params,
2061                                       struct mlx5e_channel_param *cparam)
2062 {
2063         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2064
2065         mlx5e_build_rq_param(priv, params, &cparam->rq);
2066         mlx5e_build_sq_param(priv, params, &cparam->sq);
2067         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2068         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2069         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2070         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2071         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2072 }
2073
2074 int mlx5e_open_channels(struct mlx5e_priv *priv,
2075                         struct mlx5e_channels *chs)
2076 {
2077         struct mlx5e_channel_param *cparam;
2078         int err = -ENOMEM;
2079         int i;
2080
2081         chs->num = chs->params.num_channels;
2082
2083         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2084         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2085         if (!chs->c || !cparam)
2086                 goto err_free;
2087
2088         mlx5e_build_channel_param(priv, &chs->params, cparam);
2089         for (i = 0; i < chs->num; i++) {
2090                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2091                 if (err)
2092                         goto err_close_channels;
2093         }
2094
2095         kfree(cparam);
2096         return 0;
2097
2098 err_close_channels:
2099         for (i--; i >= 0; i--)
2100                 mlx5e_close_channel(chs->c[i]);
2101
2102 err_free:
2103         kfree(chs->c);
2104         kfree(cparam);
2105         chs->num = 0;
2106         return err;
2107 }
2108
2109 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2110 {
2111         int i;
2112
2113         for (i = 0; i < chs->num; i++)
2114                 mlx5e_activate_channel(chs->c[i]);
2115 }
2116
2117 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2118 {
2119         int err = 0;
2120         int i;
2121
2122         for (i = 0; i < chs->num; i++) {
2123                 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2124                 if (err)
2125                         break;
2126         }
2127
2128         return err;
2129 }
2130
2131 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2132 {
2133         int i;
2134
2135         for (i = 0; i < chs->num; i++)
2136                 mlx5e_deactivate_channel(chs->c[i]);
2137 }
2138
2139 void mlx5e_close_channels(struct mlx5e_channels *chs)
2140 {
2141         int i;
2142
2143         for (i = 0; i < chs->num; i++)
2144                 mlx5e_close_channel(chs->c[i]);
2145
2146         kfree(chs->c);
2147         chs->num = 0;
2148 }
2149
2150 static int
2151 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2152 {
2153         struct mlx5_core_dev *mdev = priv->mdev;
2154         void *rqtc;
2155         int inlen;
2156         int err;
2157         u32 *in;
2158         int i;
2159
2160         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2161         in = kvzalloc(inlen, GFP_KERNEL);
2162         if (!in)
2163                 return -ENOMEM;
2164
2165         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2166
2167         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2168         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2169
2170         for (i = 0; i < sz; i++)
2171                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2172
2173         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2174         if (!err)
2175                 rqt->enabled = true;
2176
2177         kvfree(in);
2178         return err;
2179 }
2180
2181 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2182 {
2183         rqt->enabled = false;
2184         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2185 }
2186
2187 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2188 {
2189         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2190         int err;
2191
2192         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2193         if (err)
2194                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2195         return err;
2196 }
2197
2198 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2199 {
2200         struct mlx5e_rqt *rqt;
2201         int err;
2202         int ix;
2203
2204         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2205                 rqt = &priv->direct_tir[ix].rqt;
2206                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2207                 if (err)
2208                         goto err_destroy_rqts;
2209         }
2210
2211         return 0;
2212
2213 err_destroy_rqts:
2214         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2215         for (ix--; ix >= 0; ix--)
2216                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2217
2218         return err;
2219 }
2220
2221 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2222 {
2223         int i;
2224
2225         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2226                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2227 }
2228
2229 static int mlx5e_rx_hash_fn(int hfunc)
2230 {
2231         return (hfunc == ETH_RSS_HASH_TOP) ?
2232                MLX5_RX_HASH_FN_TOEPLITZ :
2233                MLX5_RX_HASH_FN_INVERTED_XOR8;
2234 }
2235
2236 int mlx5e_bits_invert(unsigned long a, int size)
2237 {
2238         int inv = 0;
2239         int i;
2240
2241         for (i = 0; i < size; i++)
2242                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2243
2244         return inv;
2245 }
2246
2247 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2248                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2249 {
2250         int i;
2251
2252         for (i = 0; i < sz; i++) {
2253                 u32 rqn;
2254
2255                 if (rrp.is_rss) {
2256                         int ix = i;
2257
2258                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2259                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2260
2261                         ix = priv->channels.params.indirection_rqt[ix];
2262                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2263                 } else {
2264                         rqn = rrp.rqn;
2265                 }
2266                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2267         }
2268 }
2269
2270 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2271                        struct mlx5e_redirect_rqt_param rrp)
2272 {
2273         struct mlx5_core_dev *mdev = priv->mdev;
2274         void *rqtc;
2275         int inlen;
2276         u32 *in;
2277         int err;
2278
2279         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2280         in = kvzalloc(inlen, GFP_KERNEL);
2281         if (!in)
2282                 return -ENOMEM;
2283
2284         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2285
2286         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2287         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2288         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2289         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2290
2291         kvfree(in);
2292         return err;
2293 }
2294
2295 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2296                                 struct mlx5e_redirect_rqt_param rrp)
2297 {
2298         if (!rrp.is_rss)
2299                 return rrp.rqn;
2300
2301         if (ix >= rrp.rss.channels->num)
2302                 return priv->drop_rq.rqn;
2303
2304         return rrp.rss.channels->c[ix]->rq.rqn;
2305 }
2306
2307 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2308                                 struct mlx5e_redirect_rqt_param rrp)
2309 {
2310         u32 rqtn;
2311         int ix;
2312
2313         if (priv->indir_rqt.enabled) {
2314                 /* RSS RQ table */
2315                 rqtn = priv->indir_rqt.rqtn;
2316                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2317         }
2318
2319         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2320                 struct mlx5e_redirect_rqt_param direct_rrp = {
2321                         .is_rss = false,
2322                         {
2323                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2324                         },
2325                 };
2326
2327                 /* Direct RQ Tables */
2328                 if (!priv->direct_tir[ix].rqt.enabled)
2329                         continue;
2330
2331                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2332                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2333         }
2334 }
2335
2336 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2337                                             struct mlx5e_channels *chs)
2338 {
2339         struct mlx5e_redirect_rqt_param rrp = {
2340                 .is_rss        = true,
2341                 {
2342                         .rss = {
2343                                 .channels  = chs,
2344                                 .hfunc     = chs->params.rss_hfunc,
2345                         }
2346                 },
2347         };
2348
2349         mlx5e_redirect_rqts(priv, rrp);
2350 }
2351
2352 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2353 {
2354         struct mlx5e_redirect_rqt_param drop_rrp = {
2355                 .is_rss = false,
2356                 {
2357                         .rqn = priv->drop_rq.rqn,
2358                 },
2359         };
2360
2361         mlx5e_redirect_rqts(priv, drop_rrp);
2362 }
2363
2364 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2365 {
2366         if (!params->lro_en)
2367                 return;
2368
2369 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2370
2371         MLX5_SET(tirc, tirc, lro_enable_mask,
2372                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2373                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2374         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2375                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2376         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2377 }
2378
2379 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2380                                     enum mlx5e_traffic_types tt,
2381                                     void *tirc, bool inner)
2382 {
2383         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2384                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2385
2386 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2387                                  MLX5_HASH_FIELD_SEL_DST_IP)
2388
2389 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2390                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2391                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2392                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2393
2394 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2395                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2396                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2397
2398         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2399         if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2400                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2401                                              rx_hash_toeplitz_key);
2402                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2403                                                rx_hash_toeplitz_key);
2404
2405                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2406                 memcpy(rss_key, params->toeplitz_hash_key, len);
2407         }
2408
2409         switch (tt) {
2410         case MLX5E_TT_IPV4_TCP:
2411                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2412                          MLX5_L3_PROT_TYPE_IPV4);
2413                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2414                          MLX5_L4_PROT_TYPE_TCP);
2415                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2416                          MLX5_HASH_IP_L4PORTS);
2417                 break;
2418
2419         case MLX5E_TT_IPV6_TCP:
2420                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2421                          MLX5_L3_PROT_TYPE_IPV6);
2422                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2423                          MLX5_L4_PROT_TYPE_TCP);
2424                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2425                          MLX5_HASH_IP_L4PORTS);
2426                 break;
2427
2428         case MLX5E_TT_IPV4_UDP:
2429                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2430                          MLX5_L3_PROT_TYPE_IPV4);
2431                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2432                          MLX5_L4_PROT_TYPE_UDP);
2433                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2434                          MLX5_HASH_IP_L4PORTS);
2435                 break;
2436
2437         case MLX5E_TT_IPV6_UDP:
2438                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2439                          MLX5_L3_PROT_TYPE_IPV6);
2440                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2441                          MLX5_L4_PROT_TYPE_UDP);
2442                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443                          MLX5_HASH_IP_L4PORTS);
2444                 break;
2445
2446         case MLX5E_TT_IPV4_IPSEC_AH:
2447                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448                          MLX5_L3_PROT_TYPE_IPV4);
2449                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450                          MLX5_HASH_IP_IPSEC_SPI);
2451                 break;
2452
2453         case MLX5E_TT_IPV6_IPSEC_AH:
2454                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2455                          MLX5_L3_PROT_TYPE_IPV6);
2456                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2457                          MLX5_HASH_IP_IPSEC_SPI);
2458                 break;
2459
2460         case MLX5E_TT_IPV4_IPSEC_ESP:
2461                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2462                          MLX5_L3_PROT_TYPE_IPV4);
2463                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2464                          MLX5_HASH_IP_IPSEC_SPI);
2465                 break;
2466
2467         case MLX5E_TT_IPV6_IPSEC_ESP:
2468                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2469                          MLX5_L3_PROT_TYPE_IPV6);
2470                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2471                          MLX5_HASH_IP_IPSEC_SPI);
2472                 break;
2473
2474         case MLX5E_TT_IPV4:
2475                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2476                          MLX5_L3_PROT_TYPE_IPV4);
2477                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2478                          MLX5_HASH_IP);
2479                 break;
2480
2481         case MLX5E_TT_IPV6:
2482                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2483                          MLX5_L3_PROT_TYPE_IPV6);
2484                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2485                          MLX5_HASH_IP);
2486                 break;
2487         default:
2488                 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2489         }
2490 }
2491
2492 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2493 {
2494         struct mlx5_core_dev *mdev = priv->mdev;
2495
2496         void *in;
2497         void *tirc;
2498         int inlen;
2499         int err;
2500         int tt;
2501         int ix;
2502
2503         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2504         in = kvzalloc(inlen, GFP_KERNEL);
2505         if (!in)
2506                 return -ENOMEM;
2507
2508         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2509         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2510
2511         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2512
2513         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2514                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2515                                            inlen);
2516                 if (err)
2517                         goto free_in;
2518         }
2519
2520         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2521                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2522                                            in, inlen);
2523                 if (err)
2524                         goto free_in;
2525         }
2526
2527 free_in:
2528         kvfree(in);
2529
2530         return err;
2531 }
2532
2533 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2534                                             enum mlx5e_traffic_types tt,
2535                                             u32 *tirc)
2536 {
2537         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2538
2539         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2540
2541         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2542         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2543         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2544
2545         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2546 }
2547
2548 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2549                          struct mlx5e_params *params, u16 mtu)
2550 {
2551         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2552         int err;
2553
2554         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2555         if (err)
2556                 return err;
2557
2558         /* Update vport context MTU */
2559         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2560         return 0;
2561 }
2562
2563 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2564                             struct mlx5e_params *params, u16 *mtu)
2565 {
2566         u16 hw_mtu = 0;
2567         int err;
2568
2569         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2570         if (err || !hw_mtu) /* fallback to port oper mtu */
2571                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2572
2573         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2574 }
2575
2576 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2577 {
2578         struct mlx5e_params *params = &priv->channels.params;
2579         struct net_device *netdev = priv->netdev;
2580         struct mlx5_core_dev *mdev = priv->mdev;
2581         u16 mtu;
2582         int err;
2583
2584         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2585         if (err)
2586                 return err;
2587
2588         mlx5e_query_mtu(mdev, params, &mtu);
2589         if (mtu != params->sw_mtu)
2590                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2591                             __func__, mtu, params->sw_mtu);
2592
2593         params->sw_mtu = mtu;
2594         return 0;
2595 }
2596
2597 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2598 {
2599         struct mlx5e_priv *priv = netdev_priv(netdev);
2600         int nch = priv->channels.params.num_channels;
2601         int ntc = priv->channels.params.num_tc;
2602         int tc;
2603
2604         netdev_reset_tc(netdev);
2605
2606         if (ntc == 1)
2607                 return;
2608
2609         netdev_set_num_tc(netdev, ntc);
2610
2611         /* Map netdev TCs to offset 0
2612          * We have our own UP to TXQ mapping for QoS
2613          */
2614         for (tc = 0; tc < ntc; tc++)
2615                 netdev_set_tc_queue(netdev, tc, nch, 0);
2616 }
2617
2618 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2619 {
2620         struct mlx5e_channel *c;
2621         struct mlx5e_txqsq *sq;
2622         int i, tc;
2623
2624         for (i = 0; i < priv->channels.num; i++)
2625                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2626                         priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2627
2628         for (i = 0; i < priv->channels.num; i++) {
2629                 c = priv->channels.c[i];
2630                 for (tc = 0; tc < c->num_tc; tc++) {
2631                         sq = &c->sq[tc];
2632                         priv->txq2sq[sq->txq_ix] = sq;
2633                 }
2634         }
2635 }
2636
2637 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2638 {
2639         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2640         struct net_device *netdev = priv->netdev;
2641
2642         mlx5e_netdev_set_tcs(netdev);
2643         netif_set_real_num_tx_queues(netdev, num_txqs);
2644         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2645
2646         mlx5e_build_channels_tx_maps(priv);
2647         mlx5e_activate_channels(&priv->channels);
2648         netif_tx_start_all_queues(priv->netdev);
2649
2650         if (MLX5_VPORT_MANAGER(priv->mdev))
2651                 mlx5e_add_sqs_fwd_rules(priv);
2652
2653         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2654         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2655 }
2656
2657 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2658 {
2659         mlx5e_redirect_rqts_to_drop(priv);
2660
2661         if (MLX5_VPORT_MANAGER(priv->mdev))
2662                 mlx5e_remove_sqs_fwd_rules(priv);
2663
2664         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2665          * polling for inactive tx queues.
2666          */
2667         netif_tx_stop_all_queues(priv->netdev);
2668         netif_tx_disable(priv->netdev);
2669         mlx5e_deactivate_channels(&priv->channels);
2670 }
2671
2672 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2673                                 struct mlx5e_channels *new_chs,
2674                                 mlx5e_fp_hw_modify hw_modify)
2675 {
2676         struct net_device *netdev = priv->netdev;
2677         int new_num_txqs;
2678         int carrier_ok;
2679         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2680
2681         carrier_ok = netif_carrier_ok(netdev);
2682         netif_carrier_off(netdev);
2683
2684         if (new_num_txqs < netdev->real_num_tx_queues)
2685                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2686
2687         mlx5e_deactivate_priv_channels(priv);
2688         mlx5e_close_channels(&priv->channels);
2689
2690         priv->channels = *new_chs;
2691
2692         /* New channels are ready to roll, modify HW settings if needed */
2693         if (hw_modify)
2694                 hw_modify(priv);
2695
2696         mlx5e_refresh_tirs(priv, false);
2697         mlx5e_activate_priv_channels(priv);
2698
2699         /* return carrier back if needed */
2700         if (carrier_ok)
2701                 netif_carrier_on(netdev);
2702 }
2703
2704 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2705 {
2706         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2707         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2708 }
2709
2710 int mlx5e_open_locked(struct net_device *netdev)
2711 {
2712         struct mlx5e_priv *priv = netdev_priv(netdev);
2713         int err;
2714
2715         set_bit(MLX5E_STATE_OPENED, &priv->state);
2716
2717         err = mlx5e_open_channels(priv, &priv->channels);
2718         if (err)
2719                 goto err_clear_state_opened_flag;
2720
2721         mlx5e_refresh_tirs(priv, false);
2722         mlx5e_activate_priv_channels(priv);
2723         if (priv->profile->update_carrier)
2724                 priv->profile->update_carrier(priv);
2725
2726         if (priv->profile->update_stats)
2727                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2728
2729         return 0;
2730
2731 err_clear_state_opened_flag:
2732         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2733         return err;
2734 }
2735
2736 int mlx5e_open(struct net_device *netdev)
2737 {
2738         struct mlx5e_priv *priv = netdev_priv(netdev);
2739         int err;
2740
2741         mutex_lock(&priv->state_lock);
2742         err = mlx5e_open_locked(netdev);
2743         if (!err)
2744                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2745         mutex_unlock(&priv->state_lock);
2746
2747         if (mlx5e_vxlan_allowed(priv->mdev))
2748                 udp_tunnel_get_rx_info(netdev);
2749
2750         return err;
2751 }
2752
2753 int mlx5e_close_locked(struct net_device *netdev)
2754 {
2755         struct mlx5e_priv *priv = netdev_priv(netdev);
2756
2757         /* May already be CLOSED in case a previous configuration operation
2758          * (e.g RX/TX queue size change) that involves close&open failed.
2759          */
2760         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2761                 return 0;
2762
2763         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2764
2765         netif_carrier_off(priv->netdev);
2766         mlx5e_deactivate_priv_channels(priv);
2767         mlx5e_close_channels(&priv->channels);
2768
2769         return 0;
2770 }
2771
2772 int mlx5e_close(struct net_device *netdev)
2773 {
2774         struct mlx5e_priv *priv = netdev_priv(netdev);
2775         int err;
2776
2777         if (!netif_device_present(netdev))
2778                 return -ENODEV;
2779
2780         mutex_lock(&priv->state_lock);
2781         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2782         err = mlx5e_close_locked(netdev);
2783         mutex_unlock(&priv->state_lock);
2784
2785         return err;
2786 }
2787
2788 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2789                                struct mlx5e_rq *rq,
2790                                struct mlx5e_rq_param *param)
2791 {
2792         void *rqc = param->rqc;
2793         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2794         int err;
2795
2796         param->wq.db_numa_node = param->wq.buf_numa_node;
2797
2798         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2799                                 &rq->wq_ctrl);
2800         if (err)
2801                 return err;
2802
2803         /* Mark as unused given "Drop-RQ" packets never reach XDP */
2804         xdp_rxq_info_unused(&rq->xdp_rxq);
2805
2806         rq->mdev = mdev;
2807
2808         return 0;
2809 }
2810
2811 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2812                                struct mlx5e_cq *cq,
2813                                struct mlx5e_cq_param *param)
2814 {
2815         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2816         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
2817
2818         return mlx5e_alloc_cq_common(mdev, param, cq);
2819 }
2820
2821 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2822                               struct mlx5e_rq *drop_rq)
2823 {
2824         struct mlx5_core_dev *mdev = priv->mdev;
2825         struct mlx5e_cq_param cq_param = {};
2826         struct mlx5e_rq_param rq_param = {};
2827         struct mlx5e_cq *cq = &drop_rq->cq;
2828         int err;
2829
2830         mlx5e_build_drop_rq_param(priv, &rq_param);
2831
2832         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2833         if (err)
2834                 return err;
2835
2836         err = mlx5e_create_cq(cq, &cq_param);
2837         if (err)
2838                 goto err_free_cq;
2839
2840         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2841         if (err)
2842                 goto err_destroy_cq;
2843
2844         err = mlx5e_create_rq(drop_rq, &rq_param);
2845         if (err)
2846                 goto err_free_rq;
2847
2848         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2849         if (err)
2850                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2851
2852         return 0;
2853
2854 err_free_rq:
2855         mlx5e_free_rq(drop_rq);
2856
2857 err_destroy_cq:
2858         mlx5e_destroy_cq(cq);
2859
2860 err_free_cq:
2861         mlx5e_free_cq(cq);
2862
2863         return err;
2864 }
2865
2866 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2867 {
2868         mlx5e_destroy_rq(drop_rq);
2869         mlx5e_free_rq(drop_rq);
2870         mlx5e_destroy_cq(&drop_rq->cq);
2871         mlx5e_free_cq(&drop_rq->cq);
2872 }
2873
2874 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2875                      u32 underlay_qpn, u32 *tisn)
2876 {
2877         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2878         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2879
2880         MLX5_SET(tisc, tisc, prio, tc << 1);
2881         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2882         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2883
2884         if (mlx5_lag_is_lacp_owner(mdev))
2885                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2886
2887         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2888 }
2889
2890 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2891 {
2892         mlx5_core_destroy_tis(mdev, tisn);
2893 }
2894
2895 int mlx5e_create_tises(struct mlx5e_priv *priv)
2896 {
2897         int err;
2898         int tc;
2899
2900         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2901                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2902                 if (err)
2903                         goto err_close_tises;
2904         }
2905
2906         return 0;
2907
2908 err_close_tises:
2909         for (tc--; tc >= 0; tc--)
2910                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2911
2912         return err;
2913 }
2914
2915 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2916 {
2917         int tc;
2918
2919         for (tc = 0; tc < priv->profile->max_tc; tc++)
2920                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2921 }
2922
2923 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2924                                       enum mlx5e_traffic_types tt,
2925                                       u32 *tirc)
2926 {
2927         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2928
2929         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2930
2931         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2932         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2933         mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2934 }
2935
2936 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2937 {
2938         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2939
2940         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2941
2942         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2943         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2944         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2945 }
2946
2947 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2948 {
2949         struct mlx5e_tir *tir;
2950         void *tirc;
2951         int inlen;
2952         int i = 0;
2953         int err;
2954         u32 *in;
2955         int tt;
2956
2957         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2958         in = kvzalloc(inlen, GFP_KERNEL);
2959         if (!in)
2960                 return -ENOMEM;
2961
2962         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2963                 memset(in, 0, inlen);
2964                 tir = &priv->indir_tir[tt];
2965                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2966                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2967                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2968                 if (err) {
2969                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2970                         goto err_destroy_inner_tirs;
2971                 }
2972         }
2973
2974         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2975                 goto out;
2976
2977         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2978                 memset(in, 0, inlen);
2979                 tir = &priv->inner_indir_tir[i];
2980                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2981                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2982                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2983                 if (err) {
2984                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2985                         goto err_destroy_inner_tirs;
2986                 }
2987         }
2988
2989 out:
2990         kvfree(in);
2991
2992         return 0;
2993
2994 err_destroy_inner_tirs:
2995         for (i--; i >= 0; i--)
2996                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2997
2998         for (tt--; tt >= 0; tt--)
2999                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3000
3001         kvfree(in);
3002
3003         return err;
3004 }
3005
3006 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3007 {
3008         int nch = priv->profile->max_nch(priv->mdev);
3009         struct mlx5e_tir *tir;
3010         void *tirc;
3011         int inlen;
3012         int err;
3013         u32 *in;
3014         int ix;
3015
3016         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3017         in = kvzalloc(inlen, GFP_KERNEL);
3018         if (!in)
3019                 return -ENOMEM;
3020
3021         for (ix = 0; ix < nch; ix++) {
3022                 memset(in, 0, inlen);
3023                 tir = &priv->direct_tir[ix];
3024                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3025                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3026                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3027                 if (err)
3028                         goto err_destroy_ch_tirs;
3029         }
3030
3031         kvfree(in);
3032
3033         return 0;
3034
3035 err_destroy_ch_tirs:
3036         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3037         for (ix--; ix >= 0; ix--)
3038                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3039
3040         kvfree(in);
3041
3042         return err;
3043 }
3044
3045 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3046 {
3047         int i;
3048
3049         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3050                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3051
3052         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3053                 return;
3054
3055         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3056                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3057 }
3058
3059 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3060 {
3061         int nch = priv->profile->max_nch(priv->mdev);
3062         int i;
3063
3064         for (i = 0; i < nch; i++)
3065                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3066 }
3067
3068 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3069 {
3070         int err = 0;
3071         int i;
3072
3073         for (i = 0; i < chs->num; i++) {
3074                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3075                 if (err)
3076                         return err;
3077         }
3078
3079         return 0;
3080 }
3081
3082 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3083 {
3084         int err = 0;
3085         int i;
3086
3087         for (i = 0; i < chs->num; i++) {
3088                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3089                 if (err)
3090                         return err;
3091         }
3092
3093         return 0;
3094 }
3095
3096 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3097                                  struct tc_mqprio_qopt *mqprio)
3098 {
3099         struct mlx5e_priv *priv = netdev_priv(netdev);
3100         struct mlx5e_channels new_channels = {};
3101         u8 tc = mqprio->num_tc;
3102         int err = 0;
3103
3104         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3105
3106         if (tc && tc != MLX5E_MAX_NUM_TC)
3107                 return -EINVAL;
3108
3109         mutex_lock(&priv->state_lock);
3110
3111         new_channels.params = priv->channels.params;
3112         new_channels.params.num_tc = tc ? tc : 1;
3113
3114         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3115                 priv->channels.params = new_channels.params;
3116                 goto out;
3117         }
3118
3119         err = mlx5e_open_channels(priv, &new_channels);
3120         if (err)
3121                 goto out;
3122
3123         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3124 out:
3125         mutex_unlock(&priv->state_lock);
3126         return err;
3127 }
3128
3129 #ifdef CONFIG_MLX5_ESWITCH
3130 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3131                                      struct tc_cls_flower_offload *cls_flower)
3132 {
3133         switch (cls_flower->command) {
3134         case TC_CLSFLOWER_REPLACE:
3135                 return mlx5e_configure_flower(priv, cls_flower);
3136         case TC_CLSFLOWER_DESTROY:
3137                 return mlx5e_delete_flower(priv, cls_flower);
3138         case TC_CLSFLOWER_STATS:
3139                 return mlx5e_stats_flower(priv, cls_flower);
3140         default:
3141                 return -EOPNOTSUPP;
3142         }
3143 }
3144
3145 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3146                             void *cb_priv)
3147 {
3148         struct mlx5e_priv *priv = cb_priv;
3149
3150         if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3151                 return -EOPNOTSUPP;
3152
3153         switch (type) {
3154         case TC_SETUP_CLSFLOWER:
3155                 return mlx5e_setup_tc_cls_flower(priv, type_data);
3156         default:
3157                 return -EOPNOTSUPP;
3158         }
3159 }
3160
3161 static int mlx5e_setup_tc_block(struct net_device *dev,
3162                                 struct tc_block_offload *f)
3163 {
3164         struct mlx5e_priv *priv = netdev_priv(dev);
3165
3166         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3167                 return -EOPNOTSUPP;
3168
3169         switch (f->command) {
3170         case TC_BLOCK_BIND:
3171                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3172                                              priv, priv);
3173         case TC_BLOCK_UNBIND:
3174                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3175                                         priv);
3176                 return 0;
3177         default:
3178                 return -EOPNOTSUPP;
3179         }
3180 }
3181 #endif
3182
3183 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3184                           void *type_data)
3185 {
3186         switch (type) {
3187 #ifdef CONFIG_MLX5_ESWITCH
3188         case TC_SETUP_BLOCK:
3189                 return mlx5e_setup_tc_block(dev, type_data);
3190 #endif
3191         case TC_SETUP_QDISC_MQPRIO:
3192                 return mlx5e_setup_tc_mqprio(dev, type_data);
3193         default:
3194                 return -EOPNOTSUPP;
3195         }
3196 }
3197
3198 static void
3199 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3200 {
3201         struct mlx5e_priv *priv = netdev_priv(dev);
3202         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3203         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3204         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3205
3206         if (mlx5e_is_uplink_rep(priv)) {
3207                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3208                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3209                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3210                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3211         } else {
3212                 stats->rx_packets = sstats->rx_packets;
3213                 stats->rx_bytes   = sstats->rx_bytes;
3214                 stats->tx_packets = sstats->tx_packets;
3215                 stats->tx_bytes   = sstats->tx_bytes;
3216                 stats->tx_dropped = sstats->tx_queue_dropped;
3217         }
3218
3219         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3220
3221         stats->rx_length_errors =
3222                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3223                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3224                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3225         stats->rx_crc_errors =
3226                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3227         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3228         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3229         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3230                            stats->rx_frame_errors;
3231         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3232
3233         /* vport multicast also counts packets that are dropped due to steering
3234          * or rx out of buffer
3235          */
3236         stats->multicast =
3237                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3238 }
3239
3240 static void mlx5e_set_rx_mode(struct net_device *dev)
3241 {
3242         struct mlx5e_priv *priv = netdev_priv(dev);
3243
3244         queue_work(priv->wq, &priv->set_rx_mode_work);
3245 }
3246
3247 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3248 {
3249         struct mlx5e_priv *priv = netdev_priv(netdev);
3250         struct sockaddr *saddr = addr;
3251
3252         if (!is_valid_ether_addr(saddr->sa_data))
3253                 return -EADDRNOTAVAIL;
3254
3255         netif_addr_lock_bh(netdev);
3256         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3257         netif_addr_unlock_bh(netdev);
3258
3259         queue_work(priv->wq, &priv->set_rx_mode_work);
3260
3261         return 0;
3262 }
3263
3264 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3265         do {                                            \
3266                 if (enable)                             \
3267                         *features |= feature;           \
3268                 else                                    \
3269                         *features &= ~feature;          \
3270         } while (0)
3271
3272 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3273
3274 static int set_feature_lro(struct net_device *netdev, bool enable)
3275 {
3276         struct mlx5e_priv *priv = netdev_priv(netdev);
3277         struct mlx5_core_dev *mdev = priv->mdev;
3278         struct mlx5e_channels new_channels = {};
3279         struct mlx5e_params *old_params;
3280         int err = 0;
3281         bool reset;
3282
3283         mutex_lock(&priv->state_lock);
3284
3285         old_params = &priv->channels.params;
3286         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3287
3288         new_channels.params = *old_params;
3289         new_channels.params.lro_en = enable;
3290
3291         if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3292                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3293                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3294                         reset = false;
3295         }
3296
3297         if (!reset) {
3298                 *old_params = new_channels.params;
3299                 err = mlx5e_modify_tirs_lro(priv);
3300                 goto out;
3301         }
3302
3303         err = mlx5e_open_channels(priv, &new_channels);
3304         if (err)
3305                 goto out;
3306
3307         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3308 out:
3309         mutex_unlock(&priv->state_lock);
3310         return err;
3311 }
3312
3313 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3314 {
3315         struct mlx5e_priv *priv = netdev_priv(netdev);
3316
3317         if (enable)
3318                 mlx5e_enable_cvlan_filter(priv);
3319         else
3320                 mlx5e_disable_cvlan_filter(priv);
3321
3322         return 0;
3323 }
3324
3325 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3326 {
3327         struct mlx5e_priv *priv = netdev_priv(netdev);
3328
3329         if (!enable && mlx5e_tc_num_filters(priv)) {
3330                 netdev_err(netdev,
3331                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3332                 return -EINVAL;
3333         }
3334
3335         return 0;
3336 }
3337
3338 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3339 {
3340         struct mlx5e_priv *priv = netdev_priv(netdev);
3341         struct mlx5_core_dev *mdev = priv->mdev;
3342
3343         return mlx5_set_port_fcs(mdev, !enable);
3344 }
3345
3346 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3347 {
3348         struct mlx5e_priv *priv = netdev_priv(netdev);
3349         int err;
3350
3351         mutex_lock(&priv->state_lock);
3352
3353         priv->channels.params.scatter_fcs_en = enable;
3354         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3355         if (err)
3356                 priv->channels.params.scatter_fcs_en = !enable;
3357
3358         mutex_unlock(&priv->state_lock);
3359
3360         return err;
3361 }
3362
3363 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3364 {
3365         struct mlx5e_priv *priv = netdev_priv(netdev);
3366         int err = 0;
3367
3368         mutex_lock(&priv->state_lock);
3369
3370         priv->channels.params.vlan_strip_disable = !enable;
3371         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3372                 goto unlock;
3373
3374         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3375         if (err)
3376                 priv->channels.params.vlan_strip_disable = enable;
3377
3378 unlock:
3379         mutex_unlock(&priv->state_lock);
3380
3381         return err;
3382 }
3383
3384 #ifdef CONFIG_RFS_ACCEL
3385 static int set_feature_arfs(struct net_device *netdev, bool enable)
3386 {
3387         struct mlx5e_priv *priv = netdev_priv(netdev);
3388         int err;
3389
3390         if (enable)
3391                 err = mlx5e_arfs_enable(priv);
3392         else
3393                 err = mlx5e_arfs_disable(priv);
3394
3395         return err;
3396 }
3397 #endif
3398
3399 static int mlx5e_handle_feature(struct net_device *netdev,
3400                                 netdev_features_t *features,
3401                                 netdev_features_t wanted_features,
3402                                 netdev_features_t feature,
3403                                 mlx5e_feature_handler feature_handler)
3404 {
3405         netdev_features_t changes = wanted_features ^ netdev->features;
3406         bool enable = !!(wanted_features & feature);
3407         int err;
3408
3409         if (!(changes & feature))
3410                 return 0;
3411
3412         err = feature_handler(netdev, enable);
3413         if (err) {
3414                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3415                            enable ? "Enable" : "Disable", &feature, err);
3416                 return err;
3417         }
3418
3419         MLX5E_SET_FEATURE(features, feature, enable);
3420         return 0;
3421 }
3422
3423 static int mlx5e_set_features(struct net_device *netdev,
3424                               netdev_features_t features)
3425 {
3426         netdev_features_t oper_features = netdev->features;
3427         int err = 0;
3428
3429 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3430         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3431
3432         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3433         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3434                                     set_feature_cvlan_filter);
3435         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3436         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3437         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3438         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3439 #ifdef CONFIG_RFS_ACCEL
3440         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3441 #endif
3442
3443         if (err) {
3444                 netdev->features = oper_features;
3445                 return -EINVAL;
3446         }
3447
3448         return 0;
3449 }
3450
3451 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3452                                             netdev_features_t features)
3453 {
3454         struct mlx5e_priv *priv = netdev_priv(netdev);
3455
3456         mutex_lock(&priv->state_lock);
3457         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3458                 /* HW strips the outer C-tag header, this is a problem
3459                  * for S-tag traffic.
3460                  */
3461                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3462                 if (!priv->channels.params.vlan_strip_disable)
3463                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3464         }
3465         mutex_unlock(&priv->state_lock);
3466
3467         return features;
3468 }
3469
3470 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3471 {
3472         struct mlx5e_priv *priv = netdev_priv(netdev);
3473         struct mlx5e_channels new_channels = {};
3474         struct mlx5e_params *params;
3475         int err = 0;
3476         bool reset;
3477
3478         mutex_lock(&priv->state_lock);
3479
3480         params = &priv->channels.params;
3481
3482         reset = !params->lro_en;
3483         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3484
3485         new_channels.params = *params;
3486         new_channels.params.sw_mtu = new_mtu;
3487
3488         if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3489                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3490                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3491
3492                 reset = reset && (ppw_old != ppw_new);
3493         }
3494
3495         if (!reset) {
3496                 params->sw_mtu = new_mtu;
3497                 mlx5e_set_dev_port_mtu(priv);
3498                 netdev->mtu = params->sw_mtu;
3499                 goto out;
3500         }
3501
3502         err = mlx5e_open_channels(priv, &new_channels);
3503         if (err)
3504                 goto out;
3505
3506         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3507         netdev->mtu = new_channels.params.sw_mtu;
3508
3509 out:
3510         mutex_unlock(&priv->state_lock);
3511         return err;
3512 }
3513
3514 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3515 {
3516         struct hwtstamp_config config;
3517         int err;
3518
3519         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3520                 return -EOPNOTSUPP;
3521
3522         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3523                 return -EFAULT;
3524
3525         /* TX HW timestamp */
3526         switch (config.tx_type) {
3527         case HWTSTAMP_TX_OFF:
3528         case HWTSTAMP_TX_ON:
3529                 break;
3530         default:
3531                 return -ERANGE;
3532         }
3533
3534         mutex_lock(&priv->state_lock);
3535         /* RX HW timestamp */
3536         switch (config.rx_filter) {
3537         case HWTSTAMP_FILTER_NONE:
3538                 /* Reset CQE compression to Admin default */
3539                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3540                 break;
3541         case HWTSTAMP_FILTER_ALL:
3542         case HWTSTAMP_FILTER_SOME:
3543         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3544         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3545         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3546         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3547         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3548         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3549         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3550         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3551         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3552         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3553         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3554         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3555         case HWTSTAMP_FILTER_NTP_ALL:
3556                 /* Disable CQE compression */
3557                 netdev_warn(priv->netdev, "Disabling cqe compression");
3558                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3559                 if (err) {
3560                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3561                         mutex_unlock(&priv->state_lock);
3562                         return err;
3563                 }
3564                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3565                 break;
3566         default:
3567                 mutex_unlock(&priv->state_lock);
3568                 return -ERANGE;
3569         }
3570
3571         memcpy(&priv->tstamp, &config, sizeof(config));
3572         mutex_unlock(&priv->state_lock);
3573
3574         return copy_to_user(ifr->ifr_data, &config,
3575                             sizeof(config)) ? -EFAULT : 0;
3576 }
3577
3578 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3579 {
3580         struct hwtstamp_config *cfg = &priv->tstamp;
3581
3582         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3583                 return -EOPNOTSUPP;
3584
3585         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3586 }
3587
3588 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3589 {
3590         struct mlx5e_priv *priv = netdev_priv(dev);
3591
3592         switch (cmd) {
3593         case SIOCSHWTSTAMP:
3594                 return mlx5e_hwstamp_set(priv, ifr);
3595         case SIOCGHWTSTAMP:
3596                 return mlx5e_hwstamp_get(priv, ifr);
3597         default:
3598                 return -EOPNOTSUPP;
3599         }
3600 }
3601
3602 #ifdef CONFIG_MLX5_ESWITCH
3603 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3604 {
3605         struct mlx5e_priv *priv = netdev_priv(dev);
3606         struct mlx5_core_dev *mdev = priv->mdev;
3607
3608         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3609 }
3610
3611 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3612                              __be16 vlan_proto)
3613 {
3614         struct mlx5e_priv *priv = netdev_priv(dev);
3615         struct mlx5_core_dev *mdev = priv->mdev;
3616
3617         if (vlan_proto != htons(ETH_P_8021Q))
3618                 return -EPROTONOSUPPORT;
3619
3620         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3621                                            vlan, qos);
3622 }
3623
3624 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3625 {
3626         struct mlx5e_priv *priv = netdev_priv(dev);
3627         struct mlx5_core_dev *mdev = priv->mdev;
3628
3629         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3630 }
3631
3632 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3633 {
3634         struct mlx5e_priv *priv = netdev_priv(dev);
3635         struct mlx5_core_dev *mdev = priv->mdev;
3636
3637         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3638 }
3639
3640 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3641                              int max_tx_rate)
3642 {
3643         struct mlx5e_priv *priv = netdev_priv(dev);
3644         struct mlx5_core_dev *mdev = priv->mdev;
3645
3646         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3647                                            max_tx_rate, min_tx_rate);
3648 }
3649
3650 static int mlx5_vport_link2ifla(u8 esw_link)
3651 {
3652         switch (esw_link) {
3653         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3654                 return IFLA_VF_LINK_STATE_DISABLE;
3655         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3656                 return IFLA_VF_LINK_STATE_ENABLE;
3657         }
3658         return IFLA_VF_LINK_STATE_AUTO;
3659 }
3660
3661 static int mlx5_ifla_link2vport(u8 ifla_link)
3662 {
3663         switch (ifla_link) {
3664         case IFLA_VF_LINK_STATE_DISABLE:
3665                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3666         case IFLA_VF_LINK_STATE_ENABLE:
3667                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3668         }
3669         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3670 }
3671
3672 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3673                                    int link_state)
3674 {
3675         struct mlx5e_priv *priv = netdev_priv(dev);
3676         struct mlx5_core_dev *mdev = priv->mdev;
3677
3678         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3679                                             mlx5_ifla_link2vport(link_state));
3680 }
3681
3682 static int mlx5e_get_vf_config(struct net_device *dev,
3683                                int vf, struct ifla_vf_info *ivi)
3684 {
3685         struct mlx5e_priv *priv = netdev_priv(dev);
3686         struct mlx5_core_dev *mdev = priv->mdev;
3687         int err;
3688
3689         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3690         if (err)
3691                 return err;
3692         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3693         return 0;
3694 }
3695
3696 static int mlx5e_get_vf_stats(struct net_device *dev,
3697                               int vf, struct ifla_vf_stats *vf_stats)
3698 {
3699         struct mlx5e_priv *priv = netdev_priv(dev);
3700         struct mlx5_core_dev *mdev = priv->mdev;
3701
3702         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3703                                             vf_stats);
3704 }
3705 #endif
3706
3707 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3708                                  struct udp_tunnel_info *ti)
3709 {
3710         struct mlx5e_priv *priv = netdev_priv(netdev);
3711
3712         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3713                 return;
3714
3715         if (!mlx5e_vxlan_allowed(priv->mdev))
3716                 return;
3717
3718         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3719 }
3720
3721 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3722                                  struct udp_tunnel_info *ti)
3723 {
3724         struct mlx5e_priv *priv = netdev_priv(netdev);
3725
3726         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3727                 return;
3728
3729         if (!mlx5e_vxlan_allowed(priv->mdev))
3730                 return;
3731
3732         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3733 }
3734
3735 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3736                                                      struct sk_buff *skb,
3737                                                      netdev_features_t features)
3738 {
3739         unsigned int offset = 0;
3740         struct udphdr *udph;
3741         u8 proto;
3742         u16 port;
3743
3744         switch (vlan_get_protocol(skb)) {
3745         case htons(ETH_P_IP):
3746                 proto = ip_hdr(skb)->protocol;
3747                 break;
3748         case htons(ETH_P_IPV6):
3749                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3750                 break;
3751         default:
3752                 goto out;
3753         }
3754
3755         switch (proto) {
3756         case IPPROTO_GRE:
3757                 return features;
3758         case IPPROTO_UDP:
3759                 udph = udp_hdr(skb);
3760                 port = be16_to_cpu(udph->dest);
3761
3762                 /* Verify if UDP port is being offloaded by HW */
3763                 if (mlx5e_vxlan_lookup_port(priv, port))
3764                         return features;
3765         }
3766
3767 out:
3768         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3769         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3770 }
3771
3772 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3773                                               struct net_device *netdev,
3774                                               netdev_features_t features)
3775 {
3776         struct mlx5e_priv *priv = netdev_priv(netdev);
3777
3778         features = vlan_features_check(skb, features);
3779         features = vxlan_features_check(skb, features);
3780
3781 #ifdef CONFIG_MLX5_EN_IPSEC
3782         if (mlx5e_ipsec_feature_check(skb, netdev, features))
3783                 return features;
3784 #endif
3785
3786         /* Validate if the tunneled packet is being offloaded by HW */
3787         if (skb->encapsulation &&
3788             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3789                 return mlx5e_tunnel_features_check(priv, skb, features);
3790
3791         return features;
3792 }
3793
3794 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3795                                         struct mlx5e_txqsq *sq)
3796 {
3797         struct mlx5_eq *eq = sq->cq.mcq.eq;
3798         u32 eqe_count;
3799
3800         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3801                    eq->eqn, eq->cons_index, eq->irqn);
3802
3803         eqe_count = mlx5_eq_poll_irq_disabled(eq);
3804         if (!eqe_count)
3805                 return false;
3806
3807         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
3808         sq->channel->stats.eq_rearm++;
3809         return true;
3810 }
3811
3812 static void mlx5e_tx_timeout_work(struct work_struct *work)
3813 {
3814         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3815                                                tx_timeout_work);
3816         struct net_device *dev = priv->netdev;
3817         bool reopen_channels = false;
3818         int i, err;
3819
3820         rtnl_lock();
3821         mutex_lock(&priv->state_lock);
3822
3823         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3824                 goto unlock;
3825
3826         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3827                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
3828                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3829
3830                 if (!netif_xmit_stopped(dev_queue))
3831                         continue;
3832
3833                 netdev_err(dev,
3834                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3835                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3836                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
3837
3838                 /* If we recover a lost interrupt, most likely TX timeout will
3839                  * be resolved, skip reopening channels
3840                  */
3841                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3842                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3843                         reopen_channels = true;
3844                 }
3845         }
3846
3847         if (!reopen_channels)
3848                 goto unlock;
3849
3850         mlx5e_close_locked(dev);
3851         err = mlx5e_open_locked(dev);
3852         if (err)
3853                 netdev_err(priv->netdev,
3854                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
3855                            err);
3856
3857 unlock:
3858         mutex_unlock(&priv->state_lock);
3859         rtnl_unlock();
3860 }
3861
3862 static void mlx5e_tx_timeout(struct net_device *dev)
3863 {
3864         struct mlx5e_priv *priv = netdev_priv(dev);
3865
3866         netdev_err(dev, "TX timeout detected\n");
3867         queue_work(priv->wq, &priv->tx_timeout_work);
3868 }
3869
3870 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3871 {
3872         struct mlx5e_priv *priv = netdev_priv(netdev);
3873         struct bpf_prog *old_prog;
3874         int err = 0;
3875         bool reset, was_opened;
3876         int i;
3877
3878         mutex_lock(&priv->state_lock);
3879
3880         if ((netdev->features & NETIF_F_LRO) && prog) {
3881                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3882                 err = -EINVAL;
3883                 goto unlock;
3884         }
3885
3886         if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3887                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3888                 err = -EINVAL;
3889                 goto unlock;
3890         }
3891
3892         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3893         /* no need for full reset when exchanging programs */
3894         reset = (!priv->channels.params.xdp_prog || !prog);
3895
3896         if (was_opened && reset)
3897                 mlx5e_close_locked(netdev);
3898         if (was_opened && !reset) {
3899                 /* num_channels is invariant here, so we can take the
3900                  * batched reference right upfront.
3901                  */
3902                 prog = bpf_prog_add(prog, priv->channels.num);
3903                 if (IS_ERR(prog)) {
3904                         err = PTR_ERR(prog);
3905                         goto unlock;
3906                 }
3907         }
3908
3909         /* exchange programs, extra prog reference we got from caller
3910          * as long as we don't fail from this point onwards.
3911          */
3912         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3913         if (old_prog)
3914                 bpf_prog_put(old_prog);
3915
3916         if (reset) /* change RQ type according to priv->xdp_prog */
3917                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
3918
3919         if (was_opened && reset)
3920                 mlx5e_open_locked(netdev);
3921
3922         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3923                 goto unlock;
3924
3925         /* exchanging programs w/o reset, we update ref counts on behalf
3926          * of the channels RQs here.
3927          */
3928         for (i = 0; i < priv->channels.num; i++) {
3929                 struct mlx5e_channel *c = priv->channels.c[i];
3930
3931                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3932                 napi_synchronize(&c->napi);
3933                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3934
3935                 old_prog = xchg(&c->rq.xdp_prog, prog);
3936
3937                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3938                 /* napi_schedule in case we have missed anything */
3939                 napi_schedule(&c->napi);
3940
3941                 if (old_prog)
3942                         bpf_prog_put(old_prog);
3943         }
3944
3945 unlock:
3946         mutex_unlock(&priv->state_lock);
3947         return err;
3948 }
3949
3950 static u32 mlx5e_xdp_query(struct net_device *dev)
3951 {
3952         struct mlx5e_priv *priv = netdev_priv(dev);
3953         const struct bpf_prog *xdp_prog;
3954         u32 prog_id = 0;
3955
3956         mutex_lock(&priv->state_lock);
3957         xdp_prog = priv->channels.params.xdp_prog;
3958         if (xdp_prog)
3959                 prog_id = xdp_prog->aux->id;
3960         mutex_unlock(&priv->state_lock);
3961
3962         return prog_id;
3963 }
3964
3965 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3966 {
3967         switch (xdp->command) {
3968         case XDP_SETUP_PROG:
3969                 return mlx5e_xdp_set(dev, xdp->prog);
3970         case XDP_QUERY_PROG:
3971                 xdp->prog_id = mlx5e_xdp_query(dev);
3972                 xdp->prog_attached = !!xdp->prog_id;
3973                 return 0;
3974         default:
3975                 return -EINVAL;
3976         }
3977 }
3978
3979 #ifdef CONFIG_NET_POLL_CONTROLLER
3980 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3981  * reenabling interrupts.
3982  */
3983 static void mlx5e_netpoll(struct net_device *dev)
3984 {
3985         struct mlx5e_priv *priv = netdev_priv(dev);
3986         struct mlx5e_channels *chs = &priv->channels;
3987
3988         int i;
3989
3990         for (i = 0; i < chs->num; i++)
3991                 napi_schedule(&chs->c[i]->napi);
3992 }
3993 #endif
3994
3995 static const struct net_device_ops mlx5e_netdev_ops = {
3996         .ndo_open                = mlx5e_open,
3997         .ndo_stop                = mlx5e_close,
3998         .ndo_start_xmit          = mlx5e_xmit,
3999         .ndo_setup_tc            = mlx5e_setup_tc,
4000         .ndo_select_queue        = mlx5e_select_queue,
4001         .ndo_get_stats64         = mlx5e_get_stats,
4002         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4003         .ndo_set_mac_address     = mlx5e_set_mac,
4004         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4005         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4006         .ndo_set_features        = mlx5e_set_features,
4007         .ndo_fix_features        = mlx5e_fix_features,
4008         .ndo_change_mtu          = mlx5e_change_mtu,
4009         .ndo_do_ioctl            = mlx5e_ioctl,
4010         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4011         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4012         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4013         .ndo_features_check      = mlx5e_features_check,
4014 #ifdef CONFIG_RFS_ACCEL
4015         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4016 #endif
4017         .ndo_tx_timeout          = mlx5e_tx_timeout,
4018         .ndo_bpf                 = mlx5e_xdp,
4019 #ifdef CONFIG_NET_POLL_CONTROLLER
4020         .ndo_poll_controller     = mlx5e_netpoll,
4021 #endif
4022 #ifdef CONFIG_MLX5_ESWITCH
4023         /* SRIOV E-Switch NDOs */
4024         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4025         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4026         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4027         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4028         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4029         .ndo_get_vf_config       = mlx5e_get_vf_config,
4030         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4031         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4032         .ndo_has_offload_stats   = mlx5e_has_offload_stats,
4033         .ndo_get_offload_stats   = mlx5e_get_offload_stats,
4034 #endif
4035 };
4036
4037 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4038 {
4039         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4040                 return -EOPNOTSUPP;
4041         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4042             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4043             !MLX5_CAP_ETH(mdev, csum_cap) ||
4044             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4045             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4046             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4047             MLX5_CAP_FLOWTABLE(mdev,
4048                                flow_table_properties_nic_receive.max_ft_level)
4049                                < 3) {
4050                 mlx5_core_warn(mdev,
4051                                "Not creating net device, some required device capabilities are missing\n");
4052                 return -EOPNOTSUPP;
4053         }
4054         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4055                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4056         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4057                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4058
4059         return 0;
4060 }
4061
4062 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4063                                    int num_channels)
4064 {
4065         int i;
4066
4067         for (i = 0; i < len; i++)
4068                 indirection_rqt[i] = i % num_channels;
4069 }
4070
4071 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4072 {
4073         u32 link_speed = 0;
4074         u32 pci_bw = 0;
4075
4076         mlx5e_get_max_linkspeed(mdev, &link_speed);
4077         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4078         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4079                            link_speed, pci_bw);
4080
4081 #define MLX5E_SLOW_PCI_RATIO (2)
4082
4083         return link_speed && pci_bw &&
4084                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4085 }
4086
4087 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4088 {
4089         params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4090
4091         params->tx_cq_moderation.pkts =
4092                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4093         params->tx_cq_moderation.usec =
4094                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4095
4096         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4097                 params->tx_cq_moderation.usec =
4098                         MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4099
4100         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4101                         params->tx_cq_moderation.cq_period_mode ==
4102                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4103 }
4104
4105 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4106 {
4107         params->rx_cq_moderation.cq_period_mode = cq_period_mode;
4108
4109         params->rx_cq_moderation.pkts =
4110                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4111         params->rx_cq_moderation.usec =
4112                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4113
4114         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4115                 params->rx_cq_moderation.usec =
4116                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4117
4118         if (params->rx_dim_enabled) {
4119                 switch (cq_period_mode) {
4120                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
4121                         params->rx_cq_moderation =
4122                                 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
4123                         break;
4124                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
4125                 default:
4126                         params->rx_cq_moderation =
4127                                 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
4128                 }
4129         }
4130
4131         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4132                         params->rx_cq_moderation.cq_period_mode ==
4133                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4134 }
4135
4136 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4137 {
4138         int i;
4139
4140         /* The supported periods are organized in ascending order */
4141         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4142                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4143                         break;
4144
4145         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4146 }
4147
4148 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4149                             struct mlx5e_params *params,
4150                             u16 max_channels, u16 mtu)
4151 {
4152         u8 rx_cq_period_mode;
4153
4154         params->sw_mtu = mtu;
4155         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4156         params->num_channels = max_channels;
4157         params->num_tc       = 1;
4158
4159         /* SQ */
4160         params->log_sq_size = is_kdump_kernel() ?
4161                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4162                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4163
4164         /* set CQE compression */
4165         params->rx_cqe_compress_def = false;
4166         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4167             MLX5_CAP_GEN(mdev, vport_group_manager))
4168                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4169
4170         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4171
4172         /* RQ */
4173         if (mlx5e_striding_rq_possible(mdev, params))
4174                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ,
4175                                 !slow_pci_heuristic(mdev));
4176         mlx5e_set_rq_type(mdev, params);
4177         mlx5e_init_rq_type_params(mdev, params);
4178
4179         /* HW LRO */
4180
4181         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4182         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4183                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4184                         params->lro_en = !slow_pci_heuristic(mdev);
4185         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4186
4187         /* CQ moderation params */
4188         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4189                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4190                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4191         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4192         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4193         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4194
4195         /* TX inline */
4196         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4197
4198         /* RSS */
4199         params->rss_hfunc = ETH_RSS_HASH_XOR;
4200         netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4201         mlx5e_build_default_indir_rqt(params->indirection_rqt,
4202                                       MLX5E_INDIR_RQT_SIZE, max_channels);
4203 }
4204
4205 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4206                                         struct net_device *netdev,
4207                                         const struct mlx5e_profile *profile,
4208                                         void *ppriv)
4209 {
4210         struct mlx5e_priv *priv = netdev_priv(netdev);
4211
4212         priv->mdev        = mdev;
4213         priv->netdev      = netdev;
4214         priv->profile     = profile;
4215         priv->ppriv       = ppriv;
4216         priv->msglevel    = MLX5E_MSG_LEVEL;
4217
4218         mlx5e_build_nic_params(mdev, &priv->channels.params,
4219                                profile->max_nch(mdev), netdev->mtu);
4220
4221         mutex_init(&priv->state_lock);
4222
4223         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4224         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4225         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4226         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4227
4228         mlx5e_timestamp_init(priv);
4229 }
4230
4231 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4232 {
4233         struct mlx5e_priv *priv = netdev_priv(netdev);
4234
4235         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4236         if (is_zero_ether_addr(netdev->dev_addr) &&
4237             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4238                 eth_hw_addr_random(netdev);
4239                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4240         }
4241 }
4242
4243 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4244 static const struct switchdev_ops mlx5e_switchdev_ops = {
4245         .switchdev_port_attr_get        = mlx5e_attr_get,
4246 };
4247 #endif
4248
4249 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4250 {
4251         struct mlx5e_priv *priv = netdev_priv(netdev);
4252         struct mlx5_core_dev *mdev = priv->mdev;
4253         bool fcs_supported;
4254         bool fcs_enabled;
4255
4256         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4257
4258         netdev->netdev_ops = &mlx5e_netdev_ops;
4259
4260 #ifdef CONFIG_MLX5_CORE_EN_DCB
4261         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4262                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4263 #endif
4264
4265         netdev->watchdog_timeo    = 15 * HZ;
4266
4267         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4268
4269         netdev->vlan_features    |= NETIF_F_SG;
4270         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4271         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4272         netdev->vlan_features    |= NETIF_F_GRO;
4273         netdev->vlan_features    |= NETIF_F_TSO;
4274         netdev->vlan_features    |= NETIF_F_TSO6;
4275         netdev->vlan_features    |= NETIF_F_RXCSUM;
4276         netdev->vlan_features    |= NETIF_F_RXHASH;
4277
4278         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4279         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4280
4281         if (!!MLX5_CAP_ETH(mdev, lro_cap))
4282                 netdev->vlan_features    |= NETIF_F_LRO;
4283
4284         netdev->hw_features       = netdev->vlan_features;
4285         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4286         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4287         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4288         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4289
4290         if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4291                 netdev->hw_features     |= NETIF_F_GSO_PARTIAL;
4292                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4293                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4294                 netdev->hw_enc_features |= NETIF_F_TSO;
4295                 netdev->hw_enc_features |= NETIF_F_TSO6;
4296                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4297         }
4298
4299         if (mlx5e_vxlan_allowed(mdev)) {
4300                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4301                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4302                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4303                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4304                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4305         }
4306
4307         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4308                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4309                                            NETIF_F_GSO_GRE_CSUM;
4310                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4311                                            NETIF_F_GSO_GRE_CSUM;
4312                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4313                                                 NETIF_F_GSO_GRE_CSUM;
4314         }
4315
4316         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4317
4318         if (fcs_supported)
4319                 netdev->hw_features |= NETIF_F_RXALL;
4320
4321         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4322                 netdev->hw_features |= NETIF_F_RXFCS;
4323
4324         netdev->features          = netdev->hw_features;
4325         if (!priv->channels.params.lro_en)
4326                 netdev->features  &= ~NETIF_F_LRO;
4327
4328         if (fcs_enabled)
4329                 netdev->features  &= ~NETIF_F_RXALL;
4330
4331         if (!priv->channels.params.scatter_fcs_en)
4332                 netdev->features  &= ~NETIF_F_RXFCS;
4333
4334 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4335         if (FT_CAP(flow_modify_en) &&
4336             FT_CAP(modify_root) &&
4337             FT_CAP(identified_miss_table_mode) &&
4338             FT_CAP(flow_table_modify)) {
4339                 netdev->hw_features      |= NETIF_F_HW_TC;
4340 #ifdef CONFIG_RFS_ACCEL
4341                 netdev->hw_features      |= NETIF_F_NTUPLE;
4342 #endif
4343         }
4344
4345         netdev->features         |= NETIF_F_HIGHDMA;
4346         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4347
4348         netdev->priv_flags       |= IFF_UNICAST_FLT;
4349
4350         mlx5e_set_netdev_dev_addr(netdev);
4351
4352 #if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4353         if (MLX5_VPORT_MANAGER(mdev))
4354                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4355 #endif
4356
4357         mlx5e_ipsec_build_netdev(priv);
4358 }
4359
4360 static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4361 {
4362         struct mlx5_core_dev *mdev = priv->mdev;
4363         int err;
4364
4365         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4366         if (err) {
4367                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4368                 priv->q_counter = 0;
4369         }
4370
4371         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4372         if (err) {
4373                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4374                 priv->drop_rq_q_counter = 0;
4375         }
4376 }
4377
4378 static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4379 {
4380         if (priv->q_counter)
4381                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4382
4383         if (priv->drop_rq_q_counter)
4384                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4385 }
4386
4387 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4388                            struct net_device *netdev,
4389                            const struct mlx5e_profile *profile,
4390                            void *ppriv)
4391 {
4392         struct mlx5e_priv *priv = netdev_priv(netdev);
4393         int err;
4394
4395         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4396         err = mlx5e_ipsec_init(priv);
4397         if (err)
4398                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4399         mlx5e_build_nic_netdev(netdev);
4400         mlx5e_vxlan_init(priv);
4401 }
4402
4403 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4404 {
4405         mlx5e_ipsec_cleanup(priv);
4406         mlx5e_vxlan_cleanup(priv);
4407 }
4408
4409 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4410 {
4411         struct mlx5_core_dev *mdev = priv->mdev;
4412         int err;
4413
4414         err = mlx5e_create_indirect_rqt(priv);
4415         if (err)
4416                 return err;
4417
4418         err = mlx5e_create_direct_rqts(priv);
4419         if (err)
4420                 goto err_destroy_indirect_rqts;
4421
4422         err = mlx5e_create_indirect_tirs(priv);
4423         if (err)
4424                 goto err_destroy_direct_rqts;
4425
4426         err = mlx5e_create_direct_tirs(priv);
4427         if (err)
4428                 goto err_destroy_indirect_tirs;
4429
4430         err = mlx5e_create_flow_steering(priv);
4431         if (err) {
4432                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4433                 goto err_destroy_direct_tirs;
4434         }
4435
4436         err = mlx5e_tc_init(priv);
4437         if (err)
4438                 goto err_destroy_flow_steering;
4439
4440         return 0;
4441
4442 err_destroy_flow_steering:
4443         mlx5e_destroy_flow_steering(priv);
4444 err_destroy_direct_tirs:
4445         mlx5e_destroy_direct_tirs(priv);
4446 err_destroy_indirect_tirs:
4447         mlx5e_destroy_indirect_tirs(priv);
4448 err_destroy_direct_rqts:
4449         mlx5e_destroy_direct_rqts(priv);
4450 err_destroy_indirect_rqts:
4451         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4452         return err;
4453 }
4454
4455 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4456 {
4457         mlx5e_tc_cleanup(priv);
4458         mlx5e_destroy_flow_steering(priv);
4459         mlx5e_destroy_direct_tirs(priv);
4460         mlx5e_destroy_indirect_tirs(priv);
4461         mlx5e_destroy_direct_rqts(priv);
4462         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4463 }
4464
4465 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4466 {
4467         int err;
4468
4469         err = mlx5e_create_tises(priv);
4470         if (err) {
4471                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4472                 return err;
4473         }
4474
4475 #ifdef CONFIG_MLX5_CORE_EN_DCB
4476         mlx5e_dcbnl_initialize(priv);
4477 #endif
4478         return 0;
4479 }
4480
4481 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4482 {
4483         struct net_device *netdev = priv->netdev;
4484         struct mlx5_core_dev *mdev = priv->mdev;
4485         u16 max_mtu;
4486
4487         mlx5e_init_l2_addr(priv);
4488
4489         /* Marking the link as currently not needed by the Driver */
4490         if (!netif_running(netdev))
4491                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4492
4493         /* MTU range: 68 - hw-specific max */
4494         netdev->min_mtu = ETH_MIN_MTU;
4495         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4496         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4497         mlx5e_set_dev_port_mtu(priv);
4498
4499         mlx5_lag_add(mdev, netdev);
4500
4501         mlx5e_enable_async_events(priv);
4502
4503         if (MLX5_VPORT_MANAGER(priv->mdev))
4504                 mlx5e_register_vport_reps(priv);
4505
4506         if (netdev->reg_state != NETREG_REGISTERED)
4507                 return;
4508 #ifdef CONFIG_MLX5_CORE_EN_DCB
4509         mlx5e_dcbnl_init_app(priv);
4510 #endif
4511
4512         queue_work(priv->wq, &priv->set_rx_mode_work);
4513
4514         rtnl_lock();
4515         if (netif_running(netdev))
4516                 mlx5e_open(netdev);
4517         netif_device_attach(netdev);
4518         rtnl_unlock();
4519 }
4520
4521 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4522 {
4523         struct mlx5_core_dev *mdev = priv->mdev;
4524
4525 #ifdef CONFIG_MLX5_CORE_EN_DCB
4526         if (priv->netdev->reg_state == NETREG_REGISTERED)
4527                 mlx5e_dcbnl_delete_app(priv);
4528 #endif
4529
4530         rtnl_lock();
4531         if (netif_running(priv->netdev))
4532                 mlx5e_close(priv->netdev);
4533         netif_device_detach(priv->netdev);
4534         rtnl_unlock();
4535
4536         queue_work(priv->wq, &priv->set_rx_mode_work);
4537
4538         if (MLX5_VPORT_MANAGER(priv->mdev))
4539                 mlx5e_unregister_vport_reps(priv);
4540
4541         mlx5e_disable_async_events(priv);
4542         mlx5_lag_remove(mdev);
4543 }
4544
4545 static const struct mlx5e_profile mlx5e_nic_profile = {
4546         .init              = mlx5e_nic_init,
4547         .cleanup           = mlx5e_nic_cleanup,
4548         .init_rx           = mlx5e_init_nic_rx,
4549         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4550         .init_tx           = mlx5e_init_nic_tx,
4551         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4552         .enable            = mlx5e_nic_enable,
4553         .disable           = mlx5e_nic_disable,
4554         .update_stats      = mlx5e_update_ndo_stats,
4555         .max_nch           = mlx5e_get_max_num_channels,
4556         .update_carrier    = mlx5e_update_carrier,
4557         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4558         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4559         .max_tc            = MLX5E_MAX_NUM_TC,
4560 };
4561
4562 /* mlx5e generic netdev management API (move to en_common.c) */
4563
4564 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4565                                        const struct mlx5e_profile *profile,
4566                                        void *ppriv)
4567 {
4568         int nch = profile->max_nch(mdev);
4569         struct net_device *netdev;
4570         struct mlx5e_priv *priv;
4571
4572         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4573                                     nch * profile->max_tc,
4574                                     nch);
4575         if (!netdev) {
4576                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4577                 return NULL;
4578         }
4579
4580 #ifdef CONFIG_RFS_ACCEL
4581         netdev->rx_cpu_rmap = mdev->rmap;
4582 #endif
4583
4584         profile->init(mdev, netdev, profile, ppriv);
4585
4586         netif_carrier_off(netdev);
4587
4588         priv = netdev_priv(netdev);
4589
4590         priv->wq = create_singlethread_workqueue("mlx5e");
4591         if (!priv->wq)
4592                 goto err_cleanup_nic;
4593
4594         return netdev;
4595
4596 err_cleanup_nic:
4597         if (profile->cleanup)
4598                 profile->cleanup(priv);
4599         free_netdev(netdev);
4600
4601         return NULL;
4602 }
4603
4604 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4605 {
4606         struct mlx5_core_dev *mdev = priv->mdev;
4607         const struct mlx5e_profile *profile;
4608         int err;
4609
4610         profile = priv->profile;
4611         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4612
4613         err = profile->init_tx(priv);
4614         if (err)
4615                 goto out;
4616
4617         mlx5e_create_q_counters(priv);
4618
4619         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4620         if (err) {
4621                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4622                 goto err_destroy_q_counters;
4623         }
4624
4625         err = profile->init_rx(priv);
4626         if (err)
4627                 goto err_close_drop_rq;
4628
4629         if (profile->enable)
4630                 profile->enable(priv);
4631
4632         return 0;
4633
4634 err_close_drop_rq:
4635         mlx5e_close_drop_rq(&priv->drop_rq);
4636
4637 err_destroy_q_counters:
4638         mlx5e_destroy_q_counters(priv);
4639         profile->cleanup_tx(priv);
4640
4641 out:
4642         return err;
4643 }
4644
4645 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4646 {
4647         const struct mlx5e_profile *profile = priv->profile;
4648
4649         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4650
4651         if (profile->disable)
4652                 profile->disable(priv);
4653         flush_workqueue(priv->wq);
4654
4655         profile->cleanup_rx(priv);
4656         mlx5e_close_drop_rq(&priv->drop_rq);
4657         mlx5e_destroy_q_counters(priv);
4658         profile->cleanup_tx(priv);
4659         cancel_delayed_work_sync(&priv->update_stats_work);
4660 }
4661
4662 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4663 {
4664         const struct mlx5e_profile *profile = priv->profile;
4665         struct net_device *netdev = priv->netdev;
4666
4667         destroy_workqueue(priv->wq);
4668         if (profile->cleanup)
4669                 profile->cleanup(priv);
4670         free_netdev(netdev);
4671 }
4672
4673 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4674  * hardware contexts and to connect it to the current netdev.
4675  */
4676 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4677 {
4678         struct mlx5e_priv *priv = vpriv;
4679         struct net_device *netdev = priv->netdev;
4680         int err;
4681
4682         if (netif_device_present(netdev))
4683                 return 0;
4684
4685         err = mlx5e_create_mdev_resources(mdev);
4686         if (err)
4687                 return err;
4688
4689         err = mlx5e_attach_netdev(priv);
4690         if (err) {
4691                 mlx5e_destroy_mdev_resources(mdev);
4692                 return err;
4693         }
4694
4695         return 0;
4696 }
4697
4698 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4699 {
4700         struct mlx5e_priv *priv = vpriv;
4701         struct net_device *netdev = priv->netdev;
4702
4703         if (!netif_device_present(netdev))
4704                 return;
4705
4706         mlx5e_detach_netdev(priv);
4707         mlx5e_destroy_mdev_resources(mdev);
4708 }
4709
4710 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4711 {
4712         struct net_device *netdev;
4713         void *rpriv = NULL;
4714         void *priv;
4715         int err;
4716
4717         err = mlx5e_check_required_hca_cap(mdev);
4718         if (err)
4719                 return NULL;
4720
4721 #ifdef CONFIG_MLX5_ESWITCH
4722         if (MLX5_VPORT_MANAGER(mdev)) {
4723                 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4724                 if (!rpriv) {
4725                         mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4726                         return NULL;
4727                 }
4728         }
4729 #endif
4730
4731         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4732         if (!netdev) {
4733                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4734                 goto err_free_rpriv;
4735         }
4736
4737         priv = netdev_priv(netdev);
4738
4739         err = mlx5e_attach(mdev, priv);
4740         if (err) {
4741                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4742                 goto err_destroy_netdev;
4743         }
4744
4745         err = register_netdev(netdev);
4746         if (err) {
4747                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4748                 goto err_detach;
4749         }
4750
4751 #ifdef CONFIG_MLX5_CORE_EN_DCB
4752         mlx5e_dcbnl_init_app(priv);
4753 #endif
4754         return priv;
4755
4756 err_detach:
4757         mlx5e_detach(mdev, priv);
4758 err_destroy_netdev:
4759         mlx5e_destroy_netdev(priv);
4760 err_free_rpriv:
4761         kfree(rpriv);
4762         return NULL;
4763 }
4764
4765 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4766 {
4767         struct mlx5e_priv *priv = vpriv;
4768         void *ppriv = priv->ppriv;
4769
4770 #ifdef CONFIG_MLX5_CORE_EN_DCB
4771         mlx5e_dcbnl_delete_app(priv);
4772 #endif
4773         unregister_netdev(priv->netdev);
4774         mlx5e_detach(mdev, vpriv);
4775         mlx5e_destroy_netdev(priv);
4776         kfree(ppriv);
4777 }
4778
4779 static void *mlx5e_get_netdev(void *vpriv)
4780 {
4781         struct mlx5e_priv *priv = vpriv;
4782
4783         return priv->netdev;
4784 }
4785
4786 static struct mlx5_interface mlx5e_interface = {
4787         .add       = mlx5e_add,
4788         .remove    = mlx5e_remove,
4789         .attach    = mlx5e_attach,
4790         .detach    = mlx5e_detach,
4791         .event     = mlx5e_async_event,
4792         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
4793         .get_dev   = mlx5e_get_netdev,
4794 };
4795
4796 void mlx5e_init(void)
4797 {
4798         mlx5e_ipsec_build_inverse_table();
4799         mlx5e_build_ptys2ethtool_map();
4800         mlx5_register_interface(&mlx5e_interface);
4801 }
4802
4803 void mlx5e_cleanup(void)
4804 {
4805         mlx5_unregister_interface(&mlx5e_interface);
4806 }