drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 #include "lib/mlx5.h"
  67
  68
  69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  70 {
  71         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  72                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  73                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  74         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  75         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  76
  77         if (!striding_rq_umr)
  78                 return false;
  79         if (!inline_umr) {
  80                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  81                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  82                 return false;
  83         }
  84         return true;
  85 }
  86
  87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  88                                struct mlx5e_params *params)
  89 {
  90         params->log_rq_mtu_frames = is_kdump_kernel() ?
  91                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  92                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  93
  94         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  96                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  97                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  98                        BIT(params->log_rq_mtu_frames),
  99                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
 100                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 101 }
 102
 103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 104                                 struct mlx5e_params *params)
 105 {
 106         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 107                 return false;
 108
 109         if (MLX5_IPSEC_DEV(mdev))
 110                 return false;
 111
 112         if (params->xdp_prog) {
 113                 /* XSK params are not considered here. If striding RQ is in use,
 114                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 115                  * be called with the known XSK params.
 116                  */
 117                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 118                         return false;
 119         }
 120
 121         return true;
 122 }
 123
 124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 125 {
 126         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 127                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 128                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 129                 MLX5_WQ_TYPE_CYCLIC;
 130 }
 131
 132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 void mlx5e_update_stats(struct mlx5e_priv *priv)
 163 {
 164         int i;
 165
 166         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 167                 if (mlx5e_stats_grps[i].update_stats)
 168                         mlx5e_stats_grps[i].update_stats(priv);
 169 }
 170
 171 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 172 {
 173         int i;
 174
 175         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 176                 if (mlx5e_stats_grps[i].update_stats_mask &
 177                     MLX5E_NDO_UPDATE_STATS)
 178                         mlx5e_stats_grps[i].update_stats(priv);
 179 }
 180
 181 static void mlx5e_update_stats_work(struct work_struct *work)
 182 {
 183         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 184                                                update_stats_work);
 185
 186         mutex_lock(&priv->state_lock);
 187         priv->profile->update_stats(priv);
 188         mutex_unlock(&priv->state_lock);
 189 }
 190
 191 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 192 {
 193         if (!priv->profile->update_stats)
 194                 return;
 195
 196         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 197                 return;
 198
 199         queue_work(priv->wq, &priv->update_stats_work);
 200 }
 201
 202 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 203 {
 204         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 205         struct mlx5_eqe   *eqe = data;
 206
 207         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 208                 return NOTIFY_DONE;
 209
 210         switch (eqe->sub_type) {
 211         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 212         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 213                 queue_work(priv->wq, &priv->update_carrier_work);
 214                 break;
 215         default:
 216                 return NOTIFY_DONE;
 217         }
 218
 219         return NOTIFY_OK;
 220 }
 221
 222 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 223 {
 224         priv->events_nb.notifier_call = async_event;
 225         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 226 }
 227
 228 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 229 {
 230         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 231 }
 232
 233 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 234                                        struct mlx5e_icosq *sq,
 235                                        struct mlx5e_umr_wqe *wqe)
 236 {
 237         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 238         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 239         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 240
 241         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 242                                       ds_cnt);
 243         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 244         cseg->imm       = rq->mkey_be;
 245
 246         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 247         ucseg->xlt_octowords =
 248                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 249         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 250 }
 251
 252 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 253                                      struct mlx5e_channel *c)
 254 {
 255         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 256
 257         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 258                                                   sizeof(*rq->mpwqe.info)),
 259                                        GFP_KERNEL, cpu_to_node(c->cpu));
 260         if (!rq->mpwqe.info)
 261                 return -ENOMEM;
 262
 263         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 264
 265         return 0;
 266 }
 267
 268 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 269                                  u64 npages, u8 page_shift,
 270                                  struct mlx5_core_mkey *umr_mkey)
 271 {
 272         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 273         void *mkc;
 274         u32 *in;
 275         int err;
 276
 277         in = kvzalloc(inlen, GFP_KERNEL);
 278         if (!in)
 279                 return -ENOMEM;
 280
 281         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 282
 283         MLX5_SET(mkc, mkc, free, 1);
 284         MLX5_SET(mkc, mkc, umr_en, 1);
 285         MLX5_SET(mkc, mkc, lw, 1);
 286         MLX5_SET(mkc, mkc, lr, 1);
 287         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 288
 289         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 290         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 291         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 292         MLX5_SET(mkc, mkc, translations_octword_size,
 293                  MLX5_MTT_OCTW(npages));
 294         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 295
 296         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 297
 298         kvfree(in);
 299         return err;
 300 }
 301
 302 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 303 {
 304         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 305
 306         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 307 }
 308
 309 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 310 {
 311         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 312 }
 313
 314 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 315 {
 316         struct mlx5e_wqe_frag_info next_frag = {};
 317         struct mlx5e_wqe_frag_info *prev = NULL;
 318         int i;
 319
 320         next_frag.di = &rq->wqe.di[0];
 321
 322         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 323                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 324                 struct mlx5e_wqe_frag_info *frag =
 325                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 326                 int f;
 327
 328                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 329                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 330                                 next_frag.di++;
 331                                 next_frag.offset = 0;
 332                                 if (prev)
 333                                         prev->last_in_page = true;
 334                         }
 335                         *frag = next_frag;
 336
 337                         /* prepare next */
 338                         next_frag.offset += frag_info[f].frag_stride;
 339                         prev = frag;
 340                 }
 341         }
 342
 343         if (prev)
 344                 prev->last_in_page = true;
 345 }
 346
 347 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 348                               int wq_sz, int cpu)
 349 {
 350         int len = wq_sz << rq->wqe.info.log_num_frags;
 351
 352         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 353                                    GFP_KERNEL, cpu_to_node(cpu));
 354         if (!rq->wqe.di)
 355                 return -ENOMEM;
 356
 357         mlx5e_init_frags_partition(rq);
 358
 359         return 0;
 360 }
 361
 362 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 363 {
 364         kvfree(rq->wqe.di);
 365 }
 366
 367 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 368 {
 369         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 370
 371         mlx5e_reporter_rq_cqe_err(rq);
 372 }
 373
 374 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 375                           struct mlx5e_params *params,
 376                           struct mlx5e_xsk_param *xsk,
 377                           struct xdp_umem *umem,
 378                           struct mlx5e_rq_param *rqp,
 379                           struct mlx5e_rq *rq)
 380 {
 381         struct page_pool_params pp_params = { 0 };
 382         struct mlx5_core_dev *mdev = c->mdev;
 383         void *rqc = rqp->rqc;
 384         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 385         u32 num_xsk_frames = 0;
 386         u32 rq_xdp_ix;
 387         u32 pool_size;
 388         int wq_sz;
 389         int err;
 390         int i;
 391
 392         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 393
 394         rq->wq_type = params->rq_wq_type;
 395         rq->pdev    = c->pdev;
 396         rq->netdev  = c->netdev;
 397         rq->tstamp  = c->tstamp;
 398         rq->clock   = &mdev->clock;
 399         rq->channel = c;
 400         rq->ix      = c->ix;
 401         rq->mdev    = mdev;
 402         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 403         rq->xdpsq   = &c->rq_xdpsq;
 404         rq->umem    = umem;
 405
 406         if (rq->umem)
 407                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 408         else
 409                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 410         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 411
 412         if (params->xdp_prog)
 413                 bpf_prog_inc(params->xdp_prog);
 414         rq->xdp_prog = params->xdp_prog;
 415
 416         rq_xdp_ix = rq->ix;
 417         if (xsk)
 418                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 419         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 420         if (err < 0)
 421                 goto err_rq_wq_destroy;
 422
 423         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 424         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 425         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 426         pool_size = 1 << params->log_rq_mtu_frames;
 427
 428         switch (rq->wq_type) {
 429         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 430                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 431                                         &rq->wq_ctrl);
 432                 if (err)
 433                         return err;
 434
 435                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 436
 437                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 438
 439                 if (xsk)
 440                         num_xsk_frames = wq_sz <<
 441                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 442
 443                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 444                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 445
 446                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 447                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 448
 449                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 450 #ifdef CONFIG_MLX5_EN_IPSEC
 451                 if (MLX5_IPSEC_DEV(mdev)) {
 452                         err = -EINVAL;
 453                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 454                         goto err_rq_wq_destroy;
 455                 }
 456 #endif
 457                 if (!rq->handle_rx_cqe) {
 458                         err = -EINVAL;
 459                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 460                         goto err_rq_wq_destroy;
 461                 }
 462
 463                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 464                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 465                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 466                                 mlx5e_skb_from_cqe_mpwrq_linear :
 467                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 468
 469                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 470                 rq->mpwqe.num_strides =
 471                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 472
 473                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 474                 if (err)
 475                         goto err_rq_wq_destroy;
 476                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 477
 478                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 479                 if (err)
 480                         goto err_free;
 481                 break;
 482         default: /* MLX5_WQ_TYPE_CYCLIC */
 483                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 484                                          &rq->wq_ctrl);
 485                 if (err)
 486                         return err;
 487
 488                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 489
 490                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 491
 492                 if (xsk)
 493                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 494
 495                 rq->wqe.info = rqp->frags_info;
 496                 rq->wqe.frags =
 497                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 498                                         (wq_sz << rq->wqe.info.log_num_frags)),
 499                                       GFP_KERNEL, cpu_to_node(c->cpu));
 500                 if (!rq->wqe.frags) {
 501                         err = -ENOMEM;
 502                         goto err_free;
 503                 }
 504
 505                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 506                 if (err)
 507                         goto err_free;
 508
 509                 rq->post_wqes = mlx5e_post_rx_wqes;
 510                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 511
 512 #ifdef CONFIG_MLX5_EN_IPSEC
 513                 if (c->priv->ipsec)
 514                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 515                 else
 516 #endif
 517                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 518                 if (!rq->handle_rx_cqe) {
 519                         err = -EINVAL;
 520                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 521                         goto err_free;
 522                 }
 523
 524                 rq->wqe.skb_from_cqe = xsk ?
 525                         mlx5e_xsk_skb_from_cqe_linear :
 526                         mlx5e_rx_is_linear_skb(params, NULL) ?
 527                                 mlx5e_skb_from_cqe_linear :
 528                                 mlx5e_skb_from_cqe_nonlinear;
 529                 rq->mkey_be = c->mkey_be;
 530         }
 531
 532         if (xsk) {
 533                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 534                 if (unlikely(err)) {
 535                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 536                                       num_xsk_frames);
 537                         goto err_free;
 538                 }
 539
 540                 rq->zca.free = mlx5e_xsk_zca_free;
 541                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 542                                                  MEM_TYPE_ZERO_COPY,
 543                                                  &rq->zca);
 544         } else {
 545                 /* Create a page_pool and register it with rxq */
 546                 pp_params.order     = 0;
 547                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 548                 pp_params.pool_size = pool_size;
 549                 pp_params.nid       = cpu_to_node(c->cpu);
 550                 pp_params.dev       = c->pdev;
 551                 pp_params.dma_dir   = rq->buff.map_dir;
 552
 553                 /* page_pool can be used even when there is no rq->xdp_prog,
 554                  * given page_pool does not handle DMA mapping there is no
 555                  * required state to clear. And page_pool gracefully handle
 556                  * elevated refcnt.
 557                  */
 558                 rq->page_pool = page_pool_create(&pp_params);
 559                 if (IS_ERR(rq->page_pool)) {
 560                         err = PTR_ERR(rq->page_pool);
 561                         rq->page_pool = NULL;
 562                         goto err_free;
 563                 }
 564                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 565                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 566         }
 567         if (err)
 568                 goto err_free;
 569
 570         for (i = 0; i < wq_sz; i++) {
 571                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 572                         struct mlx5e_rx_wqe_ll *wqe =
 573                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 574                         u32 byte_count =
 575                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 576                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 577
 578                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 579                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 580                         wqe->data[0].lkey = rq->mkey_be;
 581                 } else {
 582                         struct mlx5e_rx_wqe_cyc *wqe =
 583                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 584                         int f;
 585
 586                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 587                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 588                                         MLX5_HW_START_PADDING;
 589
 590                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 591                                 wqe->data[f].lkey = rq->mkey_be;
 592                         }
 593                         /* check if num_frags is not a pow of two */
 594                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 595                                 wqe->data[f].byte_count = 0;
 596                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 597                                 wqe->data[f].addr = 0;
 598                         }
 599                 }
 600         }
 601
 602         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 603
 604         switch (params->rx_cq_moderation.cq_period_mode) {
 605         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 606                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 607                 break;
 608         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 609         default:
 610                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 611         }
 612
 613         rq->page_cache.head = 0;
 614         rq->page_cache.tail = 0;
 615
 616         return 0;
 617
 618 err_free:
 619         switch (rq->wq_type) {
 620         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 621                 kvfree(rq->mpwqe.info);
 622                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 623                 break;
 624         default: /* MLX5_WQ_TYPE_CYCLIC */
 625                 kvfree(rq->wqe.frags);
 626                 mlx5e_free_di_list(rq);
 627         }
 628
 629 err_rq_wq_destroy:
 630         if (rq->xdp_prog)
 631                 bpf_prog_put(rq->xdp_prog);
 632         xdp_rxq_info_unreg(&rq->xdp_rxq);
 633         page_pool_destroy(rq->page_pool);
 634         mlx5_wq_destroy(&rq->wq_ctrl);
 635
 636         return err;
 637 }
 638
 639 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 640 {
 641         int i;
 642
 643         if (rq->xdp_prog)
 644                 bpf_prog_put(rq->xdp_prog);
 645
 646         switch (rq->wq_type) {
 647         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 648                 kvfree(rq->mpwqe.info);
 649                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 650                 break;
 651         default: /* MLX5_WQ_TYPE_CYCLIC */
 652                 kvfree(rq->wqe.frags);
 653                 mlx5e_free_di_list(rq);
 654         }
 655
 656         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 657              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 658                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 659
 660                 /* With AF_XDP, page_cache is not used, so this loop is not
 661                  * entered, and it's safe to call mlx5e_page_release_dynamic
 662                  * directly.
 663                  */
 664                 mlx5e_page_release_dynamic(rq, dma_info, false);
 665         }
 666
 667         xdp_rxq_info_unreg(&rq->xdp_rxq);
 668         page_pool_destroy(rq->page_pool);
 669         mlx5_wq_destroy(&rq->wq_ctrl);
 670 }
 671
 672 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 673                            struct mlx5e_rq_param *param)
 674 {
 675         struct mlx5_core_dev *mdev = rq->mdev;
 676
 677         void *in;
 678         void *rqc;
 679         void *wq;
 680         int inlen;
 681         int err;
 682
 683         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 684                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 685         in = kvzalloc(inlen, GFP_KERNEL);
 686         if (!in)
 687                 return -ENOMEM;
 688
 689         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 690         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 691
 692         memcpy(rqc, param->rqc, sizeof(param->rqc));
 693
 694         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 695         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 696         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 697                                                 MLX5_ADAPTER_PAGE_SHIFT);
 698         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 699
 700         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 701                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 702
 703         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 704
 705         kvfree(in);
 706
 707         return err;
 708 }
 709
 710 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 711 {
 712         struct mlx5_core_dev *mdev = rq->mdev;
 713
 714         void *in;
 715         void *rqc;
 716         int inlen;
 717         int err;
 718
 719         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 720         in = kvzalloc(inlen, GFP_KERNEL);
 721         if (!in)
 722                 return -ENOMEM;
 723
 724         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 725
 726         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 727         MLX5_SET(rqc, rqc, state, next_state);
 728
 729         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 730
 731         kvfree(in);
 732
 733         return err;
 734 }
 735
 736 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 737 {
 738         struct mlx5e_channel *c = rq->channel;
 739         struct mlx5e_priv *priv = c->priv;
 740         struct mlx5_core_dev *mdev = priv->mdev;
 741
 742         void *in;
 743         void *rqc;
 744         int inlen;
 745         int err;
 746
 747         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 748         in = kvzalloc(inlen, GFP_KERNEL);
 749         if (!in)
 750                 return -ENOMEM;
 751
 752         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 753
 754         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 755         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 756                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 757         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 758         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 759
 760         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 761
 762         kvfree(in);
 763
 764         return err;
 765 }
 766
 767 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 768 {
 769         struct mlx5e_channel *c = rq->channel;
 770         struct mlx5_core_dev *mdev = c->mdev;
 771         void *in;
 772         void *rqc;
 773         int inlen;
 774         int err;
 775
 776         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 777         in = kvzalloc(inlen, GFP_KERNEL);
 778         if (!in)
 779                 return -ENOMEM;
 780
 781         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 782
 783         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 784         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 785                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 786         MLX5_SET(rqc, rqc, vsd, vsd);
 787         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 788
 789         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 790
 791         kvfree(in);
 792
 793         return err;
 794 }
 795
 796 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 797 {
 798         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 799 }
 800
 801 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 802 {
 803         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 804         struct mlx5e_channel *c = rq->channel;
 805
 806         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 807
 808         do {
 809                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 810                         return 0;
 811
 812                 msleep(20);
 813         } while (time_before(jiffies, exp_time));
 814
 815         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 816                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 817
 818         mlx5e_reporter_rx_timeout(rq);
 819         return -ETIMEDOUT;
 820 }
 821
 822 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 823 {
 824         __be16 wqe_ix_be;
 825         u16 wqe_ix;
 826
 827         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 828                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 829                 u16 head = wq->head;
 830                 int i;
 831
 832                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 833                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 834                         rq->dealloc_wqe(rq, head);
 835                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 836                 }
 837
 838                 while (!mlx5_wq_ll_is_empty(wq)) {
 839                         struct mlx5e_rx_wqe_ll *wqe;
 840
 841                         wqe_ix_be = *wq->tail_next;
 842                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 843                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 844                         rq->dealloc_wqe(rq, wqe_ix);
 845                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 846                                        &wqe->next.next_wqe_index);
 847                 }
 848         } else {
 849                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 850
 851                 while (!mlx5_wq_cyc_is_empty(wq)) {
 852                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 853                         rq->dealloc_wqe(rq, wqe_ix);
 854                         mlx5_wq_cyc_pop(wq);
 855                 }
 856         }
 857
 858 }
 859
 860 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 861                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 862                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 863 {
 864         int err;
 865
 866         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 867         if (err)
 868                 return err;
 869
 870         err = mlx5e_create_rq(rq, param);
 871         if (err)
 872                 goto err_free_rq;
 873
 874         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 875         if (err)
 876                 goto err_destroy_rq;
 877
 878         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 879                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 880
 881         if (params->rx_dim_enabled)
 882                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 883
 884         /* We disable csum_complete when XDP is enabled since
 885          * XDP programs might manipulate packets which will render
 886          * skb->checksum incorrect.
 887          */
 888         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 889                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 890
 891         return 0;
 892
 893 err_destroy_rq:
 894         mlx5e_destroy_rq(rq);
 895 err_free_rq:
 896         mlx5e_free_rq(rq);
 897
 898         return err;
 899 }
 900
 901 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 902 {
 903         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 904         mlx5e_trigger_irq(&rq->channel->icosq);
 905 }
 906
 907 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 908 {
 909         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 910         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 911 }
 912
 913 void mlx5e_close_rq(struct mlx5e_rq *rq)
 914 {
 915         cancel_work_sync(&rq->dim.work);
 916         cancel_work_sync(&rq->channel->icosq.recover_work);
 917         cancel_work_sync(&rq->recover_work);
 918         mlx5e_destroy_rq(rq);
 919         mlx5e_free_rx_descs(rq);
 920         mlx5e_free_rq(rq);
 921 }
 922
 923 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 924 {
 925         kvfree(sq->db.xdpi_fifo.xi);
 926         kvfree(sq->db.wqe_info);
 927 }
 928
 929 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 930 {
 931         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 932         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 933         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 934
 935         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 936                                       GFP_KERNEL, numa);
 937         if (!xdpi_fifo->xi)
 938                 return -ENOMEM;
 939
 940         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 941         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 942         xdpi_fifo->mask = dsegs_per_wq - 1;
 943
 944         return 0;
 945 }
 946
 947 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 948 {
 949         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 950         int err;
 951
 952         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 953                                         GFP_KERNEL, numa);
 954         if (!sq->db.wqe_info)
 955                 return -ENOMEM;
 956
 957         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 958         if (err) {
 959                 mlx5e_free_xdpsq_db(sq);
 960                 return err;
 961         }
 962
 963         return 0;
 964 }
 965
 966 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 967                              struct mlx5e_params *params,
 968                              struct xdp_umem *umem,
 969                              struct mlx5e_sq_param *param,
 970                              struct mlx5e_xdpsq *sq,
 971                              bool is_redirect)
 972 {
 973         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 974         struct mlx5_core_dev *mdev = c->mdev;
 975         struct mlx5_wq_cyc *wq = &sq->wq;
 976         int err;
 977
 978         sq->pdev      = c->pdev;
 979         sq->mkey_be   = c->mkey_be;
 980         sq->channel   = c;
 981         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 982         sq->min_inline_mode = params->tx_min_inline_mode;
 983         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 984         sq->umem      = umem;
 985
 986         sq->stats = sq->umem ?
 987                 &c->priv->channel_stats[c->ix].xsksq :
 988                 is_redirect ?
 989                         &c->priv->channel_stats[c->ix].xdpsq :
 990                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 991
 992         param->wq.db_numa_node = cpu_to_node(c->cpu);
 993         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 994         if (err)
 995                 return err;
 996         wq->db = &wq->db[MLX5_SND_DBR];
 997
 998         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 999         if (err)
1000                 goto err_sq_wq_destroy;
1001
1002         return 0;
1003
1004 err_sq_wq_destroy:
1005         mlx5_wq_destroy(&sq->wq_ctrl);
1006
1007         return err;
1008 }
1009
1010 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1011 {
1012         mlx5e_free_xdpsq_db(sq);
1013         mlx5_wq_destroy(&sq->wq_ctrl);
1014 }
1015
1016 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1017 {
1018         kvfree(sq->db.ico_wqe);
1019 }
1020
1021 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1022 {
1023         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1024
1025         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1026                                                   sizeof(*sq->db.ico_wqe)),
1027                                        GFP_KERNEL, numa);
1028         if (!sq->db.ico_wqe)
1029                 return -ENOMEM;
1030
1031         return 0;
1032 }
1033
1034 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1035 {
1036         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1037                                               recover_work);
1038
1039         mlx5e_reporter_icosq_cqe_err(sq);
1040 }
1041
1042 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1043                              struct mlx5e_sq_param *param,
1044                              struct mlx5e_icosq *sq)
1045 {
1046         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1047         struct mlx5_core_dev *mdev = c->mdev;
1048         struct mlx5_wq_cyc *wq = &sq->wq;
1049         int err;
1050
1051         sq->channel   = c;
1052         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1053
1054         param->wq.db_numa_node = cpu_to_node(c->cpu);
1055         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1056         if (err)
1057                 return err;
1058         wq->db = &wq->db[MLX5_SND_DBR];
1059
1060         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1061         if (err)
1062                 goto err_sq_wq_destroy;
1063
1064         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1065
1066         return 0;
1067
1068 err_sq_wq_destroy:
1069         mlx5_wq_destroy(&sq->wq_ctrl);
1070
1071         return err;
1072 }
1073
1074 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1075 {
1076         mlx5e_free_icosq_db(sq);
1077         mlx5_wq_destroy(&sq->wq_ctrl);
1078 }
1079
1080 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1081 {
1082         kvfree(sq->db.wqe_info);
1083         kvfree(sq->db.dma_fifo);
1084 }
1085
1086 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1087 {
1088         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1089         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1090
1091         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1092                                                    sizeof(*sq->db.dma_fifo)),
1093                                         GFP_KERNEL, numa);
1094         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1095                                                    sizeof(*sq->db.wqe_info)),
1096                                         GFP_KERNEL, numa);
1097         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1098                 mlx5e_free_txqsq_db(sq);
1099                 return -ENOMEM;
1100         }
1101
1102         sq->dma_fifo_mask = df_sz - 1;
1103
1104         return 0;
1105 }
1106
1107 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1108 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1109                              int txq_ix,
1110                              struct mlx5e_params *params,
1111                              struct mlx5e_sq_param *param,
1112                              struct mlx5e_txqsq *sq,
1113                              int tc)
1114 {
1115         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1116         struct mlx5_core_dev *mdev = c->mdev;
1117         struct mlx5_wq_cyc *wq = &sq->wq;
1118         int err;
1119
1120         sq->pdev      = c->pdev;
1121         sq->tstamp    = c->tstamp;
1122         sq->clock     = &mdev->clock;
1123         sq->mkey_be   = c->mkey_be;
1124         sq->channel   = c;
1125         sq->ch_ix     = c->ix;
1126         sq->txq_ix    = txq_ix;
1127         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1128         sq->min_inline_mode = params->tx_min_inline_mode;
1129         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1130         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1131         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1132         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1133         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1134                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1135         if (MLX5_IPSEC_DEV(c->priv->mdev))
1136                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1137 #ifdef CONFIG_MLX5_EN_TLS
1138         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1139                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1140                 sq->stop_room += MLX5E_SQ_TLS_ROOM +
1141                         mlx5e_ktls_dumps_num_wqebbs(sq, MAX_SKB_FRAGS,
1142                                                     TLS_MAX_PAYLOAD_SIZE);
1143         }
1144 #endif
1145
1146         param->wq.db_numa_node = cpu_to_node(c->cpu);
1147         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1148         if (err)
1149                 return err;
1150         wq->db    = &wq->db[MLX5_SND_DBR];
1151
1152         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1153         if (err)
1154                 goto err_sq_wq_destroy;
1155
1156         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1157         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1158
1159         return 0;
1160
1161 err_sq_wq_destroy:
1162         mlx5_wq_destroy(&sq->wq_ctrl);
1163
1164         return err;
1165 }
1166
1167 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1168 {
1169         mlx5e_free_txqsq_db(sq);
1170         mlx5_wq_destroy(&sq->wq_ctrl);
1171 }
1172
1173 struct mlx5e_create_sq_param {
1174         struct mlx5_wq_ctrl        *wq_ctrl;
1175         u32                         cqn;
1176         u32                         tisn;
1177         u8                          tis_lst_sz;
1178         u8                          min_inline_mode;
1179 };
1180
1181 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1182                            struct mlx5e_sq_param *param,
1183                            struct mlx5e_create_sq_param *csp,
1184                            u32 *sqn)
1185 {
1186         void *in;
1187         void *sqc;
1188         void *wq;
1189         int inlen;
1190         int err;
1191
1192         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1193                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1194         in = kvzalloc(inlen, GFP_KERNEL);
1195         if (!in)
1196                 return -ENOMEM;
1197
1198         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1199         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1200
1201         memcpy(sqc, param->sqc, sizeof(param->sqc));
1202         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1203         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1204         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1205
1206         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1207                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1208
1209         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1210         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1211
1212         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1213         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1214         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1215                                           MLX5_ADAPTER_PAGE_SHIFT);
1216         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1217
1218         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1219                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1220
1221         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1222
1223         kvfree(in);
1224
1225         return err;
1226 }
1227
1228 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1229                     struct mlx5e_modify_sq_param *p)
1230 {
1231         void *in;
1232         void *sqc;
1233         int inlen;
1234         int err;
1235
1236         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1237         in = kvzalloc(inlen, GFP_KERNEL);
1238         if (!in)
1239                 return -ENOMEM;
1240
1241         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1242
1243         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1244         MLX5_SET(sqc, sqc, state, p->next_state);
1245         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1246                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1247                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1248         }
1249
1250         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1251
1252         kvfree(in);
1253
1254         return err;
1255 }
1256
1257 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1258 {
1259         mlx5_core_destroy_sq(mdev, sqn);
1260 }
1261
1262 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1263                                struct mlx5e_sq_param *param,
1264                                struct mlx5e_create_sq_param *csp,
1265                                u32 *sqn)
1266 {
1267         struct mlx5e_modify_sq_param msp = {0};
1268         int err;
1269
1270         err = mlx5e_create_sq(mdev, param, csp, sqn);
1271         if (err)
1272                 return err;
1273
1274         msp.curr_state = MLX5_SQC_STATE_RST;
1275         msp.next_state = MLX5_SQC_STATE_RDY;
1276         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1277         if (err)
1278                 mlx5e_destroy_sq(mdev, *sqn);
1279
1280         return err;
1281 }
1282
1283 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1284                                 struct mlx5e_txqsq *sq, u32 rate);
1285
1286 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1287                             u32 tisn,
1288                             int txq_ix,
1289                             struct mlx5e_params *params,
1290                             struct mlx5e_sq_param *param,
1291                             struct mlx5e_txqsq *sq,
1292                             int tc)
1293 {
1294         struct mlx5e_create_sq_param csp = {};
1295         u32 tx_rate;
1296         int err;
1297
1298         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1299         if (err)
1300                 return err;
1301
1302         csp.tisn            = tisn;
1303         csp.tis_lst_sz      = 1;
1304         csp.cqn             = sq->cq.mcq.cqn;
1305         csp.wq_ctrl         = &sq->wq_ctrl;
1306         csp.min_inline_mode = sq->min_inline_mode;
1307         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1308         if (err)
1309                 goto err_free_txqsq;
1310
1311         tx_rate = c->priv->tx_rates[sq->txq_ix];
1312         if (tx_rate)
1313                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1314
1315         if (params->tx_dim_enabled)
1316                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1317
1318         return 0;
1319
1320 err_free_txqsq:
1321         mlx5e_free_txqsq(sq);
1322
1323         return err;
1324 }
1325
1326 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1327 {
1328         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1329         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1330         netdev_tx_reset_queue(sq->txq);
1331         netif_tx_start_queue(sq->txq);
1332 }
1333
1334 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1335 {
1336         __netif_tx_lock_bh(txq);
1337         netif_tx_stop_queue(txq);
1338         __netif_tx_unlock_bh(txq);
1339 }
1340
1341 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1342 {
1343         struct mlx5e_channel *c = sq->channel;
1344         struct mlx5_wq_cyc *wq = &sq->wq;
1345
1346         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1347         /* prevent netif_tx_wake_queue */
1348         napi_synchronize(&c->napi);
1349
1350         mlx5e_tx_disable_queue(sq->txq);
1351
1352         /* last doorbell out, godspeed .. */
1353         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1354                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1355                 struct mlx5e_tx_wqe_info *wi;
1356                 struct mlx5e_tx_wqe *nop;
1357
1358                 wi = &sq->db.wqe_info[pi];
1359
1360                 memset(wi, 0, sizeof(*wi));
1361                 wi->num_wqebbs = 1;
1362                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1363                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1364         }
1365 }
1366
1367 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1368 {
1369         struct mlx5e_channel *c = sq->channel;
1370         struct mlx5_core_dev *mdev = c->mdev;
1371         struct mlx5_rate_limit rl = {0};
1372
1373         cancel_work_sync(&sq->dim.work);
1374         cancel_work_sync(&sq->recover_work);
1375         mlx5e_destroy_sq(mdev, sq->sqn);
1376         if (sq->rate_limit) {
1377                 rl.rate = sq->rate_limit;
1378                 mlx5_rl_remove_rate(mdev, &rl);
1379         }
1380         mlx5e_free_txqsq_descs(sq);
1381         mlx5e_free_txqsq(sq);
1382 }
1383
1384 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1385 {
1386         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1387                                               recover_work);
1388
1389         mlx5e_reporter_tx_err_cqe(sq);
1390 }
1391
1392 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1393                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1394 {
1395         struct mlx5e_create_sq_param csp = {};
1396         int err;
1397
1398         err = mlx5e_alloc_icosq(c, param, sq);
1399         if (err)
1400                 return err;
1401
1402         csp.cqn             = sq->cq.mcq.cqn;
1403         csp.wq_ctrl         = &sq->wq_ctrl;
1404         csp.min_inline_mode = params->tx_min_inline_mode;
1405         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1406         if (err)
1407                 goto err_free_icosq;
1408
1409         return 0;
1410
1411 err_free_icosq:
1412         mlx5e_free_icosq(sq);
1413
1414         return err;
1415 }
1416
1417 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1418 {
1419         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1420 }
1421
1422 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1423 {
1424         struct mlx5e_channel *c = icosq->channel;
1425
1426         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1427         napi_synchronize(&c->napi);
1428 }
1429
1430 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1431 {
1432         struct mlx5e_channel *c = sq->channel;
1433
1434         mlx5e_destroy_sq(c->mdev, sq->sqn);
1435         mlx5e_free_icosq(sq);
1436 }
1437
1438 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1439                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1440                      struct mlx5e_xdpsq *sq, bool is_redirect)
1441 {
1442         struct mlx5e_create_sq_param csp = {};
1443         int err;
1444
1445         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1446         if (err)
1447                 return err;
1448
1449         csp.tis_lst_sz      = 1;
1450         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1451         csp.cqn             = sq->cq.mcq.cqn;
1452         csp.wq_ctrl         = &sq->wq_ctrl;
1453         csp.min_inline_mode = sq->min_inline_mode;
1454         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1455         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1456         if (err)
1457                 goto err_free_xdpsq;
1458
1459         mlx5e_set_xmit_fp(sq, param->is_mpw);
1460
1461         if (!param->is_mpw) {
1462                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1463                 unsigned int inline_hdr_sz = 0;
1464                 int i;
1465
1466                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1467                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1468                         ds_cnt++;
1469                 }
1470
1471                 /* Pre initialize fixed WQE fields */
1472                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1473                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1474                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1475                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1476                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1477                         struct mlx5_wqe_data_seg *dseg;
1478
1479                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1480                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1481
1482                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1483                         dseg->lkey = sq->mkey_be;
1484
1485                         wi->num_wqebbs = 1;
1486                         wi->num_pkts   = 1;
1487                 }
1488         }
1489
1490         return 0;
1491
1492 err_free_xdpsq:
1493         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1494         mlx5e_free_xdpsq(sq);
1495
1496         return err;
1497 }
1498
1499 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1500 {
1501         struct mlx5e_channel *c = sq->channel;
1502
1503         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1504         napi_synchronize(&c->napi);
1505
1506         mlx5e_destroy_sq(c->mdev, sq->sqn);
1507         mlx5e_free_xdpsq_descs(sq);
1508         mlx5e_free_xdpsq(sq);
1509 }
1510
1511 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1512                                  struct mlx5e_cq_param *param,
1513                                  struct mlx5e_cq *cq)
1514 {
1515         struct mlx5_core_cq *mcq = &cq->mcq;
1516         int eqn_not_used;
1517         unsigned int irqn;
1518         int err;
1519         u32 i;
1520
1521         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1522         if (err)
1523                 return err;
1524
1525         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1526                                &cq->wq_ctrl);
1527         if (err)
1528                 return err;
1529
1530         mcq->cqe_sz     = 64;
1531         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1532         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1533         *mcq->set_ci_db = 0;
1534         *mcq->arm_db    = 0;
1535         mcq->vector     = param->eq_ix;
1536         mcq->comp       = mlx5e_completion_event;
1537         mcq->event      = mlx5e_cq_error_event;
1538         mcq->irqn       = irqn;
1539
1540         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1541                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1542
1543                 cqe->op_own = 0xf1;
1544         }
1545
1546         cq->mdev = mdev;
1547
1548         return 0;
1549 }
1550
1551 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1552                           struct mlx5e_cq_param *param,
1553                           struct mlx5e_cq *cq)
1554 {
1555         struct mlx5_core_dev *mdev = c->priv->mdev;
1556         int err;
1557
1558         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1559         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1560         param->eq_ix   = c->ix;
1561
1562         err = mlx5e_alloc_cq_common(mdev, param, cq);
1563
1564         cq->napi    = &c->napi;
1565         cq->channel = c;
1566
1567         return err;
1568 }
1569
1570 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1571 {
1572         mlx5_wq_destroy(&cq->wq_ctrl);
1573 }
1574
1575 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1576 {
1577         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1578         struct mlx5_core_dev *mdev = cq->mdev;
1579         struct mlx5_core_cq *mcq = &cq->mcq;
1580
1581         void *in;
1582         void *cqc;
1583         int inlen;
1584         unsigned int irqn_not_used;
1585         int eqn;
1586         int err;
1587
1588         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1589         if (err)
1590                 return err;
1591
1592         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1593                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1594         in = kvzalloc(inlen, GFP_KERNEL);
1595         if (!in)
1596                 return -ENOMEM;
1597
1598         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1599
1600         memcpy(cqc, param->cqc, sizeof(param->cqc));
1601
1602         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1603                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1604
1605         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1606         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1607         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1608         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1609                                             MLX5_ADAPTER_PAGE_SHIFT);
1610         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1611
1612         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1613
1614         kvfree(in);
1615
1616         if (err)
1617                 return err;
1618
1619         mlx5e_cq_arm(cq);
1620
1621         return 0;
1622 }
1623
1624 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1625 {
1626         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1627 }
1628
1629 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1630                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1631 {
1632         struct mlx5_core_dev *mdev = c->mdev;
1633         int err;
1634
1635         err = mlx5e_alloc_cq(c, param, cq);
1636         if (err)
1637                 return err;
1638
1639         err = mlx5e_create_cq(cq, param);
1640         if (err)
1641                 goto err_free_cq;
1642
1643         if (MLX5_CAP_GEN(mdev, cq_moderation))
1644                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1645         return 0;
1646
1647 err_free_cq:
1648         mlx5e_free_cq(cq);
1649
1650         return err;
1651 }
1652
1653 void mlx5e_close_cq(struct mlx5e_cq *cq)
1654 {
1655         mlx5e_destroy_cq(cq);
1656         mlx5e_free_cq(cq);
1657 }
1658
1659 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1660                              struct mlx5e_params *params,
1661                              struct mlx5e_channel_param *cparam)
1662 {
1663         int err;
1664         int tc;
1665
1666         for (tc = 0; tc < c->num_tc; tc++) {
1667                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1668                                     &cparam->tx_cq, &c->sq[tc].cq);
1669                 if (err)
1670                         goto err_close_tx_cqs;
1671         }
1672
1673         return 0;
1674
1675 err_close_tx_cqs:
1676         for (tc--; tc >= 0; tc--)
1677                 mlx5e_close_cq(&c->sq[tc].cq);
1678
1679         return err;
1680 }
1681
1682 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1683 {
1684         int tc;
1685
1686         for (tc = 0; tc < c->num_tc; tc++)
1687                 mlx5e_close_cq(&c->sq[tc].cq);
1688 }
1689
1690 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1691                           struct mlx5e_params *params,
1692                           struct mlx5e_channel_param *cparam)
1693 {
1694         struct mlx5e_priv *priv = c->priv;
1695         int err, tc;
1696
1697         for (tc = 0; tc < params->num_tc; tc++) {
1698                 int txq_ix = c->ix + tc * priv->max_nch;
1699
1700                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1701                                        params, &cparam->sq, &c->sq[tc], tc);
1702                 if (err)
1703                         goto err_close_sqs;
1704         }
1705
1706         return 0;
1707
1708 err_close_sqs:
1709         for (tc--; tc >= 0; tc--)
1710                 mlx5e_close_txqsq(&c->sq[tc]);
1711
1712         return err;
1713 }
1714
1715 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1716 {
1717         int tc;
1718
1719         for (tc = 0; tc < c->num_tc; tc++)
1720                 mlx5e_close_txqsq(&c->sq[tc]);
1721 }
1722
1723 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1724                                 struct mlx5e_txqsq *sq, u32 rate)
1725 {
1726         struct mlx5e_priv *priv = netdev_priv(dev);
1727         struct mlx5_core_dev *mdev = priv->mdev;
1728         struct mlx5e_modify_sq_param msp = {0};
1729         struct mlx5_rate_limit rl = {0};
1730         u16 rl_index = 0;
1731         int err;
1732
1733         if (rate == sq->rate_limit)
1734                 /* nothing to do */
1735                 return 0;
1736
1737         if (sq->rate_limit) {
1738                 rl.rate = sq->rate_limit;
1739                 /* remove current rl index to free space to next ones */
1740                 mlx5_rl_remove_rate(mdev, &rl);
1741         }
1742
1743         sq->rate_limit = 0;
1744
1745         if (rate) {
1746                 rl.rate = rate;
1747                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1748                 if (err) {
1749                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1750                                    rate, err);
1751                         return err;
1752                 }
1753         }
1754
1755         msp.curr_state = MLX5_SQC_STATE_RDY;
1756         msp.next_state = MLX5_SQC_STATE_RDY;
1757         msp.rl_index   = rl_index;
1758         msp.rl_update  = true;
1759         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1760         if (err) {
1761                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1762                            rate, err);
1763                 /* remove the rate from the table */
1764                 if (rate)
1765                         mlx5_rl_remove_rate(mdev, &rl);
1766                 return err;
1767         }
1768
1769         sq->rate_limit = rate;
1770         return 0;
1771 }
1772
1773 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1774 {
1775         struct mlx5e_priv *priv = netdev_priv(dev);
1776         struct mlx5_core_dev *mdev = priv->mdev;
1777         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1778         int err = 0;
1779
1780         if (!mlx5_rl_is_supported(mdev)) {
1781                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1782                 return -EINVAL;
1783         }
1784
1785         /* rate is given in Mb/sec, HW config is in Kb/sec */
1786         rate = rate << 10;
1787
1788         /* Check whether rate in valid range, 0 is always valid */
1789         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1790                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1791                 return -ERANGE;
1792         }
1793
1794         mutex_lock(&priv->state_lock);
1795         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1796                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1797         if (!err)
1798                 priv->tx_rates[index] = rate;
1799         mutex_unlock(&priv->state_lock);
1800
1801         return err;
1802 }
1803
1804 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1805                                    struct mlx5e_params *params)
1806 {
1807         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1808         int irq;
1809
1810         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1811                 return -ENOMEM;
1812
1813         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1814                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1815
1816                 cpumask_set_cpu(cpu, c->xps_cpumask);
1817         }
1818
1819         return 0;
1820 }
1821
1822 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1823 {
1824         free_cpumask_var(c->xps_cpumask);
1825 }
1826
1827 static int mlx5e_open_queues(struct mlx5e_channel *c,
1828                              struct mlx5e_params *params,
1829                              struct mlx5e_channel_param *cparam)
1830 {
1831         struct dim_cq_moder icocq_moder = {0, 0};
1832         int err;
1833
1834         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1835         if (err)
1836                 return err;
1837
1838         err = mlx5e_open_tx_cqs(c, params, cparam);
1839         if (err)
1840                 goto err_close_icosq_cq;
1841
1842         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1843         if (err)
1844                 goto err_close_tx_cqs;
1845
1846         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1847         if (err)
1848                 goto err_close_xdp_tx_cqs;
1849
1850         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1851         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1852                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1853         if (err)
1854                 goto err_close_rx_cq;
1855
1856         napi_enable(&c->napi);
1857
1858         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1859         if (err)
1860                 goto err_disable_napi;
1861
1862         err = mlx5e_open_sqs(c, params, cparam);
1863         if (err)
1864                 goto err_close_icosq;
1865
1866         if (c->xdp) {
1867                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1868                                        &c->rq_xdpsq, false);
1869                 if (err)
1870                         goto err_close_sqs;
1871         }
1872
1873         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1874         if (err)
1875                 goto err_close_xdp_sq;
1876
1877         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1878         if (err)
1879                 goto err_close_rq;
1880
1881         return 0;
1882
1883 err_close_rq:
1884         mlx5e_close_rq(&c->rq);
1885
1886 err_close_xdp_sq:
1887         if (c->xdp)
1888                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1889
1890 err_close_sqs:
1891         mlx5e_close_sqs(c);
1892
1893 err_close_icosq:
1894         mlx5e_close_icosq(&c->icosq);
1895
1896 err_disable_napi:
1897         napi_disable(&c->napi);
1898
1899         if (c->xdp)
1900                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1901
1902 err_close_rx_cq:
1903         mlx5e_close_cq(&c->rq.cq);
1904
1905 err_close_xdp_tx_cqs:
1906         mlx5e_close_cq(&c->xdpsq.cq);
1907
1908 err_close_tx_cqs:
1909         mlx5e_close_tx_cqs(c);
1910
1911 err_close_icosq_cq:
1912         mlx5e_close_cq(&c->icosq.cq);
1913
1914         return err;
1915 }
1916
1917 static void mlx5e_close_queues(struct mlx5e_channel *c)
1918 {
1919         mlx5e_close_xdpsq(&c->xdpsq);
1920         mlx5e_close_rq(&c->rq);
1921         if (c->xdp)
1922                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1923         mlx5e_close_sqs(c);
1924         mlx5e_close_icosq(&c->icosq);
1925         napi_disable(&c->napi);
1926         if (c->xdp)
1927                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1928         mlx5e_close_cq(&c->rq.cq);
1929         mlx5e_close_cq(&c->xdpsq.cq);
1930         mlx5e_close_tx_cqs(c);
1931         mlx5e_close_cq(&c->icosq.cq);
1932 }
1933
1934 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1935 {
1936         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1937
1938         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1939 }
1940
1941 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1942                               struct mlx5e_params *params,
1943                               struct mlx5e_channel_param *cparam,
1944                               struct xdp_umem *umem,
1945                               struct mlx5e_channel **cp)
1946 {
1947         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1948         struct net_device *netdev = priv->netdev;
1949         struct mlx5e_xsk_param xsk;
1950         struct mlx5e_channel *c;
1951         unsigned int irq;
1952         int err;
1953         int eqn;
1954
1955         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1956         if (err)
1957                 return err;
1958
1959         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1960         if (!c)
1961                 return -ENOMEM;
1962
1963         c->priv     = priv;
1964         c->mdev     = priv->mdev;
1965         c->tstamp   = &priv->tstamp;
1966         c->ix       = ix;
1967         c->cpu      = cpu;
1968         c->pdev     = priv->mdev->device;
1969         c->netdev   = priv->netdev;
1970         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1971         c->num_tc   = params->num_tc;
1972         c->xdp      = !!params->xdp_prog;
1973         c->stats    = &priv->channel_stats[ix].ch;
1974         c->irq_desc = irq_to_desc(irq);
1975         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1976
1977         err = mlx5e_alloc_xps_cpumask(c, params);
1978         if (err)
1979                 goto err_free_channel;
1980
1981         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1982
1983         err = mlx5e_open_queues(c, params, cparam);
1984         if (unlikely(err))
1985                 goto err_napi_del;
1986
1987         if (umem) {
1988                 mlx5e_build_xsk_param(umem, &xsk);
1989                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1990                 if (unlikely(err))
1991                         goto err_close_queues;
1992         }
1993
1994         *cp = c;
1995
1996         return 0;
1997
1998 err_close_queues:
1999         mlx5e_close_queues(c);
2000
2001 err_napi_del:
2002         netif_napi_del(&c->napi);
2003         mlx5e_free_xps_cpumask(c);
2004
2005 err_free_channel:
2006         kvfree(c);
2007
2008         return err;
2009 }
2010
2011 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2012 {
2013         int tc;
2014
2015         for (tc = 0; tc < c->num_tc; tc++)
2016                 mlx5e_activate_txqsq(&c->sq[tc]);
2017         mlx5e_activate_icosq(&c->icosq);
2018         mlx5e_activate_rq(&c->rq);
2019         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2020
2021         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2022                 mlx5e_activate_xsk(c);
2023 }
2024
2025 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2026 {
2027         int tc;
2028
2029         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2030                 mlx5e_deactivate_xsk(c);
2031
2032         mlx5e_deactivate_rq(&c->rq);
2033         mlx5e_deactivate_icosq(&c->icosq);
2034         for (tc = 0; tc < c->num_tc; tc++)
2035                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2036 }
2037
2038 static void mlx5e_close_channel(struct mlx5e_channel *c)
2039 {
2040         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2041                 mlx5e_close_xsk(c);
2042         mlx5e_close_queues(c);
2043         netif_napi_del(&c->napi);
2044         mlx5e_free_xps_cpumask(c);
2045
2046         kvfree(c);
2047 }
2048
2049 #define DEFAULT_FRAG_SIZE (2048)
2050
2051 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2052                                       struct mlx5e_params *params,
2053                                       struct mlx5e_xsk_param *xsk,
2054                                       struct mlx5e_rq_frags_info *info)
2055 {
2056         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2057         int frag_size_max = DEFAULT_FRAG_SIZE;
2058         u32 buf_size = 0;
2059         int i;
2060
2061 #ifdef CONFIG_MLX5_EN_IPSEC
2062         if (MLX5_IPSEC_DEV(mdev))
2063                 byte_count += MLX5E_METADATA_ETHER_LEN;
2064 #endif
2065
2066         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2067                 int frag_stride;
2068
2069                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2070                 frag_stride = roundup_pow_of_two(frag_stride);
2071
2072                 info->arr[0].frag_size = byte_count;
2073                 info->arr[0].frag_stride = frag_stride;
2074                 info->num_frags = 1;
2075                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2076                 goto out;
2077         }
2078
2079         if (byte_count > PAGE_SIZE +
2080             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2081                 frag_size_max = PAGE_SIZE;
2082
2083         i = 0;
2084         while (buf_size < byte_count) {
2085                 int frag_size = byte_count - buf_size;
2086
2087                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2088                         frag_size = min(frag_size, frag_size_max);
2089
2090                 info->arr[i].frag_size = frag_size;
2091                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2092
2093                 buf_size += frag_size;
2094                 i++;
2095         }
2096         info->num_frags = i;
2097         /* number of different wqes sharing a page */
2098         info->wqe_bulk = 1 + (info->num_frags % 2);
2099
2100 out:
2101         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2102         info->log_num_frags = order_base_2(info->num_frags);
2103 }
2104
2105 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2106 {
2107         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2108
2109         switch (wq_type) {
2110         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2111                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2112                 break;
2113         default: /* MLX5_WQ_TYPE_CYCLIC */
2114                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2115         }
2116
2117         return order_base_2(sz);
2118 }
2119
2120 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2121 {
2122         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2123
2124         return MLX5_GET(wq, wq, log_wq_sz);
2125 }
2126
2127 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2128                           struct mlx5e_params *params,
2129                           struct mlx5e_xsk_param *xsk,
2130                           struct mlx5e_rq_param *param)
2131 {
2132         struct mlx5_core_dev *mdev = priv->mdev;
2133         void *rqc = param->rqc;
2134         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2135         int ndsegs = 1;
2136
2137         switch (params->rq_wq_type) {
2138         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2139                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2140                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2141                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2142                 MLX5_SET(wq, wq, log_wqe_stride_size,
2143                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2144                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2145                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2146                 break;
2147         default: /* MLX5_WQ_TYPE_CYCLIC */
2148                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2149                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2150                 ndsegs = param->frags_info.num_frags;
2151         }
2152
2153         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2154         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2155         MLX5_SET(wq, wq, log_wq_stride,
2156                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2157         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2158         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2159         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2160         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2161
2162         param->wq.buf_numa_node = dev_to_node(mdev->device);
2163 }
2164
2165 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2166                                       struct mlx5e_rq_param *param)
2167 {
2168         struct mlx5_core_dev *mdev = priv->mdev;
2169         void *rqc = param->rqc;
2170         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2171
2172         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2173         MLX5_SET(wq, wq, log_wq_stride,
2174                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2175         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2176
2177         param->wq.buf_numa_node = dev_to_node(mdev->device);
2178 }
2179
2180 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2181                                  struct mlx5e_sq_param *param)
2182 {
2183         void *sqc = param->sqc;
2184         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2185
2186         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2187         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2188
2189         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2190 }
2191
2192 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2193                                  struct mlx5e_params *params,
2194                                  struct mlx5e_sq_param *param)
2195 {
2196         void *sqc = param->sqc;
2197         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2198         bool allow_swp;
2199
2200         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2201                     !!MLX5_IPSEC_DEV(priv->mdev);
2202         mlx5e_build_sq_param_common(priv, param);
2203         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2204         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2205 }
2206
2207 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2208                                         struct mlx5e_cq_param *param)
2209 {
2210         void *cqc = param->cqc;
2211
2212         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2213         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2214                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2215 }
2216
2217 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2218                              struct mlx5e_params *params,
2219                              struct mlx5e_xsk_param *xsk,
2220                              struct mlx5e_cq_param *param)
2221 {
2222         struct mlx5_core_dev *mdev = priv->mdev;
2223         void *cqc = param->cqc;
2224         u8 log_cq_size;
2225
2226         switch (params->rq_wq_type) {
2227         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2228                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2229                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2230                 break;
2231         default: /* MLX5_WQ_TYPE_CYCLIC */
2232                 log_cq_size = params->log_rq_mtu_frames;
2233         }
2234
2235         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2236         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2237                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2238                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2239         }
2240
2241         mlx5e_build_common_cq_param(priv, param);
2242         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2243 }
2244
2245 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2246                              struct mlx5e_params *params,
2247                              struct mlx5e_cq_param *param)
2248 {
2249         void *cqc = param->cqc;
2250
2251         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2252
2253         mlx5e_build_common_cq_param(priv, param);
2254         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2255 }
2256
2257 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2258                               u8 log_wq_size,
2259                               struct mlx5e_cq_param *param)
2260 {
2261         void *cqc = param->cqc;
2262
2263         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2264
2265         mlx5e_build_common_cq_param(priv, param);
2266
2267         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2268 }
2269
2270 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2271                              u8 log_wq_size,
2272                              struct mlx5e_sq_param *param)
2273 {
2274         void *sqc = param->sqc;
2275         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2276
2277         mlx5e_build_sq_param_common(priv, param);
2278
2279         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2280         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2281 }
2282
2283 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2284                              struct mlx5e_params *params,
2285                              struct mlx5e_sq_param *param)
2286 {
2287         void *sqc = param->sqc;
2288         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2289
2290         mlx5e_build_sq_param_common(priv, param);
2291         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2292         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2293 }
2294
2295 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2296                                       struct mlx5e_rq_param *rqp)
2297 {
2298         switch (params->rq_wq_type) {
2299         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2300                 return order_base_2(MLX5E_UMR_WQEBBS) +
2301                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2302         default: /* MLX5_WQ_TYPE_CYCLIC */
2303                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2304         }
2305 }
2306
2307 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2308                                       struct mlx5e_params *params,
2309                                       struct mlx5e_channel_param *cparam)
2310 {
2311         u8 icosq_log_wq_sz;
2312
2313         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2314
2315         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2316
2317         mlx5e_build_sq_param(priv, params, &cparam->sq);
2318         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2319         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2320         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2321         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2322         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2323 }
2324
2325 int mlx5e_open_channels(struct mlx5e_priv *priv,
2326                         struct mlx5e_channels *chs)
2327 {
2328         struct mlx5e_channel_param *cparam;
2329         int err = -ENOMEM;
2330         int i;
2331
2332         chs->num = chs->params.num_channels;
2333
2334         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2335         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2336         if (!chs->c || !cparam)
2337                 goto err_free;
2338
2339         mlx5e_build_channel_param(priv, &chs->params, cparam);
2340         for (i = 0; i < chs->num; i++) {
2341                 struct xdp_umem *umem = NULL;
2342
2343                 if (chs->params.xdp_prog)
2344                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2345
2346                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2347                 if (err)
2348                         goto err_close_channels;
2349         }
2350
2351         mlx5e_health_channels_update(priv);
2352         kvfree(cparam);
2353         return 0;
2354
2355 err_close_channels:
2356         for (i--; i >= 0; i--)
2357                 mlx5e_close_channel(chs->c[i]);
2358
2359 err_free:
2360         kfree(chs->c);
2361         kvfree(cparam);
2362         chs->num = 0;
2363         return err;
2364 }
2365
2366 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2367 {
2368         int i;
2369
2370         for (i = 0; i < chs->num; i++)
2371                 mlx5e_activate_channel(chs->c[i]);
2372 }
2373
2374 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2375
2376 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2377 {
2378         int err = 0;
2379         int i;
2380
2381         for (i = 0; i < chs->num; i++) {
2382                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2383
2384                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2385
2386                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2387                  * doesn't provide any Fill Ring entries at the setup stage.
2388                  */
2389         }
2390
2391         return err ? -ETIMEDOUT : 0;
2392 }
2393
2394 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2395 {
2396         int i;
2397
2398         for (i = 0; i < chs->num; i++)
2399                 mlx5e_deactivate_channel(chs->c[i]);
2400 }
2401
2402 void mlx5e_close_channels(struct mlx5e_channels *chs)
2403 {
2404         int i;
2405
2406         for (i = 0; i < chs->num; i++)
2407                 mlx5e_close_channel(chs->c[i]);
2408
2409         kfree(chs->c);
2410         chs->num = 0;
2411 }
2412
2413 static int
2414 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2415 {
2416         struct mlx5_core_dev *mdev = priv->mdev;
2417         void *rqtc;
2418         int inlen;
2419         int err;
2420         u32 *in;
2421         int i;
2422
2423         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2424         in = kvzalloc(inlen, GFP_KERNEL);
2425         if (!in)
2426                 return -ENOMEM;
2427
2428         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2429
2430         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2431         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2432
2433         for (i = 0; i < sz; i++)
2434                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2435
2436         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2437         if (!err)
2438                 rqt->enabled = true;
2439
2440         kvfree(in);
2441         return err;
2442 }
2443
2444 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2445 {
2446         rqt->enabled = false;
2447         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2448 }
2449
2450 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2451 {
2452         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2453         int err;
2454
2455         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2456         if (err)
2457                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2458         return err;
2459 }
2460
2461 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2462 {
2463         int err;
2464         int ix;
2465
2466         for (ix = 0; ix < priv->max_nch; ix++) {
2467                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2468                 if (unlikely(err))
2469                         goto err_destroy_rqts;
2470         }
2471
2472         return 0;
2473
2474 err_destroy_rqts:
2475         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2476         for (ix--; ix >= 0; ix--)
2477                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2478
2479         return err;
2480 }
2481
2482 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2483 {
2484         int i;
2485
2486         for (i = 0; i < priv->max_nch; i++)
2487                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2488 }
2489
2490 static int mlx5e_rx_hash_fn(int hfunc)
2491 {
2492         return (hfunc == ETH_RSS_HASH_TOP) ?
2493                MLX5_RX_HASH_FN_TOEPLITZ :
2494                MLX5_RX_HASH_FN_INVERTED_XOR8;
2495 }
2496
2497 int mlx5e_bits_invert(unsigned long a, int size)
2498 {
2499         int inv = 0;
2500         int i;
2501
2502         for (i = 0; i < size; i++)
2503                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2504
2505         return inv;
2506 }
2507
2508 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2509                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2510 {
2511         int i;
2512
2513         for (i = 0; i < sz; i++) {
2514                 u32 rqn;
2515
2516                 if (rrp.is_rss) {
2517                         int ix = i;
2518
2519                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2520                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2521
2522                         ix = priv->rss_params.indirection_rqt[ix];
2523                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2524                 } else {
2525                         rqn = rrp.rqn;
2526                 }
2527                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2528         }
2529 }
2530
2531 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2532                        struct mlx5e_redirect_rqt_param rrp)
2533 {
2534         struct mlx5_core_dev *mdev = priv->mdev;
2535         void *rqtc;
2536         int inlen;
2537         u32 *in;
2538         int err;
2539
2540         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2541         in = kvzalloc(inlen, GFP_KERNEL);
2542         if (!in)
2543                 return -ENOMEM;
2544
2545         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2546
2547         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2548         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2549         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2550         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2551
2552         kvfree(in);
2553         return err;
2554 }
2555
2556 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2557                                 struct mlx5e_redirect_rqt_param rrp)
2558 {
2559         if (!rrp.is_rss)
2560                 return rrp.rqn;
2561
2562         if (ix >= rrp.rss.channels->num)
2563                 return priv->drop_rq.rqn;
2564
2565         return rrp.rss.channels->c[ix]->rq.rqn;
2566 }
2567
2568 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2569                                 struct mlx5e_redirect_rqt_param rrp)
2570 {
2571         u32 rqtn;
2572         int ix;
2573
2574         if (priv->indir_rqt.enabled) {
2575                 /* RSS RQ table */
2576                 rqtn = priv->indir_rqt.rqtn;
2577                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2578         }
2579
2580         for (ix = 0; ix < priv->max_nch; ix++) {
2581                 struct mlx5e_redirect_rqt_param direct_rrp = {
2582                         .is_rss = false,
2583                         {
2584                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2585                         },
2586                 };
2587
2588                 /* Direct RQ Tables */
2589                 if (!priv->direct_tir[ix].rqt.enabled)
2590                         continue;
2591
2592                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2593                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2594         }
2595 }
2596
2597 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2598                                             struct mlx5e_channels *chs)
2599 {
2600         struct mlx5e_redirect_rqt_param rrp = {
2601                 .is_rss        = true,
2602                 {
2603                         .rss = {
2604                                 .channels  = chs,
2605                                 .hfunc     = priv->rss_params.hfunc,
2606                         }
2607                 },
2608         };
2609
2610         mlx5e_redirect_rqts(priv, rrp);
2611 }
2612
2613 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2614 {
2615         struct mlx5e_redirect_rqt_param drop_rrp = {
2616                 .is_rss = false,
2617                 {
2618                         .rqn = priv->drop_rq.rqn,
2619                 },
2620         };
2621
2622         mlx5e_redirect_rqts(priv, drop_rrp);
2623 }
2624
2625 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2626         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2627                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2628                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2629         },
2630         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2631                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2632                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2633         },
2634         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2635                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2636                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2637         },
2638         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2639                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2640                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2641         },
2642         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2643                                      .l4_prot_type = 0,
2644                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2645         },
2646         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2647                                      .l4_prot_type = 0,
2648                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2649         },
2650         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2651                                       .l4_prot_type = 0,
2652                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2653         },
2654         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2655                                       .l4_prot_type = 0,
2656                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2657         },
2658         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2659                             .l4_prot_type = 0,
2660                             .rx_hash_fields = MLX5_HASH_IP,
2661         },
2662         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2663                             .l4_prot_type = 0,
2664                             .rx_hash_fields = MLX5_HASH_IP,
2665         },
2666 };
2667
2668 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2669 {
2670         return tirc_default_config[tt];
2671 }
2672
2673 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2674 {
2675         if (!params->lro_en)
2676                 return;
2677
2678 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2679
2680         MLX5_SET(tirc, tirc, lro_enable_mask,
2681                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2682                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2683         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2684                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2685         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2686 }
2687
2688 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2689                                     const struct mlx5e_tirc_config *ttconfig,
2690                                     void *tirc, bool inner)
2691 {
2692         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2693                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2694
2695         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2696         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2697                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2698                                              rx_hash_toeplitz_key);
2699                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2700                                                rx_hash_toeplitz_key);
2701
2702                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2703                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2704         }
2705         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2706                  ttconfig->l3_prot_type);
2707         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2708                  ttconfig->l4_prot_type);
2709         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710                  ttconfig->rx_hash_fields);
2711 }
2712
2713 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2714                                         enum mlx5e_traffic_types tt,
2715                                         u32 rx_hash_fields)
2716 {
2717         *ttconfig                = tirc_default_config[tt];
2718         ttconfig->rx_hash_fields = rx_hash_fields;
2719 }
2720
2721 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2722 {
2723         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2724         struct mlx5e_rss_params *rss = &priv->rss_params;
2725         struct mlx5_core_dev *mdev = priv->mdev;
2726         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2727         struct mlx5e_tirc_config ttconfig;
2728         int tt;
2729
2730         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2731
2732         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2733                 memset(tirc, 0, ctxlen);
2734                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2735                                             rss->rx_hash_fields[tt]);
2736                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2737                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2738         }
2739
2740         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2741                 return;
2742
2743         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2744                 memset(tirc, 0, ctxlen);
2745                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2746                                             rss->rx_hash_fields[tt]);
2747                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2748                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2749                                      inlen);
2750         }
2751 }
2752
2753 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2754 {
2755         struct mlx5_core_dev *mdev = priv->mdev;
2756
2757         void *in;
2758         void *tirc;
2759         int inlen;
2760         int err;
2761         int tt;
2762         int ix;
2763
2764         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2765         in = kvzalloc(inlen, GFP_KERNEL);
2766         if (!in)
2767                 return -ENOMEM;
2768
2769         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2770         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2771
2772         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2773
2774         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2775                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2776                                            inlen);
2777                 if (err)
2778                         goto free_in;
2779         }
2780
2781         for (ix = 0; ix < priv->max_nch; ix++) {
2782                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2783                                            in, inlen);
2784                 if (err)
2785                         goto free_in;
2786         }
2787
2788 free_in:
2789         kvfree(in);
2790
2791         return err;
2792 }
2793
2794 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2795                          struct mlx5e_params *params, u16 mtu)
2796 {
2797         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2798         int err;
2799
2800         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2801         if (err)
2802                 return err;
2803
2804         /* Update vport context MTU */
2805         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2806         return 0;
2807 }
2808
2809 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2810                             struct mlx5e_params *params, u16 *mtu)
2811 {
2812         u16 hw_mtu = 0;
2813         int err;
2814
2815         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2816         if (err || !hw_mtu) /* fallback to port oper mtu */
2817                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2818
2819         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2820 }
2821
2822 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2823 {
2824         struct mlx5e_params *params = &priv->channels.params;
2825         struct net_device *netdev = priv->netdev;
2826         struct mlx5_core_dev *mdev = priv->mdev;
2827         u16 mtu;
2828         int err;
2829
2830         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2831         if (err)
2832                 return err;
2833
2834         mlx5e_query_mtu(mdev, params, &mtu);
2835         if (mtu != params->sw_mtu)
2836                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2837                             __func__, mtu, params->sw_mtu);
2838
2839         params->sw_mtu = mtu;
2840         return 0;
2841 }
2842
2843 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2844 {
2845         struct mlx5e_params *params = &priv->channels.params;
2846         struct net_device *netdev   = priv->netdev;
2847         struct mlx5_core_dev *mdev  = priv->mdev;
2848         u16 max_mtu;
2849
2850         /* MTU range: 68 - hw-specific max */
2851         netdev->min_mtu = ETH_MIN_MTU;
2852
2853         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2854         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2855                                 ETH_MAX_MTU);
2856 }
2857
2858 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2859 {
2860         struct mlx5e_priv *priv = netdev_priv(netdev);
2861         int nch = priv->channels.params.num_channels;
2862         int ntc = priv->channels.params.num_tc;
2863         int tc;
2864
2865         netdev_reset_tc(netdev);
2866
2867         if (ntc == 1)
2868                 return;
2869
2870         netdev_set_num_tc(netdev, ntc);
2871
2872         /* Map netdev TCs to offset 0
2873          * We have our own UP to TXQ mapping for QoS
2874          */
2875         for (tc = 0; tc < ntc; tc++)
2876                 netdev_set_tc_queue(netdev, tc, nch, 0);
2877 }
2878
2879 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2880 {
2881         int i, tc;
2882
2883         for (i = 0; i < priv->max_nch; i++)
2884                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2885                         priv->channel_tc2txq[i][tc] = i + tc * priv->max_nch;
2886 }
2887
2888 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2889 {
2890         struct mlx5e_channel *c;
2891         struct mlx5e_txqsq *sq;
2892         int i, tc;
2893
2894         for (i = 0; i < priv->channels.num; i++) {
2895                 c = priv->channels.c[i];
2896                 for (tc = 0; tc < c->num_tc; tc++) {
2897                         sq = &c->sq[tc];
2898                         priv->txq2sq[sq->txq_ix] = sq;
2899                 }
2900         }
2901 }
2902
2903 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2904 {
2905         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2906         int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2907         struct net_device *netdev = priv->netdev;
2908
2909         mlx5e_netdev_set_tcs(netdev);
2910         netif_set_real_num_tx_queues(netdev, num_txqs);
2911         netif_set_real_num_rx_queues(netdev, num_rxqs);
2912
2913         mlx5e_build_tx2sq_maps(priv);
2914         mlx5e_activate_channels(&priv->channels);
2915         mlx5e_xdp_tx_enable(priv);
2916         netif_tx_start_all_queues(priv->netdev);
2917
2918         if (mlx5e_is_vport_rep(priv))
2919                 mlx5e_add_sqs_fwd_rules(priv);
2920
2921         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2922         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2923
2924         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2925 }
2926
2927 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2928 {
2929         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2930
2931         mlx5e_redirect_rqts_to_drop(priv);
2932
2933         if (mlx5e_is_vport_rep(priv))
2934                 mlx5e_remove_sqs_fwd_rules(priv);
2935
2936         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2937          * polling for inactive tx queues.
2938          */
2939         netif_tx_stop_all_queues(priv->netdev);
2940         netif_tx_disable(priv->netdev);
2941         mlx5e_xdp_tx_disable(priv);
2942         mlx5e_deactivate_channels(&priv->channels);
2943 }
2944
2945 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2946                                        struct mlx5e_channels *new_chs,
2947                                        mlx5e_fp_hw_modify hw_modify)
2948 {
2949         struct net_device *netdev = priv->netdev;
2950         int new_num_txqs;
2951         int carrier_ok;
2952
2953         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2954
2955         carrier_ok = netif_carrier_ok(netdev);
2956         netif_carrier_off(netdev);
2957
2958         if (new_num_txqs < netdev->real_num_tx_queues)
2959                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2960
2961         mlx5e_deactivate_priv_channels(priv);
2962         mlx5e_close_channels(&priv->channels);
2963
2964         priv->channels = *new_chs;
2965
2966         /* New channels are ready to roll, modify HW settings if needed */
2967         if (hw_modify)
2968                 hw_modify(priv);
2969
2970         priv->profile->update_rx(priv);
2971         mlx5e_activate_priv_channels(priv);
2972
2973         /* return carrier back if needed */
2974         if (carrier_ok)
2975                 netif_carrier_on(netdev);
2976 }
2977
2978 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2979                                struct mlx5e_channels *new_chs,
2980                                mlx5e_fp_hw_modify hw_modify)
2981 {
2982         int err;
2983
2984         err = mlx5e_open_channels(priv, new_chs);
2985         if (err)
2986                 return err;
2987
2988         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2989         return 0;
2990 }
2991
2992 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2993 {
2994         struct mlx5e_channels new_channels = {};
2995
2996         new_channels.params = priv->channels.params;
2997         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2998 }
2999
3000 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3001 {
3002         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3003         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3004 }
3005
3006 int mlx5e_open_locked(struct net_device *netdev)
3007 {
3008         struct mlx5e_priv *priv = netdev_priv(netdev);
3009         bool is_xdp = priv->channels.params.xdp_prog;
3010         int err;
3011
3012         set_bit(MLX5E_STATE_OPENED, &priv->state);
3013         if (is_xdp)
3014                 mlx5e_xdp_set_open(priv);
3015
3016         err = mlx5e_open_channels(priv, &priv->channels);
3017         if (err)
3018                 goto err_clear_state_opened_flag;
3019
3020         priv->profile->update_rx(priv);
3021         mlx5e_activate_priv_channels(priv);
3022         if (priv->profile->update_carrier)
3023                 priv->profile->update_carrier(priv);
3024
3025         mlx5e_queue_update_stats(priv);
3026         return 0;
3027
3028 err_clear_state_opened_flag:
3029         if (is_xdp)
3030                 mlx5e_xdp_set_closed(priv);
3031         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3032         return err;
3033 }
3034
3035 int mlx5e_open(struct net_device *netdev)
3036 {
3037         struct mlx5e_priv *priv = netdev_priv(netdev);
3038         int err;
3039
3040         mutex_lock(&priv->state_lock);
3041         err = mlx5e_open_locked(netdev);
3042         if (!err)
3043                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3044         mutex_unlock(&priv->state_lock);
3045
3046         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3047                 udp_tunnel_get_rx_info(netdev);
3048
3049         return err;
3050 }
3051
3052 int mlx5e_close_locked(struct net_device *netdev)
3053 {
3054         struct mlx5e_priv *priv = netdev_priv(netdev);
3055
3056         /* May already be CLOSED in case a previous configuration operation
3057          * (e.g RX/TX queue size change) that involves close&open failed.
3058          */
3059         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3060                 return 0;
3061
3062         if (priv->channels.params.xdp_prog)
3063                 mlx5e_xdp_set_closed(priv);
3064         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3065
3066         netif_carrier_off(priv->netdev);
3067         mlx5e_deactivate_priv_channels(priv);
3068         mlx5e_close_channels(&priv->channels);
3069
3070         return 0;
3071 }
3072
3073 int mlx5e_close(struct net_device *netdev)
3074 {
3075         struct mlx5e_priv *priv = netdev_priv(netdev);
3076         int err;
3077
3078         if (!netif_device_present(netdev))
3079                 return -ENODEV;
3080
3081         mutex_lock(&priv->state_lock);
3082         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3083         err = mlx5e_close_locked(netdev);
3084         mutex_unlock(&priv->state_lock);
3085
3086         return err;
3087 }
3088
3089 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3090                                struct mlx5e_rq *rq,
3091                                struct mlx5e_rq_param *param)
3092 {
3093         void *rqc = param->rqc;
3094         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3095         int err;
3096
3097         param->wq.db_numa_node = param->wq.buf_numa_node;
3098
3099         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3100                                  &rq->wq_ctrl);
3101         if (err)
3102                 return err;
3103
3104         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3105         xdp_rxq_info_unused(&rq->xdp_rxq);
3106
3107         rq->mdev = mdev;
3108
3109         return 0;
3110 }
3111
3112 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3113                                struct mlx5e_cq *cq,
3114                                struct mlx5e_cq_param *param)
3115 {
3116         param->wq.buf_numa_node = dev_to_node(mdev->device);
3117         param->wq.db_numa_node  = dev_to_node(mdev->device);
3118
3119         return mlx5e_alloc_cq_common(mdev, param, cq);
3120 }
3121
3122 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3123                        struct mlx5e_rq *drop_rq)
3124 {
3125         struct mlx5_core_dev *mdev = priv->mdev;
3126         struct mlx5e_cq_param cq_param = {};
3127         struct mlx5e_rq_param rq_param = {};
3128         struct mlx5e_cq *cq = &drop_rq->cq;
3129         int err;
3130
3131         mlx5e_build_drop_rq_param(priv, &rq_param);
3132
3133         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3134         if (err)
3135                 return err;
3136
3137         err = mlx5e_create_cq(cq, &cq_param);
3138         if (err)
3139                 goto err_free_cq;
3140
3141         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3142         if (err)
3143                 goto err_destroy_cq;
3144
3145         err = mlx5e_create_rq(drop_rq, &rq_param);
3146         if (err)
3147                 goto err_free_rq;
3148
3149         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3150         if (err)
3151                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3152
3153         return 0;
3154
3155 err_free_rq:
3156         mlx5e_free_rq(drop_rq);
3157
3158 err_destroy_cq:
3159         mlx5e_destroy_cq(cq);
3160
3161 err_free_cq:
3162         mlx5e_free_cq(cq);
3163
3164         return err;
3165 }
3166
3167 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3168 {
3169         mlx5e_destroy_rq(drop_rq);
3170         mlx5e_free_rq(drop_rq);
3171         mlx5e_destroy_cq(&drop_rq->cq);
3172         mlx5e_free_cq(&drop_rq->cq);
3173 }
3174
3175 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3176 {
3177         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3178
3179         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3180
3181         if (MLX5_GET(tisc, tisc, tls_en))
3182                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3183
3184         if (mlx5_lag_is_lacp_owner(mdev))
3185                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3186
3187         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3188 }
3189
3190 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3191 {
3192         mlx5_core_destroy_tis(mdev, tisn);
3193 }
3194
3195 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3196 {
3197         int tc, i;
3198
3199         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3200                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3201                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3202 }
3203
3204 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3205 {
3206         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3207 }
3208
3209 int mlx5e_create_tises(struct mlx5e_priv *priv)
3210 {
3211         int tc, i;
3212         int err;
3213
3214         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3215                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3216                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3217                         void *tisc;
3218
3219                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3220
3221                         MLX5_SET(tisc, tisc, prio, tc << 1);
3222
3223                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3224                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3225
3226                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3227                         if (err)
3228                                 goto err_close_tises;
3229                 }
3230         }
3231
3232         return 0;
3233
3234 err_close_tises:
3235         for (; i >= 0; i--) {
3236                 for (tc--; tc >= 0; tc--)
3237                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3238                 tc = priv->profile->max_tc;
3239         }
3240
3241         return err;
3242 }
3243
3244 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3245 {
3246         mlx5e_destroy_tises(priv);
3247 }
3248
3249 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3250                                              u32 rqtn, u32 *tirc)
3251 {
3252         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3253         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3254         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3255         MLX5_SET(tirc, tirc, tunneled_offload_en,
3256                  priv->channels.params.tunneled_offload_en);
3257
3258         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3259 }
3260
3261 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3262                                       enum mlx5e_traffic_types tt,
3263                                       u32 *tirc)
3264 {
3265         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3266         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3267                                        &tirc_default_config[tt], tirc, false);
3268 }
3269
3270 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3271 {
3272         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3273         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3274 }
3275
3276 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3277                                             enum mlx5e_traffic_types tt,
3278                                             u32 *tirc)
3279 {
3280         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3281         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3282                                        &tirc_default_config[tt], tirc, true);
3283 }
3284
3285 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3286 {
3287         struct mlx5e_tir *tir;
3288         void *tirc;
3289         int inlen;
3290         int i = 0;
3291         int err;
3292         u32 *in;
3293         int tt;
3294
3295         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3296         in = kvzalloc(inlen, GFP_KERNEL);
3297         if (!in)
3298                 return -ENOMEM;
3299
3300         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3301                 memset(in, 0, inlen);
3302                 tir = &priv->indir_tir[tt];
3303                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3304                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3305                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3306                 if (err) {
3307                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3308                         goto err_destroy_inner_tirs;
3309                 }
3310         }
3311
3312         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3313                 goto out;
3314
3315         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3316                 memset(in, 0, inlen);
3317                 tir = &priv->inner_indir_tir[i];
3318                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3319                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3320                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3321                 if (err) {
3322                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3323                         goto err_destroy_inner_tirs;
3324                 }
3325         }
3326
3327 out:
3328         kvfree(in);
3329
3330         return 0;
3331
3332 err_destroy_inner_tirs:
3333         for (i--; i >= 0; i--)
3334                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3335
3336         for (tt--; tt >= 0; tt--)
3337                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3338
3339         kvfree(in);
3340
3341         return err;
3342 }
3343
3344 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3345 {
3346         struct mlx5e_tir *tir;
3347         void *tirc;
3348         int inlen;
3349         int err = 0;
3350         u32 *in;
3351         int ix;
3352
3353         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3354         in = kvzalloc(inlen, GFP_KERNEL);
3355         if (!in)
3356                 return -ENOMEM;
3357
3358         for (ix = 0; ix < priv->max_nch; ix++) {
3359                 memset(in, 0, inlen);
3360                 tir = &tirs[ix];
3361                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3362                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3363                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3364                 if (unlikely(err))
3365                         goto err_destroy_ch_tirs;
3366         }
3367
3368         goto out;
3369
3370 err_destroy_ch_tirs:
3371         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3372         for (ix--; ix >= 0; ix--)
3373                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3374
3375 out:
3376         kvfree(in);
3377
3378         return err;
3379 }
3380
3381 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3382 {
3383         int i;
3384
3385         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3386                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3387
3388         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3389                 return;
3390
3391         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3392                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3393 }
3394
3395 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3396 {
3397         int i;
3398
3399         for (i = 0; i < priv->max_nch; i++)
3400                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3401 }
3402
3403 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3404 {
3405         int err = 0;
3406         int i;
3407
3408         for (i = 0; i < chs->num; i++) {
3409                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3410                 if (err)
3411                         return err;
3412         }
3413
3414         return 0;
3415 }
3416
3417 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3418 {
3419         int err = 0;
3420         int i;
3421
3422         for (i = 0; i < chs->num; i++) {
3423                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3424                 if (err)
3425                         return err;
3426         }
3427
3428         return 0;
3429 }
3430
3431 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3432                                  struct tc_mqprio_qopt *mqprio)
3433 {
3434         struct mlx5e_channels new_channels = {};
3435         u8 tc = mqprio->num_tc;
3436         int err = 0;
3437
3438         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3439
3440         if (tc && tc != MLX5E_MAX_NUM_TC)
3441                 return -EINVAL;
3442
3443         mutex_lock(&priv->state_lock);
3444
3445         new_channels.params = priv->channels.params;
3446         new_channels.params.num_tc = tc ? tc : 1;
3447
3448         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3449                 priv->channels.params = new_channels.params;
3450                 goto out;
3451         }
3452
3453         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3454         if (err)
3455                 goto out;
3456
3457         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3458                                     new_channels.params.num_tc);
3459 out:
3460         mutex_unlock(&priv->state_lock);
3461         return err;
3462 }
3463
3464 #ifdef CONFIG_MLX5_ESWITCH
3465 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3466                                      struct flow_cls_offload *cls_flower,
3467                                      unsigned long flags)
3468 {
3469         switch (cls_flower->command) {
3470         case FLOW_CLS_REPLACE:
3471                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3472                                               flags);
3473         case FLOW_CLS_DESTROY:
3474                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3475                                            flags);
3476         case FLOW_CLS_STATS:
3477                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3478                                           flags);
3479         default:
3480                 return -EOPNOTSUPP;
3481         }
3482 }
3483
3484 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3485                                    void *cb_priv)
3486 {
3487         unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3488         struct mlx5e_priv *priv = cb_priv;
3489
3490         switch (type) {
3491         case TC_SETUP_CLSFLOWER:
3492                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3493         default:
3494                 return -EOPNOTSUPP;
3495         }
3496 }
3497 #endif
3498
3499 static LIST_HEAD(mlx5e_block_cb_list);
3500
3501 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3502                           void *type_data)
3503 {
3504         struct mlx5e_priv *priv = netdev_priv(dev);
3505
3506         switch (type) {
3507 #ifdef CONFIG_MLX5_ESWITCH
3508         case TC_SETUP_BLOCK: {
3509                 struct flow_block_offload *f = type_data;
3510
3511                 f->unlocked_driver_cb = true;
3512                 return flow_block_cb_setup_simple(type_data,
3513                                                   &mlx5e_block_cb_list,
3514                                                   mlx5e_setup_tc_block_cb,
3515                                                   priv, priv, true);
3516         }
3517 #endif
3518         case TC_SETUP_QDISC_MQPRIO:
3519                 return mlx5e_setup_tc_mqprio(priv, type_data);
3520         default:
3521                 return -EOPNOTSUPP;
3522         }
3523 }
3524
3525 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3526 {
3527         int i;
3528
3529         for (i = 0; i < priv->max_nch; i++) {
3530                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3531                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3532                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3533                 int j;
3534
3535                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3536                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3537
3538                 for (j = 0; j < priv->max_opened_tc; j++) {
3539                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3540
3541                         s->tx_packets    += sq_stats->packets;
3542                         s->tx_bytes      += sq_stats->bytes;
3543                         s->tx_dropped    += sq_stats->dropped;
3544                 }
3545         }
3546 }
3547
3548 void
3549 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3550 {
3551         struct mlx5e_priv *priv = netdev_priv(dev);
3552         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3553         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3554
3555         if (!mlx5e_monitor_counter_supported(priv)) {
3556                 /* update HW stats in background for next time */
3557                 mlx5e_queue_update_stats(priv);
3558         }
3559
3560         if (mlx5e_is_uplink_rep(priv)) {
3561                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3562                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3563                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3564                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3565         } else {
3566                 mlx5e_fold_sw_stats64(priv, stats);
3567         }
3568
3569         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3570
3571         stats->rx_length_errors =
3572                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3573                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3574                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3575         stats->rx_crc_errors =
3576                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3577         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3578         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3579         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3580                            stats->rx_frame_errors;
3581         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3582
3583         /* vport multicast also counts packets that are dropped due to steering
3584          * or rx out of buffer
3585          */
3586         stats->multicast =
3587                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3588 }
3589
3590 static void mlx5e_set_rx_mode(struct net_device *dev)
3591 {
3592         struct mlx5e_priv *priv = netdev_priv(dev);
3593
3594         queue_work(priv->wq, &priv->set_rx_mode_work);
3595 }
3596
3597 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3598 {
3599         struct mlx5e_priv *priv = netdev_priv(netdev);
3600         struct sockaddr *saddr = addr;
3601
3602         if (!is_valid_ether_addr(saddr->sa_data))
3603                 return -EADDRNOTAVAIL;
3604
3605         netif_addr_lock_bh(netdev);
3606         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3607         netif_addr_unlock_bh(netdev);
3608
3609         queue_work(priv->wq, &priv->set_rx_mode_work);
3610
3611         return 0;
3612 }
3613
3614 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3615         do {                                            \
3616                 if (enable)                             \
3617                         *features |= feature;           \
3618                 else                                    \
3619                         *features &= ~feature;          \
3620         } while (0)
3621
3622 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3623
3624 static int set_feature_lro(struct net_device *netdev, bool enable)
3625 {
3626         struct mlx5e_priv *priv = netdev_priv(netdev);
3627         struct mlx5_core_dev *mdev = priv->mdev;
3628         struct mlx5e_channels new_channels = {};
3629         struct mlx5e_params *old_params;
3630         int err = 0;
3631         bool reset;
3632
3633         mutex_lock(&priv->state_lock);
3634
3635         if (enable && priv->xsk.refcnt) {
3636                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3637                             priv->xsk.refcnt);
3638                 err = -EINVAL;
3639                 goto out;
3640         }
3641
3642         old_params = &priv->channels.params;
3643         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3644                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3645                 err = -EINVAL;
3646                 goto out;
3647         }
3648
3649         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3650
3651         new_channels.params = *old_params;
3652         new_channels.params.lro_en = enable;
3653
3654         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3655                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3656                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3657                         reset = false;
3658         }
3659
3660         if (!reset) {
3661                 *old_params = new_channels.params;
3662                 err = mlx5e_modify_tirs_lro(priv);
3663                 goto out;
3664         }
3665
3666         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3667 out:
3668         mutex_unlock(&priv->state_lock);
3669         return err;
3670 }
3671
3672 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3673 {
3674         struct mlx5e_priv *priv = netdev_priv(netdev);
3675
3676         if (enable)
3677                 mlx5e_enable_cvlan_filter(priv);
3678         else
3679                 mlx5e_disable_cvlan_filter(priv);
3680
3681         return 0;
3682 }
3683
3684 #ifdef CONFIG_MLX5_ESWITCH
3685 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3686 {
3687         struct mlx5e_priv *priv = netdev_priv(netdev);
3688
3689         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3690                 netdev_err(netdev,
3691                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3692                 return -EINVAL;
3693         }
3694
3695         return 0;
3696 }
3697 #endif
3698
3699 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3700 {
3701         struct mlx5e_priv *priv = netdev_priv(netdev);
3702         struct mlx5_core_dev *mdev = priv->mdev;
3703
3704         return mlx5_set_port_fcs(mdev, !enable);
3705 }
3706
3707 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3708 {
3709         struct mlx5e_priv *priv = netdev_priv(netdev);
3710         int err;
3711
3712         mutex_lock(&priv->state_lock);
3713
3714         priv->channels.params.scatter_fcs_en = enable;
3715         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3716         if (err)
3717                 priv->channels.params.scatter_fcs_en = !enable;
3718
3719         mutex_unlock(&priv->state_lock);
3720
3721         return err;
3722 }
3723
3724 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3725 {
3726         struct mlx5e_priv *priv = netdev_priv(netdev);
3727         int err = 0;
3728
3729         mutex_lock(&priv->state_lock);
3730
3731         priv->channels.params.vlan_strip_disable = !enable;
3732         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3733                 goto unlock;
3734
3735         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3736         if (err)
3737                 priv->channels.params.vlan_strip_disable = enable;
3738
3739 unlock:
3740         mutex_unlock(&priv->state_lock);
3741
3742         return err;
3743 }
3744
3745 #ifdef CONFIG_MLX5_EN_ARFS
3746 static int set_feature_arfs(struct net_device *netdev, bool enable)
3747 {
3748         struct mlx5e_priv *priv = netdev_priv(netdev);
3749         int err;
3750
3751         if (enable)
3752                 err = mlx5e_arfs_enable(priv);
3753         else
3754                 err = mlx5e_arfs_disable(priv);
3755
3756         return err;
3757 }
3758 #endif
3759
3760 static int mlx5e_handle_feature(struct net_device *netdev,
3761                                 netdev_features_t *features,
3762                                 netdev_features_t wanted_features,
3763                                 netdev_features_t feature,
3764                                 mlx5e_feature_handler feature_handler)
3765 {
3766         netdev_features_t changes = wanted_features ^ netdev->features;
3767         bool enable = !!(wanted_features & feature);
3768         int err;
3769
3770         if (!(changes & feature))
3771                 return 0;
3772
3773         err = feature_handler(netdev, enable);
3774         if (err) {
3775                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3776                            enable ? "Enable" : "Disable", &feature, err);
3777                 return err;
3778         }
3779
3780         MLX5E_SET_FEATURE(features, feature, enable);
3781         return 0;
3782 }
3783
3784 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3785 {
3786         netdev_features_t oper_features = netdev->features;
3787         int err = 0;
3788
3789 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3790         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3791
3792         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3793         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3794                                     set_feature_cvlan_filter);
3795 #ifdef CONFIG_MLX5_ESWITCH
3796         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3797 #endif
3798         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3799         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3800         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3801 #ifdef CONFIG_MLX5_EN_ARFS
3802         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3803 #endif
3804
3805         if (err) {
3806                 netdev->features = oper_features;
3807                 return -EINVAL;
3808         }
3809
3810         return 0;
3811 }
3812
3813 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3814                                             netdev_features_t features)
3815 {
3816         struct mlx5e_priv *priv = netdev_priv(netdev);
3817         struct mlx5e_params *params;
3818
3819         mutex_lock(&priv->state_lock);
3820         params = &priv->channels.params;
3821         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3822                 /* HW strips the outer C-tag header, this is a problem
3823                  * for S-tag traffic.
3824                  */
3825                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3826                 if (!params->vlan_strip_disable)
3827                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3828         }
3829         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3830                 if (features & NETIF_F_LRO) {
3831                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3832                         features &= ~NETIF_F_LRO;
3833                 }
3834         }
3835
3836         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3837                 features &= ~NETIF_F_RXHASH;
3838                 if (netdev->features & NETIF_F_RXHASH)
3839                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3840         }
3841
3842         mutex_unlock(&priv->state_lock);
3843
3844         return features;
3845 }
3846
3847 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3848                                    struct mlx5e_channels *chs,
3849                                    struct mlx5e_params *new_params,
3850                                    struct mlx5_core_dev *mdev)
3851 {
3852         u16 ix;
3853
3854         for (ix = 0; ix < chs->params.num_channels; ix++) {
3855                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3856                 struct mlx5e_xsk_param xsk;
3857
3858                 if (!umem)
3859                         continue;
3860
3861                 mlx5e_build_xsk_param(umem, &xsk);
3862
3863                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3864                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3865                         int max_mtu_frame, max_mtu_page, max_mtu;
3866
3867                         /* Two criteria must be met:
3868                          * 1. HW MTU + all headrooms <= XSK frame size.
3869                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3870                          */
3871                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3872                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3873                         max_mtu = min(max_mtu_frame, max_mtu_page);
3874
3875                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3876                                    new_params->sw_mtu, ix, max_mtu);
3877                         return false;
3878                 }
3879         }
3880
3881         return true;
3882 }
3883
3884 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3885                      change_hw_mtu_cb set_mtu_cb)
3886 {
3887         struct mlx5e_priv *priv = netdev_priv(netdev);
3888         struct mlx5e_channels new_channels = {};
3889         struct mlx5e_params *params;
3890         int err = 0;
3891         bool reset;
3892
3893         mutex_lock(&priv->state_lock);
3894
3895         params = &priv->channels.params;
3896
3897         reset = !params->lro_en;
3898         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3899
3900         new_channels.params = *params;
3901         new_channels.params.sw_mtu = new_mtu;
3902
3903         if (params->xdp_prog &&
3904             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3905                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3906                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3907                 err = -EINVAL;
3908                 goto out;
3909         }
3910
3911         if (priv->xsk.refcnt &&
3912             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3913                                     &new_channels.params, priv->mdev)) {
3914                 err = -EINVAL;
3915                 goto out;
3916         }
3917
3918         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3919                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3920                                                               &new_channels.params,
3921                                                               NULL);
3922                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3923                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3924
3925                 /* If XSK is active, XSK RQs are linear. */
3926                 is_linear |= priv->xsk.refcnt;
3927
3928                 /* Always reset in linear mode - hw_mtu is used in data path. */
3929                 reset = reset && (is_linear || (ppw_old != ppw_new));
3930         }
3931
3932         if (!reset) {
3933                 params->sw_mtu = new_mtu;
3934                 if (set_mtu_cb)
3935                         set_mtu_cb(priv);
3936                 netdev->mtu = params->sw_mtu;
3937                 goto out;
3938         }
3939
3940         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3941         if (err)
3942                 goto out;
3943
3944         netdev->mtu = new_channels.params.sw_mtu;
3945
3946 out:
3947         mutex_unlock(&priv->state_lock);
3948         return err;
3949 }
3950
3951 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3952 {
3953         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3954 }
3955
3956 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3957 {
3958         struct hwtstamp_config config;
3959         int err;
3960
3961         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3962             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3963                 return -EOPNOTSUPP;
3964
3965         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3966                 return -EFAULT;
3967
3968         /* TX HW timestamp */
3969         switch (config.tx_type) {
3970         case HWTSTAMP_TX_OFF:
3971         case HWTSTAMP_TX_ON:
3972                 break;
3973         default:
3974                 return -ERANGE;
3975         }
3976
3977         mutex_lock(&priv->state_lock);
3978         /* RX HW timestamp */
3979         switch (config.rx_filter) {
3980         case HWTSTAMP_FILTER_NONE:
3981                 /* Reset CQE compression to Admin default */
3982                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3983                 break;
3984         case HWTSTAMP_FILTER_ALL:
3985         case HWTSTAMP_FILTER_SOME:
3986         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3987         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3988         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3989         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3990         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3991         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3992         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3993         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3994         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3995         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3996         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3997         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3998         case HWTSTAMP_FILTER_NTP_ALL:
3999                 /* Disable CQE compression */
4000                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4001                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4002                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4003                 if (err) {
4004                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4005                         mutex_unlock(&priv->state_lock);
4006                         return err;
4007                 }
4008                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4009                 break;
4010         default:
4011                 mutex_unlock(&priv->state_lock);
4012                 return -ERANGE;
4013         }
4014
4015         memcpy(&priv->tstamp, &config, sizeof(config));
4016         mutex_unlock(&priv->state_lock);
4017
4018         /* might need to fix some features */
4019         netdev_update_features(priv->netdev);
4020
4021         return copy_to_user(ifr->ifr_data, &config,
4022                             sizeof(config)) ? -EFAULT : 0;
4023 }
4024
4025 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4026 {
4027         struct hwtstamp_config *cfg = &priv->tstamp;
4028
4029         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4030                 return -EOPNOTSUPP;
4031
4032         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4033 }
4034
4035 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4036 {
4037         struct mlx5e_priv *priv = netdev_priv(dev);
4038
4039         switch (cmd) {
4040         case SIOCSHWTSTAMP:
4041                 return mlx5e_hwstamp_set(priv, ifr);
4042         case SIOCGHWTSTAMP:
4043                 return mlx5e_hwstamp_get(priv, ifr);
4044         default:
4045                 return -EOPNOTSUPP;
4046         }
4047 }
4048
4049 #ifdef CONFIG_MLX5_ESWITCH
4050 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4051 {
4052         struct mlx5e_priv *priv = netdev_priv(dev);
4053         struct mlx5_core_dev *mdev = priv->mdev;
4054
4055         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4056 }
4057
4058 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4059                              __be16 vlan_proto)
4060 {
4061         struct mlx5e_priv *priv = netdev_priv(dev);
4062         struct mlx5_core_dev *mdev = priv->mdev;
4063
4064         if (vlan_proto != htons(ETH_P_8021Q))
4065                 return -EPROTONOSUPPORT;
4066
4067         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4068                                            vlan, qos);
4069 }
4070
4071 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4072 {
4073         struct mlx5e_priv *priv = netdev_priv(dev);
4074         struct mlx5_core_dev *mdev = priv->mdev;
4075
4076         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4077 }
4078
4079 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4080 {
4081         struct mlx5e_priv *priv = netdev_priv(dev);
4082         struct mlx5_core_dev *mdev = priv->mdev;
4083
4084         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4085 }
4086
4087 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4088                       int max_tx_rate)
4089 {
4090         struct mlx5e_priv *priv = netdev_priv(dev);
4091         struct mlx5_core_dev *mdev = priv->mdev;
4092
4093         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4094                                            max_tx_rate, min_tx_rate);
4095 }
4096
4097 static int mlx5_vport_link2ifla(u8 esw_link)
4098 {
4099         switch (esw_link) {
4100         case MLX5_VPORT_ADMIN_STATE_DOWN:
4101                 return IFLA_VF_LINK_STATE_DISABLE;
4102         case MLX5_VPORT_ADMIN_STATE_UP:
4103                 return IFLA_VF_LINK_STATE_ENABLE;
4104         }
4105         return IFLA_VF_LINK_STATE_AUTO;
4106 }
4107
4108 static int mlx5_ifla_link2vport(u8 ifla_link)
4109 {
4110         switch (ifla_link) {
4111         case IFLA_VF_LINK_STATE_DISABLE:
4112                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4113         case IFLA_VF_LINK_STATE_ENABLE:
4114                 return MLX5_VPORT_ADMIN_STATE_UP;
4115         }
4116         return MLX5_VPORT_ADMIN_STATE_AUTO;
4117 }
4118
4119 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4120                                    int link_state)
4121 {
4122         struct mlx5e_priv *priv = netdev_priv(dev);
4123         struct mlx5_core_dev *mdev = priv->mdev;
4124
4125         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4126                                             mlx5_ifla_link2vport(link_state));
4127 }
4128
4129 int mlx5e_get_vf_config(struct net_device *dev,
4130                         int vf, struct ifla_vf_info *ivi)
4131 {
4132         struct mlx5e_priv *priv = netdev_priv(dev);
4133         struct mlx5_core_dev *mdev = priv->mdev;
4134         int err;
4135
4136         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4137         if (err)
4138                 return err;
4139         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4140         return 0;
4141 }
4142
4143 int mlx5e_get_vf_stats(struct net_device *dev,
4144                        int vf, struct ifla_vf_stats *vf_stats)
4145 {
4146         struct mlx5e_priv *priv = netdev_priv(dev);
4147         struct mlx5_core_dev *mdev = priv->mdev;
4148
4149         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4150                                             vf_stats);
4151 }
4152 #endif
4153
4154 struct mlx5e_vxlan_work {
4155         struct work_struct      work;
4156         struct mlx5e_priv       *priv;
4157         u16                     port;
4158 };
4159
4160 static void mlx5e_vxlan_add_work(struct work_struct *work)
4161 {
4162         struct mlx5e_vxlan_work *vxlan_work =
4163                 container_of(work, struct mlx5e_vxlan_work, work);
4164         struct mlx5e_priv *priv = vxlan_work->priv;
4165         u16 port = vxlan_work->port;
4166
4167         mutex_lock(&priv->state_lock);
4168         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4169         mutex_unlock(&priv->state_lock);
4170
4171         kfree(vxlan_work);
4172 }
4173
4174 static void mlx5e_vxlan_del_work(struct work_struct *work)
4175 {
4176         struct mlx5e_vxlan_work *vxlan_work =
4177                 container_of(work, struct mlx5e_vxlan_work, work);
4178         struct mlx5e_priv *priv         = vxlan_work->priv;
4179         u16 port = vxlan_work->port;
4180
4181         mutex_lock(&priv->state_lock);
4182         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4183         mutex_unlock(&priv->state_lock);
4184         kfree(vxlan_work);
4185 }
4186
4187 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4188 {
4189         struct mlx5e_vxlan_work *vxlan_work;
4190
4191         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4192         if (!vxlan_work)
4193                 return;
4194
4195         if (add)
4196                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4197         else
4198                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4199
4200         vxlan_work->priv = priv;
4201         vxlan_work->port = port;
4202         queue_work(priv->wq, &vxlan_work->work);
4203 }
4204
4205 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4206 {
4207         struct mlx5e_priv *priv = netdev_priv(netdev);
4208
4209         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4210                 return;
4211
4212         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4213                 return;
4214
4215         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4216 }
4217
4218 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4219 {
4220         struct mlx5e_priv *priv = netdev_priv(netdev);
4221
4222         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4223                 return;
4224
4225         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4226                 return;
4227
4228         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4229 }
4230
4231 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4232                                                      struct sk_buff *skb,
4233                                                      netdev_features_t features)
4234 {
4235         unsigned int offset = 0;
4236         struct udphdr *udph;
4237         u8 proto;
4238         u16 port;
4239
4240         switch (vlan_get_protocol(skb)) {
4241         case htons(ETH_P_IP):
4242                 proto = ip_hdr(skb)->protocol;
4243                 break;
4244         case htons(ETH_P_IPV6):
4245                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4246                 break;
4247         default:
4248                 goto out;
4249         }
4250
4251         switch (proto) {
4252         case IPPROTO_GRE:
4253                 return features;
4254         case IPPROTO_IPIP:
4255         case IPPROTO_IPV6:
4256                 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4257                         return features;
4258                 break;
4259         case IPPROTO_UDP:
4260                 udph = udp_hdr(skb);
4261                 port = be16_to_cpu(udph->dest);
4262
4263                 /* Verify if UDP port is being offloaded by HW */
4264                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4265                         return features;
4266
4267 #if IS_ENABLED(CONFIG_GENEVE)
4268                 /* Support Geneve offload for default UDP port */
4269                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4270                         return features;
4271 #endif
4272         }
4273
4274 out:
4275         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4276         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4277 }
4278
4279 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4280                                        struct net_device *netdev,
4281                                        netdev_features_t features)
4282 {
4283         struct mlx5e_priv *priv = netdev_priv(netdev);
4284
4285         features = vlan_features_check(skb, features);
4286         features = vxlan_features_check(skb, features);
4287
4288 #ifdef CONFIG_MLX5_EN_IPSEC
4289         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4290                 return features;
4291 #endif
4292
4293         /* Validate if the tunneled packet is being offloaded by HW */
4294         if (skb->encapsulation &&
4295             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4296                 return mlx5e_tunnel_features_check(priv, skb, features);
4297
4298         return features;
4299 }
4300
4301 static void mlx5e_tx_timeout_work(struct work_struct *work)
4302 {
4303         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4304                                                tx_timeout_work);
4305         bool report_failed = false;
4306         int err;
4307         int i;
4308
4309         rtnl_lock();
4310         mutex_lock(&priv->state_lock);
4311
4312         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4313                 goto unlock;
4314
4315         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4316                 struct netdev_queue *dev_queue =
4317                         netdev_get_tx_queue(priv->netdev, i);
4318                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4319
4320                 if (!netif_xmit_stopped(dev_queue))
4321                         continue;
4322
4323                 if (mlx5e_reporter_tx_timeout(sq))
4324                         report_failed = true;
4325         }
4326
4327         if (!report_failed)
4328                 goto unlock;
4329
4330         err = mlx5e_safe_reopen_channels(priv);
4331         if (err)
4332                 netdev_err(priv->netdev,
4333                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4334                            err);
4335
4336 unlock:
4337         mutex_unlock(&priv->state_lock);
4338         rtnl_unlock();
4339 }
4340
4341 static void mlx5e_tx_timeout(struct net_device *dev)
4342 {
4343         struct mlx5e_priv *priv = netdev_priv(dev);
4344
4345         netdev_err(dev, "TX timeout detected\n");
4346         queue_work(priv->wq, &priv->tx_timeout_work);
4347 }
4348
4349 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4350 {
4351         struct net_device *netdev = priv->netdev;
4352         struct mlx5e_channels new_channels = {};
4353
4354         if (priv->channels.params.lro_en) {
4355                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4356                 return -EINVAL;
4357         }
4358
4359         if (MLX5_IPSEC_DEV(priv->mdev)) {
4360                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4361                 return -EINVAL;
4362         }
4363
4364         new_channels.params = priv->channels.params;
4365         new_channels.params.xdp_prog = prog;
4366
4367         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4368          * the XDP program.
4369          */
4370         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4371                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4372                             new_channels.params.sw_mtu,
4373                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4374                 return -EINVAL;
4375         }
4376
4377         return 0;
4378 }
4379
4380 static int mlx5e_xdp_update_state(struct mlx5e_priv *priv)
4381 {
4382         if (priv->channels.params.xdp_prog)
4383                 mlx5e_xdp_set_open(priv);
4384         else
4385                 mlx5e_xdp_set_closed(priv);
4386
4387         return 0;
4388 }
4389
4390 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4391 {
4392         struct mlx5e_priv *priv = netdev_priv(netdev);
4393         struct bpf_prog *old_prog;
4394         bool reset, was_opened;
4395         int err = 0;
4396         int i;
4397
4398         mutex_lock(&priv->state_lock);
4399
4400         if (prog) {
4401                 err = mlx5e_xdp_allowed(priv, prog);
4402                 if (err)
4403                         goto unlock;
4404         }
4405
4406         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4407         /* no need for full reset when exchanging programs */
4408         reset = (!priv->channels.params.xdp_prog || !prog);
4409
4410         if (was_opened && !reset)
4411                 /* num_channels is invariant here, so we can take the
4412                  * batched reference right upfront.
4413                  */
4414                 bpf_prog_add(prog, priv->channels.num);
4415
4416         if (was_opened && reset) {
4417                 struct mlx5e_channels new_channels = {};
4418
4419                 new_channels.params = priv->channels.params;
4420                 new_channels.params.xdp_prog = prog;
4421                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4422                 old_prog = priv->channels.params.xdp_prog;
4423
4424                 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_xdp_update_state);
4425                 if (err)
4426                         goto unlock;
4427         } else {
4428                 /* exchange programs, extra prog reference we got from caller
4429                  * as long as we don't fail from this point onwards.
4430                  */
4431                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4432         }
4433
4434         if (old_prog)
4435                 bpf_prog_put(old_prog);
4436
4437         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4438                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4439
4440         if (!was_opened || reset)
4441                 goto unlock;
4442
4443         /* exchanging programs w/o reset, we update ref counts on behalf
4444          * of the channels RQs here.
4445          */
4446         for (i = 0; i < priv->channels.num; i++) {
4447                 struct mlx5e_channel *c = priv->channels.c[i];
4448                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4449
4450                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4451                 if (xsk_open)
4452                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4453                 napi_synchronize(&c->napi);
4454                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4455
4456                 old_prog = xchg(&c->rq.xdp_prog, prog);
4457                 if (old_prog)
4458                         bpf_prog_put(old_prog);
4459
4460                 if (xsk_open) {
4461                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4462                         if (old_prog)
4463                                 bpf_prog_put(old_prog);
4464                 }
4465
4466                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4467                 if (xsk_open)
4468                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4469                 /* napi_schedule in case we have missed anything */
4470                 napi_schedule(&c->napi);
4471         }
4472
4473 unlock:
4474         mutex_unlock(&priv->state_lock);
4475         return err;
4476 }
4477
4478 static u32 mlx5e_xdp_query(struct net_device *dev)
4479 {
4480         struct mlx5e_priv *priv = netdev_priv(dev);
4481         const struct bpf_prog *xdp_prog;
4482         u32 prog_id = 0;
4483
4484         mutex_lock(&priv->state_lock);
4485         xdp_prog = priv->channels.params.xdp_prog;
4486         if (xdp_prog)
4487                 prog_id = xdp_prog->aux->id;
4488         mutex_unlock(&priv->state_lock);
4489
4490         return prog_id;
4491 }
4492
4493 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4494 {
4495         switch (xdp->command) {
4496         case XDP_SETUP_PROG:
4497                 return mlx5e_xdp_set(dev, xdp->prog);
4498         case XDP_QUERY_PROG:
4499                 xdp->prog_id = mlx5e_xdp_query(dev);
4500                 return 0;
4501         case XDP_SETUP_XSK_UMEM:
4502                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4503                                             xdp->xsk.queue_id);
4504         default:
4505                 return -EINVAL;
4506         }
4507 }
4508
4509 #ifdef CONFIG_MLX5_ESWITCH
4510 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4511                                 struct net_device *dev, u32 filter_mask,
4512                                 int nlflags)
4513 {
4514         struct mlx5e_priv *priv = netdev_priv(dev);
4515         struct mlx5_core_dev *mdev = priv->mdev;
4516         u8 mode, setting;
4517         int err;
4518
4519         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4520         if (err)
4521                 return err;
4522         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4523         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4524                                        mode,
4525                                        0, 0, nlflags, filter_mask, NULL);
4526 }
4527
4528 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4529                                 u16 flags, struct netlink_ext_ack *extack)
4530 {
4531         struct mlx5e_priv *priv = netdev_priv(dev);
4532         struct mlx5_core_dev *mdev = priv->mdev;
4533         struct nlattr *attr, *br_spec;
4534         u16 mode = BRIDGE_MODE_UNDEF;
4535         u8 setting;
4536         int rem;
4537
4538         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4539         if (!br_spec)
4540                 return -EINVAL;
4541
4542         nla_for_each_nested(attr, br_spec, rem) {
4543                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4544                         continue;
4545
4546                 if (nla_len(attr) < sizeof(mode))
4547                         return -EINVAL;
4548
4549                 mode = nla_get_u16(attr);
4550                 if (mode > BRIDGE_MODE_VEPA)
4551                         return -EINVAL;
4552
4553                 break;
4554         }
4555
4556         if (mode == BRIDGE_MODE_UNDEF)
4557                 return -EINVAL;
4558
4559         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4560         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4561 }
4562 #endif
4563
4564 const struct net_device_ops mlx5e_netdev_ops = {
4565         .ndo_open                = mlx5e_open,
4566         .ndo_stop                = mlx5e_close,
4567         .ndo_start_xmit          = mlx5e_xmit,
4568         .ndo_setup_tc            = mlx5e_setup_tc,
4569         .ndo_select_queue        = mlx5e_select_queue,
4570         .ndo_get_stats64         = mlx5e_get_stats,
4571         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4572         .ndo_set_mac_address     = mlx5e_set_mac,
4573         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4574         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4575         .ndo_set_features        = mlx5e_set_features,
4576         .ndo_fix_features        = mlx5e_fix_features,
4577         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4578         .ndo_do_ioctl            = mlx5e_ioctl,
4579         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4580         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4581         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4582         .ndo_features_check      = mlx5e_features_check,
4583         .ndo_tx_timeout          = mlx5e_tx_timeout,
4584         .ndo_bpf                 = mlx5e_xdp,
4585         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4586         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4587 #ifdef CONFIG_MLX5_EN_ARFS
4588         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4589 #endif
4590 #ifdef CONFIG_MLX5_ESWITCH
4591         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4592         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4593
4594         /* SRIOV E-Switch NDOs */
4595         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4596         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4597         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4598         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4599         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4600         .ndo_get_vf_config       = mlx5e_get_vf_config,
4601         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4602         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4603 #endif
4604 };
4605
4606 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4607 {
4608         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4609                 return -EOPNOTSUPP;
4610         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4611             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4612             !MLX5_CAP_ETH(mdev, csum_cap) ||
4613             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4614             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4615             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4616             MLX5_CAP_FLOWTABLE(mdev,
4617                                flow_table_properties_nic_receive.max_ft_level)
4618                                < 3) {
4619                 mlx5_core_warn(mdev,
4620                                "Not creating net device, some required device capabilities are missing\n");
4621                 return -EOPNOTSUPP;
4622         }
4623         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4624                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4625         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4626                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4627
4628         return 0;
4629 }
4630
4631 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4632                                    int num_channels)
4633 {
4634         int i;
4635
4636         for (i = 0; i < len; i++)
4637                 indirection_rqt[i] = i % num_channels;
4638 }
4639
4640 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4641 {
4642         u32 link_speed = 0;
4643         u32 pci_bw = 0;
4644
4645         mlx5e_port_max_linkspeed(mdev, &link_speed);
4646         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4647         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4648                            link_speed, pci_bw);
4649
4650 #define MLX5E_SLOW_PCI_RATIO (2)
4651
4652         return link_speed && pci_bw &&
4653                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4654 }
4655
4656 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4657 {
4658         struct dim_cq_moder moder;
4659
4660         moder.cq_period_mode = cq_period_mode;
4661         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4662         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4663         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4664                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4665
4666         return moder;
4667 }
4668
4669 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4670 {
4671         struct dim_cq_moder moder;
4672
4673         moder.cq_period_mode = cq_period_mode;
4674         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4675         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4676         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4677                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4678
4679         return moder;
4680 }
4681
4682 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4683 {
4684         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4685                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4686                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4687 }
4688
4689 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4690 {
4691         if (params->tx_dim_enabled) {
4692                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4693
4694                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4695         } else {
4696                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4697         }
4698
4699         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4700                         params->tx_cq_moderation.cq_period_mode ==
4701                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4702 }
4703
4704 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4705 {
4706         if (params->rx_dim_enabled) {
4707                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4708
4709                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4710         } else {
4711                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4712         }
4713
4714         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4715                         params->rx_cq_moderation.cq_period_mode ==
4716                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4717 }
4718
4719 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4720 {
4721         int i;
4722
4723         /* The supported periods are organized in ascending order */
4724         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4725                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4726                         break;
4727
4728         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4729 }
4730
4731 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4732                            struct mlx5e_params *params)
4733 {
4734         /* Prefer Striding RQ, unless any of the following holds:
4735          * - Striding RQ configuration is not possible/supported.
4736          * - Slow PCI heuristic.
4737          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4738          *
4739          * No XSK params: checking the availability of striding RQ in general.
4740          */
4741         if (!slow_pci_heuristic(mdev) &&
4742             mlx5e_striding_rq_possible(mdev, params) &&
4743             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4744              !mlx5e_rx_is_linear_skb(params, NULL)))
4745                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4746         mlx5e_set_rq_type(mdev, params);
4747         mlx5e_init_rq_type_params(mdev, params);
4748 }
4749
4750 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4751                             u16 num_channels)
4752 {
4753         enum mlx5e_traffic_types tt;
4754
4755         rss_params->hfunc = ETH_RSS_HASH_TOP;
4756         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4757                             sizeof(rss_params->toeplitz_hash_key));
4758         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4759                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4760         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4761                 rss_params->rx_hash_fields[tt] =
4762                         tirc_default_config[tt].rx_hash_fields;
4763 }
4764
4765 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4766                             struct mlx5e_xsk *xsk,
4767                             struct mlx5e_rss_params *rss_params,
4768                             struct mlx5e_params *params,
4769                             u16 max_channels, u16 mtu)
4770 {
4771         u8 rx_cq_period_mode;
4772
4773         params->sw_mtu = mtu;
4774         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4775         params->num_channels = max_channels;
4776         params->num_tc       = 1;
4777
4778         /* SQ */
4779         params->log_sq_size = is_kdump_kernel() ?
4780                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4781                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4782
4783         /* XDP SQ */
4784         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4785                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4786
4787         /* set CQE compression */
4788         params->rx_cqe_compress_def = false;
4789         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4790             MLX5_CAP_GEN(mdev, vport_group_manager))
4791                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4792
4793         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4794         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4795
4796         /* RQ */
4797         mlx5e_build_rq_params(mdev, params);
4798
4799         /* HW LRO */
4800
4801         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4802         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4803                 /* No XSK params: checking the availability of striding RQ in general. */
4804                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4805                         params->lro_en = !slow_pci_heuristic(mdev);
4806         }
4807         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4808
4809         /* CQ moderation params */
4810         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4811                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4812                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4813         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4814         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4815         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4816         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4817
4818         /* TX inline */
4819         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4820
4821         /* RSS */
4822         mlx5e_build_rss_params(rss_params, params->num_channels);
4823         params->tunneled_offload_en =
4824                 mlx5e_tunnel_inner_ft_supported(mdev);
4825
4826         /* AF_XDP */
4827         params->xsk = xsk;
4828 }
4829
4830 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4831 {
4832         struct mlx5e_priv *priv = netdev_priv(netdev);
4833
4834         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4835         if (is_zero_ether_addr(netdev->dev_addr) &&
4836             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4837                 eth_hw_addr_random(netdev);
4838                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4839         }
4840 }
4841
4842 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4843 {
4844         struct mlx5e_priv *priv = netdev_priv(netdev);
4845         struct mlx5_core_dev *mdev = priv->mdev;
4846         bool fcs_supported;
4847         bool fcs_enabled;
4848
4849         SET_NETDEV_DEV(netdev, mdev->device);
4850
4851         netdev->netdev_ops = &mlx5e_netdev_ops;
4852
4853 #ifdef CONFIG_MLX5_CORE_EN_DCB
4854         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4855                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4856 #endif
4857
4858         netdev->watchdog_timeo    = 15 * HZ;
4859
4860         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4861
4862         netdev->vlan_features    |= NETIF_F_SG;
4863         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4864         netdev->vlan_features    |= NETIF_F_GRO;
4865         netdev->vlan_features    |= NETIF_F_TSO;
4866         netdev->vlan_features    |= NETIF_F_TSO6;
4867         netdev->vlan_features    |= NETIF_F_RXCSUM;
4868         netdev->vlan_features    |= NETIF_F_RXHASH;
4869
4870         netdev->mpls_features    |= NETIF_F_SG;
4871         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4872         netdev->mpls_features    |= NETIF_F_TSO;
4873         netdev->mpls_features    |= NETIF_F_TSO6;
4874
4875         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4876         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4877
4878         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4879             mlx5e_check_fragmented_striding_rq_cap(mdev))
4880                 netdev->vlan_features    |= NETIF_F_LRO;
4881
4882         netdev->hw_features       = netdev->vlan_features;
4883         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4884         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4885         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4886         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4887
4888         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4889             mlx5e_any_tunnel_proto_supported(mdev)) {
4890                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4891                 netdev->hw_enc_features |= NETIF_F_TSO;
4892                 netdev->hw_enc_features |= NETIF_F_TSO6;
4893                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4894         }
4895
4896         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4897                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4898                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4899                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4900                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4901                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4902         }
4903
4904         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4905                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4906                                            NETIF_F_GSO_GRE_CSUM;
4907                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4908                                            NETIF_F_GSO_GRE_CSUM;
4909                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4910                                                 NETIF_F_GSO_GRE_CSUM;
4911         }
4912
4913         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4914                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4915                                        NETIF_F_GSO_IPXIP6;
4916                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4917                                            NETIF_F_GSO_IPXIP6;
4918                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4919                                                 NETIF_F_GSO_IPXIP6;
4920         }
4921
4922         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4923         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4924         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4925         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4926
4927         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4928
4929         if (fcs_supported)
4930                 netdev->hw_features |= NETIF_F_RXALL;
4931
4932         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4933                 netdev->hw_features |= NETIF_F_RXFCS;
4934
4935         netdev->features          = netdev->hw_features;
4936         if (!priv->channels.params.lro_en)
4937                 netdev->features  &= ~NETIF_F_LRO;
4938
4939         if (fcs_enabled)
4940                 netdev->features  &= ~NETIF_F_RXALL;
4941
4942         if (!priv->channels.params.scatter_fcs_en)
4943                 netdev->features  &= ~NETIF_F_RXFCS;
4944
4945         /* prefere CQE compression over rxhash */
4946         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4947                 netdev->features &= ~NETIF_F_RXHASH;
4948
4949 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4950         if (FT_CAP(flow_modify_en) &&
4951             FT_CAP(modify_root) &&
4952             FT_CAP(identified_miss_table_mode) &&
4953             FT_CAP(flow_table_modify)) {
4954 #ifdef CONFIG_MLX5_ESWITCH
4955                 netdev->hw_features      |= NETIF_F_HW_TC;
4956 #endif
4957 #ifdef CONFIG_MLX5_EN_ARFS
4958                 netdev->hw_features      |= NETIF_F_NTUPLE;
4959 #endif
4960         }
4961
4962         netdev->features         |= NETIF_F_HIGHDMA;
4963         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4964
4965         netdev->priv_flags       |= IFF_UNICAST_FLT;
4966
4967         mlx5e_set_netdev_dev_addr(netdev);
4968         mlx5e_ipsec_build_netdev(priv);
4969         mlx5e_tls_build_netdev(priv);
4970 }
4971
4972 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4973 {
4974         struct mlx5_core_dev *mdev = priv->mdev;
4975         int err;
4976
4977         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4978         if (err) {
4979                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4980                 priv->q_counter = 0;
4981         }
4982
4983         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4984         if (err) {
4985                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4986                 priv->drop_rq_q_counter = 0;
4987         }
4988 }
4989
4990 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4991 {
4992         if (priv->q_counter)
4993                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4994
4995         if (priv->drop_rq_q_counter)
4996                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4997 }
4998
4999 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5000                           struct net_device *netdev,
5001                           const struct mlx5e_profile *profile,
5002                           void *ppriv)
5003 {
5004         struct mlx5e_priv *priv = netdev_priv(netdev);
5005         struct mlx5e_rss_params *rss = &priv->rss_params;
5006         int err;
5007
5008         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5009         if (err)
5010                 return err;
5011
5012         mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
5013                                priv->max_nch, netdev->mtu);
5014
5015         mlx5e_timestamp_init(priv);
5016
5017         err = mlx5e_ipsec_init(priv);
5018         if (err)
5019                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5020         err = mlx5e_tls_init(priv);
5021         if (err)
5022                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5023         mlx5e_build_nic_netdev(netdev);
5024         mlx5e_build_tc2txq_maps(priv);
5025         mlx5e_health_create_reporters(priv);
5026
5027         return 0;
5028 }
5029
5030 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5031 {
5032         mlx5e_health_destroy_reporters(priv);
5033         mlx5e_tls_cleanup(priv);
5034         mlx5e_ipsec_cleanup(priv);
5035         mlx5e_netdev_cleanup(priv->netdev, priv);
5036 }
5037
5038 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5039 {
5040         struct mlx5_core_dev *mdev = priv->mdev;
5041         int err;
5042
5043         mlx5e_create_q_counters(priv);
5044
5045         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5046         if (err) {
5047                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5048                 goto err_destroy_q_counters;
5049         }
5050
5051         err = mlx5e_create_indirect_rqt(priv);
5052         if (err)
5053                 goto err_close_drop_rq;
5054
5055         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5056         if (err)
5057                 goto err_destroy_indirect_rqts;
5058
5059         err = mlx5e_create_indirect_tirs(priv, true);
5060         if (err)
5061                 goto err_destroy_direct_rqts;
5062
5063         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5064         if (err)
5065                 goto err_destroy_indirect_tirs;
5066
5067         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5068         if (unlikely(err))
5069                 goto err_destroy_direct_tirs;
5070
5071         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5072         if (unlikely(err))
5073                 goto err_destroy_xsk_rqts;
5074
5075         err = mlx5e_create_flow_steering(priv);
5076         if (err) {
5077                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5078                 goto err_destroy_xsk_tirs;
5079         }
5080
5081         err = mlx5e_tc_nic_init(priv);
5082         if (err)
5083                 goto err_destroy_flow_steering;
5084
5085         return 0;
5086
5087 err_destroy_flow_steering:
5088         mlx5e_destroy_flow_steering(priv);
5089 err_destroy_xsk_tirs:
5090         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5091 err_destroy_xsk_rqts:
5092         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5093 err_destroy_direct_tirs:
5094         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5095 err_destroy_indirect_tirs:
5096         mlx5e_destroy_indirect_tirs(priv, true);
5097 err_destroy_direct_rqts:
5098         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5099 err_destroy_indirect_rqts:
5100         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5101 err_close_drop_rq:
5102         mlx5e_close_drop_rq(&priv->drop_rq);
5103 err_destroy_q_counters:
5104         mlx5e_destroy_q_counters(priv);
5105         return err;
5106 }
5107
5108 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5109 {
5110         mlx5e_tc_nic_cleanup(priv);
5111         mlx5e_destroy_flow_steering(priv);
5112         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5113         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5114         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5115         mlx5e_destroy_indirect_tirs(priv, true);
5116         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5117         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5118         mlx5e_close_drop_rq(&priv->drop_rq);
5119         mlx5e_destroy_q_counters(priv);
5120 }
5121
5122 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5123 {
5124         int err;
5125
5126         err = mlx5e_create_tises(priv);
5127         if (err) {
5128                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5129                 return err;
5130         }
5131
5132 #ifdef CONFIG_MLX5_CORE_EN_DCB
5133         mlx5e_dcbnl_initialize(priv);
5134 #endif
5135         return 0;
5136 }
5137
5138 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5139 {
5140         struct net_device *netdev = priv->netdev;
5141         struct mlx5_core_dev *mdev = priv->mdev;
5142
5143         mlx5e_init_l2_addr(priv);
5144
5145         /* Marking the link as currently not needed by the Driver */
5146         if (!netif_running(netdev))
5147                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5148
5149         mlx5e_set_netdev_mtu_boundaries(priv);
5150         mlx5e_set_dev_port_mtu(priv);
5151
5152         mlx5_lag_add(mdev, netdev);
5153
5154         mlx5e_enable_async_events(priv);
5155         if (mlx5e_monitor_counter_supported(priv))
5156                 mlx5e_monitor_counter_init(priv);
5157
5158         mlx5e_hv_vhca_stats_create(priv);
5159         if (netdev->reg_state != NETREG_REGISTERED)
5160                 return;
5161 #ifdef CONFIG_MLX5_CORE_EN_DCB
5162         mlx5e_dcbnl_init_app(priv);
5163 #endif
5164
5165         queue_work(priv->wq, &priv->set_rx_mode_work);
5166
5167         rtnl_lock();
5168         if (netif_running(netdev))
5169                 mlx5e_open(netdev);
5170         netif_device_attach(netdev);
5171         rtnl_unlock();
5172 }
5173
5174 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5175 {
5176         struct mlx5_core_dev *mdev = priv->mdev;
5177
5178 #ifdef CONFIG_MLX5_CORE_EN_DCB
5179         if (priv->netdev->reg_state == NETREG_REGISTERED)
5180                 mlx5e_dcbnl_delete_app(priv);
5181 #endif
5182
5183         rtnl_lock();
5184         if (netif_running(priv->netdev))
5185                 mlx5e_close(priv->netdev);
5186         netif_device_detach(priv->netdev);
5187         rtnl_unlock();
5188
5189         queue_work(priv->wq, &priv->set_rx_mode_work);
5190
5191         mlx5e_hv_vhca_stats_destroy(priv);
5192         if (mlx5e_monitor_counter_supported(priv))
5193                 mlx5e_monitor_counter_cleanup(priv);
5194
5195         mlx5e_disable_async_events(priv);
5196         mlx5_lag_remove(mdev);
5197 }
5198
5199 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5200 {
5201         return mlx5e_refresh_tirs(priv, false);
5202 }
5203
5204 static const struct mlx5e_profile mlx5e_nic_profile = {
5205         .init              = mlx5e_nic_init,
5206         .cleanup           = mlx5e_nic_cleanup,
5207         .init_rx           = mlx5e_init_nic_rx,
5208         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5209         .init_tx           = mlx5e_init_nic_tx,
5210         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5211         .enable            = mlx5e_nic_enable,
5212         .disable           = mlx5e_nic_disable,
5213         .update_rx         = mlx5e_update_nic_rx,
5214         .update_stats      = mlx5e_update_ndo_stats,
5215         .update_carrier    = mlx5e_update_carrier,
5216         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5217         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5218         .max_tc            = MLX5E_MAX_NUM_TC,
5219         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5220 };
5221
5222 /* mlx5e generic netdev management API (move to en_common.c) */
5223
5224 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5225 int mlx5e_netdev_init(struct net_device *netdev,
5226                       struct mlx5e_priv *priv,
5227                       struct mlx5_core_dev *mdev,
5228                       const struct mlx5e_profile *profile,
5229                       void *ppriv)
5230 {
5231         /* priv init */
5232         priv->mdev        = mdev;
5233         priv->netdev      = netdev;
5234         priv->profile     = profile;
5235         priv->ppriv       = ppriv;
5236         priv->msglevel    = MLX5E_MSG_LEVEL;
5237         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5238         priv->max_opened_tc = 1;
5239
5240         mutex_init(&priv->state_lock);
5241         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5242         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5243         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5244         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5245
5246         priv->wq = create_singlethread_workqueue("mlx5e");
5247         if (!priv->wq)
5248                 return -ENOMEM;
5249
5250         /* netdev init */
5251         netif_carrier_off(netdev);
5252
5253 #ifdef CONFIG_MLX5_EN_ARFS
5254         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5255 #endif
5256
5257         return 0;
5258 }
5259
5260 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5261 {
5262         destroy_workqueue(priv->wq);
5263 }
5264
5265 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5266                                        const struct mlx5e_profile *profile,
5267                                        int nch,
5268                                        void *ppriv)
5269 {
5270         struct net_device *netdev;
5271         int err;
5272
5273         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5274                                     nch * profile->max_tc,
5275                                     nch * profile->rq_groups);
5276         if (!netdev) {
5277                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5278                 return NULL;
5279         }
5280
5281         err = profile->init(mdev, netdev, profile, ppriv);
5282         if (err) {
5283                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5284                 goto err_free_netdev;
5285         }
5286
5287         return netdev;
5288
5289 err_free_netdev:
5290         free_netdev(netdev);
5291
5292         return NULL;
5293 }
5294
5295 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5296 {
5297         const struct mlx5e_profile *profile;
5298         int max_nch;
5299         int err;
5300
5301         profile = priv->profile;
5302         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5303
5304         /* max number of channels may have changed */
5305         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5306         if (priv->channels.params.num_channels > max_nch) {
5307                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5308                 priv->channels.params.num_channels = max_nch;
5309                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5310                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5311         }
5312
5313         err = profile->init_tx(priv);
5314         if (err)
5315                 goto out;
5316
5317         err = profile->init_rx(priv);
5318         if (err)
5319                 goto err_cleanup_tx;
5320
5321         if (profile->enable)
5322                 profile->enable(priv);
5323
5324         return 0;
5325
5326 err_cleanup_tx:
5327         profile->cleanup_tx(priv);
5328
5329 out:
5330         return err;
5331 }
5332
5333 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5334 {
5335         const struct mlx5e_profile *profile = priv->profile;
5336
5337         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5338
5339         if (profile->disable)
5340                 profile->disable(priv);
5341         flush_workqueue(priv->wq);
5342
5343         profile->cleanup_rx(priv);
5344         profile->cleanup_tx(priv);
5345         cancel_work_sync(&priv->update_stats_work);
5346 }
5347
5348 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5349 {
5350         const struct mlx5e_profile *profile = priv->profile;
5351         struct net_device *netdev = priv->netdev;
5352
5353         if (profile->cleanup)
5354                 profile->cleanup(priv);
5355         free_netdev(netdev);
5356 }
5357
5358 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5359  * hardware contexts and to connect it to the current netdev.
5360  */
5361 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5362 {
5363         struct mlx5e_priv *priv = vpriv;
5364         struct net_device *netdev = priv->netdev;
5365         int err;
5366
5367         if (netif_device_present(netdev))
5368                 return 0;
5369
5370         err = mlx5e_create_mdev_resources(mdev);
5371         if (err)
5372                 return err;
5373
5374         err = mlx5e_attach_netdev(priv);
5375         if (err) {
5376                 mlx5e_destroy_mdev_resources(mdev);
5377                 return err;
5378         }
5379
5380         return 0;
5381 }
5382
5383 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5384 {
5385         struct mlx5e_priv *priv = vpriv;
5386         struct net_device *netdev = priv->netdev;
5387
5388 #ifdef CONFIG_MLX5_ESWITCH
5389         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5390                 return;
5391 #endif
5392
5393         if (!netif_device_present(netdev))
5394                 return;
5395
5396         mlx5e_detach_netdev(priv);
5397         mlx5e_destroy_mdev_resources(mdev);
5398 }
5399
5400 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5401 {
5402         struct net_device *netdev;
5403         void *priv;
5404         int err;
5405         int nch;
5406
5407         err = mlx5e_check_required_hca_cap(mdev);
5408         if (err)
5409                 return NULL;
5410
5411 #ifdef CONFIG_MLX5_ESWITCH
5412         if (MLX5_ESWITCH_MANAGER(mdev) &&
5413             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5414                 mlx5e_rep_register_vport_reps(mdev);
5415                 return mdev;
5416         }
5417 #endif
5418
5419         nch = mlx5e_get_max_num_channels(mdev);
5420         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5421         if (!netdev) {
5422                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5423                 return NULL;
5424         }
5425
5426         dev_net_set(netdev, mlx5_core_net(mdev));
5427         priv = netdev_priv(netdev);
5428
5429         err = mlx5e_attach(mdev, priv);
5430         if (err) {
5431                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5432                 goto err_destroy_netdev;
5433         }
5434
5435         err = register_netdev(netdev);
5436         if (err) {
5437                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5438                 goto err_detach;
5439         }
5440
5441 #ifdef CONFIG_MLX5_CORE_EN_DCB
5442         mlx5e_dcbnl_init_app(priv);
5443 #endif
5444         return priv;
5445
5446 err_detach:
5447         mlx5e_detach(mdev, priv);
5448 err_destroy_netdev:
5449         mlx5e_destroy_netdev(priv);
5450         return NULL;
5451 }
5452
5453 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5454 {
5455         struct mlx5e_priv *priv;
5456
5457 #ifdef CONFIG_MLX5_ESWITCH
5458         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5459                 mlx5e_rep_unregister_vport_reps(mdev);
5460                 return;
5461         }
5462 #endif
5463         priv = vpriv;
5464 #ifdef CONFIG_MLX5_CORE_EN_DCB
5465         mlx5e_dcbnl_delete_app(priv);
5466 #endif
5467         unregister_netdev(priv->netdev);
5468         mlx5e_detach(mdev, vpriv);
5469         mlx5e_destroy_netdev(priv);
5470 }
5471
5472 static struct mlx5_interface mlx5e_interface = {
5473         .add       = mlx5e_add,
5474         .remove    = mlx5e_remove,
5475         .attach    = mlx5e_attach,
5476         .detach    = mlx5e_detach,
5477         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5478 };
5479
5480 void mlx5e_init(void)
5481 {
5482         mlx5e_ipsec_build_inverse_table();
5483         mlx5e_build_ptys2ethtool_map();
5484         mlx5_register_interface(&mlx5e_interface);
5485 }
5486
5487 void mlx5e_cleanup(void)
5488 {
5489         mlx5_unregister_interface(&mlx5e_interface);
5490 }