2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
43 MLX5_EN_QP_FLUSH_TIMEOUT_MS = 5000,
44 MLX5_EN_QP_FLUSH_MSLEEP_QUANT = 20,
45 MLX5_EN_QP_FLUSH_MAX_ITER = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
46 MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
49 struct mlx5e_rq_param {
50 u32 rqc[MLX5_ST_SZ_DW(rqc)];
51 struct mlx5_wq_param wq;
54 struct mlx5e_sq_param {
55 u32 sqc[MLX5_ST_SZ_DW(sqc)];
56 struct mlx5_wq_param wq;
61 struct mlx5e_cq_param {
62 u32 cqc[MLX5_ST_SZ_DW(cqc)];
63 struct mlx5_wq_param wq;
67 struct mlx5e_channel_param {
68 struct mlx5e_rq_param rq;
69 struct mlx5e_sq_param sq;
70 struct mlx5e_sq_param icosq;
71 struct mlx5e_cq_param rx_cq;
72 struct mlx5e_cq_param tx_cq;
73 struct mlx5e_cq_param icosq_cq;
76 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
78 struct mlx5_core_dev *mdev = priv->mdev;
81 port_state = mlx5_query_vport_state(mdev,
82 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
84 if (port_state == VPORT_STATE_UP) {
85 netdev_info(priv->netdev, "Link up\n");
86 netif_carrier_on(priv->netdev);
88 netdev_info(priv->netdev, "Link down\n");
89 netif_carrier_off(priv->netdev);
93 static void mlx5e_update_carrier_work(struct work_struct *work)
95 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
98 mutex_lock(&priv->state_lock);
99 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
100 mlx5e_update_carrier(priv);
101 mutex_unlock(&priv->state_lock);
104 static void mlx5e_tx_timeout_work(struct work_struct *work)
106 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
111 mutex_lock(&priv->state_lock);
112 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
114 mlx5e_close_locked(priv->netdev);
115 err = mlx5e_open_locked(priv->netdev);
117 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
120 mutex_unlock(&priv->state_lock);
124 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
126 struct mlx5e_sw_stats *s = &priv->stats.sw;
127 struct mlx5e_rq_stats *rq_stats;
128 struct mlx5e_sq_stats *sq_stats;
129 u64 tx_offload_none = 0;
132 memset(s, 0, sizeof(*s));
133 for (i = 0; i < priv->params.num_channels; i++) {
134 rq_stats = &priv->channel[i]->rq.stats;
136 s->rx_packets += rq_stats->packets;
137 s->rx_bytes += rq_stats->bytes;
138 s->rx_lro_packets += rq_stats->lro_packets;
139 s->rx_lro_bytes += rq_stats->lro_bytes;
140 s->rx_csum_none += rq_stats->csum_none;
141 s->rx_csum_complete += rq_stats->csum_complete;
142 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
143 s->rx_wqe_err += rq_stats->wqe_err;
144 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
145 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
146 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
147 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
148 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
150 for (j = 0; j < priv->params.num_tc; j++) {
151 sq_stats = &priv->channel[i]->sq[j].stats;
153 s->tx_packets += sq_stats->packets;
154 s->tx_bytes += sq_stats->bytes;
155 s->tx_tso_packets += sq_stats->tso_packets;
156 s->tx_tso_bytes += sq_stats->tso_bytes;
157 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
158 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
159 s->tx_queue_stopped += sq_stats->stopped;
160 s->tx_queue_wake += sq_stats->wake;
161 s->tx_queue_dropped += sq_stats->dropped;
162 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
163 tx_offload_none += sq_stats->csum_none;
167 /* Update calculated offload counters */
168 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
169 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
171 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
172 priv->stats.pport.phy_counters,
173 counter_set.phys_layer_cntrs.link_down_events);
176 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
178 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
179 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
180 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
181 struct mlx5_core_dev *mdev = priv->mdev;
183 memset(in, 0, sizeof(in));
185 MLX5_SET(query_vport_counter_in, in, opcode,
186 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
187 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
188 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
190 memset(out, 0, outlen);
192 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
195 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
197 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
198 struct mlx5_core_dev *mdev = priv->mdev;
199 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
204 in = mlx5_vzalloc(sz);
208 MLX5_SET(ppcnt_reg, in, local_port, 1);
210 out = pstats->IEEE_802_3_counters;
211 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
212 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
214 out = pstats->RFC_2863_counters;
215 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
216 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
218 out = pstats->RFC_2819_counters;
219 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
220 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
222 out = pstats->phy_counters;
223 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
224 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
226 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
227 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
228 out = pstats->per_prio_counters[prio];
229 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
230 mlx5_core_access_reg(mdev, in, sz, out, sz,
231 MLX5_REG_PPCNT, 0, 0);
238 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
240 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
242 if (!priv->q_counter)
245 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
246 &qcnt->rx_out_of_buffer);
249 void mlx5e_update_stats(struct mlx5e_priv *priv)
251 mlx5e_update_q_counter(priv);
252 mlx5e_update_vport_counters(priv);
253 mlx5e_update_pport_counters(priv);
254 mlx5e_update_sw_counters(priv);
257 static void mlx5e_update_stats_work(struct work_struct *work)
259 struct delayed_work *dwork = to_delayed_work(work);
260 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
262 mutex_lock(&priv->state_lock);
263 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
264 mlx5e_update_stats(priv);
265 queue_delayed_work(priv->wq, dwork,
266 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
268 mutex_unlock(&priv->state_lock);
271 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
272 enum mlx5_dev_event event, unsigned long param)
274 struct mlx5e_priv *priv = vpriv;
276 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
280 case MLX5_DEV_EVENT_PORT_UP:
281 case MLX5_DEV_EVENT_PORT_DOWN:
282 queue_work(priv->wq, &priv->update_carrier_work);
290 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
292 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
295 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
297 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
298 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
301 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
302 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
304 static int mlx5e_create_rq(struct mlx5e_channel *c,
305 struct mlx5e_rq_param *param,
308 struct mlx5e_priv *priv = c->priv;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 void *rqc = param->rqc;
311 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
317 param->wq.db_numa_node = cpu_to_node(c->cpu);
319 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
324 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
326 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
328 switch (priv->params.rq_wq_type) {
329 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
330 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
331 GFP_KERNEL, cpu_to_node(c->cpu));
334 goto err_rq_wq_destroy;
336 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
337 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
338 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
340 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
341 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
342 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
343 byte_count = rq->wqe_sz;
345 default: /* MLX5_WQ_TYPE_LINKED_LIST */
346 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
347 cpu_to_node(c->cpu));
350 goto err_rq_wq_destroy;
352 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
353 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
354 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
356 rq->wqe_sz = (priv->params.lro_en) ?
357 priv->params.lro_wqe_sz :
358 MLX5E_SW2HW_MTU(priv->netdev->mtu);
359 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
360 byte_count = rq->wqe_sz;
361 byte_count |= MLX5_HW_START_PADDING;
364 for (i = 0; i < wq_sz; i++) {
365 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
367 wqe->data.byte_count = cpu_to_be32(byte_count);
370 rq->wq_type = priv->params.rq_wq_type;
372 rq->netdev = c->netdev;
373 rq->tstamp = &priv->tstamp;
377 rq->mkey_be = c->mkey_be;
378 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
383 mlx5_wq_destroy(&rq->wq_ctrl);
388 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
390 switch (rq->wq_type) {
391 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
394 default: /* MLX5_WQ_TYPE_LINKED_LIST */
398 mlx5_wq_destroy(&rq->wq_ctrl);
401 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
403 struct mlx5e_priv *priv = rq->priv;
404 struct mlx5_core_dev *mdev = priv->mdev;
412 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
413 sizeof(u64) * rq->wq_ctrl.buf.npages;
414 in = mlx5_vzalloc(inlen);
418 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
419 wq = MLX5_ADDR_OF(rqc, rqc, wq);
421 memcpy(rqc, param->rqc, sizeof(param->rqc));
423 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
424 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
425 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
426 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
427 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
428 MLX5_ADAPTER_PAGE_SHIFT);
429 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
431 mlx5_fill_page_array(&rq->wq_ctrl.buf,
432 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
434 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
441 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
444 struct mlx5e_channel *c = rq->channel;
445 struct mlx5e_priv *priv = c->priv;
446 struct mlx5_core_dev *mdev = priv->mdev;
453 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
454 in = mlx5_vzalloc(inlen);
458 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
460 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
461 MLX5_SET(rqc, rqc, state, next_state);
463 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
470 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
472 struct mlx5e_channel *c = rq->channel;
473 struct mlx5e_priv *priv = c->priv;
474 struct mlx5_core_dev *mdev = priv->mdev;
481 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
482 in = mlx5_vzalloc(inlen);
486 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
488 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
489 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
490 MLX5_SET(rqc, rqc, vsd, vsd);
491 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
493 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
500 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
502 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
505 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
507 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
508 struct mlx5e_channel *c = rq->channel;
509 struct mlx5e_priv *priv = c->priv;
510 struct mlx5_wq_ll *wq = &rq->wq;
512 while (time_before(jiffies, exp_time)) {
513 if (wq->cur_sz >= priv->params.min_rx_wqes)
522 static int mlx5e_open_rq(struct mlx5e_channel *c,
523 struct mlx5e_rq_param *param,
526 struct mlx5e_sq *sq = &c->icosq;
527 u16 pi = sq->pc & sq->wq.sz_m1;
530 err = mlx5e_create_rq(c, param, rq);
534 err = mlx5e_enable_rq(rq, param);
538 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
542 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
544 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
545 sq->ico_wqe_info[pi].num_wqebbs = 1;
546 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
551 mlx5e_disable_rq(rq);
553 mlx5e_destroy_rq(rq);
558 static void mlx5e_close_rq(struct mlx5e_rq *rq)
563 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
564 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
566 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
567 while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
568 tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
569 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
571 if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
572 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
574 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
575 napi_synchronize(&rq->channel->napi);
577 mlx5e_disable_rq(rq);
578 mlx5e_free_rx_descs(rq);
579 mlx5e_destroy_rq(rq);
582 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
589 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
591 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
592 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
594 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
595 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
597 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
600 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
601 mlx5e_free_sq_db(sq);
605 sq->dma_fifo_mask = df_sz - 1;
610 static int mlx5e_create_sq(struct mlx5e_channel *c,
612 struct mlx5e_sq_param *param,
615 struct mlx5e_priv *priv = c->priv;
616 struct mlx5_core_dev *mdev = priv->mdev;
618 void *sqc = param->sqc;
619 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
622 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
626 param->wq.db_numa_node = cpu_to_node(c->cpu);
628 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
631 goto err_unmap_free_uar;
633 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
634 if (sq->uar.bf_map) {
635 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
636 sq->uar_map = sq->uar.bf_map;
638 sq->uar_map = sq->uar.map;
640 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
641 sq->max_inline = param->max_inline;
643 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
645 goto err_sq_wq_destroy;
648 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
650 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
653 cpu_to_node(c->cpu));
654 if (!sq->ico_wqe_info) {
661 txq_ix = c->ix + tc * priv->params.num_channels;
662 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
663 priv->txq_to_sq_map[txq_ix] = sq;
667 sq->tstamp = &priv->tstamp;
668 sq->mkey_be = c->mkey_be;
671 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
672 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
677 mlx5e_free_sq_db(sq);
680 mlx5_wq_destroy(&sq->wq_ctrl);
683 mlx5_unmap_free_uar(mdev, &sq->uar);
688 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
690 struct mlx5e_channel *c = sq->channel;
691 struct mlx5e_priv *priv = c->priv;
693 kfree(sq->ico_wqe_info);
694 mlx5e_free_sq_db(sq);
695 mlx5_wq_destroy(&sq->wq_ctrl);
696 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
699 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
701 struct mlx5e_channel *c = sq->channel;
702 struct mlx5e_priv *priv = c->priv;
703 struct mlx5_core_dev *mdev = priv->mdev;
711 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
712 sizeof(u64) * sq->wq_ctrl.buf.npages;
713 in = mlx5_vzalloc(inlen);
717 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
718 wq = MLX5_ADDR_OF(sqc, sqc, wq);
720 memcpy(sqc, param->sqc, sizeof(param->sqc));
722 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
723 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
724 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
725 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
726 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
728 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
729 MLX5_SET(wq, wq, uar_page, sq->uar.index);
730 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
731 MLX5_ADAPTER_PAGE_SHIFT);
732 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
734 mlx5_fill_page_array(&sq->wq_ctrl.buf,
735 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
737 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
744 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
746 struct mlx5e_channel *c = sq->channel;
747 struct mlx5e_priv *priv = c->priv;
748 struct mlx5_core_dev *mdev = priv->mdev;
755 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
756 in = mlx5_vzalloc(inlen);
760 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
762 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
763 MLX5_SET(sqc, sqc, state, next_state);
765 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
772 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
774 struct mlx5e_channel *c = sq->channel;
775 struct mlx5e_priv *priv = c->priv;
776 struct mlx5_core_dev *mdev = priv->mdev;
778 mlx5_core_destroy_sq(mdev, sq->sqn);
781 static int mlx5e_open_sq(struct mlx5e_channel *c,
783 struct mlx5e_sq_param *param,
788 err = mlx5e_create_sq(c, tc, param, sq);
792 err = mlx5e_enable_sq(sq, param);
796 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
801 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
802 netdev_tx_reset_queue(sq->txq);
803 netif_tx_start_queue(sq->txq);
809 mlx5e_disable_sq(sq);
811 mlx5e_destroy_sq(sq);
816 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
818 __netif_tx_lock_bh(txq);
819 netif_tx_stop_queue(txq);
820 __netif_tx_unlock_bh(txq);
823 static void mlx5e_close_sq(struct mlx5e_sq *sq)
829 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
830 /* prevent netif_tx_wake_queue */
831 napi_synchronize(&sq->channel->napi);
832 netif_tx_disable_queue(sq->txq);
834 /* ensure hw is notified of all pending wqes */
835 if (mlx5e_sq_has_room_for(sq, 1))
836 mlx5e_send_nop(sq, true);
838 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
841 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
844 /* wait till sq is empty, unless a TX timeout occurred on this SQ */
845 while (sq->cc != sq->pc &&
846 !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
847 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
848 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
849 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
852 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
853 napi_synchronize(&sq->channel->napi);
855 mlx5e_free_tx_descs(sq);
856 mlx5e_disable_sq(sq);
857 mlx5e_destroy_sq(sq);
860 static int mlx5e_create_cq(struct mlx5e_channel *c,
861 struct mlx5e_cq_param *param,
864 struct mlx5e_priv *priv = c->priv;
865 struct mlx5_core_dev *mdev = priv->mdev;
866 struct mlx5_core_cq *mcq = &cq->mcq;
872 param->wq.buf_numa_node = cpu_to_node(c->cpu);
873 param->wq.db_numa_node = cpu_to_node(c->cpu);
874 param->eq_ix = c->ix;
876 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
881 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
886 mcq->set_ci_db = cq->wq_ctrl.db.db;
887 mcq->arm_db = cq->wq_ctrl.db.db + 1;
890 mcq->vector = param->eq_ix;
891 mcq->comp = mlx5e_completion_event;
892 mcq->event = mlx5e_cq_error_event;
894 mcq->uar = &priv->cq_uar;
896 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
897 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
908 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
910 mlx5_wq_destroy(&cq->wq_ctrl);
913 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
915 struct mlx5e_priv *priv = cq->priv;
916 struct mlx5_core_dev *mdev = priv->mdev;
917 struct mlx5_core_cq *mcq = &cq->mcq;
922 unsigned int irqn_not_used;
926 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
927 sizeof(u64) * cq->wq_ctrl.buf.npages;
928 in = mlx5_vzalloc(inlen);
932 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
934 memcpy(cqc, param->cqc, sizeof(param->cqc));
936 mlx5_fill_page_array(&cq->wq_ctrl.buf,
937 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
939 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
941 MLX5_SET(cqc, cqc, c_eqn, eqn);
942 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
943 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
944 MLX5_ADAPTER_PAGE_SHIFT);
945 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
947 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
959 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
961 struct mlx5e_priv *priv = cq->priv;
962 struct mlx5_core_dev *mdev = priv->mdev;
964 mlx5_core_destroy_cq(mdev, &cq->mcq);
967 static int mlx5e_open_cq(struct mlx5e_channel *c,
968 struct mlx5e_cq_param *param,
970 u16 moderation_usecs,
971 u16 moderation_frames)
974 struct mlx5e_priv *priv = c->priv;
975 struct mlx5_core_dev *mdev = priv->mdev;
977 err = mlx5e_create_cq(c, param, cq);
981 err = mlx5e_enable_cq(cq, param);
985 if (MLX5_CAP_GEN(mdev, cq_moderation))
986 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
992 mlx5e_destroy_cq(cq);
997 static void mlx5e_close_cq(struct mlx5e_cq *cq)
999 mlx5e_disable_cq(cq);
1000 mlx5e_destroy_cq(cq);
1003 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1005 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1008 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1009 struct mlx5e_channel_param *cparam)
1011 struct mlx5e_priv *priv = c->priv;
1015 for (tc = 0; tc < c->num_tc; tc++) {
1016 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1017 priv->params.tx_cq_moderation_usec,
1018 priv->params.tx_cq_moderation_pkts);
1020 goto err_close_tx_cqs;
1026 for (tc--; tc >= 0; tc--)
1027 mlx5e_close_cq(&c->sq[tc].cq);
1032 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1036 for (tc = 0; tc < c->num_tc; tc++)
1037 mlx5e_close_cq(&c->sq[tc].cq);
1040 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1041 struct mlx5e_channel_param *cparam)
1046 for (tc = 0; tc < c->num_tc; tc++) {
1047 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1055 for (tc--; tc >= 0; tc--)
1056 mlx5e_close_sq(&c->sq[tc]);
1061 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1065 for (tc = 0; tc < c->num_tc; tc++)
1066 mlx5e_close_sq(&c->sq[tc]);
1069 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1073 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1074 priv->channeltc_to_txq_map[ix][i] =
1075 ix + i * priv->params.num_channels;
1078 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1079 struct mlx5e_channel_param *cparam,
1080 struct mlx5e_channel **cp)
1082 struct net_device *netdev = priv->netdev;
1083 int cpu = mlx5e_get_cpu(priv, ix);
1084 struct mlx5e_channel *c;
1087 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1094 c->pdev = &priv->mdev->pdev->dev;
1095 c->netdev = priv->netdev;
1096 c->mkey_be = cpu_to_be32(priv->mkey.key);
1097 c->num_tc = priv->params.num_tc;
1099 mlx5e_build_channeltc_to_txq_map(priv, ix);
1101 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1103 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1107 err = mlx5e_open_tx_cqs(c, cparam);
1109 goto err_close_icosq_cq;
1111 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1112 priv->params.rx_cq_moderation_usec,
1113 priv->params.rx_cq_moderation_pkts);
1115 goto err_close_tx_cqs;
1117 napi_enable(&c->napi);
1119 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1121 goto err_disable_napi;
1123 err = mlx5e_open_sqs(c, cparam);
1125 goto err_close_icosq;
1127 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1131 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1140 mlx5e_close_sq(&c->icosq);
1143 napi_disable(&c->napi);
1144 mlx5e_close_cq(&c->rq.cq);
1147 mlx5e_close_tx_cqs(c);
1150 mlx5e_close_cq(&c->icosq.cq);
1153 netif_napi_del(&c->napi);
1154 napi_hash_del(&c->napi);
1160 static void mlx5e_close_channel(struct mlx5e_channel *c)
1162 mlx5e_close_rq(&c->rq);
1164 mlx5e_close_sq(&c->icosq);
1165 napi_disable(&c->napi);
1166 mlx5e_close_cq(&c->rq.cq);
1167 mlx5e_close_tx_cqs(c);
1168 mlx5e_close_cq(&c->icosq.cq);
1169 netif_napi_del(&c->napi);
1171 napi_hash_del(&c->napi);
1177 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1178 struct mlx5e_rq_param *param)
1180 void *rqc = param->rqc;
1181 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1183 switch (priv->params.rq_wq_type) {
1184 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1185 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1186 priv->params.mpwqe_log_num_strides - 9);
1187 MLX5_SET(wq, wq, log_wqe_stride_size,
1188 priv->params.mpwqe_log_stride_sz - 6);
1189 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1191 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1192 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1195 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1196 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1197 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1198 MLX5_SET(wq, wq, pd, priv->pdn);
1199 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1201 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1202 param->wq.linear = 1;
1205 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1207 void *rqc = param->rqc;
1208 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1210 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1211 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1214 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1215 struct mlx5e_sq_param *param)
1217 void *sqc = param->sqc;
1218 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1220 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1221 MLX5_SET(wq, wq, pd, priv->pdn);
1223 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1226 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1227 struct mlx5e_sq_param *param)
1229 void *sqc = param->sqc;
1230 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1232 mlx5e_build_sq_param_common(priv, param);
1233 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1235 param->max_inline = priv->params.tx_max_inline;
1238 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1239 struct mlx5e_cq_param *param)
1241 void *cqc = param->cqc;
1243 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1246 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1247 struct mlx5e_cq_param *param)
1249 void *cqc = param->cqc;
1252 switch (priv->params.rq_wq_type) {
1253 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1254 log_cq_size = priv->params.log_rq_size +
1255 priv->params.mpwqe_log_num_strides;
1257 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1258 log_cq_size = priv->params.log_rq_size;
1261 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1262 if (priv->params.rx_cqe_compress) {
1263 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1264 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1267 mlx5e_build_common_cq_param(priv, param);
1270 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1271 struct mlx5e_cq_param *param)
1273 void *cqc = param->cqc;
1275 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1277 mlx5e_build_common_cq_param(priv, param);
1280 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1281 struct mlx5e_cq_param *param,
1284 void *cqc = param->cqc;
1286 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1288 mlx5e_build_common_cq_param(priv, param);
1291 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1292 struct mlx5e_sq_param *param,
1295 void *sqc = param->sqc;
1296 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1298 mlx5e_build_sq_param_common(priv, param);
1300 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1301 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1303 param->icosq = true;
1306 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1308 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1310 mlx5e_build_rq_param(priv, &cparam->rq);
1311 mlx5e_build_sq_param(priv, &cparam->sq);
1312 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1313 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1314 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1315 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1318 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1320 struct mlx5e_channel_param *cparam;
1321 int nch = priv->params.num_channels;
1326 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1329 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1330 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1332 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1334 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1335 goto err_free_txq_to_sq_map;
1337 mlx5e_build_channel_param(priv, cparam);
1339 for (i = 0; i < nch; i++) {
1340 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1342 goto err_close_channels;
1345 for (j = 0; j < nch; j++) {
1346 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1348 goto err_close_channels;
1355 for (i--; i >= 0; i--)
1356 mlx5e_close_channel(priv->channel[i]);
1358 err_free_txq_to_sq_map:
1359 kfree(priv->txq_to_sq_map);
1360 kfree(priv->channel);
1366 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1370 for (i = 0; i < priv->params.num_channels; i++)
1371 mlx5e_close_channel(priv->channel[i]);
1373 kfree(priv->txq_to_sq_map);
1374 kfree(priv->channel);
1377 static int mlx5e_rx_hash_fn(int hfunc)
1379 return (hfunc == ETH_RSS_HASH_TOP) ?
1380 MLX5_RX_HASH_FN_TOEPLITZ :
1381 MLX5_RX_HASH_FN_INVERTED_XOR8;
1384 static int mlx5e_bits_invert(unsigned long a, int size)
1389 for (i = 0; i < size; i++)
1390 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1395 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1399 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1403 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1404 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1406 ix = priv->params.indirection_rqt[ix];
1407 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1408 priv->channel[ix]->rq.rqn :
1410 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1414 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1417 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1418 priv->channel[ix]->rq.rqn :
1421 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1424 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1426 struct mlx5_core_dev *mdev = priv->mdev;
1432 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1433 in = mlx5_vzalloc(inlen);
1437 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1439 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1440 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1442 if (sz > 1) /* RSS */
1443 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1445 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1447 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1453 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1455 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1458 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1460 int nch = mlx5e_get_max_num_channels(priv->mdev);
1466 rqtn = &priv->indir_rqtn;
1467 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1472 for (ix = 0; ix < nch; ix++) {
1473 rqtn = &priv->direct_tir[ix].rqtn;
1474 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1476 goto err_destroy_rqts;
1482 for (ix--; ix >= 0; ix--)
1483 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1485 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1490 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1492 int nch = mlx5e_get_max_num_channels(priv->mdev);
1495 for (i = 0; i < nch; i++)
1496 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1498 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1501 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1503 struct mlx5_core_dev *mdev = priv->mdev;
1509 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1510 in = mlx5_vzalloc(inlen);
1514 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1516 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1517 if (sz > 1) /* RSS */
1518 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1520 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1522 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1524 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1531 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1536 rqtn = priv->indir_rqtn;
1537 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1538 for (ix = 0; ix < priv->params.num_channels; ix++) {
1539 rqtn = priv->direct_tir[ix].rqtn;
1540 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1544 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1546 if (!priv->params.lro_en)
1549 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1551 MLX5_SET(tirc, tirc, lro_enable_mask,
1552 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1553 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1554 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1555 (priv->params.lro_wqe_sz -
1556 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1557 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1558 MLX5_CAP_ETH(priv->mdev,
1559 lro_timer_supported_periods[2]));
1562 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1564 MLX5_SET(tirc, tirc, rx_hash_fn,
1565 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1566 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1567 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1568 rx_hash_toeplitz_key);
1569 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1570 rx_hash_toeplitz_key);
1572 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1573 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1577 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1579 struct mlx5_core_dev *mdev = priv->mdev;
1588 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1589 in = mlx5_vzalloc(inlen);
1593 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1594 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1596 mlx5e_build_tir_ctx_lro(tirc, priv);
1598 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1599 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1605 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1606 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1618 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1625 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1626 in = mlx5_vzalloc(inlen);
1630 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1632 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1633 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1639 for (i = 0; i < priv->params.num_channels; i++) {
1640 err = mlx5_core_modify_tir(priv->mdev,
1641 priv->direct_tir[i].tirn, in,
1652 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1654 struct mlx5_core_dev *mdev = priv->mdev;
1655 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1658 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1662 /* Update vport context MTU */
1663 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1667 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1669 struct mlx5_core_dev *mdev = priv->mdev;
1673 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1674 if (err || !hw_mtu) /* fallback to port oper mtu */
1675 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1677 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1680 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1682 struct mlx5e_priv *priv = netdev_priv(netdev);
1686 err = mlx5e_set_mtu(priv, netdev->mtu);
1690 mlx5e_query_mtu(priv, &mtu);
1691 if (mtu != netdev->mtu)
1692 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1693 __func__, mtu, netdev->mtu);
1699 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1701 struct mlx5e_priv *priv = netdev_priv(netdev);
1702 int nch = priv->params.num_channels;
1703 int ntc = priv->params.num_tc;
1706 netdev_reset_tc(netdev);
1711 netdev_set_num_tc(netdev, ntc);
1713 /* Map netdev TCs to offset 0
1714 * We have our own UP to TXQ mapping for QoS
1716 for (tc = 0; tc < ntc; tc++)
1717 netdev_set_tc_queue(netdev, tc, nch, 0);
1720 int mlx5e_open_locked(struct net_device *netdev)
1722 struct mlx5e_priv *priv = netdev_priv(netdev);
1726 set_bit(MLX5E_STATE_OPENED, &priv->state);
1728 mlx5e_netdev_set_tcs(netdev);
1730 num_txqs = priv->params.num_channels * priv->params.num_tc;
1731 netif_set_real_num_tx_queues(netdev, num_txqs);
1732 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1734 err = mlx5e_set_dev_port_mtu(netdev);
1736 goto err_clear_state_opened_flag;
1738 err = mlx5e_open_channels(priv);
1740 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1742 goto err_clear_state_opened_flag;
1745 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1747 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1749 goto err_close_channels;
1752 mlx5e_redirect_rqts(priv);
1753 mlx5e_update_carrier(priv);
1754 mlx5e_timestamp_init(priv);
1755 #ifdef CONFIG_RFS_ACCEL
1756 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1759 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1764 mlx5e_close_channels(priv);
1765 err_clear_state_opened_flag:
1766 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1770 static int mlx5e_open(struct net_device *netdev)
1772 struct mlx5e_priv *priv = netdev_priv(netdev);
1775 mutex_lock(&priv->state_lock);
1776 err = mlx5e_open_locked(netdev);
1777 mutex_unlock(&priv->state_lock);
1782 int mlx5e_close_locked(struct net_device *netdev)
1784 struct mlx5e_priv *priv = netdev_priv(netdev);
1786 /* May already be CLOSED in case a previous configuration operation
1787 * (e.g RX/TX queue size change) that involves close&open failed.
1789 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1792 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1794 mlx5e_timestamp_cleanup(priv);
1795 netif_carrier_off(priv->netdev);
1796 mlx5e_redirect_rqts(priv);
1797 mlx5e_close_channels(priv);
1802 static int mlx5e_close(struct net_device *netdev)
1804 struct mlx5e_priv *priv = netdev_priv(netdev);
1807 mutex_lock(&priv->state_lock);
1808 err = mlx5e_close_locked(netdev);
1809 mutex_unlock(&priv->state_lock);
1814 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1815 struct mlx5e_rq *rq,
1816 struct mlx5e_rq_param *param)
1818 struct mlx5_core_dev *mdev = priv->mdev;
1819 void *rqc = param->rqc;
1820 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1823 param->wq.db_numa_node = param->wq.buf_numa_node;
1825 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1835 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1836 struct mlx5e_cq *cq,
1837 struct mlx5e_cq_param *param)
1839 struct mlx5_core_dev *mdev = priv->mdev;
1840 struct mlx5_core_cq *mcq = &cq->mcq;
1845 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1850 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1853 mcq->set_ci_db = cq->wq_ctrl.db.db;
1854 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1855 *mcq->set_ci_db = 0;
1857 mcq->vector = param->eq_ix;
1858 mcq->comp = mlx5e_completion_event;
1859 mcq->event = mlx5e_cq_error_event;
1861 mcq->uar = &priv->cq_uar;
1868 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1870 struct mlx5e_cq_param cq_param;
1871 struct mlx5e_rq_param rq_param;
1872 struct mlx5e_rq *rq = &priv->drop_rq;
1873 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1876 memset(&cq_param, 0, sizeof(cq_param));
1877 memset(&rq_param, 0, sizeof(rq_param));
1878 mlx5e_build_drop_rq_param(&rq_param);
1880 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1884 err = mlx5e_enable_cq(cq, &cq_param);
1886 goto err_destroy_cq;
1888 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1890 goto err_disable_cq;
1892 err = mlx5e_enable_rq(rq, &rq_param);
1894 goto err_destroy_rq;
1899 mlx5e_destroy_rq(&priv->drop_rq);
1902 mlx5e_disable_cq(&priv->drop_rq.cq);
1905 mlx5e_destroy_cq(&priv->drop_rq.cq);
1910 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1912 mlx5e_disable_rq(&priv->drop_rq);
1913 mlx5e_destroy_rq(&priv->drop_rq);
1914 mlx5e_disable_cq(&priv->drop_rq.cq);
1915 mlx5e_destroy_cq(&priv->drop_rq.cq);
1918 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1920 struct mlx5_core_dev *mdev = priv->mdev;
1921 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1922 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1924 memset(in, 0, sizeof(in));
1926 MLX5_SET(tisc, tisc, prio, tc << 1);
1927 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1929 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1932 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1934 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1937 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1942 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1943 err = mlx5e_create_tis(priv, tc);
1945 goto err_close_tises;
1951 for (tc--; tc >= 0; tc--)
1952 mlx5e_destroy_tis(priv, tc);
1957 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1961 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1962 mlx5e_destroy_tis(priv, tc);
1965 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1966 enum mlx5e_traffic_types tt)
1968 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1970 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1972 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1973 MLX5_HASH_FIELD_SEL_DST_IP)
1975 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1976 MLX5_HASH_FIELD_SEL_DST_IP |\
1977 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1978 MLX5_HASH_FIELD_SEL_L4_DPORT)
1980 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1981 MLX5_HASH_FIELD_SEL_DST_IP |\
1982 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1984 mlx5e_build_tir_ctx_lro(tirc, priv);
1986 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1987 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1988 mlx5e_build_tir_ctx_hash(tirc, priv);
1991 case MLX5E_TT_IPV4_TCP:
1992 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1993 MLX5_L3_PROT_TYPE_IPV4);
1994 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1995 MLX5_L4_PROT_TYPE_TCP);
1996 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1997 MLX5_HASH_IP_L4PORTS);
2000 case MLX5E_TT_IPV6_TCP:
2001 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2002 MLX5_L3_PROT_TYPE_IPV6);
2003 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2004 MLX5_L4_PROT_TYPE_TCP);
2005 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2006 MLX5_HASH_IP_L4PORTS);
2009 case MLX5E_TT_IPV4_UDP:
2010 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2011 MLX5_L3_PROT_TYPE_IPV4);
2012 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2013 MLX5_L4_PROT_TYPE_UDP);
2014 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2015 MLX5_HASH_IP_L4PORTS);
2018 case MLX5E_TT_IPV6_UDP:
2019 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2020 MLX5_L3_PROT_TYPE_IPV6);
2021 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2022 MLX5_L4_PROT_TYPE_UDP);
2023 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2024 MLX5_HASH_IP_L4PORTS);
2027 case MLX5E_TT_IPV4_IPSEC_AH:
2028 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2029 MLX5_L3_PROT_TYPE_IPV4);
2030 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2031 MLX5_HASH_IP_IPSEC_SPI);
2034 case MLX5E_TT_IPV6_IPSEC_AH:
2035 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2036 MLX5_L3_PROT_TYPE_IPV6);
2037 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2038 MLX5_HASH_IP_IPSEC_SPI);
2041 case MLX5E_TT_IPV4_IPSEC_ESP:
2042 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2043 MLX5_L3_PROT_TYPE_IPV4);
2044 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2045 MLX5_HASH_IP_IPSEC_SPI);
2048 case MLX5E_TT_IPV6_IPSEC_ESP:
2049 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2050 MLX5_L3_PROT_TYPE_IPV6);
2051 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2052 MLX5_HASH_IP_IPSEC_SPI);
2056 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2057 MLX5_L3_PROT_TYPE_IPV4);
2058 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2063 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2064 MLX5_L3_PROT_TYPE_IPV6);
2065 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2070 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2074 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2077 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2079 mlx5e_build_tir_ctx_lro(tirc, priv);
2081 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2082 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2083 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2086 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2088 int nch = mlx5e_get_max_num_channels(priv->mdev);
2097 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2098 in = mlx5_vzalloc(inlen);
2103 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2104 memset(in, 0, inlen);
2105 tirn = &priv->indir_tirn[tt];
2106 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2107 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2108 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2110 goto err_destroy_tirs;
2114 for (ix = 0; ix < nch; ix++) {
2115 memset(in, 0, inlen);
2116 tirn = &priv->direct_tir[ix].tirn;
2117 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2118 mlx5e_build_direct_tir_ctx(priv, tirc,
2119 priv->direct_tir[ix].rqtn);
2120 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2122 goto err_destroy_ch_tirs;
2129 err_destroy_ch_tirs:
2130 for (ix--; ix >= 0; ix--)
2131 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2134 for (tt--; tt >= 0; tt--)
2135 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2142 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2144 int nch = mlx5e_get_max_num_channels(priv->mdev);
2147 for (i = 0; i < nch; i++)
2148 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2150 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2151 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2154 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2159 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2162 for (i = 0; i < priv->params.num_channels; i++) {
2163 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2171 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2173 struct mlx5e_priv *priv = netdev_priv(netdev);
2177 if (tc && tc != MLX5E_MAX_NUM_TC)
2180 mutex_lock(&priv->state_lock);
2182 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2184 mlx5e_close_locked(priv->netdev);
2186 priv->params.num_tc = tc ? tc : 1;
2189 err = mlx5e_open_locked(priv->netdev);
2191 mutex_unlock(&priv->state_lock);
2196 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2197 __be16 proto, struct tc_to_netdev *tc)
2199 struct mlx5e_priv *priv = netdev_priv(dev);
2201 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2205 case TC_SETUP_CLSFLOWER:
2206 switch (tc->cls_flower->command) {
2207 case TC_CLSFLOWER_REPLACE:
2208 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2209 case TC_CLSFLOWER_DESTROY:
2210 return mlx5e_delete_flower(priv, tc->cls_flower);
2211 case TC_CLSFLOWER_STATS:
2212 return mlx5e_stats_flower(priv, tc->cls_flower);
2219 if (tc->type != TC_SETUP_MQPRIO)
2222 return mlx5e_setup_tc(dev, tc->tc);
2225 static struct rtnl_link_stats64 *
2226 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2228 struct mlx5e_priv *priv = netdev_priv(dev);
2229 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2230 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2231 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2233 stats->rx_packets = sstats->rx_packets;
2234 stats->rx_bytes = sstats->rx_bytes;
2235 stats->tx_packets = sstats->tx_packets;
2236 stats->tx_bytes = sstats->tx_bytes;
2238 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2239 stats->tx_dropped = sstats->tx_queue_dropped;
2241 stats->rx_length_errors =
2242 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2243 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2244 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2245 stats->rx_crc_errors =
2246 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2247 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2248 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2249 stats->tx_carrier_errors =
2250 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2251 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2252 stats->rx_frame_errors;
2253 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2255 /* vport multicast also counts packets that are dropped due to steering
2256 * or rx out of buffer
2259 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2264 static void mlx5e_set_rx_mode(struct net_device *dev)
2266 struct mlx5e_priv *priv = netdev_priv(dev);
2268 queue_work(priv->wq, &priv->set_rx_mode_work);
2271 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2273 struct mlx5e_priv *priv = netdev_priv(netdev);
2274 struct sockaddr *saddr = addr;
2276 if (!is_valid_ether_addr(saddr->sa_data))
2277 return -EADDRNOTAVAIL;
2279 netif_addr_lock_bh(netdev);
2280 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2281 netif_addr_unlock_bh(netdev);
2283 queue_work(priv->wq, &priv->set_rx_mode_work);
2288 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2291 netdev->features |= feature; \
2293 netdev->features &= ~feature; \
2296 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2298 static int set_feature_lro(struct net_device *netdev, bool enable)
2300 struct mlx5e_priv *priv = netdev_priv(netdev);
2301 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2304 mutex_lock(&priv->state_lock);
2306 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2307 mlx5e_close_locked(priv->netdev);
2309 priv->params.lro_en = enable;
2310 err = mlx5e_modify_tirs_lro(priv);
2312 netdev_err(netdev, "lro modify failed, %d\n", err);
2313 priv->params.lro_en = !enable;
2316 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2317 mlx5e_open_locked(priv->netdev);
2319 mutex_unlock(&priv->state_lock);
2324 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2326 struct mlx5e_priv *priv = netdev_priv(netdev);
2329 mlx5e_enable_vlan_filter(priv);
2331 mlx5e_disable_vlan_filter(priv);
2336 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2338 struct mlx5e_priv *priv = netdev_priv(netdev);
2340 if (!enable && mlx5e_tc_num_filters(priv)) {
2342 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2349 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2351 struct mlx5e_priv *priv = netdev_priv(netdev);
2352 struct mlx5_core_dev *mdev = priv->mdev;
2354 return mlx5_set_port_fcs(mdev, !enable);
2357 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2359 struct mlx5e_priv *priv = netdev_priv(netdev);
2362 mutex_lock(&priv->state_lock);
2364 priv->params.vlan_strip_disable = !enable;
2365 err = mlx5e_modify_rqs_vsd(priv, !enable);
2367 priv->params.vlan_strip_disable = enable;
2369 mutex_unlock(&priv->state_lock);
2374 #ifdef CONFIG_RFS_ACCEL
2375 static int set_feature_arfs(struct net_device *netdev, bool enable)
2377 struct mlx5e_priv *priv = netdev_priv(netdev);
2381 err = mlx5e_arfs_enable(priv);
2383 err = mlx5e_arfs_disable(priv);
2389 static int mlx5e_handle_feature(struct net_device *netdev,
2390 netdev_features_t wanted_features,
2391 netdev_features_t feature,
2392 mlx5e_feature_handler feature_handler)
2394 netdev_features_t changes = wanted_features ^ netdev->features;
2395 bool enable = !!(wanted_features & feature);
2398 if (!(changes & feature))
2401 err = feature_handler(netdev, enable);
2403 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2404 enable ? "Enable" : "Disable", feature, err);
2408 MLX5E_SET_FEATURE(netdev, feature, enable);
2412 static int mlx5e_set_features(struct net_device *netdev,
2413 netdev_features_t features)
2417 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2419 err |= mlx5e_handle_feature(netdev, features,
2420 NETIF_F_HW_VLAN_CTAG_FILTER,
2421 set_feature_vlan_filter);
2422 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2423 set_feature_tc_num_filters);
2424 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2425 set_feature_rx_all);
2426 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2427 set_feature_rx_vlan);
2428 #ifdef CONFIG_RFS_ACCEL
2429 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2433 return err ? -EINVAL : 0;
2436 #define MXL5_HW_MIN_MTU 64
2437 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2439 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2441 struct mlx5e_priv *priv = netdev_priv(netdev);
2442 struct mlx5_core_dev *mdev = priv->mdev;
2448 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2450 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2451 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2453 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2455 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2456 __func__, new_mtu, min_mtu, max_mtu);
2460 mutex_lock(&priv->state_lock);
2462 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2464 mlx5e_close_locked(netdev);
2466 netdev->mtu = new_mtu;
2469 err = mlx5e_open_locked(netdev);
2471 mutex_unlock(&priv->state_lock);
2476 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2480 return mlx5e_hwstamp_set(dev, ifr);
2482 return mlx5e_hwstamp_get(dev, ifr);
2488 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2490 struct mlx5e_priv *priv = netdev_priv(dev);
2491 struct mlx5_core_dev *mdev = priv->mdev;
2493 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2496 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2498 struct mlx5e_priv *priv = netdev_priv(dev);
2499 struct mlx5_core_dev *mdev = priv->mdev;
2501 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2505 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2507 struct mlx5e_priv *priv = netdev_priv(dev);
2508 struct mlx5_core_dev *mdev = priv->mdev;
2510 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2513 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2515 struct mlx5e_priv *priv = netdev_priv(dev);
2516 struct mlx5_core_dev *mdev = priv->mdev;
2518 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2520 static int mlx5_vport_link2ifla(u8 esw_link)
2523 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2524 return IFLA_VF_LINK_STATE_DISABLE;
2525 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2526 return IFLA_VF_LINK_STATE_ENABLE;
2528 return IFLA_VF_LINK_STATE_AUTO;
2531 static int mlx5_ifla_link2vport(u8 ifla_link)
2533 switch (ifla_link) {
2534 case IFLA_VF_LINK_STATE_DISABLE:
2535 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2536 case IFLA_VF_LINK_STATE_ENABLE:
2537 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2539 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2542 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2545 struct mlx5e_priv *priv = netdev_priv(dev);
2546 struct mlx5_core_dev *mdev = priv->mdev;
2548 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2549 mlx5_ifla_link2vport(link_state));
2552 static int mlx5e_get_vf_config(struct net_device *dev,
2553 int vf, struct ifla_vf_info *ivi)
2555 struct mlx5e_priv *priv = netdev_priv(dev);
2556 struct mlx5_core_dev *mdev = priv->mdev;
2559 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2562 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2566 static int mlx5e_get_vf_stats(struct net_device *dev,
2567 int vf, struct ifla_vf_stats *vf_stats)
2569 struct mlx5e_priv *priv = netdev_priv(dev);
2570 struct mlx5_core_dev *mdev = priv->mdev;
2572 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2576 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2577 sa_family_t sa_family, __be16 port)
2579 struct mlx5e_priv *priv = netdev_priv(netdev);
2581 if (!mlx5e_vxlan_allowed(priv->mdev))
2584 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2587 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2588 sa_family_t sa_family, __be16 port)
2590 struct mlx5e_priv *priv = netdev_priv(netdev);
2592 if (!mlx5e_vxlan_allowed(priv->mdev))
2595 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2598 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2599 struct sk_buff *skb,
2600 netdev_features_t features)
2602 struct udphdr *udph;
2606 switch (vlan_get_protocol(skb)) {
2607 case htons(ETH_P_IP):
2608 proto = ip_hdr(skb)->protocol;
2610 case htons(ETH_P_IPV6):
2611 proto = ipv6_hdr(skb)->nexthdr;
2617 if (proto == IPPROTO_UDP) {
2618 udph = udp_hdr(skb);
2619 port = be16_to_cpu(udph->dest);
2622 /* Verify if UDP port is being offloaded by HW */
2623 if (port && mlx5e_vxlan_lookup_port(priv, port))
2627 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2628 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2631 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2632 struct net_device *netdev,
2633 netdev_features_t features)
2635 struct mlx5e_priv *priv = netdev_priv(netdev);
2637 features = vlan_features_check(skb, features);
2638 features = vxlan_features_check(skb, features);
2640 /* Validate if the tunneled packet is being offloaded by HW */
2641 if (skb->encapsulation &&
2642 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2643 return mlx5e_vxlan_features_check(priv, skb, features);
2648 static void mlx5e_tx_timeout(struct net_device *dev)
2650 struct mlx5e_priv *priv = netdev_priv(dev);
2651 bool sched_work = false;
2654 netdev_err(dev, "TX timeout detected\n");
2656 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2657 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2659 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
2662 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2663 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2664 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2667 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2668 schedule_work(&priv->tx_timeout_work);
2671 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2672 .ndo_open = mlx5e_open,
2673 .ndo_stop = mlx5e_close,
2674 .ndo_start_xmit = mlx5e_xmit,
2675 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2676 .ndo_select_queue = mlx5e_select_queue,
2677 .ndo_get_stats64 = mlx5e_get_stats,
2678 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2679 .ndo_set_mac_address = mlx5e_set_mac,
2680 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2681 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2682 .ndo_set_features = mlx5e_set_features,
2683 .ndo_change_mtu = mlx5e_change_mtu,
2684 .ndo_do_ioctl = mlx5e_ioctl,
2685 #ifdef CONFIG_RFS_ACCEL
2686 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2688 .ndo_tx_timeout = mlx5e_tx_timeout,
2691 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2692 .ndo_open = mlx5e_open,
2693 .ndo_stop = mlx5e_close,
2694 .ndo_start_xmit = mlx5e_xmit,
2695 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2696 .ndo_select_queue = mlx5e_select_queue,
2697 .ndo_get_stats64 = mlx5e_get_stats,
2698 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2699 .ndo_set_mac_address = mlx5e_set_mac,
2700 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2701 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2702 .ndo_set_features = mlx5e_set_features,
2703 .ndo_change_mtu = mlx5e_change_mtu,
2704 .ndo_do_ioctl = mlx5e_ioctl,
2705 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2706 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2707 .ndo_features_check = mlx5e_features_check,
2708 #ifdef CONFIG_RFS_ACCEL
2709 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2711 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2712 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2713 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
2714 .ndo_set_vf_trust = mlx5e_set_vf_trust,
2715 .ndo_get_vf_config = mlx5e_get_vf_config,
2716 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2717 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2718 .ndo_tx_timeout = mlx5e_tx_timeout,
2721 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2723 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2725 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2726 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2727 !MLX5_CAP_ETH(mdev, csum_cap) ||
2728 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2729 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2730 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2731 MLX5_CAP_FLOWTABLE(mdev,
2732 flow_table_properties_nic_receive.max_ft_level)
2734 mlx5_core_warn(mdev,
2735 "Not creating net device, some required device capabilities are missing\n");
2738 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2739 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2740 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2741 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2746 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2748 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2750 return bf_buf_size -
2751 sizeof(struct mlx5e_tx_wqe) +
2752 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2755 #ifdef CONFIG_MLX5_CORE_EN_DCB
2756 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2760 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2761 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2762 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2763 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2764 priv->params.ets.prio_tc[i] = i;
2767 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2768 priv->params.ets.prio_tc[0] = 1;
2769 priv->params.ets.prio_tc[1] = 0;
2773 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2774 u32 *indirection_rqt, int len,
2777 int node = mdev->priv.numa_node;
2778 int node_num_of_cores;
2782 node = first_online_node;
2784 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2786 if (node_num_of_cores)
2787 num_channels = min_t(int, num_channels, node_num_of_cores);
2789 for (i = 0; i < len; i++)
2790 indirection_rqt[i] = i % num_channels;
2793 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2795 return MLX5_CAP_GEN(mdev, striding_rq) &&
2796 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2797 MLX5_CAP_ETH(mdev, reg_umr_sq);
2800 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2802 enum pcie_link_width width;
2803 enum pci_bus_speed speed;
2806 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2810 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2814 case PCIE_SPEED_2_5GT:
2815 *pci_bw = 2500 * width;
2817 case PCIE_SPEED_5_0GT:
2818 *pci_bw = 5000 * width;
2820 case PCIE_SPEED_8_0GT:
2821 *pci_bw = 8000 * width;
2830 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2832 return (link_speed && pci_bw &&
2833 (pci_bw < 40000) && (pci_bw < link_speed));
2836 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2837 struct net_device *netdev,
2840 struct mlx5e_priv *priv = netdev_priv(netdev);
2844 priv->params.log_sq_size =
2845 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2846 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2847 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2848 MLX5_WQ_TYPE_LINKED_LIST;
2850 /* set CQE compression */
2851 priv->params.rx_cqe_compress_admin = false;
2852 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2853 MLX5_CAP_GEN(mdev, vport_group_manager)) {
2854 mlx5e_get_max_linkspeed(mdev, &link_speed);
2855 mlx5e_get_pci_bw(mdev, &pci_bw);
2856 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2857 link_speed, pci_bw);
2858 priv->params.rx_cqe_compress_admin =
2859 cqe_compress_heuristic(link_speed, pci_bw);
2862 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2864 switch (priv->params.rq_wq_type) {
2865 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2866 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2867 priv->params.mpwqe_log_stride_sz =
2868 priv->params.rx_cqe_compress ?
2869 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2870 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2871 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2872 priv->params.mpwqe_log_stride_sz;
2873 priv->params.lro_en = true;
2875 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2876 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2879 mlx5_core_info(mdev,
2880 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2881 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2882 BIT(priv->params.log_rq_size),
2883 BIT(priv->params.mpwqe_log_stride_sz),
2884 priv->params.rx_cqe_compress_admin);
2886 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2887 BIT(priv->params.log_rq_size));
2888 priv->params.rx_cq_moderation_usec =
2889 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2890 priv->params.rx_cq_moderation_pkts =
2891 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2892 priv->params.tx_cq_moderation_usec =
2893 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2894 priv->params.tx_cq_moderation_pkts =
2895 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2896 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2897 priv->params.num_tc = 1;
2898 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2900 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2901 sizeof(priv->params.toeplitz_hash_key));
2903 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2904 MLX5E_INDIR_RQT_SIZE, num_channels);
2906 priv->params.lro_wqe_sz =
2907 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2910 priv->netdev = netdev;
2911 priv->params.num_channels = num_channels;
2913 #ifdef CONFIG_MLX5_CORE_EN_DCB
2914 mlx5e_ets_init(priv);
2917 mutex_init(&priv->state_lock);
2919 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2920 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2921 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
2922 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2925 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2927 struct mlx5e_priv *priv = netdev_priv(netdev);
2929 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2930 if (is_zero_ether_addr(netdev->dev_addr) &&
2931 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2932 eth_hw_addr_random(netdev);
2933 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2937 static void mlx5e_build_netdev(struct net_device *netdev)
2939 struct mlx5e_priv *priv = netdev_priv(netdev);
2940 struct mlx5_core_dev *mdev = priv->mdev;
2944 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2946 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2947 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2948 #ifdef CONFIG_MLX5_CORE_EN_DCB
2949 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2952 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2955 netdev->watchdog_timeo = 15 * HZ;
2957 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2959 netdev->vlan_features |= NETIF_F_SG;
2960 netdev->vlan_features |= NETIF_F_IP_CSUM;
2961 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2962 netdev->vlan_features |= NETIF_F_GRO;
2963 netdev->vlan_features |= NETIF_F_TSO;
2964 netdev->vlan_features |= NETIF_F_TSO6;
2965 netdev->vlan_features |= NETIF_F_RXCSUM;
2966 netdev->vlan_features |= NETIF_F_RXHASH;
2968 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2969 netdev->vlan_features |= NETIF_F_LRO;
2971 netdev->hw_features = netdev->vlan_features;
2972 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2973 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2974 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2976 if (mlx5e_vxlan_allowed(mdev)) {
2977 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
2978 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2979 NETIF_F_GSO_PARTIAL;
2980 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2981 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2982 netdev->hw_enc_features |= NETIF_F_TSO;
2983 netdev->hw_enc_features |= NETIF_F_TSO6;
2984 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2985 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2986 NETIF_F_GSO_PARTIAL;
2987 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2990 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2993 netdev->hw_features |= NETIF_F_RXALL;
2995 netdev->features = netdev->hw_features;
2996 if (!priv->params.lro_en)
2997 netdev->features &= ~NETIF_F_LRO;
3000 netdev->features &= ~NETIF_F_RXALL;
3002 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3003 if (FT_CAP(flow_modify_en) &&
3004 FT_CAP(modify_root) &&
3005 FT_CAP(identified_miss_table_mode) &&
3006 FT_CAP(flow_table_modify)) {
3007 netdev->hw_features |= NETIF_F_HW_TC;
3008 #ifdef CONFIG_RFS_ACCEL
3009 netdev->hw_features |= NETIF_F_NTUPLE;
3013 netdev->features |= NETIF_F_HIGHDMA;
3015 netdev->priv_flags |= IFF_UNICAST_FLT;
3017 mlx5e_set_netdev_dev_addr(netdev);
3020 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3021 struct mlx5_core_mkey *mkey)
3023 struct mlx5_core_dev *mdev = priv->mdev;
3024 struct mlx5_create_mkey_mbox_in *in;
3027 in = mlx5_vzalloc(sizeof(*in));
3031 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
3032 MLX5_PERM_LOCAL_READ |
3033 MLX5_ACCESS_MODE_PA;
3034 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
3035 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3037 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
3045 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3047 struct mlx5_core_dev *mdev = priv->mdev;
3050 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3052 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3053 priv->q_counter = 0;
3057 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3059 if (!priv->q_counter)
3062 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3065 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3067 struct mlx5_core_dev *mdev = priv->mdev;
3068 struct mlx5_create_mkey_mbox_in *in;
3069 struct mlx5_mkey_seg *mkc;
3070 int inlen = sizeof(*in);
3072 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3075 in = mlx5_vzalloc(inlen);
3080 mkc->status = MLX5_MKEY_STATUS_FREE;
3081 mkc->flags = MLX5_PERM_UMR_EN |
3082 MLX5_PERM_LOCAL_READ |
3083 MLX5_PERM_LOCAL_WRITE |
3084 MLX5_ACCESS_MODE_MTT;
3086 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3087 mkc->flags_pd = cpu_to_be32(priv->pdn);
3088 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3089 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3090 mkc->log2_page_size = PAGE_SHIFT;
3092 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3100 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3102 struct net_device *netdev;
3103 struct mlx5e_priv *priv;
3104 int nch = mlx5e_get_max_num_channels(mdev);
3107 if (mlx5e_check_required_hca_cap(mdev))
3110 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3111 nch * MLX5E_MAX_NUM_TC,
3114 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3118 mlx5e_build_netdev_priv(mdev, netdev, nch);
3119 mlx5e_build_netdev(netdev);
3121 netif_carrier_off(netdev);
3123 priv = netdev_priv(netdev);
3125 priv->wq = create_singlethread_workqueue("mlx5e");
3127 goto err_free_netdev;
3129 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3131 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3132 goto err_destroy_wq;
3135 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3137 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3138 goto err_unmap_free_uar;
3141 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3143 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3144 goto err_dealloc_pd;
3147 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3149 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3150 goto err_dealloc_transport_domain;
3153 err = mlx5e_create_umr_mkey(priv);
3155 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3156 goto err_destroy_mkey;
3159 err = mlx5e_create_tises(priv);
3161 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3162 goto err_destroy_umr_mkey;
3165 err = mlx5e_open_drop_rq(priv);
3167 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3168 goto err_destroy_tises;
3171 err = mlx5e_create_rqts(priv);
3173 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3174 goto err_close_drop_rq;
3177 err = mlx5e_create_tirs(priv);
3179 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3180 goto err_destroy_rqts;
3183 err = mlx5e_create_flow_steering(priv);
3185 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3186 goto err_destroy_tirs;
3189 mlx5e_create_q_counter(priv);
3191 mlx5e_init_l2_addr(priv);
3193 mlx5e_vxlan_init(priv);
3195 err = mlx5e_tc_init(priv);
3197 goto err_dealloc_q_counters;
3199 #ifdef CONFIG_MLX5_CORE_EN_DCB
3200 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3203 err = register_netdev(netdev);
3205 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3206 goto err_tc_cleanup;
3209 if (mlx5e_vxlan_allowed(mdev)) {
3211 vxlan_get_rx_port(netdev);
3215 mlx5e_enable_async_events(priv);
3216 queue_work(priv->wq, &priv->set_rx_mode_work);
3221 mlx5e_tc_cleanup(priv);
3223 err_dealloc_q_counters:
3224 mlx5e_destroy_q_counter(priv);
3225 mlx5e_destroy_flow_steering(priv);
3228 mlx5e_destroy_tirs(priv);
3231 mlx5e_destroy_rqts(priv);
3234 mlx5e_close_drop_rq(priv);
3237 mlx5e_destroy_tises(priv);
3239 err_destroy_umr_mkey:
3240 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3243 mlx5_core_destroy_mkey(mdev, &priv->mkey);
3245 err_dealloc_transport_domain:
3246 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3249 mlx5_core_dealloc_pd(mdev, priv->pdn);
3252 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3255 destroy_workqueue(priv->wq);
3258 free_netdev(netdev);
3263 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3265 struct mlx5e_priv *priv = vpriv;
3266 struct net_device *netdev = priv->netdev;
3268 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3270 queue_work(priv->wq, &priv->set_rx_mode_work);
3271 mlx5e_disable_async_events(priv);
3272 flush_workqueue(priv->wq);
3273 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3274 netif_device_detach(netdev);
3275 mlx5e_close(netdev);
3277 unregister_netdev(netdev);
3280 mlx5e_tc_cleanup(priv);
3281 mlx5e_vxlan_cleanup(priv);
3282 mlx5e_destroy_q_counter(priv);
3283 mlx5e_destroy_flow_steering(priv);
3284 mlx5e_destroy_tirs(priv);
3285 mlx5e_destroy_rqts(priv);
3286 mlx5e_close_drop_rq(priv);
3287 mlx5e_destroy_tises(priv);
3288 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3289 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3290 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3291 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3292 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3293 cancel_delayed_work_sync(&priv->update_stats_work);
3294 destroy_workqueue(priv->wq);
3296 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3297 free_netdev(netdev);
3300 static void *mlx5e_get_netdev(void *vpriv)
3302 struct mlx5e_priv *priv = vpriv;
3304 return priv->netdev;
3307 static struct mlx5_interface mlx5e_interface = {
3308 .add = mlx5e_create_netdev,
3309 .remove = mlx5e_destroy_netdev,
3310 .event = mlx5e_async_event,
3311 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3312 .get_dev = mlx5e_get_netdev,
3315 void mlx5e_init(void)
3317 mlx5_register_interface(&mlx5e_interface);
3320 void mlx5e_cleanup(void)
3322 mlx5_unregister_interface(&mlx5e_interface);