2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <net/geneve.h>
38 #include <linux/bpf.h>
39 #include <linux/if_bridge.h>
40 #include <net/page_pool.h>
41 #include <net/xdp_sock.h>
47 #include "en_accel/ipsec.h"
48 #include "en_accel/ipsec_rxtx.h"
49 #include "en_accel/en_accel.h"
50 #include "en_accel/tls.h"
51 #include "accel/ipsec.h"
52 #include "accel/tls.h"
53 #include "lib/vxlan.h"
54 #include "lib/clock.h"
58 #include "en/monitor_stats.h"
59 #include "en/health.h"
60 #include "en/params.h"
61 #include "en/xsk/umem.h"
62 #include "en/xsk/setup.h"
63 #include "en/xsk/rx.h"
64 #include "en/xsk/tx.h"
65 #include "en/hv_vhca_stats.h"
69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
71 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
72 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
73 MLX5_CAP_ETH(mdev, reg_umr_sq);
74 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
75 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
80 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
81 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
88 struct mlx5e_params *params)
90 params->log_rq_mtu_frames = is_kdump_kernel() ?
91 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
92 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
94 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
95 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
96 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
97 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
98 BIT(params->log_rq_mtu_frames),
99 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
100 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
104 struct mlx5e_params *params)
106 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
109 if (MLX5_IPSEC_DEV(mdev))
112 if (params->xdp_prog) {
113 /* XSK params are not considered here. If striding RQ is in use,
114 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
115 * be called with the known XSK params.
117 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
126 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
127 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
128 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
134 struct mlx5_core_dev *mdev = priv->mdev;
137 port_state = mlx5_query_vport_state(mdev,
138 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
141 if (port_state == VPORT_STATE_UP) {
142 netdev_info(priv->netdev, "Link up\n");
143 netif_carrier_on(priv->netdev);
145 netdev_info(priv->netdev, "Link down\n");
146 netif_carrier_off(priv->netdev);
150 static void mlx5e_update_carrier_work(struct work_struct *work)
152 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
153 update_carrier_work);
155 mutex_lock(&priv->state_lock);
156 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
157 if (priv->profile->update_carrier)
158 priv->profile->update_carrier(priv);
159 mutex_unlock(&priv->state_lock);
162 void mlx5e_update_stats(struct mlx5e_priv *priv)
166 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
167 if (mlx5e_stats_grps[i].update_stats)
168 mlx5e_stats_grps[i].update_stats(priv);
171 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
175 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
176 if (mlx5e_stats_grps[i].update_stats_mask &
177 MLX5E_NDO_UPDATE_STATS)
178 mlx5e_stats_grps[i].update_stats(priv);
181 static void mlx5e_update_stats_work(struct work_struct *work)
183 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
186 mutex_lock(&priv->state_lock);
187 priv->profile->update_stats(priv);
188 mutex_unlock(&priv->state_lock);
191 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
193 if (!priv->profile->update_stats)
196 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
199 queue_work(priv->wq, &priv->update_stats_work);
202 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
204 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
205 struct mlx5_eqe *eqe = data;
207 if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
210 switch (eqe->sub_type) {
211 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
212 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
213 queue_work(priv->wq, &priv->update_carrier_work);
222 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
224 priv->events_nb.notifier_call = async_event;
225 mlx5_notifier_register(priv->mdev, &priv->events_nb);
228 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
230 mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
233 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
234 struct mlx5e_icosq *sq,
235 struct mlx5e_umr_wqe *wqe)
237 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
238 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
239 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
241 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
243 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
244 cseg->imm = rq->mkey_be;
246 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
247 ucseg->xlt_octowords =
248 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
249 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
252 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
253 struct mlx5e_channel *c)
255 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
257 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
258 sizeof(*rq->mpwqe.info)),
259 GFP_KERNEL, cpu_to_node(c->cpu));
263 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
268 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
269 u64 npages, u8 page_shift,
270 struct mlx5_core_mkey *umr_mkey)
272 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
277 in = kvzalloc(inlen, GFP_KERNEL);
281 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
283 MLX5_SET(mkc, mkc, free, 1);
284 MLX5_SET(mkc, mkc, umr_en, 1);
285 MLX5_SET(mkc, mkc, lw, 1);
286 MLX5_SET(mkc, mkc, lr, 1);
287 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
289 MLX5_SET(mkc, mkc, qpn, 0xffffff);
290 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
291 MLX5_SET64(mkc, mkc, len, npages << page_shift);
292 MLX5_SET(mkc, mkc, translations_octword_size,
293 MLX5_MTT_OCTW(npages));
294 MLX5_SET(mkc, mkc, log_page_size, page_shift);
296 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
302 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
304 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
306 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
309 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
311 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
314 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
316 struct mlx5e_wqe_frag_info next_frag = {};
317 struct mlx5e_wqe_frag_info *prev = NULL;
320 next_frag.di = &rq->wqe.di[0];
322 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
323 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
324 struct mlx5e_wqe_frag_info *frag =
325 &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
328 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
329 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
331 next_frag.offset = 0;
333 prev->last_in_page = true;
338 next_frag.offset += frag_info[f].frag_stride;
344 prev->last_in_page = true;
347 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
350 int len = wq_sz << rq->wqe.info.log_num_frags;
352 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
353 GFP_KERNEL, cpu_to_node(cpu));
357 mlx5e_init_frags_partition(rq);
362 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
367 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
369 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
371 mlx5e_reporter_rq_cqe_err(rq);
374 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
375 struct mlx5e_params *params,
376 struct mlx5e_xsk_param *xsk,
377 struct xdp_umem *umem,
378 struct mlx5e_rq_param *rqp,
381 struct page_pool_params pp_params = { 0 };
382 struct mlx5_core_dev *mdev = c->mdev;
383 void *rqc = rqp->rqc;
384 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
385 u32 num_xsk_frames = 0;
392 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
394 rq->wq_type = params->rq_wq_type;
396 rq->netdev = c->netdev;
397 rq->tstamp = c->tstamp;
398 rq->clock = &mdev->clock;
402 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
403 rq->xdpsq = &c->rq_xdpsq;
407 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
409 rq->stats = &c->priv->channel_stats[c->ix].rq;
410 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
412 if (params->xdp_prog)
413 bpf_prog_inc(params->xdp_prog);
414 rq->xdp_prog = params->xdp_prog;
418 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
419 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
421 goto err_rq_wq_destroy;
423 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
424 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
425 rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
426 pool_size = 1 << params->log_rq_mtu_frames;
428 switch (rq->wq_type) {
429 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
430 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
435 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
437 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
440 num_xsk_frames = wq_sz <<
441 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
443 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
444 mlx5e_mpwqe_get_log_rq_size(params, xsk);
446 rq->post_wqes = mlx5e_post_rx_mpwqes;
447 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
449 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
450 #ifdef CONFIG_MLX5_EN_IPSEC
451 if (MLX5_IPSEC_DEV(mdev)) {
453 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
454 goto err_rq_wq_destroy;
457 if (!rq->handle_rx_cqe) {
459 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
460 goto err_rq_wq_destroy;
463 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
464 mlx5e_xsk_skb_from_cqe_mpwrq_linear :
465 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
466 mlx5e_skb_from_cqe_mpwrq_linear :
467 mlx5e_skb_from_cqe_mpwrq_nonlinear;
469 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
470 rq->mpwqe.num_strides =
471 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
473 err = mlx5e_create_rq_umr_mkey(mdev, rq);
475 goto err_rq_wq_destroy;
476 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
478 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
482 default: /* MLX5_WQ_TYPE_CYCLIC */
483 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
488 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
490 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
493 num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
495 rq->wqe.info = rqp->frags_info;
497 kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
498 (wq_sz << rq->wqe.info.log_num_frags)),
499 GFP_KERNEL, cpu_to_node(c->cpu));
500 if (!rq->wqe.frags) {
505 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
509 rq->post_wqes = mlx5e_post_rx_wqes;
510 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
512 #ifdef CONFIG_MLX5_EN_IPSEC
514 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
517 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
518 if (!rq->handle_rx_cqe) {
520 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
524 rq->wqe.skb_from_cqe = xsk ?
525 mlx5e_xsk_skb_from_cqe_linear :
526 mlx5e_rx_is_linear_skb(params, NULL) ?
527 mlx5e_skb_from_cqe_linear :
528 mlx5e_skb_from_cqe_nonlinear;
529 rq->mkey_be = c->mkey_be;
533 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
535 mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
540 rq->zca.free = mlx5e_xsk_zca_free;
541 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
545 /* Create a page_pool and register it with rxq */
547 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */
548 pp_params.pool_size = pool_size;
549 pp_params.nid = cpu_to_node(c->cpu);
550 pp_params.dev = c->pdev;
551 pp_params.dma_dir = rq->buff.map_dir;
553 /* page_pool can be used even when there is no rq->xdp_prog,
554 * given page_pool does not handle DMA mapping there is no
555 * required state to clear. And page_pool gracefully handle
558 rq->page_pool = page_pool_create(&pp_params);
559 if (IS_ERR(rq->page_pool)) {
560 err = PTR_ERR(rq->page_pool);
561 rq->page_pool = NULL;
564 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
565 MEM_TYPE_PAGE_POOL, rq->page_pool);
570 for (i = 0; i < wq_sz; i++) {
571 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
572 struct mlx5e_rx_wqe_ll *wqe =
573 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
575 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
576 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
578 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
579 wqe->data[0].byte_count = cpu_to_be32(byte_count);
580 wqe->data[0].lkey = rq->mkey_be;
582 struct mlx5e_rx_wqe_cyc *wqe =
583 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
586 for (f = 0; f < rq->wqe.info.num_frags; f++) {
587 u32 frag_size = rq->wqe.info.arr[f].frag_size |
588 MLX5_HW_START_PADDING;
590 wqe->data[f].byte_count = cpu_to_be32(frag_size);
591 wqe->data[f].lkey = rq->mkey_be;
593 /* check if num_frags is not a pow of two */
594 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
595 wqe->data[f].byte_count = 0;
596 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
597 wqe->data[f].addr = 0;
602 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
604 switch (params->rx_cq_moderation.cq_period_mode) {
605 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
606 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
608 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
610 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
613 rq->page_cache.head = 0;
614 rq->page_cache.tail = 0;
619 switch (rq->wq_type) {
620 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
621 kvfree(rq->mpwqe.info);
622 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
624 default: /* MLX5_WQ_TYPE_CYCLIC */
625 kvfree(rq->wqe.frags);
626 mlx5e_free_di_list(rq);
631 bpf_prog_put(rq->xdp_prog);
632 xdp_rxq_info_unreg(&rq->xdp_rxq);
633 page_pool_destroy(rq->page_pool);
634 mlx5_wq_destroy(&rq->wq_ctrl);
639 static void mlx5e_free_rq(struct mlx5e_rq *rq)
644 bpf_prog_put(rq->xdp_prog);
646 switch (rq->wq_type) {
647 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
648 kvfree(rq->mpwqe.info);
649 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
651 default: /* MLX5_WQ_TYPE_CYCLIC */
652 kvfree(rq->wqe.frags);
653 mlx5e_free_di_list(rq);
656 for (i = rq->page_cache.head; i != rq->page_cache.tail;
657 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
658 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
660 /* With AF_XDP, page_cache is not used, so this loop is not
661 * entered, and it's safe to call mlx5e_page_release_dynamic
664 mlx5e_page_release_dynamic(rq, dma_info, false);
667 xdp_rxq_info_unreg(&rq->xdp_rxq);
668 page_pool_destroy(rq->page_pool);
669 mlx5_wq_destroy(&rq->wq_ctrl);
672 static int mlx5e_create_rq(struct mlx5e_rq *rq,
673 struct mlx5e_rq_param *param)
675 struct mlx5_core_dev *mdev = rq->mdev;
683 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
684 sizeof(u64) * rq->wq_ctrl.buf.npages;
685 in = kvzalloc(inlen, GFP_KERNEL);
689 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
690 wq = MLX5_ADDR_OF(rqc, rqc, wq);
692 memcpy(rqc, param->rqc, sizeof(param->rqc));
694 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
695 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
696 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
697 MLX5_ADAPTER_PAGE_SHIFT);
698 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
700 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
701 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
703 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
710 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
712 struct mlx5_core_dev *mdev = rq->mdev;
719 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
720 in = kvzalloc(inlen, GFP_KERNEL);
724 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
726 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
727 MLX5_SET(rqc, rqc, state, next_state);
729 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
736 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
738 struct mlx5e_channel *c = rq->channel;
739 struct mlx5e_priv *priv = c->priv;
740 struct mlx5_core_dev *mdev = priv->mdev;
747 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
748 in = kvzalloc(inlen, GFP_KERNEL);
752 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
754 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
755 MLX5_SET64(modify_rq_in, in, modify_bitmask,
756 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
757 MLX5_SET(rqc, rqc, scatter_fcs, enable);
758 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
760 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
767 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
769 struct mlx5e_channel *c = rq->channel;
770 struct mlx5_core_dev *mdev = c->mdev;
776 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
777 in = kvzalloc(inlen, GFP_KERNEL);
781 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
783 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
784 MLX5_SET64(modify_rq_in, in, modify_bitmask,
785 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
786 MLX5_SET(rqc, rqc, vsd, vsd);
787 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
789 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
796 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
798 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
801 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
803 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
804 struct mlx5e_channel *c = rq->channel;
806 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
809 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
813 } while (time_before(jiffies, exp_time));
815 netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
816 c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
818 mlx5e_reporter_rx_timeout(rq);
822 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
827 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
828 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
832 /* Outstanding UMR WQEs (in progress) start at wq->head */
833 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
834 rq->dealloc_wqe(rq, head);
835 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
838 while (!mlx5_wq_ll_is_empty(wq)) {
839 struct mlx5e_rx_wqe_ll *wqe;
841 wqe_ix_be = *wq->tail_next;
842 wqe_ix = be16_to_cpu(wqe_ix_be);
843 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix);
844 rq->dealloc_wqe(rq, wqe_ix);
845 mlx5_wq_ll_pop(wq, wqe_ix_be,
846 &wqe->next.next_wqe_index);
849 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
851 while (!mlx5_wq_cyc_is_empty(wq)) {
852 wqe_ix = mlx5_wq_cyc_get_tail(wq);
853 rq->dealloc_wqe(rq, wqe_ix);
860 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
861 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
862 struct xdp_umem *umem, struct mlx5e_rq *rq)
866 err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
870 err = mlx5e_create_rq(rq, param);
874 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
878 if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
879 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
881 if (params->rx_dim_enabled)
882 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
884 /* We disable csum_complete when XDP is enabled since
885 * XDP programs might manipulate packets which will render
886 * skb->checksum incorrect.
888 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
889 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
894 mlx5e_destroy_rq(rq);
901 void mlx5e_activate_rq(struct mlx5e_rq *rq)
903 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
904 mlx5e_trigger_irq(&rq->channel->icosq);
907 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
909 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
910 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
913 void mlx5e_close_rq(struct mlx5e_rq *rq)
915 cancel_work_sync(&rq->dim.work);
916 cancel_work_sync(&rq->channel->icosq.recover_work);
917 cancel_work_sync(&rq->recover_work);
918 mlx5e_destroy_rq(rq);
919 mlx5e_free_rx_descs(rq);
923 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
925 kvfree(sq->db.xdpi_fifo.xi);
926 kvfree(sq->db.wqe_info);
929 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
931 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
932 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
933 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
935 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
940 xdpi_fifo->pc = &sq->xdpi_fifo_pc;
941 xdpi_fifo->cc = &sq->xdpi_fifo_cc;
942 xdpi_fifo->mask = dsegs_per_wq - 1;
947 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
949 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
952 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
954 if (!sq->db.wqe_info)
957 err = mlx5e_alloc_xdpsq_fifo(sq, numa);
959 mlx5e_free_xdpsq_db(sq);
966 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
967 struct mlx5e_params *params,
968 struct xdp_umem *umem,
969 struct mlx5e_sq_param *param,
970 struct mlx5e_xdpsq *sq,
973 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
974 struct mlx5_core_dev *mdev = c->mdev;
975 struct mlx5_wq_cyc *wq = &sq->wq;
979 sq->mkey_be = c->mkey_be;
981 sq->uar_map = mdev->mlx5e_res.bfreg.map;
982 sq->min_inline_mode = params->tx_min_inline_mode;
983 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
986 sq->stats = sq->umem ?
987 &c->priv->channel_stats[c->ix].xsksq :
989 &c->priv->channel_stats[c->ix].xdpsq :
990 &c->priv->channel_stats[c->ix].rq_xdpsq;
992 param->wq.db_numa_node = cpu_to_node(c->cpu);
993 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
996 wq->db = &wq->db[MLX5_SND_DBR];
998 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1000 goto err_sq_wq_destroy;
1005 mlx5_wq_destroy(&sq->wq_ctrl);
1010 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1012 mlx5e_free_xdpsq_db(sq);
1013 mlx5_wq_destroy(&sq->wq_ctrl);
1016 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1018 kvfree(sq->db.ico_wqe);
1021 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1023 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1025 sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1026 sizeof(*sq->db.ico_wqe)),
1028 if (!sq->db.ico_wqe)
1034 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1036 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1039 mlx5e_reporter_icosq_cqe_err(sq);
1042 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1043 struct mlx5e_sq_param *param,
1044 struct mlx5e_icosq *sq)
1046 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1047 struct mlx5_core_dev *mdev = c->mdev;
1048 struct mlx5_wq_cyc *wq = &sq->wq;
1052 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1054 param->wq.db_numa_node = cpu_to_node(c->cpu);
1055 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1058 wq->db = &wq->db[MLX5_SND_DBR];
1060 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1062 goto err_sq_wq_destroy;
1064 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1069 mlx5_wq_destroy(&sq->wq_ctrl);
1074 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1076 mlx5e_free_icosq_db(sq);
1077 mlx5_wq_destroy(&sq->wq_ctrl);
1080 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1082 kvfree(sq->db.wqe_info);
1083 kvfree(sq->db.dma_fifo);
1086 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1088 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1089 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1091 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1092 sizeof(*sq->db.dma_fifo)),
1094 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1095 sizeof(*sq->db.wqe_info)),
1097 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1098 mlx5e_free_txqsq_db(sq);
1102 sq->dma_fifo_mask = df_sz - 1;
1107 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1108 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1110 struct mlx5e_params *params,
1111 struct mlx5e_sq_param *param,
1112 struct mlx5e_txqsq *sq,
1115 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1116 struct mlx5_core_dev *mdev = c->mdev;
1117 struct mlx5_wq_cyc *wq = &sq->wq;
1121 sq->tstamp = c->tstamp;
1122 sq->clock = &mdev->clock;
1123 sq->mkey_be = c->mkey_be;
1126 sq->txq_ix = txq_ix;
1127 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1128 sq->min_inline_mode = params->tx_min_inline_mode;
1129 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1130 sq->stats = &c->priv->channel_stats[c->ix].sq[tc];
1131 sq->stop_room = MLX5E_SQ_STOP_ROOM;
1132 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1133 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1134 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1135 if (MLX5_IPSEC_DEV(c->priv->mdev))
1136 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1137 #ifdef CONFIG_MLX5_EN_TLS
1138 if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1139 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1140 sq->stop_room += MLX5E_SQ_TLS_ROOM +
1141 mlx5e_ktls_dumps_num_wqebbs(sq, MAX_SKB_FRAGS,
1142 TLS_MAX_PAYLOAD_SIZE);
1146 param->wq.db_numa_node = cpu_to_node(c->cpu);
1147 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl);
1150 wq->db = &wq->db[MLX5_SND_DBR];
1152 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1154 goto err_sq_wq_destroy;
1156 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1157 sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1162 mlx5_wq_destroy(&sq->wq_ctrl);
1167 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1169 mlx5e_free_txqsq_db(sq);
1170 mlx5_wq_destroy(&sq->wq_ctrl);
1173 struct mlx5e_create_sq_param {
1174 struct mlx5_wq_ctrl *wq_ctrl;
1181 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1182 struct mlx5e_sq_param *param,
1183 struct mlx5e_create_sq_param *csp,
1192 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1193 sizeof(u64) * csp->wq_ctrl->buf.npages;
1194 in = kvzalloc(inlen, GFP_KERNEL);
1198 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1199 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1201 memcpy(sqc, param->sqc, sizeof(param->sqc));
1202 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1203 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1204 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1206 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1207 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1209 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1210 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1212 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1213 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1214 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1215 MLX5_ADAPTER_PAGE_SHIFT);
1216 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1218 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1219 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1221 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1228 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1229 struct mlx5e_modify_sq_param *p)
1236 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1237 in = kvzalloc(inlen, GFP_KERNEL);
1241 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1243 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1244 MLX5_SET(sqc, sqc, state, p->next_state);
1245 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1246 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1247 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1250 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1257 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1259 mlx5_core_destroy_sq(mdev, sqn);
1262 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1263 struct mlx5e_sq_param *param,
1264 struct mlx5e_create_sq_param *csp,
1267 struct mlx5e_modify_sq_param msp = {0};
1270 err = mlx5e_create_sq(mdev, param, csp, sqn);
1274 msp.curr_state = MLX5_SQC_STATE_RST;
1275 msp.next_state = MLX5_SQC_STATE_RDY;
1276 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1278 mlx5e_destroy_sq(mdev, *sqn);
1283 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1284 struct mlx5e_txqsq *sq, u32 rate);
1286 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1289 struct mlx5e_params *params,
1290 struct mlx5e_sq_param *param,
1291 struct mlx5e_txqsq *sq,
1294 struct mlx5e_create_sq_param csp = {};
1298 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1304 csp.cqn = sq->cq.mcq.cqn;
1305 csp.wq_ctrl = &sq->wq_ctrl;
1306 csp.min_inline_mode = sq->min_inline_mode;
1307 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1309 goto err_free_txqsq;
1311 tx_rate = c->priv->tx_rates[sq->txq_ix];
1313 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1315 if (params->tx_dim_enabled)
1316 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1321 mlx5e_free_txqsq(sq);
1326 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1328 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1329 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1330 netdev_tx_reset_queue(sq->txq);
1331 netif_tx_start_queue(sq->txq);
1334 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1336 __netif_tx_lock_bh(txq);
1337 netif_tx_stop_queue(txq);
1338 __netif_tx_unlock_bh(txq);
1341 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1343 struct mlx5e_channel *c = sq->channel;
1344 struct mlx5_wq_cyc *wq = &sq->wq;
1346 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1347 /* prevent netif_tx_wake_queue */
1348 napi_synchronize(&c->napi);
1350 mlx5e_tx_disable_queue(sq->txq);
1352 /* last doorbell out, godspeed .. */
1353 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1354 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1355 struct mlx5e_tx_wqe_info *wi;
1356 struct mlx5e_tx_wqe *nop;
1358 wi = &sq->db.wqe_info[pi];
1360 memset(wi, 0, sizeof(*wi));
1362 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1363 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1367 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1369 struct mlx5e_channel *c = sq->channel;
1370 struct mlx5_core_dev *mdev = c->mdev;
1371 struct mlx5_rate_limit rl = {0};
1373 cancel_work_sync(&sq->dim.work);
1374 cancel_work_sync(&sq->recover_work);
1375 mlx5e_destroy_sq(mdev, sq->sqn);
1376 if (sq->rate_limit) {
1377 rl.rate = sq->rate_limit;
1378 mlx5_rl_remove_rate(mdev, &rl);
1380 mlx5e_free_txqsq_descs(sq);
1381 mlx5e_free_txqsq(sq);
1384 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1386 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1389 mlx5e_reporter_tx_err_cqe(sq);
1392 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1393 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1395 struct mlx5e_create_sq_param csp = {};
1398 err = mlx5e_alloc_icosq(c, param, sq);
1402 csp.cqn = sq->cq.mcq.cqn;
1403 csp.wq_ctrl = &sq->wq_ctrl;
1404 csp.min_inline_mode = params->tx_min_inline_mode;
1405 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1407 goto err_free_icosq;
1412 mlx5e_free_icosq(sq);
1417 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1419 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1422 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1424 struct mlx5e_channel *c = icosq->channel;
1426 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1427 napi_synchronize(&c->napi);
1430 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1432 struct mlx5e_channel *c = sq->channel;
1434 mlx5e_destroy_sq(c->mdev, sq->sqn);
1435 mlx5e_free_icosq(sq);
1438 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1439 struct mlx5e_sq_param *param, struct xdp_umem *umem,
1440 struct mlx5e_xdpsq *sq, bool is_redirect)
1442 struct mlx5e_create_sq_param csp = {};
1445 err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1450 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1451 csp.cqn = sq->cq.mcq.cqn;
1452 csp.wq_ctrl = &sq->wq_ctrl;
1453 csp.min_inline_mode = sq->min_inline_mode;
1454 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1455 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1457 goto err_free_xdpsq;
1459 mlx5e_set_xmit_fp(sq, param->is_mpw);
1461 if (!param->is_mpw) {
1462 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1463 unsigned int inline_hdr_sz = 0;
1466 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1467 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1471 /* Pre initialize fixed WQE fields */
1472 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1473 struct mlx5e_xdp_wqe_info *wi = &sq->db.wqe_info[i];
1474 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1475 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1476 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1477 struct mlx5_wqe_data_seg *dseg;
1479 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1480 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1482 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1483 dseg->lkey = sq->mkey_be;
1493 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1494 mlx5e_free_xdpsq(sq);
1499 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1501 struct mlx5e_channel *c = sq->channel;
1503 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1504 napi_synchronize(&c->napi);
1506 mlx5e_destroy_sq(c->mdev, sq->sqn);
1507 mlx5e_free_xdpsq_descs(sq);
1508 mlx5e_free_xdpsq(sq);
1511 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1512 struct mlx5e_cq_param *param,
1513 struct mlx5e_cq *cq)
1515 struct mlx5_core_cq *mcq = &cq->mcq;
1521 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1525 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1531 mcq->set_ci_db = cq->wq_ctrl.db.db;
1532 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1533 *mcq->set_ci_db = 0;
1535 mcq->vector = param->eq_ix;
1536 mcq->comp = mlx5e_completion_event;
1537 mcq->event = mlx5e_cq_error_event;
1540 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1541 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1551 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1552 struct mlx5e_cq_param *param,
1553 struct mlx5e_cq *cq)
1555 struct mlx5_core_dev *mdev = c->priv->mdev;
1558 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1559 param->wq.db_numa_node = cpu_to_node(c->cpu);
1560 param->eq_ix = c->ix;
1562 err = mlx5e_alloc_cq_common(mdev, param, cq);
1564 cq->napi = &c->napi;
1570 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1572 mlx5_wq_destroy(&cq->wq_ctrl);
1575 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1577 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1578 struct mlx5_core_dev *mdev = cq->mdev;
1579 struct mlx5_core_cq *mcq = &cq->mcq;
1584 unsigned int irqn_not_used;
1588 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1592 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1593 sizeof(u64) * cq->wq_ctrl.buf.npages;
1594 in = kvzalloc(inlen, GFP_KERNEL);
1598 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1600 memcpy(cqc, param->cqc, sizeof(param->cqc));
1602 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1603 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1605 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1606 MLX5_SET(cqc, cqc, c_eqn, eqn);
1607 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1608 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1609 MLX5_ADAPTER_PAGE_SHIFT);
1610 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1612 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1624 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1626 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1629 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1630 struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1632 struct mlx5_core_dev *mdev = c->mdev;
1635 err = mlx5e_alloc_cq(c, param, cq);
1639 err = mlx5e_create_cq(cq, param);
1643 if (MLX5_CAP_GEN(mdev, cq_moderation))
1644 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1653 void mlx5e_close_cq(struct mlx5e_cq *cq)
1655 mlx5e_destroy_cq(cq);
1659 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1660 struct mlx5e_params *params,
1661 struct mlx5e_channel_param *cparam)
1666 for (tc = 0; tc < c->num_tc; tc++) {
1667 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1668 &cparam->tx_cq, &c->sq[tc].cq);
1670 goto err_close_tx_cqs;
1676 for (tc--; tc >= 0; tc--)
1677 mlx5e_close_cq(&c->sq[tc].cq);
1682 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1686 for (tc = 0; tc < c->num_tc; tc++)
1687 mlx5e_close_cq(&c->sq[tc].cq);
1690 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1691 struct mlx5e_params *params,
1692 struct mlx5e_channel_param *cparam)
1694 struct mlx5e_priv *priv = c->priv;
1697 for (tc = 0; tc < params->num_tc; tc++) {
1698 int txq_ix = c->ix + tc * priv->max_nch;
1700 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1701 params, &cparam->sq, &c->sq[tc], tc);
1709 for (tc--; tc >= 0; tc--)
1710 mlx5e_close_txqsq(&c->sq[tc]);
1715 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1719 for (tc = 0; tc < c->num_tc; tc++)
1720 mlx5e_close_txqsq(&c->sq[tc]);
1723 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1724 struct mlx5e_txqsq *sq, u32 rate)
1726 struct mlx5e_priv *priv = netdev_priv(dev);
1727 struct mlx5_core_dev *mdev = priv->mdev;
1728 struct mlx5e_modify_sq_param msp = {0};
1729 struct mlx5_rate_limit rl = {0};
1733 if (rate == sq->rate_limit)
1737 if (sq->rate_limit) {
1738 rl.rate = sq->rate_limit;
1739 /* remove current rl index to free space to next ones */
1740 mlx5_rl_remove_rate(mdev, &rl);
1747 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1749 netdev_err(dev, "Failed configuring rate %u: %d\n",
1755 msp.curr_state = MLX5_SQC_STATE_RDY;
1756 msp.next_state = MLX5_SQC_STATE_RDY;
1757 msp.rl_index = rl_index;
1758 msp.rl_update = true;
1759 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1761 netdev_err(dev, "Failed configuring rate %u: %d\n",
1763 /* remove the rate from the table */
1765 mlx5_rl_remove_rate(mdev, &rl);
1769 sq->rate_limit = rate;
1773 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1775 struct mlx5e_priv *priv = netdev_priv(dev);
1776 struct mlx5_core_dev *mdev = priv->mdev;
1777 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1780 if (!mlx5_rl_is_supported(mdev)) {
1781 netdev_err(dev, "Rate limiting is not supported on this device\n");
1785 /* rate is given in Mb/sec, HW config is in Kb/sec */
1788 /* Check whether rate in valid range, 0 is always valid */
1789 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1790 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1794 mutex_lock(&priv->state_lock);
1795 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1796 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1798 priv->tx_rates[index] = rate;
1799 mutex_unlock(&priv->state_lock);
1804 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1805 struct mlx5e_params *params)
1807 int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1810 if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1813 for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1814 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1816 cpumask_set_cpu(cpu, c->xps_cpumask);
1822 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1824 free_cpumask_var(c->xps_cpumask);
1827 static int mlx5e_open_queues(struct mlx5e_channel *c,
1828 struct mlx5e_params *params,
1829 struct mlx5e_channel_param *cparam)
1831 struct dim_cq_moder icocq_moder = {0, 0};
1834 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1838 err = mlx5e_open_tx_cqs(c, params, cparam);
1840 goto err_close_icosq_cq;
1842 err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1844 goto err_close_tx_cqs;
1846 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1848 goto err_close_xdp_tx_cqs;
1850 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1851 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1852 &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1854 goto err_close_rx_cq;
1856 napi_enable(&c->napi);
1858 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1860 goto err_disable_napi;
1862 err = mlx5e_open_sqs(c, params, cparam);
1864 goto err_close_icosq;
1867 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1868 &c->rq_xdpsq, false);
1873 err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1875 goto err_close_xdp_sq;
1877 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1884 mlx5e_close_rq(&c->rq);
1888 mlx5e_close_xdpsq(&c->rq_xdpsq);
1894 mlx5e_close_icosq(&c->icosq);
1897 napi_disable(&c->napi);
1900 mlx5e_close_cq(&c->rq_xdpsq.cq);
1903 mlx5e_close_cq(&c->rq.cq);
1905 err_close_xdp_tx_cqs:
1906 mlx5e_close_cq(&c->xdpsq.cq);
1909 mlx5e_close_tx_cqs(c);
1912 mlx5e_close_cq(&c->icosq.cq);
1917 static void mlx5e_close_queues(struct mlx5e_channel *c)
1919 mlx5e_close_xdpsq(&c->xdpsq);
1920 mlx5e_close_rq(&c->rq);
1922 mlx5e_close_xdpsq(&c->rq_xdpsq);
1924 mlx5e_close_icosq(&c->icosq);
1925 napi_disable(&c->napi);
1927 mlx5e_close_cq(&c->rq_xdpsq.cq);
1928 mlx5e_close_cq(&c->rq.cq);
1929 mlx5e_close_cq(&c->xdpsq.cq);
1930 mlx5e_close_tx_cqs(c);
1931 mlx5e_close_cq(&c->icosq.cq);
1934 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1936 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1938 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1941 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1942 struct mlx5e_params *params,
1943 struct mlx5e_channel_param *cparam,
1944 struct xdp_umem *umem,
1945 struct mlx5e_channel **cp)
1947 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1948 struct net_device *netdev = priv->netdev;
1949 struct mlx5e_xsk_param xsk;
1950 struct mlx5e_channel *c;
1955 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1959 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1964 c->mdev = priv->mdev;
1965 c->tstamp = &priv->tstamp;
1968 c->pdev = priv->mdev->device;
1969 c->netdev = priv->netdev;
1970 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1971 c->num_tc = params->num_tc;
1972 c->xdp = !!params->xdp_prog;
1973 c->stats = &priv->channel_stats[ix].ch;
1974 c->irq_desc = irq_to_desc(irq);
1975 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1977 err = mlx5e_alloc_xps_cpumask(c, params);
1979 goto err_free_channel;
1981 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1983 err = mlx5e_open_queues(c, params, cparam);
1988 mlx5e_build_xsk_param(umem, &xsk);
1989 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1991 goto err_close_queues;
1999 mlx5e_close_queues(c);
2002 netif_napi_del(&c->napi);
2003 mlx5e_free_xps_cpumask(c);
2011 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2015 for (tc = 0; tc < c->num_tc; tc++)
2016 mlx5e_activate_txqsq(&c->sq[tc]);
2017 mlx5e_activate_icosq(&c->icosq);
2018 mlx5e_activate_rq(&c->rq);
2019 netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2021 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2022 mlx5e_activate_xsk(c);
2025 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2029 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2030 mlx5e_deactivate_xsk(c);
2032 mlx5e_deactivate_rq(&c->rq);
2033 mlx5e_deactivate_icosq(&c->icosq);
2034 for (tc = 0; tc < c->num_tc; tc++)
2035 mlx5e_deactivate_txqsq(&c->sq[tc]);
2038 static void mlx5e_close_channel(struct mlx5e_channel *c)
2040 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2042 mlx5e_close_queues(c);
2043 netif_napi_del(&c->napi);
2044 mlx5e_free_xps_cpumask(c);
2049 #define DEFAULT_FRAG_SIZE (2048)
2051 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2052 struct mlx5e_params *params,
2053 struct mlx5e_xsk_param *xsk,
2054 struct mlx5e_rq_frags_info *info)
2056 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2057 int frag_size_max = DEFAULT_FRAG_SIZE;
2061 #ifdef CONFIG_MLX5_EN_IPSEC
2062 if (MLX5_IPSEC_DEV(mdev))
2063 byte_count += MLX5E_METADATA_ETHER_LEN;
2066 if (mlx5e_rx_is_linear_skb(params, xsk)) {
2069 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2070 frag_stride = roundup_pow_of_two(frag_stride);
2072 info->arr[0].frag_size = byte_count;
2073 info->arr[0].frag_stride = frag_stride;
2074 info->num_frags = 1;
2075 info->wqe_bulk = PAGE_SIZE / frag_stride;
2079 if (byte_count > PAGE_SIZE +
2080 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2081 frag_size_max = PAGE_SIZE;
2084 while (buf_size < byte_count) {
2085 int frag_size = byte_count - buf_size;
2087 if (i < MLX5E_MAX_RX_FRAGS - 1)
2088 frag_size = min(frag_size, frag_size_max);
2090 info->arr[i].frag_size = frag_size;
2091 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2093 buf_size += frag_size;
2096 info->num_frags = i;
2097 /* number of different wqes sharing a page */
2098 info->wqe_bulk = 1 + (info->num_frags % 2);
2101 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2102 info->log_num_frags = order_base_2(info->num_frags);
2105 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2107 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2110 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2111 sz += sizeof(struct mlx5e_rx_wqe_ll);
2113 default: /* MLX5_WQ_TYPE_CYCLIC */
2114 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2117 return order_base_2(sz);
2120 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2122 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2124 return MLX5_GET(wq, wq, log_wq_sz);
2127 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2128 struct mlx5e_params *params,
2129 struct mlx5e_xsk_param *xsk,
2130 struct mlx5e_rq_param *param)
2132 struct mlx5_core_dev *mdev = priv->mdev;
2133 void *rqc = param->rqc;
2134 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2137 switch (params->rq_wq_type) {
2138 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2139 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2140 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2141 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2142 MLX5_SET(wq, wq, log_wqe_stride_size,
2143 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2144 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2145 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2147 default: /* MLX5_WQ_TYPE_CYCLIC */
2148 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2149 mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info);
2150 ndsegs = param->frags_info.num_frags;
2153 MLX5_SET(wq, wq, wq_type, params->rq_wq_type);
2154 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2155 MLX5_SET(wq, wq, log_wq_stride,
2156 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2157 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
2158 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2159 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
2160 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
2162 param->wq.buf_numa_node = dev_to_node(mdev->device);
2165 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2166 struct mlx5e_rq_param *param)
2168 struct mlx5_core_dev *mdev = priv->mdev;
2169 void *rqc = param->rqc;
2170 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2172 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2173 MLX5_SET(wq, wq, log_wq_stride,
2174 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2175 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2177 param->wq.buf_numa_node = dev_to_node(mdev->device);
2180 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2181 struct mlx5e_sq_param *param)
2183 void *sqc = param->sqc;
2184 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2186 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2187 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
2189 param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2192 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2193 struct mlx5e_params *params,
2194 struct mlx5e_sq_param *param)
2196 void *sqc = param->sqc;
2197 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2200 allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2201 !!MLX5_IPSEC_DEV(priv->mdev);
2202 mlx5e_build_sq_param_common(priv, param);
2203 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2204 MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2207 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2208 struct mlx5e_cq_param *param)
2210 void *cqc = param->cqc;
2212 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2213 if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2214 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2217 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2218 struct mlx5e_params *params,
2219 struct mlx5e_xsk_param *xsk,
2220 struct mlx5e_cq_param *param)
2222 struct mlx5_core_dev *mdev = priv->mdev;
2223 void *cqc = param->cqc;
2226 switch (params->rq_wq_type) {
2227 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2228 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2229 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2231 default: /* MLX5_WQ_TYPE_CYCLIC */
2232 log_cq_size = params->log_rq_mtu_frames;
2235 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2236 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2237 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2238 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2241 mlx5e_build_common_cq_param(priv, param);
2242 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2245 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2246 struct mlx5e_params *params,
2247 struct mlx5e_cq_param *param)
2249 void *cqc = param->cqc;
2251 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2253 mlx5e_build_common_cq_param(priv, param);
2254 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2257 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2259 struct mlx5e_cq_param *param)
2261 void *cqc = param->cqc;
2263 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2265 mlx5e_build_common_cq_param(priv, param);
2267 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2270 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2272 struct mlx5e_sq_param *param)
2274 void *sqc = param->sqc;
2275 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2277 mlx5e_build_sq_param_common(priv, param);
2279 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2280 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2283 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2284 struct mlx5e_params *params,
2285 struct mlx5e_sq_param *param)
2287 void *sqc = param->sqc;
2288 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2290 mlx5e_build_sq_param_common(priv, param);
2291 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2292 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2295 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2296 struct mlx5e_rq_param *rqp)
2298 switch (params->rq_wq_type) {
2299 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2300 return order_base_2(MLX5E_UMR_WQEBBS) +
2301 mlx5e_get_rq_log_wq_sz(rqp->rqc);
2302 default: /* MLX5_WQ_TYPE_CYCLIC */
2303 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2307 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2308 struct mlx5e_params *params,
2309 struct mlx5e_channel_param *cparam)
2313 mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2315 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2317 mlx5e_build_sq_param(priv, params, &cparam->sq);
2318 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2319 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2320 mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2321 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2322 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2325 int mlx5e_open_channels(struct mlx5e_priv *priv,
2326 struct mlx5e_channels *chs)
2328 struct mlx5e_channel_param *cparam;
2332 chs->num = chs->params.num_channels;
2334 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2335 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2336 if (!chs->c || !cparam)
2339 mlx5e_build_channel_param(priv, &chs->params, cparam);
2340 for (i = 0; i < chs->num; i++) {
2341 struct xdp_umem *umem = NULL;
2343 if (chs->params.xdp_prog)
2344 umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2346 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2348 goto err_close_channels;
2351 mlx5e_health_channels_update(priv);
2356 for (i--; i >= 0; i--)
2357 mlx5e_close_channel(chs->c[i]);
2366 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2370 for (i = 0; i < chs->num; i++)
2371 mlx5e_activate_channel(chs->c[i]);
2374 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2376 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2381 for (i = 0; i < chs->num; i++) {
2382 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2384 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2386 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2387 * doesn't provide any Fill Ring entries at the setup stage.
2391 return err ? -ETIMEDOUT : 0;
2394 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2398 for (i = 0; i < chs->num; i++)
2399 mlx5e_deactivate_channel(chs->c[i]);
2402 void mlx5e_close_channels(struct mlx5e_channels *chs)
2406 for (i = 0; i < chs->num; i++)
2407 mlx5e_close_channel(chs->c[i]);
2414 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2416 struct mlx5_core_dev *mdev = priv->mdev;
2423 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2424 in = kvzalloc(inlen, GFP_KERNEL);
2428 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2430 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2431 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2433 for (i = 0; i < sz; i++)
2434 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2436 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2438 rqt->enabled = true;
2444 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2446 rqt->enabled = false;
2447 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2450 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2452 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2455 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2457 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2461 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2466 for (ix = 0; ix < priv->max_nch; ix++) {
2467 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2469 goto err_destroy_rqts;
2475 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2476 for (ix--; ix >= 0; ix--)
2477 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2482 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2486 for (i = 0; i < priv->max_nch; i++)
2487 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2490 static int mlx5e_rx_hash_fn(int hfunc)
2492 return (hfunc == ETH_RSS_HASH_TOP) ?
2493 MLX5_RX_HASH_FN_TOEPLITZ :
2494 MLX5_RX_HASH_FN_INVERTED_XOR8;
2497 int mlx5e_bits_invert(unsigned long a, int size)
2502 for (i = 0; i < size; i++)
2503 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2508 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2509 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2513 for (i = 0; i < sz; i++) {
2519 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2520 ix = mlx5e_bits_invert(i, ilog2(sz));
2522 ix = priv->rss_params.indirection_rqt[ix];
2523 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2527 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2531 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2532 struct mlx5e_redirect_rqt_param rrp)
2534 struct mlx5_core_dev *mdev = priv->mdev;
2540 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2541 in = kvzalloc(inlen, GFP_KERNEL);
2545 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2547 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2548 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2549 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2550 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2556 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2557 struct mlx5e_redirect_rqt_param rrp)
2562 if (ix >= rrp.rss.channels->num)
2563 return priv->drop_rq.rqn;
2565 return rrp.rss.channels->c[ix]->rq.rqn;
2568 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2569 struct mlx5e_redirect_rqt_param rrp)
2574 if (priv->indir_rqt.enabled) {
2576 rqtn = priv->indir_rqt.rqtn;
2577 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2580 for (ix = 0; ix < priv->max_nch; ix++) {
2581 struct mlx5e_redirect_rqt_param direct_rrp = {
2584 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2588 /* Direct RQ Tables */
2589 if (!priv->direct_tir[ix].rqt.enabled)
2592 rqtn = priv->direct_tir[ix].rqt.rqtn;
2593 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2597 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2598 struct mlx5e_channels *chs)
2600 struct mlx5e_redirect_rqt_param rrp = {
2605 .hfunc = priv->rss_params.hfunc,
2610 mlx5e_redirect_rqts(priv, rrp);
2613 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2615 struct mlx5e_redirect_rqt_param drop_rrp = {
2618 .rqn = priv->drop_rq.rqn,
2622 mlx5e_redirect_rqts(priv, drop_rrp);
2625 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2626 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2627 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2628 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2630 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2631 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2632 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2634 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2635 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2636 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2638 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2639 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2640 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2642 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2644 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2646 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2648 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2650 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2652 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2654 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2656 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2658 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2660 .rx_hash_fields = MLX5_HASH_IP,
2662 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2664 .rx_hash_fields = MLX5_HASH_IP,
2668 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2670 return tirc_default_config[tt];
2673 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2675 if (!params->lro_en)
2678 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2680 MLX5_SET(tirc, tirc, lro_enable_mask,
2681 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2682 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2683 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2684 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2685 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2688 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2689 const struct mlx5e_tirc_config *ttconfig,
2690 void *tirc, bool inner)
2692 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2693 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2695 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2696 if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2697 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2698 rx_hash_toeplitz_key);
2699 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2700 rx_hash_toeplitz_key);
2702 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2703 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2705 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2706 ttconfig->l3_prot_type);
2707 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2708 ttconfig->l4_prot_type);
2709 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710 ttconfig->rx_hash_fields);
2713 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2714 enum mlx5e_traffic_types tt,
2717 *ttconfig = tirc_default_config[tt];
2718 ttconfig->rx_hash_fields = rx_hash_fields;
2721 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2723 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2724 struct mlx5e_rss_params *rss = &priv->rss_params;
2725 struct mlx5_core_dev *mdev = priv->mdev;
2726 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2727 struct mlx5e_tirc_config ttconfig;
2730 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2732 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2733 memset(tirc, 0, ctxlen);
2734 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2735 rss->rx_hash_fields[tt]);
2736 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2737 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2740 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2743 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2744 memset(tirc, 0, ctxlen);
2745 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2746 rss->rx_hash_fields[tt]);
2747 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2748 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2753 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2755 struct mlx5_core_dev *mdev = priv->mdev;
2764 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2765 in = kvzalloc(inlen, GFP_KERNEL);
2769 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2770 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2772 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2774 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2775 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2781 for (ix = 0; ix < priv->max_nch; ix++) {
2782 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2794 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2795 struct mlx5e_params *params, u16 mtu)
2797 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2800 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2804 /* Update vport context MTU */
2805 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2809 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2810 struct mlx5e_params *params, u16 *mtu)
2815 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2816 if (err || !hw_mtu) /* fallback to port oper mtu */
2817 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2819 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2822 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2824 struct mlx5e_params *params = &priv->channels.params;
2825 struct net_device *netdev = priv->netdev;
2826 struct mlx5_core_dev *mdev = priv->mdev;
2830 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2834 mlx5e_query_mtu(mdev, params, &mtu);
2835 if (mtu != params->sw_mtu)
2836 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2837 __func__, mtu, params->sw_mtu);
2839 params->sw_mtu = mtu;
2843 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2845 struct mlx5e_params *params = &priv->channels.params;
2846 struct net_device *netdev = priv->netdev;
2847 struct mlx5_core_dev *mdev = priv->mdev;
2850 /* MTU range: 68 - hw-specific max */
2851 netdev->min_mtu = ETH_MIN_MTU;
2853 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2854 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2858 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2860 struct mlx5e_priv *priv = netdev_priv(netdev);
2861 int nch = priv->channels.params.num_channels;
2862 int ntc = priv->channels.params.num_tc;
2865 netdev_reset_tc(netdev);
2870 netdev_set_num_tc(netdev, ntc);
2872 /* Map netdev TCs to offset 0
2873 * We have our own UP to TXQ mapping for QoS
2875 for (tc = 0; tc < ntc; tc++)
2876 netdev_set_tc_queue(netdev, tc, nch, 0);
2879 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2883 for (i = 0; i < priv->max_nch; i++)
2884 for (tc = 0; tc < priv->profile->max_tc; tc++)
2885 priv->channel_tc2txq[i][tc] = i + tc * priv->max_nch;
2888 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2890 struct mlx5e_channel *c;
2891 struct mlx5e_txqsq *sq;
2894 for (i = 0; i < priv->channels.num; i++) {
2895 c = priv->channels.c[i];
2896 for (tc = 0; tc < c->num_tc; tc++) {
2898 priv->txq2sq[sq->txq_ix] = sq;
2903 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2905 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2906 int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2907 struct net_device *netdev = priv->netdev;
2909 mlx5e_netdev_set_tcs(netdev);
2910 netif_set_real_num_tx_queues(netdev, num_txqs);
2911 netif_set_real_num_rx_queues(netdev, num_rxqs);
2913 mlx5e_build_tx2sq_maps(priv);
2914 mlx5e_activate_channels(&priv->channels);
2915 mlx5e_xdp_tx_enable(priv);
2916 netif_tx_start_all_queues(priv->netdev);
2918 if (mlx5e_is_vport_rep(priv))
2919 mlx5e_add_sqs_fwd_rules(priv);
2921 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2922 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2924 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2927 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2929 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2931 mlx5e_redirect_rqts_to_drop(priv);
2933 if (mlx5e_is_vport_rep(priv))
2934 mlx5e_remove_sqs_fwd_rules(priv);
2936 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2937 * polling for inactive tx queues.
2939 netif_tx_stop_all_queues(priv->netdev);
2940 netif_tx_disable(priv->netdev);
2941 mlx5e_xdp_tx_disable(priv);
2942 mlx5e_deactivate_channels(&priv->channels);
2945 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2946 struct mlx5e_channels *new_chs,
2947 mlx5e_fp_hw_modify hw_modify)
2949 struct net_device *netdev = priv->netdev;
2953 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2955 carrier_ok = netif_carrier_ok(netdev);
2956 netif_carrier_off(netdev);
2958 if (new_num_txqs < netdev->real_num_tx_queues)
2959 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2961 mlx5e_deactivate_priv_channels(priv);
2962 mlx5e_close_channels(&priv->channels);
2964 priv->channels = *new_chs;
2966 /* New channels are ready to roll, modify HW settings if needed */
2970 priv->profile->update_rx(priv);
2971 mlx5e_activate_priv_channels(priv);
2973 /* return carrier back if needed */
2975 netif_carrier_on(netdev);
2978 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2979 struct mlx5e_channels *new_chs,
2980 mlx5e_fp_hw_modify hw_modify)
2984 err = mlx5e_open_channels(priv, new_chs);
2988 mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2992 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2994 struct mlx5e_channels new_channels = {};
2996 new_channels.params = priv->channels.params;
2997 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3000 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3002 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
3003 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3006 int mlx5e_open_locked(struct net_device *netdev)
3008 struct mlx5e_priv *priv = netdev_priv(netdev);
3009 bool is_xdp = priv->channels.params.xdp_prog;
3012 set_bit(MLX5E_STATE_OPENED, &priv->state);
3014 mlx5e_xdp_set_open(priv);
3016 err = mlx5e_open_channels(priv, &priv->channels);
3018 goto err_clear_state_opened_flag;
3020 priv->profile->update_rx(priv);
3021 mlx5e_activate_priv_channels(priv);
3022 if (priv->profile->update_carrier)
3023 priv->profile->update_carrier(priv);
3025 mlx5e_queue_update_stats(priv);
3028 err_clear_state_opened_flag:
3030 mlx5e_xdp_set_closed(priv);
3031 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3035 int mlx5e_open(struct net_device *netdev)
3037 struct mlx5e_priv *priv = netdev_priv(netdev);
3040 mutex_lock(&priv->state_lock);
3041 err = mlx5e_open_locked(netdev);
3043 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3044 mutex_unlock(&priv->state_lock);
3046 if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3047 udp_tunnel_get_rx_info(netdev);
3052 int mlx5e_close_locked(struct net_device *netdev)
3054 struct mlx5e_priv *priv = netdev_priv(netdev);
3056 /* May already be CLOSED in case a previous configuration operation
3057 * (e.g RX/TX queue size change) that involves close&open failed.
3059 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3062 if (priv->channels.params.xdp_prog)
3063 mlx5e_xdp_set_closed(priv);
3064 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3066 netif_carrier_off(priv->netdev);
3067 mlx5e_deactivate_priv_channels(priv);
3068 mlx5e_close_channels(&priv->channels);
3073 int mlx5e_close(struct net_device *netdev)
3075 struct mlx5e_priv *priv = netdev_priv(netdev);
3078 if (!netif_device_present(netdev))
3081 mutex_lock(&priv->state_lock);
3082 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3083 err = mlx5e_close_locked(netdev);
3084 mutex_unlock(&priv->state_lock);
3089 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3090 struct mlx5e_rq *rq,
3091 struct mlx5e_rq_param *param)
3093 void *rqc = param->rqc;
3094 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3097 param->wq.db_numa_node = param->wq.buf_numa_node;
3099 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq,
3104 /* Mark as unused given "Drop-RQ" packets never reach XDP */
3105 xdp_rxq_info_unused(&rq->xdp_rxq);
3112 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3113 struct mlx5e_cq *cq,
3114 struct mlx5e_cq_param *param)
3116 param->wq.buf_numa_node = dev_to_node(mdev->device);
3117 param->wq.db_numa_node = dev_to_node(mdev->device);
3119 return mlx5e_alloc_cq_common(mdev, param, cq);
3122 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3123 struct mlx5e_rq *drop_rq)
3125 struct mlx5_core_dev *mdev = priv->mdev;
3126 struct mlx5e_cq_param cq_param = {};
3127 struct mlx5e_rq_param rq_param = {};
3128 struct mlx5e_cq *cq = &drop_rq->cq;
3131 mlx5e_build_drop_rq_param(priv, &rq_param);
3133 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3137 err = mlx5e_create_cq(cq, &cq_param);
3141 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3143 goto err_destroy_cq;
3145 err = mlx5e_create_rq(drop_rq, &rq_param);
3149 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3151 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3156 mlx5e_free_rq(drop_rq);
3159 mlx5e_destroy_cq(cq);
3167 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3169 mlx5e_destroy_rq(drop_rq);
3170 mlx5e_free_rq(drop_rq);
3171 mlx5e_destroy_cq(&drop_rq->cq);
3172 mlx5e_free_cq(&drop_rq->cq);
3175 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3177 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3179 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3181 if (MLX5_GET(tisc, tisc, tls_en))
3182 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3184 if (mlx5_lag_is_lacp_owner(mdev))
3185 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3187 return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3190 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3192 mlx5_core_destroy_tis(mdev, tisn);
3195 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3199 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3200 for (tc = 0; tc < priv->profile->max_tc; tc++)
3201 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3204 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3206 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3209 int mlx5e_create_tises(struct mlx5e_priv *priv)
3214 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3215 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3216 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3219 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3221 MLX5_SET(tisc, tisc, prio, tc << 1);
3223 if (mlx5e_lag_should_assign_affinity(priv->mdev))
3224 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3226 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3228 goto err_close_tises;
3235 for (; i >= 0; i--) {
3236 for (tc--; tc >= 0; tc--)
3237 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3238 tc = priv->profile->max_tc;
3244 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3246 mlx5e_destroy_tises(priv);
3249 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3250 u32 rqtn, u32 *tirc)
3252 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3253 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3254 MLX5_SET(tirc, tirc, indirect_table, rqtn);
3255 MLX5_SET(tirc, tirc, tunneled_offload_en,
3256 priv->channels.params.tunneled_offload_en);
3258 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3261 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3262 enum mlx5e_traffic_types tt,
3265 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3266 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3267 &tirc_default_config[tt], tirc, false);
3270 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3272 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3273 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3276 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3277 enum mlx5e_traffic_types tt,
3280 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3281 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3282 &tirc_default_config[tt], tirc, true);
3285 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3287 struct mlx5e_tir *tir;
3295 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3296 in = kvzalloc(inlen, GFP_KERNEL);
3300 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3301 memset(in, 0, inlen);
3302 tir = &priv->indir_tir[tt];
3303 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3304 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3305 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3307 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3308 goto err_destroy_inner_tirs;
3312 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3315 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3316 memset(in, 0, inlen);
3317 tir = &priv->inner_indir_tir[i];
3318 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3319 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3320 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3322 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3323 goto err_destroy_inner_tirs;
3332 err_destroy_inner_tirs:
3333 for (i--; i >= 0; i--)
3334 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3336 for (tt--; tt >= 0; tt--)
3337 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3344 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3346 struct mlx5e_tir *tir;
3353 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3354 in = kvzalloc(inlen, GFP_KERNEL);
3358 for (ix = 0; ix < priv->max_nch; ix++) {
3359 memset(in, 0, inlen);
3361 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3362 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3363 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3365 goto err_destroy_ch_tirs;
3370 err_destroy_ch_tirs:
3371 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3372 for (ix--; ix >= 0; ix--)
3373 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3381 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3385 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3386 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3388 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3391 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3392 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3395 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3399 for (i = 0; i < priv->max_nch; i++)
3400 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3403 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3408 for (i = 0; i < chs->num; i++) {
3409 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3417 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3422 for (i = 0; i < chs->num; i++) {
3423 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3431 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3432 struct tc_mqprio_qopt *mqprio)
3434 struct mlx5e_channels new_channels = {};
3435 u8 tc = mqprio->num_tc;
3438 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3440 if (tc && tc != MLX5E_MAX_NUM_TC)
3443 mutex_lock(&priv->state_lock);
3445 new_channels.params = priv->channels.params;
3446 new_channels.params.num_tc = tc ? tc : 1;
3448 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3449 priv->channels.params = new_channels.params;
3453 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3457 priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3458 new_channels.params.num_tc);
3460 mutex_unlock(&priv->state_lock);
3464 #ifdef CONFIG_MLX5_ESWITCH
3465 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3466 struct flow_cls_offload *cls_flower,
3467 unsigned long flags)
3469 switch (cls_flower->command) {
3470 case FLOW_CLS_REPLACE:
3471 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3473 case FLOW_CLS_DESTROY:
3474 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3476 case FLOW_CLS_STATS:
3477 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3484 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3487 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3488 struct mlx5e_priv *priv = cb_priv;
3491 case TC_SETUP_CLSFLOWER:
3492 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3499 static LIST_HEAD(mlx5e_block_cb_list);
3501 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3504 struct mlx5e_priv *priv = netdev_priv(dev);
3507 #ifdef CONFIG_MLX5_ESWITCH
3508 case TC_SETUP_BLOCK: {
3509 struct flow_block_offload *f = type_data;
3511 f->unlocked_driver_cb = true;
3512 return flow_block_cb_setup_simple(type_data,
3513 &mlx5e_block_cb_list,
3514 mlx5e_setup_tc_block_cb,
3518 case TC_SETUP_QDISC_MQPRIO:
3519 return mlx5e_setup_tc_mqprio(priv, type_data);
3525 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3529 for (i = 0; i < priv->max_nch; i++) {
3530 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3531 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3532 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3535 s->rx_packets += rq_stats->packets + xskrq_stats->packets;
3536 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes;
3538 for (j = 0; j < priv->max_opened_tc; j++) {
3539 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3541 s->tx_packets += sq_stats->packets;
3542 s->tx_bytes += sq_stats->bytes;
3543 s->tx_dropped += sq_stats->dropped;
3549 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3551 struct mlx5e_priv *priv = netdev_priv(dev);
3552 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3553 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3555 if (!mlx5e_monitor_counter_supported(priv)) {
3556 /* update HW stats in background for next time */
3557 mlx5e_queue_update_stats(priv);
3560 if (mlx5e_is_uplink_rep(priv)) {
3561 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3562 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3563 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3564 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3566 mlx5e_fold_sw_stats64(priv, stats);
3569 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3571 stats->rx_length_errors =
3572 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3573 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3574 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3575 stats->rx_crc_errors =
3576 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3577 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3578 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3579 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3580 stats->rx_frame_errors;
3581 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3583 /* vport multicast also counts packets that are dropped due to steering
3584 * or rx out of buffer
3587 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3590 static void mlx5e_set_rx_mode(struct net_device *dev)
3592 struct mlx5e_priv *priv = netdev_priv(dev);
3594 queue_work(priv->wq, &priv->set_rx_mode_work);
3597 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3599 struct mlx5e_priv *priv = netdev_priv(netdev);
3600 struct sockaddr *saddr = addr;
3602 if (!is_valid_ether_addr(saddr->sa_data))
3603 return -EADDRNOTAVAIL;
3605 netif_addr_lock_bh(netdev);
3606 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3607 netif_addr_unlock_bh(netdev);
3609 queue_work(priv->wq, &priv->set_rx_mode_work);
3614 #define MLX5E_SET_FEATURE(features, feature, enable) \
3617 *features |= feature; \
3619 *features &= ~feature; \
3622 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3624 static int set_feature_lro(struct net_device *netdev, bool enable)
3626 struct mlx5e_priv *priv = netdev_priv(netdev);
3627 struct mlx5_core_dev *mdev = priv->mdev;
3628 struct mlx5e_channels new_channels = {};
3629 struct mlx5e_params *old_params;
3633 mutex_lock(&priv->state_lock);
3635 if (enable && priv->xsk.refcnt) {
3636 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3642 old_params = &priv->channels.params;
3643 if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3644 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3649 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3651 new_channels.params = *old_params;
3652 new_channels.params.lro_en = enable;
3654 if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3655 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3656 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3661 *old_params = new_channels.params;
3662 err = mlx5e_modify_tirs_lro(priv);
3666 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3668 mutex_unlock(&priv->state_lock);
3672 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3674 struct mlx5e_priv *priv = netdev_priv(netdev);
3677 mlx5e_enable_cvlan_filter(priv);
3679 mlx5e_disable_cvlan_filter(priv);
3684 #ifdef CONFIG_MLX5_ESWITCH
3685 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3687 struct mlx5e_priv *priv = netdev_priv(netdev);
3689 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3691 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3699 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3701 struct mlx5e_priv *priv = netdev_priv(netdev);
3702 struct mlx5_core_dev *mdev = priv->mdev;
3704 return mlx5_set_port_fcs(mdev, !enable);
3707 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3709 struct mlx5e_priv *priv = netdev_priv(netdev);
3712 mutex_lock(&priv->state_lock);
3714 priv->channels.params.scatter_fcs_en = enable;
3715 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3717 priv->channels.params.scatter_fcs_en = !enable;
3719 mutex_unlock(&priv->state_lock);
3724 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3726 struct mlx5e_priv *priv = netdev_priv(netdev);
3729 mutex_lock(&priv->state_lock);
3731 priv->channels.params.vlan_strip_disable = !enable;
3732 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3735 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3737 priv->channels.params.vlan_strip_disable = enable;
3740 mutex_unlock(&priv->state_lock);
3745 #ifdef CONFIG_MLX5_EN_ARFS
3746 static int set_feature_arfs(struct net_device *netdev, bool enable)
3748 struct mlx5e_priv *priv = netdev_priv(netdev);
3752 err = mlx5e_arfs_enable(priv);
3754 err = mlx5e_arfs_disable(priv);
3760 static int mlx5e_handle_feature(struct net_device *netdev,
3761 netdev_features_t *features,
3762 netdev_features_t wanted_features,
3763 netdev_features_t feature,
3764 mlx5e_feature_handler feature_handler)
3766 netdev_features_t changes = wanted_features ^ netdev->features;
3767 bool enable = !!(wanted_features & feature);
3770 if (!(changes & feature))
3773 err = feature_handler(netdev, enable);
3775 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3776 enable ? "Enable" : "Disable", &feature, err);
3780 MLX5E_SET_FEATURE(features, feature, enable);
3784 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3786 netdev_features_t oper_features = netdev->features;
3789 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3790 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3792 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3793 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3794 set_feature_cvlan_filter);
3795 #ifdef CONFIG_MLX5_ESWITCH
3796 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3798 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3799 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3800 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3801 #ifdef CONFIG_MLX5_EN_ARFS
3802 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3806 netdev->features = oper_features;
3813 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3814 netdev_features_t features)
3816 struct mlx5e_priv *priv = netdev_priv(netdev);
3817 struct mlx5e_params *params;
3819 mutex_lock(&priv->state_lock);
3820 params = &priv->channels.params;
3821 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3822 /* HW strips the outer C-tag header, this is a problem
3823 * for S-tag traffic.
3825 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3826 if (!params->vlan_strip_disable)
3827 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3829 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3830 if (features & NETIF_F_LRO) {
3831 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3832 features &= ~NETIF_F_LRO;
3836 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3837 features &= ~NETIF_F_RXHASH;
3838 if (netdev->features & NETIF_F_RXHASH)
3839 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3842 mutex_unlock(&priv->state_lock);
3847 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3848 struct mlx5e_channels *chs,
3849 struct mlx5e_params *new_params,
3850 struct mlx5_core_dev *mdev)
3854 for (ix = 0; ix < chs->params.num_channels; ix++) {
3855 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3856 struct mlx5e_xsk_param xsk;
3861 mlx5e_build_xsk_param(umem, &xsk);
3863 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3864 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3865 int max_mtu_frame, max_mtu_page, max_mtu;
3867 /* Two criteria must be met:
3868 * 1. HW MTU + all headrooms <= XSK frame size.
3869 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3871 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3872 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3873 max_mtu = min(max_mtu_frame, max_mtu_page);
3875 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3876 new_params->sw_mtu, ix, max_mtu);
3884 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3885 change_hw_mtu_cb set_mtu_cb)
3887 struct mlx5e_priv *priv = netdev_priv(netdev);
3888 struct mlx5e_channels new_channels = {};
3889 struct mlx5e_params *params;
3893 mutex_lock(&priv->state_lock);
3895 params = &priv->channels.params;
3897 reset = !params->lro_en;
3898 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3900 new_channels.params = *params;
3901 new_channels.params.sw_mtu = new_mtu;
3903 if (params->xdp_prog &&
3904 !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3905 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3906 new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3911 if (priv->xsk.refcnt &&
3912 !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3913 &new_channels.params, priv->mdev)) {
3918 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3919 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3920 &new_channels.params,
3922 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3923 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3925 /* If XSK is active, XSK RQs are linear. */
3926 is_linear |= priv->xsk.refcnt;
3928 /* Always reset in linear mode - hw_mtu is used in data path. */
3929 reset = reset && (is_linear || (ppw_old != ppw_new));
3933 params->sw_mtu = new_mtu;
3936 netdev->mtu = params->sw_mtu;
3940 err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3944 netdev->mtu = new_channels.params.sw_mtu;
3947 mutex_unlock(&priv->state_lock);
3951 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3953 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3956 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3958 struct hwtstamp_config config;
3961 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3962 (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3965 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3968 /* TX HW timestamp */
3969 switch (config.tx_type) {
3970 case HWTSTAMP_TX_OFF:
3971 case HWTSTAMP_TX_ON:
3977 mutex_lock(&priv->state_lock);
3978 /* RX HW timestamp */
3979 switch (config.rx_filter) {
3980 case HWTSTAMP_FILTER_NONE:
3981 /* Reset CQE compression to Admin default */
3982 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3984 case HWTSTAMP_FILTER_ALL:
3985 case HWTSTAMP_FILTER_SOME:
3986 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3987 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3988 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3989 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3990 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3991 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3992 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3993 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3994 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3995 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3996 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3997 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3998 case HWTSTAMP_FILTER_NTP_ALL:
3999 /* Disable CQE compression */
4000 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4001 netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4002 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4004 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4005 mutex_unlock(&priv->state_lock);
4008 config.rx_filter = HWTSTAMP_FILTER_ALL;
4011 mutex_unlock(&priv->state_lock);
4015 memcpy(&priv->tstamp, &config, sizeof(config));
4016 mutex_unlock(&priv->state_lock);
4018 /* might need to fix some features */
4019 netdev_update_features(priv->netdev);
4021 return copy_to_user(ifr->ifr_data, &config,
4022 sizeof(config)) ? -EFAULT : 0;
4025 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4027 struct hwtstamp_config *cfg = &priv->tstamp;
4029 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4032 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4035 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4037 struct mlx5e_priv *priv = netdev_priv(dev);
4041 return mlx5e_hwstamp_set(priv, ifr);
4043 return mlx5e_hwstamp_get(priv, ifr);
4049 #ifdef CONFIG_MLX5_ESWITCH
4050 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4052 struct mlx5e_priv *priv = netdev_priv(dev);
4053 struct mlx5_core_dev *mdev = priv->mdev;
4055 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4058 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4061 struct mlx5e_priv *priv = netdev_priv(dev);
4062 struct mlx5_core_dev *mdev = priv->mdev;
4064 if (vlan_proto != htons(ETH_P_8021Q))
4065 return -EPROTONOSUPPORT;
4067 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4071 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4073 struct mlx5e_priv *priv = netdev_priv(dev);
4074 struct mlx5_core_dev *mdev = priv->mdev;
4076 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4079 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4081 struct mlx5e_priv *priv = netdev_priv(dev);
4082 struct mlx5_core_dev *mdev = priv->mdev;
4084 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4087 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4090 struct mlx5e_priv *priv = netdev_priv(dev);
4091 struct mlx5_core_dev *mdev = priv->mdev;
4093 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4094 max_tx_rate, min_tx_rate);
4097 static int mlx5_vport_link2ifla(u8 esw_link)
4100 case MLX5_VPORT_ADMIN_STATE_DOWN:
4101 return IFLA_VF_LINK_STATE_DISABLE;
4102 case MLX5_VPORT_ADMIN_STATE_UP:
4103 return IFLA_VF_LINK_STATE_ENABLE;
4105 return IFLA_VF_LINK_STATE_AUTO;
4108 static int mlx5_ifla_link2vport(u8 ifla_link)
4110 switch (ifla_link) {
4111 case IFLA_VF_LINK_STATE_DISABLE:
4112 return MLX5_VPORT_ADMIN_STATE_DOWN;
4113 case IFLA_VF_LINK_STATE_ENABLE:
4114 return MLX5_VPORT_ADMIN_STATE_UP;
4116 return MLX5_VPORT_ADMIN_STATE_AUTO;
4119 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4122 struct mlx5e_priv *priv = netdev_priv(dev);
4123 struct mlx5_core_dev *mdev = priv->mdev;
4125 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4126 mlx5_ifla_link2vport(link_state));
4129 int mlx5e_get_vf_config(struct net_device *dev,
4130 int vf, struct ifla_vf_info *ivi)
4132 struct mlx5e_priv *priv = netdev_priv(dev);
4133 struct mlx5_core_dev *mdev = priv->mdev;
4136 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4139 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4143 int mlx5e_get_vf_stats(struct net_device *dev,
4144 int vf, struct ifla_vf_stats *vf_stats)
4146 struct mlx5e_priv *priv = netdev_priv(dev);
4147 struct mlx5_core_dev *mdev = priv->mdev;
4149 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4154 struct mlx5e_vxlan_work {
4155 struct work_struct work;
4156 struct mlx5e_priv *priv;
4160 static void mlx5e_vxlan_add_work(struct work_struct *work)
4162 struct mlx5e_vxlan_work *vxlan_work =
4163 container_of(work, struct mlx5e_vxlan_work, work);
4164 struct mlx5e_priv *priv = vxlan_work->priv;
4165 u16 port = vxlan_work->port;
4167 mutex_lock(&priv->state_lock);
4168 mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4169 mutex_unlock(&priv->state_lock);
4174 static void mlx5e_vxlan_del_work(struct work_struct *work)
4176 struct mlx5e_vxlan_work *vxlan_work =
4177 container_of(work, struct mlx5e_vxlan_work, work);
4178 struct mlx5e_priv *priv = vxlan_work->priv;
4179 u16 port = vxlan_work->port;
4181 mutex_lock(&priv->state_lock);
4182 mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4183 mutex_unlock(&priv->state_lock);
4187 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4189 struct mlx5e_vxlan_work *vxlan_work;
4191 vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4196 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4198 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4200 vxlan_work->priv = priv;
4201 vxlan_work->port = port;
4202 queue_work(priv->wq, &vxlan_work->work);
4205 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4207 struct mlx5e_priv *priv = netdev_priv(netdev);
4209 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4212 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4215 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4218 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4220 struct mlx5e_priv *priv = netdev_priv(netdev);
4222 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4225 if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4228 mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4231 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4232 struct sk_buff *skb,
4233 netdev_features_t features)
4235 unsigned int offset = 0;
4236 struct udphdr *udph;
4240 switch (vlan_get_protocol(skb)) {
4241 case htons(ETH_P_IP):
4242 proto = ip_hdr(skb)->protocol;
4244 case htons(ETH_P_IPV6):
4245 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4256 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4260 udph = udp_hdr(skb);
4261 port = be16_to_cpu(udph->dest);
4263 /* Verify if UDP port is being offloaded by HW */
4264 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4267 #if IS_ENABLED(CONFIG_GENEVE)
4268 /* Support Geneve offload for default UDP port */
4269 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4275 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4276 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4279 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4280 struct net_device *netdev,
4281 netdev_features_t features)
4283 struct mlx5e_priv *priv = netdev_priv(netdev);
4285 features = vlan_features_check(skb, features);
4286 features = vxlan_features_check(skb, features);
4288 #ifdef CONFIG_MLX5_EN_IPSEC
4289 if (mlx5e_ipsec_feature_check(skb, netdev, features))
4293 /* Validate if the tunneled packet is being offloaded by HW */
4294 if (skb->encapsulation &&
4295 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4296 return mlx5e_tunnel_features_check(priv, skb, features);
4301 static void mlx5e_tx_timeout_work(struct work_struct *work)
4303 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4305 bool report_failed = false;
4310 mutex_lock(&priv->state_lock);
4312 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4315 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4316 struct netdev_queue *dev_queue =
4317 netdev_get_tx_queue(priv->netdev, i);
4318 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4320 if (!netif_xmit_stopped(dev_queue))
4323 if (mlx5e_reporter_tx_timeout(sq))
4324 report_failed = true;
4330 err = mlx5e_safe_reopen_channels(priv);
4332 netdev_err(priv->netdev,
4333 "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4337 mutex_unlock(&priv->state_lock);
4341 static void mlx5e_tx_timeout(struct net_device *dev)
4343 struct mlx5e_priv *priv = netdev_priv(dev);
4345 netdev_err(dev, "TX timeout detected\n");
4346 queue_work(priv->wq, &priv->tx_timeout_work);
4349 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4351 struct net_device *netdev = priv->netdev;
4352 struct mlx5e_channels new_channels = {};
4354 if (priv->channels.params.lro_en) {
4355 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4359 if (MLX5_IPSEC_DEV(priv->mdev)) {
4360 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4364 new_channels.params = priv->channels.params;
4365 new_channels.params.xdp_prog = prog;
4367 /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4370 if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4371 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4372 new_channels.params.sw_mtu,
4373 mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4380 static int mlx5e_xdp_update_state(struct mlx5e_priv *priv)
4382 if (priv->channels.params.xdp_prog)
4383 mlx5e_xdp_set_open(priv);
4385 mlx5e_xdp_set_closed(priv);
4390 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4392 struct mlx5e_priv *priv = netdev_priv(netdev);
4393 struct bpf_prog *old_prog;
4394 bool reset, was_opened;
4398 mutex_lock(&priv->state_lock);
4401 err = mlx5e_xdp_allowed(priv, prog);
4406 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4407 /* no need for full reset when exchanging programs */
4408 reset = (!priv->channels.params.xdp_prog || !prog);
4410 if (was_opened && !reset)
4411 /* num_channels is invariant here, so we can take the
4412 * batched reference right upfront.
4414 bpf_prog_add(prog, priv->channels.num);
4416 if (was_opened && reset) {
4417 struct mlx5e_channels new_channels = {};
4419 new_channels.params = priv->channels.params;
4420 new_channels.params.xdp_prog = prog;
4421 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4422 old_prog = priv->channels.params.xdp_prog;
4424 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_xdp_update_state);
4428 /* exchange programs, extra prog reference we got from caller
4429 * as long as we don't fail from this point onwards.
4431 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4435 bpf_prog_put(old_prog);
4437 if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4438 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4440 if (!was_opened || reset)
4443 /* exchanging programs w/o reset, we update ref counts on behalf
4444 * of the channels RQs here.
4446 for (i = 0; i < priv->channels.num; i++) {
4447 struct mlx5e_channel *c = priv->channels.c[i];
4448 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4450 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4452 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4453 napi_synchronize(&c->napi);
4454 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4456 old_prog = xchg(&c->rq.xdp_prog, prog);
4458 bpf_prog_put(old_prog);
4461 old_prog = xchg(&c->xskrq.xdp_prog, prog);
4463 bpf_prog_put(old_prog);
4466 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4468 set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4469 /* napi_schedule in case we have missed anything */
4470 napi_schedule(&c->napi);
4474 mutex_unlock(&priv->state_lock);
4478 static u32 mlx5e_xdp_query(struct net_device *dev)
4480 struct mlx5e_priv *priv = netdev_priv(dev);
4481 const struct bpf_prog *xdp_prog;
4484 mutex_lock(&priv->state_lock);
4485 xdp_prog = priv->channels.params.xdp_prog;
4487 prog_id = xdp_prog->aux->id;
4488 mutex_unlock(&priv->state_lock);
4493 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4495 switch (xdp->command) {
4496 case XDP_SETUP_PROG:
4497 return mlx5e_xdp_set(dev, xdp->prog);
4498 case XDP_QUERY_PROG:
4499 xdp->prog_id = mlx5e_xdp_query(dev);
4501 case XDP_SETUP_XSK_UMEM:
4502 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4509 #ifdef CONFIG_MLX5_ESWITCH
4510 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4511 struct net_device *dev, u32 filter_mask,
4514 struct mlx5e_priv *priv = netdev_priv(dev);
4515 struct mlx5_core_dev *mdev = priv->mdev;
4519 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4522 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4523 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4525 0, 0, nlflags, filter_mask, NULL);
4528 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4529 u16 flags, struct netlink_ext_ack *extack)
4531 struct mlx5e_priv *priv = netdev_priv(dev);
4532 struct mlx5_core_dev *mdev = priv->mdev;
4533 struct nlattr *attr, *br_spec;
4534 u16 mode = BRIDGE_MODE_UNDEF;
4538 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4542 nla_for_each_nested(attr, br_spec, rem) {
4543 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4546 if (nla_len(attr) < sizeof(mode))
4549 mode = nla_get_u16(attr);
4550 if (mode > BRIDGE_MODE_VEPA)
4556 if (mode == BRIDGE_MODE_UNDEF)
4559 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0;
4560 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4564 const struct net_device_ops mlx5e_netdev_ops = {
4565 .ndo_open = mlx5e_open,
4566 .ndo_stop = mlx5e_close,
4567 .ndo_start_xmit = mlx5e_xmit,
4568 .ndo_setup_tc = mlx5e_setup_tc,
4569 .ndo_select_queue = mlx5e_select_queue,
4570 .ndo_get_stats64 = mlx5e_get_stats,
4571 .ndo_set_rx_mode = mlx5e_set_rx_mode,
4572 .ndo_set_mac_address = mlx5e_set_mac,
4573 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
4574 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
4575 .ndo_set_features = mlx5e_set_features,
4576 .ndo_fix_features = mlx5e_fix_features,
4577 .ndo_change_mtu = mlx5e_change_nic_mtu,
4578 .ndo_do_ioctl = mlx5e_ioctl,
4579 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
4580 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
4581 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
4582 .ndo_features_check = mlx5e_features_check,
4583 .ndo_tx_timeout = mlx5e_tx_timeout,
4584 .ndo_bpf = mlx5e_xdp,
4585 .ndo_xdp_xmit = mlx5e_xdp_xmit,
4586 .ndo_xsk_wakeup = mlx5e_xsk_wakeup,
4587 #ifdef CONFIG_MLX5_EN_ARFS
4588 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
4590 #ifdef CONFIG_MLX5_ESWITCH
4591 .ndo_bridge_setlink = mlx5e_bridge_setlink,
4592 .ndo_bridge_getlink = mlx5e_bridge_getlink,
4594 /* SRIOV E-Switch NDOs */
4595 .ndo_set_vf_mac = mlx5e_set_vf_mac,
4596 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
4597 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
4598 .ndo_set_vf_trust = mlx5e_set_vf_trust,
4599 .ndo_set_vf_rate = mlx5e_set_vf_rate,
4600 .ndo_get_vf_config = mlx5e_get_vf_config,
4601 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
4602 .ndo_get_vf_stats = mlx5e_get_vf_stats,
4606 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4608 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4610 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4611 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4612 !MLX5_CAP_ETH(mdev, csum_cap) ||
4613 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4614 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4615 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4616 MLX5_CAP_FLOWTABLE(mdev,
4617 flow_table_properties_nic_receive.max_ft_level)
4619 mlx5_core_warn(mdev,
4620 "Not creating net device, some required device capabilities are missing\n");
4623 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4624 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4625 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4626 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4631 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4636 for (i = 0; i < len; i++)
4637 indirection_rqt[i] = i % num_channels;
4640 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4645 mlx5e_port_max_linkspeed(mdev, &link_speed);
4646 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4647 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4648 link_speed, pci_bw);
4650 #define MLX5E_SLOW_PCI_RATIO (2)
4652 return link_speed && pci_bw &&
4653 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4656 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4658 struct dim_cq_moder moder;
4660 moder.cq_period_mode = cq_period_mode;
4661 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4662 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4663 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4664 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4669 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4671 struct dim_cq_moder moder;
4673 moder.cq_period_mode = cq_period_mode;
4674 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4675 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4676 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4677 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4682 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4684 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4685 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4686 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4689 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4691 if (params->tx_dim_enabled) {
4692 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4694 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4696 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4699 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4700 params->tx_cq_moderation.cq_period_mode ==
4701 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4704 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4706 if (params->rx_dim_enabled) {
4707 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4709 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4711 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4714 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4715 params->rx_cq_moderation.cq_period_mode ==
4716 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4719 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4723 /* The supported periods are organized in ascending order */
4724 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4725 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4728 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4731 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4732 struct mlx5e_params *params)
4734 /* Prefer Striding RQ, unless any of the following holds:
4735 * - Striding RQ configuration is not possible/supported.
4736 * - Slow PCI heuristic.
4737 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4739 * No XSK params: checking the availability of striding RQ in general.
4741 if (!slow_pci_heuristic(mdev) &&
4742 mlx5e_striding_rq_possible(mdev, params) &&
4743 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4744 !mlx5e_rx_is_linear_skb(params, NULL)))
4745 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4746 mlx5e_set_rq_type(mdev, params);
4747 mlx5e_init_rq_type_params(mdev, params);
4750 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4753 enum mlx5e_traffic_types tt;
4755 rss_params->hfunc = ETH_RSS_HASH_TOP;
4756 netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4757 sizeof(rss_params->toeplitz_hash_key));
4758 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4759 MLX5E_INDIR_RQT_SIZE, num_channels);
4760 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4761 rss_params->rx_hash_fields[tt] =
4762 tirc_default_config[tt].rx_hash_fields;
4765 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4766 struct mlx5e_xsk *xsk,
4767 struct mlx5e_rss_params *rss_params,
4768 struct mlx5e_params *params,
4769 u16 max_channels, u16 mtu)
4771 u8 rx_cq_period_mode;
4773 params->sw_mtu = mtu;
4774 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4775 params->num_channels = max_channels;
4779 params->log_sq_size = is_kdump_kernel() ?
4780 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4781 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4784 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4785 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4787 /* set CQE compression */
4788 params->rx_cqe_compress_def = false;
4789 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4790 MLX5_CAP_GEN(mdev, vport_group_manager))
4791 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4793 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4794 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4797 mlx5e_build_rq_params(mdev, params);
4801 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4802 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4803 /* No XSK params: checking the availability of striding RQ in general. */
4804 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4805 params->lro_en = !slow_pci_heuristic(mdev);
4807 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4809 /* CQ moderation params */
4810 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4811 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4812 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4813 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4814 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4815 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4816 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4819 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
4822 mlx5e_build_rss_params(rss_params, params->num_channels);
4823 params->tunneled_offload_en =
4824 mlx5e_tunnel_inner_ft_supported(mdev);
4830 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4832 struct mlx5e_priv *priv = netdev_priv(netdev);
4834 mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4835 if (is_zero_ether_addr(netdev->dev_addr) &&
4836 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4837 eth_hw_addr_random(netdev);
4838 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4842 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4844 struct mlx5e_priv *priv = netdev_priv(netdev);
4845 struct mlx5_core_dev *mdev = priv->mdev;
4849 SET_NETDEV_DEV(netdev, mdev->device);
4851 netdev->netdev_ops = &mlx5e_netdev_ops;
4853 #ifdef CONFIG_MLX5_CORE_EN_DCB
4854 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4855 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4858 netdev->watchdog_timeo = 15 * HZ;
4860 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4862 netdev->vlan_features |= NETIF_F_SG;
4863 netdev->vlan_features |= NETIF_F_HW_CSUM;
4864 netdev->vlan_features |= NETIF_F_GRO;
4865 netdev->vlan_features |= NETIF_F_TSO;
4866 netdev->vlan_features |= NETIF_F_TSO6;
4867 netdev->vlan_features |= NETIF_F_RXCSUM;
4868 netdev->vlan_features |= NETIF_F_RXHASH;
4870 netdev->mpls_features |= NETIF_F_SG;
4871 netdev->mpls_features |= NETIF_F_HW_CSUM;
4872 netdev->mpls_features |= NETIF_F_TSO;
4873 netdev->mpls_features |= NETIF_F_TSO6;
4875 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4876 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4878 if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4879 mlx5e_check_fragmented_striding_rq_cap(mdev))
4880 netdev->vlan_features |= NETIF_F_LRO;
4882 netdev->hw_features = netdev->vlan_features;
4883 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4884 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4885 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4886 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4888 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4889 mlx5e_any_tunnel_proto_supported(mdev)) {
4890 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4891 netdev->hw_enc_features |= NETIF_F_TSO;
4892 netdev->hw_enc_features |= NETIF_F_TSO6;
4893 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4896 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4897 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4898 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4899 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4900 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4901 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4904 if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4905 netdev->hw_features |= NETIF_F_GSO_GRE |
4906 NETIF_F_GSO_GRE_CSUM;
4907 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4908 NETIF_F_GSO_GRE_CSUM;
4909 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4910 NETIF_F_GSO_GRE_CSUM;
4913 if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4914 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4916 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4918 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4922 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4923 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4;
4924 netdev->hw_features |= NETIF_F_GSO_UDP_L4;
4925 netdev->features |= NETIF_F_GSO_UDP_L4;
4927 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4930 netdev->hw_features |= NETIF_F_RXALL;
4932 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4933 netdev->hw_features |= NETIF_F_RXFCS;
4935 netdev->features = netdev->hw_features;
4936 if (!priv->channels.params.lro_en)
4937 netdev->features &= ~NETIF_F_LRO;
4940 netdev->features &= ~NETIF_F_RXALL;
4942 if (!priv->channels.params.scatter_fcs_en)
4943 netdev->features &= ~NETIF_F_RXFCS;
4945 /* prefere CQE compression over rxhash */
4946 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4947 netdev->features &= ~NETIF_F_RXHASH;
4949 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4950 if (FT_CAP(flow_modify_en) &&
4951 FT_CAP(modify_root) &&
4952 FT_CAP(identified_miss_table_mode) &&
4953 FT_CAP(flow_table_modify)) {
4954 #ifdef CONFIG_MLX5_ESWITCH
4955 netdev->hw_features |= NETIF_F_HW_TC;
4957 #ifdef CONFIG_MLX5_EN_ARFS
4958 netdev->hw_features |= NETIF_F_NTUPLE;
4962 netdev->features |= NETIF_F_HIGHDMA;
4963 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4965 netdev->priv_flags |= IFF_UNICAST_FLT;
4967 mlx5e_set_netdev_dev_addr(netdev);
4968 mlx5e_ipsec_build_netdev(priv);
4969 mlx5e_tls_build_netdev(priv);
4972 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4974 struct mlx5_core_dev *mdev = priv->mdev;
4977 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4979 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4980 priv->q_counter = 0;
4983 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4985 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4986 priv->drop_rq_q_counter = 0;
4990 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4992 if (priv->q_counter)
4993 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4995 if (priv->drop_rq_q_counter)
4996 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4999 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5000 struct net_device *netdev,
5001 const struct mlx5e_profile *profile,
5004 struct mlx5e_priv *priv = netdev_priv(netdev);
5005 struct mlx5e_rss_params *rss = &priv->rss_params;
5008 err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5012 mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
5013 priv->max_nch, netdev->mtu);
5015 mlx5e_timestamp_init(priv);
5017 err = mlx5e_ipsec_init(priv);
5019 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5020 err = mlx5e_tls_init(priv);
5022 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5023 mlx5e_build_nic_netdev(netdev);
5024 mlx5e_build_tc2txq_maps(priv);
5025 mlx5e_health_create_reporters(priv);
5030 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5032 mlx5e_health_destroy_reporters(priv);
5033 mlx5e_tls_cleanup(priv);
5034 mlx5e_ipsec_cleanup(priv);
5035 mlx5e_netdev_cleanup(priv->netdev, priv);
5038 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5040 struct mlx5_core_dev *mdev = priv->mdev;
5043 mlx5e_create_q_counters(priv);
5045 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5047 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5048 goto err_destroy_q_counters;
5051 err = mlx5e_create_indirect_rqt(priv);
5053 goto err_close_drop_rq;
5055 err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5057 goto err_destroy_indirect_rqts;
5059 err = mlx5e_create_indirect_tirs(priv, true);
5061 goto err_destroy_direct_rqts;
5063 err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5065 goto err_destroy_indirect_tirs;
5067 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5069 goto err_destroy_direct_tirs;
5071 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5073 goto err_destroy_xsk_rqts;
5075 err = mlx5e_create_flow_steering(priv);
5077 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5078 goto err_destroy_xsk_tirs;
5081 err = mlx5e_tc_nic_init(priv);
5083 goto err_destroy_flow_steering;
5087 err_destroy_flow_steering:
5088 mlx5e_destroy_flow_steering(priv);
5089 err_destroy_xsk_tirs:
5090 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5091 err_destroy_xsk_rqts:
5092 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5093 err_destroy_direct_tirs:
5094 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5095 err_destroy_indirect_tirs:
5096 mlx5e_destroy_indirect_tirs(priv, true);
5097 err_destroy_direct_rqts:
5098 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5099 err_destroy_indirect_rqts:
5100 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5102 mlx5e_close_drop_rq(&priv->drop_rq);
5103 err_destroy_q_counters:
5104 mlx5e_destroy_q_counters(priv);
5108 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5110 mlx5e_tc_nic_cleanup(priv);
5111 mlx5e_destroy_flow_steering(priv);
5112 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5113 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5114 mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5115 mlx5e_destroy_indirect_tirs(priv, true);
5116 mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5117 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5118 mlx5e_close_drop_rq(&priv->drop_rq);
5119 mlx5e_destroy_q_counters(priv);
5122 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5126 err = mlx5e_create_tises(priv);
5128 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5132 #ifdef CONFIG_MLX5_CORE_EN_DCB
5133 mlx5e_dcbnl_initialize(priv);
5138 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5140 struct net_device *netdev = priv->netdev;
5141 struct mlx5_core_dev *mdev = priv->mdev;
5143 mlx5e_init_l2_addr(priv);
5145 /* Marking the link as currently not needed by the Driver */
5146 if (!netif_running(netdev))
5147 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5149 mlx5e_set_netdev_mtu_boundaries(priv);
5150 mlx5e_set_dev_port_mtu(priv);
5152 mlx5_lag_add(mdev, netdev);
5154 mlx5e_enable_async_events(priv);
5155 if (mlx5e_monitor_counter_supported(priv))
5156 mlx5e_monitor_counter_init(priv);
5158 mlx5e_hv_vhca_stats_create(priv);
5159 if (netdev->reg_state != NETREG_REGISTERED)
5161 #ifdef CONFIG_MLX5_CORE_EN_DCB
5162 mlx5e_dcbnl_init_app(priv);
5165 queue_work(priv->wq, &priv->set_rx_mode_work);
5168 if (netif_running(netdev))
5170 netif_device_attach(netdev);
5174 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5176 struct mlx5_core_dev *mdev = priv->mdev;
5178 #ifdef CONFIG_MLX5_CORE_EN_DCB
5179 if (priv->netdev->reg_state == NETREG_REGISTERED)
5180 mlx5e_dcbnl_delete_app(priv);
5184 if (netif_running(priv->netdev))
5185 mlx5e_close(priv->netdev);
5186 netif_device_detach(priv->netdev);
5189 queue_work(priv->wq, &priv->set_rx_mode_work);
5191 mlx5e_hv_vhca_stats_destroy(priv);
5192 if (mlx5e_monitor_counter_supported(priv))
5193 mlx5e_monitor_counter_cleanup(priv);
5195 mlx5e_disable_async_events(priv);
5196 mlx5_lag_remove(mdev);
5199 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5201 return mlx5e_refresh_tirs(priv, false);
5204 static const struct mlx5e_profile mlx5e_nic_profile = {
5205 .init = mlx5e_nic_init,
5206 .cleanup = mlx5e_nic_cleanup,
5207 .init_rx = mlx5e_init_nic_rx,
5208 .cleanup_rx = mlx5e_cleanup_nic_rx,
5209 .init_tx = mlx5e_init_nic_tx,
5210 .cleanup_tx = mlx5e_cleanup_nic_tx,
5211 .enable = mlx5e_nic_enable,
5212 .disable = mlx5e_nic_disable,
5213 .update_rx = mlx5e_update_nic_rx,
5214 .update_stats = mlx5e_update_ndo_stats,
5215 .update_carrier = mlx5e_update_carrier,
5216 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
5217 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5218 .max_tc = MLX5E_MAX_NUM_TC,
5219 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK),
5222 /* mlx5e generic netdev management API (move to en_common.c) */
5224 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5225 int mlx5e_netdev_init(struct net_device *netdev,
5226 struct mlx5e_priv *priv,
5227 struct mlx5_core_dev *mdev,
5228 const struct mlx5e_profile *profile,
5233 priv->netdev = netdev;
5234 priv->profile = profile;
5235 priv->ppriv = ppriv;
5236 priv->msglevel = MLX5E_MSG_LEVEL;
5237 priv->max_nch = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5238 priv->max_opened_tc = 1;
5240 mutex_init(&priv->state_lock);
5241 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5242 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5243 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5244 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5246 priv->wq = create_singlethread_workqueue("mlx5e");
5251 netif_carrier_off(netdev);
5253 #ifdef CONFIG_MLX5_EN_ARFS
5254 netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(mdev);
5260 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5262 destroy_workqueue(priv->wq);
5265 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5266 const struct mlx5e_profile *profile,
5270 struct net_device *netdev;
5273 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5274 nch * profile->max_tc,
5275 nch * profile->rq_groups);
5277 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5281 err = profile->init(mdev, netdev, profile, ppriv);
5283 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5284 goto err_free_netdev;
5290 free_netdev(netdev);
5295 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5297 const struct mlx5e_profile *profile;
5301 profile = priv->profile;
5302 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5304 /* max number of channels may have changed */
5305 max_nch = mlx5e_get_max_num_channels(priv->mdev);
5306 if (priv->channels.params.num_channels > max_nch) {
5307 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5308 priv->channels.params.num_channels = max_nch;
5309 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5310 MLX5E_INDIR_RQT_SIZE, max_nch);
5313 err = profile->init_tx(priv);
5317 err = profile->init_rx(priv);
5319 goto err_cleanup_tx;
5321 if (profile->enable)
5322 profile->enable(priv);
5327 profile->cleanup_tx(priv);
5333 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5335 const struct mlx5e_profile *profile = priv->profile;
5337 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5339 if (profile->disable)
5340 profile->disable(priv);
5341 flush_workqueue(priv->wq);
5343 profile->cleanup_rx(priv);
5344 profile->cleanup_tx(priv);
5345 cancel_work_sync(&priv->update_stats_work);
5348 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5350 const struct mlx5e_profile *profile = priv->profile;
5351 struct net_device *netdev = priv->netdev;
5353 if (profile->cleanup)
5354 profile->cleanup(priv);
5355 free_netdev(netdev);
5358 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5359 * hardware contexts and to connect it to the current netdev.
5361 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5363 struct mlx5e_priv *priv = vpriv;
5364 struct net_device *netdev = priv->netdev;
5367 if (netif_device_present(netdev))
5370 err = mlx5e_create_mdev_resources(mdev);
5374 err = mlx5e_attach_netdev(priv);
5376 mlx5e_destroy_mdev_resources(mdev);
5383 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5385 struct mlx5e_priv *priv = vpriv;
5386 struct net_device *netdev = priv->netdev;
5388 #ifdef CONFIG_MLX5_ESWITCH
5389 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5393 if (!netif_device_present(netdev))
5396 mlx5e_detach_netdev(priv);
5397 mlx5e_destroy_mdev_resources(mdev);
5400 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5402 struct net_device *netdev;
5407 err = mlx5e_check_required_hca_cap(mdev);
5411 #ifdef CONFIG_MLX5_ESWITCH
5412 if (MLX5_ESWITCH_MANAGER(mdev) &&
5413 mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5414 mlx5e_rep_register_vport_reps(mdev);
5419 nch = mlx5e_get_max_num_channels(mdev);
5420 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5422 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5426 dev_net_set(netdev, mlx5_core_net(mdev));
5427 priv = netdev_priv(netdev);
5429 err = mlx5e_attach(mdev, priv);
5431 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5432 goto err_destroy_netdev;
5435 err = register_netdev(netdev);
5437 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5441 #ifdef CONFIG_MLX5_CORE_EN_DCB
5442 mlx5e_dcbnl_init_app(priv);
5447 mlx5e_detach(mdev, priv);
5449 mlx5e_destroy_netdev(priv);
5453 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5455 struct mlx5e_priv *priv;
5457 #ifdef CONFIG_MLX5_ESWITCH
5458 if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5459 mlx5e_rep_unregister_vport_reps(mdev);
5464 #ifdef CONFIG_MLX5_CORE_EN_DCB
5465 mlx5e_dcbnl_delete_app(priv);
5467 unregister_netdev(priv->netdev);
5468 mlx5e_detach(mdev, vpriv);
5469 mlx5e_destroy_netdev(priv);
5472 static struct mlx5_interface mlx5e_interface = {
5474 .remove = mlx5e_remove,
5475 .attach = mlx5e_attach,
5476 .detach = mlx5e_detach,
5477 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5480 void mlx5e_init(void)
5482 mlx5e_ipsec_build_inverse_table();
5483 mlx5e_build_ptys2ethtool_map();
5484 mlx5_register_interface(&mlx5e_interface);
5487 void mlx5e_cleanup(void)
5489 mlx5_unregister_interface(&mlx5e_interface);