drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66
  67
  68 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  69 {
  70         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  71                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  72                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  73         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  74         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  75
  76         if (!striding_rq_umr)
  77                 return false;
  78         if (!inline_umr) {
  79                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  80                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  81                 return false;
  82         }
  83         return true;
  84 }
  85
  86 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  87                                struct mlx5e_params *params)
  88 {
  89         params->log_rq_mtu_frames = is_kdump_kernel() ?
  90                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  91                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  92
  93         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  94                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  96                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  97                        BIT(params->log_rq_mtu_frames),
  98                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
  99                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 100 }
 101
 102 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 103                                 struct mlx5e_params *params)
 104 {
 105         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 106                 return false;
 107
 108         if (MLX5_IPSEC_DEV(mdev))
 109                 return false;
 110
 111         if (params->xdp_prog) {
 112                 /* XSK params are not considered here. If striding RQ is in use,
 113                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 114                  * be called with the known XSK params.
 115                  */
 116                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 117                         return false;
 118         }
 119
 120         return true;
 121 }
 122
 123 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 124 {
 125         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 126                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 127                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 128                 MLX5_WQ_TYPE_CYCLIC;
 129 }
 130
 131 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 132 {
 133         struct mlx5_core_dev *mdev = priv->mdev;
 134         u8 port_state;
 135
 136         port_state = mlx5_query_vport_state(mdev,
 137                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 138                                             0);
 139
 140         if (port_state == VPORT_STATE_UP) {
 141                 netdev_info(priv->netdev, "Link up\n");
 142                 netif_carrier_on(priv->netdev);
 143         } else {
 144                 netdev_info(priv->netdev, "Link down\n");
 145                 netif_carrier_off(priv->netdev);
 146         }
 147 }
 148
 149 static void mlx5e_update_carrier_work(struct work_struct *work)
 150 {
 151         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 152                                                update_carrier_work);
 153
 154         mutex_lock(&priv->state_lock);
 155         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 156                 if (priv->profile->update_carrier)
 157                         priv->profile->update_carrier(priv);
 158         mutex_unlock(&priv->state_lock);
 159 }
 160
 161 void mlx5e_update_stats(struct mlx5e_priv *priv)
 162 {
 163         int i;
 164
 165         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 166                 if (mlx5e_stats_grps[i].update_stats)
 167                         mlx5e_stats_grps[i].update_stats(priv);
 168 }
 169
 170 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 171 {
 172         int i;
 173
 174         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 175                 if (mlx5e_stats_grps[i].update_stats_mask &
 176                     MLX5E_NDO_UPDATE_STATS)
 177                         mlx5e_stats_grps[i].update_stats(priv);
 178 }
 179
 180 static void mlx5e_update_stats_work(struct work_struct *work)
 181 {
 182         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 183                                                update_stats_work);
 184
 185         mutex_lock(&priv->state_lock);
 186         priv->profile->update_stats(priv);
 187         mutex_unlock(&priv->state_lock);
 188 }
 189
 190 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 191 {
 192         if (!priv->profile->update_stats)
 193                 return;
 194
 195         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 196                 return;
 197
 198         queue_work(priv->wq, &priv->update_stats_work);
 199 }
 200
 201 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 202 {
 203         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 204         struct mlx5_eqe   *eqe = data;
 205
 206         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 207                 return NOTIFY_DONE;
 208
 209         switch (eqe->sub_type) {
 210         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 211         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 212                 queue_work(priv->wq, &priv->update_carrier_work);
 213                 break;
 214         default:
 215                 return NOTIFY_DONE;
 216         }
 217
 218         return NOTIFY_OK;
 219 }
 220
 221 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 222 {
 223         priv->events_nb.notifier_call = async_event;
 224         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 225 }
 226
 227 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 228 {
 229         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 230 }
 231
 232 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 233                                        struct mlx5e_icosq *sq,
 234                                        struct mlx5e_umr_wqe *wqe)
 235 {
 236         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 237         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 238         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 239
 240         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 241                                       ds_cnt);
 242         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 243         cseg->imm       = rq->mkey_be;
 244
 245         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 246         ucseg->xlt_octowords =
 247                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 248         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 249 }
 250
 251 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 252                                      struct mlx5e_channel *c)
 253 {
 254         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 255
 256         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 257                                                   sizeof(*rq->mpwqe.info)),
 258                                        GFP_KERNEL, cpu_to_node(c->cpu));
 259         if (!rq->mpwqe.info)
 260                 return -ENOMEM;
 261
 262         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 263
 264         return 0;
 265 }
 266
 267 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 268                                  u64 npages, u8 page_shift,
 269                                  struct mlx5_core_mkey *umr_mkey)
 270 {
 271         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 272         void *mkc;
 273         u32 *in;
 274         int err;
 275
 276         in = kvzalloc(inlen, GFP_KERNEL);
 277         if (!in)
 278                 return -ENOMEM;
 279
 280         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 281
 282         MLX5_SET(mkc, mkc, free, 1);
 283         MLX5_SET(mkc, mkc, umr_en, 1);
 284         MLX5_SET(mkc, mkc, lw, 1);
 285         MLX5_SET(mkc, mkc, lr, 1);
 286         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 287
 288         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 289         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 290         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 291         MLX5_SET(mkc, mkc, translations_octword_size,
 292                  MLX5_MTT_OCTW(npages));
 293         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 294
 295         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 296
 297         kvfree(in);
 298         return err;
 299 }
 300
 301 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 302 {
 303         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 304
 305         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 306 }
 307
 308 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 309 {
 310         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 311 }
 312
 313 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 314 {
 315         struct mlx5e_wqe_frag_info next_frag = {};
 316         struct mlx5e_wqe_frag_info *prev = NULL;
 317         int i;
 318
 319         next_frag.di = &rq->wqe.di[0];
 320
 321         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 322                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 323                 struct mlx5e_wqe_frag_info *frag =
 324                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 325                 int f;
 326
 327                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 328                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 329                                 next_frag.di++;
 330                                 next_frag.offset = 0;
 331                                 if (prev)
 332                                         prev->last_in_page = true;
 333                         }
 334                         *frag = next_frag;
 335
 336                         /* prepare next */
 337                         next_frag.offset += frag_info[f].frag_stride;
 338                         prev = frag;
 339                 }
 340         }
 341
 342         if (prev)
 343                 prev->last_in_page = true;
 344 }
 345
 346 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 347                               int wq_sz, int cpu)
 348 {
 349         int len = wq_sz << rq->wqe.info.log_num_frags;
 350
 351         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 352                                    GFP_KERNEL, cpu_to_node(cpu));
 353         if (!rq->wqe.di)
 354                 return -ENOMEM;
 355
 356         mlx5e_init_frags_partition(rq);
 357
 358         return 0;
 359 }
 360
 361 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 362 {
 363         kvfree(rq->wqe.di);
 364 }
 365
 366 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 367 {
 368         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 369
 370         mlx5e_reporter_rq_cqe_err(rq);
 371 }
 372
 373 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 374                           struct mlx5e_params *params,
 375                           struct mlx5e_xsk_param *xsk,
 376                           struct xdp_umem *umem,
 377                           struct mlx5e_rq_param *rqp,
 378                           struct mlx5e_rq *rq)
 379 {
 380         struct page_pool_params pp_params = { 0 };
 381         struct mlx5_core_dev *mdev = c->mdev;
 382         void *rqc = rqp->rqc;
 383         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 384         u32 num_xsk_frames = 0;
 385         u32 rq_xdp_ix;
 386         u32 pool_size;
 387         int wq_sz;
 388         int err;
 389         int i;
 390
 391         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 392
 393         rq->wq_type = params->rq_wq_type;
 394         rq->pdev    = c->pdev;
 395         rq->netdev  = c->netdev;
 396         rq->tstamp  = c->tstamp;
 397         rq->clock   = &mdev->clock;
 398         rq->channel = c;
 399         rq->ix      = c->ix;
 400         rq->mdev    = mdev;
 401         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 402         rq->xdpsq   = &c->rq_xdpsq;
 403         rq->umem    = umem;
 404
 405         if (rq->umem)
 406                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 407         else
 408                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 409         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 410
 411         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 412         if (IS_ERR(rq->xdp_prog)) {
 413                 err = PTR_ERR(rq->xdp_prog);
 414                 rq->xdp_prog = NULL;
 415                 goto err_rq_wq_destroy;
 416         }
 417
 418         rq_xdp_ix = rq->ix;
 419         if (xsk)
 420                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 421         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 422         if (err < 0)
 423                 goto err_rq_wq_destroy;
 424
 425         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 426         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 427         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 428         pool_size = 1 << params->log_rq_mtu_frames;
 429
 430         switch (rq->wq_type) {
 431         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 432                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 433                                         &rq->wq_ctrl);
 434                 if (err)
 435                         return err;
 436
 437                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 438
 439                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 440
 441                 if (xsk)
 442                         num_xsk_frames = wq_sz <<
 443                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 444
 445                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 446                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 447
 448                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 449                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 450
 451                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 452 #ifdef CONFIG_MLX5_EN_IPSEC
 453                 if (MLX5_IPSEC_DEV(mdev)) {
 454                         err = -EINVAL;
 455                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 456                         goto err_rq_wq_destroy;
 457                 }
 458 #endif
 459                 if (!rq->handle_rx_cqe) {
 460                         err = -EINVAL;
 461                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 462                         goto err_rq_wq_destroy;
 463                 }
 464
 465                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 466                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 467                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 468                                 mlx5e_skb_from_cqe_mpwrq_linear :
 469                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 470
 471                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 472                 rq->mpwqe.num_strides =
 473                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 474
 475                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 476                 if (err)
 477                         goto err_rq_wq_destroy;
 478                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 479
 480                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 481                 if (err)
 482                         goto err_free;
 483                 break;
 484         default: /* MLX5_WQ_TYPE_CYCLIC */
 485                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 486                                          &rq->wq_ctrl);
 487                 if (err)
 488                         return err;
 489
 490                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 491
 492                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 493
 494                 if (xsk)
 495                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 496
 497                 rq->wqe.info = rqp->frags_info;
 498                 rq->wqe.frags =
 499                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 500                                         (wq_sz << rq->wqe.info.log_num_frags)),
 501                                       GFP_KERNEL, cpu_to_node(c->cpu));
 502                 if (!rq->wqe.frags) {
 503                         err = -ENOMEM;
 504                         goto err_free;
 505                 }
 506
 507                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 508                 if (err)
 509                         goto err_free;
 510
 511                 rq->post_wqes = mlx5e_post_rx_wqes;
 512                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 513
 514 #ifdef CONFIG_MLX5_EN_IPSEC
 515                 if (c->priv->ipsec)
 516                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 517                 else
 518 #endif
 519                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 520                 if (!rq->handle_rx_cqe) {
 521                         err = -EINVAL;
 522                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 523                         goto err_free;
 524                 }
 525
 526                 rq->wqe.skb_from_cqe = xsk ?
 527                         mlx5e_xsk_skb_from_cqe_linear :
 528                         mlx5e_rx_is_linear_skb(params, NULL) ?
 529                                 mlx5e_skb_from_cqe_linear :
 530                                 mlx5e_skb_from_cqe_nonlinear;
 531                 rq->mkey_be = c->mkey_be;
 532         }
 533
 534         if (xsk) {
 535                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 536                 if (unlikely(err)) {
 537                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 538                                       num_xsk_frames);
 539                         goto err_free;
 540                 }
 541
 542                 rq->zca.free = mlx5e_xsk_zca_free;
 543                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 544                                                  MEM_TYPE_ZERO_COPY,
 545                                                  &rq->zca);
 546         } else {
 547                 /* Create a page_pool and register it with rxq */
 548                 pp_params.order     = 0;
 549                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 550                 pp_params.pool_size = pool_size;
 551                 pp_params.nid       = cpu_to_node(c->cpu);
 552                 pp_params.dev       = c->pdev;
 553                 pp_params.dma_dir   = rq->buff.map_dir;
 554
 555                 /* page_pool can be used even when there is no rq->xdp_prog,
 556                  * given page_pool does not handle DMA mapping there is no
 557                  * required state to clear. And page_pool gracefully handle
 558                  * elevated refcnt.
 559                  */
 560                 rq->page_pool = page_pool_create(&pp_params);
 561                 if (IS_ERR(rq->page_pool)) {
 562                         err = PTR_ERR(rq->page_pool);
 563                         rq->page_pool = NULL;
 564                         goto err_free;
 565                 }
 566                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 567                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 568         }
 569         if (err)
 570                 goto err_free;
 571
 572         for (i = 0; i < wq_sz; i++) {
 573                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 574                         struct mlx5e_rx_wqe_ll *wqe =
 575                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 576                         u32 byte_count =
 577                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 578                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 579
 580                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 581                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 582                         wqe->data[0].lkey = rq->mkey_be;
 583                 } else {
 584                         struct mlx5e_rx_wqe_cyc *wqe =
 585                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 586                         int f;
 587
 588                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 589                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 590                                         MLX5_HW_START_PADDING;
 591
 592                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 593                                 wqe->data[f].lkey = rq->mkey_be;
 594                         }
 595                         /* check if num_frags is not a pow of two */
 596                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 597                                 wqe->data[f].byte_count = 0;
 598                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 599                                 wqe->data[f].addr = 0;
 600                         }
 601                 }
 602         }
 603
 604         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 605
 606         switch (params->rx_cq_moderation.cq_period_mode) {
 607         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 608                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 609                 break;
 610         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 611         default:
 612                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 613         }
 614
 615         rq->page_cache.head = 0;
 616         rq->page_cache.tail = 0;
 617
 618         return 0;
 619
 620 err_free:
 621         switch (rq->wq_type) {
 622         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 623                 kvfree(rq->mpwqe.info);
 624                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 625                 break;
 626         default: /* MLX5_WQ_TYPE_CYCLIC */
 627                 kvfree(rq->wqe.frags);
 628                 mlx5e_free_di_list(rq);
 629         }
 630
 631 err_rq_wq_destroy:
 632         if (rq->xdp_prog)
 633                 bpf_prog_put(rq->xdp_prog);
 634         xdp_rxq_info_unreg(&rq->xdp_rxq);
 635         page_pool_destroy(rq->page_pool);
 636         mlx5_wq_destroy(&rq->wq_ctrl);
 637
 638         return err;
 639 }
 640
 641 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 642 {
 643         int i;
 644
 645         if (rq->xdp_prog)
 646                 bpf_prog_put(rq->xdp_prog);
 647
 648         switch (rq->wq_type) {
 649         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 650                 kvfree(rq->mpwqe.info);
 651                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 652                 break;
 653         default: /* MLX5_WQ_TYPE_CYCLIC */
 654                 kvfree(rq->wqe.frags);
 655                 mlx5e_free_di_list(rq);
 656         }
 657
 658         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 659              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 660                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 661
 662                 /* With AF_XDP, page_cache is not used, so this loop is not
 663                  * entered, and it's safe to call mlx5e_page_release_dynamic
 664                  * directly.
 665                  */
 666                 mlx5e_page_release_dynamic(rq, dma_info, false);
 667         }
 668
 669         xdp_rxq_info_unreg(&rq->xdp_rxq);
 670         page_pool_destroy(rq->page_pool);
 671         mlx5_wq_destroy(&rq->wq_ctrl);
 672 }
 673
 674 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 675                            struct mlx5e_rq_param *param)
 676 {
 677         struct mlx5_core_dev *mdev = rq->mdev;
 678
 679         void *in;
 680         void *rqc;
 681         void *wq;
 682         int inlen;
 683         int err;
 684
 685         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 686                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 687         in = kvzalloc(inlen, GFP_KERNEL);
 688         if (!in)
 689                 return -ENOMEM;
 690
 691         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 692         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 693
 694         memcpy(rqc, param->rqc, sizeof(param->rqc));
 695
 696         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 697         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 698         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 699                                                 MLX5_ADAPTER_PAGE_SHIFT);
 700         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 701
 702         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 703                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 704
 705         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 706
 707         kvfree(in);
 708
 709         return err;
 710 }
 711
 712 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 713 {
 714         struct mlx5_core_dev *mdev = rq->mdev;
 715
 716         void *in;
 717         void *rqc;
 718         int inlen;
 719         int err;
 720
 721         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 722         in = kvzalloc(inlen, GFP_KERNEL);
 723         if (!in)
 724                 return -ENOMEM;
 725
 726         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 727
 728         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 729         MLX5_SET(rqc, rqc, state, next_state);
 730
 731         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 732
 733         kvfree(in);
 734
 735         return err;
 736 }
 737
 738 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 739 {
 740         struct mlx5e_channel *c = rq->channel;
 741         struct mlx5e_priv *priv = c->priv;
 742         struct mlx5_core_dev *mdev = priv->mdev;
 743
 744         void *in;
 745         void *rqc;
 746         int inlen;
 747         int err;
 748
 749         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 750         in = kvzalloc(inlen, GFP_KERNEL);
 751         if (!in)
 752                 return -ENOMEM;
 753
 754         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 755
 756         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 757         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 758                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 759         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 760         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 761
 762         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 763
 764         kvfree(in);
 765
 766         return err;
 767 }
 768
 769 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 770 {
 771         struct mlx5e_channel *c = rq->channel;
 772         struct mlx5_core_dev *mdev = c->mdev;
 773         void *in;
 774         void *rqc;
 775         int inlen;
 776         int err;
 777
 778         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 779         in = kvzalloc(inlen, GFP_KERNEL);
 780         if (!in)
 781                 return -ENOMEM;
 782
 783         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 784
 785         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 786         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 787                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 788         MLX5_SET(rqc, rqc, vsd, vsd);
 789         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 790
 791         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 792
 793         kvfree(in);
 794
 795         return err;
 796 }
 797
 798 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 799 {
 800         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 801 }
 802
 803 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 804 {
 805         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 806         struct mlx5e_channel *c = rq->channel;
 807
 808         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 809
 810         do {
 811                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 812                         return 0;
 813
 814                 msleep(20);
 815         } while (time_before(jiffies, exp_time));
 816
 817         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 818                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 819
 820         mlx5e_reporter_rx_timeout(rq);
 821         return -ETIMEDOUT;
 822 }
 823
 824 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 825 {
 826         __be16 wqe_ix_be;
 827         u16 wqe_ix;
 828
 829         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 830                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 831                 u16 head = wq->head;
 832                 int i;
 833
 834                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 835                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 836                         rq->dealloc_wqe(rq, head);
 837                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 838                 }
 839
 840                 while (!mlx5_wq_ll_is_empty(wq)) {
 841                         struct mlx5e_rx_wqe_ll *wqe;
 842
 843                         wqe_ix_be = *wq->tail_next;
 844                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 845                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 846                         rq->dealloc_wqe(rq, wqe_ix);
 847                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 848                                        &wqe->next.next_wqe_index);
 849                 }
 850         } else {
 851                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 852
 853                 while (!mlx5_wq_cyc_is_empty(wq)) {
 854                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 855                         rq->dealloc_wqe(rq, wqe_ix);
 856                         mlx5_wq_cyc_pop(wq);
 857                 }
 858         }
 859
 860 }
 861
 862 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 863                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 864                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 865 {
 866         int err;
 867
 868         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 869         if (err)
 870                 return err;
 871
 872         err = mlx5e_create_rq(rq, param);
 873         if (err)
 874                 goto err_free_rq;
 875
 876         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 877         if (err)
 878                 goto err_destroy_rq;
 879
 880         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 881                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 882
 883         if (params->rx_dim_enabled)
 884                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 885
 886         /* We disable csum_complete when XDP is enabled since
 887          * XDP programs might manipulate packets which will render
 888          * skb->checksum incorrect.
 889          */
 890         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 891                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 892
 893         return 0;
 894
 895 err_destroy_rq:
 896         mlx5e_destroy_rq(rq);
 897 err_free_rq:
 898         mlx5e_free_rq(rq);
 899
 900         return err;
 901 }
 902
 903 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 904 {
 905         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 906         mlx5e_trigger_irq(&rq->channel->icosq);
 907 }
 908
 909 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 910 {
 911         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 912         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 913 }
 914
 915 void mlx5e_close_rq(struct mlx5e_rq *rq)
 916 {
 917         cancel_work_sync(&rq->dim.work);
 918         cancel_work_sync(&rq->channel->icosq.recover_work);
 919         cancel_work_sync(&rq->recover_work);
 920         mlx5e_destroy_rq(rq);
 921         mlx5e_free_rx_descs(rq);
 922         mlx5e_free_rq(rq);
 923 }
 924
 925 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 926 {
 927         kvfree(sq->db.xdpi_fifo.xi);
 928         kvfree(sq->db.wqe_info);
 929 }
 930
 931 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 932 {
 933         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 934         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 935         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 936
 937         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 938                                       GFP_KERNEL, numa);
 939         if (!xdpi_fifo->xi)
 940                 return -ENOMEM;
 941
 942         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 943         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 944         xdpi_fifo->mask = dsegs_per_wq - 1;
 945
 946         return 0;
 947 }
 948
 949 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 950 {
 951         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 952         int err;
 953
 954         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 955                                         GFP_KERNEL, numa);
 956         if (!sq->db.wqe_info)
 957                 return -ENOMEM;
 958
 959         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 960         if (err) {
 961                 mlx5e_free_xdpsq_db(sq);
 962                 return err;
 963         }
 964
 965         return 0;
 966 }
 967
 968 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 969                              struct mlx5e_params *params,
 970                              struct xdp_umem *umem,
 971                              struct mlx5e_sq_param *param,
 972                              struct mlx5e_xdpsq *sq,
 973                              bool is_redirect)
 974 {
 975         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 976         struct mlx5_core_dev *mdev = c->mdev;
 977         struct mlx5_wq_cyc *wq = &sq->wq;
 978         int err;
 979
 980         sq->pdev      = c->pdev;
 981         sq->mkey_be   = c->mkey_be;
 982         sq->channel   = c;
 983         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 984         sq->min_inline_mode = params->tx_min_inline_mode;
 985         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 986         sq->umem      = umem;
 987
 988         sq->stats = sq->umem ?
 989                 &c->priv->channel_stats[c->ix].xsksq :
 990                 is_redirect ?
 991                         &c->priv->channel_stats[c->ix].xdpsq :
 992                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 993
 994         param->wq.db_numa_node = cpu_to_node(c->cpu);
 995         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 996         if (err)
 997                 return err;
 998         wq->db = &wq->db[MLX5_SND_DBR];
 999
1000         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1001         if (err)
1002                 goto err_sq_wq_destroy;
1003
1004         return 0;
1005
1006 err_sq_wq_destroy:
1007         mlx5_wq_destroy(&sq->wq_ctrl);
1008
1009         return err;
1010 }
1011
1012 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1013 {
1014         mlx5e_free_xdpsq_db(sq);
1015         mlx5_wq_destroy(&sq->wq_ctrl);
1016 }
1017
1018 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1019 {
1020         kvfree(sq->db.ico_wqe);
1021 }
1022
1023 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1024 {
1025         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1026
1027         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1028                                                   sizeof(*sq->db.ico_wqe)),
1029                                        GFP_KERNEL, numa);
1030         if (!sq->db.ico_wqe)
1031                 return -ENOMEM;
1032
1033         return 0;
1034 }
1035
1036 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1037 {
1038         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1039                                               recover_work);
1040
1041         mlx5e_reporter_icosq_cqe_err(sq);
1042 }
1043
1044 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1045                              struct mlx5e_sq_param *param,
1046                              struct mlx5e_icosq *sq)
1047 {
1048         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1049         struct mlx5_core_dev *mdev = c->mdev;
1050         struct mlx5_wq_cyc *wq = &sq->wq;
1051         int err;
1052
1053         sq->channel   = c;
1054         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1055
1056         param->wq.db_numa_node = cpu_to_node(c->cpu);
1057         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1058         if (err)
1059                 return err;
1060         wq->db = &wq->db[MLX5_SND_DBR];
1061
1062         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1063         if (err)
1064                 goto err_sq_wq_destroy;
1065
1066         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1067
1068         return 0;
1069
1070 err_sq_wq_destroy:
1071         mlx5_wq_destroy(&sq->wq_ctrl);
1072
1073         return err;
1074 }
1075
1076 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1077 {
1078         mlx5e_free_icosq_db(sq);
1079         mlx5_wq_destroy(&sq->wq_ctrl);
1080 }
1081
1082 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1083 {
1084         kvfree(sq->db.wqe_info);
1085         kvfree(sq->db.dma_fifo);
1086 }
1087
1088 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1089 {
1090         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1091         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1092
1093         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1094                                                    sizeof(*sq->db.dma_fifo)),
1095                                         GFP_KERNEL, numa);
1096         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1097                                                    sizeof(*sq->db.wqe_info)),
1098                                         GFP_KERNEL, numa);
1099         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1100                 mlx5e_free_txqsq_db(sq);
1101                 return -ENOMEM;
1102         }
1103
1104         sq->dma_fifo_mask = df_sz - 1;
1105
1106         return 0;
1107 }
1108
1109 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1110 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1111                              int txq_ix,
1112                              struct mlx5e_params *params,
1113                              struct mlx5e_sq_param *param,
1114                              struct mlx5e_txqsq *sq,
1115                              int tc)
1116 {
1117         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1118         struct mlx5_core_dev *mdev = c->mdev;
1119         struct mlx5_wq_cyc *wq = &sq->wq;
1120         int err;
1121
1122         sq->pdev      = c->pdev;
1123         sq->tstamp    = c->tstamp;
1124         sq->clock     = &mdev->clock;
1125         sq->mkey_be   = c->mkey_be;
1126         sq->channel   = c;
1127         sq->ch_ix     = c->ix;
1128         sq->txq_ix    = txq_ix;
1129         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1130         sq->min_inline_mode = params->tx_min_inline_mode;
1131         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1132         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1133         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1134         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1135         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1136                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1137         if (MLX5_IPSEC_DEV(c->priv->mdev))
1138                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1139 #ifdef CONFIG_MLX5_EN_TLS
1140         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1141                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1142                 sq->stop_room += MLX5E_SQ_TLS_ROOM +
1143                         mlx5e_ktls_dumps_num_wqebbs(sq, MAX_SKB_FRAGS,
1144                                                     TLS_MAX_PAYLOAD_SIZE);
1145         }
1146 #endif
1147
1148         param->wq.db_numa_node = cpu_to_node(c->cpu);
1149         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1150         if (err)
1151                 return err;
1152         wq->db    = &wq->db[MLX5_SND_DBR];
1153
1154         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1155         if (err)
1156                 goto err_sq_wq_destroy;
1157
1158         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1159         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1160
1161         return 0;
1162
1163 err_sq_wq_destroy:
1164         mlx5_wq_destroy(&sq->wq_ctrl);
1165
1166         return err;
1167 }
1168
1169 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1170 {
1171         mlx5e_free_txqsq_db(sq);
1172         mlx5_wq_destroy(&sq->wq_ctrl);
1173 }
1174
1175 struct mlx5e_create_sq_param {
1176         struct mlx5_wq_ctrl        *wq_ctrl;
1177         u32                         cqn;
1178         u32                         tisn;
1179         u8                          tis_lst_sz;
1180         u8                          min_inline_mode;
1181 };
1182
1183 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1184                            struct mlx5e_sq_param *param,
1185                            struct mlx5e_create_sq_param *csp,
1186                            u32 *sqn)
1187 {
1188         void *in;
1189         void *sqc;
1190         void *wq;
1191         int inlen;
1192         int err;
1193
1194         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1195                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1196         in = kvzalloc(inlen, GFP_KERNEL);
1197         if (!in)
1198                 return -ENOMEM;
1199
1200         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1201         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1202
1203         memcpy(sqc, param->sqc, sizeof(param->sqc));
1204         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1205         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1206         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1207
1208         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1209                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1210
1211         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1212         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1213
1214         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1215         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1216         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1217                                           MLX5_ADAPTER_PAGE_SHIFT);
1218         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1219
1220         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1221                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1222
1223         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1224
1225         kvfree(in);
1226
1227         return err;
1228 }
1229
1230 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1231                     struct mlx5e_modify_sq_param *p)
1232 {
1233         void *in;
1234         void *sqc;
1235         int inlen;
1236         int err;
1237
1238         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1239         in = kvzalloc(inlen, GFP_KERNEL);
1240         if (!in)
1241                 return -ENOMEM;
1242
1243         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1244
1245         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1246         MLX5_SET(sqc, sqc, state, p->next_state);
1247         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1248                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1249                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1250         }
1251
1252         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1253
1254         kvfree(in);
1255
1256         return err;
1257 }
1258
1259 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1260 {
1261         mlx5_core_destroy_sq(mdev, sqn);
1262 }
1263
1264 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1265                                struct mlx5e_sq_param *param,
1266                                struct mlx5e_create_sq_param *csp,
1267                                u32 *sqn)
1268 {
1269         struct mlx5e_modify_sq_param msp = {0};
1270         int err;
1271
1272         err = mlx5e_create_sq(mdev, param, csp, sqn);
1273         if (err)
1274                 return err;
1275
1276         msp.curr_state = MLX5_SQC_STATE_RST;
1277         msp.next_state = MLX5_SQC_STATE_RDY;
1278         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1279         if (err)
1280                 mlx5e_destroy_sq(mdev, *sqn);
1281
1282         return err;
1283 }
1284
1285 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1286                                 struct mlx5e_txqsq *sq, u32 rate);
1287
1288 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1289                             u32 tisn,
1290                             int txq_ix,
1291                             struct mlx5e_params *params,
1292                             struct mlx5e_sq_param *param,
1293                             struct mlx5e_txqsq *sq,
1294                             int tc)
1295 {
1296         struct mlx5e_create_sq_param csp = {};
1297         u32 tx_rate;
1298         int err;
1299
1300         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1301         if (err)
1302                 return err;
1303
1304         csp.tisn            = tisn;
1305         csp.tis_lst_sz      = 1;
1306         csp.cqn             = sq->cq.mcq.cqn;
1307         csp.wq_ctrl         = &sq->wq_ctrl;
1308         csp.min_inline_mode = sq->min_inline_mode;
1309         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1310         if (err)
1311                 goto err_free_txqsq;
1312
1313         tx_rate = c->priv->tx_rates[sq->txq_ix];
1314         if (tx_rate)
1315                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1316
1317         if (params->tx_dim_enabled)
1318                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1319
1320         return 0;
1321
1322 err_free_txqsq:
1323         mlx5e_free_txqsq(sq);
1324
1325         return err;
1326 }
1327
1328 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1329 {
1330         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1331         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1332         netdev_tx_reset_queue(sq->txq);
1333         netif_tx_start_queue(sq->txq);
1334 }
1335
1336 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1337 {
1338         __netif_tx_lock_bh(txq);
1339         netif_tx_stop_queue(txq);
1340         __netif_tx_unlock_bh(txq);
1341 }
1342
1343 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1344 {
1345         struct mlx5e_channel *c = sq->channel;
1346         struct mlx5_wq_cyc *wq = &sq->wq;
1347
1348         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1349         /* prevent netif_tx_wake_queue */
1350         napi_synchronize(&c->napi);
1351
1352         mlx5e_tx_disable_queue(sq->txq);
1353
1354         /* last doorbell out, godspeed .. */
1355         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1356                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1357                 struct mlx5e_tx_wqe_info *wi;
1358                 struct mlx5e_tx_wqe *nop;
1359
1360                 wi = &sq->db.wqe_info[pi];
1361
1362                 memset(wi, 0, sizeof(*wi));
1363                 wi->num_wqebbs = 1;
1364                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1365                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1366         }
1367 }
1368
1369 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1370 {
1371         struct mlx5e_channel *c = sq->channel;
1372         struct mlx5_core_dev *mdev = c->mdev;
1373         struct mlx5_rate_limit rl = {0};
1374
1375         cancel_work_sync(&sq->dim.work);
1376         cancel_work_sync(&sq->recover_work);
1377         mlx5e_destroy_sq(mdev, sq->sqn);
1378         if (sq->rate_limit) {
1379                 rl.rate = sq->rate_limit;
1380                 mlx5_rl_remove_rate(mdev, &rl);
1381         }
1382         mlx5e_free_txqsq_descs(sq);
1383         mlx5e_free_txqsq(sq);
1384 }
1385
1386 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1387 {
1388         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1389                                               recover_work);
1390
1391         mlx5e_reporter_tx_err_cqe(sq);
1392 }
1393
1394 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1395                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1396 {
1397         struct mlx5e_create_sq_param csp = {};
1398         int err;
1399
1400         err = mlx5e_alloc_icosq(c, param, sq);
1401         if (err)
1402                 return err;
1403
1404         csp.cqn             = sq->cq.mcq.cqn;
1405         csp.wq_ctrl         = &sq->wq_ctrl;
1406         csp.min_inline_mode = params->tx_min_inline_mode;
1407         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1408         if (err)
1409                 goto err_free_icosq;
1410
1411         return 0;
1412
1413 err_free_icosq:
1414         mlx5e_free_icosq(sq);
1415
1416         return err;
1417 }
1418
1419 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1420 {
1421         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1422 }
1423
1424 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1425 {
1426         struct mlx5e_channel *c = icosq->channel;
1427
1428         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1429         napi_synchronize(&c->napi);
1430 }
1431
1432 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1433 {
1434         struct mlx5e_channel *c = sq->channel;
1435
1436         mlx5e_destroy_sq(c->mdev, sq->sqn);
1437         mlx5e_free_icosq(sq);
1438 }
1439
1440 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1441                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1442                      struct mlx5e_xdpsq *sq, bool is_redirect)
1443 {
1444         struct mlx5e_create_sq_param csp = {};
1445         int err;
1446
1447         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1448         if (err)
1449                 return err;
1450
1451         csp.tis_lst_sz      = 1;
1452         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1453         csp.cqn             = sq->cq.mcq.cqn;
1454         csp.wq_ctrl         = &sq->wq_ctrl;
1455         csp.min_inline_mode = sq->min_inline_mode;
1456         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1457         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1458         if (err)
1459                 goto err_free_xdpsq;
1460
1461         mlx5e_set_xmit_fp(sq, param->is_mpw);
1462
1463         if (!param->is_mpw) {
1464                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1465                 unsigned int inline_hdr_sz = 0;
1466                 int i;
1467
1468                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1469                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1470                         ds_cnt++;
1471                 }
1472
1473                 /* Pre initialize fixed WQE fields */
1474                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1475                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1476                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1477                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1478                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1479                         struct mlx5_wqe_data_seg *dseg;
1480
1481                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1482                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1483
1484                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1485                         dseg->lkey = sq->mkey_be;
1486
1487                         wi->num_wqebbs = 1;
1488                         wi->num_pkts   = 1;
1489                 }
1490         }
1491
1492         return 0;
1493
1494 err_free_xdpsq:
1495         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1496         mlx5e_free_xdpsq(sq);
1497
1498         return err;
1499 }
1500
1501 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1502 {
1503         struct mlx5e_channel *c = sq->channel;
1504
1505         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1506         napi_synchronize(&c->napi);
1507
1508         mlx5e_destroy_sq(c->mdev, sq->sqn);
1509         mlx5e_free_xdpsq_descs(sq);
1510         mlx5e_free_xdpsq(sq);
1511 }
1512
1513 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1514                                  struct mlx5e_cq_param *param,
1515                                  struct mlx5e_cq *cq)
1516 {
1517         struct mlx5_core_cq *mcq = &cq->mcq;
1518         int eqn_not_used;
1519         unsigned int irqn;
1520         int err;
1521         u32 i;
1522
1523         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1524         if (err)
1525                 return err;
1526
1527         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1528                                &cq->wq_ctrl);
1529         if (err)
1530                 return err;
1531
1532         mcq->cqe_sz     = 64;
1533         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1534         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1535         *mcq->set_ci_db = 0;
1536         *mcq->arm_db    = 0;
1537         mcq->vector     = param->eq_ix;
1538         mcq->comp       = mlx5e_completion_event;
1539         mcq->event      = mlx5e_cq_error_event;
1540         mcq->irqn       = irqn;
1541
1542         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1543                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1544
1545                 cqe->op_own = 0xf1;
1546         }
1547
1548         cq->mdev = mdev;
1549
1550         return 0;
1551 }
1552
1553 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1554                           struct mlx5e_cq_param *param,
1555                           struct mlx5e_cq *cq)
1556 {
1557         struct mlx5_core_dev *mdev = c->priv->mdev;
1558         int err;
1559
1560         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1561         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1562         param->eq_ix   = c->ix;
1563
1564         err = mlx5e_alloc_cq_common(mdev, param, cq);
1565
1566         cq->napi    = &c->napi;
1567         cq->channel = c;
1568
1569         return err;
1570 }
1571
1572 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1573 {
1574         mlx5_wq_destroy(&cq->wq_ctrl);
1575 }
1576
1577 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1578 {
1579         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1580         struct mlx5_core_dev *mdev = cq->mdev;
1581         struct mlx5_core_cq *mcq = &cq->mcq;
1582
1583         void *in;
1584         void *cqc;
1585         int inlen;
1586         unsigned int irqn_not_used;
1587         int eqn;
1588         int err;
1589
1590         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1591         if (err)
1592                 return err;
1593
1594         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1595                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1596         in = kvzalloc(inlen, GFP_KERNEL);
1597         if (!in)
1598                 return -ENOMEM;
1599
1600         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1601
1602         memcpy(cqc, param->cqc, sizeof(param->cqc));
1603
1604         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1605                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1606
1607         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1608         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1609         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1610         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1611                                             MLX5_ADAPTER_PAGE_SHIFT);
1612         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1613
1614         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1615
1616         kvfree(in);
1617
1618         if (err)
1619                 return err;
1620
1621         mlx5e_cq_arm(cq);
1622
1623         return 0;
1624 }
1625
1626 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1627 {
1628         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1629 }
1630
1631 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1632                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1633 {
1634         struct mlx5_core_dev *mdev = c->mdev;
1635         int err;
1636
1637         err = mlx5e_alloc_cq(c, param, cq);
1638         if (err)
1639                 return err;
1640
1641         err = mlx5e_create_cq(cq, param);
1642         if (err)
1643                 goto err_free_cq;
1644
1645         if (MLX5_CAP_GEN(mdev, cq_moderation))
1646                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1647         return 0;
1648
1649 err_free_cq:
1650         mlx5e_free_cq(cq);
1651
1652         return err;
1653 }
1654
1655 void mlx5e_close_cq(struct mlx5e_cq *cq)
1656 {
1657         mlx5e_destroy_cq(cq);
1658         mlx5e_free_cq(cq);
1659 }
1660
1661 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1662                              struct mlx5e_params *params,
1663                              struct mlx5e_channel_param *cparam)
1664 {
1665         int err;
1666         int tc;
1667
1668         for (tc = 0; tc < c->num_tc; tc++) {
1669                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1670                                     &cparam->tx_cq, &c->sq[tc].cq);
1671                 if (err)
1672                         goto err_close_tx_cqs;
1673         }
1674
1675         return 0;
1676
1677 err_close_tx_cqs:
1678         for (tc--; tc >= 0; tc--)
1679                 mlx5e_close_cq(&c->sq[tc].cq);
1680
1681         return err;
1682 }
1683
1684 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1685 {
1686         int tc;
1687
1688         for (tc = 0; tc < c->num_tc; tc++)
1689                 mlx5e_close_cq(&c->sq[tc].cq);
1690 }
1691
1692 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1693                           struct mlx5e_params *params,
1694                           struct mlx5e_channel_param *cparam)
1695 {
1696         struct mlx5e_priv *priv = c->priv;
1697         int err, tc;
1698
1699         for (tc = 0; tc < params->num_tc; tc++) {
1700                 int txq_ix = c->ix + tc * priv->max_nch;
1701
1702                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1703                                        params, &cparam->sq, &c->sq[tc], tc);
1704                 if (err)
1705                         goto err_close_sqs;
1706         }
1707
1708         return 0;
1709
1710 err_close_sqs:
1711         for (tc--; tc >= 0; tc--)
1712                 mlx5e_close_txqsq(&c->sq[tc]);
1713
1714         return err;
1715 }
1716
1717 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1718 {
1719         int tc;
1720
1721         for (tc = 0; tc < c->num_tc; tc++)
1722                 mlx5e_close_txqsq(&c->sq[tc]);
1723 }
1724
1725 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1726                                 struct mlx5e_txqsq *sq, u32 rate)
1727 {
1728         struct mlx5e_priv *priv = netdev_priv(dev);
1729         struct mlx5_core_dev *mdev = priv->mdev;
1730         struct mlx5e_modify_sq_param msp = {0};
1731         struct mlx5_rate_limit rl = {0};
1732         u16 rl_index = 0;
1733         int err;
1734
1735         if (rate == sq->rate_limit)
1736                 /* nothing to do */
1737                 return 0;
1738
1739         if (sq->rate_limit) {
1740                 rl.rate = sq->rate_limit;
1741                 /* remove current rl index to free space to next ones */
1742                 mlx5_rl_remove_rate(mdev, &rl);
1743         }
1744
1745         sq->rate_limit = 0;
1746
1747         if (rate) {
1748                 rl.rate = rate;
1749                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1750                 if (err) {
1751                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1752                                    rate, err);
1753                         return err;
1754                 }
1755         }
1756
1757         msp.curr_state = MLX5_SQC_STATE_RDY;
1758         msp.next_state = MLX5_SQC_STATE_RDY;
1759         msp.rl_index   = rl_index;
1760         msp.rl_update  = true;
1761         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1762         if (err) {
1763                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1764                            rate, err);
1765                 /* remove the rate from the table */
1766                 if (rate)
1767                         mlx5_rl_remove_rate(mdev, &rl);
1768                 return err;
1769         }
1770
1771         sq->rate_limit = rate;
1772         return 0;
1773 }
1774
1775 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1776 {
1777         struct mlx5e_priv *priv = netdev_priv(dev);
1778         struct mlx5_core_dev *mdev = priv->mdev;
1779         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1780         int err = 0;
1781
1782         if (!mlx5_rl_is_supported(mdev)) {
1783                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1784                 return -EINVAL;
1785         }
1786
1787         /* rate is given in Mb/sec, HW config is in Kb/sec */
1788         rate = rate << 10;
1789
1790         /* Check whether rate in valid range, 0 is always valid */
1791         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1792                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1793                 return -ERANGE;
1794         }
1795
1796         mutex_lock(&priv->state_lock);
1797         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1798                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1799         if (!err)
1800                 priv->tx_rates[index] = rate;
1801         mutex_unlock(&priv->state_lock);
1802
1803         return err;
1804 }
1805
1806 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1807                                    struct mlx5e_params *params)
1808 {
1809         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1810         int irq;
1811
1812         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1813                 return -ENOMEM;
1814
1815         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1816                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1817
1818                 cpumask_set_cpu(cpu, c->xps_cpumask);
1819         }
1820
1821         return 0;
1822 }
1823
1824 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1825 {
1826         free_cpumask_var(c->xps_cpumask);
1827 }
1828
1829 static int mlx5e_open_queues(struct mlx5e_channel *c,
1830                              struct mlx5e_params *params,
1831                              struct mlx5e_channel_param *cparam)
1832 {
1833         struct dim_cq_moder icocq_moder = {0, 0};
1834         int err;
1835
1836         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1837         if (err)
1838                 return err;
1839
1840         err = mlx5e_open_tx_cqs(c, params, cparam);
1841         if (err)
1842                 goto err_close_icosq_cq;
1843
1844         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1845         if (err)
1846                 goto err_close_tx_cqs;
1847
1848         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1849         if (err)
1850                 goto err_close_xdp_tx_cqs;
1851
1852         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1853         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1854                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1855         if (err)
1856                 goto err_close_rx_cq;
1857
1858         napi_enable(&c->napi);
1859
1860         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1861         if (err)
1862                 goto err_disable_napi;
1863
1864         err = mlx5e_open_sqs(c, params, cparam);
1865         if (err)
1866                 goto err_close_icosq;
1867
1868         if (c->xdp) {
1869                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1870                                        &c->rq_xdpsq, false);
1871                 if (err)
1872                         goto err_close_sqs;
1873         }
1874
1875         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1876         if (err)
1877                 goto err_close_xdp_sq;
1878
1879         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1880         if (err)
1881                 goto err_close_rq;
1882
1883         return 0;
1884
1885 err_close_rq:
1886         mlx5e_close_rq(&c->rq);
1887
1888 err_close_xdp_sq:
1889         if (c->xdp)
1890                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1891
1892 err_close_sqs:
1893         mlx5e_close_sqs(c);
1894
1895 err_close_icosq:
1896         mlx5e_close_icosq(&c->icosq);
1897
1898 err_disable_napi:
1899         napi_disable(&c->napi);
1900
1901         if (c->xdp)
1902                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1903
1904 err_close_rx_cq:
1905         mlx5e_close_cq(&c->rq.cq);
1906
1907 err_close_xdp_tx_cqs:
1908         mlx5e_close_cq(&c->xdpsq.cq);
1909
1910 err_close_tx_cqs:
1911         mlx5e_close_tx_cqs(c);
1912
1913 err_close_icosq_cq:
1914         mlx5e_close_cq(&c->icosq.cq);
1915
1916         return err;
1917 }
1918
1919 static void mlx5e_close_queues(struct mlx5e_channel *c)
1920 {
1921         mlx5e_close_xdpsq(&c->xdpsq);
1922         mlx5e_close_rq(&c->rq);
1923         if (c->xdp)
1924                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1925         mlx5e_close_sqs(c);
1926         mlx5e_close_icosq(&c->icosq);
1927         napi_disable(&c->napi);
1928         if (c->xdp)
1929                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1930         mlx5e_close_cq(&c->rq.cq);
1931         mlx5e_close_cq(&c->xdpsq.cq);
1932         mlx5e_close_tx_cqs(c);
1933         mlx5e_close_cq(&c->icosq.cq);
1934 }
1935
1936 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1937 {
1938         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1939
1940         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1941 }
1942
1943 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1944                               struct mlx5e_params *params,
1945                               struct mlx5e_channel_param *cparam,
1946                               struct xdp_umem *umem,
1947                               struct mlx5e_channel **cp)
1948 {
1949         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1950         struct net_device *netdev = priv->netdev;
1951         struct mlx5e_xsk_param xsk;
1952         struct mlx5e_channel *c;
1953         unsigned int irq;
1954         int err;
1955         int eqn;
1956
1957         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1958         if (err)
1959                 return err;
1960
1961         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1962         if (!c)
1963                 return -ENOMEM;
1964
1965         c->priv     = priv;
1966         c->mdev     = priv->mdev;
1967         c->tstamp   = &priv->tstamp;
1968         c->ix       = ix;
1969         c->cpu      = cpu;
1970         c->pdev     = priv->mdev->device;
1971         c->netdev   = priv->netdev;
1972         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1973         c->num_tc   = params->num_tc;
1974         c->xdp      = !!params->xdp_prog;
1975         c->stats    = &priv->channel_stats[ix].ch;
1976         c->irq_desc = irq_to_desc(irq);
1977         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1978
1979         err = mlx5e_alloc_xps_cpumask(c, params);
1980         if (err)
1981                 goto err_free_channel;
1982
1983         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1984
1985         err = mlx5e_open_queues(c, params, cparam);
1986         if (unlikely(err))
1987                 goto err_napi_del;
1988
1989         if (umem) {
1990                 mlx5e_build_xsk_param(umem, &xsk);
1991                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1992                 if (unlikely(err))
1993                         goto err_close_queues;
1994         }
1995
1996         *cp = c;
1997
1998         return 0;
1999
2000 err_close_queues:
2001         mlx5e_close_queues(c);
2002
2003 err_napi_del:
2004         netif_napi_del(&c->napi);
2005         mlx5e_free_xps_cpumask(c);
2006
2007 err_free_channel:
2008         kvfree(c);
2009
2010         return err;
2011 }
2012
2013 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2014 {
2015         int tc;
2016
2017         for (tc = 0; tc < c->num_tc; tc++)
2018                 mlx5e_activate_txqsq(&c->sq[tc]);
2019         mlx5e_activate_icosq(&c->icosq);
2020         mlx5e_activate_rq(&c->rq);
2021         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2022
2023         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2024                 mlx5e_activate_xsk(c);
2025 }
2026
2027 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2028 {
2029         int tc;
2030
2031         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2032                 mlx5e_deactivate_xsk(c);
2033
2034         mlx5e_deactivate_rq(&c->rq);
2035         mlx5e_deactivate_icosq(&c->icosq);
2036         for (tc = 0; tc < c->num_tc; tc++)
2037                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2038 }
2039
2040 static void mlx5e_close_channel(struct mlx5e_channel *c)
2041 {
2042         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2043                 mlx5e_close_xsk(c);
2044         mlx5e_close_queues(c);
2045         netif_napi_del(&c->napi);
2046         mlx5e_free_xps_cpumask(c);
2047
2048         kvfree(c);
2049 }
2050
2051 #define DEFAULT_FRAG_SIZE (2048)
2052
2053 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2054                                       struct mlx5e_params *params,
2055                                       struct mlx5e_xsk_param *xsk,
2056                                       struct mlx5e_rq_frags_info *info)
2057 {
2058         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2059         int frag_size_max = DEFAULT_FRAG_SIZE;
2060         u32 buf_size = 0;
2061         int i;
2062
2063 #ifdef CONFIG_MLX5_EN_IPSEC
2064         if (MLX5_IPSEC_DEV(mdev))
2065                 byte_count += MLX5E_METADATA_ETHER_LEN;
2066 #endif
2067
2068         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2069                 int frag_stride;
2070
2071                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2072                 frag_stride = roundup_pow_of_two(frag_stride);
2073
2074                 info->arr[0].frag_size = byte_count;
2075                 info->arr[0].frag_stride = frag_stride;
2076                 info->num_frags = 1;
2077                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2078                 goto out;
2079         }
2080
2081         if (byte_count > PAGE_SIZE +
2082             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2083                 frag_size_max = PAGE_SIZE;
2084
2085         i = 0;
2086         while (buf_size < byte_count) {
2087                 int frag_size = byte_count - buf_size;
2088
2089                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2090                         frag_size = min(frag_size, frag_size_max);
2091
2092                 info->arr[i].frag_size = frag_size;
2093                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2094
2095                 buf_size += frag_size;
2096                 i++;
2097         }
2098         info->num_frags = i;
2099         /* number of different wqes sharing a page */
2100         info->wqe_bulk = 1 + (info->num_frags % 2);
2101
2102 out:
2103         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2104         info->log_num_frags = order_base_2(info->num_frags);
2105 }
2106
2107 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2108 {
2109         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2110
2111         switch (wq_type) {
2112         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2113                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2114                 break;
2115         default: /* MLX5_WQ_TYPE_CYCLIC */
2116                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2117         }
2118
2119         return order_base_2(sz);
2120 }
2121
2122 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2123 {
2124         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2125
2126         return MLX5_GET(wq, wq, log_wq_sz);
2127 }
2128
2129 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2130                           struct mlx5e_params *params,
2131                           struct mlx5e_xsk_param *xsk,
2132                           struct mlx5e_rq_param *param)
2133 {
2134         struct mlx5_core_dev *mdev = priv->mdev;
2135         void *rqc = param->rqc;
2136         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2137         int ndsegs = 1;
2138
2139         switch (params->rq_wq_type) {
2140         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2141                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2142                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2143                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2144                 MLX5_SET(wq, wq, log_wqe_stride_size,
2145                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2146                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2147                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2148                 break;
2149         default: /* MLX5_WQ_TYPE_CYCLIC */
2150                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2151                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2152                 ndsegs = param->frags_info.num_frags;
2153         }
2154
2155         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2156         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2157         MLX5_SET(wq, wq, log_wq_stride,
2158                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2159         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2160         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2161         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2162         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2163
2164         param->wq.buf_numa_node = dev_to_node(mdev->device);
2165 }
2166
2167 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2168                                       struct mlx5e_rq_param *param)
2169 {
2170         struct mlx5_core_dev *mdev = priv->mdev;
2171         void *rqc = param->rqc;
2172         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2173
2174         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2175         MLX5_SET(wq, wq, log_wq_stride,
2176                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2177         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2178
2179         param->wq.buf_numa_node = dev_to_node(mdev->device);
2180 }
2181
2182 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2183                                  struct mlx5e_sq_param *param)
2184 {
2185         void *sqc = param->sqc;
2186         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2187
2188         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2189         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2190
2191         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2192 }
2193
2194 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2195                                  struct mlx5e_params *params,
2196                                  struct mlx5e_sq_param *param)
2197 {
2198         void *sqc = param->sqc;
2199         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2200         bool allow_swp;
2201
2202         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2203                     !!MLX5_IPSEC_DEV(priv->mdev);
2204         mlx5e_build_sq_param_common(priv, param);
2205         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2206         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2207 }
2208
2209 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2210                                         struct mlx5e_cq_param *param)
2211 {
2212         void *cqc = param->cqc;
2213
2214         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2215         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2216                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2217 }
2218
2219 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2220                              struct mlx5e_params *params,
2221                              struct mlx5e_xsk_param *xsk,
2222                              struct mlx5e_cq_param *param)
2223 {
2224         struct mlx5_core_dev *mdev = priv->mdev;
2225         void *cqc = param->cqc;
2226         u8 log_cq_size;
2227
2228         switch (params->rq_wq_type) {
2229         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2230                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2231                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2232                 break;
2233         default: /* MLX5_WQ_TYPE_CYCLIC */
2234                 log_cq_size = params->log_rq_mtu_frames;
2235         }
2236
2237         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2238         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2239                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2240                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2241         }
2242
2243         mlx5e_build_common_cq_param(priv, param);
2244         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2245 }
2246
2247 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2248                              struct mlx5e_params *params,
2249                              struct mlx5e_cq_param *param)
2250 {
2251         void *cqc = param->cqc;
2252
2253         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2254
2255         mlx5e_build_common_cq_param(priv, param);
2256         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2257 }
2258
2259 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2260                               u8 log_wq_size,
2261                               struct mlx5e_cq_param *param)
2262 {
2263         void *cqc = param->cqc;
2264
2265         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2266
2267         mlx5e_build_common_cq_param(priv, param);
2268
2269         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2270 }
2271
2272 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2273                              u8 log_wq_size,
2274                              struct mlx5e_sq_param *param)
2275 {
2276         void *sqc = param->sqc;
2277         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2278
2279         mlx5e_build_sq_param_common(priv, param);
2280
2281         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2282         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2283 }
2284
2285 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2286                              struct mlx5e_params *params,
2287                              struct mlx5e_sq_param *param)
2288 {
2289         void *sqc = param->sqc;
2290         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2291
2292         mlx5e_build_sq_param_common(priv, param);
2293         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2294         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2295 }
2296
2297 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2298                                       struct mlx5e_rq_param *rqp)
2299 {
2300         switch (params->rq_wq_type) {
2301         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2302                 return order_base_2(MLX5E_UMR_WQEBBS) +
2303                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2304         default: /* MLX5_WQ_TYPE_CYCLIC */
2305                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2306         }
2307 }
2308
2309 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2310                                       struct mlx5e_params *params,
2311                                       struct mlx5e_channel_param *cparam)
2312 {
2313         u8 icosq_log_wq_sz;
2314
2315         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2316
2317         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2318
2319         mlx5e_build_sq_param(priv, params, &cparam->sq);
2320         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2321         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2322         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2323         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2324         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2325 }
2326
2327 int mlx5e_open_channels(struct mlx5e_priv *priv,
2328                         struct mlx5e_channels *chs)
2329 {
2330         struct mlx5e_channel_param *cparam;
2331         int err = -ENOMEM;
2332         int i;
2333
2334         chs->num = chs->params.num_channels;
2335
2336         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2337         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2338         if (!chs->c || !cparam)
2339                 goto err_free;
2340
2341         mlx5e_build_channel_param(priv, &chs->params, cparam);
2342         for (i = 0; i < chs->num; i++) {
2343                 struct xdp_umem *umem = NULL;
2344
2345                 if (chs->params.xdp_prog)
2346                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2347
2348                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2349                 if (err)
2350                         goto err_close_channels;
2351         }
2352
2353         mlx5e_health_channels_update(priv);
2354         kvfree(cparam);
2355         return 0;
2356
2357 err_close_channels:
2358         for (i--; i >= 0; i--)
2359                 mlx5e_close_channel(chs->c[i]);
2360
2361 err_free:
2362         kfree(chs->c);
2363         kvfree(cparam);
2364         chs->num = 0;
2365         return err;
2366 }
2367
2368 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2369 {
2370         int i;
2371
2372         for (i = 0; i < chs->num; i++)
2373                 mlx5e_activate_channel(chs->c[i]);
2374 }
2375
2376 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2377
2378 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2379 {
2380         int err = 0;
2381         int i;
2382
2383         for (i = 0; i < chs->num; i++) {
2384                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2385
2386                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2387
2388                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2389                  * doesn't provide any Fill Ring entries at the setup stage.
2390                  */
2391         }
2392
2393         return err ? -ETIMEDOUT : 0;
2394 }
2395
2396 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2397 {
2398         int i;
2399
2400         for (i = 0; i < chs->num; i++)
2401                 mlx5e_deactivate_channel(chs->c[i]);
2402 }
2403
2404 void mlx5e_close_channels(struct mlx5e_channels *chs)
2405 {
2406         int i;
2407
2408         for (i = 0; i < chs->num; i++)
2409                 mlx5e_close_channel(chs->c[i]);
2410
2411         kfree(chs->c);
2412         chs->num = 0;
2413 }
2414
2415 static int
2416 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2417 {
2418         struct mlx5_core_dev *mdev = priv->mdev;
2419         void *rqtc;
2420         int inlen;
2421         int err;
2422         u32 *in;
2423         int i;
2424
2425         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2426         in = kvzalloc(inlen, GFP_KERNEL);
2427         if (!in)
2428                 return -ENOMEM;
2429
2430         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2431
2432         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2433         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2434
2435         for (i = 0; i < sz; i++)
2436                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2437
2438         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2439         if (!err)
2440                 rqt->enabled = true;
2441
2442         kvfree(in);
2443         return err;
2444 }
2445
2446 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2447 {
2448         rqt->enabled = false;
2449         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2450 }
2451
2452 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2453 {
2454         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2455         int err;
2456
2457         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2458         if (err)
2459                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2460         return err;
2461 }
2462
2463 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2464 {
2465         int err;
2466         int ix;
2467
2468         for (ix = 0; ix < priv->max_nch; ix++) {
2469                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2470                 if (unlikely(err))
2471                         goto err_destroy_rqts;
2472         }
2473
2474         return 0;
2475
2476 err_destroy_rqts:
2477         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2478         for (ix--; ix >= 0; ix--)
2479                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2480
2481         return err;
2482 }
2483
2484 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2485 {
2486         int i;
2487
2488         for (i = 0; i < priv->max_nch; i++)
2489                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2490 }
2491
2492 static int mlx5e_rx_hash_fn(int hfunc)
2493 {
2494         return (hfunc == ETH_RSS_HASH_TOP) ?
2495                MLX5_RX_HASH_FN_TOEPLITZ :
2496                MLX5_RX_HASH_FN_INVERTED_XOR8;
2497 }
2498
2499 int mlx5e_bits_invert(unsigned long a, int size)
2500 {
2501         int inv = 0;
2502         int i;
2503
2504         for (i = 0; i < size; i++)
2505                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2506
2507         return inv;
2508 }
2509
2510 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2511                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2512 {
2513         int i;
2514
2515         for (i = 0; i < sz; i++) {
2516                 u32 rqn;
2517
2518                 if (rrp.is_rss) {
2519                         int ix = i;
2520
2521                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2522                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2523
2524                         ix = priv->rss_params.indirection_rqt[ix];
2525                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2526                 } else {
2527                         rqn = rrp.rqn;
2528                 }
2529                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2530         }
2531 }
2532
2533 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2534                        struct mlx5e_redirect_rqt_param rrp)
2535 {
2536         struct mlx5_core_dev *mdev = priv->mdev;
2537         void *rqtc;
2538         int inlen;
2539         u32 *in;
2540         int err;
2541
2542         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2543         in = kvzalloc(inlen, GFP_KERNEL);
2544         if (!in)
2545                 return -ENOMEM;
2546
2547         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2548
2549         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2550         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2551         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2552         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2553
2554         kvfree(in);
2555         return err;
2556 }
2557
2558 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2559                                 struct mlx5e_redirect_rqt_param rrp)
2560 {
2561         if (!rrp.is_rss)
2562                 return rrp.rqn;
2563
2564         if (ix >= rrp.rss.channels->num)
2565                 return priv->drop_rq.rqn;
2566
2567         return rrp.rss.channels->c[ix]->rq.rqn;
2568 }
2569
2570 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2571                                 struct mlx5e_redirect_rqt_param rrp)
2572 {
2573         u32 rqtn;
2574         int ix;
2575
2576         if (priv->indir_rqt.enabled) {
2577                 /* RSS RQ table */
2578                 rqtn = priv->indir_rqt.rqtn;
2579                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2580         }
2581
2582         for (ix = 0; ix < priv->max_nch; ix++) {
2583                 struct mlx5e_redirect_rqt_param direct_rrp = {
2584                         .is_rss = false,
2585                         {
2586                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2587                         },
2588                 };
2589
2590                 /* Direct RQ Tables */
2591                 if (!priv->direct_tir[ix].rqt.enabled)
2592                         continue;
2593
2594                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2595                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2596         }
2597 }
2598
2599 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2600                                             struct mlx5e_channels *chs)
2601 {
2602         struct mlx5e_redirect_rqt_param rrp = {
2603                 .is_rss        = true,
2604                 {
2605                         .rss = {
2606                                 .channels  = chs,
2607                                 .hfunc     = priv->rss_params.hfunc,
2608                         }
2609                 },
2610         };
2611
2612         mlx5e_redirect_rqts(priv, rrp);
2613 }
2614
2615 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2616 {
2617         struct mlx5e_redirect_rqt_param drop_rrp = {
2618                 .is_rss = false,
2619                 {
2620                         .rqn = priv->drop_rq.rqn,
2621                 },
2622         };
2623
2624         mlx5e_redirect_rqts(priv, drop_rrp);
2625 }
2626
2627 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2628         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2629                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2630                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2631         },
2632         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2633                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2634                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2635         },
2636         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2637                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2638                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2639         },
2640         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2641                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2642                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2643         },
2644         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2645                                      .l4_prot_type = 0,
2646                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2647         },
2648         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2649                                      .l4_prot_type = 0,
2650                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2651         },
2652         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2653                                       .l4_prot_type = 0,
2654                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2655         },
2656         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2657                                       .l4_prot_type = 0,
2658                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2659         },
2660         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2661                             .l4_prot_type = 0,
2662                             .rx_hash_fields = MLX5_HASH_IP,
2663         },
2664         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2665                             .l4_prot_type = 0,
2666                             .rx_hash_fields = MLX5_HASH_IP,
2667         },
2668 };
2669
2670 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2671 {
2672         return tirc_default_config[tt];
2673 }
2674
2675 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2676 {
2677         if (!params->lro_en)
2678                 return;
2679
2680 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2681
2682         MLX5_SET(tirc, tirc, lro_enable_mask,
2683                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2684                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2685         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2686                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2687         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2688 }
2689
2690 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2691                                     const struct mlx5e_tirc_config *ttconfig,
2692                                     void *tirc, bool inner)
2693 {
2694         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2695                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2696
2697         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2698         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2699                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2700                                              rx_hash_toeplitz_key);
2701                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2702                                                rx_hash_toeplitz_key);
2703
2704                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2705                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2706         }
2707         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2708                  ttconfig->l3_prot_type);
2709         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2710                  ttconfig->l4_prot_type);
2711         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2712                  ttconfig->rx_hash_fields);
2713 }
2714
2715 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2716                                         enum mlx5e_traffic_types tt,
2717                                         u32 rx_hash_fields)
2718 {
2719         *ttconfig                = tirc_default_config[tt];
2720         ttconfig->rx_hash_fields = rx_hash_fields;
2721 }
2722
2723 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2724 {
2725         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2726         struct mlx5e_rss_params *rss = &priv->rss_params;
2727         struct mlx5_core_dev *mdev = priv->mdev;
2728         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2729         struct mlx5e_tirc_config ttconfig;
2730         int tt;
2731
2732         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2733
2734         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2735                 memset(tirc, 0, ctxlen);
2736                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2737                                             rss->rx_hash_fields[tt]);
2738                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2739                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2740         }
2741
2742         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2743                 return;
2744
2745         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2746                 memset(tirc, 0, ctxlen);
2747                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2748                                             rss->rx_hash_fields[tt]);
2749                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2750                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2751                                      inlen);
2752         }
2753 }
2754
2755 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2756 {
2757         struct mlx5_core_dev *mdev = priv->mdev;
2758
2759         void *in;
2760         void *tirc;
2761         int inlen;
2762         int err;
2763         int tt;
2764         int ix;
2765
2766         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2767         in = kvzalloc(inlen, GFP_KERNEL);
2768         if (!in)
2769                 return -ENOMEM;
2770
2771         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2772         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2773
2774         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2775
2776         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2777                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2778                                            inlen);
2779                 if (err)
2780                         goto free_in;
2781         }
2782
2783         for (ix = 0; ix < priv->max_nch; ix++) {
2784                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2785                                            in, inlen);
2786                 if (err)
2787                         goto free_in;
2788         }
2789
2790 free_in:
2791         kvfree(in);
2792
2793         return err;
2794 }
2795
2796 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2797                          struct mlx5e_params *params, u16 mtu)
2798 {
2799         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2800         int err;
2801
2802         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2803         if (err)
2804                 return err;
2805
2806         /* Update vport context MTU */
2807         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2808         return 0;
2809 }
2810
2811 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2812                             struct mlx5e_params *params, u16 *mtu)
2813 {
2814         u16 hw_mtu = 0;
2815         int err;
2816
2817         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2818         if (err || !hw_mtu) /* fallback to port oper mtu */
2819                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2820
2821         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2822 }
2823
2824 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2825 {
2826         struct mlx5e_params *params = &priv->channels.params;
2827         struct net_device *netdev = priv->netdev;
2828         struct mlx5_core_dev *mdev = priv->mdev;
2829         u16 mtu;
2830         int err;
2831
2832         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2833         if (err)
2834                 return err;
2835
2836         mlx5e_query_mtu(mdev, params, &mtu);
2837         if (mtu != params->sw_mtu)
2838                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2839                             __func__, mtu, params->sw_mtu);
2840
2841         params->sw_mtu = mtu;
2842         return 0;
2843 }
2844
2845 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2846 {
2847         struct mlx5e_params *params = &priv->channels.params;
2848         struct net_device *netdev   = priv->netdev;
2849         struct mlx5_core_dev *mdev  = priv->mdev;
2850         u16 max_mtu;
2851
2852         /* MTU range: 68 - hw-specific max */
2853         netdev->min_mtu = ETH_MIN_MTU;
2854
2855         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2856         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2857                                 ETH_MAX_MTU);
2858 }
2859
2860 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2861 {
2862         struct mlx5e_priv *priv = netdev_priv(netdev);
2863         int nch = priv->channels.params.num_channels;
2864         int ntc = priv->channels.params.num_tc;
2865         int tc;
2866
2867         netdev_reset_tc(netdev);
2868
2869         if (ntc == 1)
2870                 return;
2871
2872         netdev_set_num_tc(netdev, ntc);
2873
2874         /* Map netdev TCs to offset 0
2875          * We have our own UP to TXQ mapping for QoS
2876          */
2877         for (tc = 0; tc < ntc; tc++)
2878                 netdev_set_tc_queue(netdev, tc, nch, 0);
2879 }
2880
2881 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2882 {
2883         int i, tc;
2884
2885         for (i = 0; i < priv->max_nch; i++)
2886                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2887                         priv->channel_tc2txq[i][tc] = i + tc * priv->max_nch;
2888 }
2889
2890 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2891 {
2892         struct mlx5e_channel *c;
2893         struct mlx5e_txqsq *sq;
2894         int i, tc;
2895
2896         for (i = 0; i < priv->channels.num; i++) {
2897                 c = priv->channels.c[i];
2898                 for (tc = 0; tc < c->num_tc; tc++) {
2899                         sq = &c->sq[tc];
2900                         priv->txq2sq[sq->txq_ix] = sq;
2901                 }
2902         }
2903 }
2904
2905 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2906 {
2907         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2908         int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2909         struct net_device *netdev = priv->netdev;
2910
2911         mlx5e_netdev_set_tcs(netdev);
2912         netif_set_real_num_tx_queues(netdev, num_txqs);
2913         netif_set_real_num_rx_queues(netdev, num_rxqs);
2914
2915         mlx5e_build_tx2sq_maps(priv);
2916         mlx5e_activate_channels(&priv->channels);
2917         mlx5e_xdp_tx_enable(priv);
2918         netif_tx_start_all_queues(priv->netdev);
2919
2920         if (mlx5e_is_vport_rep(priv))
2921                 mlx5e_add_sqs_fwd_rules(priv);
2922
2923         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2924         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2925
2926         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2927 }
2928
2929 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2930 {
2931         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2932
2933         mlx5e_redirect_rqts_to_drop(priv);
2934
2935         if (mlx5e_is_vport_rep(priv))
2936                 mlx5e_remove_sqs_fwd_rules(priv);
2937
2938         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2939          * polling for inactive tx queues.
2940          */
2941         netif_tx_stop_all_queues(priv->netdev);
2942         netif_tx_disable(priv->netdev);
2943         mlx5e_xdp_tx_disable(priv);
2944         mlx5e_deactivate_channels(&priv->channels);
2945 }
2946
2947 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2948                                        struct mlx5e_channels *new_chs,
2949                                        mlx5e_fp_hw_modify hw_modify)
2950 {
2951         struct net_device *netdev = priv->netdev;
2952         int new_num_txqs;
2953         int carrier_ok;
2954
2955         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2956
2957         carrier_ok = netif_carrier_ok(netdev);
2958         netif_carrier_off(netdev);
2959
2960         if (new_num_txqs < netdev->real_num_tx_queues)
2961                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2962
2963         mlx5e_deactivate_priv_channels(priv);
2964         mlx5e_close_channels(&priv->channels);
2965
2966         priv->channels = *new_chs;
2967
2968         /* New channels are ready to roll, modify HW settings if needed */
2969         if (hw_modify)
2970                 hw_modify(priv);
2971
2972         priv->profile->update_rx(priv);
2973         mlx5e_activate_priv_channels(priv);
2974
2975         /* return carrier back if needed */
2976         if (carrier_ok)
2977                 netif_carrier_on(netdev);
2978 }
2979
2980 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2981                                struct mlx5e_channels *new_chs,
2982                                mlx5e_fp_hw_modify hw_modify)
2983 {
2984         int err;
2985
2986         err = mlx5e_open_channels(priv, new_chs);
2987         if (err)
2988                 return err;
2989
2990         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2991         return 0;
2992 }
2993
2994 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2995 {
2996         struct mlx5e_channels new_channels = {};
2997
2998         new_channels.params = priv->channels.params;
2999         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3000 }
3001
3002 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
3003 {
3004         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
3005         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
3006 }
3007
3008 int mlx5e_open_locked(struct net_device *netdev)
3009 {
3010         struct mlx5e_priv *priv = netdev_priv(netdev);
3011         bool is_xdp = priv->channels.params.xdp_prog;
3012         int err;
3013
3014         set_bit(MLX5E_STATE_OPENED, &priv->state);
3015         if (is_xdp)
3016                 mlx5e_xdp_set_open(priv);
3017
3018         err = mlx5e_open_channels(priv, &priv->channels);
3019         if (err)
3020                 goto err_clear_state_opened_flag;
3021
3022         priv->profile->update_rx(priv);
3023         mlx5e_activate_priv_channels(priv);
3024         if (priv->profile->update_carrier)
3025                 priv->profile->update_carrier(priv);
3026
3027         mlx5e_queue_update_stats(priv);
3028         return 0;
3029
3030 err_clear_state_opened_flag:
3031         if (is_xdp)
3032                 mlx5e_xdp_set_closed(priv);
3033         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3034         return err;
3035 }
3036
3037 int mlx5e_open(struct net_device *netdev)
3038 {
3039         struct mlx5e_priv *priv = netdev_priv(netdev);
3040         int err;
3041
3042         mutex_lock(&priv->state_lock);
3043         err = mlx5e_open_locked(netdev);
3044         if (!err)
3045                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3046         mutex_unlock(&priv->state_lock);
3047
3048         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3049                 udp_tunnel_get_rx_info(netdev);
3050
3051         return err;
3052 }
3053
3054 int mlx5e_close_locked(struct net_device *netdev)
3055 {
3056         struct mlx5e_priv *priv = netdev_priv(netdev);
3057
3058         /* May already be CLOSED in case a previous configuration operation
3059          * (e.g RX/TX queue size change) that involves close&open failed.
3060          */
3061         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3062                 return 0;
3063
3064         if (priv->channels.params.xdp_prog)
3065                 mlx5e_xdp_set_closed(priv);
3066         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3067
3068         netif_carrier_off(priv->netdev);
3069         mlx5e_deactivate_priv_channels(priv);
3070         mlx5e_close_channels(&priv->channels);
3071
3072         return 0;
3073 }
3074
3075 int mlx5e_close(struct net_device *netdev)
3076 {
3077         struct mlx5e_priv *priv = netdev_priv(netdev);
3078         int err;
3079
3080         if (!netif_device_present(netdev))
3081                 return -ENODEV;
3082
3083         mutex_lock(&priv->state_lock);
3084         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3085         err = mlx5e_close_locked(netdev);
3086         mutex_unlock(&priv->state_lock);
3087
3088         return err;
3089 }
3090
3091 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3092                                struct mlx5e_rq *rq,
3093                                struct mlx5e_rq_param *param)
3094 {
3095         void *rqc = param->rqc;
3096         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3097         int err;
3098
3099         param->wq.db_numa_node = param->wq.buf_numa_node;
3100
3101         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3102                                  &rq->wq_ctrl);
3103         if (err)
3104                 return err;
3105
3106         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3107         xdp_rxq_info_unused(&rq->xdp_rxq);
3108
3109         rq->mdev = mdev;
3110
3111         return 0;
3112 }
3113
3114 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3115                                struct mlx5e_cq *cq,
3116                                struct mlx5e_cq_param *param)
3117 {
3118         param->wq.buf_numa_node = dev_to_node(mdev->device);
3119         param->wq.db_numa_node  = dev_to_node(mdev->device);
3120
3121         return mlx5e_alloc_cq_common(mdev, param, cq);
3122 }
3123
3124 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3125                        struct mlx5e_rq *drop_rq)
3126 {
3127         struct mlx5_core_dev *mdev = priv->mdev;
3128         struct mlx5e_cq_param cq_param = {};
3129         struct mlx5e_rq_param rq_param = {};
3130         struct mlx5e_cq *cq = &drop_rq->cq;
3131         int err;
3132
3133         mlx5e_build_drop_rq_param(priv, &rq_param);
3134
3135         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3136         if (err)
3137                 return err;
3138
3139         err = mlx5e_create_cq(cq, &cq_param);
3140         if (err)
3141                 goto err_free_cq;
3142
3143         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3144         if (err)
3145                 goto err_destroy_cq;
3146
3147         err = mlx5e_create_rq(drop_rq, &rq_param);
3148         if (err)
3149                 goto err_free_rq;
3150
3151         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3152         if (err)
3153                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3154
3155         return 0;
3156
3157 err_free_rq:
3158         mlx5e_free_rq(drop_rq);
3159
3160 err_destroy_cq:
3161         mlx5e_destroy_cq(cq);
3162
3163 err_free_cq:
3164         mlx5e_free_cq(cq);
3165
3166         return err;
3167 }
3168
3169 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3170 {
3171         mlx5e_destroy_rq(drop_rq);
3172         mlx5e_free_rq(drop_rq);
3173         mlx5e_destroy_cq(&drop_rq->cq);
3174         mlx5e_free_cq(&drop_rq->cq);
3175 }
3176
3177 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3178 {
3179         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3180
3181         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3182
3183         if (MLX5_GET(tisc, tisc, tls_en))
3184                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3185
3186         if (mlx5_lag_is_lacp_owner(mdev))
3187                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3188
3189         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3190 }
3191
3192 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3193 {
3194         mlx5_core_destroy_tis(mdev, tisn);
3195 }
3196
3197 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3198 {
3199         int tc, i;
3200
3201         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3202                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3203                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3204 }
3205
3206 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3207 {
3208         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3209 }
3210
3211 int mlx5e_create_tises(struct mlx5e_priv *priv)
3212 {
3213         int tc, i;
3214         int err;
3215
3216         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3217                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3218                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3219                         void *tisc;
3220
3221                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3222
3223                         MLX5_SET(tisc, tisc, prio, tc << 1);
3224
3225                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3226                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3227
3228                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3229                         if (err)
3230                                 goto err_close_tises;
3231                 }
3232         }
3233
3234         return 0;
3235
3236 err_close_tises:
3237         for (; i >= 0; i--) {
3238                 for (tc--; tc >= 0; tc--)
3239                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3240                 tc = priv->profile->max_tc;
3241         }
3242
3243         return err;
3244 }
3245
3246 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3247 {
3248         mlx5e_destroy_tises(priv);
3249 }
3250
3251 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3252                                              u32 rqtn, u32 *tirc)
3253 {
3254         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3255         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3256         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3257         MLX5_SET(tirc, tirc, tunneled_offload_en,
3258                  priv->channels.params.tunneled_offload_en);
3259
3260         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3261 }
3262
3263 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3264                                       enum mlx5e_traffic_types tt,
3265                                       u32 *tirc)
3266 {
3267         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3268         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3269                                        &tirc_default_config[tt], tirc, false);
3270 }
3271
3272 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3273 {
3274         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3275         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3276 }
3277
3278 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3279                                             enum mlx5e_traffic_types tt,
3280                                             u32 *tirc)
3281 {
3282         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3283         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3284                                        &tirc_default_config[tt], tirc, true);
3285 }
3286
3287 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3288 {
3289         struct mlx5e_tir *tir;
3290         void *tirc;
3291         int inlen;
3292         int i = 0;
3293         int err;
3294         u32 *in;
3295         int tt;
3296
3297         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3298         in = kvzalloc(inlen, GFP_KERNEL);
3299         if (!in)
3300                 return -ENOMEM;
3301
3302         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3303                 memset(in, 0, inlen);
3304                 tir = &priv->indir_tir[tt];
3305                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3306                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3307                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3308                 if (err) {
3309                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3310                         goto err_destroy_inner_tirs;
3311                 }
3312         }
3313
3314         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3315                 goto out;
3316
3317         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3318                 memset(in, 0, inlen);
3319                 tir = &priv->inner_indir_tir[i];
3320                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3321                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3322                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3323                 if (err) {
3324                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3325                         goto err_destroy_inner_tirs;
3326                 }
3327         }
3328
3329 out:
3330         kvfree(in);
3331
3332         return 0;
3333
3334 err_destroy_inner_tirs:
3335         for (i--; i >= 0; i--)
3336                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3337
3338         for (tt--; tt >= 0; tt--)
3339                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3340
3341         kvfree(in);
3342
3343         return err;
3344 }
3345
3346 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3347 {
3348         struct mlx5e_tir *tir;
3349         void *tirc;
3350         int inlen;
3351         int err = 0;
3352         u32 *in;
3353         int ix;
3354
3355         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3356         in = kvzalloc(inlen, GFP_KERNEL);
3357         if (!in)
3358                 return -ENOMEM;
3359
3360         for (ix = 0; ix < priv->max_nch; ix++) {
3361                 memset(in, 0, inlen);
3362                 tir = &tirs[ix];
3363                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3364                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3365                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3366                 if (unlikely(err))
3367                         goto err_destroy_ch_tirs;
3368         }
3369
3370         goto out;
3371
3372 err_destroy_ch_tirs:
3373         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3374         for (ix--; ix >= 0; ix--)
3375                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3376
3377 out:
3378         kvfree(in);
3379
3380         return err;
3381 }
3382
3383 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3384 {
3385         int i;
3386
3387         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3388                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3389
3390         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3391                 return;
3392
3393         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3394                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3395 }
3396
3397 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3398 {
3399         int i;
3400
3401         for (i = 0; i < priv->max_nch; i++)
3402                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3403 }
3404
3405 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3406 {
3407         int err = 0;
3408         int i;
3409
3410         for (i = 0; i < chs->num; i++) {
3411                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3412                 if (err)
3413                         return err;
3414         }
3415
3416         return 0;
3417 }
3418
3419 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3420 {
3421         int err = 0;
3422         int i;
3423
3424         for (i = 0; i < chs->num; i++) {
3425                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3426                 if (err)
3427                         return err;
3428         }
3429
3430         return 0;
3431 }
3432
3433 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3434                                  struct tc_mqprio_qopt *mqprio)
3435 {
3436         struct mlx5e_channels new_channels = {};
3437         u8 tc = mqprio->num_tc;
3438         int err = 0;
3439
3440         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3441
3442         if (tc && tc != MLX5E_MAX_NUM_TC)
3443                 return -EINVAL;
3444
3445         mutex_lock(&priv->state_lock);
3446
3447         new_channels.params = priv->channels.params;
3448         new_channels.params.num_tc = tc ? tc : 1;
3449
3450         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3451                 priv->channels.params = new_channels.params;
3452                 goto out;
3453         }
3454
3455         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3456         if (err)
3457                 goto out;
3458
3459         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3460                                     new_channels.params.num_tc);
3461 out:
3462         mutex_unlock(&priv->state_lock);
3463         return err;
3464 }
3465
3466 #ifdef CONFIG_MLX5_ESWITCH
3467 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3468                                      struct flow_cls_offload *cls_flower,
3469                                      unsigned long flags)
3470 {
3471         switch (cls_flower->command) {
3472         case FLOW_CLS_REPLACE:
3473                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3474                                               flags);
3475         case FLOW_CLS_DESTROY:
3476                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3477                                            flags);
3478         case FLOW_CLS_STATS:
3479                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3480                                           flags);
3481         default:
3482                 return -EOPNOTSUPP;
3483         }
3484 }
3485
3486 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3487                                    void *cb_priv)
3488 {
3489         unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3490         struct mlx5e_priv *priv = cb_priv;
3491
3492         switch (type) {
3493         case TC_SETUP_CLSFLOWER:
3494                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3495         default:
3496                 return -EOPNOTSUPP;
3497         }
3498 }
3499 #endif
3500
3501 static LIST_HEAD(mlx5e_block_cb_list);
3502
3503 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3504                           void *type_data)
3505 {
3506         struct mlx5e_priv *priv = netdev_priv(dev);
3507
3508         switch (type) {
3509 #ifdef CONFIG_MLX5_ESWITCH
3510         case TC_SETUP_BLOCK: {
3511                 struct flow_block_offload *f = type_data;
3512
3513                 f->unlocked_driver_cb = true;
3514                 return flow_block_cb_setup_simple(type_data,
3515                                                   &mlx5e_block_cb_list,
3516                                                   mlx5e_setup_tc_block_cb,
3517                                                   priv, priv, true);
3518         }
3519 #endif
3520         case TC_SETUP_QDISC_MQPRIO:
3521                 return mlx5e_setup_tc_mqprio(priv, type_data);
3522         default:
3523                 return -EOPNOTSUPP;
3524         }
3525 }
3526
3527 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3528 {
3529         int i;
3530
3531         for (i = 0; i < priv->max_nch; i++) {
3532                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3533                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3534                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3535                 int j;
3536
3537                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3538                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3539
3540                 for (j = 0; j < priv->max_opened_tc; j++) {
3541                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3542
3543                         s->tx_packets    += sq_stats->packets;
3544                         s->tx_bytes      += sq_stats->bytes;
3545                         s->tx_dropped    += sq_stats->dropped;
3546                 }
3547         }
3548 }
3549
3550 void
3551 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3552 {
3553         struct mlx5e_priv *priv = netdev_priv(dev);
3554         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3555         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3556
3557         if (!mlx5e_monitor_counter_supported(priv)) {
3558                 /* update HW stats in background for next time */
3559                 mlx5e_queue_update_stats(priv);
3560         }
3561
3562         if (mlx5e_is_uplink_rep(priv)) {
3563                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3564                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3565                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3566                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3567         } else {
3568                 mlx5e_fold_sw_stats64(priv, stats);
3569         }
3570
3571         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3572
3573         stats->rx_length_errors =
3574                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3575                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3576                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3577         stats->rx_crc_errors =
3578                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3579         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3580         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3581         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3582                            stats->rx_frame_errors;
3583         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3584
3585         /* vport multicast also counts packets that are dropped due to steering
3586          * or rx out of buffer
3587          */
3588         stats->multicast =
3589                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3590 }
3591
3592 static void mlx5e_set_rx_mode(struct net_device *dev)
3593 {
3594         struct mlx5e_priv *priv = netdev_priv(dev);
3595
3596         queue_work(priv->wq, &priv->set_rx_mode_work);
3597 }
3598
3599 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3600 {
3601         struct mlx5e_priv *priv = netdev_priv(netdev);
3602         struct sockaddr *saddr = addr;
3603
3604         if (!is_valid_ether_addr(saddr->sa_data))
3605                 return -EADDRNOTAVAIL;
3606
3607         netif_addr_lock_bh(netdev);
3608         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3609         netif_addr_unlock_bh(netdev);
3610
3611         queue_work(priv->wq, &priv->set_rx_mode_work);
3612
3613         return 0;
3614 }
3615
3616 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3617         do {                                            \
3618                 if (enable)                             \
3619                         *features |= feature;           \
3620                 else                                    \
3621                         *features &= ~feature;          \
3622         } while (0)
3623
3624 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3625
3626 static int set_feature_lro(struct net_device *netdev, bool enable)
3627 {
3628         struct mlx5e_priv *priv = netdev_priv(netdev);
3629         struct mlx5_core_dev *mdev = priv->mdev;
3630         struct mlx5e_channels new_channels = {};
3631         struct mlx5e_params *old_params;
3632         int err = 0;
3633         bool reset;
3634
3635         mutex_lock(&priv->state_lock);
3636
3637         if (enable && priv->xsk.refcnt) {
3638                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3639                             priv->xsk.refcnt);
3640                 err = -EINVAL;
3641                 goto out;
3642         }
3643
3644         old_params = &priv->channels.params;
3645         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3646                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3647                 err = -EINVAL;
3648                 goto out;
3649         }
3650
3651         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3652
3653         new_channels.params = *old_params;
3654         new_channels.params.lro_en = enable;
3655
3656         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3657                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3658                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3659                         reset = false;
3660         }
3661
3662         if (!reset) {
3663                 *old_params = new_channels.params;
3664                 err = mlx5e_modify_tirs_lro(priv);
3665                 goto out;
3666         }
3667
3668         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3669 out:
3670         mutex_unlock(&priv->state_lock);
3671         return err;
3672 }
3673
3674 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3675 {
3676         struct mlx5e_priv *priv = netdev_priv(netdev);
3677
3678         if (enable)
3679                 mlx5e_enable_cvlan_filter(priv);
3680         else
3681                 mlx5e_disable_cvlan_filter(priv);
3682
3683         return 0;
3684 }
3685
3686 #ifdef CONFIG_MLX5_ESWITCH
3687 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3688 {
3689         struct mlx5e_priv *priv = netdev_priv(netdev);
3690
3691         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3692                 netdev_err(netdev,
3693                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3694                 return -EINVAL;
3695         }
3696
3697         return 0;
3698 }
3699 #endif
3700
3701 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3702 {
3703         struct mlx5e_priv *priv = netdev_priv(netdev);
3704         struct mlx5_core_dev *mdev = priv->mdev;
3705
3706         return mlx5_set_port_fcs(mdev, !enable);
3707 }
3708
3709 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3710 {
3711         struct mlx5e_priv *priv = netdev_priv(netdev);
3712         int err;
3713
3714         mutex_lock(&priv->state_lock);
3715
3716         priv->channels.params.scatter_fcs_en = enable;
3717         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3718         if (err)
3719                 priv->channels.params.scatter_fcs_en = !enable;
3720
3721         mutex_unlock(&priv->state_lock);
3722
3723         return err;
3724 }
3725
3726 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3727 {
3728         struct mlx5e_priv *priv = netdev_priv(netdev);
3729         int err = 0;
3730
3731         mutex_lock(&priv->state_lock);
3732
3733         priv->channels.params.vlan_strip_disable = !enable;
3734         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3735                 goto unlock;
3736
3737         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3738         if (err)
3739                 priv->channels.params.vlan_strip_disable = enable;
3740
3741 unlock:
3742         mutex_unlock(&priv->state_lock);
3743
3744         return err;
3745 }
3746
3747 #ifdef CONFIG_MLX5_EN_ARFS
3748 static int set_feature_arfs(struct net_device *netdev, bool enable)
3749 {
3750         struct mlx5e_priv *priv = netdev_priv(netdev);
3751         int err;
3752
3753         if (enable)
3754                 err = mlx5e_arfs_enable(priv);
3755         else
3756                 err = mlx5e_arfs_disable(priv);
3757
3758         return err;
3759 }
3760 #endif
3761
3762 static int mlx5e_handle_feature(struct net_device *netdev,
3763                                 netdev_features_t *features,
3764                                 netdev_features_t wanted_features,
3765                                 netdev_features_t feature,
3766                                 mlx5e_feature_handler feature_handler)
3767 {
3768         netdev_features_t changes = wanted_features ^ netdev->features;
3769         bool enable = !!(wanted_features & feature);
3770         int err;
3771
3772         if (!(changes & feature))
3773                 return 0;
3774
3775         err = feature_handler(netdev, enable);
3776         if (err) {
3777                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3778                            enable ? "Enable" : "Disable", &feature, err);
3779                 return err;
3780         }
3781
3782         MLX5E_SET_FEATURE(features, feature, enable);
3783         return 0;
3784 }
3785
3786 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3787 {
3788         netdev_features_t oper_features = netdev->features;
3789         int err = 0;
3790
3791 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3792         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3793
3794         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3795         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3796                                     set_feature_cvlan_filter);
3797 #ifdef CONFIG_MLX5_ESWITCH
3798         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3799 #endif
3800         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3801         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3802         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3803 #ifdef CONFIG_MLX5_EN_ARFS
3804         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3805 #endif
3806
3807         if (err) {
3808                 netdev->features = oper_features;
3809                 return -EINVAL;
3810         }
3811
3812         return 0;
3813 }
3814
3815 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3816                                             netdev_features_t features)
3817 {
3818         struct mlx5e_priv *priv = netdev_priv(netdev);
3819         struct mlx5e_params *params;
3820
3821         mutex_lock(&priv->state_lock);
3822         params = &priv->channels.params;
3823         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3824                 /* HW strips the outer C-tag header, this is a problem
3825                  * for S-tag traffic.
3826                  */
3827                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3828                 if (!params->vlan_strip_disable)
3829                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3830         }
3831         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3832                 if (features & NETIF_F_LRO) {
3833                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3834                         features &= ~NETIF_F_LRO;
3835                 }
3836         }
3837
3838         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3839                 features &= ~NETIF_F_RXHASH;
3840                 if (netdev->features & NETIF_F_RXHASH)
3841                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3842         }
3843
3844         mutex_unlock(&priv->state_lock);
3845
3846         return features;
3847 }
3848
3849 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3850                                    struct mlx5e_channels *chs,
3851                                    struct mlx5e_params *new_params,
3852                                    struct mlx5_core_dev *mdev)
3853 {
3854         u16 ix;
3855
3856         for (ix = 0; ix < chs->params.num_channels; ix++) {
3857                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3858                 struct mlx5e_xsk_param xsk;
3859
3860                 if (!umem)
3861                         continue;
3862
3863                 mlx5e_build_xsk_param(umem, &xsk);
3864
3865                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3866                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3867                         int max_mtu_frame, max_mtu_page, max_mtu;
3868
3869                         /* Two criteria must be met:
3870                          * 1. HW MTU + all headrooms <= XSK frame size.
3871                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3872                          */
3873                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3874                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3875                         max_mtu = min(max_mtu_frame, max_mtu_page);
3876
3877                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3878                                    new_params->sw_mtu, ix, max_mtu);
3879                         return false;
3880                 }
3881         }
3882
3883         return true;
3884 }
3885
3886 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3887                      change_hw_mtu_cb set_mtu_cb)
3888 {
3889         struct mlx5e_priv *priv = netdev_priv(netdev);
3890         struct mlx5e_channels new_channels = {};
3891         struct mlx5e_params *params;
3892         int err = 0;
3893         bool reset;
3894
3895         mutex_lock(&priv->state_lock);
3896
3897         params = &priv->channels.params;
3898
3899         reset = !params->lro_en;
3900         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3901
3902         new_channels.params = *params;
3903         new_channels.params.sw_mtu = new_mtu;
3904
3905         if (params->xdp_prog &&
3906             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3907                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3908                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3909                 err = -EINVAL;
3910                 goto out;
3911         }
3912
3913         if (priv->xsk.refcnt &&
3914             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3915                                     &new_channels.params, priv->mdev)) {
3916                 err = -EINVAL;
3917                 goto out;
3918         }
3919
3920         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3921                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3922                                                               &new_channels.params,
3923                                                               NULL);
3924                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3925                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3926
3927                 /* If XSK is active, XSK RQs are linear. */
3928                 is_linear |= priv->xsk.refcnt;
3929
3930                 /* Always reset in linear mode - hw_mtu is used in data path. */
3931                 reset = reset && (is_linear || (ppw_old != ppw_new));
3932         }
3933
3934         if (!reset) {
3935                 params->sw_mtu = new_mtu;
3936                 if (set_mtu_cb)
3937                         set_mtu_cb(priv);
3938                 netdev->mtu = params->sw_mtu;
3939                 goto out;
3940         }
3941
3942         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3943         if (err)
3944                 goto out;
3945
3946         netdev->mtu = new_channels.params.sw_mtu;
3947
3948 out:
3949         mutex_unlock(&priv->state_lock);
3950         return err;
3951 }
3952
3953 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3954 {
3955         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3956 }
3957
3958 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3959 {
3960         struct hwtstamp_config config;
3961         int err;
3962
3963         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3964             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3965                 return -EOPNOTSUPP;
3966
3967         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3968                 return -EFAULT;
3969
3970         /* TX HW timestamp */
3971         switch (config.tx_type) {
3972         case HWTSTAMP_TX_OFF:
3973         case HWTSTAMP_TX_ON:
3974                 break;
3975         default:
3976                 return -ERANGE;
3977         }
3978
3979         mutex_lock(&priv->state_lock);
3980         /* RX HW timestamp */
3981         switch (config.rx_filter) {
3982         case HWTSTAMP_FILTER_NONE:
3983                 /* Reset CQE compression to Admin default */
3984                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3985                 break;
3986         case HWTSTAMP_FILTER_ALL:
3987         case HWTSTAMP_FILTER_SOME:
3988         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3989         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3990         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3991         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3992         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3993         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3994         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3995         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3996         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3997         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3998         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3999         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4000         case HWTSTAMP_FILTER_NTP_ALL:
4001                 /* Disable CQE compression */
4002                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4003                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
4004                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
4005                 if (err) {
4006                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
4007                         mutex_unlock(&priv->state_lock);
4008                         return err;
4009                 }
4010                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4011                 break;
4012         default:
4013                 mutex_unlock(&priv->state_lock);
4014                 return -ERANGE;
4015         }
4016
4017         memcpy(&priv->tstamp, &config, sizeof(config));
4018         mutex_unlock(&priv->state_lock);
4019
4020         /* might need to fix some features */
4021         netdev_update_features(priv->netdev);
4022
4023         return copy_to_user(ifr->ifr_data, &config,
4024                             sizeof(config)) ? -EFAULT : 0;
4025 }
4026
4027 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4028 {
4029         struct hwtstamp_config *cfg = &priv->tstamp;
4030
4031         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4032                 return -EOPNOTSUPP;
4033
4034         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4035 }
4036
4037 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4038 {
4039         struct mlx5e_priv *priv = netdev_priv(dev);
4040
4041         switch (cmd) {
4042         case SIOCSHWTSTAMP:
4043                 return mlx5e_hwstamp_set(priv, ifr);
4044         case SIOCGHWTSTAMP:
4045                 return mlx5e_hwstamp_get(priv, ifr);
4046         default:
4047                 return -EOPNOTSUPP;
4048         }
4049 }
4050
4051 #ifdef CONFIG_MLX5_ESWITCH
4052 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4053 {
4054         struct mlx5e_priv *priv = netdev_priv(dev);
4055         struct mlx5_core_dev *mdev = priv->mdev;
4056
4057         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4058 }
4059
4060 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4061                              __be16 vlan_proto)
4062 {
4063         struct mlx5e_priv *priv = netdev_priv(dev);
4064         struct mlx5_core_dev *mdev = priv->mdev;
4065
4066         if (vlan_proto != htons(ETH_P_8021Q))
4067                 return -EPROTONOSUPPORT;
4068
4069         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4070                                            vlan, qos);
4071 }
4072
4073 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4074 {
4075         struct mlx5e_priv *priv = netdev_priv(dev);
4076         struct mlx5_core_dev *mdev = priv->mdev;
4077
4078         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4079 }
4080
4081 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4082 {
4083         struct mlx5e_priv *priv = netdev_priv(dev);
4084         struct mlx5_core_dev *mdev = priv->mdev;
4085
4086         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4087 }
4088
4089 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4090                       int max_tx_rate)
4091 {
4092         struct mlx5e_priv *priv = netdev_priv(dev);
4093         struct mlx5_core_dev *mdev = priv->mdev;
4094
4095         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4096                                            max_tx_rate, min_tx_rate);
4097 }
4098
4099 static int mlx5_vport_link2ifla(u8 esw_link)
4100 {
4101         switch (esw_link) {
4102         case MLX5_VPORT_ADMIN_STATE_DOWN:
4103                 return IFLA_VF_LINK_STATE_DISABLE;
4104         case MLX5_VPORT_ADMIN_STATE_UP:
4105                 return IFLA_VF_LINK_STATE_ENABLE;
4106         }
4107         return IFLA_VF_LINK_STATE_AUTO;
4108 }
4109
4110 static int mlx5_ifla_link2vport(u8 ifla_link)
4111 {
4112         switch (ifla_link) {
4113         case IFLA_VF_LINK_STATE_DISABLE:
4114                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4115         case IFLA_VF_LINK_STATE_ENABLE:
4116                 return MLX5_VPORT_ADMIN_STATE_UP;
4117         }
4118         return MLX5_VPORT_ADMIN_STATE_AUTO;
4119 }
4120
4121 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4122                                    int link_state)
4123 {
4124         struct mlx5e_priv *priv = netdev_priv(dev);
4125         struct mlx5_core_dev *mdev = priv->mdev;
4126
4127         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4128                                             mlx5_ifla_link2vport(link_state));
4129 }
4130
4131 int mlx5e_get_vf_config(struct net_device *dev,
4132                         int vf, struct ifla_vf_info *ivi)
4133 {
4134         struct mlx5e_priv *priv = netdev_priv(dev);
4135         struct mlx5_core_dev *mdev = priv->mdev;
4136         int err;
4137
4138         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4139         if (err)
4140                 return err;
4141         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4142         return 0;
4143 }
4144
4145 int mlx5e_get_vf_stats(struct net_device *dev,
4146                        int vf, struct ifla_vf_stats *vf_stats)
4147 {
4148         struct mlx5e_priv *priv = netdev_priv(dev);
4149         struct mlx5_core_dev *mdev = priv->mdev;
4150
4151         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4152                                             vf_stats);
4153 }
4154 #endif
4155
4156 struct mlx5e_vxlan_work {
4157         struct work_struct      work;
4158         struct mlx5e_priv       *priv;
4159         u16                     port;
4160 };
4161
4162 static void mlx5e_vxlan_add_work(struct work_struct *work)
4163 {
4164         struct mlx5e_vxlan_work *vxlan_work =
4165                 container_of(work, struct mlx5e_vxlan_work, work);
4166         struct mlx5e_priv *priv = vxlan_work->priv;
4167         u16 port = vxlan_work->port;
4168
4169         mutex_lock(&priv->state_lock);
4170         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4171         mutex_unlock(&priv->state_lock);
4172
4173         kfree(vxlan_work);
4174 }
4175
4176 static void mlx5e_vxlan_del_work(struct work_struct *work)
4177 {
4178         struct mlx5e_vxlan_work *vxlan_work =
4179                 container_of(work, struct mlx5e_vxlan_work, work);
4180         struct mlx5e_priv *priv         = vxlan_work->priv;
4181         u16 port = vxlan_work->port;
4182
4183         mutex_lock(&priv->state_lock);
4184         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4185         mutex_unlock(&priv->state_lock);
4186         kfree(vxlan_work);
4187 }
4188
4189 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4190 {
4191         struct mlx5e_vxlan_work *vxlan_work;
4192
4193         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4194         if (!vxlan_work)
4195                 return;
4196
4197         if (add)
4198                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4199         else
4200                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4201
4202         vxlan_work->priv = priv;
4203         vxlan_work->port = port;
4204         queue_work(priv->wq, &vxlan_work->work);
4205 }
4206
4207 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4208 {
4209         struct mlx5e_priv *priv = netdev_priv(netdev);
4210
4211         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4212                 return;
4213
4214         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4215                 return;
4216
4217         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4218 }
4219
4220 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4221 {
4222         struct mlx5e_priv *priv = netdev_priv(netdev);
4223
4224         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4225                 return;
4226
4227         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4228                 return;
4229
4230         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4231 }
4232
4233 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4234                                                      struct sk_buff *skb,
4235                                                      netdev_features_t features)
4236 {
4237         unsigned int offset = 0;
4238         struct udphdr *udph;
4239         u8 proto;
4240         u16 port;
4241
4242         switch (vlan_get_protocol(skb)) {
4243         case htons(ETH_P_IP):
4244                 proto = ip_hdr(skb)->protocol;
4245                 break;
4246         case htons(ETH_P_IPV6):
4247                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4248                 break;
4249         default:
4250                 goto out;
4251         }
4252
4253         switch (proto) {
4254         case IPPROTO_GRE:
4255         case IPPROTO_IPIP:
4256         case IPPROTO_IPV6:
4257                 return features;
4258         case IPPROTO_UDP:
4259                 udph = udp_hdr(skb);
4260                 port = be16_to_cpu(udph->dest);
4261
4262                 /* Verify if UDP port is being offloaded by HW */
4263                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4264                         return features;
4265
4266 #if IS_ENABLED(CONFIG_GENEVE)
4267                 /* Support Geneve offload for default UDP port */
4268                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4269                         return features;
4270 #endif
4271         }
4272
4273 out:
4274         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4275         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4276 }
4277
4278 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4279                                        struct net_device *netdev,
4280                                        netdev_features_t features)
4281 {
4282         struct mlx5e_priv *priv = netdev_priv(netdev);
4283
4284         features = vlan_features_check(skb, features);
4285         features = vxlan_features_check(skb, features);
4286
4287 #ifdef CONFIG_MLX5_EN_IPSEC
4288         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4289                 return features;
4290 #endif
4291
4292         /* Validate if the tunneled packet is being offloaded by HW */
4293         if (skb->encapsulation &&
4294             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4295                 return mlx5e_tunnel_features_check(priv, skb, features);
4296
4297         return features;
4298 }
4299
4300 static void mlx5e_tx_timeout_work(struct work_struct *work)
4301 {
4302         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4303                                                tx_timeout_work);
4304         bool report_failed = false;
4305         int err;
4306         int i;
4307
4308         rtnl_lock();
4309         mutex_lock(&priv->state_lock);
4310
4311         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4312                 goto unlock;
4313
4314         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4315                 struct netdev_queue *dev_queue =
4316                         netdev_get_tx_queue(priv->netdev, i);
4317                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4318
4319                 if (!netif_xmit_stopped(dev_queue))
4320                         continue;
4321
4322                 if (mlx5e_reporter_tx_timeout(sq))
4323                         report_failed = true;
4324         }
4325
4326         if (!report_failed)
4327                 goto unlock;
4328
4329         err = mlx5e_safe_reopen_channels(priv);
4330         if (err)
4331                 netdev_err(priv->netdev,
4332                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4333                            err);
4334
4335 unlock:
4336         mutex_unlock(&priv->state_lock);
4337         rtnl_unlock();
4338 }
4339
4340 static void mlx5e_tx_timeout(struct net_device *dev)
4341 {
4342         struct mlx5e_priv *priv = netdev_priv(dev);
4343
4344         netdev_err(dev, "TX timeout detected\n");
4345         queue_work(priv->wq, &priv->tx_timeout_work);
4346 }
4347
4348 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4349 {
4350         struct net_device *netdev = priv->netdev;
4351         struct mlx5e_channels new_channels = {};
4352
4353         if (priv->channels.params.lro_en) {
4354                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4355                 return -EINVAL;
4356         }
4357
4358         if (MLX5_IPSEC_DEV(priv->mdev)) {
4359                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4360                 return -EINVAL;
4361         }
4362
4363         new_channels.params = priv->channels.params;
4364         new_channels.params.xdp_prog = prog;
4365
4366         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4367          * the XDP program.
4368          */
4369         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4370                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4371                             new_channels.params.sw_mtu,
4372                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4373                 return -EINVAL;
4374         }
4375
4376         return 0;
4377 }
4378
4379 static int mlx5e_xdp_update_state(struct mlx5e_priv *priv)
4380 {
4381         if (priv->channels.params.xdp_prog)
4382                 mlx5e_xdp_set_open(priv);
4383         else
4384                 mlx5e_xdp_set_closed(priv);
4385
4386         return 0;
4387 }
4388
4389 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4390 {
4391         struct mlx5e_priv *priv = netdev_priv(netdev);
4392         struct bpf_prog *old_prog;
4393         bool reset, was_opened;
4394         int err = 0;
4395         int i;
4396
4397         mutex_lock(&priv->state_lock);
4398
4399         if (prog) {
4400                 err = mlx5e_xdp_allowed(priv, prog);
4401                 if (err)
4402                         goto unlock;
4403         }
4404
4405         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4406         /* no need for full reset when exchanging programs */
4407         reset = (!priv->channels.params.xdp_prog || !prog);
4408
4409         if (was_opened && !reset) {
4410                 /* num_channels is invariant here, so we can take the
4411                  * batched reference right upfront.
4412                  */
4413                 prog = bpf_prog_add(prog, priv->channels.num);
4414                 if (IS_ERR(prog)) {
4415                         err = PTR_ERR(prog);
4416                         goto unlock;
4417                 }
4418         }
4419
4420         if (was_opened && reset) {
4421                 struct mlx5e_channels new_channels = {};
4422
4423                 new_channels.params = priv->channels.params;
4424                 new_channels.params.xdp_prog = prog;
4425                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4426                 old_prog = priv->channels.params.xdp_prog;
4427
4428                 err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_xdp_update_state);
4429                 if (err)
4430                         goto unlock;
4431         } else {
4432                 /* exchange programs, extra prog reference we got from caller
4433                  * as long as we don't fail from this point onwards.
4434                  */
4435                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4436         }
4437
4438         if (old_prog)
4439                 bpf_prog_put(old_prog);
4440
4441         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4442                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4443
4444         if (!was_opened || reset)
4445                 goto unlock;
4446
4447         /* exchanging programs w/o reset, we update ref counts on behalf
4448          * of the channels RQs here.
4449          */
4450         for (i = 0; i < priv->channels.num; i++) {
4451                 struct mlx5e_channel *c = priv->channels.c[i];
4452                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4453
4454                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4455                 if (xsk_open)
4456                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4457                 napi_synchronize(&c->napi);
4458                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4459
4460                 old_prog = xchg(&c->rq.xdp_prog, prog);
4461                 if (old_prog)
4462                         bpf_prog_put(old_prog);
4463
4464                 if (xsk_open) {
4465                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4466                         if (old_prog)
4467                                 bpf_prog_put(old_prog);
4468                 }
4469
4470                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4471                 if (xsk_open)
4472                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4473                 /* napi_schedule in case we have missed anything */
4474                 napi_schedule(&c->napi);
4475         }
4476
4477 unlock:
4478         mutex_unlock(&priv->state_lock);
4479         return err;
4480 }
4481
4482 static u32 mlx5e_xdp_query(struct net_device *dev)
4483 {
4484         struct mlx5e_priv *priv = netdev_priv(dev);
4485         const struct bpf_prog *xdp_prog;
4486         u32 prog_id = 0;
4487
4488         mutex_lock(&priv->state_lock);
4489         xdp_prog = priv->channels.params.xdp_prog;
4490         if (xdp_prog)
4491                 prog_id = xdp_prog->aux->id;
4492         mutex_unlock(&priv->state_lock);
4493
4494         return prog_id;
4495 }
4496
4497 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4498 {
4499         switch (xdp->command) {
4500         case XDP_SETUP_PROG:
4501                 return mlx5e_xdp_set(dev, xdp->prog);
4502         case XDP_QUERY_PROG:
4503                 xdp->prog_id = mlx5e_xdp_query(dev);
4504                 return 0;
4505         case XDP_SETUP_XSK_UMEM:
4506                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4507                                             xdp->xsk.queue_id);
4508         default:
4509                 return -EINVAL;
4510         }
4511 }
4512
4513 #ifdef CONFIG_MLX5_ESWITCH
4514 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4515                                 struct net_device *dev, u32 filter_mask,
4516                                 int nlflags)
4517 {
4518         struct mlx5e_priv *priv = netdev_priv(dev);
4519         struct mlx5_core_dev *mdev = priv->mdev;
4520         u8 mode, setting;
4521         int err;
4522
4523         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4524         if (err)
4525                 return err;
4526         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4527         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4528                                        mode,
4529                                        0, 0, nlflags, filter_mask, NULL);
4530 }
4531
4532 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4533                                 u16 flags, struct netlink_ext_ack *extack)
4534 {
4535         struct mlx5e_priv *priv = netdev_priv(dev);
4536         struct mlx5_core_dev *mdev = priv->mdev;
4537         struct nlattr *attr, *br_spec;
4538         u16 mode = BRIDGE_MODE_UNDEF;
4539         u8 setting;
4540         int rem;
4541
4542         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4543         if (!br_spec)
4544                 return -EINVAL;
4545
4546         nla_for_each_nested(attr, br_spec, rem) {
4547                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4548                         continue;
4549
4550                 if (nla_len(attr) < sizeof(mode))
4551                         return -EINVAL;
4552
4553                 mode = nla_get_u16(attr);
4554                 if (mode > BRIDGE_MODE_VEPA)
4555                         return -EINVAL;
4556
4557                 break;
4558         }
4559
4560         if (mode == BRIDGE_MODE_UNDEF)
4561                 return -EINVAL;
4562
4563         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4564         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4565 }
4566 #endif
4567
4568 const struct net_device_ops mlx5e_netdev_ops = {
4569         .ndo_open                = mlx5e_open,
4570         .ndo_stop                = mlx5e_close,
4571         .ndo_start_xmit          = mlx5e_xmit,
4572         .ndo_setup_tc            = mlx5e_setup_tc,
4573         .ndo_select_queue        = mlx5e_select_queue,
4574         .ndo_get_stats64         = mlx5e_get_stats,
4575         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4576         .ndo_set_mac_address     = mlx5e_set_mac,
4577         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4578         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4579         .ndo_set_features        = mlx5e_set_features,
4580         .ndo_fix_features        = mlx5e_fix_features,
4581         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4582         .ndo_do_ioctl            = mlx5e_ioctl,
4583         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4584         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4585         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4586         .ndo_features_check      = mlx5e_features_check,
4587         .ndo_tx_timeout          = mlx5e_tx_timeout,
4588         .ndo_bpf                 = mlx5e_xdp,
4589         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4590         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4591 #ifdef CONFIG_MLX5_EN_ARFS
4592         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4593 #endif
4594 #ifdef CONFIG_MLX5_ESWITCH
4595         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4596         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4597
4598         /* SRIOV E-Switch NDOs */
4599         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4600         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4601         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4602         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4603         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4604         .ndo_get_vf_config       = mlx5e_get_vf_config,
4605         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4606         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4607 #endif
4608 };
4609
4610 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4611 {
4612         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4613                 return -EOPNOTSUPP;
4614         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4615             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4616             !MLX5_CAP_ETH(mdev, csum_cap) ||
4617             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4618             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4619             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4620             MLX5_CAP_FLOWTABLE(mdev,
4621                                flow_table_properties_nic_receive.max_ft_level)
4622                                < 3) {
4623                 mlx5_core_warn(mdev,
4624                                "Not creating net device, some required device capabilities are missing\n");
4625                 return -EOPNOTSUPP;
4626         }
4627         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4628                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4629         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4630                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4631
4632         return 0;
4633 }
4634
4635 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4636                                    int num_channels)
4637 {
4638         int i;
4639
4640         for (i = 0; i < len; i++)
4641                 indirection_rqt[i] = i % num_channels;
4642 }
4643
4644 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4645 {
4646         u32 link_speed = 0;
4647         u32 pci_bw = 0;
4648
4649         mlx5e_port_max_linkspeed(mdev, &link_speed);
4650         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4651         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4652                            link_speed, pci_bw);
4653
4654 #define MLX5E_SLOW_PCI_RATIO (2)
4655
4656         return link_speed && pci_bw &&
4657                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4658 }
4659
4660 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4661 {
4662         struct dim_cq_moder moder;
4663
4664         moder.cq_period_mode = cq_period_mode;
4665         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4666         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4667         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4668                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4669
4670         return moder;
4671 }
4672
4673 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4674 {
4675         struct dim_cq_moder moder;
4676
4677         moder.cq_period_mode = cq_period_mode;
4678         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4679         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4680         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4681                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4682
4683         return moder;
4684 }
4685
4686 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4687 {
4688         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4689                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4690                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4691 }
4692
4693 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4694 {
4695         if (params->tx_dim_enabled) {
4696                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4697
4698                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4699         } else {
4700                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4701         }
4702
4703         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4704                         params->tx_cq_moderation.cq_period_mode ==
4705                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4706 }
4707
4708 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4709 {
4710         if (params->rx_dim_enabled) {
4711                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4712
4713                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4714         } else {
4715                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4716         }
4717
4718         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4719                         params->rx_cq_moderation.cq_period_mode ==
4720                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4721 }
4722
4723 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4724 {
4725         int i;
4726
4727         /* The supported periods are organized in ascending order */
4728         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4729                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4730                         break;
4731
4732         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4733 }
4734
4735 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4736                            struct mlx5e_params *params)
4737 {
4738         /* Prefer Striding RQ, unless any of the following holds:
4739          * - Striding RQ configuration is not possible/supported.
4740          * - Slow PCI heuristic.
4741          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4742          *
4743          * No XSK params: checking the availability of striding RQ in general.
4744          */
4745         if (!slow_pci_heuristic(mdev) &&
4746             mlx5e_striding_rq_possible(mdev, params) &&
4747             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4748              !mlx5e_rx_is_linear_skb(params, NULL)))
4749                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4750         mlx5e_set_rq_type(mdev, params);
4751         mlx5e_init_rq_type_params(mdev, params);
4752 }
4753
4754 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4755                             u16 num_channels)
4756 {
4757         enum mlx5e_traffic_types tt;
4758
4759         rss_params->hfunc = ETH_RSS_HASH_TOP;
4760         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4761                             sizeof(rss_params->toeplitz_hash_key));
4762         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4763                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4764         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4765                 rss_params->rx_hash_fields[tt] =
4766                         tirc_default_config[tt].rx_hash_fields;
4767 }
4768
4769 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4770                             struct mlx5e_xsk *xsk,
4771                             struct mlx5e_rss_params *rss_params,
4772                             struct mlx5e_params *params,
4773                             u16 max_channels, u16 mtu)
4774 {
4775         u8 rx_cq_period_mode;
4776
4777         params->sw_mtu = mtu;
4778         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4779         params->num_channels = max_channels;
4780         params->num_tc       = 1;
4781
4782         /* SQ */
4783         params->log_sq_size = is_kdump_kernel() ?
4784                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4785                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4786
4787         /* XDP SQ */
4788         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4789                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4790
4791         /* set CQE compression */
4792         params->rx_cqe_compress_def = false;
4793         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4794             MLX5_CAP_GEN(mdev, vport_group_manager))
4795                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4796
4797         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4798         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4799
4800         /* RQ */
4801         mlx5e_build_rq_params(mdev, params);
4802
4803         /* HW LRO */
4804
4805         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4806         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4807                 /* No XSK params: checking the availability of striding RQ in general. */
4808                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4809                         params->lro_en = !slow_pci_heuristic(mdev);
4810         }
4811         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4812
4813         /* CQ moderation params */
4814         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4815                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4816                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4817         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4818         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4819         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4820         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4821
4822         /* TX inline */
4823         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4824
4825         /* RSS */
4826         mlx5e_build_rss_params(rss_params, params->num_channels);
4827         params->tunneled_offload_en =
4828                 mlx5e_tunnel_inner_ft_supported(mdev);
4829
4830         /* AF_XDP */
4831         params->xsk = xsk;
4832 }
4833
4834 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4835 {
4836         struct mlx5e_priv *priv = netdev_priv(netdev);
4837
4838         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4839         if (is_zero_ether_addr(netdev->dev_addr) &&
4840             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4841                 eth_hw_addr_random(netdev);
4842                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4843         }
4844 }
4845
4846 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4847 {
4848         struct mlx5e_priv *priv = netdev_priv(netdev);
4849         struct mlx5_core_dev *mdev = priv->mdev;
4850         bool fcs_supported;
4851         bool fcs_enabled;
4852
4853         SET_NETDEV_DEV(netdev, mdev->device);
4854
4855         netdev->netdev_ops = &mlx5e_netdev_ops;
4856
4857 #ifdef CONFIG_MLX5_CORE_EN_DCB
4858         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4859                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4860 #endif
4861
4862         netdev->watchdog_timeo    = 15 * HZ;
4863
4864         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4865
4866         netdev->vlan_features    |= NETIF_F_SG;
4867         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4868         netdev->vlan_features    |= NETIF_F_GRO;
4869         netdev->vlan_features    |= NETIF_F_TSO;
4870         netdev->vlan_features    |= NETIF_F_TSO6;
4871         netdev->vlan_features    |= NETIF_F_RXCSUM;
4872         netdev->vlan_features    |= NETIF_F_RXHASH;
4873
4874         netdev->mpls_features    |= NETIF_F_SG;
4875         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4876         netdev->mpls_features    |= NETIF_F_TSO;
4877         netdev->mpls_features    |= NETIF_F_TSO6;
4878
4879         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4880         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4881
4882         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4883             mlx5e_check_fragmented_striding_rq_cap(mdev))
4884                 netdev->vlan_features    |= NETIF_F_LRO;
4885
4886         netdev->hw_features       = netdev->vlan_features;
4887         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4888         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4889         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4890         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4891
4892         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4893             mlx5e_any_tunnel_proto_supported(mdev)) {
4894                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4895                 netdev->hw_enc_features |= NETIF_F_TSO;
4896                 netdev->hw_enc_features |= NETIF_F_TSO6;
4897                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4898         }
4899
4900         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4901                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4902                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4903                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4904                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4905                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4906         }
4907
4908         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4909                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4910                                            NETIF_F_GSO_GRE_CSUM;
4911                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4912                                            NETIF_F_GSO_GRE_CSUM;
4913                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4914                                                 NETIF_F_GSO_GRE_CSUM;
4915         }
4916
4917         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4918                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4919                                        NETIF_F_GSO_IPXIP6;
4920                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4921                                            NETIF_F_GSO_IPXIP6;
4922                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4923                                                 NETIF_F_GSO_IPXIP6;
4924         }
4925
4926         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4927         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4928         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4929         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4930
4931         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4932
4933         if (fcs_supported)
4934                 netdev->hw_features |= NETIF_F_RXALL;
4935
4936         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4937                 netdev->hw_features |= NETIF_F_RXFCS;
4938
4939         netdev->features          = netdev->hw_features;
4940         if (!priv->channels.params.lro_en)
4941                 netdev->features  &= ~NETIF_F_LRO;
4942
4943         if (fcs_enabled)
4944                 netdev->features  &= ~NETIF_F_RXALL;
4945
4946         if (!priv->channels.params.scatter_fcs_en)
4947                 netdev->features  &= ~NETIF_F_RXFCS;
4948
4949         /* prefere CQE compression over rxhash */
4950         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4951                 netdev->features &= ~NETIF_F_RXHASH;
4952
4953 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4954         if (FT_CAP(flow_modify_en) &&
4955             FT_CAP(modify_root) &&
4956             FT_CAP(identified_miss_table_mode) &&
4957             FT_CAP(flow_table_modify)) {
4958 #ifdef CONFIG_MLX5_ESWITCH
4959                 netdev->hw_features      |= NETIF_F_HW_TC;
4960 #endif
4961 #ifdef CONFIG_MLX5_EN_ARFS
4962                 netdev->hw_features      |= NETIF_F_NTUPLE;
4963 #endif
4964         }
4965
4966         netdev->features         |= NETIF_F_HIGHDMA;
4967         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4968
4969         netdev->priv_flags       |= IFF_UNICAST_FLT;
4970
4971         mlx5e_set_netdev_dev_addr(netdev);
4972         mlx5e_ipsec_build_netdev(priv);
4973         mlx5e_tls_build_netdev(priv);
4974 }
4975
4976 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4977 {
4978         struct mlx5_core_dev *mdev = priv->mdev;
4979         int err;
4980
4981         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4982         if (err) {
4983                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4984                 priv->q_counter = 0;
4985         }
4986
4987         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4988         if (err) {
4989                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4990                 priv->drop_rq_q_counter = 0;
4991         }
4992 }
4993
4994 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4995 {
4996         if (priv->q_counter)
4997                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4998
4999         if (priv->drop_rq_q_counter)
5000                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
5001 }
5002
5003 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
5004                           struct net_device *netdev,
5005                           const struct mlx5e_profile *profile,
5006                           void *ppriv)
5007 {
5008         struct mlx5e_priv *priv = netdev_priv(netdev);
5009         struct mlx5e_rss_params *rss = &priv->rss_params;
5010         int err;
5011
5012         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
5013         if (err)
5014                 return err;
5015
5016         mlx5e_build_nic_params(mdev, &priv->xsk, rss, &priv->channels.params,
5017                                priv->max_nch, netdev->mtu);
5018
5019         mlx5e_timestamp_init(priv);
5020
5021         err = mlx5e_ipsec_init(priv);
5022         if (err)
5023                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
5024         err = mlx5e_tls_init(priv);
5025         if (err)
5026                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
5027         mlx5e_build_nic_netdev(netdev);
5028         mlx5e_build_tc2txq_maps(priv);
5029         mlx5e_health_create_reporters(priv);
5030
5031         return 0;
5032 }
5033
5034 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5035 {
5036         mlx5e_health_destroy_reporters(priv);
5037         mlx5e_tls_cleanup(priv);
5038         mlx5e_ipsec_cleanup(priv);
5039         mlx5e_netdev_cleanup(priv->netdev, priv);
5040 }
5041
5042 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5043 {
5044         struct mlx5_core_dev *mdev = priv->mdev;
5045         int err;
5046
5047         mlx5e_create_q_counters(priv);
5048
5049         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5050         if (err) {
5051                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5052                 goto err_destroy_q_counters;
5053         }
5054
5055         err = mlx5e_create_indirect_rqt(priv);
5056         if (err)
5057                 goto err_close_drop_rq;
5058
5059         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5060         if (err)
5061                 goto err_destroy_indirect_rqts;
5062
5063         err = mlx5e_create_indirect_tirs(priv, true);
5064         if (err)
5065                 goto err_destroy_direct_rqts;
5066
5067         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5068         if (err)
5069                 goto err_destroy_indirect_tirs;
5070
5071         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5072         if (unlikely(err))
5073                 goto err_destroy_direct_tirs;
5074
5075         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5076         if (unlikely(err))
5077                 goto err_destroy_xsk_rqts;
5078
5079         err = mlx5e_create_flow_steering(priv);
5080         if (err) {
5081                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5082                 goto err_destroy_xsk_tirs;
5083         }
5084
5085         err = mlx5e_tc_nic_init(priv);
5086         if (err)
5087                 goto err_destroy_flow_steering;
5088
5089         return 0;
5090
5091 err_destroy_flow_steering:
5092         mlx5e_destroy_flow_steering(priv);
5093 err_destroy_xsk_tirs:
5094         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5095 err_destroy_xsk_rqts:
5096         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5097 err_destroy_direct_tirs:
5098         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5099 err_destroy_indirect_tirs:
5100         mlx5e_destroy_indirect_tirs(priv, true);
5101 err_destroy_direct_rqts:
5102         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5103 err_destroy_indirect_rqts:
5104         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5105 err_close_drop_rq:
5106         mlx5e_close_drop_rq(&priv->drop_rq);
5107 err_destroy_q_counters:
5108         mlx5e_destroy_q_counters(priv);
5109         return err;
5110 }
5111
5112 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5113 {
5114         mlx5e_tc_nic_cleanup(priv);
5115         mlx5e_destroy_flow_steering(priv);
5116         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5117         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5118         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5119         mlx5e_destroy_indirect_tirs(priv, true);
5120         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5121         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5122         mlx5e_close_drop_rq(&priv->drop_rq);
5123         mlx5e_destroy_q_counters(priv);
5124 }
5125
5126 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5127 {
5128         int err;
5129
5130         err = mlx5e_create_tises(priv);
5131         if (err) {
5132                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5133                 return err;
5134         }
5135
5136 #ifdef CONFIG_MLX5_CORE_EN_DCB
5137         mlx5e_dcbnl_initialize(priv);
5138 #endif
5139         return 0;
5140 }
5141
5142 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5143 {
5144         struct net_device *netdev = priv->netdev;
5145         struct mlx5_core_dev *mdev = priv->mdev;
5146
5147         mlx5e_init_l2_addr(priv);
5148
5149         /* Marking the link as currently not needed by the Driver */
5150         if (!netif_running(netdev))
5151                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5152
5153         mlx5e_set_netdev_mtu_boundaries(priv);
5154         mlx5e_set_dev_port_mtu(priv);
5155
5156         mlx5_lag_add(mdev, netdev);
5157
5158         mlx5e_enable_async_events(priv);
5159         if (mlx5e_monitor_counter_supported(priv))
5160                 mlx5e_monitor_counter_init(priv);
5161
5162         mlx5e_hv_vhca_stats_create(priv);
5163         if (netdev->reg_state != NETREG_REGISTERED)
5164                 return;
5165 #ifdef CONFIG_MLX5_CORE_EN_DCB
5166         mlx5e_dcbnl_init_app(priv);
5167 #endif
5168
5169         queue_work(priv->wq, &priv->set_rx_mode_work);
5170
5171         rtnl_lock();
5172         if (netif_running(netdev))
5173                 mlx5e_open(netdev);
5174         netif_device_attach(netdev);
5175         rtnl_unlock();
5176 }
5177
5178 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5179 {
5180         struct mlx5_core_dev *mdev = priv->mdev;
5181
5182 #ifdef CONFIG_MLX5_CORE_EN_DCB
5183         if (priv->netdev->reg_state == NETREG_REGISTERED)
5184                 mlx5e_dcbnl_delete_app(priv);
5185 #endif
5186
5187         rtnl_lock();
5188         if (netif_running(priv->netdev))
5189                 mlx5e_close(priv->netdev);
5190         netif_device_detach(priv->netdev);
5191         rtnl_unlock();
5192
5193         queue_work(priv->wq, &priv->set_rx_mode_work);
5194
5195         mlx5e_hv_vhca_stats_destroy(priv);
5196         if (mlx5e_monitor_counter_supported(priv))
5197                 mlx5e_monitor_counter_cleanup(priv);
5198
5199         mlx5e_disable_async_events(priv);
5200         mlx5_lag_remove(mdev);
5201 }
5202
5203 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5204 {
5205         return mlx5e_refresh_tirs(priv, false);
5206 }
5207
5208 static const struct mlx5e_profile mlx5e_nic_profile = {
5209         .init              = mlx5e_nic_init,
5210         .cleanup           = mlx5e_nic_cleanup,
5211         .init_rx           = mlx5e_init_nic_rx,
5212         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5213         .init_tx           = mlx5e_init_nic_tx,
5214         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5215         .enable            = mlx5e_nic_enable,
5216         .disable           = mlx5e_nic_disable,
5217         .update_rx         = mlx5e_update_nic_rx,
5218         .update_stats      = mlx5e_update_ndo_stats,
5219         .update_carrier    = mlx5e_update_carrier,
5220         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5221         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5222         .max_tc            = MLX5E_MAX_NUM_TC,
5223         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5224 };
5225
5226 /* mlx5e generic netdev management API (move to en_common.c) */
5227
5228 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5229 int mlx5e_netdev_init(struct net_device *netdev,
5230                       struct mlx5e_priv *priv,
5231                       struct mlx5_core_dev *mdev,
5232                       const struct mlx5e_profile *profile,
5233                       void *ppriv)
5234 {
5235         /* priv init */
5236         priv->mdev        = mdev;
5237         priv->netdev      = netdev;
5238         priv->profile     = profile;
5239         priv->ppriv       = ppriv;
5240         priv->msglevel    = MLX5E_MSG_LEVEL;
5241         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5242         priv->max_opened_tc = 1;
5243
5244         mutex_init(&priv->state_lock);
5245         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5246         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5247         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5248         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5249
5250         priv->wq = create_singlethread_workqueue("mlx5e");
5251         if (!priv->wq)
5252                 return -ENOMEM;
5253
5254         /* netdev init */
5255         netif_carrier_off(netdev);
5256
5257 #ifdef CONFIG_MLX5_EN_ARFS
5258         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5259 #endif
5260
5261         return 0;
5262 }
5263
5264 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5265 {
5266         destroy_workqueue(priv->wq);
5267 }
5268
5269 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5270                                        const struct mlx5e_profile *profile,
5271                                        int nch,
5272                                        void *ppriv)
5273 {
5274         struct net_device *netdev;
5275         int err;
5276
5277         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5278                                     nch * profile->max_tc,
5279                                     nch * profile->rq_groups);
5280         if (!netdev) {
5281                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5282                 return NULL;
5283         }
5284
5285         err = profile->init(mdev, netdev, profile, ppriv);
5286         if (err) {
5287                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5288                 goto err_free_netdev;
5289         }
5290
5291         return netdev;
5292
5293 err_free_netdev:
5294         free_netdev(netdev);
5295
5296         return NULL;
5297 }
5298
5299 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5300 {
5301         const struct mlx5e_profile *profile;
5302         int max_nch;
5303         int err;
5304
5305         profile = priv->profile;
5306         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5307
5308         /* max number of channels may have changed */
5309         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5310         if (priv->channels.params.num_channels > max_nch) {
5311                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5312                 priv->channels.params.num_channels = max_nch;
5313                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5314                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5315         }
5316
5317         err = profile->init_tx(priv);
5318         if (err)
5319                 goto out;
5320
5321         err = profile->init_rx(priv);
5322         if (err)
5323                 goto err_cleanup_tx;
5324
5325         if (profile->enable)
5326                 profile->enable(priv);
5327
5328         return 0;
5329
5330 err_cleanup_tx:
5331         profile->cleanup_tx(priv);
5332
5333 out:
5334         return err;
5335 }
5336
5337 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5338 {
5339         const struct mlx5e_profile *profile = priv->profile;
5340
5341         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5342
5343         if (profile->disable)
5344                 profile->disable(priv);
5345         flush_workqueue(priv->wq);
5346
5347         profile->cleanup_rx(priv);
5348         profile->cleanup_tx(priv);
5349         cancel_work_sync(&priv->update_stats_work);
5350 }
5351
5352 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5353 {
5354         const struct mlx5e_profile *profile = priv->profile;
5355         struct net_device *netdev = priv->netdev;
5356
5357         if (profile->cleanup)
5358                 profile->cleanup(priv);
5359         free_netdev(netdev);
5360 }
5361
5362 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5363  * hardware contexts and to connect it to the current netdev.
5364  */
5365 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5366 {
5367         struct mlx5e_priv *priv = vpriv;
5368         struct net_device *netdev = priv->netdev;
5369         int err;
5370
5371         if (netif_device_present(netdev))
5372                 return 0;
5373
5374         err = mlx5e_create_mdev_resources(mdev);
5375         if (err)
5376                 return err;
5377
5378         err = mlx5e_attach_netdev(priv);
5379         if (err) {
5380                 mlx5e_destroy_mdev_resources(mdev);
5381                 return err;
5382         }
5383
5384         return 0;
5385 }
5386
5387 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5388 {
5389         struct mlx5e_priv *priv = vpriv;
5390         struct net_device *netdev = priv->netdev;
5391
5392 #ifdef CONFIG_MLX5_ESWITCH
5393         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5394                 return;
5395 #endif
5396
5397         if (!netif_device_present(netdev))
5398                 return;
5399
5400         mlx5e_detach_netdev(priv);
5401         mlx5e_destroy_mdev_resources(mdev);
5402 }
5403
5404 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5405 {
5406         struct net_device *netdev;
5407         void *priv;
5408         int err;
5409         int nch;
5410
5411         err = mlx5e_check_required_hca_cap(mdev);
5412         if (err)
5413                 return NULL;
5414
5415 #ifdef CONFIG_MLX5_ESWITCH
5416         if (MLX5_ESWITCH_MANAGER(mdev) &&
5417             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5418                 mlx5e_rep_register_vport_reps(mdev);
5419                 return mdev;
5420         }
5421 #endif
5422
5423         nch = mlx5e_get_max_num_channels(mdev);
5424         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5425         if (!netdev) {
5426                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5427                 return NULL;
5428         }
5429
5430         priv = netdev_priv(netdev);
5431
5432         err = mlx5e_attach(mdev, priv);
5433         if (err) {
5434                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5435                 goto err_destroy_netdev;
5436         }
5437
5438         err = register_netdev(netdev);
5439         if (err) {
5440                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5441                 goto err_detach;
5442         }
5443
5444 #ifdef CONFIG_MLX5_CORE_EN_DCB
5445         mlx5e_dcbnl_init_app(priv);
5446 #endif
5447         return priv;
5448
5449 err_detach:
5450         mlx5e_detach(mdev, priv);
5451 err_destroy_netdev:
5452         mlx5e_destroy_netdev(priv);
5453         return NULL;
5454 }
5455
5456 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5457 {
5458         struct mlx5e_priv *priv;
5459
5460 #ifdef CONFIG_MLX5_ESWITCH
5461         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5462                 mlx5e_rep_unregister_vport_reps(mdev);
5463                 return;
5464         }
5465 #endif
5466         priv = vpriv;
5467 #ifdef CONFIG_MLX5_CORE_EN_DCB
5468         mlx5e_dcbnl_delete_app(priv);
5469 #endif
5470         unregister_netdev(priv->netdev);
5471         mlx5e_detach(mdev, vpriv);
5472         mlx5e_destroy_netdev(priv);
5473 }
5474
5475 static struct mlx5_interface mlx5e_interface = {
5476         .add       = mlx5e_add,
5477         .remove    = mlx5e_remove,
5478         .attach    = mlx5e_attach,
5479         .detach    = mlx5e_detach,
5480         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5481 };
5482
5483 void mlx5e_init(void)
5484 {
5485         mlx5e_ipsec_build_inverse_table();
5486         mlx5e_build_ptys2ethtool_map();
5487         mlx5_register_interface(&mlx5e_interface);
5488 }
5489
5490 void mlx5e_cleanup(void)
5491 {
5492         mlx5_unregister_interface(&mlx5e_interface);
5493 }