drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include <net/ip6_checksum.h>
  40 #include <net/page_pool.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "lib/clock.h"
  48
  49 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  50 {
  51         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  52 }
  53
  54 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  55                                        void *data)
  56 {
  57         u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc);
  58
  59         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  60 }
  61
  62 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  63                                          struct mlx5e_cq *cq, u32 cqcc)
  64 {
  65         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  66         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  67         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  68         rq->stats->cqe_compress_blks++;
  69 }
  70
  71 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  72 {
  73         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  74         cq->mini_arr_idx = 0;
  75 }
  76
  77 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  78 {
  79         struct mlx5_cqwq *wq = &cq->wq;
  80
  81         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  82         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  83         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  84         u32 ci_top = min_t(u32, wq_sz, ci + n);
  85
  86         for (; ci < ci_top; ci++, n--) {
  87                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  88
  89                 cqe->op_own = op_own;
  90         }
  91
  92         if (unlikely(ci == wq_sz)) {
  93                 op_own = !op_own;
  94                 for (ci = 0; ci < n; ci++) {
  95                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  96
  97                         cqe->op_own = op_own;
  98                 }
  99         }
 100 }
 101
 102 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 103                                         struct mlx5e_cq *cq, u32 cqcc)
 104 {
 105         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 106         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 107         cq->title.op_own      &= 0xf0;
 108         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 109         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 110
 111         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 112                 cq->decmprs_wqe_counter +=
 113                         mpwrq_get_cqe_consumed_strides(&cq->title);
 114         else
 115                 cq->decmprs_wqe_counter =
 116                         mlx5_wq_ll_ctr2ix(&rq->wq, cq->decmprs_wqe_counter + 1);
 117 }
 118
 119 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 120                                                 struct mlx5e_cq *cq, u32 cqcc)
 121 {
 122         mlx5e_decompress_cqe(rq, cq, cqcc);
 123         cq->title.rss_hash_type   = 0;
 124         cq->title.rss_hash_result = 0;
 125 }
 126
 127 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 128                                              struct mlx5e_cq *cq,
 129                                              int update_owner_only,
 130                                              int budget_rem)
 131 {
 132         u32 cqcc = cq->wq.cc + update_owner_only;
 133         u32 cqe_count;
 134         u32 i;
 135
 136         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 137
 138         for (i = update_owner_only; i < cqe_count;
 139              i++, cq->mini_arr_idx++, cqcc++) {
 140                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 141                         mlx5e_read_mini_arr_slot(cq, cqcc);
 142
 143                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 144                 rq->handle_rx_cqe(rq, &cq->title);
 145         }
 146         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 147         cq->wq.cc = cqcc;
 148         cq->decmprs_left -= cqe_count;
 149         rq->stats->cqe_compress_pkts += cqe_count;
 150
 151         return cqe_count;
 152 }
 153
 154 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 155                                               struct mlx5e_cq *cq,
 156                                               int budget_rem)
 157 {
 158         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 159         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 160         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 161         rq->handle_rx_cqe(rq, &cq->title);
 162         cq->mini_arr_idx++;
 163
 164         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 165 }
 166
 167 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 168
 169 static inline bool mlx5e_page_is_reserved(struct page *page)
 170 {
 171         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 172 }
 173
 174 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 175                                       struct mlx5e_dma_info *dma_info)
 176 {
 177         struct mlx5e_page_cache *cache = &rq->page_cache;
 178         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 179         struct mlx5e_rq_stats *stats = rq->stats;
 180
 181         if (tail_next == cache->head) {
 182                 stats->cache_full++;
 183                 return false;
 184         }
 185
 186         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 187                 stats->cache_waive++;
 188                 return false;
 189         }
 190
 191         cache->page_cache[cache->tail] = *dma_info;
 192         cache->tail = tail_next;
 193         return true;
 194 }
 195
 196 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 197                                       struct mlx5e_dma_info *dma_info)
 198 {
 199         struct mlx5e_page_cache *cache = &rq->page_cache;
 200         struct mlx5e_rq_stats *stats = rq->stats;
 201
 202         if (unlikely(cache->head == cache->tail)) {
 203                 stats->cache_empty++;
 204                 return false;
 205         }
 206
 207         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 208                 stats->cache_busy++;
 209                 return false;
 210         }
 211
 212         *dma_info = cache->page_cache[cache->head];
 213         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 214         stats->cache_reuse++;
 215
 216         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 217                                    RQ_PAGE_SIZE(rq),
 218                                    DMA_FROM_DEVICE);
 219         return true;
 220 }
 221
 222 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 223                                           struct mlx5e_dma_info *dma_info)
 224 {
 225         if (mlx5e_rx_cache_get(rq, dma_info))
 226                 return 0;
 227
 228         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 229         if (unlikely(!dma_info->page))
 230                 return -ENOMEM;
 231
 232         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 233                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 234         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 235                 put_page(dma_info->page);
 236                 dma_info->page = NULL;
 237                 return -ENOMEM;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq,
 244                                         struct mlx5e_dma_info *dma_info)
 245 {
 246         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 247                        rq->buff.map_dir);
 248 }
 249
 250 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 251                         bool recycle)
 252 {
 253         if (likely(recycle)) {
 254                 if (mlx5e_rx_cache_put(rq, dma_info))
 255                         return;
 256
 257                 mlx5e_page_dma_unmap(rq, dma_info);
 258                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 259         } else {
 260                 mlx5e_page_dma_unmap(rq, dma_info);
 261                 put_page(dma_info->page);
 262         }
 263 }
 264
 265 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
 266                                     struct mlx5e_wqe_frag_info *wi)
 267 {
 268         return rq->wqe.page_reuse && wi->di.page &&
 269                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
 270                 !mlx5e_page_is_reserved(wi->di.page);
 271 }
 272
 273 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 274 {
 275         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 276
 277         /* check if page exists, hence can be reused */
 278         if (!wi->di.page) {
 279                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
 280                         return -ENOMEM;
 281                 wi->offset = 0;
 282         }
 283
 284         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
 285         return 0;
 286 }
 287
 288 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 289                                      struct mlx5e_wqe_frag_info *wi)
 290 {
 291         mlx5e_page_release(rq, &wi->di, true);
 292         wi->di.page = NULL;
 293 }
 294
 295 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
 296                                            struct mlx5e_wqe_frag_info *wi)
 297 {
 298         if (mlx5e_page_reuse(rq, wi)) {
 299                 rq->stats->page_reuse++;
 300                 return;
 301         }
 302
 303         mlx5e_free_rx_wqe(rq, wi);
 304 }
 305
 306 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 307 {
 308         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 309
 310         if (wi->di.page)
 311                 mlx5e_free_rx_wqe(rq, wi);
 312 }
 313
 314 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 315                                             struct sk_buff *skb,
 316                                             struct mlx5e_dma_info *di,
 317                                             u32 frag_offset, u32 len)
 318 {
 319         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
 320
 321         dma_sync_single_for_cpu(rq->pdev,
 322                                 di->addr + frag_offset,
 323                                 len, DMA_FROM_DEVICE);
 324         page_ref_inc(di->page);
 325         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 326                         di->page, frag_offset, len, truesize);
 327 }
 328
 329 static inline void
 330 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 331                             struct sk_buff *skb,
 332                             struct mlx5e_dma_info *dma_info,
 333                             u32 offset, u32 headlen)
 334 {
 335         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 336         unsigned int len;
 337
 338          /* Aligning len to sizeof(long) optimizes memcpy performance */
 339         len = ALIGN(headlen_pg, sizeof(long));
 340         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 341                                 DMA_FROM_DEVICE);
 342         skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len);
 343
 344         if (unlikely(offset + headlen > PAGE_SIZE)) {
 345                 dma_info++;
 346                 headlen_pg = len;
 347                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 348                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 349                                         DMA_FROM_DEVICE);
 350                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 351                                                page_address(dma_info->page),
 352                                                len);
 353         }
 354 }
 355
 356 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 357 {
 358         const bool no_xdp_xmit =
 359                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 360         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 361         int i;
 362
 363         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 364                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 365                         mlx5e_page_release(rq, &dma_info[i], true);
 366 }
 367
 368 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 369 {
 370         struct mlx5_wq_ll *wq = &rq->wq;
 371         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 372
 373         rq->mpwqe.umr_in_progress = false;
 374
 375         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 376
 377         /* ensure wqes are visible to device before updating doorbell record */
 378         dma_wmb();
 379
 380         mlx5_wq_ll_update_db_record(wq);
 381 }
 382
 383 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
 384 {
 385         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
 386 }
 387
 388 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 389                                               struct mlx5_wq_cyc *wq,
 390                                               u16 pi, u16 frag_pi)
 391 {
 392         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 393         u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi;
 394
 395         edge_wi = wi + nnops;
 396
 397         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 398         for (; wi < edge_wi; wi++) {
 399                 wi->opcode = MLX5_OPCODE_NOP;
 400                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 401         }
 402 }
 403
 404 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 405 {
 406         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 407         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 408         struct mlx5e_icosq *sq = &rq->channel->icosq;
 409         struct mlx5_wq_cyc *wq = &sq->wq;
 410         struct mlx5e_umr_wqe *umr_wqe;
 411         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 412         u16 pi, frag_pi;
 413         int err;
 414         int i;
 415
 416         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 417         frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc);
 418
 419         if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) {
 420                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi);
 421                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 422         }
 423
 424         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 425         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
 426                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
 427                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
 428
 429         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 430                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 431                 if (unlikely(err))
 432                         goto err_unmap;
 433                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 434         }
 435
 436         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 437         wi->consumed_strides = 0;
 438
 439         rq->mpwqe.umr_in_progress = true;
 440
 441         umr_wqe->ctrl.opmod_idx_opcode =
 442                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 443                             MLX5_OPCODE_UMR);
 444         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 445
 446         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 447         sq->pc += MLX5E_UMR_WQEBBS;
 448         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
 449
 450         return 0;
 451
 452 err_unmap:
 453         while (--i >= 0) {
 454                 dma_info--;
 455                 mlx5e_page_release(rq, dma_info, true);
 456         }
 457         rq->stats->buff_alloc_err++;
 458
 459         return err;
 460 }
 461
 462 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 463 {
 464         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 465
 466         mlx5e_free_rx_mpwqe(rq, wi);
 467 }
 468
 469 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 470 {
 471         struct mlx5_wq_ll *wq = &rq->wq;
 472         int err;
 473
 474         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 475                 return false;
 476
 477         if (mlx5_wq_ll_is_full(wq))
 478                 return false;
 479
 480         do {
 481                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 482
 483                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
 484                 if (unlikely(err)) {
 485                         rq->stats->buff_alloc_err++;
 486                         break;
 487                 }
 488
 489                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 490         } while (!mlx5_wq_ll_is_full(wq));
 491
 492         /* ensure wqes are visible to device before updating doorbell record */
 493         dma_wmb();
 494
 495         mlx5_wq_ll_update_db_record(wq);
 496
 497         return !!err;
 498 }
 499
 500 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 501                                              struct mlx5e_icosq *sq,
 502                                              struct mlx5e_rq *rq,
 503                                              struct mlx5_cqe64 *cqe)
 504 {
 505         struct mlx5_wq_cyc *wq = &sq->wq;
 506         u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
 507         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 508
 509         mlx5_cqwq_pop(&cq->wq);
 510
 511         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 512                 netdev_WARN_ONCE(cq->channel->netdev,
 513                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 514                 return;
 515         }
 516
 517         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 518                 mlx5e_post_rx_mpwqe(rq);
 519                 return;
 520         }
 521
 522         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 523                 netdev_WARN_ONCE(cq->channel->netdev,
 524                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 525 }
 526
 527 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 528 {
 529         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 530         struct mlx5_cqe64 *cqe;
 531
 532         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 533                 return;
 534
 535         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 536         if (likely(!cqe))
 537                 return;
 538
 539         /* by design, there's only a single cqe */
 540         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 541
 542         mlx5_cqwq_update_db_record(&cq->wq);
 543 }
 544
 545 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 546 {
 547         struct mlx5_wq_ll *wq = &rq->wq;
 548
 549         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 550                 return false;
 551
 552         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 553
 554         if (mlx5_wq_ll_is_full(wq))
 555                 return false;
 556
 557         if (!rq->mpwqe.umr_in_progress)
 558                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 559
 560         return false;
 561 }
 562
 563 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 564 {
 565         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 566         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 567                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 568
 569         tcp->check                      = 0;
 570         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 571
 572         if (tcp_ack) {
 573                 tcp->ack                = 1;
 574                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 575                 tcp->window             = cqe->lro_tcp_win;
 576         }
 577 }
 578
 579 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 580                                  u32 cqe_bcnt)
 581 {
 582         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 583         struct tcphdr   *tcp;
 584         int network_depth = 0;
 585         __wsum check;
 586         __be16 proto;
 587         u16 tot_len;
 588         void *ip_p;
 589
 590         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 591
 592         tot_len = cqe_bcnt - network_depth;
 593         ip_p = skb->data + network_depth;
 594
 595         if (proto == htons(ETH_P_IP)) {
 596                 struct iphdr *ipv4 = ip_p;
 597
 598                 tcp = ip_p + sizeof(struct iphdr);
 599                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 600
 601                 ipv4->ttl               = cqe->lro_min_ttl;
 602                 ipv4->tot_len           = cpu_to_be16(tot_len);
 603                 ipv4->check             = 0;
 604                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 605                                                        ipv4->ihl);
 606
 607                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 608                 check = csum_partial(tcp, tcp->doff * 4,
 609                                      csum_unfold((__force __sum16)cqe->check_sum));
 610                 /* Almost done, don't forget the pseudo header */
 611                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 612                                                tot_len - sizeof(struct iphdr),
 613                                                IPPROTO_TCP, check);
 614         } else {
 615                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 616                 struct ipv6hdr *ipv6 = ip_p;
 617
 618                 tcp = ip_p + sizeof(struct ipv6hdr);
 619                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 620
 621                 ipv6->hop_limit         = cqe->lro_min_ttl;
 622                 ipv6->payload_len       = cpu_to_be16(payload_len);
 623
 624                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 625                 check = csum_partial(tcp, tcp->doff * 4,
 626                                      csum_unfold((__force __sum16)cqe->check_sum));
 627                 /* Almost done, don't forget the pseudo header */
 628                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 629                                              IPPROTO_TCP, check);
 630         }
 631 }
 632
 633 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 634                                       struct sk_buff *skb)
 635 {
 636         u8 cht = cqe->rss_hash_type;
 637         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 638                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 639                                             PKT_HASH_TYPE_NONE;
 640         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 641 }
 642
 643 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
 644 {
 645         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 646
 647         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
 648         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 649 }
 650
 651 static __be32 mlx5e_get_fcs(struct sk_buff *skb)
 652 {
 653         int last_frag_sz, bytes_in_prev, nr_frags;
 654         u8 *fcs_p1, *fcs_p2;
 655         skb_frag_t *last_frag;
 656         __be32 fcs_bytes;
 657
 658         if (!skb_is_nonlinear(skb))
 659                 return *(__be32 *)(skb->data + skb->len - ETH_FCS_LEN);
 660
 661         nr_frags = skb_shinfo(skb)->nr_frags;
 662         last_frag = &skb_shinfo(skb)->frags[nr_frags - 1];
 663         last_frag_sz = skb_frag_size(last_frag);
 664
 665         /* If all FCS data is in last frag */
 666         if (last_frag_sz >= ETH_FCS_LEN)
 667                 return *(__be32 *)(skb_frag_address(last_frag) +
 668                                    last_frag_sz - ETH_FCS_LEN);
 669
 670         fcs_p2 = (u8 *)skb_frag_address(last_frag);
 671         bytes_in_prev = ETH_FCS_LEN - last_frag_sz;
 672
 673         /* Find where the other part of the FCS is - Linear or another frag */
 674         if (nr_frags == 1) {
 675                 fcs_p1 = skb_tail_pointer(skb);
 676         } else {
 677                 skb_frag_t *prev_frag = &skb_shinfo(skb)->frags[nr_frags - 2];
 678
 679                 fcs_p1 = skb_frag_address(prev_frag) +
 680                             skb_frag_size(prev_frag);
 681         }
 682         fcs_p1 -= bytes_in_prev;
 683
 684         memcpy(&fcs_bytes, fcs_p1, bytes_in_prev);
 685         memcpy(((u8 *)&fcs_bytes) + bytes_in_prev, fcs_p2, last_frag_sz);
 686
 687         return fcs_bytes;
 688 }
 689
 690 static inline void mlx5e_handle_csum(struct net_device *netdev,
 691                                      struct mlx5_cqe64 *cqe,
 692                                      struct mlx5e_rq *rq,
 693                                      struct sk_buff *skb,
 694                                      bool   lro)
 695 {
 696         struct mlx5e_rq_stats *stats = rq->stats;
 697         int network_depth = 0;
 698
 699         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 700                 goto csum_none;
 701
 702         if (lro) {
 703                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 704                 stats->csum_unnecessary++;
 705                 return;
 706         }
 707
 708         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
 709                 skb->ip_summed = CHECKSUM_COMPLETE;
 710                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 711                 if (network_depth > ETH_HLEN)
 712                         /* CQE csum is calculated from the IP header and does
 713                          * not cover VLAN headers (if present). This will add
 714                          * the checksum manually.
 715                          */
 716                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 717                                                  network_depth - ETH_HLEN,
 718                                                  skb->csum);
 719                 if (unlikely(netdev->features & NETIF_F_RXFCS))
 720                         skb->csum = csum_add(skb->csum,
 721                                              (__force __wsum)mlx5e_get_fcs(skb));
 722                 stats->csum_complete++;
 723                 return;
 724         }
 725
 726         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 727                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 728                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 729                 if (cqe_is_tunneled(cqe)) {
 730                         skb->csum_level = 1;
 731                         skb->encapsulation = 1;
 732                         stats->csum_unnecessary_inner++;
 733                         return;
 734                 }
 735                 stats->csum_unnecessary++;
 736                 return;
 737         }
 738 csum_none:
 739         skb->ip_summed = CHECKSUM_NONE;
 740         stats->csum_none++;
 741 }
 742
 743 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 744                                       u32 cqe_bcnt,
 745                                       struct mlx5e_rq *rq,
 746                                       struct sk_buff *skb)
 747 {
 748         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 749         struct mlx5e_rq_stats *stats = rq->stats;
 750         struct net_device *netdev = rq->netdev;
 751
 752         skb->mac_len = ETH_HLEN;
 753         if (lro_num_seg > 1) {
 754                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 755                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 756                 /* Subtract one since we already counted this as one
 757                  * "regular" packet in mlx5e_complete_rx_cqe()
 758                  */
 759                 stats->packets += lro_num_seg - 1;
 760                 stats->lro_packets++;
 761                 stats->lro_bytes += cqe_bcnt;
 762         }
 763
 764         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 765                 skb_hwtstamps(skb)->hwtstamp =
 766                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 767
 768         skb_record_rx_queue(skb, rq->ix);
 769
 770         if (likely(netdev->features & NETIF_F_RXHASH))
 771                 mlx5e_skb_set_hash(cqe, skb);
 772
 773         if (cqe_has_vlan(cqe)) {
 774                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 775                                        be16_to_cpu(cqe->vlan_info));
 776                 stats->removed_vlan_packets++;
 777         }
 778
 779         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 780
 781         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 782         skb->protocol = eth_type_trans(skb, netdev);
 783 }
 784
 785 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 786                                          struct mlx5_cqe64 *cqe,
 787                                          u32 cqe_bcnt,
 788                                          struct sk_buff *skb)
 789 {
 790         struct mlx5e_rq_stats *stats = rq->stats;
 791
 792         stats->packets++;
 793         stats->bytes += cqe_bcnt;
 794         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 795 }
 796
 797 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 798 {
 799         struct mlx5_wq_cyc *wq = &sq->wq;
 800         struct mlx5e_tx_wqe *wqe;
 801         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc - 1); /* last pi */
 802
 803         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 804
 805         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 806 }
 807
 808 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 809                                         struct mlx5e_dma_info *di,
 810                                         const struct xdp_buff *xdp)
 811 {
 812         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 813         struct mlx5_wq_cyc       *wq   = &sq->wq;
 814         u16                       pi   = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 815         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 816
 817         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 818         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 819         struct mlx5_wqe_data_seg *dseg;
 820
 821         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 822         dma_addr_t dma_addr  = di->addr + data_offset;
 823         unsigned int dma_len = xdp->data_end - xdp->data;
 824
 825         struct mlx5e_rq_stats *stats = rq->stats;
 826
 827         prefetchw(wqe);
 828
 829         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
 830                 stats->xdp_drop++;
 831                 return false;
 832         }
 833
 834         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 835                 if (sq->db.doorbell) {
 836                         /* SQ is full, ring doorbell */
 837                         mlx5e_xmit_xdp_doorbell(sq);
 838                         sq->db.doorbell = false;
 839                 }
 840                 stats->xdp_tx_full++;
 841                 return false;
 842         }
 843
 844         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 845
 846         cseg->fm_ce_se = 0;
 847
 848         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 849
 850         /* copy the inline part if required */
 851         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 852                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 853                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 854                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 855                 dma_addr += MLX5E_XDP_MIN_INLINE;
 856                 dseg++;
 857         }
 858
 859         /* write the dma part */
 860         dseg->addr       = cpu_to_be64(dma_addr);
 861         dseg->byte_count = cpu_to_be32(dma_len);
 862
 863         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 864
 865         /* move page to reference to sq responsibility,
 866          * and mark so it's not put back in page-cache.
 867          */
 868         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
 869         sq->db.di[pi] = *di;
 870         sq->pc++;
 871
 872         sq->db.doorbell = true;
 873
 874         stats->xdp_tx++;
 875         return true;
 876 }
 877
 878 /* returns true if packet was consumed by xdp */
 879 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
 880                                     struct mlx5e_dma_info *di,
 881                                     void *va, u16 *rx_headroom, u32 *len)
 882 {
 883         struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 884         struct xdp_buff xdp;
 885         u32 act;
 886         int err;
 887
 888         if (!prog)
 889                 return false;
 890
 891         xdp.data = va + *rx_headroom;
 892         xdp_set_data_meta_invalid(&xdp);
 893         xdp.data_end = xdp.data + *len;
 894         xdp.data_hard_start = va;
 895         xdp.rxq = &rq->xdp_rxq;
 896
 897         act = bpf_prog_run_xdp(prog, &xdp);
 898         switch (act) {
 899         case XDP_PASS:
 900                 *rx_headroom = xdp.data - xdp.data_hard_start;
 901                 *len = xdp.data_end - xdp.data;
 902                 return false;
 903         case XDP_TX:
 904                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 905                         trace_xdp_exception(rq->netdev, prog, act);
 906                 return true;
 907         case XDP_REDIRECT:
 908                 /* When XDP enabled then page-refcnt==1 here */
 909                 err = xdp_do_redirect(rq->netdev, &xdp, prog);
 910                 if (!err) {
 911                         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
 912                         rq->xdpsq.db.redirect_flush = true;
 913                         mlx5e_page_dma_unmap(rq, di);
 914                 }
 915                 return true;
 916         default:
 917                 bpf_warn_invalid_xdp_action(act);
 918         case XDP_ABORTED:
 919                 trace_xdp_exception(rq->netdev, prog, act);
 920         case XDP_DROP:
 921                 rq->stats->xdp_drop++;
 922                 return true;
 923         }
 924 }
 925
 926 static inline
 927 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 928                                        u32 frag_size, u16 headroom,
 929                                        u32 cqe_bcnt)
 930 {
 931         struct sk_buff *skb = build_skb(va, frag_size);
 932
 933         if (unlikely(!skb)) {
 934                 rq->stats->buff_alloc_err++;
 935                 return NULL;
 936         }
 937
 938         skb_reserve(skb, headroom);
 939         skb_put(skb, cqe_bcnt);
 940
 941         return skb;
 942 }
 943
 944 static inline
 945 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 946                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 947 {
 948         struct mlx5e_dma_info *di = &wi->di;
 949         u16 rx_headroom = rq->buff.headroom;
 950         struct sk_buff *skb;
 951         void *va, *data;
 952         bool consumed;
 953         u32 frag_size;
 954
 955         va             = page_address(di->page) + wi->offset;
 956         data           = va + rx_headroom;
 957         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 958
 959         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
 960                                       frag_size, DMA_FROM_DEVICE);
 961         prefetchw(va); /* xdp_frame data area */
 962         prefetch(data);
 963         wi->offset += frag_size;
 964
 965         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 966                 rq->stats->wqe_err++;
 967                 return NULL;
 968         }
 969
 970         rcu_read_lock();
 971         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 972         rcu_read_unlock();
 973         if (consumed)
 974                 return NULL; /* page/packet was consumed by XDP */
 975
 976         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
 977         if (unlikely(!skb))
 978                 return NULL;
 979
 980         /* queue up for recycling/reuse */
 981         page_ref_inc(di->page);
 982
 983         return skb;
 984 }
 985
 986 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 987 {
 988         struct mlx5e_wqe_frag_info *wi;
 989         struct mlx5e_rx_wqe *wqe;
 990         __be16 wqe_counter_be;
 991         struct sk_buff *skb;
 992         u16 wqe_counter;
 993         u32 cqe_bcnt;
 994
 995         wqe_counter_be = cqe->wqe_counter;
 996         wqe_counter    = be16_to_cpu(wqe_counter_be);
 997         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 998         wi             = &rq->wqe.frag_info[wqe_counter];
 999         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1000
1001         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1002         if (!skb) {
1003                 /* probably for XDP */
1004                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1005                         wi->di.page = NULL;
1006                         /* do not return page to cache, it will be returned on XDP_TX completion */
1007                         goto wq_ll_pop;
1008                 }
1009                 /* probably an XDP_DROP, save the page-reuse checks */
1010                 mlx5e_free_rx_wqe(rq, wi);
1011                 goto wq_ll_pop;
1012         }
1013
1014         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1015         napi_gro_receive(rq->cq.napi, skb);
1016
1017         mlx5e_free_rx_wqe_reuse(rq, wi);
1018 wq_ll_pop:
1019         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1020                        &wqe->next.next_wqe_index);
1021 }
1022
1023 #ifdef CONFIG_MLX5_ESWITCH
1024 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1025 {
1026         struct net_device *netdev = rq->netdev;
1027         struct mlx5e_priv *priv = netdev_priv(netdev);
1028         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1029         struct mlx5_eswitch_rep *rep = rpriv->rep;
1030         struct mlx5e_wqe_frag_info *wi;
1031         struct mlx5e_rx_wqe *wqe;
1032         struct sk_buff *skb;
1033         __be16 wqe_counter_be;
1034         u16 wqe_counter;
1035         u32 cqe_bcnt;
1036
1037         wqe_counter_be = cqe->wqe_counter;
1038         wqe_counter    = be16_to_cpu(wqe_counter_be);
1039         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1040         wi             = &rq->wqe.frag_info[wqe_counter];
1041         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1042
1043         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1044         if (!skb) {
1045                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1046                         wi->di.page = NULL;
1047                         /* do not return page to cache, it will be returned on XDP_TX completion */
1048                         goto wq_ll_pop;
1049                 }
1050                 /* probably an XDP_DROP, save the page-reuse checks */
1051                 mlx5e_free_rx_wqe(rq, wi);
1052                 goto wq_ll_pop;
1053         }
1054
1055         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1056
1057         if (rep->vlan && skb_vlan_tag_present(skb))
1058                 skb_vlan_pop(skb);
1059
1060         napi_gro_receive(rq->cq.napi, skb);
1061
1062         mlx5e_free_rx_wqe_reuse(rq, wi);
1063 wq_ll_pop:
1064         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1065                        &wqe->next.next_wqe_index);
1066 }
1067 #endif
1068
1069 struct sk_buff *
1070 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1071                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1072 {
1073         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1074         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1075         u32 frag_offset    = head_offset + headlen;
1076         u32 byte_cnt       = cqe_bcnt - headlen;
1077         struct mlx5e_dma_info *head_di = di;
1078         struct sk_buff *skb;
1079
1080         skb = napi_alloc_skb(rq->cq.napi,
1081                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1082         if (unlikely(!skb)) {
1083                 rq->stats->buff_alloc_err++;
1084                 return NULL;
1085         }
1086
1087         prefetchw(skb->data);
1088
1089         if (unlikely(frag_offset >= PAGE_SIZE)) {
1090                 di++;
1091                 frag_offset -= PAGE_SIZE;
1092         }
1093
1094         while (byte_cnt) {
1095                 u32 pg_consumed_bytes =
1096                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1097
1098                 mlx5e_add_skb_frag_mpwqe(rq, skb, di, frag_offset,
1099                                          pg_consumed_bytes);
1100                 byte_cnt -= pg_consumed_bytes;
1101                 frag_offset = 0;
1102                 di++;
1103         }
1104         /* copy header */
1105         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1106                                     head_offset, headlen);
1107         /* skb linear part was allocated with headlen and aligned to long */
1108         skb->tail += headlen;
1109         skb->len  += headlen;
1110
1111         return skb;
1112 }
1113
1114 struct sk_buff *
1115 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1116                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1117 {
1118         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1119         u16 rx_headroom = rq->buff.headroom;
1120         u32 cqe_bcnt32 = cqe_bcnt;
1121         struct sk_buff *skb;
1122         void *va, *data;
1123         u32 frag_size;
1124         bool consumed;
1125
1126         va             = page_address(di->page) + head_offset;
1127         data           = va + rx_headroom;
1128         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1129
1130         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1131                                       frag_size, DMA_FROM_DEVICE);
1132         prefetch(data);
1133
1134         rcu_read_lock();
1135         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1136         rcu_read_unlock();
1137         if (consumed) {
1138                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1139                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1140                 return NULL; /* page/packet was consumed by XDP */
1141         }
1142
1143         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1144         if (unlikely(!skb))
1145                 return NULL;
1146
1147         /* queue up for recycling/reuse */
1148         page_ref_inc(di->page);
1149
1150         return skb;
1151 }
1152
1153 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1154 {
1155         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1156         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1157         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1158         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1159         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1160         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1161         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1162         struct mlx5e_rx_wqe *wqe;
1163         struct sk_buff *skb;
1164         u16 cqe_bcnt;
1165
1166         wi->consumed_strides += cstrides;
1167
1168         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1169                 rq->stats->wqe_err++;
1170                 goto mpwrq_cqe_out;
1171         }
1172
1173         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1174                 rq->stats->mpwqe_filler++;
1175                 goto mpwrq_cqe_out;
1176         }
1177
1178         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1179
1180         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1181                                            page_idx);
1182         if (!skb)
1183                 goto mpwrq_cqe_out;
1184
1185         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1186         napi_gro_receive(rq->cq.napi, skb);
1187
1188 mpwrq_cqe_out:
1189         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1190                 return;
1191
1192         wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1193         mlx5e_free_rx_mpwqe(rq, wi);
1194         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1195 }
1196
1197 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1198 {
1199         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1200         struct mlx5e_xdpsq *xdpsq;
1201         struct mlx5_cqe64 *cqe;
1202         int work_done = 0;
1203
1204         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1205                 return 0;
1206
1207         if (cq->decmprs_left)
1208                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1209
1210         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1211         if (!cqe)
1212                 return 0;
1213
1214         xdpsq = &rq->xdpsq;
1215
1216         do {
1217                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1218                         work_done +=
1219                                 mlx5e_decompress_cqes_start(rq, cq,
1220                                                             budget - work_done);
1221                         continue;
1222                 }
1223
1224                 mlx5_cqwq_pop(&cq->wq);
1225
1226                 rq->handle_rx_cqe(rq, cqe);
1227         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1228
1229         if (xdpsq->db.doorbell) {
1230                 mlx5e_xmit_xdp_doorbell(xdpsq);
1231                 xdpsq->db.doorbell = false;
1232         }
1233
1234         if (xdpsq->db.redirect_flush) {
1235                 xdp_do_flush_map();
1236                 xdpsq->db.redirect_flush = false;
1237         }
1238
1239         mlx5_cqwq_update_db_record(&cq->wq);
1240
1241         /* ensure cq space is freed before enabling more cqes */
1242         wmb();
1243
1244         return work_done;
1245 }
1246
1247 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1248 {
1249         struct mlx5e_xdpsq *sq;
1250         struct mlx5_cqe64 *cqe;
1251         struct mlx5e_rq *rq;
1252         u16 sqcc;
1253         int i;
1254
1255         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1256
1257         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
1258                 return false;
1259
1260         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1261         if (!cqe)
1262                 return false;
1263
1264         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1265
1266         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1267          * otherwise a cq overrun may occur
1268          */
1269         sqcc = sq->cc;
1270
1271         i = 0;
1272         do {
1273                 u16 wqe_counter;
1274                 bool last_wqe;
1275
1276                 mlx5_cqwq_pop(&cq->wq);
1277
1278                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1279
1280                 do {
1281                         struct mlx5e_dma_info *di;
1282                         u16 ci;
1283
1284                         last_wqe = (sqcc == wqe_counter);
1285
1286                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
1287                         di = &sq->db.di[ci];
1288
1289                         sqcc++;
1290                         /* Recycle RX page */
1291                         mlx5e_page_release(rq, di, true);
1292                 } while (!last_wqe);
1293         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1294
1295         mlx5_cqwq_update_db_record(&cq->wq);
1296
1297         /* ensure cq space is freed before enabling more cqes */
1298         wmb();
1299
1300         sq->cc = sqcc;
1301         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1302 }
1303
1304 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1305 {
1306         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1307         struct mlx5e_dma_info *di;
1308         u16 ci;
1309
1310         while (sq->cc != sq->pc) {
1311                 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc);
1312                 di = &sq->db.di[ci];
1313                 sq->cc++;
1314
1315                 mlx5e_page_release(rq, di, false);
1316         }
1317 }
1318
1319 #ifdef CONFIG_MLX5_CORE_IPOIB
1320
1321 #define MLX5_IB_GRH_DGID_OFFSET 24
1322 #define MLX5_GID_SIZE           16
1323
1324 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1325                                          struct mlx5_cqe64 *cqe,
1326                                          u32 cqe_bcnt,
1327                                          struct sk_buff *skb)
1328 {
1329         struct mlx5e_rq_stats *stats = rq->stats;
1330         struct hwtstamp_config *tstamp;
1331         struct net_device *netdev;
1332         struct mlx5e_priv *priv;
1333         char *pseudo_header;
1334         u32 qpn;
1335         u8 *dgid;
1336         u8 g;
1337
1338         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1339         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1340
1341         /* No mapping present, cannot process SKB. This might happen if a child
1342          * interface is going down while having unprocessed CQEs on parent RQ
1343          */
1344         if (unlikely(!netdev)) {
1345                 /* TODO: add drop counters support */
1346                 skb->dev = NULL;
1347                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1348                 return;
1349         }
1350
1351         priv = mlx5i_epriv(netdev);
1352         tstamp = &priv->tstamp;
1353
1354         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1355         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1356         if ((!g) || dgid[0] != 0xff)
1357                 skb->pkt_type = PACKET_HOST;
1358         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1359                 skb->pkt_type = PACKET_BROADCAST;
1360         else
1361                 skb->pkt_type = PACKET_MULTICAST;
1362
1363         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1364          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1365          */
1366
1367         skb_pull(skb, MLX5_IB_GRH_BYTES);
1368
1369         skb->protocol = *((__be16 *)(skb->data));
1370
1371         skb->ip_summed = CHECKSUM_COMPLETE;
1372         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1373
1374         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1375                 skb_hwtstamps(skb)->hwtstamp =
1376                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1377
1378         skb_record_rx_queue(skb, rq->ix);
1379
1380         if (likely(netdev->features & NETIF_F_RXHASH))
1381                 mlx5e_skb_set_hash(cqe, skb);
1382
1383         /* 20 bytes of ipoib header and 4 for encap existing */
1384         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1385         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1386         skb_reset_mac_header(skb);
1387         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1388
1389         skb->dev = netdev;
1390
1391         stats->csum_complete++;
1392         stats->packets++;
1393         stats->bytes += cqe_bcnt;
1394 }
1395
1396 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1397 {
1398         struct mlx5e_wqe_frag_info *wi;
1399         struct mlx5e_rx_wqe *wqe;
1400         __be16 wqe_counter_be;
1401         struct sk_buff *skb;
1402         u16 wqe_counter;
1403         u32 cqe_bcnt;
1404
1405         wqe_counter_be = cqe->wqe_counter;
1406         wqe_counter    = be16_to_cpu(wqe_counter_be);
1407         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1408         wi             = &rq->wqe.frag_info[wqe_counter];
1409         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1410
1411         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1412         if (!skb)
1413                 goto wq_free_wqe;
1414
1415         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1416         if (unlikely(!skb->dev)) {
1417                 dev_kfree_skb_any(skb);
1418                 goto wq_free_wqe;
1419         }
1420         napi_gro_receive(rq->cq.napi, skb);
1421
1422 wq_free_wqe:
1423         mlx5e_free_rx_wqe_reuse(rq, wi);
1424         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1425                        &wqe->next.next_wqe_index);
1426 }
1427
1428 #endif /* CONFIG_MLX5_CORE_IPOIB */
1429
1430 #ifdef CONFIG_MLX5_EN_IPSEC
1431
1432 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1433 {
1434         struct mlx5e_wqe_frag_info *wi;
1435         struct mlx5e_rx_wqe *wqe;
1436         __be16 wqe_counter_be;
1437         struct sk_buff *skb;
1438         u16 wqe_counter;
1439         u32 cqe_bcnt;
1440
1441         wqe_counter_be = cqe->wqe_counter;
1442         wqe_counter    = be16_to_cpu(wqe_counter_be);
1443         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1444         wi             = &rq->wqe.frag_info[wqe_counter];
1445         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1446
1447         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1448         if (unlikely(!skb)) {
1449                 /* a DROP, save the page-reuse checks */
1450                 mlx5e_free_rx_wqe(rq, wi);
1451                 goto wq_ll_pop;
1452         }
1453         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1454         if (unlikely(!skb)) {
1455                 mlx5e_free_rx_wqe(rq, wi);
1456                 goto wq_ll_pop;
1457         }
1458
1459         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1460         napi_gro_receive(rq->cq.napi, skb);
1461
1462         mlx5e_free_rx_wqe_reuse(rq, wi);
1463 wq_ll_pop:
1464         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1465                        &wqe->next.next_wqe_index);
1466 }
1467
1468 #endif /* CONFIG_MLX5_EN_IPSEC */