drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/bpf_trace.h>
  38 #include <net/busy_poll.h>
  39 #include <net/ip6_checksum.h>
  40 #include <net/page_pool.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "lib/clock.h"
  48
  49 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  50 {
  51         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  52 }
  53
  54 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
  55                                        void *data)
  56 {
  57         u32 ci = cqcc & cq->wq.fbc.sz_m1;
  58
  59         memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
  60 }
  61
  62 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  63                                          struct mlx5e_cq *cq, u32 cqcc)
  64 {
  65         mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
  66         cq->decmprs_left        = be32_to_cpu(cq->title.byte_cnt);
  67         cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
  68         rq->stats.cqe_compress_blks++;
  69 }
  70
  71 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
  72 {
  73         mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
  74         cq->mini_arr_idx = 0;
  75 }
  76
  77 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
  78 {
  79         struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc;
  80         u8 op_own = (cqcc >> fbc->log_sz) & 1;
  81         u32 wq_sz = 1 << fbc->log_sz;
  82         u32 ci = cqcc & fbc->sz_m1;
  83         u32 ci_top = min_t(u32, wq_sz, ci + n);
  84
  85         for (; ci < ci_top; ci++, n--) {
  86                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  87
  88                 cqe->op_own = op_own;
  89         }
  90
  91         if (unlikely(ci == wq_sz)) {
  92                 op_own = !op_own;
  93                 for (ci = 0; ci < n; ci++) {
  94                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
  95
  96                         cqe->op_own = op_own;
  97                 }
  98         }
  99 }
 100
 101 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 102                                         struct mlx5e_cq *cq, u32 cqcc)
 103 {
 104         cq->title.byte_cnt     = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
 105         cq->title.check_sum    = cq->mini_arr[cq->mini_arr_idx].checksum;
 106         cq->title.op_own      &= 0xf0;
 107         cq->title.op_own      |= 0x01 & (cqcc >> cq->wq.fbc.log_sz);
 108         cq->title.wqe_counter  = cpu_to_be16(cq->decmprs_wqe_counter);
 109
 110         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 111                 cq->decmprs_wqe_counter +=
 112                         mpwrq_get_cqe_consumed_strides(&cq->title);
 113         else
 114                 cq->decmprs_wqe_counter =
 115                         (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1;
 116 }
 117
 118 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 119                                                 struct mlx5e_cq *cq, u32 cqcc)
 120 {
 121         mlx5e_decompress_cqe(rq, cq, cqcc);
 122         cq->title.rss_hash_type   = 0;
 123         cq->title.rss_hash_result = 0;
 124 }
 125
 126 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 127                                              struct mlx5e_cq *cq,
 128                                              int update_owner_only,
 129                                              int budget_rem)
 130 {
 131         u32 cqcc = cq->wq.cc + update_owner_only;
 132         u32 cqe_count;
 133         u32 i;
 134
 135         cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
 136
 137         for (i = update_owner_only; i < cqe_count;
 138              i++, cq->mini_arr_idx++, cqcc++) {
 139                 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 140                         mlx5e_read_mini_arr_slot(cq, cqcc);
 141
 142                 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
 143                 rq->handle_rx_cqe(rq, &cq->title);
 144         }
 145         mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
 146         cq->wq.cc = cqcc;
 147         cq->decmprs_left -= cqe_count;
 148         rq->stats.cqe_compress_pkts += cqe_count;
 149
 150         return cqe_count;
 151 }
 152
 153 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 154                                               struct mlx5e_cq *cq,
 155                                               int budget_rem)
 156 {
 157         mlx5e_read_title_slot(rq, cq, cq->wq.cc);
 158         mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
 159         mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
 160         rq->handle_rx_cqe(rq, &cq->title);
 161         cq->mini_arr_idx++;
 162
 163         return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
 164 }
 165
 166 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
 167
 168 static inline bool mlx5e_page_is_reserved(struct page *page)
 169 {
 170         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 171 }
 172
 173 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 174                                       struct mlx5e_dma_info *dma_info)
 175 {
 176         struct mlx5e_page_cache *cache = &rq->page_cache;
 177         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 178
 179         if (tail_next == cache->head) {
 180                 rq->stats.cache_full++;
 181                 return false;
 182         }
 183
 184         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 185                 rq->stats.cache_waive++;
 186                 return false;
 187         }
 188
 189         cache->page_cache[cache->tail] = *dma_info;
 190         cache->tail = tail_next;
 191         return true;
 192 }
 193
 194 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 195                                       struct mlx5e_dma_info *dma_info)
 196 {
 197         struct mlx5e_page_cache *cache = &rq->page_cache;
 198
 199         if (unlikely(cache->head == cache->tail)) {
 200                 rq->stats.cache_empty++;
 201                 return false;
 202         }
 203
 204         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 205                 rq->stats.cache_busy++;
 206                 return false;
 207         }
 208
 209         *dma_info = cache->page_cache[cache->head];
 210         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 211         rq->stats.cache_reuse++;
 212
 213         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 214                                    RQ_PAGE_SIZE(rq),
 215                                    DMA_FROM_DEVICE);
 216         return true;
 217 }
 218
 219 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 220                                           struct mlx5e_dma_info *dma_info)
 221 {
 222         if (mlx5e_rx_cache_get(rq, dma_info))
 223                 return 0;
 224
 225         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 226         if (unlikely(!dma_info->page))
 227                 return -ENOMEM;
 228
 229         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 230                                       RQ_PAGE_SIZE(rq), rq->buff.map_dir);
 231         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 232                 put_page(dma_info->page);
 233                 dma_info->page = NULL;
 234                 return -ENOMEM;
 235         }
 236
 237         return 0;
 238 }
 239
 240 static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq,
 241                                         struct mlx5e_dma_info *dma_info)
 242 {
 243         dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
 244                        rq->buff.map_dir);
 245 }
 246
 247 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 248                         bool recycle)
 249 {
 250         if (likely(recycle)) {
 251                 if (mlx5e_rx_cache_put(rq, dma_info))
 252                         return;
 253
 254                 mlx5e_page_dma_unmap(rq, dma_info);
 255                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 256         } else {
 257                 mlx5e_page_dma_unmap(rq, dma_info);
 258                 put_page(dma_info->page);
 259         }
 260 }
 261
 262 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq,
 263                                     struct mlx5e_wqe_frag_info *wi)
 264 {
 265         return rq->wqe.page_reuse && wi->di.page &&
 266                 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) &&
 267                 !mlx5e_page_is_reserved(wi->di.page);
 268 }
 269
 270 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
 271 {
 272         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 273
 274         /* check if page exists, hence can be reused */
 275         if (!wi->di.page) {
 276                 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di)))
 277                         return -ENOMEM;
 278                 wi->offset = 0;
 279         }
 280
 281         wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom);
 282         return 0;
 283 }
 284
 285 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 286                                      struct mlx5e_wqe_frag_info *wi)
 287 {
 288         mlx5e_page_release(rq, &wi->di, true);
 289         wi->di.page = NULL;
 290 }
 291
 292 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq,
 293                                            struct mlx5e_wqe_frag_info *wi)
 294 {
 295         if (mlx5e_page_reuse(rq, wi)) {
 296                 rq->stats.page_reuse++;
 297                 return;
 298         }
 299
 300         mlx5e_free_rx_wqe(rq, wi);
 301 }
 302
 303 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 304 {
 305         struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix];
 306
 307         if (wi->di.page)
 308                 mlx5e_free_rx_wqe(rq, wi);
 309 }
 310
 311 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
 312                                             struct sk_buff *skb,
 313                                             struct mlx5e_dma_info *di,
 314                                             u32 frag_offset, u32 len)
 315 {
 316         unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz));
 317
 318         dma_sync_single_for_cpu(rq->pdev,
 319                                 di->addr + frag_offset,
 320                                 len, DMA_FROM_DEVICE);
 321         page_ref_inc(di->page);
 322         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 323                         di->page, frag_offset, len, truesize);
 324 }
 325
 326 static inline void
 327 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
 328                             struct sk_buff *skb,
 329                             struct mlx5e_dma_info *dma_info,
 330                             u32 offset, u32 headlen)
 331 {
 332         u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
 333         unsigned int len;
 334
 335          /* Aligning len to sizeof(long) optimizes memcpy performance */
 336         len = ALIGN(headlen_pg, sizeof(long));
 337         dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
 338                                 DMA_FROM_DEVICE);
 339         skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len);
 340
 341         if (unlikely(offset + headlen > PAGE_SIZE)) {
 342                 dma_info++;
 343                 headlen_pg = len;
 344                 len = ALIGN(headlen - headlen_pg, sizeof(long));
 345                 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
 346                                         DMA_FROM_DEVICE);
 347                 skb_copy_to_linear_data_offset(skb, headlen_pg,
 348                                                page_address(dma_info->page),
 349                                                len);
 350         }
 351 }
 352
 353 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
 354 {
 355         const bool no_xdp_xmit =
 356                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 357         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 358         int i;
 359
 360         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 361                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 362                         mlx5e_page_release(rq, &dma_info[i], true);
 363 }
 364
 365 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
 366 {
 367         struct mlx5_wq_ll *wq = &rq->wq;
 368         struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 369
 370         rq->mpwqe.umr_in_progress = false;
 371
 372         mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 373
 374         /* ensure wqes are visible to device before updating doorbell record */
 375         dma_wmb();
 376
 377         mlx5_wq_ll_update_db_record(wq);
 378 }
 379
 380 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
 381 {
 382         return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
 383 }
 384
 385 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 386 {
 387         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 388         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 389         struct mlx5e_icosq *sq = &rq->channel->icosq;
 390         struct mlx5_wq_cyc *wq = &sq->wq;
 391         struct mlx5e_umr_wqe *umr_wqe;
 392         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 393         int err;
 394         u16 pi;
 395         int i;
 396
 397         /* fill sq edge with nops to avoid wqe wrap around */
 398         while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
 399                 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
 400                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 401         }
 402
 403         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 404         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
 405                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
 406                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
 407
 408         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 409                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 410                 if (unlikely(err))
 411                         goto err_unmap;
 412                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 413         }
 414
 415         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 416         wi->consumed_strides = 0;
 417
 418         rq->mpwqe.umr_in_progress = true;
 419
 420         umr_wqe->ctrl.opmod_idx_opcode =
 421                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 422                             MLX5_OPCODE_UMR);
 423         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 424
 425         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 426         sq->pc += MLX5E_UMR_WQEBBS;
 427         mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl);
 428
 429         return 0;
 430
 431 err_unmap:
 432         while (--i >= 0) {
 433                 dma_info--;
 434                 mlx5e_page_release(rq, dma_info, true);
 435         }
 436         rq->stats.buff_alloc_err++;
 437
 438         return err;
 439 }
 440
 441 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 442 {
 443         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 444
 445         mlx5e_free_rx_mpwqe(rq, wi);
 446 }
 447
 448 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 449 {
 450         struct mlx5_wq_ll *wq = &rq->wq;
 451         int err;
 452
 453         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 454                 return false;
 455
 456         if (mlx5_wq_ll_is_full(wq))
 457                 return false;
 458
 459         do {
 460                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
 461
 462                 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head);
 463                 if (unlikely(err)) {
 464                         rq->stats.buff_alloc_err++;
 465                         break;
 466                 }
 467
 468                 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
 469         } while (!mlx5_wq_ll_is_full(wq));
 470
 471         /* ensure wqes are visible to device before updating doorbell record */
 472         dma_wmb();
 473
 474         mlx5_wq_ll_update_db_record(wq);
 475
 476         return !!err;
 477 }
 478
 479 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
 480                                              struct mlx5e_icosq *sq,
 481                                              struct mlx5e_rq *rq,
 482                                              struct mlx5_cqe64 *cqe)
 483 {
 484         struct mlx5_wq_cyc *wq = &sq->wq;
 485         u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
 486         struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
 487
 488         mlx5_cqwq_pop(&cq->wq);
 489
 490         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
 491                 netdev_WARN_ONCE(cq->channel->netdev,
 492                                  "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own);
 493                 return;
 494         }
 495
 496         if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
 497                 mlx5e_post_rx_mpwqe(rq);
 498                 return;
 499         }
 500
 501         if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
 502                 netdev_WARN_ONCE(cq->channel->netdev,
 503                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode);
 504 }
 505
 506 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 507 {
 508         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 509         struct mlx5_cqe64 *cqe;
 510
 511         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
 512                 return;
 513
 514         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 515         if (likely(!cqe))
 516                 return;
 517
 518         /* by design, there's only a single cqe */
 519         mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe);
 520
 521         mlx5_cqwq_update_db_record(&cq->wq);
 522 }
 523
 524 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 525 {
 526         struct mlx5_wq_ll *wq = &rq->wq;
 527
 528         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
 529                 return false;
 530
 531         mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq);
 532
 533         if (mlx5_wq_ll_is_full(wq))
 534                 return false;
 535
 536         if (!rq->mpwqe.umr_in_progress)
 537                 mlx5e_alloc_rx_mpwqe(rq, wq->head);
 538
 539         return false;
 540 }
 541
 542 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 543 {
 544         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 545         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 546                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 547
 548         tcp->check                      = 0;
 549         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 550
 551         if (tcp_ack) {
 552                 tcp->ack                = 1;
 553                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 554                 tcp->window             = cqe->lro_tcp_win;
 555         }
 556 }
 557
 558 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 559                                  u32 cqe_bcnt)
 560 {
 561         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 562         struct tcphdr   *tcp;
 563         int network_depth = 0;
 564         __wsum check;
 565         __be16 proto;
 566         u16 tot_len;
 567         void *ip_p;
 568
 569         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 570
 571         tot_len = cqe_bcnt - network_depth;
 572         ip_p = skb->data + network_depth;
 573
 574         if (proto == htons(ETH_P_IP)) {
 575                 struct iphdr *ipv4 = ip_p;
 576
 577                 tcp = ip_p + sizeof(struct iphdr);
 578                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 579
 580                 ipv4->ttl               = cqe->lro_min_ttl;
 581                 ipv4->tot_len           = cpu_to_be16(tot_len);
 582                 ipv4->check             = 0;
 583                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 584                                                        ipv4->ihl);
 585
 586                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 587                 check = csum_partial(tcp, tcp->doff * 4,
 588                                      csum_unfold((__force __sum16)cqe->check_sum));
 589                 /* Almost done, don't forget the pseudo header */
 590                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 591                                                tot_len - sizeof(struct iphdr),
 592                                                IPPROTO_TCP, check);
 593         } else {
 594                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 595                 struct ipv6hdr *ipv6 = ip_p;
 596
 597                 tcp = ip_p + sizeof(struct ipv6hdr);
 598                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 599
 600                 ipv6->hop_limit         = cqe->lro_min_ttl;
 601                 ipv6->payload_len       = cpu_to_be16(payload_len);
 602
 603                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 604                 check = csum_partial(tcp, tcp->doff * 4,
 605                                      csum_unfold((__force __sum16)cqe->check_sum));
 606                 /* Almost done, don't forget the pseudo header */
 607                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 608                                              IPPROTO_TCP, check);
 609         }
 610 }
 611
 612 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 613                                       struct sk_buff *skb)
 614 {
 615         u8 cht = cqe->rss_hash_type;
 616         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 617                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 618                                             PKT_HASH_TYPE_NONE;
 619         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 620 }
 621
 622 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth)
 623 {
 624         __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
 625
 626         ethertype = __vlan_get_protocol(skb, ethertype, network_depth);
 627         return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
 628 }
 629
 630 static inline void mlx5e_handle_csum(struct net_device *netdev,
 631                                      struct mlx5_cqe64 *cqe,
 632                                      struct mlx5e_rq *rq,
 633                                      struct sk_buff *skb,
 634                                      bool   lro)
 635 {
 636         int network_depth = 0;
 637
 638         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 639                 goto csum_none;
 640
 641         if (lro) {
 642                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 643                 rq->stats.csum_unnecessary++;
 644                 return;
 645         }
 646
 647         if (likely(is_last_ethertype_ip(skb, &network_depth))) {
 648                 skb->ip_summed = CHECKSUM_COMPLETE;
 649                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 650                 if (network_depth > ETH_HLEN)
 651                         /* CQE csum is calculated from the IP header and does
 652                          * not cover VLAN headers (if present). This will add
 653                          * the checksum manually.
 654                          */
 655                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 656                                                  network_depth - ETH_HLEN,
 657                                                  skb->csum);
 658                 rq->stats.csum_complete++;
 659                 return;
 660         }
 661
 662         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 663                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 664                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 665                 if (cqe_is_tunneled(cqe)) {
 666                         skb->csum_level = 1;
 667                         skb->encapsulation = 1;
 668                         rq->stats.csum_unnecessary_inner++;
 669                         return;
 670                 }
 671                 rq->stats.csum_unnecessary++;
 672                 return;
 673         }
 674 csum_none:
 675         skb->ip_summed = CHECKSUM_NONE;
 676         rq->stats.csum_none++;
 677 }
 678
 679 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 680                                       u32 cqe_bcnt,
 681                                       struct mlx5e_rq *rq,
 682                                       struct sk_buff *skb)
 683 {
 684         struct net_device *netdev = rq->netdev;
 685         int lro_num_seg;
 686
 687         skb->mac_len = ETH_HLEN;
 688         lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 689         if (lro_num_seg > 1) {
 690                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 691                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 692                 /* Subtract one since we already counted this as one
 693                  * "regular" packet in mlx5e_complete_rx_cqe()
 694                  */
 695                 rq->stats.packets += lro_num_seg - 1;
 696                 rq->stats.lro_packets++;
 697                 rq->stats.lro_bytes += cqe_bcnt;
 698         }
 699
 700         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 701                 skb_hwtstamps(skb)->hwtstamp =
 702                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 703
 704         skb_record_rx_queue(skb, rq->ix);
 705
 706         if (likely(netdev->features & NETIF_F_RXHASH))
 707                 mlx5e_skb_set_hash(cqe, skb);
 708
 709         if (cqe_has_vlan(cqe)) {
 710                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 711                                        be16_to_cpu(cqe->vlan_info));
 712                 rq->stats.removed_vlan_packets++;
 713         }
 714
 715         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 716
 717         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 718         skb->protocol = eth_type_trans(skb, netdev);
 719 }
 720
 721 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 722                                          struct mlx5_cqe64 *cqe,
 723                                          u32 cqe_bcnt,
 724                                          struct sk_buff *skb)
 725 {
 726         rq->stats.packets++;
 727         rq->stats.bytes += cqe_bcnt;
 728         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 729 }
 730
 731 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
 732 {
 733         struct mlx5_wq_cyc *wq = &sq->wq;
 734         struct mlx5e_tx_wqe *wqe;
 735         u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */
 736
 737         wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 738
 739         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl);
 740 }
 741
 742 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
 743                                         struct mlx5e_dma_info *di,
 744                                         const struct xdp_buff *xdp)
 745 {
 746         struct mlx5e_xdpsq       *sq   = &rq->xdpsq;
 747         struct mlx5_wq_cyc       *wq   = &sq->wq;
 748         u16                       pi   = sq->pc & wq->sz_m1;
 749         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 750
 751         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 752         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 753         struct mlx5_wqe_data_seg *dseg;
 754
 755         ptrdiff_t data_offset = xdp->data - xdp->data_hard_start;
 756         dma_addr_t dma_addr  = di->addr + data_offset;
 757         unsigned int dma_len = xdp->data_end - xdp->data;
 758
 759         prefetchw(wqe);
 760
 761         if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) {
 762                 rq->stats.xdp_drop++;
 763                 return false;
 764         }
 765
 766         if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) {
 767                 if (sq->db.doorbell) {
 768                         /* SQ is full, ring doorbell */
 769                         mlx5e_xmit_xdp_doorbell(sq);
 770                         sq->db.doorbell = false;
 771                 }
 772                 rq->stats.xdp_tx_full++;
 773                 return false;
 774         }
 775
 776         dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
 777
 778         cseg->fm_ce_se = 0;
 779
 780         dseg = (struct mlx5_wqe_data_seg *)eseg + 1;
 781
 782         /* copy the inline part if required */
 783         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
 784                 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE);
 785                 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
 786                 dma_len  -= MLX5E_XDP_MIN_INLINE;
 787                 dma_addr += MLX5E_XDP_MIN_INLINE;
 788                 dseg++;
 789         }
 790
 791         /* write the dma part */
 792         dseg->addr       = cpu_to_be64(dma_addr);
 793         dseg->byte_count = cpu_to_be32(dma_len);
 794
 795         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
 796
 797         /* move page to reference to sq responsibility,
 798          * and mark so it's not put back in page-cache.
 799          */
 800         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */
 801         sq->db.di[pi] = *di;
 802         sq->pc++;
 803
 804         sq->db.doorbell = true;
 805
 806         rq->stats.xdp_tx++;
 807         return true;
 808 }
 809
 810 /* returns true if packet was consumed by xdp */
 811 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq,
 812                                    struct mlx5e_dma_info *di,
 813                                    void *va, u16 *rx_headroom, u32 *len)
 814 {
 815         struct bpf_prog *prog = READ_ONCE(rq->xdp_prog);
 816         struct xdp_buff xdp;
 817         u32 act;
 818         int err;
 819
 820         if (!prog)
 821                 return false;
 822
 823         xdp.data = va + *rx_headroom;
 824         xdp_set_data_meta_invalid(&xdp);
 825         xdp.data_end = xdp.data + *len;
 826         xdp.data_hard_start = va;
 827         xdp.rxq = &rq->xdp_rxq;
 828
 829         act = bpf_prog_run_xdp(prog, &xdp);
 830         switch (act) {
 831         case XDP_PASS:
 832                 *rx_headroom = xdp.data - xdp.data_hard_start;
 833                 *len = xdp.data_end - xdp.data;
 834                 return false;
 835         case XDP_TX:
 836                 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp)))
 837                         trace_xdp_exception(rq->netdev, prog, act);
 838                 return true;
 839         case XDP_REDIRECT:
 840                 /* When XDP enabled then page-refcnt==1 here */
 841                 err = xdp_do_redirect(rq->netdev, &xdp, prog);
 842                 if (!err) {
 843                         __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags);
 844                         rq->xdpsq.db.redirect_flush = true;
 845                         mlx5e_page_dma_unmap(rq, di);
 846                 }
 847                 return true;
 848         default:
 849                 bpf_warn_invalid_xdp_action(act);
 850         case XDP_ABORTED:
 851                 trace_xdp_exception(rq->netdev, prog, act);
 852         case XDP_DROP:
 853                 rq->stats.xdp_drop++;
 854                 return true;
 855         }
 856 }
 857
 858 static inline
 859 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 860                                        u32 frag_size, u16 headroom,
 861                                        u32 cqe_bcnt)
 862 {
 863         struct sk_buff *skb = build_skb(va, frag_size);
 864
 865         if (unlikely(!skb)) {
 866                 rq->stats.buff_alloc_err++;
 867                 return NULL;
 868         }
 869
 870         skb_reserve(skb, headroom);
 871         skb_put(skb, cqe_bcnt);
 872
 873         return skb;
 874 }
 875
 876 static inline
 877 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 878                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 879 {
 880         struct mlx5e_dma_info *di = &wi->di;
 881         u16 rx_headroom = rq->buff.headroom;
 882         struct sk_buff *skb;
 883         void *va, *data;
 884         bool consumed;
 885         u32 frag_size;
 886
 887         va             = page_address(di->page) + wi->offset;
 888         data           = va + rx_headroom;
 889         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
 890
 891         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
 892                                       frag_size, DMA_FROM_DEVICE);
 893         prefetchw(va); /* xdp_frame data area */
 894         prefetch(data);
 895         wi->offset += frag_size;
 896
 897         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
 898                 rq->stats.wqe_err++;
 899                 return NULL;
 900         }
 901
 902         rcu_read_lock();
 903         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
 904         rcu_read_unlock();
 905         if (consumed)
 906                 return NULL; /* page/packet was consumed by XDP */
 907
 908         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
 909         if (unlikely(!skb))
 910                 return NULL;
 911
 912         /* queue up for recycling/reuse */
 913         page_ref_inc(di->page);
 914
 915         return skb;
 916 }
 917
 918 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 919 {
 920         struct mlx5e_wqe_frag_info *wi;
 921         struct mlx5e_rx_wqe *wqe;
 922         __be16 wqe_counter_be;
 923         struct sk_buff *skb;
 924         u16 wqe_counter;
 925         u32 cqe_bcnt;
 926
 927         wqe_counter_be = cqe->wqe_counter;
 928         wqe_counter    = be16_to_cpu(wqe_counter_be);
 929         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 930         wi             = &rq->wqe.frag_info[wqe_counter];
 931         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 932
 933         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 934         if (!skb) {
 935                 /* probably for XDP */
 936                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
 937                         wi->di.page = NULL;
 938                         /* do not return page to cache, it will be returned on XDP_TX completion */
 939                         goto wq_ll_pop;
 940                 }
 941                 /* probably an XDP_DROP, save the page-reuse checks */
 942                 mlx5e_free_rx_wqe(rq, wi);
 943                 goto wq_ll_pop;
 944         }
 945
 946         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 947         napi_gro_receive(rq->cq.napi, skb);
 948
 949         mlx5e_free_rx_wqe_reuse(rq, wi);
 950 wq_ll_pop:
 951         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 952                        &wqe->next.next_wqe_index);
 953 }
 954
 955 #ifdef CONFIG_MLX5_ESWITCH
 956 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
 957 {
 958         struct net_device *netdev = rq->netdev;
 959         struct mlx5e_priv *priv = netdev_priv(netdev);
 960         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
 961         struct mlx5_eswitch_rep *rep = rpriv->rep;
 962         struct mlx5e_wqe_frag_info *wi;
 963         struct mlx5e_rx_wqe *wqe;
 964         struct sk_buff *skb;
 965         __be16 wqe_counter_be;
 966         u16 wqe_counter;
 967         u32 cqe_bcnt;
 968
 969         wqe_counter_be = cqe->wqe_counter;
 970         wqe_counter    = be16_to_cpu(wqe_counter_be);
 971         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
 972         wi             = &rq->wqe.frag_info[wqe_counter];
 973         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
 974
 975         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
 976         if (!skb) {
 977                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
 978                         wi->di.page = NULL;
 979                         /* do not return page to cache, it will be returned on XDP_TX completion */
 980                         goto wq_ll_pop;
 981                 }
 982                 /* probably an XDP_DROP, save the page-reuse checks */
 983                 mlx5e_free_rx_wqe(rq, wi);
 984                 goto wq_ll_pop;
 985         }
 986
 987         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
 988
 989         if (rep->vlan && skb_vlan_tag_present(skb))
 990                 skb_vlan_pop(skb);
 991
 992         napi_gro_receive(rq->cq.napi, skb);
 993
 994         mlx5e_free_rx_wqe_reuse(rq, wi);
 995 wq_ll_pop:
 996         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
 997                        &wqe->next.next_wqe_index);
 998 }
 999 #endif
1000
1001 struct sk_buff *
1002 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1003                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1004 {
1005         u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
1006         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1007         u32 frag_offset    = head_offset + headlen;
1008         u32 byte_cnt       = cqe_bcnt - headlen;
1009         struct mlx5e_dma_info *head_di = di;
1010         struct sk_buff *skb;
1011
1012         skb = napi_alloc_skb(rq->cq.napi,
1013                              ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long)));
1014         if (unlikely(!skb)) {
1015                 rq->stats.buff_alloc_err++;
1016                 return NULL;
1017         }
1018
1019         prefetchw(skb->data);
1020
1021         if (unlikely(frag_offset >= PAGE_SIZE)) {
1022                 di++;
1023                 frag_offset -= PAGE_SIZE;
1024         }
1025
1026         while (byte_cnt) {
1027                 u32 pg_consumed_bytes =
1028                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1029
1030                 mlx5e_add_skb_frag_mpwqe(rq, skb, di, frag_offset,
1031                                          pg_consumed_bytes);
1032                 byte_cnt -= pg_consumed_bytes;
1033                 frag_offset = 0;
1034                 di++;
1035         }
1036         /* copy header */
1037         mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di,
1038                                     head_offset, headlen);
1039         /* skb linear part was allocated with headlen and aligned to long */
1040         skb->tail += headlen;
1041         skb->len  += headlen;
1042
1043         return skb;
1044 }
1045
1046 struct sk_buff *
1047 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1048                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1049 {
1050         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1051         u16 rx_headroom = rq->buff.headroom;
1052         u32 cqe_bcnt32 = cqe_bcnt;
1053         struct sk_buff *skb;
1054         void *va, *data;
1055         u32 frag_size;
1056         bool consumed;
1057
1058         va             = page_address(di->page) + head_offset;
1059         data           = va + rx_headroom;
1060         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1061
1062         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1063                                       frag_size, DMA_FROM_DEVICE);
1064         prefetch(data);
1065
1066         rcu_read_lock();
1067         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1068         rcu_read_unlock();
1069         if (consumed) {
1070                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1071                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1072                 return NULL; /* page/packet was consumed by XDP */
1073         }
1074
1075         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1076         if (unlikely(!skb))
1077                 return NULL;
1078
1079         /* queue up for recycling/reuse */
1080         page_ref_inc(di->page);
1081
1082         return skb;
1083 }
1084
1085 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1086 {
1087         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1088         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1089         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1090         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1091         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1092         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1093         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1094         struct mlx5e_rx_wqe *wqe;
1095         struct sk_buff *skb;
1096         u16 cqe_bcnt;
1097
1098         wi->consumed_strides += cstrides;
1099
1100         if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
1101                 rq->stats.wqe_err++;
1102                 goto mpwrq_cqe_out;
1103         }
1104
1105         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1106                 rq->stats.mpwqe_filler++;
1107                 goto mpwrq_cqe_out;
1108         }
1109
1110         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1111
1112         skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset,
1113                                            page_idx);
1114         if (!skb)
1115                 goto mpwrq_cqe_out;
1116
1117         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1118         napi_gro_receive(rq->cq.napi, skb);
1119
1120 mpwrq_cqe_out:
1121         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1122                 return;
1123
1124         wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
1125         mlx5e_free_rx_mpwqe(rq, wi);
1126         mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1127 }
1128
1129 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1130 {
1131         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1132         struct mlx5e_xdpsq *xdpsq;
1133         struct mlx5_cqe64 *cqe;
1134         int work_done = 0;
1135
1136         if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED)))
1137                 return 0;
1138
1139         if (cq->decmprs_left)
1140                 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
1141
1142         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1143         if (!cqe)
1144                 return 0;
1145
1146         xdpsq = &rq->xdpsq;
1147
1148         do {
1149                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1150                         work_done +=
1151                                 mlx5e_decompress_cqes_start(rq, cq,
1152                                                             budget - work_done);
1153                         continue;
1154                 }
1155
1156                 mlx5_cqwq_pop(&cq->wq);
1157
1158                 rq->handle_rx_cqe(rq, cqe);
1159         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1160
1161         if (xdpsq->db.doorbell) {
1162                 mlx5e_xmit_xdp_doorbell(xdpsq);
1163                 xdpsq->db.doorbell = false;
1164         }
1165
1166         if (xdpsq->db.redirect_flush) {
1167                 xdp_do_flush_map();
1168                 xdpsq->db.redirect_flush = false;
1169         }
1170
1171         mlx5_cqwq_update_db_record(&cq->wq);
1172
1173         /* ensure cq space is freed before enabling more cqes */
1174         wmb();
1175
1176         return work_done;
1177 }
1178
1179 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq)
1180 {
1181         struct mlx5e_xdpsq *sq;
1182         struct mlx5_cqe64 *cqe;
1183         struct mlx5e_rq *rq;
1184         u16 sqcc;
1185         int i;
1186
1187         sq = container_of(cq, struct mlx5e_xdpsq, cq);
1188
1189         if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED)))
1190                 return false;
1191
1192         cqe = mlx5_cqwq_get_cqe(&cq->wq);
1193         if (!cqe)
1194                 return false;
1195
1196         rq = container_of(sq, struct mlx5e_rq, xdpsq);
1197
1198         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1199          * otherwise a cq overrun may occur
1200          */
1201         sqcc = sq->cc;
1202
1203         i = 0;
1204         do {
1205                 u16 wqe_counter;
1206                 bool last_wqe;
1207
1208                 mlx5_cqwq_pop(&cq->wq);
1209
1210                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
1211
1212                 do {
1213                         struct mlx5e_dma_info *di;
1214                         u16 ci;
1215
1216                         last_wqe = (sqcc == wqe_counter);
1217
1218                         ci = sqcc & sq->wq.sz_m1;
1219                         di = &sq->db.di[ci];
1220
1221                         sqcc++;
1222                         /* Recycle RX page */
1223                         mlx5e_page_release(rq, di, true);
1224                 } while (!last_wqe);
1225         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
1226
1227         mlx5_cqwq_update_db_record(&cq->wq);
1228
1229         /* ensure cq space is freed before enabling more cqes */
1230         wmb();
1231
1232         sq->cc = sqcc;
1233         return (i == MLX5E_TX_CQ_POLL_BUDGET);
1234 }
1235
1236 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq)
1237 {
1238         struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq);
1239         struct mlx5e_dma_info *di;
1240         u16 ci;
1241
1242         while (sq->cc != sq->pc) {
1243                 ci = sq->cc & sq->wq.sz_m1;
1244                 di = &sq->db.di[ci];
1245                 sq->cc++;
1246
1247                 mlx5e_page_release(rq, di, false);
1248         }
1249 }
1250
1251 #ifdef CONFIG_MLX5_CORE_IPOIB
1252
1253 #define MLX5_IB_GRH_DGID_OFFSET 24
1254 #define MLX5_GID_SIZE           16
1255
1256 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1257                                          struct mlx5_cqe64 *cqe,
1258                                          u32 cqe_bcnt,
1259                                          struct sk_buff *skb)
1260 {
1261         struct hwtstamp_config *tstamp;
1262         struct net_device *netdev;
1263         struct mlx5e_priv *priv;
1264         char *pseudo_header;
1265         u32 qpn;
1266         u8 *dgid;
1267         u8 g;
1268
1269         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1270         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1271
1272         /* No mapping present, cannot process SKB. This might happen if a child
1273          * interface is going down while having unprocessed CQEs on parent RQ
1274          */
1275         if (unlikely(!netdev)) {
1276                 /* TODO: add drop counters support */
1277                 skb->dev = NULL;
1278                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1279                 return;
1280         }
1281
1282         priv = mlx5i_epriv(netdev);
1283         tstamp = &priv->tstamp;
1284
1285         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1286         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1287         if ((!g) || dgid[0] != 0xff)
1288                 skb->pkt_type = PACKET_HOST;
1289         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1290                 skb->pkt_type = PACKET_BROADCAST;
1291         else
1292                 skb->pkt_type = PACKET_MULTICAST;
1293
1294         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1295          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1296          */
1297
1298         skb_pull(skb, MLX5_IB_GRH_BYTES);
1299
1300         skb->protocol = *((__be16 *)(skb->data));
1301
1302         skb->ip_summed = CHECKSUM_COMPLETE;
1303         skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1304
1305         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1306                 skb_hwtstamps(skb)->hwtstamp =
1307                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1308
1309         skb_record_rx_queue(skb, rq->ix);
1310
1311         if (likely(netdev->features & NETIF_F_RXHASH))
1312                 mlx5e_skb_set_hash(cqe, skb);
1313
1314         /* 20 bytes of ipoib header and 4 for encap existing */
1315         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1316         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1317         skb_reset_mac_header(skb);
1318         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1319
1320         skb->dev = netdev;
1321
1322         rq->stats.csum_complete++;
1323         rq->stats.packets++;
1324         rq->stats.bytes += cqe_bcnt;
1325 }
1326
1327 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1328 {
1329         struct mlx5e_wqe_frag_info *wi;
1330         struct mlx5e_rx_wqe *wqe;
1331         __be16 wqe_counter_be;
1332         struct sk_buff *skb;
1333         u16 wqe_counter;
1334         u32 cqe_bcnt;
1335
1336         wqe_counter_be = cqe->wqe_counter;
1337         wqe_counter    = be16_to_cpu(wqe_counter_be);
1338         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1339         wi             = &rq->wqe.frag_info[wqe_counter];
1340         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1341
1342         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1343         if (!skb)
1344                 goto wq_free_wqe;
1345
1346         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1347         if (unlikely(!skb->dev)) {
1348                 dev_kfree_skb_any(skb);
1349                 goto wq_free_wqe;
1350         }
1351         napi_gro_receive(rq->cq.napi, skb);
1352
1353 wq_free_wqe:
1354         mlx5e_free_rx_wqe_reuse(rq, wi);
1355         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1356                        &wqe->next.next_wqe_index);
1357 }
1358
1359 #endif /* CONFIG_MLX5_CORE_IPOIB */
1360
1361 #ifdef CONFIG_MLX5_EN_IPSEC
1362
1363 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1364 {
1365         struct mlx5e_wqe_frag_info *wi;
1366         struct mlx5e_rx_wqe *wqe;
1367         __be16 wqe_counter_be;
1368         struct sk_buff *skb;
1369         u16 wqe_counter;
1370         u32 cqe_bcnt;
1371
1372         wqe_counter_be = cqe->wqe_counter;
1373         wqe_counter    = be16_to_cpu(wqe_counter_be);
1374         wqe            = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
1375         wi             = &rq->wqe.frag_info[wqe_counter];
1376         cqe_bcnt       = be32_to_cpu(cqe->byte_cnt);
1377
1378         skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1379         if (unlikely(!skb)) {
1380                 /* a DROP, save the page-reuse checks */
1381                 mlx5e_free_rx_wqe(rq, wi);
1382                 goto wq_ll_pop;
1383         }
1384         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb);
1385         if (unlikely(!skb)) {
1386                 mlx5e_free_rx_wqe(rq, wi);
1387                 goto wq_ll_pop;
1388         }
1389
1390         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1391         napi_gro_receive(rq->cq.napi, skb);
1392
1393         mlx5e_free_rx_wqe_reuse(rq, wi);
1394 wq_ll_pop:
1395         mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
1396                        &wqe->next.next_wqe_index);
1397 }
1398
1399 #endif /* CONFIG_MLX5_EN_IPSEC */