2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/ipv6.h>
35 #include <linux/tcp.h>
36 #include <net/busy_poll.h>
41 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp)
43 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
46 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc,
49 u32 ci = cqcc & cq->wq.sz_m1;
51 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64));
54 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
55 struct mlx5e_cq *cq, u32 cqcc)
57 mlx5e_read_cqe_slot(cq, cqcc, &cq->title);
58 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt);
59 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter);
60 rq->stats.cqe_compress_blks++;
63 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc)
65 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr);
69 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n)
71 u8 op_own = (cqcc >> cq->wq.log_sz) & 1;
72 u32 wq_sz = 1 << cq->wq.log_sz;
73 u32 ci = cqcc & cq->wq.sz_m1;
74 u32 ci_top = min_t(u32, wq_sz, ci + n);
76 for (; ci < ci_top; ci++, n--) {
77 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
82 if (unlikely(ci == wq_sz)) {
84 for (ci = 0; ci < n; ci++) {
85 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci);
92 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
93 struct mlx5e_cq *cq, u32 cqcc)
97 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt;
98 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum;
99 cq->title.op_own &= 0xf0;
100 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz);
101 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter);
104 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
105 mpwrq_get_cqe_consumed_strides(&cq->title) : 1;
106 cq->decmprs_wqe_counter =
107 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1;
110 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
111 struct mlx5e_cq *cq, u32 cqcc)
113 mlx5e_decompress_cqe(rq, cq, cqcc);
114 cq->title.rss_hash_type = 0;
115 cq->title.rss_hash_result = 0;
118 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
120 int update_owner_only,
123 u32 cqcc = cq->wq.cc + update_owner_only;
127 cqe_count = min_t(u32, cq->decmprs_left, budget_rem);
129 for (i = update_owner_only; i < cqe_count;
130 i++, cq->mini_arr_idx++, cqcc++) {
131 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
132 mlx5e_read_mini_arr_slot(cq, cqcc);
134 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc);
135 rq->handle_rx_cqe(rq, &cq->title);
137 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc);
139 cq->decmprs_left -= cqe_count;
140 rq->stats.cqe_compress_pkts += cqe_count;
145 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
149 mlx5e_read_title_slot(rq, cq, cq->wq.cc);
150 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1);
151 mlx5e_decompress_cqe(rq, cq, cq->wq.cc);
152 rq->handle_rx_cqe(rq, &cq->title);
155 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1;
158 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val)
162 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
165 mutex_lock(&priv->state_lock);
167 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) == val)
170 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
172 mlx5e_close_locked(priv->netdev);
174 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, val);
177 mlx5e_open_locked(priv->netdev);
180 mutex_unlock(&priv->state_lock);
183 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
185 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
186 struct mlx5e_dma_info *dma_info)
188 struct mlx5e_page_cache *cache = &rq->page_cache;
189 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
191 if (tail_next == cache->head) {
192 rq->stats.cache_full++;
196 if (unlikely(page_is_pfmemalloc(dma_info->page)))
199 cache->page_cache[cache->tail] = *dma_info;
200 cache->tail = tail_next;
204 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
205 struct mlx5e_dma_info *dma_info)
207 struct mlx5e_page_cache *cache = &rq->page_cache;
209 if (unlikely(cache->head == cache->tail)) {
210 rq->stats.cache_empty++;
214 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
215 rq->stats.cache_busy++;
219 *dma_info = cache->page_cache[cache->head];
220 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
221 rq->stats.cache_reuse++;
223 dma_sync_single_for_device(rq->pdev, dma_info->addr,
229 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
230 struct mlx5e_dma_info *dma_info)
234 if (mlx5e_rx_cache_get(rq, dma_info))
237 page = dev_alloc_pages(rq->buff.page_order);
241 dma_info->page = page;
242 dma_info->addr = dma_map_page(rq->pdev, page, 0,
243 RQ_PAGE_SIZE(rq), rq->buff.map_dir);
244 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
252 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
255 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info))
258 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq),
260 put_page(dma_info->page);
263 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
265 struct mlx5e_dma_info *di = &rq->dma_info[ix];
267 if (unlikely(mlx5e_page_alloc_mapped(rq, di)))
270 wqe->data.addr = cpu_to_be64(di->addr + MLX5_RX_HEADROOM);
274 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
276 struct mlx5e_dma_info *di = &rq->dma_info[ix];
278 mlx5e_page_release(rq, di, true);
281 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq)
283 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER;
286 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq,
288 struct mlx5e_mpw_info *wi,
289 u32 page_idx, u32 frag_offset,
292 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz);
294 dma_sync_single_for_cpu(rq->pdev,
295 wi->umr.dma_info[page_idx].addr + frag_offset,
296 len, DMA_FROM_DEVICE);
297 wi->skbs_frags[page_idx]++;
298 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
299 wi->umr.dma_info[page_idx].page, frag_offset,
304 mlx5e_copy_skb_header_mpwqe(struct device *pdev,
306 struct mlx5e_mpw_info *wi,
307 u32 page_idx, u32 offset,
310 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset);
311 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx];
314 /* Aligning len to sizeof(long) optimizes memcpy performance */
315 len = ALIGN(headlen_pg, sizeof(long));
316 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len,
318 skb_copy_to_linear_data_offset(skb, 0,
319 page_address(dma_info->page) + offset,
321 if (unlikely(offset + headlen > PAGE_SIZE)) {
324 len = ALIGN(headlen - headlen_pg, sizeof(long));
325 dma_sync_single_for_cpu(pdev, dma_info->addr, len,
327 skb_copy_to_linear_data_offset(skb, headlen_pg,
328 page_address(dma_info->page),
333 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix)
335 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
336 struct mlx5e_sq *sq = &rq->channel->icosq;
337 struct mlx5_wq_cyc *wq = &sq->wq;
338 struct mlx5e_umr_wqe *wqe;
339 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB);
342 /* fill sq edge with nops to avoid wqe wrap around */
343 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
344 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
345 sq->db.ico_wqe[pi].num_wqebbs = 1;
346 mlx5e_send_nop(sq, false);
349 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
350 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe));
351 wqe->ctrl.opmod_idx_opcode =
352 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
355 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
356 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs;
357 sq->pc += num_wqebbs;
358 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
361 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq,
362 struct mlx5e_rx_wqe *wqe,
365 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
366 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT;
367 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
371 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
372 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
374 err = mlx5e_page_alloc_mapped(rq, dma_info);
377 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
378 page_ref_add(dma_info->page, pg_strides);
379 wi->skbs_frags[i] = 0;
382 wi->consumed_strides = 0;
383 wqe->data.addr = cpu_to_be64(dma_offset);
389 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
391 page_ref_sub(dma_info->page, pg_strides);
392 mlx5e_page_release(rq, dma_info, true);
398 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi)
400 int pg_strides = mlx5e_mpwqe_strides_per_page(rq);
403 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) {
404 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i];
406 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]);
407 mlx5e_page_release(rq, dma_info, true);
411 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq)
413 struct mlx5_wq_ll *wq = &rq->wq;
414 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
416 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
418 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) {
419 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
423 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
425 /* ensure wqes are visible to device before updating doorbell record */
428 mlx5_wq_ll_update_db_record(wq);
431 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix)
435 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix);
438 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state);
439 mlx5e_post_umr_wqe(rq, ix);
443 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
445 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
447 mlx5e_free_rx_mpwqe(rq, wi);
450 #define RQ_CANNOT_POST(rq) \
451 (!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state) || \
452 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
454 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
456 struct mlx5_wq_ll *wq = &rq->wq;
458 if (unlikely(RQ_CANNOT_POST(rq)))
461 while (!mlx5_wq_ll_is_full(wq)) {
462 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head);
465 err = rq->alloc_wqe(rq, wqe, wq->head);
469 rq->stats.buff_alloc_err++;
473 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index));
476 /* ensure wqes are visible to device before updating doorbell record */
479 mlx5_wq_ll_update_db_record(wq);
481 return !mlx5_wq_ll_is_full(wq);
484 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
487 struct ethhdr *eth = (struct ethhdr *)(skb->data);
489 struct ipv6hdr *ipv6;
491 int network_depth = 0;
495 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
496 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) ||
497 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type));
499 skb->mac_len = ETH_HLEN;
500 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
502 ipv4 = (struct iphdr *)(skb->data + network_depth);
503 ipv6 = (struct ipv6hdr *)(skb->data + network_depth);
504 tot_len = cqe_bcnt - network_depth;
506 if (proto == htons(ETH_P_IP)) {
507 tcp = (struct tcphdr *)(skb->data + network_depth +
508 sizeof(struct iphdr));
510 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
512 tcp = (struct tcphdr *)(skb->data + network_depth +
513 sizeof(struct ipv6hdr));
515 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
518 if (get_cqe_lro_tcppsh(cqe))
523 tcp->ack_seq = cqe->lro_ack_seq_num;
524 tcp->window = cqe->lro_tcp_win;
528 ipv4->ttl = cqe->lro_min_ttl;
529 ipv4->tot_len = cpu_to_be16(tot_len);
531 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
534 ipv6->hop_limit = cqe->lro_min_ttl;
535 ipv6->payload_len = cpu_to_be16(tot_len -
536 sizeof(struct ipv6hdr));
540 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
543 u8 cht = cqe->rss_hash_type;
544 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
545 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
547 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
550 static inline bool is_first_ethertype_ip(struct sk_buff *skb)
552 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto;
554 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6));
557 static inline void mlx5e_handle_csum(struct net_device *netdev,
558 struct mlx5_cqe64 *cqe,
563 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
567 skb->ip_summed = CHECKSUM_UNNECESSARY;
571 if (is_first_ethertype_ip(skb)) {
572 skb->ip_summed = CHECKSUM_COMPLETE;
573 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
574 rq->stats.csum_complete++;
578 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
579 (cqe->hds_ip_ext & CQE_L4_OK))) {
580 skb->ip_summed = CHECKSUM_UNNECESSARY;
581 if (cqe_is_tunneled(cqe)) {
583 skb->encapsulation = 1;
584 rq->stats.csum_unnecessary_inner++;
589 skb->ip_summed = CHECKSUM_NONE;
590 rq->stats.csum_none++;
593 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
598 struct net_device *netdev = rq->netdev;
599 struct mlx5e_tstamp *tstamp = rq->tstamp;
602 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
603 if (lro_num_seg > 1) {
604 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
605 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
606 rq->stats.lro_packets++;
607 rq->stats.lro_bytes += cqe_bcnt;
610 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
611 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb));
613 skb_record_rx_queue(skb, rq->ix);
615 if (likely(netdev->features & NETIF_F_RXHASH))
616 mlx5e_skb_set_hash(cqe, skb);
618 if (cqe_has_vlan(cqe))
619 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
620 be16_to_cpu(cqe->vlan_info));
622 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
624 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
625 skb->protocol = eth_type_trans(skb, netdev);
628 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
629 struct mlx5_cqe64 *cqe,
634 rq->stats.bytes += cqe_bcnt;
635 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
638 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_sq *sq)
640 struct mlx5_wq_cyc *wq = &sq->wq;
641 struct mlx5e_tx_wqe *wqe;
642 u16 pi = (sq->pc - MLX5E_XDP_TX_WQEBBS) & wq->sz_m1; /* last pi */
644 wqe = mlx5_wq_cyc_get_wqe(wq, pi);
646 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
647 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
650 static inline void mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq,
651 struct mlx5e_dma_info *di,
652 unsigned int data_offset,
655 struct mlx5e_sq *sq = &rq->channel->xdp_sq;
656 struct mlx5_wq_cyc *wq = &sq->wq;
657 u16 pi = sq->pc & wq->sz_m1;
658 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
659 struct mlx5e_sq_wqe_info *wi = &sq->db.xdp.wqe_info[pi];
661 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
662 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
663 struct mlx5_wqe_data_seg *dseg;
665 dma_addr_t dma_addr = di->addr + data_offset + MLX5E_XDP_MIN_INLINE;
666 unsigned int dma_len = len - MLX5E_XDP_MIN_INLINE;
667 void *data = page_address(di->page) + data_offset;
669 if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_XDP_TX_WQEBBS))) {
670 if (sq->db.xdp.doorbell) {
671 /* SQ is full, ring doorbell */
672 mlx5e_xmit_xdp_doorbell(sq);
673 sq->db.xdp.doorbell = false;
675 rq->stats.xdp_tx_full++;
676 mlx5e_page_release(rq, di, true);
680 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len,
683 memset(wqe, 0, sizeof(*wqe));
685 /* copy the inline part */
686 memcpy(eseg->inline_hdr_start, data, MLX5E_XDP_MIN_INLINE);
687 eseg->inline_hdr_sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE);
689 dseg = (struct mlx5_wqe_data_seg *)cseg + (MLX5E_XDP_TX_DS_COUNT - 1);
691 /* write the dma part */
692 dseg->addr = cpu_to_be64(dma_addr);
693 dseg->byte_count = cpu_to_be32(dma_len);
694 dseg->lkey = sq->mkey_be;
696 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND);
697 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | MLX5E_XDP_TX_DS_COUNT);
699 sq->db.xdp.di[pi] = *di;
700 wi->opcode = MLX5_OPCODE_SEND;
701 wi->num_wqebbs = MLX5E_XDP_TX_WQEBBS;
702 sq->pc += MLX5E_XDP_TX_WQEBBS;
704 sq->db.xdp.doorbell = true;
708 /* returns true if packet was consumed by xdp */
709 static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq,
710 const struct bpf_prog *prog,
711 struct mlx5e_dma_info *di,
721 xdp.data_end = xdp.data + len;
722 act = bpf_prog_run_xdp(prog, &xdp);
727 mlx5e_xmit_xdp_frame(rq, di, MLX5_RX_HEADROOM, len);
730 bpf_warn_invalid_xdp_action(act);
733 rq->stats.xdp_drop++;
734 mlx5e_page_release(rq, di, true);
740 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
741 u16 wqe_counter, u32 cqe_bcnt)
743 struct mlx5e_dma_info *di;
748 di = &rq->dma_info[wqe_counter];
749 va = page_address(di->page);
750 data = va + MLX5_RX_HEADROOM;
752 dma_sync_single_range_for_cpu(rq->pdev,
759 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
761 mlx5e_page_release(rq, di, true);
766 consumed = mlx5e_xdp_handle(rq, READ_ONCE(rq->xdp_prog), di, data,
770 return NULL; /* page/packet was consumed by XDP */
772 skb = build_skb(va, RQ_PAGE_SIZE(rq));
773 if (unlikely(!skb)) {
774 rq->stats.buff_alloc_err++;
775 mlx5e_page_release(rq, di, true);
779 /* queue up for recycling ..*/
780 page_ref_inc(di->page);
781 mlx5e_page_release(rq, di, true);
783 skb_reserve(skb, MLX5_RX_HEADROOM);
784 skb_put(skb, cqe_bcnt);
789 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
791 struct mlx5e_rx_wqe *wqe;
792 __be16 wqe_counter_be;
797 wqe_counter_be = cqe->wqe_counter;
798 wqe_counter = be16_to_cpu(wqe_counter_be);
799 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
800 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
802 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
806 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
807 napi_gro_receive(rq->cq.napi, skb);
810 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
811 &wqe->next.next_wqe_index);
814 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
816 struct net_device *netdev = rq->netdev;
817 struct mlx5e_priv *priv = netdev_priv(netdev);
818 struct mlx5_eswitch_rep *rep = priv->ppriv;
819 struct mlx5e_rx_wqe *wqe;
821 __be16 wqe_counter_be;
825 wqe_counter_be = cqe->wqe_counter;
826 wqe_counter = be16_to_cpu(wqe_counter_be);
827 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter);
828 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
830 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt);
834 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
836 if (rep->vlan && skb_vlan_tag_present(skb))
839 napi_gro_receive(rq->cq.napi, skb);
842 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be,
843 &wqe->next.next_wqe_index);
846 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq,
847 struct mlx5_cqe64 *cqe,
848 struct mlx5e_mpw_info *wi,
852 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
853 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz;
854 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
855 u32 page_idx = wqe_offset >> PAGE_SHIFT;
856 u32 head_page_idx = page_idx;
857 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt);
858 u32 frag_offset = head_offset + headlen;
859 u16 byte_cnt = cqe_bcnt - headlen;
861 if (unlikely(frag_offset >= PAGE_SIZE)) {
863 frag_offset -= PAGE_SIZE;
867 u32 pg_consumed_bytes =
868 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
870 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset,
872 byte_cnt -= pg_consumed_bytes;
877 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx,
878 head_offset, headlen);
879 /* skb linear part was allocated with headlen and aligned to long */
880 skb->tail += headlen;
884 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
886 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
887 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
888 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
889 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id);
893 wi->consumed_strides += cstrides;
895 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {
900 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
901 rq->stats.mpwqe_filler++;
905 skb = napi_alloc_skb(rq->cq.napi,
906 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD,
908 if (unlikely(!skb)) {
909 rq->stats.buff_alloc_err++;
914 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
916 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb);
917 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
918 napi_gro_receive(rq->cq.napi, skb);
921 if (likely(wi->consumed_strides < rq->mpwqe_num_strides))
924 mlx5e_free_rx_mpwqe(rq, wi);
925 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index);
928 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
930 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
931 struct mlx5e_sq *xdp_sq = &rq->channel->xdp_sq;
934 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
937 if (cq->decmprs_left)
938 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget);
940 for (; work_done < budget; work_done++) {
941 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq);
946 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
948 mlx5e_decompress_cqes_start(rq, cq,
953 mlx5_cqwq_pop(&cq->wq);
955 rq->handle_rx_cqe(rq, cqe);
958 if (xdp_sq->db.xdp.doorbell) {
959 mlx5e_xmit_xdp_doorbell(xdp_sq);
960 xdp_sq->db.xdp.doorbell = false;
963 mlx5_cqwq_update_db_record(&cq->wq);
965 /* ensure cq space is freed before enabling more cqes */