drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/sch_generic.h>
  35 #include <net/pkt_cls.h>
  36 #include <net/tc_act/tc_gact.h>
  37 #include <net/tc_act/tc_skbedit.h>
  38 #include <linux/mlx5/fs.h>
  39 #include <linux/mlx5/device.h>
  40 #include <linux/rhashtable.h>
  41 #include <linux/refcount.h>
  42 #include <linux/completion.h>
  43 #include <net/tc_act/tc_mirred.h>
  44 #include <net/tc_act/tc_vlan.h>
  45 #include <net/tc_act/tc_tunnel_key.h>
  46 #include <net/tc_act/tc_pedit.h>
  47 #include <net/tc_act/tc_csum.h>
  48 #include <net/arp.h>
  49 #include <net/ipv6_stubs.h>
  50 #include "en.h"
  51 #include "en_rep.h"
  52 #include "en_tc.h"
  53 #include "eswitch.h"
  54 #include "fs_core.h"
  55 #include "en/port.h"
  56 #include "en/tc_tun.h"
  57 #include "lib/devcom.h"
  58 #include "lib/geneve.h"
  59
  60 struct mlx5_nic_flow_attr {
  61         u32 action;
  62         u32 flow_tag;
  63         u32 mod_hdr_id;
  64         u32 hairpin_tirn;
  65         u8 match_level;
  66         struct mlx5_flow_table  *hairpin_ft;
  67         struct mlx5_fc          *counter;
  68 };
  69
  70 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
  71
  72 enum {
  73         MLX5E_TC_FLOW_FLAG_INGRESS      = MLX5E_TC_FLAG_INGRESS_BIT,
  74         MLX5E_TC_FLOW_FLAG_EGRESS       = MLX5E_TC_FLAG_EGRESS_BIT,
  75         MLX5E_TC_FLOW_FLAG_ESWITCH      = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
  76         MLX5E_TC_FLOW_FLAG_NIC          = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
  77         MLX5E_TC_FLOW_FLAG_OFFLOADED    = MLX5E_TC_FLOW_BASE,
  78         MLX5E_TC_FLOW_FLAG_HAIRPIN      = MLX5E_TC_FLOW_BASE + 1,
  79         MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS  = MLX5E_TC_FLOW_BASE + 2,
  80         MLX5E_TC_FLOW_FLAG_SLOW         = MLX5E_TC_FLOW_BASE + 3,
  81         MLX5E_TC_FLOW_FLAG_DUP          = MLX5E_TC_FLOW_BASE + 4,
  82         MLX5E_TC_FLOW_FLAG_NOT_READY    = MLX5E_TC_FLOW_BASE + 5,
  83         MLX5E_TC_FLOW_FLAG_DELETED      = MLX5E_TC_FLOW_BASE + 6,
  84 };
  85
  86 #define MLX5E_TC_MAX_SPLITS 1
  87
  88 /* Helper struct for accessing a struct containing list_head array.
  89  * Containing struct
  90  *   |- Helper array
  91  *      [0] Helper item 0
  92  *          |- list_head item 0
  93  *          |- index (0)
  94  *      [1] Helper item 1
  95  *          |- list_head item 1
  96  *          |- index (1)
  97  * To access the containing struct from one of the list_head items:
  98  * 1. Get the helper item from the list_head item using
  99  *    helper item =
 100  *        container_of(list_head item, helper struct type, list_head field)
 101  * 2. Get the contining struct from the helper item and its index in the array:
 102  *    containing struct =
 103  *        container_of(helper item, containing struct type, helper field[index])
 104  */
 105 struct encap_flow_item {
 106         struct mlx5e_encap_entry *e; /* attached encap instance */
 107         struct list_head list;
 108         int index;
 109 };
 110
 111 struct mlx5e_tc_flow {
 112         struct rhash_head       node;
 113         struct mlx5e_priv       *priv;
 114         u64                     cookie;
 115         unsigned long           flags;
 116         struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
 117         /* Flow can be associated with multiple encap IDs.
 118          * The number of encaps is bounded by the number of supported
 119          * destinations.
 120          */
 121         struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
 122         struct mlx5e_tc_flow    *peer_flow;
 123         struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
 124         struct list_head        mod_hdr; /* flows sharing the same mod hdr ID */
 125         struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
 126         struct list_head        hairpin; /* flows sharing the same hairpin */
 127         struct list_head        peer;    /* flows with peer flow */
 128         struct list_head        unready; /* flows not ready to be offloaded (e.g due to missing route) */
 129         refcount_t              refcnt;
 130         struct rcu_head         rcu_head;
 131         union {
 132                 struct mlx5_esw_flow_attr esw_attr[0];
 133                 struct mlx5_nic_flow_attr nic_attr[0];
 134         };
 135 };
 136
 137 struct mlx5e_tc_flow_parse_attr {
 138         const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
 139         struct net_device *filter_dev;
 140         struct mlx5_flow_spec spec;
 141         int num_mod_hdr_actions;
 142         int max_mod_hdr_actions;
 143         void *mod_hdr_actions;
 144         int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
 145 };
 146
 147 #define MLX5E_TC_TABLE_NUM_GROUPS 4
 148 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
 149
 150 struct mlx5e_hairpin {
 151         struct mlx5_hairpin *pair;
 152
 153         struct mlx5_core_dev *func_mdev;
 154         struct mlx5e_priv *func_priv;
 155         u32 tdn;
 156         u32 tirn;
 157
 158         int num_channels;
 159         struct mlx5e_rqt indir_rqt;
 160         u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
 161         struct mlx5e_ttc_table ttc;
 162 };
 163
 164 struct mlx5e_hairpin_entry {
 165         /* a node of a hash table which keeps all the  hairpin entries */
 166         struct hlist_node hairpin_hlist;
 167
 168         /* protects flows list */
 169         spinlock_t flows_lock;
 170         /* flows sharing the same hairpin */
 171         struct list_head flows;
 172         /* hpe's that were not fully initialized when dead peer update event
 173          * function traversed them.
 174          */
 175         struct list_head dead_peer_wait_list;
 176
 177         u16 peer_vhca_id;
 178         u8 prio;
 179         struct mlx5e_hairpin *hp;
 180         refcount_t refcnt;
 181         struct completion res_ready;
 182 };
 183
 184 struct mod_hdr_key {
 185         int num_actions;
 186         void *actions;
 187 };
 188
 189 struct mlx5e_mod_hdr_entry {
 190         /* a node of a hash table which keeps all the mod_hdr entries */
 191         struct hlist_node mod_hdr_hlist;
 192
 193         /* protects flows list */
 194         spinlock_t flows_lock;
 195         /* flows sharing the same mod_hdr entry */
 196         struct list_head flows;
 197
 198         struct mod_hdr_key key;
 199
 200         u32 mod_hdr_id;
 201
 202         refcount_t refcnt;
 203         struct completion res_ready;
 204         int compl_result;
 205 };
 206
 207 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
 208
 209 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 210                               struct mlx5e_tc_flow *flow);
 211
 212 static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 213 {
 214         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 215                 return ERR_PTR(-EINVAL);
 216         return flow;
 217 }
 218
 219 static void mlx5e_flow_put(struct mlx5e_priv *priv,
 220                            struct mlx5e_tc_flow *flow)
 221 {
 222         if (refcount_dec_and_test(&flow->refcnt)) {
 223                 mlx5e_tc_del_flow(priv, flow);
 224                 kfree_rcu(flow, rcu_head);
 225         }
 226 }
 227
 228 static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
 229 {
 230         /* Complete all memory stores before setting bit. */
 231         smp_mb__before_atomic();
 232         set_bit(flag, &flow->flags);
 233 }
 234
 235 #define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
 236
 237 static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
 238                                      unsigned long flag)
 239 {
 240         /* test_and_set_bit() provides all necessary barriers */
 241         return test_and_set_bit(flag, &flow->flags);
 242 }
 243
 244 #define flow_flag_test_and_set(flow, flag)                      \
 245         __flow_flag_test_and_set(flow,                          \
 246                                  MLX5E_TC_FLOW_FLAG_##flag)
 247
 248 static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
 249 {
 250         /* Complete all memory stores before clearing bit. */
 251         smp_mb__before_atomic();
 252         clear_bit(flag, &flow->flags);
 253 }
 254
 255 #define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
 256                                                       MLX5E_TC_FLOW_FLAG_##flag)
 257
 258 static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
 259 {
 260         bool ret = test_bit(flag, &flow->flags);
 261
 262         /* Read fields of flow structure only after checking flags. */
 263         smp_mb__after_atomic();
 264         return ret;
 265 }
 266
 267 #define flow_flag_test(flow, flag) __flow_flag_test(flow, \
 268                                                     MLX5E_TC_FLOW_FLAG_##flag)
 269
 270 static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 271 {
 272         return flow_flag_test(flow, ESWITCH);
 273 }
 274
 275 static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 276 {
 277         return flow_flag_test(flow, OFFLOADED);
 278 }
 279
 280 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
 281 {
 282         return jhash(key->actions,
 283                      key->num_actions * MLX5_MH_ACT_SZ, 0);
 284 }
 285
 286 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
 287                                    struct mod_hdr_key *b)
 288 {
 289         if (a->num_actions != b->num_actions)
 290                 return 1;
 291
 292         return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
 293 }
 294
 295 static struct mod_hdr_tbl *
 296 get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
 297 {
 298         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 299
 300         return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
 301                 &priv->fs.tc.mod_hdr;
 302 }
 303
 304 static struct mlx5e_mod_hdr_entry *
 305 mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
 306 {
 307         struct mlx5e_mod_hdr_entry *mh, *found = NULL;
 308
 309         hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
 310                 if (!cmp_mod_hdr_info(&mh->key, key)) {
 311                         refcount_inc(&mh->refcnt);
 312                         found = mh;
 313                         break;
 314                 }
 315         }
 316
 317         return found;
 318 }
 319
 320 static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
 321                               struct mlx5e_mod_hdr_entry *mh,
 322                               int namespace)
 323 {
 324         struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
 325
 326         if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
 327                 return;
 328         hash_del(&mh->mod_hdr_hlist);
 329         mutex_unlock(&tbl->lock);
 330
 331         WARN_ON(!list_empty(&mh->flows));
 332         if (mh->compl_result > 0)
 333                 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
 334
 335         kfree(mh);
 336 }
 337
 338 static int get_flow_name_space(struct mlx5e_tc_flow *flow)
 339 {
 340         return mlx5e_is_eswitch_flow(flow) ?
 341                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 342 }
 343 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
 344                                 struct mlx5e_tc_flow *flow,
 345                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
 346 {
 347         int num_actions, actions_size, namespace, err;
 348         struct mlx5e_mod_hdr_entry *mh;
 349         struct mod_hdr_tbl *tbl;
 350         struct mod_hdr_key key;
 351         u32 hash_key;
 352
 353         num_actions  = parse_attr->num_mod_hdr_actions;
 354         actions_size = MLX5_MH_ACT_SZ * num_actions;
 355
 356         key.actions = parse_attr->mod_hdr_actions;
 357         key.num_actions = num_actions;
 358
 359         hash_key = hash_mod_hdr_info(&key);
 360
 361         namespace = get_flow_name_space(flow);
 362         tbl = get_mod_hdr_table(priv, namespace);
 363
 364         mutex_lock(&tbl->lock);
 365         mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
 366         if (mh) {
 367                 mutex_unlock(&tbl->lock);
 368                 wait_for_completion(&mh->res_ready);
 369
 370                 if (mh->compl_result < 0) {
 371                         err = -EREMOTEIO;
 372                         goto attach_header_err;
 373                 }
 374                 goto attach_flow;
 375         }
 376
 377         mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
 378         if (!mh) {
 379                 mutex_unlock(&tbl->lock);
 380                 return -ENOMEM;
 381         }
 382
 383         mh->key.actions = (void *)mh + sizeof(*mh);
 384         memcpy(mh->key.actions, key.actions, actions_size);
 385         mh->key.num_actions = num_actions;
 386         spin_lock_init(&mh->flows_lock);
 387         INIT_LIST_HEAD(&mh->flows);
 388         refcount_set(&mh->refcnt, 1);
 389         init_completion(&mh->res_ready);
 390
 391         hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
 392         mutex_unlock(&tbl->lock);
 393
 394         err = mlx5_modify_header_alloc(priv->mdev, namespace,
 395                                        mh->key.num_actions,
 396                                        mh->key.actions,
 397                                        &mh->mod_hdr_id);
 398         if (err) {
 399                 mh->compl_result = err;
 400                 goto alloc_header_err;
 401         }
 402         mh->compl_result = 1;
 403         complete_all(&mh->res_ready);
 404
 405 attach_flow:
 406         flow->mh = mh;
 407         spin_lock(&mh->flows_lock);
 408         list_add(&flow->mod_hdr, &mh->flows);
 409         spin_unlock(&mh->flows_lock);
 410         if (mlx5e_is_eswitch_flow(flow))
 411                 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
 412         else
 413                 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
 414
 415         return 0;
 416
 417 alloc_header_err:
 418         complete_all(&mh->res_ready);
 419 attach_header_err:
 420         mlx5e_mod_hdr_put(priv, mh, namespace);
 421         return err;
 422 }
 423
 424 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
 425                                  struct mlx5e_tc_flow *flow)
 426 {
 427         /* flow wasn't fully initialized */
 428         if (!flow->mh)
 429                 return;
 430
 431         spin_lock(&flow->mh->flows_lock);
 432         list_del(&flow->mod_hdr);
 433         spin_unlock(&flow->mh->flows_lock);
 434
 435         mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
 436         flow->mh = NULL;
 437 }
 438
 439 static
 440 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 441 {
 442         struct net_device *netdev;
 443         struct mlx5e_priv *priv;
 444
 445         netdev = __dev_get_by_index(net, ifindex);
 446         priv = netdev_priv(netdev);
 447         return priv->mdev;
 448 }
 449
 450 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 451 {
 452         u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 453         void *tirc;
 454         int err;
 455
 456         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 457         if (err)
 458                 goto alloc_tdn_err;
 459
 460         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 461
 462         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
 463         MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
 464         MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 465
 466         err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
 467         if (err)
 468                 goto create_tir_err;
 469
 470         return 0;
 471
 472 create_tir_err:
 473         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 474 alloc_tdn_err:
 475         return err;
 476 }
 477
 478 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 479 {
 480         mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
 481         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 482 }
 483
 484 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
 485 {
 486         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
 487         struct mlx5e_priv *priv = hp->func_priv;
 488         int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
 489
 490         mlx5e_build_default_indir_rqt(indirection_rqt, sz,
 491                                       hp->num_channels);
 492
 493         for (i = 0; i < sz; i++) {
 494                 ix = i;
 495                 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
 496                         ix = mlx5e_bits_invert(i, ilog2(sz));
 497                 ix = indirection_rqt[ix];
 498                 rqn = hp->pair->rqn[ix];
 499                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
 500         }
 501 }
 502
 503 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 504 {
 505         int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
 506         struct mlx5e_priv *priv = hp->func_priv;
 507         struct mlx5_core_dev *mdev = priv->mdev;
 508         void *rqtc;
 509         u32 *in;
 510
 511         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
 512         in = kvzalloc(inlen, GFP_KERNEL);
 513         if (!in)
 514                 return -ENOMEM;
 515
 516         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 517
 518         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
 519         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
 520
 521         mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
 522
 523         err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
 524         if (!err)
 525                 hp->indir_rqt.enabled = true;
 526
 527         kvfree(in);
 528         return err;
 529 }
 530
 531 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 532 {
 533         struct mlx5e_priv *priv = hp->func_priv;
 534         u32 in[MLX5_ST_SZ_DW(create_tir_in)];
 535         int tt, i, err;
 536         void *tirc;
 537
 538         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 539                 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
 540
 541                 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
 542                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 543
 544                 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 545                 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
 546                 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
 547                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
 548
 549                 err = mlx5_core_create_tir(hp->func_mdev, in,
 550                                            MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
 551                 if (err) {
 552                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 553                         goto err_destroy_tirs;
 554                 }
 555         }
 556         return 0;
 557
 558 err_destroy_tirs:
 559         for (i = 0; i < tt; i++)
 560                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
 561         return err;
 562 }
 563
 564 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 565 {
 566         int tt;
 567
 568         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 569                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
 570 }
 571
 572 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 573                                          struct ttc_params *ttc_params)
 574 {
 575         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 576         int tt;
 577
 578         memset(ttc_params, 0, sizeof(*ttc_params));
 579
 580         ttc_params->any_tt_tirn = hp->tirn;
 581
 582         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 583                 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
 584
 585         ft_attr->max_fte = MLX5E_NUM_TT;
 586         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 587         ft_attr->prio = MLX5E_TC_PRIO;
 588 }
 589
 590 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 591 {
 592         struct mlx5e_priv *priv = hp->func_priv;
 593         struct ttc_params ttc_params;
 594         int err;
 595
 596         err = mlx5e_hairpin_create_indirect_rqt(hp);
 597         if (err)
 598                 return err;
 599
 600         err = mlx5e_hairpin_create_indirect_tirs(hp);
 601         if (err)
 602                 goto err_create_indirect_tirs;
 603
 604         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 605         err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
 606         if (err)
 607                 goto err_create_ttc_table;
 608
 609         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 610                    hp->num_channels, hp->ttc.ft.t->id);
 611
 612         return 0;
 613
 614 err_create_ttc_table:
 615         mlx5e_hairpin_destroy_indirect_tirs(hp);
 616 err_create_indirect_tirs:
 617         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 618
 619         return err;
 620 }
 621
 622 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 623 {
 624         struct mlx5e_priv *priv = hp->func_priv;
 625
 626         mlx5e_destroy_ttc_table(priv, &hp->ttc);
 627         mlx5e_hairpin_destroy_indirect_tirs(hp);
 628         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 629 }
 630
 631 static struct mlx5e_hairpin *
 632 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 633                      int peer_ifindex)
 634 {
 635         struct mlx5_core_dev *func_mdev, *peer_mdev;
 636         struct mlx5e_hairpin *hp;
 637         struct mlx5_hairpin *pair;
 638         int err;
 639
 640         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 641         if (!hp)
 642                 return ERR_PTR(-ENOMEM);
 643
 644         func_mdev = priv->mdev;
 645         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 646
 647         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 648         if (IS_ERR(pair)) {
 649                 err = PTR_ERR(pair);
 650                 goto create_pair_err;
 651         }
 652         hp->pair = pair;
 653         hp->func_mdev = func_mdev;
 654         hp->func_priv = priv;
 655         hp->num_channels = params->num_channels;
 656
 657         err = mlx5e_hairpin_create_transport(hp);
 658         if (err)
 659                 goto create_transport_err;
 660
 661         if (hp->num_channels > 1) {
 662                 err = mlx5e_hairpin_rss_init(hp);
 663                 if (err)
 664                         goto rss_init_err;
 665         }
 666
 667         return hp;
 668
 669 rss_init_err:
 670         mlx5e_hairpin_destroy_transport(hp);
 671 create_transport_err:
 672         mlx5_core_hairpin_destroy(hp->pair);
 673 create_pair_err:
 674         kfree(hp);
 675         return ERR_PTR(err);
 676 }
 677
 678 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 679 {
 680         if (hp->num_channels > 1)
 681                 mlx5e_hairpin_rss_cleanup(hp);
 682         mlx5e_hairpin_destroy_transport(hp);
 683         mlx5_core_hairpin_destroy(hp->pair);
 684         kvfree(hp);
 685 }
 686
 687 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 688 {
 689         return (peer_vhca_id << 16 | prio);
 690 }
 691
 692 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 693                                                      u16 peer_vhca_id, u8 prio)
 694 {
 695         struct mlx5e_hairpin_entry *hpe;
 696         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 697
 698         hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
 699                                hairpin_hlist, hash_key) {
 700                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 701                         refcount_inc(&hpe->refcnt);
 702                         return hpe;
 703                 }
 704         }
 705
 706         return NULL;
 707 }
 708
 709 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 710                               struct mlx5e_hairpin_entry *hpe)
 711 {
 712         /* no more hairpin flows for us, release the hairpin pair */
 713         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
 714                 return;
 715         hash_del(&hpe->hairpin_hlist);
 716         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 717
 718         if (!IS_ERR_OR_NULL(hpe->hp)) {
 719                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 720                            dev_name(hpe->hp->pair->peer_mdev->device));
 721
 722                 mlx5e_hairpin_destroy(hpe->hp);
 723         }
 724
 725         WARN_ON(!list_empty(&hpe->flows));
 726         kfree(hpe);
 727 }
 728
 729 #define UNKNOWN_MATCH_PRIO 8
 730
 731 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 732                                   struct mlx5_flow_spec *spec, u8 *match_prio,
 733                                   struct netlink_ext_ack *extack)
 734 {
 735         void *headers_c, *headers_v;
 736         u8 prio_val, prio_mask = 0;
 737         bool vlan_present;
 738
 739 #ifdef CONFIG_MLX5_CORE_EN_DCB
 740         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
 741                 NL_SET_ERR_MSG_MOD(extack,
 742                                    "only PCP trust state supported for hairpin");
 743                 return -EOPNOTSUPP;
 744         }
 745 #endif
 746         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
 747         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
 748
 749         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
 750         if (vlan_present) {
 751                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
 752                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
 753         }
 754
 755         if (!vlan_present || !prio_mask) {
 756                 prio_val = UNKNOWN_MATCH_PRIO;
 757         } else if (prio_mask != 0x7) {
 758                 NL_SET_ERR_MSG_MOD(extack,
 759                                    "masked priority match not supported for hairpin");
 760                 return -EOPNOTSUPP;
 761         }
 762
 763         *match_prio = prio_val;
 764         return 0;
 765 }
 766
 767 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
 768                                   struct mlx5e_tc_flow *flow,
 769                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
 770                                   struct netlink_ext_ack *extack)
 771 {
 772         int peer_ifindex = parse_attr->mirred_ifindex[0];
 773         struct mlx5_hairpin_params params;
 774         struct mlx5_core_dev *peer_mdev;
 775         struct mlx5e_hairpin_entry *hpe;
 776         struct mlx5e_hairpin *hp;
 777         u64 link_speed64;
 778         u32 link_speed;
 779         u8 match_prio;
 780         u16 peer_id;
 781         int err;
 782
 783         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 784         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
 785                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
 786                 return -EOPNOTSUPP;
 787         }
 788
 789         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
 790         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
 791                                      extack);
 792         if (err)
 793                 return err;
 794
 795         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
 796         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
 797         if (hpe) {
 798                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 799                 wait_for_completion(&hpe->res_ready);
 800
 801                 if (IS_ERR(hpe->hp)) {
 802                         err = -EREMOTEIO;
 803                         goto out_err;
 804                 }
 805                 goto attach_flow;
 806         }
 807
 808         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
 809         if (!hpe) {
 810                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 811                 return -ENOMEM;
 812         }
 813
 814         spin_lock_init(&hpe->flows_lock);
 815         INIT_LIST_HEAD(&hpe->flows);
 816         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
 817         hpe->peer_vhca_id = peer_id;
 818         hpe->prio = match_prio;
 819         refcount_set(&hpe->refcnt, 1);
 820         init_completion(&hpe->res_ready);
 821
 822         hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
 823                  hash_hairpin_info(peer_id, match_prio));
 824         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 825
 826         params.log_data_size = 15;
 827         params.log_data_size = min_t(u8, params.log_data_size,
 828                                      MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
 829         params.log_data_size = max_t(u8, params.log_data_size,
 830                                      MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
 831
 832         params.log_num_packets = params.log_data_size -
 833                                  MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
 834         params.log_num_packets = min_t(u8, params.log_num_packets,
 835                                        MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
 836
 837         params.q_counter = priv->q_counter;
 838         /* set hairpin pair per each 50Gbs share of the link */
 839         mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
 840         link_speed = max_t(u32, link_speed, 50000);
 841         link_speed64 = link_speed;
 842         do_div(link_speed64, 50000);
 843         params.num_channels = link_speed64;
 844
 845         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
 846         hpe->hp = hp;
 847         complete_all(&hpe->res_ready);
 848         if (IS_ERR(hp)) {
 849                 err = PTR_ERR(hp);
 850                 goto out_err;
 851         }
 852
 853         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
 854                    hp->tirn, hp->pair->rqn[0],
 855                    dev_name(hp->pair->peer_mdev->device),
 856                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
 857
 858 attach_flow:
 859         if (hpe->hp->num_channels > 1) {
 860                 flow_flag_set(flow, HAIRPIN_RSS);
 861                 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
 862         } else {
 863                 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
 864         }
 865
 866         flow->hpe = hpe;
 867         spin_lock(&hpe->flows_lock);
 868         list_add(&flow->hairpin, &hpe->flows);
 869         spin_unlock(&hpe->flows_lock);
 870
 871         return 0;
 872
 873 out_err:
 874         mlx5e_hairpin_put(priv, hpe);
 875         return err;
 876 }
 877
 878 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
 879                                    struct mlx5e_tc_flow *flow)
 880 {
 881         /* flow wasn't fully initialized */
 882         if (!flow->hpe)
 883                 return;
 884
 885         spin_lock(&flow->hpe->flows_lock);
 886         list_del(&flow->hairpin);
 887         spin_unlock(&flow->hpe->flows_lock);
 888
 889         mlx5e_hairpin_put(priv, flow->hpe);
 890         flow->hpe = NULL;
 891 }
 892
 893 static int
 894 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
 895                       struct mlx5e_tc_flow_parse_attr *parse_attr,
 896                       struct mlx5e_tc_flow *flow,
 897                       struct netlink_ext_ack *extack)
 898 {
 899         struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
 900         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 901         struct mlx5_core_dev *dev = priv->mdev;
 902         struct mlx5_flow_destination dest[2] = {};
 903         struct mlx5_flow_act flow_act = {
 904                 .action = attr->action,
 905                 .reformat_id = 0,
 906                 .flags    = FLOW_ACT_NO_APPEND,
 907         };
 908         struct mlx5_fc *counter = NULL;
 909         int err, dest_ix = 0;
 910
 911         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
 912         flow_context->flow_tag = attr->flow_tag;
 913
 914         if (flow_flag_test(flow, HAIRPIN)) {
 915                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
 916                 if (err)
 917                         return err;
 918
 919                 if (flow_flag_test(flow, HAIRPIN_RSS)) {
 920                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 921                         dest[dest_ix].ft = attr->hairpin_ft;
 922                 } else {
 923                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
 924                         dest[dest_ix].tir_num = attr->hairpin_tirn;
 925                 }
 926                 dest_ix++;
 927         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
 928                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
 929                 dest[dest_ix].ft = priv->fs.vlan.ft.t;
 930                 dest_ix++;
 931         }
 932
 933         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
 934                 counter = mlx5_fc_create(dev, true);
 935                 if (IS_ERR(counter))
 936                         return PTR_ERR(counter);
 937
 938                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
 939                 dest[dest_ix].counter_id = mlx5_fc_id(counter);
 940                 dest_ix++;
 941                 attr->counter = counter;
 942         }
 943
 944         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
 945                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
 946                 flow_act.modify_id = attr->mod_hdr_id;
 947                 kfree(parse_attr->mod_hdr_actions);
 948                 if (err)
 949                         return err;
 950         }
 951
 952         mutex_lock(&priv->fs.tc.t_lock);
 953         if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
 954                 int tc_grp_size, tc_tbl_size;
 955                 u32 max_flow_counter;
 956
 957                 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
 958                                     MLX5_CAP_GEN(dev, max_flow_counter_15_0);
 959
 960                 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
 961
 962                 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
 963                                     BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
 964
 965                 priv->fs.tc.t =
 966                         mlx5_create_auto_grouped_flow_table(priv->fs.ns,
 967                                                             MLX5E_TC_PRIO,
 968                                                             tc_tbl_size,
 969                                                             MLX5E_TC_TABLE_NUM_GROUPS,
 970                                                             MLX5E_TC_FT_LEVEL, 0);
 971                 if (IS_ERR(priv->fs.tc.t)) {
 972                         mutex_unlock(&priv->fs.tc.t_lock);
 973                         NL_SET_ERR_MSG_MOD(extack,
 974                                            "Failed to create tc offload table\n");
 975                         netdev_err(priv->netdev,
 976                                    "Failed to create tc offload table\n");
 977                         return PTR_ERR(priv->fs.tc.t);
 978                 }
 979         }
 980
 981         if (attr->match_level != MLX5_MATCH_NONE)
 982                 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
 983
 984         flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
 985                                             &flow_act, dest, dest_ix);
 986         mutex_unlock(&priv->fs.tc.t_lock);
 987
 988         if (IS_ERR(flow->rule[0]))
 989                 return PTR_ERR(flow->rule[0]);
 990
 991         return 0;
 992 }
 993
 994 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
 995                                   struct mlx5e_tc_flow *flow)
 996 {
 997         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
 998         struct mlx5_fc *counter = NULL;
 999
1000         counter = attr->counter;
1001         if (!IS_ERR_OR_NULL(flow->rule[0]))
1002                 mlx5_del_flow_rules(flow->rule[0]);
1003         mlx5_fc_destroy(priv->mdev, counter);
1004
1005         mutex_lock(&priv->fs.tc.t_lock);
1006         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
1007                 mlx5_destroy_flow_table(priv->fs.tc.t);
1008                 priv->fs.tc.t = NULL;
1009         }
1010         mutex_unlock(&priv->fs.tc.t_lock);
1011
1012         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1013                 mlx5e_detach_mod_hdr(priv, flow);
1014
1015         if (flow_flag_test(flow, HAIRPIN))
1016                 mlx5e_hairpin_flow_del(priv, flow);
1017 }
1018
1019 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1020                                struct mlx5e_tc_flow *flow, int out_index);
1021
1022 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1023                               struct mlx5e_tc_flow *flow,
1024                               struct net_device *mirred_dev,
1025                               int out_index,
1026                               struct netlink_ext_ack *extack,
1027                               struct net_device **encap_dev,
1028                               bool *encap_valid);
1029
1030 static struct mlx5_flow_handle *
1031 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1032                            struct mlx5e_tc_flow *flow,
1033                            struct mlx5_flow_spec *spec,
1034                            struct mlx5_esw_flow_attr *attr)
1035 {
1036         struct mlx5_flow_handle *rule;
1037
1038         rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1039         if (IS_ERR(rule))
1040                 return rule;
1041
1042         if (attr->split_count) {
1043                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1044                 if (IS_ERR(flow->rule[1])) {
1045                         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1046                         return flow->rule[1];
1047                 }
1048         }
1049
1050         return rule;
1051 }
1052
1053 static void
1054 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1055                              struct mlx5e_tc_flow *flow,
1056                            struct mlx5_esw_flow_attr *attr)
1057 {
1058         flow_flag_clear(flow, OFFLOADED);
1059
1060         if (attr->split_count)
1061                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1062
1063         mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1064 }
1065
1066 static struct mlx5_flow_handle *
1067 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1068                               struct mlx5e_tc_flow *flow,
1069                               struct mlx5_flow_spec *spec,
1070                               struct mlx5_esw_flow_attr *slow_attr)
1071 {
1072         struct mlx5_flow_handle *rule;
1073
1074         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1075         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1076         slow_attr->split_count = 0;
1077         slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
1078
1079         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1080         if (!IS_ERR(rule))
1081                 flow_flag_set(flow, SLOW);
1082
1083         return rule;
1084 }
1085
1086 static void
1087 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1088                                   struct mlx5e_tc_flow *flow,
1089                                   struct mlx5_esw_flow_attr *slow_attr)
1090 {
1091         memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
1092         slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1093         slow_attr->split_count = 0;
1094         slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
1095         mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1096         flow_flag_clear(flow, SLOW);
1097 }
1098
1099 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1100  * function.
1101  */
1102 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1103                              struct list_head *unready_flows)
1104 {
1105         flow_flag_set(flow, NOT_READY);
1106         list_add_tail(&flow->unready, unready_flows);
1107 }
1108
1109 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1110  * function.
1111  */
1112 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1113 {
1114         list_del(&flow->unready);
1115         flow_flag_clear(flow, NOT_READY);
1116 }
1117
1118 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1119 {
1120         struct mlx5_rep_uplink_priv *uplink_priv;
1121         struct mlx5e_rep_priv *rpriv;
1122         struct mlx5_eswitch *esw;
1123
1124         esw = flow->priv->mdev->priv.eswitch;
1125         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1126         uplink_priv = &rpriv->uplink_priv;
1127
1128         mutex_lock(&uplink_priv->unready_flows_lock);
1129         unready_flow_add(flow, &uplink_priv->unready_flows);
1130         mutex_unlock(&uplink_priv->unready_flows_lock);
1131 }
1132
1133 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1134 {
1135         struct mlx5_rep_uplink_priv *uplink_priv;
1136         struct mlx5e_rep_priv *rpriv;
1137         struct mlx5_eswitch *esw;
1138
1139         esw = flow->priv->mdev->priv.eswitch;
1140         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1141         uplink_priv = &rpriv->uplink_priv;
1142
1143         mutex_lock(&uplink_priv->unready_flows_lock);
1144         unready_flow_del(flow);
1145         mutex_unlock(&uplink_priv->unready_flows_lock);
1146 }
1147
1148 static int
1149 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1150                       struct mlx5e_tc_flow *flow,
1151                       struct netlink_ext_ack *extack)
1152 {
1153         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1154         u32 max_chain = mlx5_eswitch_get_chain_range(esw);
1155         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1156         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1157         u16 max_prio = mlx5_eswitch_get_prio_range(esw);
1158         struct net_device *out_dev, *encap_dev = NULL;
1159         struct mlx5_fc *counter = NULL;
1160         struct mlx5e_rep_priv *rpriv;
1161         struct mlx5e_priv *out_priv;
1162         bool encap_valid = true;
1163         int err = 0;
1164         int out_index;
1165
1166         if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
1167                 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1168                 return -EOPNOTSUPP;
1169         }
1170
1171         if (attr->chain > max_chain) {
1172                 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
1173                 return -EOPNOTSUPP;
1174         }
1175
1176         if (attr->prio > max_prio) {
1177                 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
1178                 return -EOPNOTSUPP;
1179         }
1180
1181         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1182                 int mirred_ifindex;
1183
1184                 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1185                         continue;
1186
1187                 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1188                 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1189                                              mirred_ifindex);
1190                 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1191                                          extack, &encap_dev, &encap_valid);
1192                 if (err)
1193                         return err;
1194
1195                 out_priv = netdev_priv(encap_dev);
1196                 rpriv = out_priv->ppriv;
1197                 attr->dests[out_index].rep = rpriv->rep;
1198                 attr->dests[out_index].mdev = out_priv->mdev;
1199         }
1200
1201         err = mlx5_eswitch_add_vlan_action(esw, attr);
1202         if (err)
1203                 return err;
1204
1205         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1206                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1207                 kfree(parse_attr->mod_hdr_actions);
1208                 if (err)
1209                         return err;
1210         }
1211
1212         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1213                 counter = mlx5_fc_create(attr->counter_dev, true);
1214                 if (IS_ERR(counter))
1215                         return PTR_ERR(counter);
1216
1217                 attr->counter = counter;
1218         }
1219
1220         /* we get here if one of the following takes place:
1221          * (1) there's no error
1222          * (2) there's an encap action and we don't have valid neigh
1223          */
1224         if (!encap_valid) {
1225                 /* continue with goto slow path rule instead */
1226                 struct mlx5_esw_flow_attr slow_attr;
1227
1228                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1229         } else {
1230                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1231         }
1232
1233         if (IS_ERR(flow->rule[0]))
1234                 return PTR_ERR(flow->rule[0]);
1235         else
1236                 flow_flag_set(flow, OFFLOADED);
1237
1238         return 0;
1239 }
1240
1241 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1242 {
1243         struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1244         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1245                                        spec->match_value,
1246                                        misc_parameters_3);
1247         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1248                                              headers_v,
1249                                              geneve_tlv_option_0_data);
1250
1251         return !!geneve_tlv_opt_0_data;
1252 }
1253
1254 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1255                                   struct mlx5e_tc_flow *flow)
1256 {
1257         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1258         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1259         struct mlx5_esw_flow_attr slow_attr;
1260         int out_index;
1261
1262         if (flow_flag_test(flow, NOT_READY)) {
1263                 remove_unready_flow(flow);
1264                 kvfree(attr->parse_attr);
1265                 return;
1266         }
1267
1268         if (mlx5e_is_offloaded_flow(flow)) {
1269                 if (flow_flag_test(flow, SLOW))
1270                         mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1271                 else
1272                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1273         }
1274
1275         if (mlx5_flow_has_geneve_opt(flow))
1276                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1277
1278         mlx5_eswitch_del_vlan_action(esw, attr);
1279
1280         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1281                 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1282                         mlx5e_detach_encap(priv, flow, out_index);
1283         kvfree(attr->parse_attr);
1284
1285         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1286                 mlx5e_detach_mod_hdr(priv, flow);
1287
1288         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1289                 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1290 }
1291
1292 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1293                               struct mlx5e_encap_entry *e)
1294 {
1295         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1296         struct mlx5_esw_flow_attr slow_attr, *esw_attr;
1297         struct encap_flow_item *efi, *tmp;
1298         struct mlx5_flow_handle *rule;
1299         struct mlx5_flow_spec *spec;
1300         struct mlx5e_tc_flow *flow;
1301         int err;
1302
1303         err = mlx5_packet_reformat_alloc(priv->mdev,
1304                                          e->reformat_type,
1305                                          e->encap_size, e->encap_header,
1306                                          MLX5_FLOW_NAMESPACE_FDB,
1307                                          &e->encap_id);
1308         if (err) {
1309                 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1310                                err);
1311                 return;
1312         }
1313         e->flags |= MLX5_ENCAP_ENTRY_VALID;
1314         mlx5e_rep_queue_neigh_stats_work(priv);
1315
1316         list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1317                 bool all_flow_encaps_valid = true;
1318                 int i;
1319
1320                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1321                 if (IS_ERR(mlx5e_flow_get(flow)))
1322                         continue;
1323
1324                 esw_attr = flow->esw_attr;
1325                 spec = &esw_attr->parse_attr->spec;
1326
1327                 esw_attr->dests[efi->index].encap_id = e->encap_id;
1328                 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1329                 /* Flow can be associated with multiple encap entries.
1330                  * Before offloading the flow verify that all of them have
1331                  * a valid neighbour.
1332                  */
1333                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1334                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1335                                 continue;
1336                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1337                                 all_flow_encaps_valid = false;
1338                                 break;
1339                         }
1340                 }
1341                 /* Do not offload flows with unresolved neighbors */
1342                 if (!all_flow_encaps_valid)
1343                         goto loop_cont;
1344                 /* update from slow path rule to encap rule */
1345                 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1346                 if (IS_ERR(rule)) {
1347                         err = PTR_ERR(rule);
1348                         mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1349                                        err);
1350                         goto loop_cont;
1351                 }
1352
1353                 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1354                 flow->rule[0] = rule;
1355                 /* was unset when slow path rule removed */
1356                 flow_flag_set(flow, OFFLOADED);
1357
1358 loop_cont:
1359                 mlx5e_flow_put(priv, flow);
1360         }
1361 }
1362
1363 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1364                               struct mlx5e_encap_entry *e)
1365 {
1366         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1367         struct mlx5_esw_flow_attr slow_attr;
1368         struct encap_flow_item *efi, *tmp;
1369         struct mlx5_flow_handle *rule;
1370         struct mlx5_flow_spec *spec;
1371         struct mlx5e_tc_flow *flow;
1372         int err;
1373
1374         list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1375                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1376                 if (IS_ERR(mlx5e_flow_get(flow)))
1377                         continue;
1378
1379                 spec = &flow->esw_attr->parse_attr->spec;
1380
1381                 /* update from encap rule to slow path rule */
1382                 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1383                 /* mark the flow's encap dest as non-valid */
1384                 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1385
1386                 if (IS_ERR(rule)) {
1387                         err = PTR_ERR(rule);
1388                         mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1389                                        err);
1390                         goto loop_cont;
1391                 }
1392
1393                 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1394                 flow->rule[0] = rule;
1395                 /* was unset when fast path rule removed */
1396                 flow_flag_set(flow, OFFLOADED);
1397
1398 loop_cont:
1399                 mlx5e_flow_put(priv, flow);
1400         }
1401
1402         /* we know that the encap is valid */
1403         e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1404         mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1405 }
1406
1407 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1408 {
1409         if (mlx5e_is_eswitch_flow(flow))
1410                 return flow->esw_attr->counter;
1411         else
1412                 return flow->nic_attr->counter;
1413 }
1414
1415 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1416 {
1417         struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1418         struct mlx5e_tc_flow *flow;
1419         struct mlx5e_encap_entry *e;
1420         struct mlx5_fc *counter;
1421         struct neigh_table *tbl;
1422         bool neigh_used = false;
1423         struct neighbour *n;
1424         u64 lastuse;
1425
1426         if (m_neigh->family == AF_INET)
1427                 tbl = &arp_tbl;
1428 #if IS_ENABLED(CONFIG_IPV6)
1429         else if (m_neigh->family == AF_INET6)
1430                 tbl = &nd_tbl;
1431 #endif
1432         else
1433                 return;
1434
1435         list_for_each_entry(e, &nhe->encap_list, encap_list) {
1436                 struct encap_flow_item *efi, *tmp;
1437
1438                 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID) ||
1439                     !mlx5e_encap_take(e))
1440                         continue;
1441
1442                 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1443                         flow = container_of(efi, struct mlx5e_tc_flow,
1444                                             encaps[efi->index]);
1445                         if (IS_ERR(mlx5e_flow_get(flow)))
1446                                 continue;
1447
1448                         if (mlx5e_is_offloaded_flow(flow)) {
1449                                 counter = mlx5e_tc_get_counter(flow);
1450                                 lastuse = mlx5_fc_query_lastuse(counter);
1451                                 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1452                                         mlx5e_flow_put(netdev_priv(e->out_dev), flow);
1453                                         neigh_used = true;
1454                                         break;
1455                                 }
1456                         }
1457
1458                         mlx5e_flow_put(netdev_priv(e->out_dev), flow);
1459                 }
1460
1461                 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1462                 if (neigh_used)
1463                         break;
1464         }
1465
1466         if (neigh_used) {
1467                 nhe->reported_lastuse = jiffies;
1468
1469                 /* find the relevant neigh according to the cached device and
1470                  * dst ip pair
1471                  */
1472                 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1473                 if (!n)
1474                         return;
1475
1476                 neigh_event_send(n, NULL);
1477                 neigh_release(n);
1478         }
1479 }
1480
1481 static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1482 {
1483         WARN_ON(!list_empty(&e->flows));
1484         mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1485
1486         if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1487                 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
1488
1489         kfree(e->encap_header);
1490         kfree(e);
1491 }
1492
1493 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1494 {
1495         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1496
1497         if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1498                 return;
1499         hash_del_rcu(&e->encap_hlist);
1500         mutex_unlock(&esw->offloads.encap_tbl_lock);
1501
1502         mlx5e_encap_dealloc(priv, e);
1503 }
1504
1505 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1506                                struct mlx5e_tc_flow *flow, int out_index)
1507 {
1508         struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1509         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1510
1511         /* flow wasn't fully initialized */
1512         if (!e)
1513                 return;
1514
1515         mutex_lock(&esw->offloads.encap_tbl_lock);
1516         list_del(&flow->encaps[out_index].list);
1517         flow->encaps[out_index].e = NULL;
1518         if (!refcount_dec_and_test(&e->refcnt)) {
1519                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1520                 return;
1521         }
1522         hash_del_rcu(&e->encap_hlist);
1523         mutex_unlock(&esw->offloads.encap_tbl_lock);
1524
1525         mlx5e_encap_dealloc(priv, e);
1526 }
1527
1528 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1529 {
1530         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1531
1532         if (!flow_flag_test(flow, ESWITCH) ||
1533             !flow_flag_test(flow, DUP))
1534                 return;
1535
1536         mutex_lock(&esw->offloads.peer_mutex);
1537         list_del(&flow->peer);
1538         mutex_unlock(&esw->offloads.peer_mutex);
1539
1540         flow_flag_clear(flow, DUP);
1541
1542         mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1543         kvfree(flow->peer_flow);
1544         flow->peer_flow = NULL;
1545 }
1546
1547 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1548 {
1549         struct mlx5_core_dev *dev = flow->priv->mdev;
1550         struct mlx5_devcom *devcom = dev->priv.devcom;
1551         struct mlx5_eswitch *peer_esw;
1552
1553         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1554         if (!peer_esw)
1555                 return;
1556
1557         __mlx5e_tc_del_fdb_peer_flow(flow);
1558         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1559 }
1560
1561 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1562                               struct mlx5e_tc_flow *flow)
1563 {
1564         if (mlx5e_is_eswitch_flow(flow)) {
1565                 mlx5e_tc_del_fdb_peer_flow(flow);
1566                 mlx5e_tc_del_fdb_flow(priv, flow);
1567         } else {
1568                 mlx5e_tc_del_nic_flow(priv, flow);
1569         }
1570 }
1571
1572
1573 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1574                              struct mlx5_flow_spec *spec,
1575                              struct flow_cls_offload *f,
1576                              struct net_device *filter_dev, u8 *match_level)
1577 {
1578         struct netlink_ext_ack *extack = f->common.extack;
1579         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1580                                        outer_headers);
1581         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1582                                        outer_headers);
1583         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1584         int err;
1585
1586         err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1587                                  headers_c, headers_v, match_level);
1588         if (err) {
1589                 NL_SET_ERR_MSG_MOD(extack,
1590                                    "failed to parse tunnel attributes");
1591                 return err;
1592         }
1593
1594         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) {
1595                 struct flow_match_ipv4_addrs match;
1596
1597                 flow_rule_match_enc_ipv4_addrs(rule, &match);
1598                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1599                          src_ipv4_src_ipv6.ipv4_layout.ipv4,
1600                          ntohl(match.mask->src));
1601                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1602                          src_ipv4_src_ipv6.ipv4_layout.ipv4,
1603                          ntohl(match.key->src));
1604
1605                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1606                          dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1607                          ntohl(match.mask->dst));
1608                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1609                          dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1610                          ntohl(match.key->dst));
1611
1612                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1613                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
1614         } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) {
1615                 struct flow_match_ipv6_addrs match;
1616
1617                 flow_rule_match_enc_ipv6_addrs(rule, &match);
1618                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1619                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1620                        &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1621                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1622                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1623                        &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1624
1625                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1626                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1627                        &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1628                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1629                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1630                        &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1631
1632                 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1633                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
1634         }
1635
1636         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1637                 struct flow_match_ip match;
1638
1639                 flow_rule_match_enc_ip(rule, &match);
1640                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1641                          match.mask->tos & 0x3);
1642                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1643                          match.key->tos & 0x3);
1644
1645                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1646                          match.mask->tos >> 2);
1647                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1648                          match.key->tos  >> 2);
1649
1650                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1651                          match.mask->ttl);
1652                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1653                          match.key->ttl);
1654
1655                 if (match.mask->ttl &&
1656                     !MLX5_CAP_ESW_FLOWTABLE_FDB
1657                         (priv->mdev,
1658                          ft_field_support.outer_ipv4_ttl)) {
1659                         NL_SET_ERR_MSG_MOD(extack,
1660                                            "Matching on TTL is not supported");
1661                         return -EOPNOTSUPP;
1662                 }
1663
1664         }
1665
1666         /* Enforce DMAC when offloading incoming tunneled flows.
1667          * Flow counters require a match on the DMAC.
1668          */
1669         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1670         MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1671         ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1672                                      dmac_47_16), priv->netdev->dev_addr);
1673
1674         /* let software handle IP fragments */
1675         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1676         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1677
1678         return 0;
1679 }
1680
1681 static void *get_match_headers_criteria(u32 flags,
1682                                         struct mlx5_flow_spec *spec)
1683 {
1684         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1685                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1686                              inner_headers) :
1687                 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1688                              outer_headers);
1689 }
1690
1691 static void *get_match_headers_value(u32 flags,
1692                                      struct mlx5_flow_spec *spec)
1693 {
1694         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1695                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1696                              inner_headers) :
1697                 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1698                              outer_headers);
1699 }
1700
1701 static int __parse_cls_flower(struct mlx5e_priv *priv,
1702                               struct mlx5_flow_spec *spec,
1703                               struct flow_cls_offload *f,
1704                               struct net_device *filter_dev,
1705                               u8 *match_level, u8 *tunnel_match_level)
1706 {
1707         struct netlink_ext_ack *extack = f->common.extack;
1708         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1709                                        outer_headers);
1710         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1711                                        outer_headers);
1712         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1713                                     misc_parameters);
1714         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1715                                     misc_parameters);
1716         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1717         struct flow_dissector *dissector = rule->match.dissector;
1718         u16 addr_type = 0;
1719         u8 ip_proto = 0;
1720
1721         *match_level = MLX5_MATCH_NONE;
1722
1723         if (dissector->used_keys &
1724             ~(BIT(FLOW_DISSECTOR_KEY_META) |
1725               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1726               BIT(FLOW_DISSECTOR_KEY_BASIC) |
1727               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
1728               BIT(FLOW_DISSECTOR_KEY_VLAN) |
1729               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
1730               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1731               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
1732               BIT(FLOW_DISSECTOR_KEY_PORTS) |
1733               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1734               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1735               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1736               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
1737               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
1738               BIT(FLOW_DISSECTOR_KEY_TCP) |
1739               BIT(FLOW_DISSECTOR_KEY_IP)  |
1740               BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1741               BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
1742                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
1743                 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1744                             dissector->used_keys);
1745                 return -EOPNOTSUPP;
1746         }
1747
1748         if (mlx5e_get_tc_tun(filter_dev)) {
1749                 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
1750                         return -EOPNOTSUPP;
1751
1752                 /* In decap flow, header pointers should point to the inner
1753                  * headers, outer header were already set by parse_tunnel_attr
1754                  */
1755                 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1756                                                        spec);
1757                 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1758                                                     spec);
1759         }
1760
1761         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1762                 struct flow_match_basic match;
1763
1764                 flow_rule_match_basic(rule, &match);
1765                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1766                          ntohs(match.mask->n_proto));
1767                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1768                          ntohs(match.key->n_proto));
1769
1770                 if (match.mask->n_proto)
1771                         *match_level = MLX5_MATCH_L2;
1772         }
1773         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1774             is_vlan_dev(filter_dev)) {
1775                 struct flow_dissector_key_vlan filter_dev_mask;
1776                 struct flow_dissector_key_vlan filter_dev_key;
1777                 struct flow_match_vlan match;
1778
1779                 if (is_vlan_dev(filter_dev)) {
1780                         match.key = &filter_dev_key;
1781                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1782                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1783                         match.key->vlan_priority = 0;
1784                         match.mask = &filter_dev_mask;
1785                         memset(match.mask, 0xff, sizeof(*match.mask));
1786                         match.mask->vlan_priority = 0;
1787                 } else {
1788                         flow_rule_match_vlan(rule, &match);
1789                 }
1790                 if (match.mask->vlan_id ||
1791                     match.mask->vlan_priority ||
1792                     match.mask->vlan_tpid) {
1793                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1794                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1795                                          svlan_tag, 1);
1796                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1797                                          svlan_tag, 1);
1798                         } else {
1799                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1800                                          cvlan_tag, 1);
1801                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1802                                          cvlan_tag, 1);
1803                         }
1804
1805                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1806                                  match.mask->vlan_id);
1807                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1808                                  match.key->vlan_id);
1809
1810                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1811                                  match.mask->vlan_priority);
1812                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1813                                  match.key->vlan_priority);
1814
1815                         *match_level = MLX5_MATCH_L2;
1816                 }
1817         } else if (*match_level != MLX5_MATCH_NONE) {
1818                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1819                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1820                 *match_level = MLX5_MATCH_L2;
1821         }
1822
1823         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1824                 struct flow_match_vlan match;
1825
1826                 flow_rule_match_cvlan(rule, &match);
1827                 if (match.mask->vlan_id ||
1828                     match.mask->vlan_priority ||
1829                     match.mask->vlan_tpid) {
1830                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
1831                                 MLX5_SET(fte_match_set_misc, misc_c,
1832                                          outer_second_svlan_tag, 1);
1833                                 MLX5_SET(fte_match_set_misc, misc_v,
1834                                          outer_second_svlan_tag, 1);
1835                         } else {
1836                                 MLX5_SET(fte_match_set_misc, misc_c,
1837                                          outer_second_cvlan_tag, 1);
1838                                 MLX5_SET(fte_match_set_misc, misc_v,
1839                                          outer_second_cvlan_tag, 1);
1840                         }
1841
1842                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1843                                  match.mask->vlan_id);
1844                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1845                                  match.key->vlan_id);
1846                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1847                                  match.mask->vlan_priority);
1848                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1849                                  match.key->vlan_priority);
1850
1851                         *match_level = MLX5_MATCH_L2;
1852                 }
1853         }
1854
1855         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1856                 struct flow_match_eth_addrs match;
1857
1858                 flow_rule_match_eth_addrs(rule, &match);
1859                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1860                                              dmac_47_16),
1861                                 match.mask->dst);
1862                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1863                                              dmac_47_16),
1864                                 match.key->dst);
1865
1866                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1867                                              smac_47_16),
1868                                 match.mask->src);
1869                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1870                                              smac_47_16),
1871                                 match.key->src);
1872
1873                 if (!is_zero_ether_addr(match.mask->src) ||
1874                     !is_zero_ether_addr(match.mask->dst))
1875                         *match_level = MLX5_MATCH_L2;
1876         }
1877
1878         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1879                 struct flow_match_control match;
1880
1881                 flow_rule_match_control(rule, &match);
1882                 addr_type = match.key->addr_type;
1883
1884                 /* the HW doesn't support frag first/later */
1885                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
1886                         return -EOPNOTSUPP;
1887
1888                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
1889                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1890                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1891                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
1892
1893                         /* the HW doesn't need L3 inline to match on frag=no */
1894                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
1895                                 *match_level = MLX5_MATCH_L2;
1896         /* ***  L2 attributes parsing up to here *** */
1897                         else
1898                                 *match_level = MLX5_MATCH_L3;
1899                 }
1900         }
1901
1902         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1903                 struct flow_match_basic match;
1904
1905                 flow_rule_match_basic(rule, &match);
1906                 ip_proto = match.key->ip_proto;
1907
1908                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1909                          match.mask->ip_proto);
1910                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1911                          match.key->ip_proto);
1912
1913                 if (match.mask->ip_proto)
1914                         *match_level = MLX5_MATCH_L3;
1915         }
1916
1917         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1918                 struct flow_match_ipv4_addrs match;
1919
1920                 flow_rule_match_ipv4_addrs(rule, &match);
1921                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1922                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1923                        &match.mask->src, sizeof(match.mask->src));
1924                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1925                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1926                        &match.key->src, sizeof(match.key->src));
1927                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1928                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1929                        &match.mask->dst, sizeof(match.mask->dst));
1930                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1931                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1932                        &match.key->dst, sizeof(match.key->dst));
1933
1934                 if (match.mask->src || match.mask->dst)
1935                         *match_level = MLX5_MATCH_L3;
1936         }
1937
1938         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1939                 struct flow_match_ipv6_addrs match;
1940
1941                 flow_rule_match_ipv6_addrs(rule, &match);
1942                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1943                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1944                        &match.mask->src, sizeof(match.mask->src));
1945                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1946                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1947                        &match.key->src, sizeof(match.key->src));
1948
1949                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1950                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1951                        &match.mask->dst, sizeof(match.mask->dst));
1952                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1953                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1954                        &match.key->dst, sizeof(match.key->dst));
1955
1956                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1957                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
1958                         *match_level = MLX5_MATCH_L3;
1959         }
1960
1961         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1962                 struct flow_match_ip match;
1963
1964                 flow_rule_match_ip(rule, &match);
1965                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1966                          match.mask->tos & 0x3);
1967                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1968                          match.key->tos & 0x3);
1969
1970                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1971                          match.mask->tos >> 2);
1972                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1973                          match.key->tos  >> 2);
1974
1975                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1976                          match.mask->ttl);
1977                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1978                          match.key->ttl);
1979
1980                 if (match.mask->ttl &&
1981                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1982                                                 ft_field_support.outer_ipv4_ttl)) {
1983                         NL_SET_ERR_MSG_MOD(extack,
1984                                            "Matching on TTL is not supported");
1985                         return -EOPNOTSUPP;
1986                 }
1987
1988                 if (match.mask->tos || match.mask->ttl)
1989                         *match_level = MLX5_MATCH_L3;
1990         }
1991
1992         /* ***  L3 attributes parsing up to here *** */
1993
1994         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1995                 struct flow_match_ports match;
1996
1997                 flow_rule_match_ports(rule, &match);
1998                 switch (ip_proto) {
1999                 case IPPROTO_TCP:
2000                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2001                                  tcp_sport, ntohs(match.mask->src));
2002                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2003                                  tcp_sport, ntohs(match.key->src));
2004
2005                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2006                                  tcp_dport, ntohs(match.mask->dst));
2007                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2008                                  tcp_dport, ntohs(match.key->dst));
2009                         break;
2010
2011                 case IPPROTO_UDP:
2012                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2013                                  udp_sport, ntohs(match.mask->src));
2014                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2015                                  udp_sport, ntohs(match.key->src));
2016
2017                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2018                                  udp_dport, ntohs(match.mask->dst));
2019                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2020                                  udp_dport, ntohs(match.key->dst));
2021                         break;
2022                 default:
2023                         NL_SET_ERR_MSG_MOD(extack,
2024                                            "Only UDP and TCP transports are supported for L4 matching");
2025                         netdev_err(priv->netdev,
2026                                    "Only UDP and TCP transport are supported\n");
2027                         return -EINVAL;
2028                 }
2029
2030                 if (match.mask->src || match.mask->dst)
2031                         *match_level = MLX5_MATCH_L4;
2032         }
2033
2034         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2035                 struct flow_match_tcp match;
2036
2037                 flow_rule_match_tcp(rule, &match);
2038                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2039                          ntohs(match.mask->flags));
2040                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2041                          ntohs(match.key->flags));
2042
2043                 if (match.mask->flags)
2044                         *match_level = MLX5_MATCH_L4;
2045         }
2046
2047         return 0;
2048 }
2049
2050 static int parse_cls_flower(struct mlx5e_priv *priv,
2051                             struct mlx5e_tc_flow *flow,
2052                             struct mlx5_flow_spec *spec,
2053                             struct flow_cls_offload *f,
2054                             struct net_device *filter_dev)
2055 {
2056         struct netlink_ext_ack *extack = f->common.extack;
2057         struct mlx5_core_dev *dev = priv->mdev;
2058         struct mlx5_eswitch *esw = dev->priv.eswitch;
2059         struct mlx5e_rep_priv *rpriv = priv->ppriv;
2060         u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
2061         struct mlx5_eswitch_rep *rep;
2062         bool is_eswitch_flow;
2063         int err;
2064
2065         err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
2066
2067         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2068         if (!err && is_eswitch_flow) {
2069                 rep = rpriv->rep;
2070                 if (rep->vport != MLX5_VPORT_UPLINK &&
2071                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2072                     esw->offloads.inline_mode < match_level)) {
2073                         NL_SET_ERR_MSG_MOD(extack,
2074                                            "Flow is not offloaded due to min inline setting");
2075                         netdev_warn(priv->netdev,
2076                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2077                                     match_level, esw->offloads.inline_mode);
2078                         return -EOPNOTSUPP;
2079                 }
2080         }
2081
2082         if (is_eswitch_flow) {
2083                 flow->esw_attr->match_level = match_level;
2084                 flow->esw_attr->tunnel_match_level = tunnel_match_level;
2085         } else {
2086                 flow->nic_attr->match_level = match_level;
2087         }
2088
2089         return err;
2090 }
2091
2092 struct pedit_headers {
2093         struct ethhdr  eth;
2094         struct vlan_hdr vlan;
2095         struct iphdr   ip4;
2096         struct ipv6hdr ip6;
2097         struct tcphdr  tcp;
2098         struct udphdr  udp;
2099 };
2100
2101 struct pedit_headers_action {
2102         struct pedit_headers    vals;
2103         struct pedit_headers    masks;
2104         u32                     pedits;
2105 };
2106
2107 static int pedit_header_offsets[] = {
2108         [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2109         [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2110         [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2111         [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2112         [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2113 };
2114
2115 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2116
2117 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2118                          struct pedit_headers_action *hdrs)
2119 {
2120         u32 *curr_pmask, *curr_pval;
2121
2122         curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2123         curr_pval  = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2124
2125         if (*curr_pmask & mask)  /* disallow acting twice on the same location */
2126                 goto out_err;
2127
2128         *curr_pmask |= mask;
2129         *curr_pval  |= (val & mask);
2130
2131         return 0;
2132
2133 out_err:
2134         return -EOPNOTSUPP;
2135 }
2136
2137 struct mlx5_fields {
2138         u8  field;
2139         u8  size;
2140         u32 offset;
2141         u32 match_offset;
2142 };
2143
2144 #define OFFLOAD(fw_field, size, field, off, match_field) \
2145                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
2146                  offsetof(struct pedit_headers, field) + (off), \
2147                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2148
2149 /* masked values are the same and there are no rewrites that do not have a
2150  * match.
2151  */
2152 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2153         type matchmaskx = *(type *)(matchmaskp); \
2154         type matchvalx = *(type *)(matchvalp); \
2155         type maskx = *(type *)(maskp); \
2156         type valx = *(type *)(valp); \
2157         \
2158         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2159                                                                  matchmaskx)); \
2160 })
2161
2162 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2163                          void *matchmaskp, int size)
2164 {
2165         bool same = false;
2166
2167         switch (size) {
2168         case sizeof(u8):
2169                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2170                 break;
2171         case sizeof(u16):
2172                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2173                 break;
2174         case sizeof(u32):
2175                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2176                 break;
2177         }
2178
2179         return same;
2180 }
2181
2182 static struct mlx5_fields fields[] = {
2183         OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
2184         OFFLOAD(DMAC_15_0,  2, eth.h_dest[4], 0, dmac_15_0),
2185         OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
2186         OFFLOAD(SMAC_15_0,  2, eth.h_source[4], 0, smac_15_0),
2187         OFFLOAD(ETHERTYPE,  2, eth.h_proto, 0, ethertype),
2188         OFFLOAD(FIRST_VID,  2, vlan.h_vlan_TCI, 0, first_vid),
2189
2190         OFFLOAD(IP_TTL, 1, ip4.ttl,   0, ttl_hoplimit),
2191         OFFLOAD(SIPV4,  4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2192         OFFLOAD(DIPV4,  4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2193
2194         OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
2195                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2196         OFFLOAD(SIPV6_95_64,  4, ip6.saddr.s6_addr32[1], 0,
2197                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2198         OFFLOAD(SIPV6_63_32,  4, ip6.saddr.s6_addr32[2], 0,
2199                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2200         OFFLOAD(SIPV6_31_0,   4, ip6.saddr.s6_addr32[3], 0,
2201                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2202         OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
2203                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2204         OFFLOAD(DIPV6_95_64,  4, ip6.daddr.s6_addr32[1], 0,
2205                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2206         OFFLOAD(DIPV6_63_32,  4, ip6.daddr.s6_addr32[2], 0,
2207                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2208         OFFLOAD(DIPV6_31_0,   4, ip6.daddr.s6_addr32[3], 0,
2209                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2210         OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
2211
2212         OFFLOAD(TCP_SPORT, 2, tcp.source,  0, tcp_sport),
2213         OFFLOAD(TCP_DPORT, 2, tcp.dest,    0, tcp_dport),
2214         OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
2215
2216         OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
2217         OFFLOAD(UDP_DPORT, 2, udp.dest,   0, udp_dport),
2218 };
2219
2220 /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2221  * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2222  * says how many HW actions were actually parsed.
2223  */
2224 static int offload_pedit_fields(struct pedit_headers_action *hdrs,
2225                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2226                                 u32 *action_flags,
2227                                 struct netlink_ext_ack *extack)
2228 {
2229         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2230         void *headers_c = get_match_headers_criteria(*action_flags,
2231                                                      &parse_attr->spec);
2232         void *headers_v = get_match_headers_value(*action_flags,
2233                                                   &parse_attr->spec);
2234         int i, action_size, nactions, max_actions, first, last, next_z;
2235         void *s_masks_p, *a_masks_p, *vals_p;
2236         struct mlx5_fields *f;
2237         u8 cmd, field_bsize;
2238         u32 s_mask, a_mask;
2239         unsigned long mask;
2240         __be32 mask_be32;
2241         __be16 mask_be16;
2242         void *action;
2243
2244         set_masks = &hdrs[0].masks;
2245         add_masks = &hdrs[1].masks;
2246         set_vals = &hdrs[0].vals;
2247         add_vals = &hdrs[1].vals;
2248
2249         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2250         action = parse_attr->mod_hdr_actions +
2251                  parse_attr->num_mod_hdr_actions * action_size;
2252
2253         max_actions = parse_attr->max_mod_hdr_actions;
2254         nactions = parse_attr->num_mod_hdr_actions;
2255
2256         for (i = 0; i < ARRAY_SIZE(fields); i++) {
2257                 bool skip;
2258
2259                 f = &fields[i];
2260                 /* avoid seeing bits set from previous iterations */
2261                 s_mask = 0;
2262                 a_mask = 0;
2263
2264                 s_masks_p = (void *)set_masks + f->offset;
2265                 a_masks_p = (void *)add_masks + f->offset;
2266
2267                 memcpy(&s_mask, s_masks_p, f->size);
2268                 memcpy(&a_mask, a_masks_p, f->size);
2269
2270                 if (!s_mask && !a_mask) /* nothing to offload here */
2271                         continue;
2272
2273                 if (s_mask && a_mask) {
2274                         NL_SET_ERR_MSG_MOD(extack,
2275                                            "can't set and add to the same HW field");
2276                         printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2277                         return -EOPNOTSUPP;
2278                 }
2279
2280                 if (nactions == max_actions) {
2281                         NL_SET_ERR_MSG_MOD(extack,
2282                                            "too many pedit actions, can't offload");
2283                         printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2284                         return -EOPNOTSUPP;
2285                 }
2286
2287                 skip = false;
2288                 if (s_mask) {
2289                         void *match_mask = headers_c + f->match_offset;
2290                         void *match_val = headers_v + f->match_offset;
2291
2292                         cmd  = MLX5_ACTION_TYPE_SET;
2293                         mask = s_mask;
2294                         vals_p = (void *)set_vals + f->offset;
2295                         /* don't rewrite if we have a match on the same value */
2296                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
2297                                          match_mask, f->size))
2298                                 skip = true;
2299                         /* clear to denote we consumed this field */
2300                         memset(s_masks_p, 0, f->size);
2301                 } else {
2302                         u32 zero = 0;
2303
2304                         cmd  = MLX5_ACTION_TYPE_ADD;
2305                         mask = a_mask;
2306                         vals_p = (void *)add_vals + f->offset;
2307                         /* add 0 is no change */
2308                         if (!memcmp(vals_p, &zero, f->size))
2309                                 skip = true;
2310                         /* clear to denote we consumed this field */
2311                         memset(a_masks_p, 0, f->size);
2312                 }
2313                 if (skip)
2314                         continue;
2315
2316                 field_bsize = f->size * BITS_PER_BYTE;
2317
2318                 if (field_bsize == 32) {
2319                         mask_be32 = *(__be32 *)&mask;
2320                         mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2321                 } else if (field_bsize == 16) {
2322                         mask_be16 = *(__be16 *)&mask;
2323                         mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2324                 }
2325
2326                 first = find_first_bit(&mask, field_bsize);
2327                 next_z = find_next_zero_bit(&mask, field_bsize, first);
2328                 last  = find_last_bit(&mask, field_bsize);
2329                 if (first < next_z && next_z < last) {
2330                         NL_SET_ERR_MSG_MOD(extack,
2331                                            "rewrite of few sub-fields isn't supported");
2332                         printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2333                                mask);
2334                         return -EOPNOTSUPP;
2335                 }
2336
2337                 MLX5_SET(set_action_in, action, action_type, cmd);
2338                 MLX5_SET(set_action_in, action, field, f->field);
2339
2340                 if (cmd == MLX5_ACTION_TYPE_SET) {
2341                         MLX5_SET(set_action_in, action, offset, first);
2342                         /* length is num of bits to be written, zero means length of 32 */
2343                         MLX5_SET(set_action_in, action, length, (last - first + 1));
2344                 }
2345
2346                 if (field_bsize == 32)
2347                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2348                 else if (field_bsize == 16)
2349                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2350                 else if (field_bsize == 8)
2351                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2352
2353                 action += action_size;
2354                 nactions++;
2355         }
2356
2357         parse_attr->num_mod_hdr_actions = nactions;
2358         return 0;
2359 }
2360
2361 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2362                                                   int namespace)
2363 {
2364         if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2365                 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2366         else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2367                 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2368 }
2369
2370 static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2371                                  struct pedit_headers_action *hdrs,
2372                                  int namespace,
2373                                  struct mlx5e_tc_flow_parse_attr *parse_attr)
2374 {
2375         int nkeys, action_size, max_actions;
2376
2377         nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2378                 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
2379         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2380
2381         max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
2382         /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2383         max_actions = min(max_actions, nkeys * 16);
2384
2385         parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2386         if (!parse_attr->mod_hdr_actions)
2387                 return -ENOMEM;
2388
2389         parse_attr->max_mod_hdr_actions = max_actions;
2390         return 0;
2391 }
2392
2393 static const struct pedit_headers zero_masks = {};
2394
2395 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2396                                  const struct flow_action_entry *act, int namespace,
2397                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2398                                  struct pedit_headers_action *hdrs,
2399                                  struct netlink_ext_ack *extack)
2400 {
2401         u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2402         int err = -EOPNOTSUPP;
2403         u32 mask, val, offset;
2404         u8 htype;
2405
2406         htype = act->mangle.htype;
2407         err = -EOPNOTSUPP; /* can't be all optimistic */
2408
2409         if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2410                 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2411                 goto out_err;
2412         }
2413
2414         if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2415                 NL_SET_ERR_MSG_MOD(extack,
2416                                    "The pedit offload action is not supported");
2417                 goto out_err;
2418         }
2419
2420         mask = act->mangle.mask;
2421         val = act->mangle.val;
2422         offset = act->mangle.offset;
2423
2424         err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2425         if (err)
2426                 goto out_err;
2427
2428         hdrs[cmd].pedits++;
2429
2430         return 0;
2431 out_err:
2432         return err;
2433 }
2434
2435 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2436                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2437                                  struct pedit_headers_action *hdrs,
2438                                  u32 *action_flags,
2439                                  struct netlink_ext_ack *extack)
2440 {
2441         struct pedit_headers *cmd_masks;
2442         int err;
2443         u8 cmd;
2444
2445         if (!parse_attr->mod_hdr_actions) {
2446                 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
2447                 if (err)
2448                         goto out_err;
2449         }
2450
2451         err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
2452         if (err < 0)
2453                 goto out_dealloc_parsed_actions;
2454
2455         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2456                 cmd_masks = &hdrs[cmd].masks;
2457                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2458                         NL_SET_ERR_MSG_MOD(extack,
2459                                            "attempt to offload an unsupported field");
2460                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2461                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2462                                        16, 1, cmd_masks, sizeof(zero_masks), true);
2463                         err = -EOPNOTSUPP;
2464                         goto out_dealloc_parsed_actions;
2465                 }
2466         }
2467
2468         return 0;
2469
2470 out_dealloc_parsed_actions:
2471         kfree(parse_attr->mod_hdr_actions);
2472 out_err:
2473         return err;
2474 }
2475
2476 static bool csum_offload_supported(struct mlx5e_priv *priv,
2477                                    u32 action,
2478                                    u32 update_flags,
2479                                    struct netlink_ext_ack *extack)
2480 {
2481         u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2482                          TCA_CSUM_UPDATE_FLAG_UDP;
2483
2484         /*  The HW recalcs checksums only if re-writing headers */
2485         if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2486                 NL_SET_ERR_MSG_MOD(extack,
2487                                    "TC csum action is only offloaded with pedit");
2488                 netdev_warn(priv->netdev,
2489                             "TC csum action is only offloaded with pedit\n");
2490                 return false;
2491         }
2492
2493         if (update_flags & ~prot_flags) {
2494                 NL_SET_ERR_MSG_MOD(extack,
2495                                    "can't offload TC csum action for some header/s");
2496                 netdev_warn(priv->netdev,
2497                             "can't offload TC csum action for some header/s - flags %#x\n",
2498                             update_flags);
2499                 return false;
2500         }
2501
2502         return true;
2503 }
2504
2505 struct ip_ttl_word {
2506         __u8    ttl;
2507         __u8    protocol;
2508         __sum16 check;
2509 };
2510
2511 struct ipv6_hoplimit_word {
2512         __be16  payload_len;
2513         __u8    nexthdr;
2514         __u8    hop_limit;
2515 };
2516
2517 static bool is_action_keys_supported(const struct flow_action_entry *act)
2518 {
2519         u32 mask, offset;
2520         u8 htype;
2521
2522         htype = act->mangle.htype;
2523         offset = act->mangle.offset;
2524         mask = ~act->mangle.mask;
2525         /* For IPv4 & IPv6 header check 4 byte word,
2526          * to determine that modified fields
2527          * are NOT ttl & hop_limit only.
2528          */
2529         if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2530                 struct ip_ttl_word *ttl_word =
2531                         (struct ip_ttl_word *)&mask;
2532
2533                 if (offset != offsetof(struct iphdr, ttl) ||
2534                     ttl_word->protocol ||
2535                     ttl_word->check) {
2536                         return true;
2537                 }
2538         } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2539                 struct ipv6_hoplimit_word *hoplimit_word =
2540                         (struct ipv6_hoplimit_word *)&mask;
2541
2542                 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2543                     hoplimit_word->payload_len ||
2544                     hoplimit_word->nexthdr) {
2545                         return true;
2546                 }
2547         }
2548         return false;
2549 }
2550
2551 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
2552                                           struct flow_action *flow_action,
2553                                           u32 actions,
2554                                           struct netlink_ext_ack *extack)
2555 {
2556         const struct flow_action_entry *act;
2557         bool modify_ip_header;
2558         void *headers_v;
2559         u16 ethertype;
2560         u8 ip_proto;
2561         int i;
2562
2563         headers_v = get_match_headers_value(actions, spec);
2564         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2565
2566         /* for non-IP we only re-write MACs, so we're okay */
2567         if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2568                 goto out_ok;
2569
2570         modify_ip_header = false;
2571         flow_action_for_each(i, act, flow_action) {
2572                 if (act->id != FLOW_ACTION_MANGLE &&
2573                     act->id != FLOW_ACTION_ADD)
2574                         continue;
2575
2576                 if (is_action_keys_supported(act)) {
2577                         modify_ip_header = true;
2578                         break;
2579                 }
2580         }
2581
2582         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
2583         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2584             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
2585                 NL_SET_ERR_MSG_MOD(extack,
2586                                    "can't offload re-write of non TCP/UDP");
2587                 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2588                 return false;
2589         }
2590
2591 out_ok:
2592         return true;
2593 }
2594
2595 static bool actions_match_supported(struct mlx5e_priv *priv,
2596                                     struct flow_action *flow_action,
2597                                     struct mlx5e_tc_flow_parse_attr *parse_attr,
2598                                     struct mlx5e_tc_flow *flow,
2599                                     struct netlink_ext_ack *extack)
2600 {
2601         u32 actions;
2602
2603         if (mlx5e_is_eswitch_flow(flow))
2604                 actions = flow->esw_attr->action;
2605         else
2606                 actions = flow->nic_attr->action;
2607
2608         if (flow_flag_test(flow, EGRESS) &&
2609             !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
2610               (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2611               (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
2612                 return false;
2613
2614         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2615                 return modify_header_match_supported(&parse_attr->spec,
2616                                                      flow_action, actions,
2617                                                      extack);
2618
2619         return true;
2620 }
2621
2622 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2623 {
2624         struct mlx5_core_dev *fmdev, *pmdev;
2625         u64 fsystem_guid, psystem_guid;
2626
2627         fmdev = priv->mdev;
2628         pmdev = peer_priv->mdev;
2629
2630         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2631         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
2632
2633         return (fsystem_guid == psystem_guid);
2634 }
2635
2636 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2637                                    const struct flow_action_entry *act,
2638                                    struct mlx5e_tc_flow_parse_attr *parse_attr,
2639                                    struct pedit_headers_action *hdrs,
2640                                    u32 *action, struct netlink_ext_ack *extack)
2641 {
2642         u16 mask16 = VLAN_VID_MASK;
2643         u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2644         const struct flow_action_entry pedit_act = {
2645                 .id = FLOW_ACTION_MANGLE,
2646                 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2647                 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2648                 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2649                 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2650         };
2651         u8 match_prio_mask, match_prio_val;
2652         void *headers_c, *headers_v;
2653         int err;
2654
2655         headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2656         headers_v = get_match_headers_value(*action, &parse_attr->spec);
2657
2658         if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2659               MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2660                 NL_SET_ERR_MSG_MOD(extack,
2661                                    "VLAN rewrite action must have VLAN protocol match");
2662                 return -EOPNOTSUPP;
2663         }
2664
2665         match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2666         match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2667         if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2668                 NL_SET_ERR_MSG_MOD(extack,
2669                                    "Changing VLAN prio is not supported");
2670                 return -EOPNOTSUPP;
2671         }
2672
2673         err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2674                                     hdrs, NULL);
2675         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2676
2677         return err;
2678 }
2679
2680 static int
2681 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2682                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2683                                  struct pedit_headers_action *hdrs,
2684                                  u32 *action, struct netlink_ext_ack *extack)
2685 {
2686         const struct flow_action_entry prio_tag_act = {
2687                 .vlan.vid = 0,
2688                 .vlan.prio =
2689                         MLX5_GET(fte_match_set_lyr_2_4,
2690                                  get_match_headers_value(*action,
2691                                                          &parse_attr->spec),
2692                                  first_prio) &
2693                         MLX5_GET(fte_match_set_lyr_2_4,
2694                                  get_match_headers_criteria(*action,
2695                                                             &parse_attr->spec),
2696                                  first_prio),
2697         };
2698
2699         return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2700                                        &prio_tag_act, parse_attr, hdrs, action,
2701                                        extack);
2702 }
2703
2704 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2705                                 struct flow_action *flow_action,
2706                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2707                                 struct mlx5e_tc_flow *flow,
2708                                 struct netlink_ext_ack *extack)
2709 {
2710         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
2711         struct pedit_headers_action hdrs[2] = {};
2712         const struct flow_action_entry *act;
2713         u32 action = 0;
2714         int err, i;
2715
2716         if (!flow_action_has_entries(flow_action))
2717                 return -EINVAL;
2718
2719         attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2720
2721         flow_action_for_each(i, act, flow_action) {
2722                 switch (act->id) {
2723                 case FLOW_ACTION_DROP:
2724                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2725                         if (MLX5_CAP_FLOWTABLE(priv->mdev,
2726                                                flow_table_properties_nic_receive.flow_counter))
2727                                 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2728                         break;
2729                 case FLOW_ACTION_MANGLE:
2730                 case FLOW_ACTION_ADD:
2731                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
2732                                                     parse_attr, hdrs, extack);
2733                         if (err)
2734                                 return err;
2735
2736                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2737                                   MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2738                         break;
2739                 case FLOW_ACTION_VLAN_MANGLE:
2740                         err = add_vlan_rewrite_action(priv,
2741                                                       MLX5_FLOW_NAMESPACE_KERNEL,
2742                                                       act, parse_attr, hdrs,
2743                                                       &action, extack);
2744                         if (err)
2745                                 return err;
2746
2747                         break;
2748                 case FLOW_ACTION_CSUM:
2749                         if (csum_offload_supported(priv, action,
2750                                                    act->csum_flags,
2751                                                    extack))
2752                                 break;
2753
2754                         return -EOPNOTSUPP;
2755                 case FLOW_ACTION_REDIRECT: {
2756                         struct net_device *peer_dev = act->dev;
2757
2758                         if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2759                             same_hw_devs(priv, netdev_priv(peer_dev))) {
2760                                 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
2761                                 flow_flag_set(flow, HAIRPIN);
2762                                 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2763                                           MLX5_FLOW_CONTEXT_ACTION_COUNT;
2764                         } else {
2765                                 NL_SET_ERR_MSG_MOD(extack,
2766                                                    "device is not on same HW, can't offload");
2767                                 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2768                                             peer_dev->name);
2769                                 return -EINVAL;
2770                         }
2771                         }
2772                         break;
2773                 case FLOW_ACTION_MARK: {
2774                         u32 mark = act->mark;
2775
2776                         if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2777                                 NL_SET_ERR_MSG_MOD(extack,
2778                                                    "Bad flow mark - only 16 bit is supported");
2779                                 return -EINVAL;
2780                         }
2781
2782                         attr->flow_tag = mark;
2783                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2784                         }
2785                         break;
2786                 default:
2787                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2788                         return -EOPNOTSUPP;
2789                 }
2790         }
2791
2792         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2793             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2794                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
2795                                             parse_attr, hdrs, &action, extack);
2796                 if (err)
2797                         return err;
2798                 /* in case all pedit actions are skipped, remove the MOD_HDR
2799                  * flag.
2800                  */
2801                 if (parse_attr->num_mod_hdr_actions == 0) {
2802                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2803                         kfree(parse_attr->mod_hdr_actions);
2804                 }
2805         }
2806
2807         attr->action = action;
2808         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
2809                 return -EOPNOTSUPP;
2810
2811         return 0;
2812 }
2813
2814 struct encap_key {
2815         const struct ip_tunnel_key *ip_tun_key;
2816         struct mlx5e_tc_tunnel *tc_tunnel;
2817 };
2818
2819 static inline int cmp_encap_info(struct encap_key *a,
2820                                  struct encap_key *b)
2821 {
2822         return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
2823                a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
2824 }
2825
2826 static inline int hash_encap_info(struct encap_key *key)
2827 {
2828         return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
2829                      key->tc_tunnel->tunnel_type);
2830 }
2831
2832
2833 static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2834                                   struct net_device *peer_netdev)
2835 {
2836         struct mlx5e_priv *peer_priv;
2837
2838         peer_priv = netdev_priv(peer_netdev);
2839
2840         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2841                 mlx5e_eswitch_rep(priv->netdev) &&
2842                 mlx5e_eswitch_rep(peer_netdev) &&
2843                 same_hw_devs(priv, peer_priv));
2844 }
2845
2846
2847
2848 bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
2849 {
2850         return refcount_inc_not_zero(&e->refcnt);
2851 }
2852
2853 static struct mlx5e_encap_entry *
2854 mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
2855                 uintptr_t hash_key)
2856 {
2857         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2858         struct mlx5e_encap_entry *e;
2859         struct encap_key e_key;
2860
2861         hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2862                                    encap_hlist, hash_key) {
2863                 e_key.ip_tun_key = &e->tun_info->key;
2864                 e_key.tc_tunnel = e->tunnel;
2865                 if (!cmp_encap_info(&e_key, key) &&
2866                     mlx5e_encap_take(e))
2867                         return e;
2868         }
2869
2870         return NULL;
2871 }
2872
2873 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2874                               struct mlx5e_tc_flow *flow,
2875                               struct net_device *mirred_dev,
2876                               int out_index,
2877                               struct netlink_ext_ack *extack,
2878                               struct net_device **encap_dev,
2879                               bool *encap_valid)
2880 {
2881         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2882         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2883         struct mlx5e_tc_flow_parse_attr *parse_attr;
2884         const struct ip_tunnel_info *tun_info;
2885         struct encap_key key;
2886         struct mlx5e_encap_entry *e;
2887         unsigned short family;
2888         uintptr_t hash_key;
2889         int err = 0;
2890
2891         parse_attr = attr->parse_attr;
2892         tun_info = parse_attr->tun_info[out_index];
2893         family = ip_tunnel_info_af(tun_info);
2894         key.ip_tun_key = &tun_info->key;
2895         key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
2896         if (!key.tc_tunnel) {
2897                 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
2898                 return -EOPNOTSUPP;
2899         }
2900
2901         hash_key = hash_encap_info(&key);
2902
2903         mutex_lock(&esw->offloads.encap_tbl_lock);
2904         e = mlx5e_encap_get(priv, &key, hash_key);
2905
2906         /* must verify if encap is valid or not */
2907         if (e) {
2908                 mutex_unlock(&esw->offloads.encap_tbl_lock);
2909                 wait_for_completion(&e->res_ready);
2910
2911                 /* Protect against concurrent neigh update. */
2912                 mutex_lock(&esw->offloads.encap_tbl_lock);
2913                 if (e->compl_result) {
2914                         err = -EREMOTEIO;
2915                         goto out_err;
2916                 }
2917                 goto attach_flow;
2918         }
2919
2920         e = kzalloc(sizeof(*e), GFP_KERNEL);
2921         if (!e) {
2922                 err = -ENOMEM;
2923                 goto out_err;
2924         }
2925
2926         refcount_set(&e->refcnt, 1);
2927         init_completion(&e->res_ready);
2928
2929         e->tun_info = tun_info;
2930         err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2931         if (err) {
2932                 kfree(e);
2933                 e = NULL;
2934                 goto out_err;
2935         }
2936
2937         INIT_LIST_HEAD(&e->flows);
2938         hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2939         mutex_unlock(&esw->offloads.encap_tbl_lock);
2940
2941         if (family == AF_INET)
2942                 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
2943         else if (family == AF_INET6)
2944                 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
2945
2946         /* Protect against concurrent neigh update. */
2947         mutex_lock(&esw->offloads.encap_tbl_lock);
2948         complete_all(&e->res_ready);
2949         if (err) {
2950                 e->compl_result = err;
2951                 goto out_err;
2952         }
2953
2954 attach_flow:
2955         flow->encaps[out_index].e = e;
2956         list_add(&flow->encaps[out_index].list, &e->flows);
2957         flow->encaps[out_index].index = out_index;
2958         *encap_dev = e->out_dev;
2959         if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2960                 attr->dests[out_index].encap_id = e->encap_id;
2961                 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
2962                 *encap_valid = true;
2963         } else {
2964                 *encap_valid = false;
2965         }
2966         mutex_unlock(&esw->offloads.encap_tbl_lock);
2967
2968         return err;
2969
2970 out_err:
2971         mutex_unlock(&esw->offloads.encap_tbl_lock);
2972         if (e)
2973                 mlx5e_encap_put(priv, e);
2974         return err;
2975 }
2976
2977 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2978                                 const struct flow_action_entry *act,
2979                                 struct mlx5_esw_flow_attr *attr,
2980                                 u32 *action)
2981 {
2982         u8 vlan_idx = attr->total_vlan;
2983
2984         if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2985                 return -EOPNOTSUPP;
2986
2987         switch (act->id) {
2988         case FLOW_ACTION_VLAN_POP:
2989                 if (vlan_idx) {
2990                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2991                                                                  MLX5_FS_VLAN_DEPTH))
2992                                 return -EOPNOTSUPP;
2993
2994                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2995                 } else {
2996                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2997                 }
2998                 break;
2999         case FLOW_ACTION_VLAN_PUSH:
3000                 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3001                 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3002                 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3003                 if (!attr->vlan_proto[vlan_idx])
3004                         attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3005
3006                 if (vlan_idx) {
3007                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3008                                                                  MLX5_FS_VLAN_DEPTH))
3009                                 return -EOPNOTSUPP;
3010
3011                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3012                 } else {
3013                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3014                             (act->vlan.proto != htons(ETH_P_8021Q) ||
3015                              act->vlan.prio))
3016                                 return -EOPNOTSUPP;
3017
3018                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3019                 }
3020                 break;
3021         default:
3022                 return -EINVAL;
3023         }
3024
3025         attr->total_vlan = vlan_idx + 1;
3026
3027         return 0;
3028 }
3029
3030 static int add_vlan_push_action(struct mlx5e_priv *priv,
3031                                 struct mlx5_esw_flow_attr *attr,
3032                                 struct net_device **out_dev,
3033                                 u32 *action)
3034 {
3035         struct net_device *vlan_dev = *out_dev;
3036         struct flow_action_entry vlan_act = {
3037                 .id = FLOW_ACTION_VLAN_PUSH,
3038                 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3039                 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3040                 .vlan.prio = 0,
3041         };
3042         int err;
3043
3044         err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3045         if (err)
3046                 return err;
3047
3048         *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3049                                         dev_get_iflink(vlan_dev));
3050         if (is_vlan_dev(*out_dev))
3051                 err = add_vlan_push_action(priv, attr, out_dev, action);
3052
3053         return err;
3054 }
3055
3056 static int add_vlan_pop_action(struct mlx5e_priv *priv,
3057                                struct mlx5_esw_flow_attr *attr,
3058                                u32 *action)
3059 {
3060         int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev);
3061         struct flow_action_entry vlan_act = {
3062                 .id = FLOW_ACTION_VLAN_POP,
3063         };
3064         int err = 0;
3065
3066         while (nest_level--) {
3067                 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3068                 if (err)
3069                         return err;
3070         }
3071
3072         return err;
3073 }
3074
3075 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3076                                     struct net_device *out_dev)
3077 {
3078         if (is_merged_eswitch_dev(priv, out_dev))
3079                 return true;
3080
3081         return mlx5e_eswitch_rep(out_dev) &&
3082                same_hw_devs(priv, netdev_priv(out_dev));
3083 }
3084
3085 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3086                                 struct flow_action *flow_action,
3087                                 struct mlx5e_tc_flow *flow,
3088                                 struct netlink_ext_ack *extack)
3089 {
3090         struct pedit_headers_action hdrs[2] = {};
3091         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3092         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3093         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3094         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3095         const struct ip_tunnel_info *info = NULL;
3096         const struct flow_action_entry *act;
3097         bool encap = false;
3098         u32 action = 0;
3099         int err, i;
3100
3101         if (!flow_action_has_entries(flow_action))
3102                 return -EINVAL;
3103
3104         flow_action_for_each(i, act, flow_action) {
3105                 switch (act->id) {
3106                 case FLOW_ACTION_DROP:
3107                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3108                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3109                         break;
3110                 case FLOW_ACTION_MANGLE:
3111                 case FLOW_ACTION_ADD:
3112                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3113                                                     parse_attr, hdrs, extack);
3114                         if (err)
3115                                 return err;
3116
3117                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3118                         attr->split_count = attr->out_count;
3119                         break;
3120                 case FLOW_ACTION_CSUM:
3121                         if (csum_offload_supported(priv, action,
3122                                                    act->csum_flags, extack))
3123                                 break;
3124
3125                         return -EOPNOTSUPP;
3126                 case FLOW_ACTION_REDIRECT:
3127                 case FLOW_ACTION_MIRRED: {
3128                         struct mlx5e_priv *out_priv;
3129                         struct net_device *out_dev;
3130
3131                         out_dev = act->dev;
3132                         if (!out_dev) {
3133                                 /* out_dev is NULL when filters with
3134                                  * non-existing mirred device are replayed to
3135                                  * the driver.
3136                                  */
3137                                 return -EINVAL;
3138                         }
3139
3140                         if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3141                                 NL_SET_ERR_MSG_MOD(extack,
3142                                                    "can't support more output ports, can't offload forwarding");
3143                                 pr_err("can't support more than %d output ports, can't offload forwarding\n",
3144                                        attr->out_count);
3145                                 return -EOPNOTSUPP;
3146                         }
3147
3148                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3149                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3150                         if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3151                                 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3152                                 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3153                                 struct net_device *uplink_upper;
3154
3155                                 rcu_read_lock();
3156                                 uplink_upper =
3157                                         netdev_master_upper_dev_get_rcu(uplink_dev);
3158                                 if (uplink_upper &&
3159                                     netif_is_lag_master(uplink_upper) &&
3160                                     uplink_upper == out_dev)
3161                                         out_dev = uplink_dev;
3162                                 rcu_read_unlock();
3163
3164                                 if (is_vlan_dev(out_dev)) {
3165                                         err = add_vlan_push_action(priv, attr,
3166                                                                    &out_dev,
3167                                                                    &action);
3168                                         if (err)
3169                                                 return err;
3170                                 }
3171
3172                                 if (is_vlan_dev(parse_attr->filter_dev)) {
3173                                         err = add_vlan_pop_action(priv, attr,
3174                                                                   &action);
3175                                         if (err)
3176                                                 return err;
3177                                 }
3178
3179                                 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3180                                         NL_SET_ERR_MSG_MOD(extack,
3181                                                            "devices are not on same switch HW, can't offload forwarding");
3182                                         pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3183                                                priv->netdev->name, out_dev->name);
3184                                         return -EOPNOTSUPP;
3185                                 }
3186
3187                                 out_priv = netdev_priv(out_dev);
3188                                 rpriv = out_priv->ppriv;
3189                                 attr->dests[attr->out_count].rep = rpriv->rep;
3190                                 attr->dests[attr->out_count].mdev = out_priv->mdev;
3191                                 attr->out_count++;
3192                         } else if (encap) {
3193                                 parse_attr->mirred_ifindex[attr->out_count] =
3194                                         out_dev->ifindex;
3195                                 parse_attr->tun_info[attr->out_count] = info;
3196                                 encap = false;
3197                                 attr->dests[attr->out_count].flags |=
3198                                         MLX5_ESW_DEST_ENCAP;
3199                                 attr->out_count++;
3200                                 /* attr->dests[].rep is resolved when we
3201                                  * handle encap
3202                                  */
3203                         } else if (parse_attr->filter_dev != priv->netdev) {
3204                                 /* All mlx5 devices are called to configure
3205                                  * high level device filters. Therefore, the
3206                                  * *attempt* to  install a filter on invalid
3207                                  * eswitch should not trigger an explicit error
3208                                  */
3209                                 return -EINVAL;
3210                         } else {
3211                                 NL_SET_ERR_MSG_MOD(extack,
3212                                                    "devices are not on same switch HW, can't offload forwarding");
3213                                 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3214                                        priv->netdev->name, out_dev->name);
3215                                 return -EINVAL;
3216                         }
3217                         }
3218                         break;
3219                 case FLOW_ACTION_TUNNEL_ENCAP:
3220                         info = act->tunnel;
3221                         if (info)
3222                                 encap = true;
3223                         else
3224                                 return -EOPNOTSUPP;
3225
3226                         break;
3227                 case FLOW_ACTION_VLAN_PUSH:
3228                 case FLOW_ACTION_VLAN_POP:
3229                         if (act->id == FLOW_ACTION_VLAN_PUSH &&
3230                             (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3231                                 /* Replace vlan pop+push with vlan modify */
3232                                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3233                                 err = add_vlan_rewrite_action(priv,
3234                                                               MLX5_FLOW_NAMESPACE_FDB,
3235                                                               act, parse_attr, hdrs,
3236                                                               &action, extack);
3237                         } else {
3238                                 err = parse_tc_vlan_action(priv, act, attr, &action);
3239                         }
3240                         if (err)
3241                                 return err;
3242
3243                         attr->split_count = attr->out_count;
3244                         break;
3245                 case FLOW_ACTION_VLAN_MANGLE:
3246                         err = add_vlan_rewrite_action(priv,
3247                                                       MLX5_FLOW_NAMESPACE_FDB,
3248                                                       act, parse_attr, hdrs,
3249                                                       &action, extack);
3250                         if (err)
3251                                 return err;
3252
3253                         attr->split_count = attr->out_count;
3254                         break;
3255                 case FLOW_ACTION_TUNNEL_DECAP:
3256                         action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
3257                         break;
3258                 case FLOW_ACTION_GOTO: {
3259                         u32 dest_chain = act->chain_index;
3260                         u32 max_chain = mlx5_eswitch_get_chain_range(esw);
3261
3262                         if (dest_chain <= attr->chain) {
3263                                 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3264                                 return -EOPNOTSUPP;
3265                         }
3266                         if (dest_chain > max_chain) {
3267                                 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3268                                 return -EOPNOTSUPP;
3269                         }
3270                         action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3271                         attr->dest_chain = dest_chain;
3272                         break;
3273                         }
3274                 default:
3275                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3276                         return -EOPNOTSUPP;
3277                 }
3278         }
3279
3280         if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3281             action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3282                 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3283                  * tag rewrite.
3284                  */
3285                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3286                 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3287                                                        &action, extack);
3288                 if (err)
3289                         return err;
3290         }
3291
3292         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3293             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3294                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3295                                             parse_attr, hdrs, &action, extack);
3296                 if (err)
3297                         return err;
3298                 /* in case all pedit actions are skipped, remove the MOD_HDR
3299                  * flag. we might have set split_count either by pedit or
3300                  * pop/push. if there is no pop/push either, reset it too.
3301                  */
3302                 if (parse_attr->num_mod_hdr_actions == 0) {
3303                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3304                         kfree(parse_attr->mod_hdr_actions);
3305                         if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3306                               (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3307                                 attr->split_count = 0;
3308                 }
3309         }
3310
3311         attr->action = action;
3312         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3313                 return -EOPNOTSUPP;
3314
3315         if (attr->dest_chain) {
3316                 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3317                         NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3318                         return -EOPNOTSUPP;
3319                 }
3320                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3321         }
3322
3323         if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3324                 NL_SET_ERR_MSG_MOD(extack,
3325                                    "current firmware doesn't support split rule for port mirroring");
3326                 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3327                 return -EOPNOTSUPP;
3328         }
3329
3330         return 0;
3331 }
3332
3333 static void get_flags(int flags, unsigned long *flow_flags)
3334 {
3335         unsigned long __flow_flags = 0;
3336
3337         if (flags & MLX5_TC_FLAG(INGRESS))
3338                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3339         if (flags & MLX5_TC_FLAG(EGRESS))
3340                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
3341
3342         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3343                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3344         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3345                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3346
3347         *flow_flags = __flow_flags;
3348 }
3349
3350 static const struct rhashtable_params tc_ht_params = {
3351         .head_offset = offsetof(struct mlx5e_tc_flow, node),
3352         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3353         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3354         .automatic_shrinking = true,
3355 };
3356
3357 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3358                                     unsigned long flags)
3359 {
3360         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3361         struct mlx5e_rep_priv *uplink_rpriv;
3362
3363         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
3364                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3365                 return &uplink_rpriv->uplink_priv.tc_ht;
3366         } else /* NIC offload */
3367                 return &priv->fs.tc.ht;
3368 }
3369
3370 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3371 {
3372         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3373         bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
3374                 flow_flag_test(flow, INGRESS);
3375         bool act_is_encap = !!(attr->action &
3376                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3377         bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3378                                                 MLX5_DEVCOM_ESW_OFFLOADS);
3379
3380         if (!esw_paired)
3381                 return false;
3382
3383         if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3384              mlx5_lag_is_multipath(attr->in_mdev)) &&
3385             (is_rep_ingress || act_is_encap))
3386                 return true;
3387
3388         return false;
3389 }
3390
3391 static int
3392 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
3393                  struct flow_cls_offload *f, unsigned long flow_flags,
3394                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
3395                  struct mlx5e_tc_flow **__flow)
3396 {
3397         struct mlx5e_tc_flow_parse_attr *parse_attr;
3398         struct mlx5e_tc_flow *flow;
3399         int out_index, err;
3400
3401         flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
3402         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3403         if (!parse_attr || !flow) {
3404                 err = -ENOMEM;
3405                 goto err_free;
3406         }
3407
3408         flow->cookie = f->cookie;
3409         flow->flags = flow_flags;
3410         flow->priv = priv;
3411         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3412                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3413         INIT_LIST_HEAD(&flow->mod_hdr);
3414         INIT_LIST_HEAD(&flow->hairpin);
3415         refcount_set(&flow->refcnt, 1);
3416
3417         *__flow = flow;
3418         *__parse_attr = parse_attr;
3419
3420         return 0;
3421
3422 err_free:
3423         kfree(flow);
3424         kvfree(parse_attr);
3425         return err;
3426 }
3427
3428 static void
3429 mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3430                          struct mlx5e_priv *priv,
3431                          struct mlx5e_tc_flow_parse_attr *parse_attr,
3432                          struct flow_cls_offload *f,
3433                          struct mlx5_eswitch_rep *in_rep,
3434                          struct mlx5_core_dev *in_mdev)
3435 {
3436         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3437
3438         esw_attr->parse_attr = parse_attr;
3439         esw_attr->chain = f->common.chain_index;
3440         esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
3441
3442         esw_attr->in_rep = in_rep;
3443         esw_attr->in_mdev = in_mdev;
3444
3445         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3446             MLX5_COUNTER_SOURCE_ESWITCH)
3447                 esw_attr->counter_dev = in_mdev;
3448         else
3449                 esw_attr->counter_dev = priv->mdev;
3450 }
3451
3452 static struct mlx5e_tc_flow *
3453 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3454                      struct flow_cls_offload *f,
3455                      unsigned long flow_flags,
3456                      struct net_device *filter_dev,
3457                      struct mlx5_eswitch_rep *in_rep,
3458                      struct mlx5_core_dev *in_mdev)
3459 {
3460         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3461         struct netlink_ext_ack *extack = f->common.extack;
3462         struct mlx5e_tc_flow_parse_attr *parse_attr;
3463         struct mlx5e_tc_flow *flow;
3464         int attr_size, err;
3465
3466         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3467         attr_size  = sizeof(struct mlx5_esw_flow_attr);
3468         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3469                                &parse_attr, &flow);
3470         if (err)
3471                 goto out;
3472
3473         parse_attr->filter_dev = filter_dev;
3474         mlx5e_flow_esw_attr_init(flow->esw_attr,
3475                                  priv, parse_attr,
3476                                  f, in_rep, in_mdev);
3477
3478         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3479                                f, filter_dev);
3480         if (err)
3481                 goto err_free;
3482
3483         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
3484         if (err)
3485                 goto err_free;
3486
3487         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
3488         if (err) {
3489                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3490                         goto err_free;
3491
3492                 add_unready_flow(flow);
3493         }
3494
3495         return flow;
3496
3497 err_free:
3498         mlx5e_flow_put(priv, flow);
3499 out:
3500         return ERR_PTR(err);
3501 }
3502
3503 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
3504                                       struct mlx5e_tc_flow *flow,
3505                                       unsigned long flow_flags)
3506 {
3507         struct mlx5e_priv *priv = flow->priv, *peer_priv;
3508         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3509         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3510         struct mlx5e_tc_flow_parse_attr *parse_attr;
3511         struct mlx5e_rep_priv *peer_urpriv;
3512         struct mlx5e_tc_flow *peer_flow;
3513         struct mlx5_core_dev *in_mdev;
3514         int err = 0;
3515
3516         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3517         if (!peer_esw)
3518                 return -ENODEV;
3519
3520         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3521         peer_priv = netdev_priv(peer_urpriv->netdev);
3522
3523         /* in_mdev is assigned of which the packet originated from.
3524          * So packets redirected to uplink use the same mdev of the
3525          * original flow and packets redirected from uplink use the
3526          * peer mdev.
3527          */
3528         if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
3529                 in_mdev = peer_priv->mdev;
3530         else
3531                 in_mdev = priv->mdev;
3532
3533         parse_attr = flow->esw_attr->parse_attr;
3534         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
3535                                          parse_attr->filter_dev,
3536                                          flow->esw_attr->in_rep, in_mdev);
3537         if (IS_ERR(peer_flow)) {
3538                 err = PTR_ERR(peer_flow);
3539                 goto out;
3540         }
3541
3542         flow->peer_flow = peer_flow;
3543         flow_flag_set(flow, DUP);
3544         mutex_lock(&esw->offloads.peer_mutex);
3545         list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3546         mutex_unlock(&esw->offloads.peer_mutex);
3547
3548 out:
3549         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3550         return err;
3551 }
3552
3553 static int
3554 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3555                    struct flow_cls_offload *f,
3556                    unsigned long flow_flags,
3557                    struct net_device *filter_dev,
3558                    struct mlx5e_tc_flow **__flow)
3559 {
3560         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3561         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3562         struct mlx5_core_dev *in_mdev = priv->mdev;
3563         struct mlx5e_tc_flow *flow;
3564         int err;
3565
3566         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3567                                     in_mdev);
3568         if (IS_ERR(flow))
3569                 return PTR_ERR(flow);
3570
3571         if (is_peer_flow_needed(flow)) {
3572                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
3573                 if (err) {
3574                         mlx5e_tc_del_fdb_flow(priv, flow);
3575                         goto out;
3576                 }
3577         }
3578
3579         *__flow = flow;
3580
3581         return 0;
3582
3583 out:
3584         return err;
3585 }
3586
3587 static int
3588 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3589                    struct flow_cls_offload *f,
3590                    unsigned long flow_flags,
3591                    struct net_device *filter_dev,
3592                    struct mlx5e_tc_flow **__flow)
3593 {
3594         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
3595         struct netlink_ext_ack *extack = f->common.extack;
3596         struct mlx5e_tc_flow_parse_attr *parse_attr;
3597         struct mlx5e_tc_flow *flow;
3598         int attr_size, err;
3599
3600         /* multi-chain not supported for NIC rules */
3601         if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3602                 return -EOPNOTSUPP;
3603
3604         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
3605         attr_size  = sizeof(struct mlx5_nic_flow_attr);
3606         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3607                                &parse_attr, &flow);
3608         if (err)
3609                 goto out;
3610
3611         parse_attr->filter_dev = filter_dev;
3612         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3613                                f, filter_dev);
3614         if (err)
3615                 goto err_free;
3616
3617         err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
3618         if (err)
3619                 goto err_free;
3620
3621         err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3622         if (err)
3623                 goto err_free;
3624
3625         flow_flag_set(flow, OFFLOADED);
3626         kvfree(parse_attr);
3627         *__flow = flow;
3628
3629         return 0;
3630
3631 err_free:
3632         mlx5e_flow_put(priv, flow);
3633         kvfree(parse_attr);
3634 out:
3635         return err;
3636 }
3637
3638 static int
3639 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3640                   struct flow_cls_offload *f,
3641                   unsigned long flags,
3642                   struct net_device *filter_dev,
3643                   struct mlx5e_tc_flow **flow)
3644 {
3645         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3646         unsigned long flow_flags;
3647         int err;
3648
3649         get_flags(flags, &flow_flags);
3650
3651         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3652                 return -EOPNOTSUPP;
3653
3654         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
3655                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3656                                          filter_dev, flow);
3657         else
3658                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3659                                          filter_dev, flow);
3660
3661         return err;
3662 }
3663
3664 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
3665                            struct flow_cls_offload *f, unsigned long flags)
3666 {
3667         struct netlink_ext_ack *extack = f->common.extack;
3668         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3669         struct mlx5e_tc_flow *flow;
3670         int err = 0;
3671
3672         rcu_read_lock();
3673         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3674         rcu_read_unlock();
3675         if (flow) {
3676                 NL_SET_ERR_MSG_MOD(extack,
3677                                    "flow cookie already exists, ignoring");
3678                 netdev_warn_once(priv->netdev,
3679                                  "flow cookie %lx already exists, ignoring\n",
3680                                  f->cookie);
3681                 err = -EEXIST;
3682                 goto out;
3683         }
3684
3685         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
3686         if (err)
3687                 goto out;
3688
3689         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
3690         if (err)
3691                 goto err_free;
3692
3693         return 0;
3694
3695 err_free:
3696         mlx5e_flow_put(priv, flow);
3697 out:
3698         return err;
3699 }
3700
3701 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3702 {
3703         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3704         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
3705
3706         return flow_flag_test(flow, INGRESS) == dir_ingress &&
3707                 flow_flag_test(flow, EGRESS) == dir_egress;
3708 }
3709
3710 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
3711                         struct flow_cls_offload *f, unsigned long flags)
3712 {
3713         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3714         struct mlx5e_tc_flow *flow;
3715         int err;
3716
3717         rcu_read_lock();
3718         flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3719         if (!flow || !same_flow_direction(flow, flags)) {
3720                 err = -EINVAL;
3721                 goto errout;
3722         }
3723
3724         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3725          * set.
3726          */
3727         if (flow_flag_test_and_set(flow, DELETED)) {
3728                 err = -EINVAL;
3729                 goto errout;
3730         }
3731         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
3732         rcu_read_unlock();
3733
3734         mlx5e_flow_put(priv, flow);
3735
3736         return 0;
3737
3738 errout:
3739         rcu_read_unlock();
3740         return err;
3741 }
3742
3743 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
3744                        struct flow_cls_offload *f, unsigned long flags)
3745 {
3746         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3747         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
3748         struct mlx5_eswitch *peer_esw;
3749         struct mlx5e_tc_flow *flow;
3750         struct mlx5_fc *counter;
3751         u64 lastuse = 0;
3752         u64 packets = 0;
3753         u64 bytes = 0;
3754         int err = 0;
3755
3756         rcu_read_lock();
3757         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
3758                                                 tc_ht_params));
3759         rcu_read_unlock();
3760         if (IS_ERR(flow))
3761                 return PTR_ERR(flow);
3762
3763         if (!same_flow_direction(flow, flags)) {
3764                 err = -EINVAL;
3765                 goto errout;
3766         }
3767
3768         if (mlx5e_is_offloaded_flow(flow)) {
3769                 counter = mlx5e_tc_get_counter(flow);
3770                 if (!counter)
3771                         goto errout;
3772
3773                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3774         }
3775
3776         /* Under multipath it's possible for one rule to be currently
3777          * un-offloaded while the other rule is offloaded.
3778          */
3779         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3780         if (!peer_esw)
3781                 goto out;
3782
3783         if (flow_flag_test(flow, DUP) &&
3784             flow_flag_test(flow->peer_flow, OFFLOADED)) {
3785                 u64 bytes2;
3786                 u64 packets2;
3787                 u64 lastuse2;
3788
3789                 counter = mlx5e_tc_get_counter(flow->peer_flow);
3790                 if (!counter)
3791                         goto no_peer_counter;
3792                 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3793
3794                 bytes += bytes2;
3795                 packets += packets2;
3796                 lastuse = max_t(u64, lastuse, lastuse2);
3797         }
3798
3799 no_peer_counter:
3800         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3801 out:
3802         flow_stats_update(&f->stats, bytes, packets, lastuse);
3803 errout:
3804         mlx5e_flow_put(priv, flow);
3805         return err;
3806 }
3807
3808 static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
3809                                struct netlink_ext_ack *extack)
3810 {
3811         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3812         struct mlx5_eswitch *esw;
3813         u16 vport_num;
3814         u32 rate_mbps;
3815         int err;
3816
3817         esw = priv->mdev->priv.eswitch;
3818         /* rate is given in bytes/sec.
3819          * First convert to bits/sec and then round to the nearest mbit/secs.
3820          * mbit means million bits.
3821          * Moreover, if rate is non zero we choose to configure to a minimum of
3822          * 1 mbit/sec.
3823          */
3824         rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
3825         vport_num = rpriv->rep->vport;
3826
3827         err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
3828         if (err)
3829                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
3830
3831         return err;
3832 }
3833
3834 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
3835                                         struct flow_action *flow_action,
3836                                         struct netlink_ext_ack *extack)
3837 {
3838         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3839         const struct flow_action_entry *act;
3840         int err;
3841         int i;
3842
3843         if (!flow_action_has_entries(flow_action)) {
3844                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
3845                 return -EINVAL;
3846         }
3847
3848         if (!flow_offload_has_one_action(flow_action)) {
3849                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
3850                 return -EOPNOTSUPP;
3851         }
3852
3853         flow_action_for_each(i, act, flow_action) {
3854                 switch (act->id) {
3855                 case FLOW_ACTION_POLICE:
3856                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
3857                         if (err)
3858                                 return err;
3859
3860                         rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
3861                         break;
3862                 default:
3863                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
3864                         return -EOPNOTSUPP;
3865                 }
3866         }
3867
3868         return 0;
3869 }
3870
3871 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
3872                                 struct tc_cls_matchall_offload *ma)
3873 {
3874         struct netlink_ext_ack *extack = ma->common.extack;
3875         int prio = TC_H_MAJ(ma->common.prio) >> 16;
3876
3877         if (prio != 1) {
3878                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
3879                 return -EINVAL;
3880         }
3881
3882         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
3883 }
3884
3885 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
3886                              struct tc_cls_matchall_offload *ma)
3887 {
3888         struct netlink_ext_ack *extack = ma->common.extack;
3889
3890         return apply_police_params(priv, 0, extack);
3891 }
3892
3893 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
3894                              struct tc_cls_matchall_offload *ma)
3895 {
3896         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3897         struct rtnl_link_stats64 cur_stats;
3898         u64 dbytes;
3899         u64 dpkts;
3900
3901         cur_stats = priv->stats.vf_vport;
3902         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
3903         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
3904         rpriv->prev_vf_vport_stats = cur_stats;
3905         flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
3906 }
3907
3908 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3909                                               struct mlx5e_priv *peer_priv)
3910 {
3911         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3912         struct mlx5e_hairpin_entry *hpe, *tmp;
3913         LIST_HEAD(init_wait_list);
3914         u16 peer_vhca_id;
3915         int bkt;
3916
3917         if (!same_hw_devs(priv, peer_priv))
3918                 return;
3919
3920         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3921
3922         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
3923         hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
3924                 if (refcount_inc_not_zero(&hpe->refcnt))
3925                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
3926         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
3927
3928         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
3929                 wait_for_completion(&hpe->res_ready);
3930                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
3931                         hpe->hp->pair->peer_gone = true;
3932
3933                 mlx5e_hairpin_put(priv, hpe);
3934         }
3935 }
3936
3937 static int mlx5e_tc_netdev_event(struct notifier_block *this,
3938                                  unsigned long event, void *ptr)
3939 {
3940         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3941         struct mlx5e_flow_steering *fs;
3942         struct mlx5e_priv *peer_priv;
3943         struct mlx5e_tc_table *tc;
3944         struct mlx5e_priv *priv;
3945
3946         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3947             event != NETDEV_UNREGISTER ||
3948             ndev->reg_state == NETREG_REGISTERED)
3949                 return NOTIFY_DONE;
3950
3951         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3952         fs = container_of(tc, struct mlx5e_flow_steering, tc);
3953         priv = container_of(fs, struct mlx5e_priv, fs);
3954         peer_priv = netdev_priv(ndev);
3955         if (priv == peer_priv ||
3956             !(priv->netdev->features & NETIF_F_HW_TC))
3957                 return NOTIFY_DONE;
3958
3959         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3960
3961         return NOTIFY_DONE;
3962 }
3963
3964 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
3965 {
3966         struct mlx5e_tc_table *tc = &priv->fs.tc;
3967         int err;
3968
3969         mutex_init(&tc->t_lock);
3970         mutex_init(&tc->mod_hdr.lock);
3971         hash_init(tc->mod_hdr.hlist);
3972         mutex_init(&tc->hairpin_tbl_lock);
3973         hash_init(tc->hairpin_tbl);
3974
3975         err = rhashtable_init(&tc->ht, &tc_ht_params);
3976         if (err)
3977                 return err;
3978
3979         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3980         if (register_netdevice_notifier(&tc->netdevice_nb)) {
3981                 tc->netdevice_nb.notifier_call = NULL;
3982                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3983         }
3984
3985         return err;
3986 }
3987
3988 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3989 {
3990         struct mlx5e_tc_flow *flow = ptr;
3991         struct mlx5e_priv *priv = flow->priv;
3992
3993         mlx5e_tc_del_flow(priv, flow);
3994         kfree(flow);
3995 }
3996
3997 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
3998 {
3999         struct mlx5e_tc_table *tc = &priv->fs.tc;
4000
4001         if (tc->netdevice_nb.notifier_call)
4002                 unregister_netdevice_notifier(&tc->netdevice_nb);
4003
4004         mutex_destroy(&tc->mod_hdr.lock);
4005         mutex_destroy(&tc->hairpin_tbl_lock);
4006
4007         rhashtable_destroy(&tc->ht);
4008
4009         if (!IS_ERR_OR_NULL(tc->t)) {
4010                 mlx5_destroy_flow_table(tc->t);
4011                 tc->t = NULL;
4012         }
4013         mutex_destroy(&tc->t_lock);
4014 }
4015
4016 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4017 {
4018         return rhashtable_init(tc_ht, &tc_ht_params);
4019 }
4020
4021 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4022 {
4023         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4024 }
4025
4026 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4027 {
4028         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4029
4030         return atomic_read(&tc_ht->nelems);
4031 }
4032
4033 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4034 {
4035         struct mlx5e_tc_flow *flow, *tmp;
4036
4037         list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4038                 __mlx5e_tc_del_fdb_peer_flow(flow);
4039 }
4040
4041 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4042 {
4043         struct mlx5_rep_uplink_priv *rpriv =
4044                 container_of(work, struct mlx5_rep_uplink_priv,
4045                              reoffload_flows_work);
4046         struct mlx5e_tc_flow *flow, *tmp;
4047
4048         mutex_lock(&rpriv->unready_flows_lock);
4049         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4050                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4051                         unready_flow_del(flow);
4052         }
4053         mutex_unlock(&rpriv->unready_flows_lock);
4054 }