2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/tcp.h>
34 #include <linux/if_vlan.h>
36 #include "ipoib/ipoib.h"
37 #include "en_accel/ipsec_rxtx.h"
39 #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
40 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
43 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
44 struct mlx5e_sq_dma *dma)
47 case MLX5E_DMA_MAP_SINGLE:
48 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
50 case MLX5E_DMA_MAP_PAGE:
51 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
54 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
58 static inline void mlx5e_dma_push(struct mlx5e_txqsq *sq,
61 enum mlx5e_dma_map_type map_type)
63 u32 i = sq->dma_fifo_pc & sq->dma_fifo_mask;
65 sq->db.dma_fifo[i].addr = addr;
66 sq->db.dma_fifo[i].size = size;
67 sq->db.dma_fifo[i].type = map_type;
71 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i)
73 return &sq->db.dma_fifo[i & sq->dma_fifo_mask];
76 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma)
80 for (i = 0; i < num_dma; i++) {
81 struct mlx5e_sq_dma *last_pushed_dma =
82 mlx5e_dma_get(sq, --sq->dma_fifo_pc);
84 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
88 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
89 void *accel_priv, select_queue_fallback_t fallback)
91 struct mlx5e_priv *priv = netdev_priv(dev);
92 int channel_ix = fallback(dev, skb);
96 if (!netdev_get_num_tc(dev))
99 if (skb_vlan_tag_present(skb))
100 up = skb->vlan_tci >> VLAN_PRIO_SHIFT;
102 /* channel_ix can be larger than num_channels since
103 * dev->num_real_tx_queues = num_channels * num_tc
105 num_channels = priv->channels.params.num_channels;
106 if (channel_ix >= num_channels)
107 channel_ix = reciprocal_scale(channel_ix, num_channels);
109 return priv->channel_tc2txq[channel_ix][up];
112 static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb)
114 #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
116 return max(skb_network_offset(skb), MLX5E_MIN_INLINE);
119 static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb)
121 struct flow_keys keys;
123 if (skb_transport_header_was_set(skb))
124 return skb_transport_offset(skb);
125 else if (skb_flow_dissect_flow_keys(skb, &keys, 0))
126 return keys.control.thoff;
128 return mlx5e_skb_l2_header_offset(skb);
131 static inline unsigned int mlx5e_calc_min_inline(enum mlx5_inline_modes mode,
137 case MLX5_INLINE_MODE_NONE:
139 case MLX5_INLINE_MODE_TCP_UDP:
140 hlen = eth_get_headlen(skb->data, skb_headlen(skb));
141 if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb))
144 case MLX5_INLINE_MODE_IP:
145 /* When transport header is set to zero, it means no transport
146 * header. When transport header is set to 0xff's, it means
147 * transport header wasn't set.
149 if (skb_transport_offset(skb))
150 return mlx5e_skb_l3_header_offset(skb);
152 case MLX5_INLINE_MODE_L2:
154 return mlx5e_skb_l2_header_offset(skb);
158 static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
159 unsigned int *skb_len,
166 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
167 unsigned char **skb_data,
168 unsigned int *skb_len)
170 struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
171 int cpy1_sz = 2 * ETH_ALEN;
172 int cpy2_sz = ihs - cpy1_sz;
174 memcpy(vhdr, *skb_data, cpy1_sz);
175 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
176 vhdr->h_vlan_proto = skb->vlan_proto;
177 vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
178 memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
179 mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
183 mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
185 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
186 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
187 if (skb->encapsulation) {
188 eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
189 MLX5_ETH_WQE_L4_INNER_CSUM;
190 sq->stats.csum_partial_inner++;
192 eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
195 sq->stats.csum_none++;
199 mlx5e_txwqe_build_eseg_gso(struct mlx5e_txqsq *sq, struct sk_buff *skb,
200 struct mlx5_wqe_eth_seg *eseg, unsigned int *num_bytes)
204 eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
206 if (skb->encapsulation) {
207 ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
208 sq->stats.tso_inner_packets++;
209 sq->stats.tso_inner_bytes += skb->len - ihs;
211 ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
212 sq->stats.tso_packets++;
213 sq->stats.tso_bytes += skb->len - ihs;
216 *num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
221 mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb,
222 unsigned char *skb_data, u16 headlen,
223 struct mlx5_wqe_data_seg *dseg)
225 dma_addr_t dma_addr = 0;
230 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
232 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
235 dseg->addr = cpu_to_be64(dma_addr);
236 dseg->lkey = sq->mkey_be;
237 dseg->byte_count = cpu_to_be32(headlen);
239 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
244 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
245 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
246 int fsz = skb_frag_size(frag);
248 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
250 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
253 dseg->addr = cpu_to_be64(dma_addr);
254 dseg->lkey = sq->mkey_be;
255 dseg->byte_count = cpu_to_be32(fsz);
257 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
266 mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb,
267 u8 opcode, u16 ds_cnt, u32 num_bytes, u8 num_dma,
268 struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg)
270 struct mlx5_wq_cyc *wq = &sq->wq;
273 wi->num_bytes = num_bytes;
274 wi->num_dma = num_dma;
275 wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
278 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
279 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
281 netdev_tx_sent_queue(sq->txq, num_bytes);
283 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
284 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
286 sq->pc += wi->num_wqebbs;
287 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM))) {
288 netif_tx_stop_queue(sq->txq);
292 if (!skb->xmit_more || netif_xmit_stopped(sq->txq))
293 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg);
295 /* fill sq edge with nops to avoid wqe wrap around */
296 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) {
297 sq->db.wqe_info[pi].skb = NULL;
298 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
303 static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
304 struct mlx5e_tx_wqe *wqe, u16 pi)
306 struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
308 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
309 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
311 unsigned char *skb_data = skb->data;
312 unsigned int skb_len = skb->len;
313 u8 opcode = MLX5_OPCODE_SEND;
314 unsigned int num_bytes;
320 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
322 if (skb_is_gso(skb)) {
323 opcode = MLX5_OPCODE_LSO;
324 ihs = mlx5e_txwqe_build_eseg_gso(sq, skb, eseg, &num_bytes);
325 sq->stats.packets += skb_shinfo(skb)->gso_segs;
327 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
328 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
331 sq->stats.bytes += num_bytes;
332 sq->stats.xmit_more += skb->xmit_more;
334 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
336 if (skb_vlan_tag_present(skb)) {
337 mlx5e_insert_vlan(eseg->inline_hdr.start, skb, ihs, &skb_data, &skb_len);
340 memcpy(eseg->inline_hdr.start, skb_data, ihs);
341 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
343 eseg->inline_hdr.sz = cpu_to_be16(ihs);
344 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr.start), MLX5_SEND_WQE_DS);
345 } else if (skb_vlan_tag_present(skb)) {
346 eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN);
347 eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb));
350 headlen = skb_len - skb->data_len;
351 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen,
352 (struct mlx5_wqe_data_seg *)cseg + ds_cnt);
353 if (unlikely(num_dma < 0))
354 goto dma_unmap_wqe_err;
356 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt + num_dma,
357 num_bytes, num_dma, wi, cseg);
363 mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
365 dev_kfree_skb_any(skb);
370 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
372 struct mlx5e_priv *priv = netdev_priv(dev);
373 struct mlx5e_txqsq *sq = priv->txq2sq[skb_get_queue_mapping(skb)];
374 struct mlx5_wq_cyc *wq = &sq->wq;
375 u16 pi = sq->pc & wq->sz_m1;
376 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
378 memset(wqe, 0, sizeof(*wqe));
380 #ifdef CONFIG_MLX5_EN_IPSEC
381 if (sq->state & BIT(MLX5E_SQ_STATE_IPSEC)) {
382 skb = mlx5e_ipsec_handle_tx_skb(dev, wqe, skb);
388 return mlx5e_sq_xmit(sq, skb, wqe, pi);
391 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
393 struct mlx5e_txqsq *sq;
400 sq = container_of(cq, struct mlx5e_txqsq, cq);
402 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
408 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
409 * otherwise a cq overrun may occur
413 /* avoid dirtying sq cache line every cqe */
414 dma_fifo_cc = sq->dma_fifo_cc;
416 for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
417 struct mlx5_cqe64 *cqe;
421 cqe = mlx5_cqwq_get_cqe(&cq->wq);
425 mlx5_cqwq_pop(&cq->wq);
427 wqe_counter = be16_to_cpu(cqe->wqe_counter);
430 struct mlx5e_tx_wqe_info *wi;
435 last_wqe = (sqcc == wqe_counter);
437 ci = sqcc & sq->wq.sz_m1;
438 wi = &sq->db.wqe_info[ci];
441 if (unlikely(!skb)) { /* nop */
446 if (unlikely(skb_shinfo(skb)->tx_flags &
448 struct skb_shared_hwtstamps hwts = {};
450 mlx5e_fill_hwstamp(sq->tstamp,
451 get_cqe_ts(cqe), &hwts);
452 skb_tstamp_tx(skb, &hwts);
455 for (j = 0; j < wi->num_dma; j++) {
456 struct mlx5e_sq_dma *dma =
457 mlx5e_dma_get(sq, dma_fifo_cc++);
459 mlx5e_tx_dma_unmap(sq->pdev, dma);
463 nbytes += wi->num_bytes;
464 sqcc += wi->num_wqebbs;
465 napi_consume_skb(skb, napi_budget);
469 mlx5_cqwq_update_db_record(&cq->wq);
471 /* ensure cq space is freed before enabling more cqes */
474 sq->dma_fifo_cc = dma_fifo_cc;
477 netdev_tx_completed_queue(sq->txq, npkts, nbytes);
479 if (netif_tx_queue_stopped(sq->txq) &&
480 mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, MLX5E_SQ_STOP_ROOM)) {
481 netif_tx_wake_queue(sq->txq);
485 return (i == MLX5E_TX_CQ_POLL_BUDGET);
488 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq)
490 struct mlx5e_tx_wqe_info *wi;
495 while (sq->cc != sq->pc) {
496 ci = sq->cc & sq->wq.sz_m1;
497 wi = &sq->db.wqe_info[ci];
500 if (!skb) { /* nop */
505 for (i = 0; i < wi->num_dma; i++) {
506 struct mlx5e_sq_dma *dma =
507 mlx5e_dma_get(sq, sq->dma_fifo_cc++);
509 mlx5e_tx_dma_unmap(sq->pdev, dma);
512 dev_kfree_skb_any(skb);
513 sq->cc += wi->num_wqebbs;
517 #ifdef CONFIG_MLX5_CORE_IPOIB
519 struct mlx5_wqe_eth_pad {
523 struct mlx5i_tx_wqe {
524 struct mlx5_wqe_ctrl_seg ctrl;
525 struct mlx5_wqe_datagram_seg datagram;
526 struct mlx5_wqe_eth_pad pad;
527 struct mlx5_wqe_eth_seg eth;
531 mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey,
532 struct mlx5_wqe_datagram_seg *dseg)
534 memcpy(&dseg->av, av, sizeof(struct mlx5_av));
535 dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV);
536 dseg->av.key.qkey.qkey = cpu_to_be32(dqkey);
539 netdev_tx_t mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
540 struct mlx5_av *av, u32 dqpn, u32 dqkey)
542 struct mlx5_wq_cyc *wq = &sq->wq;
543 u16 pi = sq->pc & wq->sz_m1;
544 struct mlx5i_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
545 struct mlx5e_tx_wqe_info *wi = &sq->db.wqe_info[pi];
547 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
548 struct mlx5_wqe_datagram_seg *datagram = &wqe->datagram;
549 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
551 unsigned char *skb_data = skb->data;
552 unsigned int skb_len = skb->len;
553 u8 opcode = MLX5_OPCODE_SEND;
554 unsigned int num_bytes;
560 memset(wqe, 0, sizeof(*wqe));
562 mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram);
564 mlx5e_txwqe_build_eseg_csum(sq, skb, eseg);
566 if (skb_is_gso(skb)) {
567 opcode = MLX5_OPCODE_LSO;
568 ihs = mlx5e_txwqe_build_eseg_gso(sq, skb, eseg, &num_bytes);
569 sq->stats.packets += skb_shinfo(skb)->gso_segs;
571 ihs = mlx5e_calc_min_inline(sq->min_inline_mode, skb);
572 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
576 sq->stats.bytes += num_bytes;
577 sq->stats.xmit_more += skb->xmit_more;
579 ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
581 memcpy(eseg->inline_hdr.start, skb_data, ihs);
582 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
583 eseg->inline_hdr.sz = cpu_to_be16(ihs);
584 ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr.start), MLX5_SEND_WQE_DS);
587 headlen = skb_len - skb->data_len;
588 num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb_data, headlen,
589 (struct mlx5_wqe_data_seg *)cseg + ds_cnt);
590 if (unlikely(num_dma < 0))
591 goto dma_unmap_wqe_err;
593 mlx5e_txwqe_complete(sq, skb, opcode, ds_cnt + num_dma,
594 num_bytes, num_dma, wi, cseg);
600 mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
602 dev_kfree_skb_any(skb);