2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <net/devlink.h>
39 #include <linux/mlx5/device.h>
40 #include <linux/mlx5/eswitch.h>
41 #include <linux/mlx5/fs.h>
44 #ifdef CONFIG_MLX5_ESWITCH
46 #define MLX5_MAX_UC_PER_VPORT(dev) \
47 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
49 #define MLX5_MAX_MC_PER_VPORT(dev) \
50 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
52 #define MLX5_MIN_BW_SHARE 1
54 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
55 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
57 #define mlx5_esw_has_fwd_fdb(dev) \
58 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
60 #define FDB_MAX_CHAIN 3
61 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
62 #define FDB_MAX_PRIO 16
64 struct vport_ingress {
65 struct mlx5_flow_table *acl;
66 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
67 struct mlx5_flow_group *allow_spoofchk_only_grp;
68 struct mlx5_flow_group *allow_untagged_only_grp;
69 struct mlx5_flow_group *drop_grp;
70 struct mlx5_flow_handle *allow_rule;
71 struct mlx5_flow_handle *drop_rule;
72 struct mlx5_fc *drop_counter;
76 struct mlx5_flow_table *acl;
77 struct mlx5_flow_group *allowed_vlans_grp;
78 struct mlx5_flow_group *drop_grp;
79 struct mlx5_flow_handle *allowed_vlan;
80 struct mlx5_flow_handle *drop_rule;
81 struct mlx5_fc *drop_counter;
84 struct mlx5_vport_drop_stats {
89 struct mlx5_vport_info {
102 struct mlx5_core_dev *dev;
104 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
105 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
106 struct mlx5_flow_handle *promisc_rule;
107 struct mlx5_flow_handle *allmulti_rule;
108 struct work_struct vport_change_handler;
110 struct vport_ingress ingress;
111 struct vport_egress egress;
113 struct mlx5_vport_info info;
125 enum offloads_fdb_flags {
126 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
129 extern const unsigned int ESW_POOLS[4];
131 #define PRIO_LEVELS 2
132 struct mlx5_eswitch_fdb {
135 struct mlx5_flow_table *fdb;
136 struct mlx5_flow_group *addr_grp;
137 struct mlx5_flow_group *allmulti_grp;
138 struct mlx5_flow_group *promisc_grp;
141 struct offloads_fdb {
142 struct mlx5_flow_table *slow_fdb;
143 struct mlx5_flow_group *send_to_vport_grp;
144 struct mlx5_flow_group *peer_miss_grp;
145 struct mlx5_flow_handle **peer_miss_rules;
146 struct mlx5_flow_group *miss_grp;
147 struct mlx5_flow_handle *miss_rule_uni;
148 struct mlx5_flow_handle *miss_rule_multi;
149 int vlan_push_pop_refcount;
152 struct mlx5_flow_table *fdb;
154 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
155 /* Protects fdb_prio table */
156 struct mutex fdb_prio_lock;
158 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
164 struct mlx5_esw_offload {
165 struct mlx5_flow_table *ft_offloads;
166 struct mlx5_flow_group *vport_rx_group;
167 struct mlx5_eswitch_rep *vport_reps;
168 struct list_head peer_flows;
169 struct mutex peer_mutex;
170 DECLARE_HASHTABLE(encap_tbl, 8);
171 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
177 /* E-Switch MC FDB table hash node */
178 struct esw_mc_addr { /* SRIOV only */
179 struct l2addr_node node;
180 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
184 struct mlx5_eswitch {
185 struct mlx5_core_dev *dev;
187 struct mlx5_eswitch_fdb fdb_table;
188 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
189 struct workqueue_struct *work_queue;
190 struct mlx5_vport *vports;
193 /* Synchronize between vport change events
194 * and async SRIOV admin state changes
196 struct mutex state_lock;
197 struct esw_mc_addr mc_promisc;
204 struct mlx5_esw_offload offloads;
209 void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
210 int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
211 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
212 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
215 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
216 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
217 int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
218 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
219 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
220 int vport, u8 mac[ETH_ALEN]);
221 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
222 int vport, int link_state);
223 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
224 int vport, u16 vlan, u8 qos);
225 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
226 int vport, bool spoofchk);
227 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
228 int vport_num, bool setting);
229 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
230 u32 max_rate, u32 min_rate);
231 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
232 int vport, struct ifla_vf_info *ivi);
233 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
235 struct ifla_vf_stats *vf_stats);
236 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
238 struct mlx5_flow_spec;
239 struct mlx5_esw_flow_attr;
241 struct mlx5_flow_handle *
242 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
243 struct mlx5_flow_spec *spec,
244 struct mlx5_esw_flow_attr *attr);
245 struct mlx5_flow_handle *
246 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
247 struct mlx5_flow_spec *spec,
248 struct mlx5_esw_flow_attr *attr);
250 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
251 struct mlx5_flow_handle *rule,
252 struct mlx5_esw_flow_attr *attr);
254 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
255 struct mlx5_flow_handle *rule,
256 struct mlx5_esw_flow_attr *attr);
259 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
262 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
265 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
267 struct mlx5_flow_handle *
268 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
269 struct mlx5_flow_destination *dest);
272 SET_VLAN_STRIP = BIT(0),
273 SET_VLAN_INSERT = BIT(1)
276 enum mlx5_flow_match_level {
277 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
278 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
279 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
280 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
283 /* current maximum for flow based vport multicasting */
284 #define MLX5_MAX_FLOW_FWD_VPORTS 2
287 MLX5_ESW_DEST_ENCAP = BIT(0),
288 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
291 struct mlx5_esw_flow_attr {
292 struct mlx5_eswitch_rep *in_rep;
293 struct mlx5_core_dev *in_mdev;
294 struct mlx5_core_dev *counter_dev;
300 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
301 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
302 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
307 struct mlx5_eswitch_rep *rep;
308 struct mlx5_core_dev *mdev;
310 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
313 u8 tunnel_match_level;
314 struct mlx5_fc *counter;
318 struct mlx5e_tc_flow_parse_attr *parse_attr;
321 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
322 struct netlink_ext_ack *extack);
323 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
324 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
325 struct netlink_ext_ack *extack);
326 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
327 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
328 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
329 struct netlink_ext_ack *extack);
330 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
331 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
333 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
334 struct mlx5_esw_flow_attr *attr);
335 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
336 struct mlx5_esw_flow_attr *attr);
337 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
338 int vport, u16 vlan, u8 qos, u8 set_flags);
340 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
343 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
344 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
349 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
350 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
353 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
354 struct mlx5_core_dev *dev1);
356 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
358 #define esw_info(dev, format, ...) \
359 pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
361 #define esw_warn(dev, format, ...) \
362 pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
364 #define esw_debug(dev, format, ...) \
365 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
366 #else /* CONFIG_MLX5_ESWITCH */
367 /* eswitch API stubs */
368 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
369 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
370 static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
371 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
372 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
374 #define FDB_MAX_CHAIN 1
375 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
376 #define FDB_MAX_PRIO 1
378 #endif /* CONFIG_MLX5_ESWITCH */
380 #endif /* __MLX5_ESWITCH_H__ */