2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <linux/atomic.h>
39 #include <net/devlink.h>
40 #include <linux/mlx5/device.h>
41 #include <linux/mlx5/eswitch.h>
42 #include <linux/mlx5/vport.h>
43 #include <linux/mlx5/fs.h>
46 #ifdef CONFIG_MLX5_ESWITCH
48 #define MLX5_MAX_UC_PER_VPORT(dev) \
49 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
51 #define MLX5_MAX_MC_PER_VPORT(dev) \
52 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
54 #define MLX5_MIN_BW_SHARE 1
56 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
57 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
59 #define mlx5_esw_has_fwd_fdb(dev) \
60 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
62 #define FDB_MAX_CHAIN 3
63 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
64 #define FDB_MAX_PRIO 16
66 struct vport_ingress {
67 struct mlx5_flow_table *acl;
68 struct mlx5_flow_handle *allow_rule;
70 struct mlx5_flow_group *allow_spoofchk_only_grp;
71 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
72 struct mlx5_flow_group *allow_untagged_only_grp;
73 struct mlx5_flow_group *drop_grp;
74 struct mlx5_flow_handle *drop_rule;
75 struct mlx5_fc *drop_counter;
78 struct mlx5_flow_group *metadata_grp;
79 struct mlx5_modify_hdr *modify_metadata;
80 struct mlx5_flow_handle *modify_metadata_rule;
85 struct mlx5_flow_table *acl;
86 struct mlx5_flow_group *allowed_vlans_grp;
87 struct mlx5_flow_group *drop_grp;
88 struct mlx5_flow_handle *allowed_vlan;
90 struct mlx5_flow_handle *drop_rule;
91 struct mlx5_fc *drop_counter;
95 struct mlx5_vport_drop_stats {
100 struct mlx5_vport_info {
112 /* Vport context events */
113 enum mlx5_eswitch_vport_event {
114 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0),
115 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1),
116 MLX5_VPORT_PROMISC_CHANGE = BIT(3),
120 struct mlx5_core_dev *dev;
122 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
123 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
124 struct mlx5_flow_handle *promisc_rule;
125 struct mlx5_flow_handle *allmulti_rule;
126 struct work_struct vport_change_handler;
128 struct vport_ingress ingress;
129 struct vport_egress egress;
131 struct mlx5_vport_info info;
140 enum mlx5_eswitch_vport_event enabled_events;
143 enum offloads_fdb_flags {
144 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
147 extern const unsigned int ESW_POOLS[4];
149 #define PRIO_LEVELS 2
150 struct mlx5_eswitch_fdb {
153 struct mlx5_flow_table *fdb;
154 struct mlx5_flow_group *addr_grp;
155 struct mlx5_flow_group *allmulti_grp;
156 struct mlx5_flow_group *promisc_grp;
157 struct mlx5_flow_table *vepa_fdb;
158 struct mlx5_flow_handle *vepa_uplink_rule;
159 struct mlx5_flow_handle *vepa_star_rule;
162 struct offloads_fdb {
163 struct mlx5_flow_namespace *ns;
164 struct mlx5_flow_table *slow_fdb;
165 struct mlx5_flow_group *send_to_vport_grp;
166 struct mlx5_flow_group *peer_miss_grp;
167 struct mlx5_flow_handle **peer_miss_rules;
168 struct mlx5_flow_group *miss_grp;
169 struct mlx5_flow_handle *miss_rule_uni;
170 struct mlx5_flow_handle *miss_rule_multi;
171 int vlan_push_pop_refcount;
174 struct mlx5_flow_table *fdb;
176 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
177 /* Protects fdb_prio table */
178 struct mutex fdb_prio_lock;
180 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
186 struct mlx5_esw_offload {
187 struct mlx5_flow_table *ft_offloads;
188 struct mlx5_flow_group *vport_rx_group;
189 struct mlx5_eswitch_rep *vport_reps;
190 struct list_head peer_flows;
191 struct mutex peer_mutex;
192 struct mutex encap_tbl_lock; /* protects encap_tbl */
193 DECLARE_HASHTABLE(encap_tbl, 8);
194 struct mod_hdr_tbl mod_hdr;
195 DECLARE_HASHTABLE(termtbl_tbl, 8);
196 struct mutex termtbl_mutex; /* protects termtbl hash */
197 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
199 atomic64_t num_flows;
200 enum devlink_eswitch_encap_mode encap;
203 /* E-Switch MC FDB table hash node */
204 struct esw_mc_addr { /* SRIOV only */
205 struct l2addr_node node;
206 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
210 struct mlx5_host_work {
211 struct work_struct work;
212 struct mlx5_eswitch *esw;
215 struct mlx5_esw_functions {
221 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
224 struct mlx5_eswitch {
225 struct mlx5_core_dev *dev;
227 struct mlx5_eswitch_fdb fdb_table;
228 /* legacy data structures */
229 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
230 struct esw_mc_addr mc_promisc;
232 struct workqueue_struct *work_queue;
233 struct mlx5_vport *vports;
237 /* Synchronize between vport change events
238 * and async SRIOV admin state changes
240 struct mutex state_lock;
247 struct mlx5_esw_offload offloads;
251 u16 first_host_vport;
252 struct mlx5_esw_functions esw_funcs;
255 void esw_offloads_disable(struct mlx5_eswitch *esw);
256 int esw_offloads_enable(struct mlx5_eswitch *esw);
257 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
258 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
259 void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
260 struct mlx5_vport *vport);
261 int esw_vport_create_ingress_acl_table(struct mlx5_eswitch *esw,
262 struct mlx5_vport *vport,
264 void esw_vport_destroy_ingress_acl_table(struct mlx5_vport *vport);
265 void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
266 struct mlx5_vport *vport);
267 int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
268 struct mlx5_vport *vport);
269 void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
270 struct mlx5_vport *vport);
271 int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num,
275 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
276 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
277 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode);
278 void mlx5_eswitch_disable(struct mlx5_eswitch *esw);
279 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
280 u16 vport, u8 mac[ETH_ALEN]);
281 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
282 u16 vport, int link_state);
283 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
284 u16 vport, u16 vlan, u8 qos);
285 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
286 u16 vport, bool spoofchk);
287 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
288 u16 vport_num, bool setting);
289 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
290 u32 max_rate, u32 min_rate);
291 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
292 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
293 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
294 u16 vport, struct ifla_vf_info *ivi);
295 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
297 struct ifla_vf_stats *vf_stats);
298 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
300 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
301 void *in, int inlen);
302 int mlx5_eswitch_query_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
303 void *out, int outlen);
305 struct mlx5_flow_spec;
306 struct mlx5_esw_flow_attr;
307 struct mlx5_termtbl_handle;
310 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,
311 struct mlx5_flow_act *flow_act,
312 struct mlx5_flow_spec *spec);
314 struct mlx5_flow_handle *
315 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw,
316 struct mlx5_flow_table *ft,
317 struct mlx5_flow_spec *spec,
318 struct mlx5_esw_flow_attr *attr,
319 struct mlx5_flow_act *flow_act,
320 struct mlx5_flow_destination *dest,
324 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw,
325 struct mlx5_termtbl_handle *tt);
327 struct mlx5_flow_handle *
328 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
329 struct mlx5_flow_spec *spec,
330 struct mlx5_esw_flow_attr *attr);
331 struct mlx5_flow_handle *
332 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
333 struct mlx5_flow_spec *spec,
334 struct mlx5_esw_flow_attr *attr);
336 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
337 struct mlx5_flow_handle *rule,
338 struct mlx5_esw_flow_attr *attr);
340 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
341 struct mlx5_flow_handle *rule,
342 struct mlx5_esw_flow_attr *attr);
345 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
348 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
351 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
353 struct mlx5_flow_handle *
354 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
355 struct mlx5_flow_destination *dest);
358 SET_VLAN_STRIP = BIT(0),
359 SET_VLAN_INSERT = BIT(1)
362 enum mlx5_flow_match_level {
363 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
364 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
365 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
366 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
369 /* current maximum for flow based vport multicasting */
370 #define MLX5_MAX_FLOW_FWD_VPORTS 2
373 MLX5_ESW_DEST_ENCAP = BIT(0),
374 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
377 struct mlx5_esw_flow_attr {
378 struct mlx5_eswitch_rep *in_rep;
379 struct mlx5_core_dev *in_mdev;
380 struct mlx5_core_dev *counter_dev;
386 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
387 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
388 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
393 struct mlx5_eswitch_rep *rep;
394 struct mlx5_pkt_reformat *pkt_reformat;
395 struct mlx5_core_dev *mdev;
396 struct mlx5_termtbl_handle *termtbl;
397 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
398 struct mlx5_modify_hdr *modify_hdr;
399 u8 inner_match_level;
400 u8 outer_match_level;
401 struct mlx5_fc *counter;
405 struct mlx5e_tc_flow_parse_attr *parse_attr;
408 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
409 struct netlink_ext_ack *extack);
410 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
411 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
412 struct netlink_ext_ack *extack);
413 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
414 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode);
415 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
416 enum devlink_eswitch_encap_mode encap,
417 struct netlink_ext_ack *extack);
418 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
419 enum devlink_eswitch_encap_mode *encap);
420 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
422 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
423 struct mlx5_esw_flow_attr *attr);
424 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
425 struct mlx5_esw_flow_attr *attr);
426 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
427 u16 vport, u16 vlan, u8 qos, u8 set_flags);
429 int mlx5_esw_create_vport_egress_acl_vlan(struct mlx5_eswitch *esw,
430 struct mlx5_vport *vport,
431 u16 vlan_id, u32 flow_action);
433 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
436 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
437 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
442 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
443 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
446 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
447 struct mlx5_core_dev *dev1);
448 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
449 struct mlx5_core_dev *dev1);
451 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
453 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
455 #define esw_info(__dev, format, ...) \
456 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
458 #define esw_warn(__dev, format, ...) \
459 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
461 #define esw_debug(dev, format, ...) \
462 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
464 /* The returned number is valid only when the dev is eswitch manager. */
465 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
467 return mlx5_core_is_ecpf_esw_manager(dev) ?
468 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
472 mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num)
474 return esw->manager_vport == vport_num;
477 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
479 return mlx5_core_is_ecpf_esw_manager(dev) ?
480 MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF;
483 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev)
485 /* Ideally device should have the functions changed supported
486 * capability regardless of it being ECPF or PF wherever such
487 * event should be processed such as on eswitch manager device.
488 * However, some ECPF based device might not have this capability
489 * set. Hence OR for ECPF check to cover such device.
491 return MLX5_CAP_ESW(dev, esw_functions_changed) ||
492 mlx5_core_is_ecpf_esw_manager(dev);
495 static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
497 /* Uplink always locate at the last element of the array.*/
498 return esw->total_vports - 1;
501 static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
503 return esw->total_vports - 2;
506 static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
509 if (vport_num == MLX5_VPORT_ECPF) {
510 if (!mlx5_ecpf_vport_exists(esw->dev))
511 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
512 return mlx5_eswitch_ecpf_idx(esw);
515 if (vport_num == MLX5_VPORT_UPLINK)
516 return mlx5_eswitch_uplink_idx(esw);
521 static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
524 if (index == mlx5_eswitch_ecpf_idx(esw) &&
525 mlx5_ecpf_vport_exists(esw->dev))
526 return MLX5_VPORT_ECPF;
528 if (index == mlx5_eswitch_uplink_idx(esw))
529 return MLX5_VPORT_UPLINK;
534 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
535 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
537 /* The vport getter/iterator are only valid after esw->total_vports
538 * and vport->vport are initialized in mlx5_eswitch_init.
540 #define mlx5_esw_for_all_vports(esw, i, vport) \
541 for ((i) = MLX5_VPORT_PF; \
542 (vport) = &(esw)->vports[i], \
543 (i) < (esw)->total_vports; (i)++)
545 #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \
546 for ((i) = (esw)->total_vports - 1; \
547 (vport) = &(esw)->vports[i], \
548 (i) >= MLX5_VPORT_PF; (i)--)
550 #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
551 for ((i) = MLX5_VPORT_FIRST_VF; \
552 (vport) = &(esw)->vports[(i)], \
553 (i) <= (nvfs); (i)++)
555 #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
557 (vport) = &(esw)->vports[(i)], \
558 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
560 /* The rep getter/iterator are only valid after esw->total_vports
561 * and vport->vport are initialized in mlx5_eswitch_init.
563 #define mlx5_esw_for_all_reps(esw, i, rep) \
564 for ((i) = MLX5_VPORT_PF; \
565 (rep) = &(esw)->offloads.vport_reps[i], \
566 (i) < (esw)->total_vports; (i)++)
568 #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
569 for ((i) = MLX5_VPORT_FIRST_VF; \
570 (rep) = &(esw)->offloads.vport_reps[i], \
571 (i) <= (nvfs); (i)++)
573 #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
575 (rep) = &(esw)->offloads.vport_reps[i], \
576 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
578 #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
579 for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
581 #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
582 for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
584 /* Includes host PF (vport 0) if it's not esw manager. */
585 #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \
586 for ((i) = (esw)->first_host_vport; \
587 (rep) = &(esw)->offloads.vport_reps[i], \
588 (i) <= (nvfs); (i)++)
590 #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \
592 (rep) = &(esw)->offloads.vport_reps[i], \
593 (i) >= (esw)->first_host_vport; (i)--)
595 #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \
596 for ((vport) = (esw)->first_host_vport; \
597 (vport) <= (nvfs); (vport)++)
599 #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \
600 for ((vport) = (nvfs); \
601 (vport) >= (esw)->first_host_vport; (vport)--)
603 struct mlx5_vport *__must_check
604 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
606 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num);
608 void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs);
609 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
612 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
613 enum mlx5_eswitch_vport_event enabled_events);
614 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw);
617 esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
618 struct mlx5_vport *vport);
620 esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
621 struct mlx5_vport *vport);
623 #else /* CONFIG_MLX5_ESWITCH */
624 /* eswitch API stubs */
625 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
626 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
627 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { return 0; }
628 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {}
629 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
630 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
631 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
633 return ERR_PTR(-EOPNOTSUPP);
636 static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {}
638 #define FDB_MAX_CHAIN 1
639 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
640 #define FDB_MAX_PRIO 1
642 #endif /* CONFIG_MLX5_ESWITCH */
644 #endif /* __MLX5_ESWITCH_H__ */