2 * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_ESWITCH_H__
34 #define __MLX5_ESWITCH_H__
36 #include <linux/if_ether.h>
37 #include <linux/if_link.h>
38 #include <linux/atomic.h>
39 #include <net/devlink.h>
40 #include <linux/mlx5/device.h>
41 #include <linux/mlx5/eswitch.h>
42 #include <linux/mlx5/vport.h>
43 #include <linux/mlx5/fs.h>
46 #ifdef CONFIG_MLX5_ESWITCH
48 #define MLX5_MAX_UC_PER_VPORT(dev) \
49 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
51 #define MLX5_MAX_MC_PER_VPORT(dev) \
52 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
54 #define MLX5_MIN_BW_SHARE 1
56 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
57 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
59 #define mlx5_esw_has_fwd_fdb(dev) \
60 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
62 #define FDB_MAX_CHAIN 3
63 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
64 #define FDB_MAX_PRIO 16
66 struct vport_ingress {
67 struct mlx5_flow_table *acl;
68 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
69 struct mlx5_flow_group *allow_spoofchk_only_grp;
70 struct mlx5_flow_group *allow_untagged_only_grp;
71 struct mlx5_flow_group *drop_grp;
72 int modify_metadata_id;
73 struct mlx5_flow_handle *modify_metadata_rule;
74 struct mlx5_flow_handle *allow_rule;
75 struct mlx5_flow_handle *drop_rule;
76 struct mlx5_fc *drop_counter;
80 struct mlx5_flow_table *acl;
81 struct mlx5_flow_group *allowed_vlans_grp;
82 struct mlx5_flow_group *drop_grp;
83 struct mlx5_flow_handle *allowed_vlan;
84 struct mlx5_flow_handle *drop_rule;
85 struct mlx5_fc *drop_counter;
88 struct mlx5_vport_drop_stats {
93 struct mlx5_vport_info {
105 /* Vport context events */
106 enum mlx5_eswitch_vport_event {
107 MLX5_VPORT_UC_ADDR_CHANGE = BIT(0),
108 MLX5_VPORT_MC_ADDR_CHANGE = BIT(1),
109 MLX5_VPORT_PROMISC_CHANGE = BIT(3),
113 struct mlx5_core_dev *dev;
115 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
116 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
117 struct mlx5_flow_handle *promisc_rule;
118 struct mlx5_flow_handle *allmulti_rule;
119 struct work_struct vport_change_handler;
121 struct vport_ingress ingress;
122 struct vport_egress egress;
124 struct mlx5_vport_info info;
133 enum mlx5_eswitch_vport_event enabled_events;
136 enum offloads_fdb_flags {
137 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
140 extern const unsigned int ESW_POOLS[4];
142 #define PRIO_LEVELS 2
143 struct mlx5_eswitch_fdb {
146 struct mlx5_flow_table *fdb;
147 struct mlx5_flow_group *addr_grp;
148 struct mlx5_flow_group *allmulti_grp;
149 struct mlx5_flow_group *promisc_grp;
150 struct mlx5_flow_table *vepa_fdb;
151 struct mlx5_flow_handle *vepa_uplink_rule;
152 struct mlx5_flow_handle *vepa_star_rule;
155 struct offloads_fdb {
156 struct mlx5_flow_table *slow_fdb;
157 struct mlx5_flow_group *send_to_vport_grp;
158 struct mlx5_flow_group *peer_miss_grp;
159 struct mlx5_flow_handle **peer_miss_rules;
160 struct mlx5_flow_group *miss_grp;
161 struct mlx5_flow_handle *miss_rule_uni;
162 struct mlx5_flow_handle *miss_rule_multi;
163 int vlan_push_pop_refcount;
166 struct mlx5_flow_table *fdb;
168 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
169 /* Protects fdb_prio table */
170 struct mutex fdb_prio_lock;
172 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
178 struct mlx5_esw_offload {
179 struct mlx5_flow_table *ft_offloads;
180 struct mlx5_flow_group *vport_rx_group;
181 struct mlx5_eswitch_rep *vport_reps;
182 struct list_head peer_flows;
183 struct mutex peer_mutex;
184 struct mutex encap_tbl_lock; /* protects encap_tbl */
185 DECLARE_HASHTABLE(encap_tbl, 8);
186 struct mod_hdr_tbl mod_hdr;
187 DECLARE_HASHTABLE(termtbl_tbl, 8);
188 struct mutex termtbl_mutex; /* protects termtbl hash */
189 const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
191 atomic64_t num_flows;
192 enum devlink_eswitch_encap_mode encap;
195 /* E-Switch MC FDB table hash node */
196 struct esw_mc_addr { /* SRIOV only */
197 struct l2addr_node node;
198 struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
202 struct mlx5_host_work {
203 struct work_struct work;
204 struct mlx5_eswitch *esw;
207 struct mlx5_esw_functions {
213 MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
216 struct mlx5_eswitch {
217 struct mlx5_core_dev *dev;
219 /* legacy data structures */
220 struct mlx5_eswitch_fdb fdb_table;
221 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
222 struct esw_mc_addr mc_promisc;
224 struct workqueue_struct *work_queue;
225 struct mlx5_vport *vports;
229 /* Synchronize between vport change events
230 * and async SRIOV admin state changes
232 struct mutex state_lock;
239 struct mlx5_esw_offload offloads;
243 u16 first_host_vport;
244 struct mlx5_esw_functions esw_funcs;
247 void esw_offloads_disable(struct mlx5_eswitch *esw);
248 int esw_offloads_enable(struct mlx5_eswitch *esw);
249 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
250 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
251 void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
252 struct mlx5_vport *vport);
253 int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
254 struct mlx5_vport *vport);
255 void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
256 struct mlx5_vport *vport);
257 int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
258 struct mlx5_vport *vport);
259 void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
260 struct mlx5_vport *vport);
261 void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
262 struct mlx5_vport *vport);
263 void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
264 struct mlx5_vport *vport);
265 int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num,
269 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
270 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
271 int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode);
272 void mlx5_eswitch_disable(struct mlx5_eswitch *esw);
273 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
274 u16 vport, u8 mac[ETH_ALEN]);
275 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
276 u16 vport, int link_state);
277 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
278 u16 vport, u16 vlan, u8 qos);
279 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
280 u16 vport, bool spoofchk);
281 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
282 u16 vport_num, bool setting);
283 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
284 u32 max_rate, u32 min_rate);
285 int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
286 int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
287 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
288 u16 vport, struct ifla_vf_info *ivi);
289 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
291 struct ifla_vf_stats *vf_stats);
292 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
294 int mlx5_eswitch_modify_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
295 void *in, int inlen);
296 int mlx5_eswitch_query_esw_vport_context(struct mlx5_eswitch *esw, u16 vport,
297 void *out, int outlen);
299 struct mlx5_flow_spec;
300 struct mlx5_esw_flow_attr;
301 struct mlx5_termtbl_handle;
304 mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,
305 struct mlx5_flow_act *flow_act,
306 struct mlx5_flow_spec *spec);
308 struct mlx5_flow_handle *
309 mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw,
310 struct mlx5_flow_table *ft,
311 struct mlx5_flow_spec *spec,
312 struct mlx5_esw_flow_attr *attr,
313 struct mlx5_flow_act *flow_act,
314 struct mlx5_flow_destination *dest,
318 mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw,
319 struct mlx5_termtbl_handle *tt);
321 struct mlx5_flow_handle *
322 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
323 struct mlx5_flow_spec *spec,
324 struct mlx5_esw_flow_attr *attr);
325 struct mlx5_flow_handle *
326 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
327 struct mlx5_flow_spec *spec,
328 struct mlx5_esw_flow_attr *attr);
330 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
331 struct mlx5_flow_handle *rule,
332 struct mlx5_esw_flow_attr *attr);
334 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
335 struct mlx5_flow_handle *rule,
336 struct mlx5_esw_flow_attr *attr);
339 mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
342 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
345 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
347 struct mlx5_flow_handle *
348 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
349 struct mlx5_flow_destination *dest);
352 SET_VLAN_STRIP = BIT(0),
353 SET_VLAN_INSERT = BIT(1)
356 enum mlx5_flow_match_level {
357 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
358 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
359 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
360 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
363 /* current maximum for flow based vport multicasting */
364 #define MLX5_MAX_FLOW_FWD_VPORTS 2
367 MLX5_ESW_DEST_ENCAP = BIT(0),
368 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
371 struct mlx5_esw_flow_attr {
372 struct mlx5_eswitch_rep *in_rep;
373 struct mlx5_core_dev *in_mdev;
374 struct mlx5_core_dev *counter_dev;
380 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
381 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
382 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
387 struct mlx5_eswitch_rep *rep;
388 struct mlx5_core_dev *mdev;
390 struct mlx5_termtbl_handle *termtbl;
391 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
394 u8 tunnel_match_level;
395 struct mlx5_fc *counter;
399 struct mlx5e_tc_flow_parse_attr *parse_attr;
402 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
403 struct netlink_ext_ack *extack);
404 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
405 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
406 struct netlink_ext_ack *extack);
407 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
408 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode);
409 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
410 enum devlink_eswitch_encap_mode encap,
411 struct netlink_ext_ack *extack);
412 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
413 enum devlink_eswitch_encap_mode *encap);
414 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
416 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
417 struct mlx5_esw_flow_attr *attr);
418 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
419 struct mlx5_esw_flow_attr *attr);
420 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
421 u16 vport, u16 vlan, u8 qos, u8 set_flags);
423 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
426 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
427 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
432 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
433 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
436 bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
437 struct mlx5_core_dev *dev1);
438 bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
439 struct mlx5_core_dev *dev1);
441 const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
443 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
445 #define esw_info(__dev, format, ...) \
446 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
448 #define esw_warn(__dev, format, ...) \
449 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
451 #define esw_debug(dev, format, ...) \
452 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
454 /* The returned number is valid only when the dev is eswitch manager. */
455 static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
457 return mlx5_core_is_ecpf_esw_manager(dev) ?
458 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
461 static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
463 return mlx5_core_is_ecpf_esw_manager(dev) ?
464 MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF;
467 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev)
469 /* Ideally device should have the functions changed supported
470 * capability regardless of it being ECPF or PF wherever such
471 * event should be processed such as on eswitch manager device.
472 * However, some ECPF based device might not have this capability
473 * set. Hence OR for ECPF check to cover such device.
475 return MLX5_CAP_ESW(dev, esw_functions_changed) ||
476 mlx5_core_is_ecpf_esw_manager(dev);
479 static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
481 /* Uplink always locate at the last element of the array.*/
482 return esw->total_vports - 1;
485 static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
487 return esw->total_vports - 2;
490 static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
493 if (vport_num == MLX5_VPORT_ECPF) {
494 if (!mlx5_ecpf_vport_exists(esw->dev))
495 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
496 return mlx5_eswitch_ecpf_idx(esw);
499 if (vport_num == MLX5_VPORT_UPLINK)
500 return mlx5_eswitch_uplink_idx(esw);
505 static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
508 if (index == mlx5_eswitch_ecpf_idx(esw) &&
509 mlx5_ecpf_vport_exists(esw->dev))
510 return MLX5_VPORT_ECPF;
512 if (index == mlx5_eswitch_uplink_idx(esw))
513 return MLX5_VPORT_UPLINK;
518 /* TODO: This mlx5e_tc function shouldn't be called by eswitch */
519 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
521 /* The vport getter/iterator are only valid after esw->total_vports
522 * and vport->vport are initialized in mlx5_eswitch_init.
524 #define mlx5_esw_for_all_vports(esw, i, vport) \
525 for ((i) = MLX5_VPORT_PF; \
526 (vport) = &(esw)->vports[i], \
527 (i) < (esw)->total_vports; (i)++)
529 #define mlx5_esw_for_all_vports_reverse(esw, i, vport) \
530 for ((i) = (esw)->total_vports - 1; \
531 (vport) = &(esw)->vports[i], \
532 (i) >= MLX5_VPORT_PF; (i)--)
534 #define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
535 for ((i) = MLX5_VPORT_FIRST_VF; \
536 (vport) = &(esw)->vports[(i)], \
537 (i) <= (nvfs); (i)++)
539 #define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
541 (vport) = &(esw)->vports[(i)], \
542 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
544 /* The rep getter/iterator are only valid after esw->total_vports
545 * and vport->vport are initialized in mlx5_eswitch_init.
547 #define mlx5_esw_for_all_reps(esw, i, rep) \
548 for ((i) = MLX5_VPORT_PF; \
549 (rep) = &(esw)->offloads.vport_reps[i], \
550 (i) < (esw)->total_vports; (i)++)
552 #define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
553 for ((i) = MLX5_VPORT_FIRST_VF; \
554 (rep) = &(esw)->offloads.vport_reps[i], \
555 (i) <= (nvfs); (i)++)
557 #define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
559 (rep) = &(esw)->offloads.vport_reps[i], \
560 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
562 #define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
563 for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
565 #define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
566 for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
568 /* Includes host PF (vport 0) if it's not esw manager. */
569 #define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \
570 for ((i) = (esw)->first_host_vport; \
571 (rep) = &(esw)->offloads.vport_reps[i], \
572 (i) <= (nvfs); (i)++)
574 #define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \
576 (rep) = &(esw)->offloads.vport_reps[i], \
577 (i) >= (esw)->first_host_vport; (i)--)
579 #define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \
580 for ((vport) = (esw)->first_host_vport; \
581 (vport) <= (nvfs); (vport)++)
583 #define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \
584 for ((vport) = (nvfs); \
585 (vport) >= (esw)->first_host_vport; (vport)--)
587 struct mlx5_vport *__must_check
588 mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
590 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num);
592 void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs);
593 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
596 mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
597 enum mlx5_eswitch_vport_event enabled_events);
598 void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw);
600 #else /* CONFIG_MLX5_ESWITCH */
601 /* eswitch API stubs */
602 static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
603 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
604 static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int mode) { return 0; }
605 static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {}
606 static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
607 static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
608 static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
610 return ERR_PTR(-EOPNOTSUPP);
613 static inline void mlx5_eswitch_update_num_of_vfs(struct mlx5_eswitch *esw, const int num_vfs) {}
615 #define FDB_MAX_CHAIN 1
616 #define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
617 #define FDB_MAX_PRIO 1
619 #endif /* CONFIG_MLX5_ESWITCH */
621 #endif /* __MLX5_ESWITCH_H__ */