2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/mlx5_ifc.h>
36 #include <linux/mlx5/vport.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_core.h"
43 #include "lib/devcom.h"
46 /* There are two match-all miss flows, one for unicast dst mac and
49 #define MLX5_ESW_MISS_FLOWS (2)
51 #define fdb_prio_table(esw, chain, prio, level) \
52 (esw)->fdb_table.offloads.fdb_prio[(chain)][(prio)][(level)]
54 #define UPLINK_REP_INDEX 0
56 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
59 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
61 WARN_ON(idx > esw->total_vports - 1);
62 return &esw->offloads.vport_reps[idx];
65 static struct mlx5_flow_table *
66 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
68 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
70 bool mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw)
72 return (!!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED));
75 u32 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw)
77 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
83 u16 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw)
85 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
92 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
93 struct mlx5_flow_spec *spec,
94 struct mlx5_esw_flow_attr *attr)
99 /* Use metadata matching because vport is not represented by single
100 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
103 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
104 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
105 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
106 attr->in_rep->vport));
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET_TO_ONES(fte_match_set_misc2, misc2, metadata_reg_c_0);
111 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
112 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
113 if (memchr_inv(misc, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc)))
114 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
116 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
117 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
119 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
120 MLX5_SET(fte_match_set_misc, misc,
121 source_eswitch_owner_vhca_id,
122 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
124 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
125 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
126 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
127 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
128 source_eswitch_owner_vhca_id);
130 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
133 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
134 attr->in_rep->vport == MLX5_VPORT_UPLINK)
135 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
138 struct mlx5_flow_handle *
139 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
140 struct mlx5_flow_spec *spec,
141 struct mlx5_esw_flow_attr *attr)
143 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
144 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
145 bool split = !!(attr->split_count);
146 struct mlx5_flow_handle *rule;
147 struct mlx5_flow_table *fdb;
150 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
151 return ERR_PTR(-EOPNOTSUPP);
153 flow_act.action = attr->action;
154 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
155 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
156 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
157 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
158 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
159 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
160 flow_act.vlan[0].vid = attr->vlan_vid[0];
161 flow_act.vlan[0].prio = attr->vlan_prio[0];
162 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
163 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
164 flow_act.vlan[1].vid = attr->vlan_vid[1];
165 flow_act.vlan[1].prio = attr->vlan_prio[1];
169 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
170 if (attr->dest_chain) {
171 struct mlx5_flow_table *ft;
173 ft = esw_get_prio_table(esw, attr->dest_chain, 1, 0);
176 goto err_create_goto_table;
179 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
183 for (j = attr->split_count; j < attr->out_count; j++) {
184 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
185 dest[i].vport.num = attr->dests[j].rep->vport;
186 dest[i].vport.vhca_id =
187 MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
188 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
189 dest[i].vport.flags |=
190 MLX5_FLOW_DEST_VPORT_VHCA_ID;
191 if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
192 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
193 flow_act.reformat_id = attr->dests[j].encap_id;
194 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
195 dest[i].vport.reformat_id =
196 attr->dests[j].encap_id;
202 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
203 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
204 dest[i].counter_id = mlx5_fc_id(attr->counter);
208 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
210 if (attr->outer_match_level != MLX5_MATCH_NONE)
211 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
212 if (attr->inner_match_level != MLX5_MATCH_NONE)
213 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
215 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
216 flow_act.modify_id = attr->mod_hdr_id;
218 fdb = esw_get_prio_table(esw, attr->chain, attr->prio, !!split);
220 rule = ERR_CAST(fdb);
224 if (mlx5_eswitch_termtbl_required(esw, &flow_act, spec))
225 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, attr,
228 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
232 esw->offloads.num_flows++;
237 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
239 if (attr->dest_chain)
240 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
241 err_create_goto_table:
245 struct mlx5_flow_handle *
246 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
247 struct mlx5_flow_spec *spec,
248 struct mlx5_esw_flow_attr *attr)
250 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
251 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
252 struct mlx5_flow_table *fast_fdb;
253 struct mlx5_flow_table *fwd_fdb;
254 struct mlx5_flow_handle *rule;
257 fast_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 0);
258 if (IS_ERR(fast_fdb)) {
259 rule = ERR_CAST(fast_fdb);
263 fwd_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 1);
264 if (IS_ERR(fwd_fdb)) {
265 rule = ERR_CAST(fwd_fdb);
269 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
270 for (i = 0; i < attr->split_count; i++) {
271 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
272 dest[i].vport.num = attr->dests[i].rep->vport;
273 dest[i].vport.vhca_id =
274 MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
275 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
276 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
277 if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
278 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
279 dest[i].vport.reformat_id = attr->dests[i].encap_id;
282 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
283 dest[i].ft = fwd_fdb,
286 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
288 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
289 if (attr->outer_match_level != MLX5_MATCH_NONE)
290 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
292 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
297 esw->offloads.num_flows++;
301 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
303 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
309 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
310 struct mlx5_flow_handle *rule,
311 struct mlx5_esw_flow_attr *attr,
314 bool split = (attr->split_count > 0);
317 mlx5_del_flow_rules(rule);
319 /* unref the term table */
320 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
321 if (attr->dests[i].termtbl)
322 mlx5_eswitch_termtbl_put(esw, attr->dests[i].termtbl);
325 esw->offloads.num_flows--;
328 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
329 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
331 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
332 if (attr->dest_chain)
333 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
338 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
339 struct mlx5_flow_handle *rule,
340 struct mlx5_esw_flow_attr *attr)
342 __mlx5_eswitch_del_rule(esw, rule, attr, false);
346 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
347 struct mlx5_flow_handle *rule,
348 struct mlx5_esw_flow_attr *attr)
350 __mlx5_eswitch_del_rule(esw, rule, attr, true);
353 static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
355 struct mlx5_eswitch_rep *rep;
358 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
359 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
360 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
363 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
372 static struct mlx5_eswitch_rep *
373 esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
375 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
377 in_rep = attr->in_rep;
378 out_rep = attr->dests[0].rep;
390 static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
391 bool push, bool pop, bool fwd)
393 struct mlx5_eswitch_rep *in_rep, *out_rep;
395 if ((push || pop) && !fwd)
398 in_rep = attr->in_rep;
399 out_rep = attr->dests[0].rep;
401 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
404 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
407 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
408 if (!push && !pop && fwd)
409 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
412 /* protects against (1) setting rules with different vlans to push and
413 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
415 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
424 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
425 struct mlx5_esw_flow_attr *attr)
427 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
428 struct mlx5_eswitch_rep *vport = NULL;
432 /* nop if we're on the vlan push/pop non emulation mode */
433 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
436 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
437 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
438 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
441 err = esw_add_vlan_action_check(attr, push, pop, fwd);
445 attr->vlan_handled = false;
447 vport = esw_vlan_action_get_vport(attr, push, pop);
449 if (!push && !pop && fwd) {
450 /* tracks VF --> wire rules without vlan push action */
451 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
452 vport->vlan_refcount++;
453 attr->vlan_handled = true;
462 if (!(offloads->vlan_push_pop_refcount)) {
463 /* it's the 1st vlan rule, apply global vlan pop policy */
464 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
468 offloads->vlan_push_pop_refcount++;
471 if (vport->vlan_refcount)
474 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
475 SET_VLAN_INSERT | SET_VLAN_STRIP);
478 vport->vlan = attr->vlan_vid[0];
480 vport->vlan_refcount++;
484 attr->vlan_handled = true;
488 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
489 struct mlx5_esw_flow_attr *attr)
491 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
492 struct mlx5_eswitch_rep *vport = NULL;
496 /* nop if we're on the vlan push/pop non emulation mode */
497 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
500 if (!attr->vlan_handled)
503 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
504 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
505 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
507 vport = esw_vlan_action_get_vport(attr, push, pop);
509 if (!push && !pop && fwd) {
510 /* tracks VF --> wire rules without vlan push action */
511 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
512 vport->vlan_refcount--;
518 vport->vlan_refcount--;
519 if (vport->vlan_refcount)
520 goto skip_unset_push;
523 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
524 0, 0, SET_VLAN_STRIP);
530 offloads->vlan_push_pop_refcount--;
531 if (offloads->vlan_push_pop_refcount)
534 /* no more vlan rules, stop global vlan pop policy */
535 err = esw_set_global_vlan_pop(esw, 0);
541 struct mlx5_flow_handle *
542 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
545 struct mlx5_flow_act flow_act = {0};
546 struct mlx5_flow_destination dest = {};
547 struct mlx5_flow_handle *flow_rule;
548 struct mlx5_flow_spec *spec;
551 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
553 flow_rule = ERR_PTR(-ENOMEM);
557 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
558 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
559 /* source vport is the esw manager */
560 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
562 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
563 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
564 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
566 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
567 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
568 dest.vport.num = vport;
569 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
571 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
572 &flow_act, &dest, 1);
573 if (IS_ERR(flow_rule))
574 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
579 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
581 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
583 mlx5_del_flow_rules(rule);
586 static int mlx5_eswitch_enable_passing_vport_metadata(struct mlx5_eswitch *esw)
588 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
589 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
590 u8 fdb_to_vport_reg_c_id;
593 err = mlx5_eswitch_query_esw_vport_context(esw, esw->manager_vport,
598 fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
599 esw_vport_context.fdb_to_vport_reg_c_id);
601 fdb_to_vport_reg_c_id |= MLX5_FDB_TO_VPORT_REG_C_0;
602 MLX5_SET(modify_esw_vport_context_in, in,
603 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);
605 MLX5_SET(modify_esw_vport_context_in, in,
606 field_select.fdb_to_vport_reg_c_id, 1);
608 return mlx5_eswitch_modify_esw_vport_context(esw, esw->manager_vport,
612 static int mlx5_eswitch_disable_passing_vport_metadata(struct mlx5_eswitch *esw)
614 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
615 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
616 u8 fdb_to_vport_reg_c_id;
619 err = mlx5_eswitch_query_esw_vport_context(esw, esw->manager_vport,
624 fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
625 esw_vport_context.fdb_to_vport_reg_c_id);
627 fdb_to_vport_reg_c_id &= ~MLX5_FDB_TO_VPORT_REG_C_0;
629 MLX5_SET(modify_esw_vport_context_in, in,
630 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);
632 MLX5_SET(modify_esw_vport_context_in, in,
633 field_select.fdb_to_vport_reg_c_id, 1);
635 return mlx5_eswitch_modify_esw_vport_context(esw, esw->manager_vport,
639 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
640 struct mlx5_core_dev *peer_dev,
641 struct mlx5_flow_spec *spec,
642 struct mlx5_flow_destination *dest)
646 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
647 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
649 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
651 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
653 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
656 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
657 MLX5_CAP_GEN(peer_dev, vhca_id));
659 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
661 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
663 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
664 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
665 source_eswitch_owner_vhca_id);
668 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
669 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
670 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
671 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
674 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
675 struct mlx5_eswitch *peer_esw,
676 struct mlx5_flow_spec *spec,
681 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
682 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
684 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
685 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
688 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
690 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
694 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
695 struct mlx5_core_dev *peer_dev)
697 struct mlx5_flow_destination dest = {};
698 struct mlx5_flow_act flow_act = {0};
699 struct mlx5_flow_handle **flows;
700 struct mlx5_flow_handle *flow;
701 struct mlx5_flow_spec *spec;
702 /* total vports is the same for both e-switches */
703 int nvports = esw->total_vports;
707 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
711 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
713 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
716 goto alloc_flows_err;
719 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
720 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
723 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
724 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
725 spec, MLX5_VPORT_PF);
727 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
728 spec, &flow_act, &dest, 1);
731 goto add_pf_flow_err;
733 flows[MLX5_VPORT_PF] = flow;
736 if (mlx5_ecpf_vport_exists(esw->dev)) {
737 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
738 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
739 spec, &flow_act, &dest, 1);
742 goto add_ecpf_flow_err;
744 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
747 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
748 esw_set_peer_miss_rule_source_port(esw,
749 peer_dev->priv.eswitch,
752 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
753 spec, &flow_act, &dest, 1);
756 goto add_vf_flow_err;
761 esw->fdb_table.offloads.peer_miss_rules = flows;
768 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
769 mlx5_del_flow_rules(flows[i]);
771 if (mlx5_ecpf_vport_exists(esw->dev))
772 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
774 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
775 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
777 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
784 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
786 struct mlx5_flow_handle **flows;
789 flows = esw->fdb_table.offloads.peer_miss_rules;
791 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
792 mlx5_core_max_vfs(esw->dev))
793 mlx5_del_flow_rules(flows[i]);
795 if (mlx5_ecpf_vport_exists(esw->dev))
796 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
798 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
799 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
804 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
806 struct mlx5_flow_act flow_act = {0};
807 struct mlx5_flow_destination dest = {};
808 struct mlx5_flow_handle *flow_rule = NULL;
809 struct mlx5_flow_spec *spec;
816 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
822 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
823 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
825 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
826 outer_headers.dmac_47_16);
829 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
830 dest.vport.num = esw->manager_vport;
831 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
833 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
834 &flow_act, &dest, 1);
835 if (IS_ERR(flow_rule)) {
836 err = PTR_ERR(flow_rule);
837 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
841 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
843 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
845 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
846 outer_headers.dmac_47_16);
848 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
849 &flow_act, &dest, 1);
850 if (IS_ERR(flow_rule)) {
851 err = PTR_ERR(flow_rule);
852 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
853 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
857 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
864 #define ESW_OFFLOADS_NUM_GROUPS 4
866 /* Firmware currently has 4 pool of 4 sizes that it supports (ESW_POOLS),
867 * and a virtual memory region of 16M (ESW_SIZE), this region is duplicated
868 * for each flow table pool. We can allocate up to 16M of each pool,
869 * and we keep track of how much we used via put/get_sz_to_pool.
870 * Firmware doesn't report any of this for now.
871 * ESW_POOL is expected to be sorted from large to small
873 #define ESW_SIZE (16 * 1024 * 1024)
874 const unsigned int ESW_POOLS[4] = { 4 * 1024 * 1024, 1 * 1024 * 1024,
875 64 * 1024, 4 * 1024 };
878 get_sz_from_pool(struct mlx5_eswitch *esw)
882 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
883 if (esw->fdb_table.offloads.fdb_left[i]) {
884 --esw->fdb_table.offloads.fdb_left[i];
894 put_sz_to_pool(struct mlx5_eswitch *esw, int sz)
898 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
899 if (sz >= ESW_POOLS[i]) {
900 ++esw->fdb_table.offloads.fdb_left[i];
906 static struct mlx5_flow_table *
907 create_next_size_table(struct mlx5_eswitch *esw,
908 struct mlx5_flow_namespace *ns,
913 struct mlx5_flow_table *fdb;
916 sz = get_sz_from_pool(esw);
918 return ERR_PTR(-ENOSPC);
920 fdb = mlx5_create_auto_grouped_flow_table(ns,
923 ESW_OFFLOADS_NUM_GROUPS,
927 esw_warn(esw->dev, "Failed to create FDB Table err %d (table prio: %d, level: %d, size: %d)\n",
928 (int)PTR_ERR(fdb), table_prio, level, sz);
929 put_sz_to_pool(esw, sz);
935 static struct mlx5_flow_table *
936 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
938 struct mlx5_core_dev *dev = esw->dev;
939 struct mlx5_flow_table *fdb = NULL;
940 struct mlx5_flow_namespace *ns;
941 int table_prio, l = 0;
944 if (chain == FDB_SLOW_PATH_CHAIN)
945 return esw->fdb_table.offloads.slow_fdb;
947 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
949 fdb = fdb_prio_table(esw, chain, prio, level).fdb;
951 /* take ref on earlier levels as well */
953 fdb_prio_table(esw, chain, prio, level--).num_rules++;
954 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
958 ns = mlx5_get_fdb_sub_ns(dev, chain);
960 esw_warn(dev, "Failed to get FDB sub namespace\n");
961 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
962 return ERR_PTR(-EOPNOTSUPP);
965 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
966 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
967 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
969 table_prio = (chain * FDB_MAX_PRIO) + prio - 1;
971 /* create earlier levels for correct fs_core lookup when
974 for (l = 0; l <= level; l++) {
975 if (fdb_prio_table(esw, chain, prio, l).fdb) {
976 fdb_prio_table(esw, chain, prio, l).num_rules++;
980 fdb = create_next_size_table(esw, ns, table_prio, l, flags);
986 fdb_prio_table(esw, chain, prio, l).fdb = fdb;
987 fdb_prio_table(esw, chain, prio, l).num_rules = 1;
990 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
994 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
996 esw_put_prio_table(esw, chain, prio, l);
1002 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
1006 if (chain == FDB_SLOW_PATH_CHAIN)
1009 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
1011 for (l = level; l >= 0; l--) {
1012 if (--(fdb_prio_table(esw, chain, prio, l).num_rules) > 0)
1015 put_sz_to_pool(esw, fdb_prio_table(esw, chain, prio, l).fdb->max_fte);
1016 mlx5_destroy_flow_table(fdb_prio_table(esw, chain, prio, l).fdb);
1017 fdb_prio_table(esw, chain, prio, l).fdb = NULL;
1020 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
1023 static void esw_destroy_offloads_fast_fdb_tables(struct mlx5_eswitch *esw)
1025 /* If lazy creation isn't supported, deref the fast path tables */
1026 if (!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)) {
1027 esw_put_prio_table(esw, 0, 1, 1);
1028 esw_put_prio_table(esw, 0, 1, 0);
1032 #define MAX_PF_SQ 256
1033 #define MAX_SQ_NVPORTS 32
1035 static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1038 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1042 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1043 MLX5_SET(create_flow_group_in, flow_group_in,
1044 match_criteria_enable,
1045 MLX5_MATCH_MISC_PARAMETERS_2);
1047 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1048 misc_parameters_2.metadata_reg_c_0);
1050 MLX5_SET(create_flow_group_in, flow_group_in,
1051 match_criteria_enable,
1052 MLX5_MATCH_MISC_PARAMETERS);
1054 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1055 misc_parameters.source_port);
1059 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
1061 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1062 struct mlx5_flow_table_attr ft_attr = {};
1063 struct mlx5_core_dev *dev = esw->dev;
1064 u32 *flow_group_in, max_flow_counter;
1065 struct mlx5_flow_namespace *root_ns;
1066 struct mlx5_flow_table *fdb = NULL;
1067 int table_size, ix, err = 0, i;
1068 struct mlx5_flow_group *g;
1069 u32 flags = 0, fdb_max;
1070 void *match_criteria;
1073 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1074 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1078 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1080 esw_warn(dev, "Failed to get FDB flow namespace\n");
1085 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1086 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1087 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1089 esw_debug(dev, "Create offloads FDB table, min (max esw size(2^%d), max counters(%d), groups(%d), max flow table size(2^%d))\n",
1090 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size),
1091 max_flow_counter, ESW_OFFLOADS_NUM_GROUPS,
1094 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++)
1095 esw->fdb_table.offloads.fdb_left[i] =
1096 ESW_POOLS[i] <= fdb_max ? ESW_SIZE / ESW_POOLS[i] : 0;
1098 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1099 MLX5_ESW_MISS_FLOWS + esw->total_vports;
1101 /* create the slow path fdb with encap set, so further table instances
1102 * can be created at run time while VFs are probed if the FW allows that.
1104 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1105 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1106 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1108 ft_attr.flags = flags;
1109 ft_attr.max_fte = table_size;
1110 ft_attr.prio = FDB_SLOW_PATH;
1112 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1115 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1118 esw->fdb_table.offloads.slow_fdb = fdb;
1120 /* If lazy creation isn't supported, open the fast path tables now */
1121 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, multi_fdb_encap) &&
1122 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1123 esw->fdb_table.flags &= ~ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
1124 esw_warn(dev, "Lazy creation of flow tables isn't supported, ignoring priorities\n");
1125 esw_get_prio_table(esw, 0, 1, 0);
1126 esw_get_prio_table(esw, 0, 1, 1);
1128 esw_debug(dev, "Lazy creation of flow tables supported, deferring table opening\n");
1129 esw->fdb_table.flags |= ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
1132 /* create send-to-vport group */
1133 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1134 MLX5_MATCH_MISC_PARAMETERS);
1136 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1138 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1139 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1141 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
1142 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1143 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1145 g = mlx5_create_flow_group(fdb, flow_group_in);
1148 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1149 goto send_vport_err;
1151 esw->fdb_table.offloads.send_to_vport_grp = g;
1153 /* create peer esw miss group */
1154 memset(flow_group_in, 0, inlen);
1156 esw_set_flow_group_source_port(esw, flow_group_in);
1158 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1159 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1163 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1164 misc_parameters.source_eswitch_owner_vhca_id);
1166 MLX5_SET(create_flow_group_in, flow_group_in,
1167 source_eswitch_owner_vhca_id_valid, 1);
1170 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1171 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1172 ix + esw->total_vports - 1);
1173 ix += esw->total_vports;
1175 g = mlx5_create_flow_group(fdb, flow_group_in);
1178 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1181 esw->fdb_table.offloads.peer_miss_grp = g;
1183 /* create miss group */
1184 memset(flow_group_in, 0, inlen);
1185 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1186 MLX5_MATCH_OUTER_HEADERS);
1187 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1189 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1190 outer_headers.dmac_47_16);
1193 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1194 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1195 ix + MLX5_ESW_MISS_FLOWS);
1197 g = mlx5_create_flow_group(fdb, flow_group_in);
1200 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1203 esw->fdb_table.offloads.miss_grp = g;
1205 err = esw_add_fdb_miss_rule(esw);
1209 esw->nvports = nvports;
1210 kvfree(flow_group_in);
1214 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1216 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1218 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1220 esw_destroy_offloads_fast_fdb_tables(esw);
1221 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1224 kvfree(flow_group_in);
1228 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1230 if (!esw->fdb_table.offloads.slow_fdb)
1233 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1234 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1235 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1236 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1237 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1238 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1240 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1241 esw_destroy_offloads_fast_fdb_tables(esw);
1244 static int esw_create_offloads_table(struct mlx5_eswitch *esw, int nvports)
1246 struct mlx5_flow_table_attr ft_attr = {};
1247 struct mlx5_core_dev *dev = esw->dev;
1248 struct mlx5_flow_table *ft_offloads;
1249 struct mlx5_flow_namespace *ns;
1252 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1254 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1258 ft_attr.max_fte = nvports + MLX5_ESW_MISS_FLOWS;
1260 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1261 if (IS_ERR(ft_offloads)) {
1262 err = PTR_ERR(ft_offloads);
1263 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1267 esw->offloads.ft_offloads = ft_offloads;
1271 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1273 struct mlx5_esw_offload *offloads = &esw->offloads;
1275 mlx5_destroy_flow_table(offloads->ft_offloads);
1278 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw, int nvports)
1280 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1281 struct mlx5_flow_group *g;
1285 nvports = nvports + MLX5_ESW_MISS_FLOWS;
1286 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1290 /* create vport rx group */
1291 esw_set_flow_group_source_port(esw, flow_group_in);
1293 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1294 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1296 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1300 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1304 esw->offloads.vport_rx_group = g;
1306 kvfree(flow_group_in);
1310 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1312 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1315 struct mlx5_flow_handle *
1316 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1317 struct mlx5_flow_destination *dest)
1319 struct mlx5_flow_act flow_act = {0};
1320 struct mlx5_flow_handle *flow_rule;
1321 struct mlx5_flow_spec *spec;
1324 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1326 flow_rule = ERR_PTR(-ENOMEM);
1330 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1331 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1332 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1333 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
1335 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
1336 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
1338 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1340 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1341 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1343 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1344 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1346 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1349 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1350 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1351 &flow_act, dest, 1);
1352 if (IS_ERR(flow_rule)) {
1353 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1362 static int esw_offloads_start(struct mlx5_eswitch *esw,
1363 struct netlink_ext_ack *extack)
1367 if (esw->mode != MLX5_ESWITCH_LEGACY &&
1368 !mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1369 NL_SET_ERR_MSG_MOD(extack,
1370 "Can't set offloads mode, SRIOV legacy not enabled");
1374 mlx5_eswitch_disable(esw);
1375 mlx5_eswitch_update_num_of_vfs(esw, esw->dev->priv.sriov.num_vfs);
1376 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
1378 NL_SET_ERR_MSG_MOD(extack,
1379 "Failed setting eswitch to offloads");
1380 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
1382 NL_SET_ERR_MSG_MOD(extack,
1383 "Failed setting eswitch back to legacy");
1386 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1387 if (mlx5_eswitch_inline_mode_get(esw,
1388 &esw->offloads.inline_mode)) {
1389 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
1390 NL_SET_ERR_MSG_MOD(extack,
1391 "Inline mode is different between vports");
1397 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1399 kfree(esw->offloads.vport_reps);
1402 int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1404 int total_vports = esw->total_vports;
1405 struct mlx5_core_dev *dev = esw->dev;
1406 struct mlx5_eswitch_rep *rep;
1407 u8 hw_id[ETH_ALEN], rep_type;
1410 esw->offloads.vport_reps = kcalloc(total_vports,
1411 sizeof(struct mlx5_eswitch_rep),
1413 if (!esw->offloads.vport_reps)
1416 mlx5_query_mac_address(dev, hw_id);
1418 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1419 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
1420 rep->vport_index = vport_index;
1421 ether_addr_copy(rep->hw_id, hw_id);
1423 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1424 atomic_set(&rep->rep_data[rep_type].state,
1431 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1432 struct mlx5_eswitch_rep *rep, u8 rep_type)
1434 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1435 REP_LOADED, REP_REGISTERED) == REP_LOADED)
1436 esw->offloads.rep_ops[rep_type]->unload(rep);
1439 static void __unload_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1441 struct mlx5_eswitch_rep *rep;
1443 if (mlx5_ecpf_vport_exists(esw->dev)) {
1444 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1445 __esw_offloads_unload_rep(esw, rep, rep_type);
1448 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1449 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1450 __esw_offloads_unload_rep(esw, rep, rep_type);
1453 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1454 __esw_offloads_unload_rep(esw, rep, rep_type);
1457 static void __unload_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1460 struct mlx5_eswitch_rep *rep;
1463 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvports)
1464 __esw_offloads_unload_rep(esw, rep, rep_type);
1467 static void esw_offloads_unload_vf_reps(struct mlx5_eswitch *esw, int nvports)
1469 u8 rep_type = NUM_REP_TYPES;
1471 while (rep_type-- > 0)
1472 __unload_reps_vf_vport(esw, nvports, rep_type);
1475 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1477 __unload_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1479 /* Special vports must be the last to unload. */
1480 __unload_reps_special_vport(esw, rep_type);
1483 static void esw_offloads_unload_all_reps(struct mlx5_eswitch *esw)
1485 u8 rep_type = NUM_REP_TYPES;
1487 while (rep_type-- > 0)
1488 __unload_reps_all_vport(esw, rep_type);
1491 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
1492 struct mlx5_eswitch_rep *rep, u8 rep_type)
1496 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1497 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1498 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1500 atomic_set(&rep->rep_data[rep_type].state,
1507 static int __load_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1509 struct mlx5_eswitch_rep *rep;
1512 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1513 err = __esw_offloads_load_rep(esw, rep, rep_type);
1517 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1518 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1519 err = __esw_offloads_load_rep(esw, rep, rep_type);
1524 if (mlx5_ecpf_vport_exists(esw->dev)) {
1525 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1526 err = __esw_offloads_load_rep(esw, rep, rep_type);
1534 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1535 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1536 __esw_offloads_unload_rep(esw, rep, rep_type);
1540 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1541 __esw_offloads_unload_rep(esw, rep, rep_type);
1545 static int __load_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1548 struct mlx5_eswitch_rep *rep;
1551 mlx5_esw_for_each_vf_rep(esw, i, rep, nvports) {
1552 err = __esw_offloads_load_rep(esw, rep, rep_type);
1560 __unload_reps_vf_vport(esw, --i, rep_type);
1564 static int __load_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1568 /* Special vports must be loaded first, uplink rep creates mdev resource. */
1569 err = __load_reps_special_vport(esw, rep_type);
1573 err = __load_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1580 __unload_reps_special_vport(esw, rep_type);
1584 static int esw_offloads_load_vf_reps(struct mlx5_eswitch *esw, int nvports)
1589 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1590 err = __load_reps_vf_vport(esw, nvports, rep_type);
1598 while (rep_type-- > 0)
1599 __unload_reps_vf_vport(esw, nvports, rep_type);
1603 static int esw_offloads_load_all_reps(struct mlx5_eswitch *esw)
1608 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1609 err = __load_reps_all_vport(esw, rep_type);
1617 while (rep_type-- > 0)
1618 __unload_reps_all_vport(esw, rep_type);
1622 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
1623 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1625 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1626 struct mlx5_eswitch *peer_esw)
1630 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1637 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1639 mlx5e_tc_clean_fdb_peer_flows(esw);
1640 esw_del_fdb_peer_miss_rules(esw);
1643 static int mlx5_esw_offloads_devcom_event(int event,
1647 struct mlx5_eswitch *esw = my_data;
1648 struct mlx5_eswitch *peer_esw = event_data;
1649 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1653 case ESW_OFFLOADS_DEVCOM_PAIR:
1654 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1655 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1658 err = mlx5_esw_offloads_pair(esw, peer_esw);
1662 err = mlx5_esw_offloads_pair(peer_esw, esw);
1666 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1669 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1670 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1673 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1674 mlx5_esw_offloads_unpair(peer_esw);
1675 mlx5_esw_offloads_unpair(esw);
1682 mlx5_esw_offloads_unpair(esw);
1685 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1690 static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1692 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1694 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1695 mutex_init(&esw->offloads.peer_mutex);
1697 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1700 mlx5_devcom_register_component(devcom,
1701 MLX5_DEVCOM_ESW_OFFLOADS,
1702 mlx5_esw_offloads_devcom_event,
1705 mlx5_devcom_send_event(devcom,
1706 MLX5_DEVCOM_ESW_OFFLOADS,
1707 ESW_OFFLOADS_DEVCOM_PAIR, esw);
1710 static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
1712 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1714 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1717 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1718 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
1720 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1723 static int esw_vport_ingress_prio_tag_config(struct mlx5_eswitch *esw,
1724 struct mlx5_vport *vport)
1726 struct mlx5_flow_act flow_act = {0};
1727 struct mlx5_flow_spec *spec;
1730 /* For prio tag mode, there is only 1 FTEs:
1731 * 1) Untagged packets - push prio tag VLAN and modify metadata if
1733 * Unmatched traffic is allowed by default
1736 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1742 /* Untagged packets - push prio tag VLAN, allow */
1743 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1744 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 0);
1745 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1746 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
1747 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1748 flow_act.vlan[0].ethtype = ETH_P_8021Q;
1749 flow_act.vlan[0].vid = 0;
1750 flow_act.vlan[0].prio = 0;
1752 if (vport->ingress.modify_metadata_rule) {
1753 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1754 flow_act.modify_id = vport->ingress.modify_metadata_id;
1757 vport->ingress.allow_rule =
1758 mlx5_add_flow_rules(vport->ingress.acl, spec,
1759 &flow_act, NULL, 0);
1760 if (IS_ERR(vport->ingress.allow_rule)) {
1761 err = PTR_ERR(vport->ingress.allow_rule);
1763 "vport[%d] configure ingress untagged allow rule, err(%d)\n",
1765 vport->ingress.allow_rule = NULL;
1773 esw_vport_cleanup_ingress_rules(esw, vport);
1777 static int esw_vport_add_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1778 struct mlx5_vport *vport)
1780 u8 action[MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)] = {};
1781 static const struct mlx5_flow_spec spec = {};
1782 struct mlx5_flow_act flow_act = {};
1785 MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET);
1786 MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_C_0);
1787 MLX5_SET(set_action_in, action, data,
1788 mlx5_eswitch_get_vport_metadata_for_match(esw, vport->vport));
1790 err = mlx5_modify_header_alloc(esw->dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS,
1791 1, action, &vport->ingress.modify_metadata_id);
1794 "failed to alloc modify header for vport %d ingress acl (%d)\n",
1799 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1800 flow_act.modify_id = vport->ingress.modify_metadata_id;
1801 vport->ingress.modify_metadata_rule = mlx5_add_flow_rules(vport->ingress.acl,
1802 &spec, &flow_act, NULL, 0);
1803 if (IS_ERR(vport->ingress.modify_metadata_rule)) {
1804 err = PTR_ERR(vport->ingress.modify_metadata_rule);
1806 "failed to add setting metadata rule for vport %d ingress acl, err(%d)\n",
1808 vport->ingress.modify_metadata_rule = NULL;
1814 mlx5_modify_header_dealloc(esw->dev, vport->ingress.modify_metadata_id);
1818 void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1819 struct mlx5_vport *vport)
1821 if (vport->ingress.modify_metadata_rule) {
1822 mlx5_del_flow_rules(vport->ingress.modify_metadata_rule);
1823 mlx5_modify_header_dealloc(esw->dev, vport->ingress.modify_metadata_id);
1825 vport->ingress.modify_metadata_rule = NULL;
1829 static int esw_vport_egress_prio_tag_config(struct mlx5_eswitch *esw,
1830 struct mlx5_vport *vport)
1832 struct mlx5_flow_act flow_act = {0};
1833 struct mlx5_flow_spec *spec;
1836 if (!MLX5_CAP_GEN(esw->dev, prio_tag_required))
1839 /* For prio tag mode, there is only 1 FTEs:
1840 * 1) prio tag packets - pop the prio tag VLAN, allow
1841 * Unmatched traffic is allowed by default
1844 esw_vport_cleanup_egress_rules(esw, vport);
1846 err = esw_vport_enable_egress_acl(esw, vport);
1848 mlx5_core_warn(esw->dev,
1849 "failed to enable egress acl (%d) on vport[%d]\n",
1855 "vport[%d] configure prio tag egress rules\n", vport->vport);
1857 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1863 /* prio tag vlan rule - pop it so VF receives untagged packets */
1864 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1865 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag);
1866 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1867 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, 0);
1869 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1870 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
1871 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1872 vport->egress.allowed_vlan =
1873 mlx5_add_flow_rules(vport->egress.acl, spec,
1874 &flow_act, NULL, 0);
1875 if (IS_ERR(vport->egress.allowed_vlan)) {
1876 err = PTR_ERR(vport->egress.allowed_vlan);
1878 "vport[%d] configure egress pop prio tag vlan rule failed, err(%d)\n",
1880 vport->egress.allowed_vlan = NULL;
1888 esw_vport_cleanup_egress_rules(esw, vport);
1892 static int esw_vport_ingress_common_config(struct mlx5_eswitch *esw,
1893 struct mlx5_vport *vport)
1897 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1898 !MLX5_CAP_GEN(esw->dev, prio_tag_required))
1901 esw_vport_cleanup_ingress_rules(esw, vport);
1903 err = esw_vport_enable_ingress_acl(esw, vport);
1906 "failed to enable ingress acl (%d) on vport[%d]\n",
1912 "vport[%d] configure ingress rules\n", vport->vport);
1914 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1915 err = esw_vport_add_ingress_acl_modify_metadata(esw, vport);
1920 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
1921 mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
1922 err = esw_vport_ingress_prio_tag_config(esw, vport);
1929 esw_vport_disable_ingress_acl(esw, vport);
1934 esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
1936 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
1939 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1940 MLX5_FDB_TO_VPORT_REG_C_0))
1943 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
1946 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
1947 mlx5_ecpf_vport_exists(esw->dev))
1953 static int esw_create_offloads_acl_tables(struct mlx5_eswitch *esw)
1955 struct mlx5_vport *vport;
1959 if (esw_check_vport_match_metadata_supported(esw))
1960 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
1962 mlx5_esw_for_all_vports(esw, i, vport) {
1963 err = esw_vport_ingress_common_config(esw, vport);
1967 if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
1968 err = esw_vport_egress_prio_tag_config(esw, vport);
1974 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
1975 esw_info(esw->dev, "Use metadata reg_c as source vport to match\n");
1980 esw_vport_disable_ingress_acl(esw, vport);
1982 for (j = MLX5_VPORT_PF; j < i; j++) {
1983 vport = &esw->vports[j];
1984 esw_vport_disable_egress_acl(esw, vport);
1985 esw_vport_disable_ingress_acl(esw, vport);
1991 static void esw_destroy_offloads_acl_tables(struct mlx5_eswitch *esw)
1993 struct mlx5_vport *vport;
1996 mlx5_esw_for_all_vports(esw, i, vport) {
1997 esw_vport_disable_egress_acl(esw, vport);
1998 esw_vport_disable_ingress_acl(esw, vport);
2001 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2004 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
2006 int num_vfs = esw->esw_funcs.num_vfs;
2010 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
2011 total_vports = esw->total_vports;
2013 total_vports = num_vfs + MLX5_SPECIAL_VPORTS(esw->dev);
2015 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
2016 mutex_init(&esw->fdb_table.offloads.fdb_prio_lock);
2018 err = esw_create_offloads_acl_tables(esw);
2022 err = esw_create_offloads_fdb_tables(esw, total_vports);
2024 goto create_fdb_err;
2026 err = esw_create_offloads_table(esw, total_vports);
2030 err = esw_create_vport_rx_group(esw, total_vports);
2037 esw_destroy_offloads_table(esw);
2040 esw_destroy_offloads_fdb_tables(esw);
2043 esw_destroy_offloads_acl_tables(esw);
2048 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2050 esw_destroy_vport_rx_group(esw);
2051 esw_destroy_offloads_table(esw);
2052 esw_destroy_offloads_fdb_tables(esw);
2053 esw_destroy_offloads_acl_tables(esw);
2057 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
2059 bool host_pf_disabled;
2062 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2063 host_params_context.host_num_of_vfs);
2064 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2065 host_params_context.host_pf_disabled);
2067 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2070 /* Number of VFs can only change from "0 to x" or "x to 0". */
2071 if (esw->esw_funcs.num_vfs > 0) {
2072 esw_offloads_unload_vf_reps(esw, esw->esw_funcs.num_vfs);
2076 err = esw_offloads_load_vf_reps(esw, new_num_vfs);
2080 esw->esw_funcs.num_vfs = new_num_vfs;
2083 static void esw_functions_changed_event_handler(struct work_struct *work)
2085 struct mlx5_host_work *host_work;
2086 struct mlx5_eswitch *esw;
2089 host_work = container_of(work, struct mlx5_host_work, work);
2090 esw = host_work->esw;
2092 out = mlx5_esw_query_functions(esw->dev);
2096 esw_vfs_changed_event_handler(esw, out);
2102 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
2104 struct mlx5_esw_functions *esw_funcs;
2105 struct mlx5_host_work *host_work;
2106 struct mlx5_eswitch *esw;
2108 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2112 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2113 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
2115 host_work->esw = esw;
2117 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
2118 queue_work(esw->work_queue, &host_work->work);
2123 int esw_offloads_init(struct mlx5_eswitch *esw)
2127 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2128 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2129 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2131 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2133 err = esw_offloads_steering_init(esw);
2137 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2138 err = mlx5_eswitch_enable_passing_vport_metadata(esw);
2140 goto err_vport_metadata;
2143 err = esw_offloads_load_all_reps(esw);
2147 esw_offloads_devcom_init(esw);
2148 mutex_init(&esw->offloads.termtbl_mutex);
2150 mlx5_rdma_enable_roce(esw->dev);
2155 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
2156 mlx5_eswitch_disable_passing_vport_metadata(esw);
2158 esw_offloads_steering_cleanup(esw);
2162 static int esw_offloads_stop(struct mlx5_eswitch *esw,
2163 struct netlink_ext_ack *extack)
2167 mlx5_eswitch_disable(esw);
2168 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
2170 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
2171 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
2173 NL_SET_ERR_MSG_MOD(extack,
2174 "Failed setting eswitch back to offloads");
2181 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2183 mlx5_rdma_disable_roce(esw->dev);
2184 esw_offloads_devcom_cleanup(esw);
2185 esw_offloads_unload_all_reps(esw);
2186 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
2187 mlx5_eswitch_disable_passing_vport_metadata(esw);
2188 esw_offloads_steering_cleanup(esw);
2189 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2192 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
2195 case DEVLINK_ESWITCH_MODE_LEGACY:
2196 *mlx5_mode = MLX5_ESWITCH_LEGACY;
2198 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
2199 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
2208 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2210 switch (mlx5_mode) {
2211 case MLX5_ESWITCH_LEGACY:
2212 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2214 case MLX5_ESWITCH_OFFLOADS:
2215 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2224 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2227 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2228 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2230 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2231 *mlx5_mode = MLX5_INLINE_MODE_L2;
2233 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2234 *mlx5_mode = MLX5_INLINE_MODE_IP;
2236 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2237 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2246 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2248 switch (mlx5_mode) {
2249 case MLX5_INLINE_MODE_NONE:
2250 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2252 case MLX5_INLINE_MODE_L2:
2253 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2255 case MLX5_INLINE_MODE_IP:
2256 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2258 case MLX5_INLINE_MODE_TCP_UDP:
2259 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2268 static int mlx5_devlink_eswitch_check(struct devlink *devlink)
2270 struct mlx5_core_dev *dev = devlink_priv(devlink);
2272 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2275 if(!MLX5_ESWITCH_MANAGER(dev))
2278 if (dev->priv.eswitch->mode == MLX5_ESWITCH_NONE &&
2279 !mlx5_core_is_ecpf_esw_manager(dev))
2285 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2286 struct netlink_ext_ack *extack)
2288 struct mlx5_core_dev *dev = devlink_priv(devlink);
2289 u16 cur_mlx5_mode, mlx5_mode = 0;
2292 err = mlx5_devlink_eswitch_check(devlink);
2296 cur_mlx5_mode = dev->priv.eswitch->mode;
2298 if (esw_mode_from_devlink(mode, &mlx5_mode))
2301 if (cur_mlx5_mode == mlx5_mode)
2304 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
2305 return esw_offloads_start(dev->priv.eswitch, extack);
2306 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
2307 return esw_offloads_stop(dev->priv.eswitch, extack);
2312 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2314 struct mlx5_core_dev *dev = devlink_priv(devlink);
2317 err = mlx5_devlink_eswitch_check(devlink);
2321 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
2324 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2325 struct netlink_ext_ack *extack)
2327 struct mlx5_core_dev *dev = devlink_priv(devlink);
2328 struct mlx5_eswitch *esw = dev->priv.eswitch;
2329 int err, vport, num_vport;
2332 err = mlx5_devlink_eswitch_check(devlink);
2336 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2337 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2338 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
2341 case MLX5_CAP_INLINE_MODE_L2:
2342 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
2344 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2348 if (esw->offloads.num_flows > 0) {
2349 NL_SET_ERR_MSG_MOD(extack,
2350 "Can't set inline mode when flows are configured");
2354 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2358 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2359 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2361 NL_SET_ERR_MSG_MOD(extack,
2362 "Failed to set min inline on vport");
2363 goto revert_inline_mode;
2367 esw->offloads.inline_mode = mlx5_mode;
2371 num_vport = --vport;
2372 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
2373 mlx5_modify_nic_vport_min_inline(dev,
2375 esw->offloads.inline_mode);
2380 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2382 struct mlx5_core_dev *dev = devlink_priv(devlink);
2383 struct mlx5_eswitch *esw = dev->priv.eswitch;
2386 err = mlx5_devlink_eswitch_check(devlink);
2390 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2393 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2395 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2396 struct mlx5_core_dev *dev = esw->dev;
2399 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2402 if (esw->mode == MLX5_ESWITCH_NONE)
2405 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2406 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2407 mlx5_mode = MLX5_INLINE_MODE_NONE;
2409 case MLX5_CAP_INLINE_MODE_L2:
2410 mlx5_mode = MLX5_INLINE_MODE_L2;
2412 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2417 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2418 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2419 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
2420 if (prev_mlx5_mode != mlx5_mode)
2422 prev_mlx5_mode = mlx5_mode;
2430 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2431 enum devlink_eswitch_encap_mode encap,
2432 struct netlink_ext_ack *extack)
2434 struct mlx5_core_dev *dev = devlink_priv(devlink);
2435 struct mlx5_eswitch *esw = dev->priv.eswitch;
2438 err = mlx5_devlink_eswitch_check(devlink);
2442 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
2443 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
2444 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)))
2447 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC)
2450 if (esw->mode == MLX5_ESWITCH_LEGACY) {
2451 esw->offloads.encap = encap;
2455 if (esw->offloads.encap == encap)
2458 if (esw->offloads.num_flows > 0) {
2459 NL_SET_ERR_MSG_MOD(extack,
2460 "Can't set encapsulation when flows are configured");
2464 esw_destroy_offloads_fdb_tables(esw);
2466 esw->offloads.encap = encap;
2468 err = esw_create_offloads_fdb_tables(esw, esw->nvports);
2471 NL_SET_ERR_MSG_MOD(extack,
2472 "Failed re-creating fast FDB table");
2473 esw->offloads.encap = !encap;
2474 (void)esw_create_offloads_fdb_tables(esw, esw->nvports);
2480 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2481 enum devlink_eswitch_encap_mode *encap)
2483 struct mlx5_core_dev *dev = devlink_priv(devlink);
2484 struct mlx5_eswitch *esw = dev->priv.eswitch;
2487 err = mlx5_devlink_eswitch_check(devlink);
2491 *encap = esw->offloads.encap;
2495 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
2496 const struct mlx5_eswitch_rep_ops *ops,
2499 struct mlx5_eswitch_rep_data *rep_data;
2500 struct mlx5_eswitch_rep *rep;
2503 esw->offloads.rep_ops[rep_type] = ops;
2504 mlx5_esw_for_all_reps(esw, i, rep) {
2505 rep_data = &rep->rep_data[rep_type];
2506 atomic_set(&rep_data->state, REP_REGISTERED);
2509 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
2511 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
2513 struct mlx5_eswitch_rep *rep;
2516 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
2517 __unload_reps_all_vport(esw, rep_type);
2519 mlx5_esw_for_all_reps(esw, i, rep)
2520 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2522 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
2524 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
2526 struct mlx5_eswitch_rep *rep;
2528 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2529 return rep->rep_data[rep_type].priv;
2532 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
2536 struct mlx5_eswitch_rep *rep;
2538 rep = mlx5_eswitch_get_rep(esw, vport);
2540 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2541 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2542 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
2545 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
2547 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2549 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
2551 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2553 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
2556 return mlx5_eswitch_get_rep(esw, vport);
2558 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
2560 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2562 return vport_num >= MLX5_VPORT_FIRST_VF &&
2563 vport_num <= esw->dev->priv.sriov.max_vfs;
2566 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2568 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2570 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2572 u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,
2575 return ((MLX5_CAP_GEN(esw->dev, vhca_id) & 0xffff) << 16) | vport_num;
2577 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);