2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/mlx5_ifc.h>
36 #include <linux/mlx5/vport.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_core.h"
43 #include "lib/devcom.h"
46 /* There are two match-all miss flows, one for unicast dst mac and
49 #define MLX5_ESW_MISS_FLOWS (2)
51 #define fdb_prio_table(esw, chain, prio, level) \
52 (esw)->fdb_table.offloads.fdb_prio[(chain)][(prio)][(level)]
54 #define UPLINK_REP_INDEX 0
56 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
59 u16 idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
61 WARN_ON(idx > esw->total_vports - 1);
62 return &esw->offloads.vport_reps[idx];
65 static struct mlx5_flow_table *
66 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
68 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
70 bool mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw)
72 return (!!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED));
75 u32 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw)
77 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
83 u16 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw)
85 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
91 struct mlx5_flow_handle *
92 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
93 struct mlx5_flow_spec *spec,
94 struct mlx5_esw_flow_attr *attr)
96 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
97 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
98 bool split = !!(attr->split_count);
99 struct mlx5_flow_handle *rule;
100 struct mlx5_flow_table *fdb;
104 if (esw->mode != SRIOV_OFFLOADS)
105 return ERR_PTR(-EOPNOTSUPP);
107 flow_act.action = attr->action;
108 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
109 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
110 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
111 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
112 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
113 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
114 flow_act.vlan[0].vid = attr->vlan_vid[0];
115 flow_act.vlan[0].prio = attr->vlan_prio[0];
116 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
117 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
118 flow_act.vlan[1].vid = attr->vlan_vid[1];
119 flow_act.vlan[1].prio = attr->vlan_prio[1];
123 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
124 if (attr->dest_chain) {
125 struct mlx5_flow_table *ft;
127 ft = esw_get_prio_table(esw, attr->dest_chain, 1, 0);
130 goto err_create_goto_table;
133 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
137 for (j = attr->split_count; j < attr->out_count; j++) {
138 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
139 dest[i].vport.num = attr->dests[j].rep->vport;
140 dest[i].vport.vhca_id =
141 MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
142 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
143 dest[i].vport.flags |=
144 MLX5_FLOW_DEST_VPORT_VHCA_ID;
145 if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
146 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
147 flow_act.reformat_id = attr->dests[j].encap_id;
148 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
149 dest[i].vport.reformat_id =
150 attr->dests[j].encap_id;
156 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
157 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
158 dest[i].counter_id = mlx5_fc_id(attr->counter);
162 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
163 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
165 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
166 MLX5_SET(fte_match_set_misc, misc,
167 source_eswitch_owner_vhca_id,
168 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
170 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
171 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
172 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
173 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
174 source_eswitch_owner_vhca_id);
176 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
177 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DECAP) {
178 if (attr->tunnel_match_level != MLX5_MATCH_NONE)
179 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
180 if (attr->match_level != MLX5_MATCH_NONE)
181 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
182 } else if (attr->match_level != MLX5_MATCH_NONE) {
183 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
186 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
187 flow_act.modify_id = attr->mod_hdr_id;
189 fdb = esw_get_prio_table(esw, attr->chain, attr->prio, !!split);
191 rule = ERR_CAST(fdb);
195 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
199 esw->offloads.num_flows++;
204 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
206 if (attr->dest_chain)
207 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
208 err_create_goto_table:
212 struct mlx5_flow_handle *
213 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
214 struct mlx5_flow_spec *spec,
215 struct mlx5_esw_flow_attr *attr)
217 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
218 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
219 struct mlx5_flow_table *fast_fdb;
220 struct mlx5_flow_table *fwd_fdb;
221 struct mlx5_flow_handle *rule;
225 fast_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 0);
226 if (IS_ERR(fast_fdb)) {
227 rule = ERR_CAST(fast_fdb);
231 fwd_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 1);
232 if (IS_ERR(fwd_fdb)) {
233 rule = ERR_CAST(fwd_fdb);
237 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
238 for (i = 0; i < attr->split_count; i++) {
239 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
240 dest[i].vport.num = attr->dests[i].rep->vport;
241 dest[i].vport.vhca_id =
242 MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
243 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
244 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
245 if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
246 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
247 dest[i].vport.reformat_id = attr->dests[i].encap_id;
250 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
251 dest[i].ft = fwd_fdb,
254 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
255 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
257 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
258 MLX5_SET(fte_match_set_misc, misc,
259 source_eswitch_owner_vhca_id,
260 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
262 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
263 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
264 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
265 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
266 source_eswitch_owner_vhca_id);
268 if (attr->match_level == MLX5_MATCH_NONE)
269 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
271 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS |
272 MLX5_MATCH_MISC_PARAMETERS;
274 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
279 esw->offloads.num_flows++;
283 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
285 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
291 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
292 struct mlx5_flow_handle *rule,
293 struct mlx5_esw_flow_attr *attr,
296 bool split = (attr->split_count > 0);
298 mlx5_del_flow_rules(rule);
299 esw->offloads.num_flows--;
302 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
303 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
305 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
306 if (attr->dest_chain)
307 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
312 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
313 struct mlx5_flow_handle *rule,
314 struct mlx5_esw_flow_attr *attr)
316 __mlx5_eswitch_del_rule(esw, rule, attr, false);
320 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
321 struct mlx5_flow_handle *rule,
322 struct mlx5_esw_flow_attr *attr)
324 __mlx5_eswitch_del_rule(esw, rule, attr, true);
327 static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
329 struct mlx5_eswitch_rep *rep;
330 int vf_vport, err = 0;
332 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
333 for (vf_vport = 1; vf_vport < esw->enabled_vports; vf_vport++) {
334 rep = &esw->offloads.vport_reps[vf_vport];
335 if (atomic_read(&rep->rep_if[REP_ETH].state) != REP_LOADED)
338 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
347 static struct mlx5_eswitch_rep *
348 esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
350 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
352 in_rep = attr->in_rep;
353 out_rep = attr->dests[0].rep;
365 static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
366 bool push, bool pop, bool fwd)
368 struct mlx5_eswitch_rep *in_rep, *out_rep;
370 if ((push || pop) && !fwd)
373 in_rep = attr->in_rep;
374 out_rep = attr->dests[0].rep;
376 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
379 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
382 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
383 if (!push && !pop && fwd)
384 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
387 /* protects against (1) setting rules with different vlans to push and
388 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
390 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
399 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
400 struct mlx5_esw_flow_attr *attr)
402 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
403 struct mlx5_eswitch_rep *vport = NULL;
407 /* nop if we're on the vlan push/pop non emulation mode */
408 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
411 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
412 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
413 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
416 err = esw_add_vlan_action_check(attr, push, pop, fwd);
420 attr->vlan_handled = false;
422 vport = esw_vlan_action_get_vport(attr, push, pop);
424 if (!push && !pop && fwd) {
425 /* tracks VF --> wire rules without vlan push action */
426 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
427 vport->vlan_refcount++;
428 attr->vlan_handled = true;
437 if (!(offloads->vlan_push_pop_refcount)) {
438 /* it's the 1st vlan rule, apply global vlan pop policy */
439 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
443 offloads->vlan_push_pop_refcount++;
446 if (vport->vlan_refcount)
449 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
450 SET_VLAN_INSERT | SET_VLAN_STRIP);
453 vport->vlan = attr->vlan_vid[0];
455 vport->vlan_refcount++;
459 attr->vlan_handled = true;
463 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
464 struct mlx5_esw_flow_attr *attr)
466 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
467 struct mlx5_eswitch_rep *vport = NULL;
471 /* nop if we're on the vlan push/pop non emulation mode */
472 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
475 if (!attr->vlan_handled)
478 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
479 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
480 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
482 vport = esw_vlan_action_get_vport(attr, push, pop);
484 if (!push && !pop && fwd) {
485 /* tracks VF --> wire rules without vlan push action */
486 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
487 vport->vlan_refcount--;
493 vport->vlan_refcount--;
494 if (vport->vlan_refcount)
495 goto skip_unset_push;
498 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
499 0, 0, SET_VLAN_STRIP);
505 offloads->vlan_push_pop_refcount--;
506 if (offloads->vlan_push_pop_refcount)
509 /* no more vlan rules, stop global vlan pop policy */
510 err = esw_set_global_vlan_pop(esw, 0);
516 struct mlx5_flow_handle *
517 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport, u32 sqn)
519 struct mlx5_flow_act flow_act = {0};
520 struct mlx5_flow_destination dest = {};
521 struct mlx5_flow_handle *flow_rule;
522 struct mlx5_flow_spec *spec;
525 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
527 flow_rule = ERR_PTR(-ENOMEM);
531 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
532 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
533 /* source vport is the esw manager */
534 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
536 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
537 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
538 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
540 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
541 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
542 dest.vport.num = vport;
543 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
545 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
546 &flow_act, &dest, 1);
547 if (IS_ERR(flow_rule))
548 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
553 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
555 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
557 mlx5_del_flow_rules(rule);
560 static void peer_miss_rules_setup(struct mlx5_core_dev *peer_dev,
561 struct mlx5_flow_spec *spec,
562 struct mlx5_flow_destination *dest)
564 void *misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
567 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
568 MLX5_CAP_GEN(peer_dev, vhca_id));
570 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
572 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
574 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
575 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
576 source_eswitch_owner_vhca_id);
578 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
579 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
580 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
581 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
584 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
585 struct mlx5_core_dev *peer_dev)
587 struct mlx5_flow_destination dest = {};
588 struct mlx5_flow_act flow_act = {0};
589 struct mlx5_flow_handle **flows;
590 struct mlx5_flow_handle *flow;
591 struct mlx5_flow_spec *spec;
592 /* total vports is the same for both e-switches */
593 int nvports = esw->total_vports;
597 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
601 peer_miss_rules_setup(peer_dev, spec, &dest);
603 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
606 goto alloc_flows_err;
609 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
610 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
613 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
614 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_PF);
615 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
616 spec, &flow_act, &dest, 1);
619 goto add_pf_flow_err;
621 flows[MLX5_VPORT_PF] = flow;
624 if (mlx5_ecpf_vport_exists(esw->dev)) {
625 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
626 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
627 spec, &flow_act, &dest, 1);
630 goto add_ecpf_flow_err;
632 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
635 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
636 MLX5_SET(fte_match_set_misc, misc, source_port, i);
637 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
638 spec, &flow_act, &dest, 1);
641 goto add_vf_flow_err;
646 esw->fdb_table.offloads.peer_miss_rules = flows;
653 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
654 mlx5_del_flow_rules(flows[i]);
656 if (mlx5_ecpf_vport_exists(esw->dev))
657 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
659 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
660 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
662 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
669 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
671 struct mlx5_flow_handle **flows;
674 flows = esw->fdb_table.offloads.peer_miss_rules;
676 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
677 mlx5_core_max_vfs(esw->dev))
678 mlx5_del_flow_rules(flows[i]);
680 if (mlx5_ecpf_vport_exists(esw->dev))
681 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
683 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
684 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
689 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
691 struct mlx5_flow_act flow_act = {0};
692 struct mlx5_flow_destination dest = {};
693 struct mlx5_flow_handle *flow_rule = NULL;
694 struct mlx5_flow_spec *spec;
701 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
707 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
708 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
710 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
711 outer_headers.dmac_47_16);
714 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
715 dest.vport.num = esw->manager_vport;
716 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
718 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
719 &flow_act, &dest, 1);
720 if (IS_ERR(flow_rule)) {
721 err = PTR_ERR(flow_rule);
722 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
726 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
728 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
730 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
731 outer_headers.dmac_47_16);
733 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
734 &flow_act, &dest, 1);
735 if (IS_ERR(flow_rule)) {
736 err = PTR_ERR(flow_rule);
737 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
738 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
742 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
749 #define ESW_OFFLOADS_NUM_GROUPS 4
751 /* Firmware currently has 4 pool of 4 sizes that it supports (ESW_POOLS),
752 * and a virtual memory region of 16M (ESW_SIZE), this region is duplicated
753 * for each flow table pool. We can allocate up to 16M of each pool,
754 * and we keep track of how much we used via put/get_sz_to_pool.
755 * Firmware doesn't report any of this for now.
756 * ESW_POOL is expected to be sorted from large to small
758 #define ESW_SIZE (16 * 1024 * 1024)
759 const unsigned int ESW_POOLS[4] = { 4 * 1024 * 1024, 1 * 1024 * 1024,
760 64 * 1024, 4 * 1024 };
763 get_sz_from_pool(struct mlx5_eswitch *esw)
767 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
768 if (esw->fdb_table.offloads.fdb_left[i]) {
769 --esw->fdb_table.offloads.fdb_left[i];
779 put_sz_to_pool(struct mlx5_eswitch *esw, int sz)
783 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
784 if (sz >= ESW_POOLS[i]) {
785 ++esw->fdb_table.offloads.fdb_left[i];
791 static struct mlx5_flow_table *
792 create_next_size_table(struct mlx5_eswitch *esw,
793 struct mlx5_flow_namespace *ns,
798 struct mlx5_flow_table *fdb;
801 sz = get_sz_from_pool(esw);
803 return ERR_PTR(-ENOSPC);
805 fdb = mlx5_create_auto_grouped_flow_table(ns,
808 ESW_OFFLOADS_NUM_GROUPS,
812 esw_warn(esw->dev, "Failed to create FDB Table err %d (table prio: %d, level: %d, size: %d)\n",
813 (int)PTR_ERR(fdb), table_prio, level, sz);
814 put_sz_to_pool(esw, sz);
820 static struct mlx5_flow_table *
821 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
823 struct mlx5_core_dev *dev = esw->dev;
824 struct mlx5_flow_table *fdb = NULL;
825 struct mlx5_flow_namespace *ns;
826 int table_prio, l = 0;
829 if (chain == FDB_SLOW_PATH_CHAIN)
830 return esw->fdb_table.offloads.slow_fdb;
832 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
834 fdb = fdb_prio_table(esw, chain, prio, level).fdb;
836 /* take ref on earlier levels as well */
838 fdb_prio_table(esw, chain, prio, level--).num_rules++;
839 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
843 ns = mlx5_get_fdb_sub_ns(dev, chain);
845 esw_warn(dev, "Failed to get FDB sub namespace\n");
846 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
847 return ERR_PTR(-EOPNOTSUPP);
850 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
851 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
852 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
854 table_prio = (chain * FDB_MAX_PRIO) + prio - 1;
856 /* create earlier levels for correct fs_core lookup when
859 for (l = 0; l <= level; l++) {
860 if (fdb_prio_table(esw, chain, prio, l).fdb) {
861 fdb_prio_table(esw, chain, prio, l).num_rules++;
865 fdb = create_next_size_table(esw, ns, table_prio, l, flags);
871 fdb_prio_table(esw, chain, prio, l).fdb = fdb;
872 fdb_prio_table(esw, chain, prio, l).num_rules = 1;
875 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
879 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
881 esw_put_prio_table(esw, chain, prio, l);
887 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
891 if (chain == FDB_SLOW_PATH_CHAIN)
894 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
896 for (l = level; l >= 0; l--) {
897 if (--(fdb_prio_table(esw, chain, prio, l).num_rules) > 0)
900 put_sz_to_pool(esw, fdb_prio_table(esw, chain, prio, l).fdb->max_fte);
901 mlx5_destroy_flow_table(fdb_prio_table(esw, chain, prio, l).fdb);
902 fdb_prio_table(esw, chain, prio, l).fdb = NULL;
905 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
908 static void esw_destroy_offloads_fast_fdb_tables(struct mlx5_eswitch *esw)
910 /* If lazy creation isn't supported, deref the fast path tables */
911 if (!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)) {
912 esw_put_prio_table(esw, 0, 1, 1);
913 esw_put_prio_table(esw, 0, 1, 0);
917 #define MAX_PF_SQ 256
918 #define MAX_SQ_NVPORTS 32
920 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
922 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
923 struct mlx5_flow_table_attr ft_attr = {};
924 struct mlx5_core_dev *dev = esw->dev;
925 u32 *flow_group_in, max_flow_counter;
926 struct mlx5_flow_namespace *root_ns;
927 struct mlx5_flow_table *fdb = NULL;
928 int table_size, ix, err = 0, i;
929 struct mlx5_flow_group *g;
930 u32 flags = 0, fdb_max;
931 void *match_criteria;
934 esw_debug(esw->dev, "Create offloads FDB Tables\n");
935 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
939 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
941 esw_warn(dev, "Failed to get FDB flow namespace\n");
946 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
947 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
948 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
950 esw_debug(dev, "Create offloads FDB table, min (max esw size(2^%d), max counters(%d), groups(%d), max flow table size(2^%d))\n",
951 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size),
952 max_flow_counter, ESW_OFFLOADS_NUM_GROUPS,
955 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++)
956 esw->fdb_table.offloads.fdb_left[i] =
957 ESW_POOLS[i] <= fdb_max ? ESW_SIZE / ESW_POOLS[i] : 0;
959 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ +
960 MLX5_ESW_MISS_FLOWS + esw->total_vports;
962 /* create the slow path fdb with encap set, so further table instances
963 * can be created at run time while VFs are probed if the FW allows that.
965 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
966 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
967 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
969 ft_attr.flags = flags;
970 ft_attr.max_fte = table_size;
971 ft_attr.prio = FDB_SLOW_PATH;
973 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
976 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
979 esw->fdb_table.offloads.slow_fdb = fdb;
981 /* If lazy creation isn't supported, open the fast path tables now */
982 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, multi_fdb_encap) &&
983 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
984 esw->fdb_table.flags &= ~ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
985 esw_warn(dev, "Lazy creation of flow tables isn't supported, ignoring priorities\n");
986 esw_get_prio_table(esw, 0, 1, 0);
987 esw_get_prio_table(esw, 0, 1, 1);
989 esw_debug(dev, "Lazy creation of flow tables supported, deferring table opening\n");
990 esw->fdb_table.flags |= ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
993 /* create send-to-vport group */
994 memset(flow_group_in, 0, inlen);
995 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
996 MLX5_MATCH_MISC_PARAMETERS);
998 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1000 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1001 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1003 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
1004 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1005 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1007 g = mlx5_create_flow_group(fdb, flow_group_in);
1010 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1011 goto send_vport_err;
1013 esw->fdb_table.offloads.send_to_vport_grp = g;
1015 /* create peer esw miss group */
1016 memset(flow_group_in, 0, inlen);
1017 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1018 MLX5_MATCH_MISC_PARAMETERS);
1020 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1023 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1024 misc_parameters.source_port);
1025 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1026 misc_parameters.source_eswitch_owner_vhca_id);
1028 MLX5_SET(create_flow_group_in, flow_group_in,
1029 source_eswitch_owner_vhca_id_valid, 1);
1030 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1031 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1032 ix + esw->total_vports - 1);
1033 ix += esw->total_vports;
1035 g = mlx5_create_flow_group(fdb, flow_group_in);
1038 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1041 esw->fdb_table.offloads.peer_miss_grp = g;
1043 /* create miss group */
1044 memset(flow_group_in, 0, inlen);
1045 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1046 MLX5_MATCH_OUTER_HEADERS);
1047 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1049 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1050 outer_headers.dmac_47_16);
1053 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1054 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1055 ix + MLX5_ESW_MISS_FLOWS);
1057 g = mlx5_create_flow_group(fdb, flow_group_in);
1060 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1063 esw->fdb_table.offloads.miss_grp = g;
1065 err = esw_add_fdb_miss_rule(esw);
1069 esw->nvports = nvports;
1070 kvfree(flow_group_in);
1074 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1076 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1078 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1080 esw_destroy_offloads_fast_fdb_tables(esw);
1081 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1084 kvfree(flow_group_in);
1088 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1090 if (!esw->fdb_table.offloads.slow_fdb)
1093 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1094 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1095 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1096 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1097 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1098 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1100 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1101 esw_destroy_offloads_fast_fdb_tables(esw);
1104 static int esw_create_offloads_table(struct mlx5_eswitch *esw, int nvports)
1106 struct mlx5_flow_table_attr ft_attr = {};
1107 struct mlx5_core_dev *dev = esw->dev;
1108 struct mlx5_flow_table *ft_offloads;
1109 struct mlx5_flow_namespace *ns;
1112 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1114 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1118 ft_attr.max_fte = nvports + MLX5_ESW_MISS_FLOWS;
1120 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1121 if (IS_ERR(ft_offloads)) {
1122 err = PTR_ERR(ft_offloads);
1123 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1127 esw->offloads.ft_offloads = ft_offloads;
1131 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1133 struct mlx5_esw_offload *offloads = &esw->offloads;
1135 mlx5_destroy_flow_table(offloads->ft_offloads);
1138 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw, int nvports)
1140 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1141 struct mlx5_flow_group *g;
1143 void *match_criteria, *misc;
1146 nvports = nvports + MLX5_ESW_MISS_FLOWS;
1147 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1151 /* create vport rx group */
1152 memset(flow_group_in, 0, inlen);
1153 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1154 MLX5_MATCH_MISC_PARAMETERS);
1156 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1157 misc = MLX5_ADDR_OF(fte_match_param, match_criteria, misc_parameters);
1158 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1160 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1161 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1163 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1167 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1171 esw->offloads.vport_rx_group = g;
1173 kvfree(flow_group_in);
1177 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1179 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1182 struct mlx5_flow_handle *
1183 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
1184 struct mlx5_flow_destination *dest)
1186 struct mlx5_flow_act flow_act = {0};
1187 struct mlx5_flow_handle *flow_rule;
1188 struct mlx5_flow_spec *spec;
1191 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1193 flow_rule = ERR_PTR(-ENOMEM);
1197 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1198 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1200 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1201 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1203 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1205 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1206 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1207 &flow_act, dest, 1);
1208 if (IS_ERR(flow_rule)) {
1209 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1218 static int esw_offloads_start(struct mlx5_eswitch *esw,
1219 struct netlink_ext_ack *extack)
1221 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
1223 if (esw->mode != SRIOV_LEGACY &&
1224 !mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1225 NL_SET_ERR_MSG_MOD(extack,
1226 "Can't set offloads mode, SRIOV legacy not enabled");
1230 mlx5_eswitch_disable_sriov(esw);
1231 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
1233 NL_SET_ERR_MSG_MOD(extack,
1234 "Failed setting eswitch to offloads");
1235 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
1237 NL_SET_ERR_MSG_MOD(extack,
1238 "Failed setting eswitch back to legacy");
1241 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1242 if (mlx5_eswitch_inline_mode_get(esw,
1244 &esw->offloads.inline_mode)) {
1245 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
1246 NL_SET_ERR_MSG_MOD(extack,
1247 "Inline mode is different between vports");
1253 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1255 kfree(esw->offloads.vport_reps);
1258 int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1260 int total_vports = MLX5_TOTAL_VPORTS(esw->dev);
1261 struct mlx5_core_dev *dev = esw->dev;
1262 struct mlx5_eswitch_rep *rep;
1263 u8 hw_id[ETH_ALEN], rep_type;
1266 esw->offloads.vport_reps = kcalloc(total_vports,
1267 sizeof(struct mlx5_eswitch_rep),
1269 if (!esw->offloads.vport_reps)
1272 mlx5_query_nic_vport_mac_address(dev, 0, hw_id);
1274 mlx5_esw_for_all_reps(esw, vport, rep) {
1275 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport);
1276 ether_addr_copy(rep->hw_id, hw_id);
1278 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1279 atomic_set(&rep->rep_if[rep_type].state,
1286 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1287 struct mlx5_eswitch_rep *rep, u8 rep_type)
1289 if (atomic_cmpxchg(&rep->rep_if[rep_type].state,
1290 REP_LOADED, REP_REGISTERED) == REP_LOADED)
1291 rep->rep_if[rep_type].unload(rep);
1294 static void __unload_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1296 struct mlx5_eswitch_rep *rep;
1298 if (mlx5_ecpf_vport_exists(esw->dev)) {
1299 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1300 __esw_offloads_unload_rep(esw, rep, rep_type);
1303 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1304 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1305 __esw_offloads_unload_rep(esw, rep, rep_type);
1308 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1309 __esw_offloads_unload_rep(esw, rep, rep_type);
1312 static void __unload_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1315 struct mlx5_eswitch_rep *rep;
1318 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvports)
1319 __esw_offloads_unload_rep(esw, rep, rep_type);
1322 static void esw_offloads_unload_vf_reps(struct mlx5_eswitch *esw, int nvports)
1324 u8 rep_type = NUM_REP_TYPES;
1326 while (rep_type-- > 0)
1327 __unload_reps_vf_vport(esw, nvports, rep_type);
1330 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, int nvports,
1333 __unload_reps_vf_vport(esw, nvports, rep_type);
1335 /* Special vports must be the last to unload. */
1336 __unload_reps_special_vport(esw, rep_type);
1339 static void esw_offloads_unload_all_reps(struct mlx5_eswitch *esw, int nvports)
1341 u8 rep_type = NUM_REP_TYPES;
1343 while (rep_type-- > 0)
1344 __unload_reps_all_vport(esw, nvports, rep_type);
1347 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
1348 struct mlx5_eswitch_rep *rep, u8 rep_type)
1352 if (atomic_cmpxchg(&rep->rep_if[rep_type].state,
1353 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1354 err = rep->rep_if[rep_type].load(esw->dev, rep);
1356 atomic_set(&rep->rep_if[rep_type].state,
1363 static int __load_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1365 struct mlx5_eswitch_rep *rep;
1368 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1369 err = __esw_offloads_load_rep(esw, rep, rep_type);
1373 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1374 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1375 err = __esw_offloads_load_rep(esw, rep, rep_type);
1380 if (mlx5_ecpf_vport_exists(esw->dev)) {
1381 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1382 err = __esw_offloads_load_rep(esw, rep, rep_type);
1390 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1391 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1392 __esw_offloads_unload_rep(esw, rep, rep_type);
1396 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1397 __esw_offloads_unload_rep(esw, rep, rep_type);
1401 static int __load_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1404 struct mlx5_eswitch_rep *rep;
1407 mlx5_esw_for_each_vf_rep(esw, i, rep, nvports) {
1408 err = __esw_offloads_load_rep(esw, rep, rep_type);
1416 __unload_reps_vf_vport(esw, --i, rep_type);
1420 static int esw_offloads_load_vf_reps(struct mlx5_eswitch *esw, int nvports)
1425 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1426 err = __load_reps_vf_vport(esw, nvports, rep_type);
1434 while (rep_type-- > 0)
1435 __unload_reps_vf_vport(esw, nvports, rep_type);
1439 static int __load_reps_all_vport(struct mlx5_eswitch *esw, int nvports,
1444 /* Special vports must be loaded first. */
1445 err = __load_reps_special_vport(esw, rep_type);
1449 err = __load_reps_vf_vport(esw, nvports, rep_type);
1456 __unload_reps_special_vport(esw, rep_type);
1460 static int esw_offloads_load_all_reps(struct mlx5_eswitch *esw, int nvports)
1465 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1466 err = __load_reps_all_vport(esw, nvports, rep_type);
1474 while (rep_type-- > 0)
1475 __unload_reps_all_vport(esw, nvports, rep_type);
1479 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
1480 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1482 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1483 struct mlx5_eswitch *peer_esw)
1487 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1494 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1496 mlx5e_tc_clean_fdb_peer_flows(esw);
1497 esw_del_fdb_peer_miss_rules(esw);
1500 static int mlx5_esw_offloads_devcom_event(int event,
1504 struct mlx5_eswitch *esw = my_data;
1505 struct mlx5_eswitch *peer_esw = event_data;
1506 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1510 case ESW_OFFLOADS_DEVCOM_PAIR:
1511 err = mlx5_esw_offloads_pair(esw, peer_esw);
1515 err = mlx5_esw_offloads_pair(peer_esw, esw);
1519 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1522 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1523 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1526 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1527 mlx5_esw_offloads_unpair(peer_esw);
1528 mlx5_esw_offloads_unpair(esw);
1535 mlx5_esw_offloads_unpair(esw);
1538 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1543 static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1545 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1547 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1548 mutex_init(&esw->offloads.peer_mutex);
1550 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1553 mlx5_devcom_register_component(devcom,
1554 MLX5_DEVCOM_ESW_OFFLOADS,
1555 mlx5_esw_offloads_devcom_event,
1558 mlx5_devcom_send_event(devcom,
1559 MLX5_DEVCOM_ESW_OFFLOADS,
1560 ESW_OFFLOADS_DEVCOM_PAIR, esw);
1563 static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
1565 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1567 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1570 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1571 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
1573 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1576 static int esw_vport_ingress_prio_tag_config(struct mlx5_eswitch *esw,
1577 struct mlx5_vport *vport)
1579 struct mlx5_core_dev *dev = esw->dev;
1580 struct mlx5_flow_act flow_act = {0};
1581 struct mlx5_flow_spec *spec;
1584 /* For prio tag mode, there is only 1 FTEs:
1585 * 1) Untagged packets - push prio tag VLAN, allow
1586 * Unmatched traffic is allowed by default
1589 if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support))
1592 esw_vport_cleanup_ingress_rules(esw, vport);
1594 err = esw_vport_enable_ingress_acl(esw, vport);
1596 mlx5_core_warn(esw->dev,
1597 "failed to enable prio tag ingress acl (%d) on vport[%d]\n",
1603 "vport[%d] configure ingress rules\n", vport->vport);
1605 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1611 /* Untagged packets - push prio tag VLAN, allow */
1612 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1613 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 0);
1614 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1615 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
1616 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1617 flow_act.vlan[0].ethtype = ETH_P_8021Q;
1618 flow_act.vlan[0].vid = 0;
1619 flow_act.vlan[0].prio = 0;
1620 vport->ingress.allow_rule =
1621 mlx5_add_flow_rules(vport->ingress.acl, spec,
1622 &flow_act, NULL, 0);
1623 if (IS_ERR(vport->ingress.allow_rule)) {
1624 err = PTR_ERR(vport->ingress.allow_rule);
1626 "vport[%d] configure ingress untagged allow rule, err(%d)\n",
1628 vport->ingress.allow_rule = NULL;
1636 esw_vport_cleanup_ingress_rules(esw, vport);
1640 static int esw_vport_egress_prio_tag_config(struct mlx5_eswitch *esw,
1641 struct mlx5_vport *vport)
1643 struct mlx5_flow_act flow_act = {0};
1644 struct mlx5_flow_spec *spec;
1647 /* For prio tag mode, there is only 1 FTEs:
1648 * 1) prio tag packets - pop the prio tag VLAN, allow
1649 * Unmatched traffic is allowed by default
1652 esw_vport_cleanup_egress_rules(esw, vport);
1654 err = esw_vport_enable_egress_acl(esw, vport);
1656 mlx5_core_warn(esw->dev,
1657 "failed to enable egress acl (%d) on vport[%d]\n",
1663 "vport[%d] configure prio tag egress rules\n", vport->vport);
1665 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1671 /* prio tag vlan rule - pop it so VF receives untagged packets */
1672 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1673 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag);
1674 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1675 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, 0);
1677 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1678 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
1679 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1680 vport->egress.allowed_vlan =
1681 mlx5_add_flow_rules(vport->egress.acl, spec,
1682 &flow_act, NULL, 0);
1683 if (IS_ERR(vport->egress.allowed_vlan)) {
1684 err = PTR_ERR(vport->egress.allowed_vlan);
1686 "vport[%d] configure egress pop prio tag vlan rule failed, err(%d)\n",
1688 vport->egress.allowed_vlan = NULL;
1696 esw_vport_cleanup_egress_rules(esw, vport);
1700 static int esw_prio_tag_acls_config(struct mlx5_eswitch *esw, int nvports)
1702 struct mlx5_vport *vport = NULL;
1706 mlx5_esw_for_each_vf_vport(esw, i, vport, nvports) {
1707 err = esw_vport_ingress_prio_tag_config(esw, vport);
1710 err = esw_vport_egress_prio_tag_config(esw, vport);
1718 esw_vport_disable_ingress_acl(esw, vport);
1720 mlx5_esw_for_each_vf_vport_reverse(esw, j, vport, i - 1) {
1721 esw_vport_disable_egress_acl(esw, vport);
1722 esw_vport_disable_ingress_acl(esw, vport);
1728 static void esw_prio_tag_acls_cleanup(struct mlx5_eswitch *esw)
1730 struct mlx5_vport *vport;
1733 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->nvports) {
1734 esw_vport_disable_egress_acl(esw, vport);
1735 esw_vport_disable_ingress_acl(esw, vport);
1739 static int esw_offloads_steering_init(struct mlx5_eswitch *esw, int nvports)
1743 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
1744 mutex_init(&esw->fdb_table.offloads.fdb_prio_lock);
1746 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) {
1747 err = esw_prio_tag_acls_config(esw, nvports);
1752 err = esw_create_offloads_fdb_tables(esw, nvports);
1756 err = esw_create_offloads_table(esw, nvports);
1760 err = esw_create_vport_rx_group(esw, nvports);
1767 esw_destroy_offloads_table(esw);
1770 esw_destroy_offloads_fdb_tables(esw);
1775 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
1777 esw_destroy_vport_rx_group(esw);
1778 esw_destroy_offloads_table(esw);
1779 esw_destroy_offloads_fdb_tables(esw);
1780 if (MLX5_CAP_GEN(esw->dev, prio_tag_required))
1781 esw_prio_tag_acls_cleanup(esw);
1784 static void esw_functions_changed_event_handler(struct work_struct *work)
1786 struct mlx5_host_work *host_work;
1787 struct mlx5_eswitch *esw;
1791 host_work = container_of(work, struct mlx5_host_work, work);
1792 esw = host_work->esw;
1794 err = mlx5_esw_query_functions(esw->dev, &num_vfs);
1795 if (err || num_vfs == esw->esw_funcs.num_vfs)
1798 /* Number of VFs can only change from "0 to x" or "x to 0". */
1799 if (esw->esw_funcs.num_vfs > 0) {
1800 esw_offloads_unload_vf_reps(esw, esw->esw_funcs.num_vfs);
1802 err = esw_offloads_load_vf_reps(esw, num_vfs);
1808 esw->esw_funcs.num_vfs = num_vfs;
1814 static int esw_functions_changed_event(struct notifier_block *nb,
1815 unsigned long type, void *data)
1817 struct mlx5_esw_functions *esw_funcs;
1818 struct mlx5_host_work *host_work;
1819 struct mlx5_eswitch *esw;
1821 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
1825 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
1826 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
1828 host_work->esw = esw;
1830 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
1831 queue_work(esw->work_queue, &host_work->work);
1836 static void esw_functions_changed_event_init(struct mlx5_eswitch *esw,
1839 if (!mlx5_eswitch_is_funcs_handler(esw->dev))
1842 MLX5_NB_INIT(&esw->esw_funcs.nb, esw_functions_changed_event,
1843 ESW_FUNCTIONS_CHANGED);
1844 mlx5_eq_notifier_register(esw->dev, &esw->esw_funcs.nb);
1845 esw->esw_funcs.num_vfs = vf_nvports;
1848 static void esw_functions_changed_event_cleanup(struct mlx5_eswitch *esw)
1850 if (!mlx5_eswitch_is_funcs_handler(esw->dev))
1853 mlx5_eq_notifier_unregister(esw->dev, &esw->esw_funcs.nb);
1854 flush_workqueue(esw->work_queue);
1857 int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
1862 err = esw_offloads_steering_init(esw, total_nvports);
1866 err = esw_offloads_load_all_reps(esw, vf_nvports);
1870 esw_offloads_devcom_init(esw);
1872 esw_functions_changed_event_init(esw, vf_nvports);
1874 mlx5_rdma_enable_roce(esw->dev);
1879 esw_offloads_steering_cleanup(esw);
1883 static int esw_offloads_stop(struct mlx5_eswitch *esw,
1884 struct netlink_ext_ack *extack)
1886 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
1888 mlx5_eswitch_disable_sriov(esw);
1889 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
1891 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
1892 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
1894 NL_SET_ERR_MSG_MOD(extack,
1895 "Failed setting eswitch back to offloads");
1902 void esw_offloads_cleanup(struct mlx5_eswitch *esw)
1906 esw_functions_changed_event_cleanup(esw);
1908 if (mlx5_eswitch_is_funcs_handler(esw->dev))
1909 num_vfs = esw->esw_funcs.num_vfs;
1911 num_vfs = esw->dev->priv.sriov.num_vfs;
1913 mlx5_rdma_disable_roce(esw->dev);
1914 esw_offloads_devcom_cleanup(esw);
1915 esw_offloads_unload_all_reps(esw, num_vfs);
1916 esw_offloads_steering_cleanup(esw);
1919 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
1922 case DEVLINK_ESWITCH_MODE_LEGACY:
1923 *mlx5_mode = SRIOV_LEGACY;
1925 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
1926 *mlx5_mode = SRIOV_OFFLOADS;
1935 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
1937 switch (mlx5_mode) {
1939 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
1941 case SRIOV_OFFLOADS:
1942 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
1951 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
1954 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
1955 *mlx5_mode = MLX5_INLINE_MODE_NONE;
1957 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
1958 *mlx5_mode = MLX5_INLINE_MODE_L2;
1960 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
1961 *mlx5_mode = MLX5_INLINE_MODE_IP;
1963 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
1964 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
1973 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
1975 switch (mlx5_mode) {
1976 case MLX5_INLINE_MODE_NONE:
1977 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
1979 case MLX5_INLINE_MODE_L2:
1980 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
1982 case MLX5_INLINE_MODE_IP:
1983 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
1985 case MLX5_INLINE_MODE_TCP_UDP:
1986 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
1995 static int mlx5_devlink_eswitch_check(struct devlink *devlink)
1997 struct mlx5_core_dev *dev = devlink_priv(devlink);
1999 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2002 if(!MLX5_ESWITCH_MANAGER(dev))
2005 if (dev->priv.eswitch->mode == SRIOV_NONE &&
2006 !mlx5_core_is_ecpf_esw_manager(dev))
2012 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2013 struct netlink_ext_ack *extack)
2015 struct mlx5_core_dev *dev = devlink_priv(devlink);
2016 u16 cur_mlx5_mode, mlx5_mode = 0;
2019 err = mlx5_devlink_eswitch_check(devlink);
2023 cur_mlx5_mode = dev->priv.eswitch->mode;
2025 if (esw_mode_from_devlink(mode, &mlx5_mode))
2028 if (cur_mlx5_mode == mlx5_mode)
2031 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
2032 return esw_offloads_start(dev->priv.eswitch, extack);
2033 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
2034 return esw_offloads_stop(dev->priv.eswitch, extack);
2039 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2041 struct mlx5_core_dev *dev = devlink_priv(devlink);
2044 err = mlx5_devlink_eswitch_check(devlink);
2048 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
2051 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2052 struct netlink_ext_ack *extack)
2054 struct mlx5_core_dev *dev = devlink_priv(devlink);
2055 struct mlx5_eswitch *esw = dev->priv.eswitch;
2059 err = mlx5_devlink_eswitch_check(devlink);
2063 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2064 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2065 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
2068 case MLX5_CAP_INLINE_MODE_L2:
2069 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
2071 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2075 if (esw->offloads.num_flows > 0) {
2076 NL_SET_ERR_MSG_MOD(extack,
2077 "Can't set inline mode when flows are configured");
2081 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2085 for (vport = 1; vport < esw->enabled_vports; vport++) {
2086 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2088 NL_SET_ERR_MSG_MOD(extack,
2089 "Failed to set min inline on vport");
2090 goto revert_inline_mode;
2094 esw->offloads.inline_mode = mlx5_mode;
2099 mlx5_modify_nic_vport_min_inline(dev,
2101 esw->offloads.inline_mode);
2106 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2108 struct mlx5_core_dev *dev = devlink_priv(devlink);
2109 struct mlx5_eswitch *esw = dev->priv.eswitch;
2112 err = mlx5_devlink_eswitch_check(devlink);
2116 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2119 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode)
2121 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2122 struct mlx5_core_dev *dev = esw->dev;
2125 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2128 if (esw->mode == SRIOV_NONE)
2131 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2132 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2133 mlx5_mode = MLX5_INLINE_MODE_NONE;
2135 case MLX5_CAP_INLINE_MODE_L2:
2136 mlx5_mode = MLX5_INLINE_MODE_L2;
2138 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2143 for (vport = 1; vport <= nvfs; vport++) {
2144 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
2145 if (vport > 1 && prev_mlx5_mode != mlx5_mode)
2147 prev_mlx5_mode = mlx5_mode;
2155 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
2156 struct netlink_ext_ack *extack)
2158 struct mlx5_core_dev *dev = devlink_priv(devlink);
2159 struct mlx5_eswitch *esw = dev->priv.eswitch;
2162 err = mlx5_devlink_eswitch_check(devlink);
2166 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
2167 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
2168 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)))
2171 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC)
2174 if (esw->mode == SRIOV_LEGACY) {
2175 esw->offloads.encap = encap;
2179 if (esw->offloads.encap == encap)
2182 if (esw->offloads.num_flows > 0) {
2183 NL_SET_ERR_MSG_MOD(extack,
2184 "Can't set encapsulation when flows are configured");
2188 esw_destroy_offloads_fdb_tables(esw);
2190 esw->offloads.encap = encap;
2192 err = esw_create_offloads_fdb_tables(esw, esw->nvports);
2195 NL_SET_ERR_MSG_MOD(extack,
2196 "Failed re-creating fast FDB table");
2197 esw->offloads.encap = !encap;
2198 (void)esw_create_offloads_fdb_tables(esw, esw->nvports);
2204 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap)
2206 struct mlx5_core_dev *dev = devlink_priv(devlink);
2207 struct mlx5_eswitch *esw = dev->priv.eswitch;
2210 err = mlx5_devlink_eswitch_check(devlink);
2214 *encap = esw->offloads.encap;
2218 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
2219 struct mlx5_eswitch_rep_if *__rep_if,
2222 struct mlx5_eswitch_rep_if *rep_if;
2223 struct mlx5_eswitch_rep *rep;
2226 mlx5_esw_for_all_reps(esw, i, rep) {
2227 rep_if = &rep->rep_if[rep_type];
2228 rep_if->load = __rep_if->load;
2229 rep_if->unload = __rep_if->unload;
2230 rep_if->get_proto_dev = __rep_if->get_proto_dev;
2231 rep_if->priv = __rep_if->priv;
2233 atomic_set(&rep_if->state, REP_REGISTERED);
2236 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
2238 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
2240 u16 max_vf = mlx5_core_max_vfs(esw->dev);
2241 struct mlx5_eswitch_rep *rep;
2244 if (esw->mode == SRIOV_OFFLOADS)
2245 __unload_reps_all_vport(esw, max_vf, rep_type);
2247 mlx5_esw_for_all_reps(esw, i, rep)
2248 atomic_set(&rep->rep_if[rep_type].state, REP_UNREGISTERED);
2250 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
2252 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
2254 struct mlx5_eswitch_rep *rep;
2256 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2257 return rep->rep_if[rep_type].priv;
2260 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
2264 struct mlx5_eswitch_rep *rep;
2266 rep = mlx5_eswitch_get_rep(esw, vport);
2268 if (atomic_read(&rep->rep_if[rep_type].state) == REP_LOADED &&
2269 rep->rep_if[rep_type].get_proto_dev)
2270 return rep->rep_if[rep_type].get_proto_dev(rep);
2273 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
2275 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2277 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
2279 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2281 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
2284 return mlx5_eswitch_get_rep(esw, vport);
2286 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);