2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/etherdevice.h>
34 #include <linux/mlx5/driver.h>
35 #include <linux/mlx5/mlx5_ifc.h>
36 #include <linux/mlx5/vport.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_core.h"
43 #include "lib/devcom.h"
46 /* There are two match-all miss flows, one for unicast dst mac and
49 #define MLX5_ESW_MISS_FLOWS (2)
51 #define fdb_prio_table(esw, chain, prio, level) \
52 (esw)->fdb_table.offloads.fdb_prio[(chain)][(prio)][(level)]
54 #define UPLINK_REP_INDEX 0
56 static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
59 int idx = mlx5_eswitch_vport_num_to_index(esw, vport_num);
61 WARN_ON(idx > esw->total_vports - 1);
62 return &esw->offloads.vport_reps[idx];
65 static struct mlx5_flow_table *
66 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
68 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level);
70 bool mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw)
72 return (!!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED));
75 u32 mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw)
77 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
83 u16 mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw)
85 if (esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)
92 mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
93 struct mlx5_flow_spec *spec,
94 struct mlx5_esw_flow_attr *attr)
99 /* Use metadata matching because vport is not represented by single
100 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
102 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
103 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
104 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
105 mlx5_eswitch_get_vport_metadata_for_match(attr->in_mdev->priv.eswitch,
106 attr->in_rep->vport));
108 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
109 MLX5_SET_TO_ONES(fte_match_set_misc2, misc2, metadata_reg_c_0);
111 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
112 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
113 if (memchr_inv(misc, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc)))
114 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
116 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
117 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
119 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
120 MLX5_SET(fte_match_set_misc, misc,
121 source_eswitch_owner_vhca_id,
122 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
124 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
125 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
126 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
127 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
128 source_eswitch_owner_vhca_id);
130 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
133 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
134 attr->in_rep->vport == MLX5_VPORT_UPLINK)
135 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK;
138 struct mlx5_flow_handle *
139 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
140 struct mlx5_flow_spec *spec,
141 struct mlx5_esw_flow_attr *attr)
143 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
144 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
145 bool split = !!(attr->split_count);
146 struct mlx5_flow_handle *rule;
147 struct mlx5_flow_table *fdb;
150 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
151 return ERR_PTR(-EOPNOTSUPP);
153 flow_act.action = attr->action;
154 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
155 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
156 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
157 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
158 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
159 flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto[0]);
160 flow_act.vlan[0].vid = attr->vlan_vid[0];
161 flow_act.vlan[0].prio = attr->vlan_prio[0];
162 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
163 flow_act.vlan[1].ethtype = ntohs(attr->vlan_proto[1]);
164 flow_act.vlan[1].vid = attr->vlan_vid[1];
165 flow_act.vlan[1].prio = attr->vlan_prio[1];
169 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
170 if (attr->dest_chain) {
171 struct mlx5_flow_table *ft;
173 ft = esw_get_prio_table(esw, attr->dest_chain, 1, 0);
176 goto err_create_goto_table;
179 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
183 for (j = attr->split_count; j < attr->out_count; j++) {
184 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
185 dest[i].vport.num = attr->dests[j].rep->vport;
186 dest[i].vport.vhca_id =
187 MLX5_CAP_GEN(attr->dests[j].mdev, vhca_id);
188 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
189 dest[i].vport.flags |=
190 MLX5_FLOW_DEST_VPORT_VHCA_ID;
191 if (attr->dests[j].flags & MLX5_ESW_DEST_ENCAP) {
192 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
193 flow_act.reformat_id = attr->dests[j].encap_id;
194 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
195 dest[i].vport.reformat_id =
196 attr->dests[j].encap_id;
202 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
203 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
204 dest[i].counter_id = mlx5_fc_id(attr->counter);
208 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
210 if (attr->outer_match_level != MLX5_MATCH_NONE)
211 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
212 if (attr->inner_match_level != MLX5_MATCH_NONE)
213 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
215 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
216 flow_act.modify_id = attr->mod_hdr_id;
218 fdb = esw_get_prio_table(esw, attr->chain, attr->prio, !!split);
220 rule = ERR_CAST(fdb);
224 if (mlx5_eswitch_termtbl_required(esw, &flow_act, spec))
225 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, attr,
228 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
232 atomic64_inc(&esw->offloads.num_flows);
237 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
239 if (attr->dest_chain)
240 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
241 err_create_goto_table:
245 struct mlx5_flow_handle *
246 mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
247 struct mlx5_flow_spec *spec,
248 struct mlx5_esw_flow_attr *attr)
250 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
251 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
252 struct mlx5_flow_table *fast_fdb;
253 struct mlx5_flow_table *fwd_fdb;
254 struct mlx5_flow_handle *rule;
257 fast_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 0);
258 if (IS_ERR(fast_fdb)) {
259 rule = ERR_CAST(fast_fdb);
263 fwd_fdb = esw_get_prio_table(esw, attr->chain, attr->prio, 1);
264 if (IS_ERR(fwd_fdb)) {
265 rule = ERR_CAST(fwd_fdb);
269 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
270 for (i = 0; i < attr->split_count; i++) {
271 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
272 dest[i].vport.num = attr->dests[i].rep->vport;
273 dest[i].vport.vhca_id =
274 MLX5_CAP_GEN(attr->dests[i].mdev, vhca_id);
275 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
276 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
277 if (attr->dests[i].flags & MLX5_ESW_DEST_ENCAP) {
278 dest[i].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
279 dest[i].vport.reformat_id = attr->dests[i].encap_id;
282 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
283 dest[i].ft = fwd_fdb,
286 mlx5_eswitch_set_rule_source_port(esw, spec, attr);
288 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
289 if (attr->outer_match_level != MLX5_MATCH_NONE)
290 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
292 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
297 atomic64_inc(&esw->offloads.num_flows);
301 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
303 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
309 __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
310 struct mlx5_flow_handle *rule,
311 struct mlx5_esw_flow_attr *attr,
314 bool split = (attr->split_count > 0);
317 mlx5_del_flow_rules(rule);
319 /* unref the term table */
320 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
321 if (attr->dests[i].termtbl)
322 mlx5_eswitch_termtbl_put(esw, attr->dests[i].termtbl);
325 atomic64_dec(&esw->offloads.num_flows);
328 esw_put_prio_table(esw, attr->chain, attr->prio, 1);
329 esw_put_prio_table(esw, attr->chain, attr->prio, 0);
331 esw_put_prio_table(esw, attr->chain, attr->prio, !!split);
332 if (attr->dest_chain)
333 esw_put_prio_table(esw, attr->dest_chain, 1, 0);
338 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
339 struct mlx5_flow_handle *rule,
340 struct mlx5_esw_flow_attr *attr)
342 __mlx5_eswitch_del_rule(esw, rule, attr, false);
346 mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
347 struct mlx5_flow_handle *rule,
348 struct mlx5_esw_flow_attr *attr)
350 __mlx5_eswitch_del_rule(esw, rule, attr, true);
353 static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
355 struct mlx5_eswitch_rep *rep;
358 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
359 mlx5_esw_for_each_host_func_rep(esw, i, rep, esw->esw_funcs.num_vfs) {
360 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
363 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
372 static struct mlx5_eswitch_rep *
373 esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
375 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
377 in_rep = attr->in_rep;
378 out_rep = attr->dests[0].rep;
390 static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
391 bool push, bool pop, bool fwd)
393 struct mlx5_eswitch_rep *in_rep, *out_rep;
395 if ((push || pop) && !fwd)
398 in_rep = attr->in_rep;
399 out_rep = attr->dests[0].rep;
401 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
404 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
407 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
408 if (!push && !pop && fwd)
409 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
412 /* protects against (1) setting rules with different vlans to push and
413 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
415 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
424 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
425 struct mlx5_esw_flow_attr *attr)
427 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
428 struct mlx5_eswitch_rep *vport = NULL;
432 /* nop if we're on the vlan push/pop non emulation mode */
433 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
436 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
437 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
438 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
441 mutex_lock(&esw->state_lock);
443 err = esw_add_vlan_action_check(attr, push, pop, fwd);
447 attr->vlan_handled = false;
449 vport = esw_vlan_action_get_vport(attr, push, pop);
451 if (!push && !pop && fwd) {
452 /* tracks VF --> wire rules without vlan push action */
453 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
454 vport->vlan_refcount++;
455 attr->vlan_handled = true;
464 if (!(offloads->vlan_push_pop_refcount)) {
465 /* it's the 1st vlan rule, apply global vlan pop policy */
466 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
470 offloads->vlan_push_pop_refcount++;
473 if (vport->vlan_refcount)
476 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid[0], 0,
477 SET_VLAN_INSERT | SET_VLAN_STRIP);
480 vport->vlan = attr->vlan_vid[0];
482 vport->vlan_refcount++;
486 attr->vlan_handled = true;
488 mutex_unlock(&esw->state_lock);
492 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
493 struct mlx5_esw_flow_attr *attr)
495 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
496 struct mlx5_eswitch_rep *vport = NULL;
500 /* nop if we're on the vlan push/pop non emulation mode */
501 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
504 if (!attr->vlan_handled)
507 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
508 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
509 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
511 mutex_lock(&esw->state_lock);
513 vport = esw_vlan_action_get_vport(attr, push, pop);
515 if (!push && !pop && fwd) {
516 /* tracks VF --> wire rules without vlan push action */
517 if (attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
518 vport->vlan_refcount--;
524 vport->vlan_refcount--;
525 if (vport->vlan_refcount)
526 goto skip_unset_push;
529 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
530 0, 0, SET_VLAN_STRIP);
536 offloads->vlan_push_pop_refcount--;
537 if (offloads->vlan_push_pop_refcount)
540 /* no more vlan rules, stop global vlan pop policy */
541 err = esw_set_global_vlan_pop(esw, 0);
544 mutex_unlock(&esw->state_lock);
548 struct mlx5_flow_handle *
549 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, u16 vport,
552 struct mlx5_flow_act flow_act = {0};
553 struct mlx5_flow_destination dest = {};
554 struct mlx5_flow_handle *flow_rule;
555 struct mlx5_flow_spec *spec;
558 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
560 flow_rule = ERR_PTR(-ENOMEM);
564 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
565 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
566 /* source vport is the esw manager */
567 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport);
569 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
570 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
571 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
573 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
574 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
575 dest.vport.num = vport;
576 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
578 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
579 &flow_act, &dest, 1);
580 if (IS_ERR(flow_rule))
581 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
586 EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
588 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
590 mlx5_del_flow_rules(rule);
593 static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
595 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
596 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
597 u8 fdb_to_vport_reg_c_id;
600 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
603 err = mlx5_eswitch_query_esw_vport_context(esw, esw->manager_vport,
608 fdb_to_vport_reg_c_id = MLX5_GET(query_esw_vport_context_out, out,
609 esw_vport_context.fdb_to_vport_reg_c_id);
612 fdb_to_vport_reg_c_id |= MLX5_FDB_TO_VPORT_REG_C_0;
614 fdb_to_vport_reg_c_id &= ~MLX5_FDB_TO_VPORT_REG_C_0;
616 MLX5_SET(modify_esw_vport_context_in, in,
617 esw_vport_context.fdb_to_vport_reg_c_id, fdb_to_vport_reg_c_id);
619 MLX5_SET(modify_esw_vport_context_in, in,
620 field_select.fdb_to_vport_reg_c_id, 1);
622 return mlx5_eswitch_modify_esw_vport_context(esw, esw->manager_vport,
626 static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
627 struct mlx5_core_dev *peer_dev,
628 struct mlx5_flow_spec *spec,
629 struct mlx5_flow_destination *dest)
633 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
634 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
636 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
638 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
640 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
643 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
644 MLX5_CAP_GEN(peer_dev, vhca_id));
646 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
648 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
650 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
651 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
652 source_eswitch_owner_vhca_id);
655 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
656 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
657 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
658 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
661 static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
662 struct mlx5_eswitch *peer_esw,
663 struct mlx5_flow_spec *spec,
668 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
669 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
671 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
672 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
675 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
677 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
681 static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
682 struct mlx5_core_dev *peer_dev)
684 struct mlx5_flow_destination dest = {};
685 struct mlx5_flow_act flow_act = {0};
686 struct mlx5_flow_handle **flows;
687 struct mlx5_flow_handle *flow;
688 struct mlx5_flow_spec *spec;
689 /* total vports is the same for both e-switches */
690 int nvports = esw->total_vports;
694 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
698 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
700 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
703 goto alloc_flows_err;
706 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
707 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
710 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
711 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
712 spec, MLX5_VPORT_PF);
714 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
715 spec, &flow_act, &dest, 1);
718 goto add_pf_flow_err;
720 flows[MLX5_VPORT_PF] = flow;
723 if (mlx5_ecpf_vport_exists(esw->dev)) {
724 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
725 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
726 spec, &flow_act, &dest, 1);
729 goto add_ecpf_flow_err;
731 flows[mlx5_eswitch_ecpf_idx(esw)] = flow;
734 mlx5_esw_for_each_vf_vport_num(esw, i, mlx5_core_max_vfs(esw->dev)) {
735 esw_set_peer_miss_rule_source_port(esw,
736 peer_dev->priv.eswitch,
739 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
740 spec, &flow_act, &dest, 1);
743 goto add_vf_flow_err;
748 esw->fdb_table.offloads.peer_miss_rules = flows;
755 mlx5_esw_for_each_vf_vport_num_reverse(esw, i, nvports)
756 mlx5_del_flow_rules(flows[i]);
758 if (mlx5_ecpf_vport_exists(esw->dev))
759 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
761 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
762 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
764 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
771 static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
773 struct mlx5_flow_handle **flows;
776 flows = esw->fdb_table.offloads.peer_miss_rules;
778 mlx5_esw_for_each_vf_vport_num_reverse(esw, i,
779 mlx5_core_max_vfs(esw->dev))
780 mlx5_del_flow_rules(flows[i]);
782 if (mlx5_ecpf_vport_exists(esw->dev))
783 mlx5_del_flow_rules(flows[mlx5_eswitch_ecpf_idx(esw)]);
785 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
786 mlx5_del_flow_rules(flows[MLX5_VPORT_PF]);
791 static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
793 struct mlx5_flow_act flow_act = {0};
794 struct mlx5_flow_destination dest = {};
795 struct mlx5_flow_handle *flow_rule = NULL;
796 struct mlx5_flow_spec *spec;
803 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
809 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
810 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
812 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
813 outer_headers.dmac_47_16);
816 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
817 dest.vport.num = esw->manager_vport;
818 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
820 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
821 &flow_act, &dest, 1);
822 if (IS_ERR(flow_rule)) {
823 err = PTR_ERR(flow_rule);
824 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
828 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
830 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
832 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
833 outer_headers.dmac_47_16);
835 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, spec,
836 &flow_act, &dest, 1);
837 if (IS_ERR(flow_rule)) {
838 err = PTR_ERR(flow_rule);
839 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
840 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
844 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
851 #define ESW_OFFLOADS_NUM_GROUPS 4
853 /* Firmware currently has 4 pool of 4 sizes that it supports (ESW_POOLS),
854 * and a virtual memory region of 16M (ESW_SIZE), this region is duplicated
855 * for each flow table pool. We can allocate up to 16M of each pool,
856 * and we keep track of how much we used via put/get_sz_to_pool.
857 * Firmware doesn't report any of this for now.
858 * ESW_POOL is expected to be sorted from large to small
860 #define ESW_SIZE (16 * 1024 * 1024)
861 const unsigned int ESW_POOLS[4] = { 4 * 1024 * 1024, 1 * 1024 * 1024,
862 64 * 1024, 4 * 1024 };
865 get_sz_from_pool(struct mlx5_eswitch *esw)
869 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
870 if (esw->fdb_table.offloads.fdb_left[i]) {
871 --esw->fdb_table.offloads.fdb_left[i];
881 put_sz_to_pool(struct mlx5_eswitch *esw, int sz)
885 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++) {
886 if (sz >= ESW_POOLS[i]) {
887 ++esw->fdb_table.offloads.fdb_left[i];
893 static struct mlx5_flow_table *
894 create_next_size_table(struct mlx5_eswitch *esw,
895 struct mlx5_flow_namespace *ns,
900 struct mlx5_flow_table *fdb;
903 sz = get_sz_from_pool(esw);
905 return ERR_PTR(-ENOSPC);
907 fdb = mlx5_create_auto_grouped_flow_table(ns,
910 ESW_OFFLOADS_NUM_GROUPS,
914 esw_warn(esw->dev, "Failed to create FDB Table err %d (table prio: %d, level: %d, size: %d)\n",
915 (int)PTR_ERR(fdb), table_prio, level, sz);
916 put_sz_to_pool(esw, sz);
922 static struct mlx5_flow_table *
923 esw_get_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
925 struct mlx5_core_dev *dev = esw->dev;
926 struct mlx5_flow_table *fdb = NULL;
927 struct mlx5_flow_namespace *ns;
928 int table_prio, l = 0;
931 if (chain == FDB_SLOW_PATH_CHAIN)
932 return esw->fdb_table.offloads.slow_fdb;
934 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
936 fdb = fdb_prio_table(esw, chain, prio, level).fdb;
938 /* take ref on earlier levels as well */
940 fdb_prio_table(esw, chain, prio, level--).num_rules++;
941 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
945 ns = mlx5_get_fdb_sub_ns(dev, chain);
947 esw_warn(dev, "Failed to get FDB sub namespace\n");
948 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
949 return ERR_PTR(-EOPNOTSUPP);
952 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
953 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
954 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
956 table_prio = (chain * FDB_MAX_PRIO) + prio - 1;
958 /* create earlier levels for correct fs_core lookup when
961 for (l = 0; l <= level; l++) {
962 if (fdb_prio_table(esw, chain, prio, l).fdb) {
963 fdb_prio_table(esw, chain, prio, l).num_rules++;
967 fdb = create_next_size_table(esw, ns, table_prio, l, flags);
973 fdb_prio_table(esw, chain, prio, l).fdb = fdb;
974 fdb_prio_table(esw, chain, prio, l).num_rules = 1;
977 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
981 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
983 esw_put_prio_table(esw, chain, prio, l);
989 esw_put_prio_table(struct mlx5_eswitch *esw, u32 chain, u16 prio, int level)
993 if (chain == FDB_SLOW_PATH_CHAIN)
996 mutex_lock(&esw->fdb_table.offloads.fdb_prio_lock);
998 for (l = level; l >= 0; l--) {
999 if (--(fdb_prio_table(esw, chain, prio, l).num_rules) > 0)
1002 put_sz_to_pool(esw, fdb_prio_table(esw, chain, prio, l).fdb->max_fte);
1003 mlx5_destroy_flow_table(fdb_prio_table(esw, chain, prio, l).fdb);
1004 fdb_prio_table(esw, chain, prio, l).fdb = NULL;
1007 mutex_unlock(&esw->fdb_table.offloads.fdb_prio_lock);
1010 static void esw_destroy_offloads_fast_fdb_tables(struct mlx5_eswitch *esw)
1012 /* If lazy creation isn't supported, deref the fast path tables */
1013 if (!(esw->fdb_table.flags & ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED)) {
1014 esw_put_prio_table(esw, 0, 1, 1);
1015 esw_put_prio_table(esw, 0, 1, 0);
1019 #define MAX_PF_SQ 256
1020 #define MAX_SQ_NVPORTS 32
1022 static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1025 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1029 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1030 MLX5_SET(create_flow_group_in, flow_group_in,
1031 match_criteria_enable,
1032 MLX5_MATCH_MISC_PARAMETERS_2);
1034 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1035 misc_parameters_2.metadata_reg_c_0);
1037 MLX5_SET(create_flow_group_in, flow_group_in,
1038 match_criteria_enable,
1039 MLX5_MATCH_MISC_PARAMETERS);
1041 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1042 misc_parameters.source_port);
1046 static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
1048 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1049 struct mlx5_flow_table_attr ft_attr = {};
1050 struct mlx5_core_dev *dev = esw->dev;
1051 u32 *flow_group_in, max_flow_counter;
1052 struct mlx5_flow_namespace *root_ns;
1053 struct mlx5_flow_table *fdb = NULL;
1054 int table_size, ix, err = 0, i;
1055 struct mlx5_flow_group *g;
1056 u32 flags = 0, fdb_max;
1057 void *match_criteria;
1060 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1061 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1065 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1067 esw_warn(dev, "Failed to get FDB flow namespace\n");
1072 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1073 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1074 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1076 esw_debug(dev, "Create offloads FDB table, min (max esw size(2^%d), max counters(%d), groups(%d), max flow table size(2^%d))\n",
1077 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size),
1078 max_flow_counter, ESW_OFFLOADS_NUM_GROUPS,
1081 for (i = 0; i < ARRAY_SIZE(ESW_POOLS); i++)
1082 esw->fdb_table.offloads.fdb_left[i] =
1083 ESW_POOLS[i] <= fdb_max ? ESW_SIZE / ESW_POOLS[i] : 0;
1085 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1086 MLX5_ESW_MISS_FLOWS + esw->total_vports;
1088 /* create the slow path fdb with encap set, so further table instances
1089 * can be created at run time while VFs are probed if the FW allows that.
1091 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1092 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1093 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1095 ft_attr.flags = flags;
1096 ft_attr.max_fte = table_size;
1097 ft_attr.prio = FDB_SLOW_PATH;
1099 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1102 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1105 esw->fdb_table.offloads.slow_fdb = fdb;
1107 /* If lazy creation isn't supported, open the fast path tables now */
1108 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, multi_fdb_encap) &&
1109 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1110 esw->fdb_table.flags &= ~ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
1111 esw_warn(dev, "Lazy creation of flow tables isn't supported, ignoring priorities\n");
1112 esw_get_prio_table(esw, 0, 1, 0);
1113 esw_get_prio_table(esw, 0, 1, 1);
1115 esw_debug(dev, "Lazy creation of flow tables supported, deferring table opening\n");
1116 esw->fdb_table.flags |= ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED;
1119 /* create send-to-vport group */
1120 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1121 MLX5_MATCH_MISC_PARAMETERS);
1123 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1125 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1126 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1128 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
1129 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1130 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1132 g = mlx5_create_flow_group(fdb, flow_group_in);
1135 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1136 goto send_vport_err;
1138 esw->fdb_table.offloads.send_to_vport_grp = g;
1140 /* create peer esw miss group */
1141 memset(flow_group_in, 0, inlen);
1143 esw_set_flow_group_source_port(esw, flow_group_in);
1145 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1146 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1150 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1151 misc_parameters.source_eswitch_owner_vhca_id);
1153 MLX5_SET(create_flow_group_in, flow_group_in,
1154 source_eswitch_owner_vhca_id_valid, 1);
1157 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1158 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1159 ix + esw->total_vports - 1);
1160 ix += esw->total_vports;
1162 g = mlx5_create_flow_group(fdb, flow_group_in);
1165 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1168 esw->fdb_table.offloads.peer_miss_grp = g;
1170 /* create miss group */
1171 memset(flow_group_in, 0, inlen);
1172 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1173 MLX5_MATCH_OUTER_HEADERS);
1174 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1176 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1177 outer_headers.dmac_47_16);
1180 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1181 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1182 ix + MLX5_ESW_MISS_FLOWS);
1184 g = mlx5_create_flow_group(fdb, flow_group_in);
1187 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1190 esw->fdb_table.offloads.miss_grp = g;
1192 err = esw_add_fdb_miss_rule(esw);
1196 esw->nvports = nvports;
1197 kvfree(flow_group_in);
1201 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1203 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1205 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1207 esw_destroy_offloads_fast_fdb_tables(esw);
1208 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1211 kvfree(flow_group_in);
1215 static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1217 if (!esw->fdb_table.offloads.slow_fdb)
1220 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1221 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1222 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1223 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1224 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1225 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1227 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1228 esw_destroy_offloads_fast_fdb_tables(esw);
1231 static int esw_create_offloads_table(struct mlx5_eswitch *esw, int nvports)
1233 struct mlx5_flow_table_attr ft_attr = {};
1234 struct mlx5_core_dev *dev = esw->dev;
1235 struct mlx5_flow_table *ft_offloads;
1236 struct mlx5_flow_namespace *ns;
1239 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1241 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1245 ft_attr.max_fte = nvports + MLX5_ESW_MISS_FLOWS;
1247 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1248 if (IS_ERR(ft_offloads)) {
1249 err = PTR_ERR(ft_offloads);
1250 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1254 esw->offloads.ft_offloads = ft_offloads;
1258 static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1260 struct mlx5_esw_offload *offloads = &esw->offloads;
1262 mlx5_destroy_flow_table(offloads->ft_offloads);
1265 static int esw_create_vport_rx_group(struct mlx5_eswitch *esw, int nvports)
1267 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1268 struct mlx5_flow_group *g;
1272 nvports = nvports + MLX5_ESW_MISS_FLOWS;
1273 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1277 /* create vport rx group */
1278 esw_set_flow_group_source_port(esw, flow_group_in);
1280 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1281 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1283 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1287 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1291 esw->offloads.vport_rx_group = g;
1293 kvfree(flow_group_in);
1297 static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1299 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1302 struct mlx5_flow_handle *
1303 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1304 struct mlx5_flow_destination *dest)
1306 struct mlx5_flow_act flow_act = {0};
1307 struct mlx5_flow_handle *flow_rule;
1308 struct mlx5_flow_spec *spec;
1311 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1313 flow_rule = ERR_PTR(-ENOMEM);
1317 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1318 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1319 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1320 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
1322 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
1323 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
1325 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1327 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1328 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1330 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1331 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1333 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1336 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1337 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1338 &flow_act, dest, 1);
1339 if (IS_ERR(flow_rule)) {
1340 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1349 static int esw_offloads_start(struct mlx5_eswitch *esw,
1350 struct netlink_ext_ack *extack)
1354 if (esw->mode != MLX5_ESWITCH_LEGACY &&
1355 !mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1356 NL_SET_ERR_MSG_MOD(extack,
1357 "Can't set offloads mode, SRIOV legacy not enabled");
1361 mlx5_eswitch_disable(esw);
1362 mlx5_eswitch_update_num_of_vfs(esw, esw->dev->priv.sriov.num_vfs);
1363 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
1365 NL_SET_ERR_MSG_MOD(extack,
1366 "Failed setting eswitch to offloads");
1367 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
1369 NL_SET_ERR_MSG_MOD(extack,
1370 "Failed setting eswitch back to legacy");
1373 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
1374 if (mlx5_eswitch_inline_mode_get(esw,
1375 &esw->offloads.inline_mode)) {
1376 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
1377 NL_SET_ERR_MSG_MOD(extack,
1378 "Inline mode is different between vports");
1384 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
1386 kfree(esw->offloads.vport_reps);
1389 int esw_offloads_init_reps(struct mlx5_eswitch *esw)
1391 int total_vports = esw->total_vports;
1392 struct mlx5_eswitch_rep *rep;
1396 esw->offloads.vport_reps = kcalloc(total_vports,
1397 sizeof(struct mlx5_eswitch_rep),
1399 if (!esw->offloads.vport_reps)
1402 mlx5_esw_for_all_reps(esw, vport_index, rep) {
1403 rep->vport = mlx5_eswitch_index_to_vport_num(esw, vport_index);
1404 rep->vport_index = vport_index;
1406 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
1407 atomic_set(&rep->rep_data[rep_type].state,
1414 static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
1415 struct mlx5_eswitch_rep *rep, u8 rep_type)
1417 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1418 REP_LOADED, REP_REGISTERED) == REP_LOADED)
1419 esw->offloads.rep_ops[rep_type]->unload(rep);
1422 static void __unload_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1424 struct mlx5_eswitch_rep *rep;
1426 if (mlx5_ecpf_vport_exists(esw->dev)) {
1427 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1428 __esw_offloads_unload_rep(esw, rep, rep_type);
1431 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1432 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1433 __esw_offloads_unload_rep(esw, rep, rep_type);
1436 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1437 __esw_offloads_unload_rep(esw, rep, rep_type);
1440 static void __unload_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1443 struct mlx5_eswitch_rep *rep;
1446 mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvports)
1447 __esw_offloads_unload_rep(esw, rep, rep_type);
1450 static void esw_offloads_unload_vf_reps(struct mlx5_eswitch *esw, int nvports)
1452 u8 rep_type = NUM_REP_TYPES;
1454 while (rep_type-- > 0)
1455 __unload_reps_vf_vport(esw, nvports, rep_type);
1458 static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1460 __unload_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1462 /* Special vports must be the last to unload. */
1463 __unload_reps_special_vport(esw, rep_type);
1466 static void esw_offloads_unload_all_reps(struct mlx5_eswitch *esw)
1468 u8 rep_type = NUM_REP_TYPES;
1470 while (rep_type-- > 0)
1471 __unload_reps_all_vport(esw, rep_type);
1474 static int __esw_offloads_load_rep(struct mlx5_eswitch *esw,
1475 struct mlx5_eswitch_rep *rep, u8 rep_type)
1479 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
1480 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
1481 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
1483 atomic_set(&rep->rep_data[rep_type].state,
1490 static int __load_reps_special_vport(struct mlx5_eswitch *esw, u8 rep_type)
1492 struct mlx5_eswitch_rep *rep;
1495 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1496 err = __esw_offloads_load_rep(esw, rep, rep_type);
1500 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1501 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1502 err = __esw_offloads_load_rep(esw, rep, rep_type);
1507 if (mlx5_ecpf_vport_exists(esw->dev)) {
1508 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
1509 err = __esw_offloads_load_rep(esw, rep, rep_type);
1517 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1518 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
1519 __esw_offloads_unload_rep(esw, rep, rep_type);
1523 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
1524 __esw_offloads_unload_rep(esw, rep, rep_type);
1528 static int __load_reps_vf_vport(struct mlx5_eswitch *esw, int nvports,
1531 struct mlx5_eswitch_rep *rep;
1534 mlx5_esw_for_each_vf_rep(esw, i, rep, nvports) {
1535 err = __esw_offloads_load_rep(esw, rep, rep_type);
1543 __unload_reps_vf_vport(esw, --i, rep_type);
1547 static int __load_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
1551 /* Special vports must be loaded first, uplink rep creates mdev resource. */
1552 err = __load_reps_special_vport(esw, rep_type);
1556 err = __load_reps_vf_vport(esw, esw->esw_funcs.num_vfs, rep_type);
1563 __unload_reps_special_vport(esw, rep_type);
1567 static int esw_offloads_load_vf_reps(struct mlx5_eswitch *esw, int nvports)
1572 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1573 err = __load_reps_vf_vport(esw, nvports, rep_type);
1581 while (rep_type-- > 0)
1582 __unload_reps_vf_vport(esw, nvports, rep_type);
1586 static int esw_offloads_load_all_reps(struct mlx5_eswitch *esw)
1591 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
1592 err = __load_reps_all_vport(esw, rep_type);
1600 while (rep_type-- > 0)
1601 __unload_reps_all_vport(esw, rep_type);
1605 #define ESW_OFFLOADS_DEVCOM_PAIR (0)
1606 #define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
1608 static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
1609 struct mlx5_eswitch *peer_esw)
1613 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
1620 static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
1622 mlx5e_tc_clean_fdb_peer_flows(esw);
1623 esw_del_fdb_peer_miss_rules(esw);
1626 static int mlx5_esw_offloads_devcom_event(int event,
1630 struct mlx5_eswitch *esw = my_data;
1631 struct mlx5_eswitch *peer_esw = event_data;
1632 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1636 case ESW_OFFLOADS_DEVCOM_PAIR:
1637 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
1638 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
1641 err = mlx5_esw_offloads_pair(esw, peer_esw);
1645 err = mlx5_esw_offloads_pair(peer_esw, esw);
1649 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
1652 case ESW_OFFLOADS_DEVCOM_UNPAIR:
1653 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
1656 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
1657 mlx5_esw_offloads_unpair(peer_esw);
1658 mlx5_esw_offloads_unpair(esw);
1665 mlx5_esw_offloads_unpair(esw);
1668 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
1673 static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
1675 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1677 INIT_LIST_HEAD(&esw->offloads.peer_flows);
1678 mutex_init(&esw->offloads.peer_mutex);
1680 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1683 mlx5_devcom_register_component(devcom,
1684 MLX5_DEVCOM_ESW_OFFLOADS,
1685 mlx5_esw_offloads_devcom_event,
1688 mlx5_devcom_send_event(devcom,
1689 MLX5_DEVCOM_ESW_OFFLOADS,
1690 ESW_OFFLOADS_DEVCOM_PAIR, esw);
1693 static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
1695 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
1697 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1700 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
1701 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
1703 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1706 static int esw_vport_ingress_prio_tag_config(struct mlx5_eswitch *esw,
1707 struct mlx5_vport *vport)
1709 struct mlx5_flow_act flow_act = {0};
1710 struct mlx5_flow_spec *spec;
1713 /* For prio tag mode, there is only 1 FTEs:
1714 * 1) Untagged packets - push prio tag VLAN and modify metadata if
1716 * Unmatched traffic is allowed by default
1719 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1725 /* Untagged packets - push prio tag VLAN, allow */
1726 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1727 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 0);
1728 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1729 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
1730 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1731 flow_act.vlan[0].ethtype = ETH_P_8021Q;
1732 flow_act.vlan[0].vid = 0;
1733 flow_act.vlan[0].prio = 0;
1735 if (vport->ingress.modify_metadata_rule) {
1736 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1737 flow_act.modify_id = vport->ingress.modify_metadata_id;
1740 vport->ingress.allow_rule =
1741 mlx5_add_flow_rules(vport->ingress.acl, spec,
1742 &flow_act, NULL, 0);
1743 if (IS_ERR(vport->ingress.allow_rule)) {
1744 err = PTR_ERR(vport->ingress.allow_rule);
1746 "vport[%d] configure ingress untagged allow rule, err(%d)\n",
1748 vport->ingress.allow_rule = NULL;
1756 esw_vport_cleanup_ingress_rules(esw, vport);
1760 static int esw_vport_add_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1761 struct mlx5_vport *vport)
1763 u8 action[MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)] = {};
1764 static const struct mlx5_flow_spec spec = {};
1765 struct mlx5_flow_act flow_act = {};
1768 MLX5_SET(set_action_in, action, action_type, MLX5_ACTION_TYPE_SET);
1769 MLX5_SET(set_action_in, action, field, MLX5_ACTION_IN_FIELD_METADATA_REG_C_0);
1770 MLX5_SET(set_action_in, action, data,
1771 mlx5_eswitch_get_vport_metadata_for_match(esw, vport->vport));
1773 err = mlx5_modify_header_alloc(esw->dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS,
1774 1, action, &vport->ingress.modify_metadata_id);
1777 "failed to alloc modify header for vport %d ingress acl (%d)\n",
1782 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1783 flow_act.modify_id = vport->ingress.modify_metadata_id;
1784 vport->ingress.modify_metadata_rule = mlx5_add_flow_rules(vport->ingress.acl,
1785 &spec, &flow_act, NULL, 0);
1786 if (IS_ERR(vport->ingress.modify_metadata_rule)) {
1787 err = PTR_ERR(vport->ingress.modify_metadata_rule);
1789 "failed to add setting metadata rule for vport %d ingress acl, err(%d)\n",
1791 vport->ingress.modify_metadata_rule = NULL;
1797 mlx5_modify_header_dealloc(esw->dev, vport->ingress.modify_metadata_id);
1801 void esw_vport_del_ingress_acl_modify_metadata(struct mlx5_eswitch *esw,
1802 struct mlx5_vport *vport)
1804 if (vport->ingress.modify_metadata_rule) {
1805 mlx5_del_flow_rules(vport->ingress.modify_metadata_rule);
1806 mlx5_modify_header_dealloc(esw->dev, vport->ingress.modify_metadata_id);
1808 vport->ingress.modify_metadata_rule = NULL;
1812 static int esw_vport_egress_prio_tag_config(struct mlx5_eswitch *esw,
1813 struct mlx5_vport *vport)
1815 struct mlx5_flow_act flow_act = {0};
1816 struct mlx5_flow_spec *spec;
1819 if (!MLX5_CAP_GEN(esw->dev, prio_tag_required))
1822 /* For prio tag mode, there is only 1 FTEs:
1823 * 1) prio tag packets - pop the prio tag VLAN, allow
1824 * Unmatched traffic is allowed by default
1827 esw_vport_cleanup_egress_rules(esw, vport);
1829 err = esw_vport_enable_egress_acl(esw, vport);
1831 mlx5_core_warn(esw->dev,
1832 "failed to enable egress acl (%d) on vport[%d]\n",
1838 "vport[%d] configure prio tag egress rules\n", vport->vport);
1840 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1846 /* prio tag vlan rule - pop it so VF receives untagged packets */
1847 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.cvlan_tag);
1848 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag);
1849 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1850 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, 0);
1852 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1853 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
1854 MLX5_FLOW_CONTEXT_ACTION_ALLOW;
1855 vport->egress.allowed_vlan =
1856 mlx5_add_flow_rules(vport->egress.acl, spec,
1857 &flow_act, NULL, 0);
1858 if (IS_ERR(vport->egress.allowed_vlan)) {
1859 err = PTR_ERR(vport->egress.allowed_vlan);
1861 "vport[%d] configure egress pop prio tag vlan rule failed, err(%d)\n",
1863 vport->egress.allowed_vlan = NULL;
1871 esw_vport_cleanup_egress_rules(esw, vport);
1875 static int esw_vport_ingress_common_config(struct mlx5_eswitch *esw,
1876 struct mlx5_vport *vport)
1880 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1881 !MLX5_CAP_GEN(esw->dev, prio_tag_required))
1884 esw_vport_cleanup_ingress_rules(esw, vport);
1886 err = esw_vport_enable_ingress_acl(esw, vport);
1889 "failed to enable ingress acl (%d) on vport[%d]\n",
1895 "vport[%d] configure ingress rules\n", vport->vport);
1897 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1898 err = esw_vport_add_ingress_acl_modify_metadata(esw, vport);
1903 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
1904 mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
1905 err = esw_vport_ingress_prio_tag_config(esw, vport);
1912 esw_vport_disable_ingress_acl(esw, vport);
1917 esw_check_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
1919 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
1922 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1923 MLX5_FDB_TO_VPORT_REG_C_0))
1926 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
1929 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
1930 mlx5_ecpf_vport_exists(esw->dev))
1936 static int esw_create_offloads_acl_tables(struct mlx5_eswitch *esw)
1938 struct mlx5_vport *vport;
1942 if (esw_check_vport_match_metadata_supported(esw))
1943 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
1945 mlx5_esw_for_all_vports(esw, i, vport) {
1946 err = esw_vport_ingress_common_config(esw, vport);
1950 if (mlx5_eswitch_is_vf_vport(esw, vport->vport)) {
1951 err = esw_vport_egress_prio_tag_config(esw, vport);
1957 if (mlx5_eswitch_vport_match_metadata_enabled(esw))
1958 esw_info(esw->dev, "Use metadata reg_c as source vport to match\n");
1963 esw_vport_disable_ingress_acl(esw, vport);
1965 for (j = MLX5_VPORT_PF; j < i; j++) {
1966 vport = &esw->vports[j];
1967 esw_vport_disable_egress_acl(esw, vport);
1968 esw_vport_disable_ingress_acl(esw, vport);
1974 static void esw_destroy_offloads_acl_tables(struct mlx5_eswitch *esw)
1976 struct mlx5_vport *vport;
1979 mlx5_esw_for_all_vports(esw, i, vport) {
1980 esw_vport_disable_egress_acl(esw, vport);
1981 esw_vport_disable_ingress_acl(esw, vport);
1984 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
1987 static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
1989 int num_vfs = esw->esw_funcs.num_vfs;
1993 if (mlx5_core_is_ecpf_esw_manager(esw->dev))
1994 total_vports = esw->total_vports;
1996 total_vports = num_vfs + MLX5_SPECIAL_VPORTS(esw->dev);
1998 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
1999 mutex_init(&esw->fdb_table.offloads.fdb_prio_lock);
2001 err = esw_create_offloads_acl_tables(esw);
2005 err = esw_create_offloads_fdb_tables(esw, total_vports);
2007 goto create_fdb_err;
2009 err = esw_create_offloads_table(esw, total_vports);
2013 err = esw_create_vport_rx_group(esw, total_vports);
2020 esw_destroy_offloads_table(esw);
2023 esw_destroy_offloads_fdb_tables(esw);
2026 esw_destroy_offloads_acl_tables(esw);
2031 static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
2033 esw_destroy_vport_rx_group(esw);
2034 esw_destroy_offloads_table(esw);
2035 esw_destroy_offloads_fdb_tables(esw);
2036 esw_destroy_offloads_acl_tables(esw);
2040 esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
2042 bool host_pf_disabled;
2045 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
2046 host_params_context.host_num_of_vfs);
2047 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
2048 host_params_context.host_pf_disabled);
2050 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
2053 /* Number of VFs can only change from "0 to x" or "x to 0". */
2054 if (esw->esw_funcs.num_vfs > 0) {
2055 esw_offloads_unload_vf_reps(esw, esw->esw_funcs.num_vfs);
2059 err = esw_offloads_load_vf_reps(esw, new_num_vfs);
2063 esw->esw_funcs.num_vfs = new_num_vfs;
2066 static void esw_functions_changed_event_handler(struct work_struct *work)
2068 struct mlx5_host_work *host_work;
2069 struct mlx5_eswitch *esw;
2072 host_work = container_of(work, struct mlx5_host_work, work);
2073 esw = host_work->esw;
2075 out = mlx5_esw_query_functions(esw->dev);
2079 esw_vfs_changed_event_handler(esw, out);
2085 int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
2087 struct mlx5_esw_functions *esw_funcs;
2088 struct mlx5_host_work *host_work;
2089 struct mlx5_eswitch *esw;
2091 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
2095 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
2096 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
2098 host_work->esw = esw;
2100 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
2101 queue_work(esw->work_queue, &host_work->work);
2106 int esw_offloads_enable(struct mlx5_eswitch *esw)
2110 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
2111 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
2112 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
2114 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2116 err = esw_offloads_steering_init(esw);
2120 err = esw_set_passing_vport_metadata(esw, true);
2122 goto err_vport_metadata;
2124 mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
2126 err = esw_offloads_load_all_reps(esw);
2130 esw_offloads_devcom_init(esw);
2131 mutex_init(&esw->offloads.termtbl_mutex);
2133 mlx5_rdma_enable_roce(esw->dev);
2138 mlx5_eswitch_disable_pf_vf_vports(esw);
2139 esw_set_passing_vport_metadata(esw, false);
2141 esw_offloads_steering_cleanup(esw);
2145 static int esw_offloads_stop(struct mlx5_eswitch *esw,
2146 struct netlink_ext_ack *extack)
2150 mlx5_eswitch_disable(esw);
2151 err = mlx5_eswitch_enable(esw, MLX5_ESWITCH_LEGACY);
2153 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
2154 err1 = mlx5_eswitch_enable(esw, MLX5_ESWITCH_OFFLOADS);
2156 NL_SET_ERR_MSG_MOD(extack,
2157 "Failed setting eswitch back to offloads");
2164 void esw_offloads_disable(struct mlx5_eswitch *esw)
2166 mlx5_rdma_disable_roce(esw->dev);
2167 esw_offloads_devcom_cleanup(esw);
2168 esw_offloads_unload_all_reps(esw);
2169 mlx5_eswitch_disable_pf_vf_vports(esw);
2170 esw_set_passing_vport_metadata(esw, false);
2171 esw_offloads_steering_cleanup(esw);
2172 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
2175 static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
2178 case DEVLINK_ESWITCH_MODE_LEGACY:
2179 *mlx5_mode = MLX5_ESWITCH_LEGACY;
2181 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
2182 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
2191 static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
2193 switch (mlx5_mode) {
2194 case MLX5_ESWITCH_LEGACY:
2195 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
2197 case MLX5_ESWITCH_OFFLOADS:
2198 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
2207 static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
2210 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
2211 *mlx5_mode = MLX5_INLINE_MODE_NONE;
2213 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
2214 *mlx5_mode = MLX5_INLINE_MODE_L2;
2216 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
2217 *mlx5_mode = MLX5_INLINE_MODE_IP;
2219 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
2220 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
2229 static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
2231 switch (mlx5_mode) {
2232 case MLX5_INLINE_MODE_NONE:
2233 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
2235 case MLX5_INLINE_MODE_L2:
2236 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
2238 case MLX5_INLINE_MODE_IP:
2239 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
2241 case MLX5_INLINE_MODE_TCP_UDP:
2242 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
2251 static int mlx5_devlink_eswitch_check(struct devlink *devlink)
2253 struct mlx5_core_dev *dev = devlink_priv(devlink);
2255 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2258 if(!MLX5_ESWITCH_MANAGER(dev))
2261 if (dev->priv.eswitch->mode == MLX5_ESWITCH_NONE &&
2262 !mlx5_core_is_ecpf_esw_manager(dev))
2268 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
2269 struct netlink_ext_ack *extack)
2271 struct mlx5_core_dev *dev = devlink_priv(devlink);
2272 u16 cur_mlx5_mode, mlx5_mode = 0;
2275 err = mlx5_devlink_eswitch_check(devlink);
2279 cur_mlx5_mode = dev->priv.eswitch->mode;
2281 if (esw_mode_from_devlink(mode, &mlx5_mode))
2284 if (cur_mlx5_mode == mlx5_mode)
2287 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
2288 return esw_offloads_start(dev->priv.eswitch, extack);
2289 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
2290 return esw_offloads_stop(dev->priv.eswitch, extack);
2295 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
2297 struct mlx5_core_dev *dev = devlink_priv(devlink);
2300 err = mlx5_devlink_eswitch_check(devlink);
2304 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
2307 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
2308 struct netlink_ext_ack *extack)
2310 struct mlx5_core_dev *dev = devlink_priv(devlink);
2311 struct mlx5_eswitch *esw = dev->priv.eswitch;
2312 int err, vport, num_vport;
2315 err = mlx5_devlink_eswitch_check(devlink);
2319 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2320 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2321 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
2324 case MLX5_CAP_INLINE_MODE_L2:
2325 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
2327 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2331 if (atomic64_read(&esw->offloads.num_flows) > 0) {
2332 NL_SET_ERR_MSG_MOD(extack,
2333 "Can't set inline mode when flows are configured");
2337 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
2341 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2342 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
2344 NL_SET_ERR_MSG_MOD(extack,
2345 "Failed to set min inline on vport");
2346 goto revert_inline_mode;
2350 esw->offloads.inline_mode = mlx5_mode;
2354 num_vport = --vport;
2355 mlx5_esw_for_each_host_func_vport_reverse(esw, vport, num_vport)
2356 mlx5_modify_nic_vport_min_inline(dev,
2358 esw->offloads.inline_mode);
2363 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
2365 struct mlx5_core_dev *dev = devlink_priv(devlink);
2366 struct mlx5_eswitch *esw = dev->priv.eswitch;
2369 err = mlx5_devlink_eswitch_check(devlink);
2373 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
2376 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
2378 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2379 struct mlx5_core_dev *dev = esw->dev;
2382 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2385 if (esw->mode == MLX5_ESWITCH_NONE)
2388 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2389 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2390 mlx5_mode = MLX5_INLINE_MODE_NONE;
2392 case MLX5_CAP_INLINE_MODE_L2:
2393 mlx5_mode = MLX5_INLINE_MODE_L2;
2395 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2400 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
2401 mlx5_esw_for_each_host_func_vport(esw, vport, esw->esw_funcs.num_vfs) {
2402 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
2403 if (prev_mlx5_mode != mlx5_mode)
2405 prev_mlx5_mode = mlx5_mode;
2413 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
2414 enum devlink_eswitch_encap_mode encap,
2415 struct netlink_ext_ack *extack)
2417 struct mlx5_core_dev *dev = devlink_priv(devlink);
2418 struct mlx5_eswitch *esw = dev->priv.eswitch;
2421 err = mlx5_devlink_eswitch_check(devlink);
2425 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
2426 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
2427 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)))
2430 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC)
2433 if (esw->mode == MLX5_ESWITCH_LEGACY) {
2434 esw->offloads.encap = encap;
2438 if (esw->offloads.encap == encap)
2441 if (atomic64_read(&esw->offloads.num_flows) > 0) {
2442 NL_SET_ERR_MSG_MOD(extack,
2443 "Can't set encapsulation when flows are configured");
2447 esw_destroy_offloads_fdb_tables(esw);
2449 esw->offloads.encap = encap;
2451 err = esw_create_offloads_fdb_tables(esw, esw->nvports);
2454 NL_SET_ERR_MSG_MOD(extack,
2455 "Failed re-creating fast FDB table");
2456 esw->offloads.encap = !encap;
2457 (void)esw_create_offloads_fdb_tables(esw, esw->nvports);
2463 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
2464 enum devlink_eswitch_encap_mode *encap)
2466 struct mlx5_core_dev *dev = devlink_priv(devlink);
2467 struct mlx5_eswitch *esw = dev->priv.eswitch;
2470 err = mlx5_devlink_eswitch_check(devlink);
2474 *encap = esw->offloads.encap;
2478 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
2479 const struct mlx5_eswitch_rep_ops *ops,
2482 struct mlx5_eswitch_rep_data *rep_data;
2483 struct mlx5_eswitch_rep *rep;
2486 esw->offloads.rep_ops[rep_type] = ops;
2487 mlx5_esw_for_all_reps(esw, i, rep) {
2488 rep_data = &rep->rep_data[rep_type];
2489 atomic_set(&rep_data->state, REP_REGISTERED);
2492 EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
2494 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
2496 struct mlx5_eswitch_rep *rep;
2499 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
2500 __unload_reps_all_vport(esw, rep_type);
2502 mlx5_esw_for_all_reps(esw, i, rep)
2503 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2505 EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
2507 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
2509 struct mlx5_eswitch_rep *rep;
2511 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2512 return rep->rep_data[rep_type].priv;
2515 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
2519 struct mlx5_eswitch_rep *rep;
2521 rep = mlx5_eswitch_get_rep(esw, vport);
2523 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2524 esw->offloads.rep_ops[rep_type]->get_proto_dev)
2525 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
2528 EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
2530 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
2532 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
2534 EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
2536 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
2539 return mlx5_eswitch_get_rep(esw, vport);
2541 EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
2543 bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num)
2545 return vport_num >= MLX5_VPORT_FIRST_VF &&
2546 vport_num <= esw->dev->priv.sriov.max_vfs;
2549 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
2551 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
2553 EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
2555 u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,
2558 return ((MLX5_CAP_GEN(esw->dev, vhca_id) & 0xffff) << 16) | vport_num;
2560 EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);