drivers/net/ethernet/mellanox/mlx5/core/fw.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/driver.h>
  34 #include <linux/mlx5/cmd.h>
  35 #include <linux/mlx5/eswitch.h>
  36 #include <linux/module.h>
  37 #include "mlx5_core.h"
  38 #include "../../mlxfw/mlxfw.h"
  39
  40 enum {
  41         MCQS_IDENTIFIER_BOOT_IMG        = 0x1,
  42         MCQS_IDENTIFIER_OEM_NVCONFIG    = 0x4,
  43         MCQS_IDENTIFIER_MLNX_NVCONFIG   = 0x5,
  44         MCQS_IDENTIFIER_CS_TOKEN        = 0x6,
  45         MCQS_IDENTIFIER_DBG_TOKEN       = 0x7,
  46         MCQS_IDENTIFIER_GEARBOX         = 0xA,
  47 };
  48
  49 enum {
  50         MCQS_UPDATE_STATE_IDLE,
  51         MCQS_UPDATE_STATE_IN_PROGRESS,
  52         MCQS_UPDATE_STATE_APPLIED,
  53         MCQS_UPDATE_STATE_ACTIVE,
  54         MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
  55         MCQS_UPDATE_STATE_FAILED,
  56         MCQS_UPDATE_STATE_CANCELED,
  57         MCQS_UPDATE_STATE_BUSY,
  58 };
  59
  60 enum {
  61         MCQI_INFO_TYPE_CAPABILITIES       = 0x0,
  62         MCQI_INFO_TYPE_VERSION            = 0x1,
  63         MCQI_INFO_TYPE_ACTIVATION_METHOD  = 0x5,
  64 };
  65
  66 enum {
  67         MCQI_FW_RUNNING_VERSION = 0,
  68         MCQI_FW_STORED_VERSION  = 1,
  69 };
  70
  71 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
  72                                   int outlen)
  73 {
  74         u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0};
  75
  76         MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
  77         return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
  78 }
  79
  80 int mlx5_query_board_id(struct mlx5_core_dev *dev)
  81 {
  82         u32 *out;
  83         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  84         int err;
  85
  86         out = kzalloc(outlen, GFP_KERNEL);
  87         if (!out)
  88                 return -ENOMEM;
  89
  90         err = mlx5_cmd_query_adapter(dev, out, outlen);
  91         if (err)
  92                 goto out;
  93
  94         memcpy(dev->board_id,
  95                MLX5_ADDR_OF(query_adapter_out, out,
  96                             query_adapter_struct.vsd_contd_psid),
  97                MLX5_FLD_SZ_BYTES(query_adapter_out,
  98                                  query_adapter_struct.vsd_contd_psid));
  99
 100 out:
 101         kfree(out);
 102         return err;
 103 }
 104
 105 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
 106 {
 107         u32 *out;
 108         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
 109         int err;
 110
 111         out = kzalloc(outlen, GFP_KERNEL);
 112         if (!out)
 113                 return -ENOMEM;
 114
 115         err = mlx5_cmd_query_adapter(mdev, out, outlen);
 116         if (err)
 117                 goto out;
 118
 119         *vendor_id = MLX5_GET(query_adapter_out, out,
 120                               query_adapter_struct.ieee_vendor_id);
 121 out:
 122         kfree(out);
 123         return err;
 124 }
 125 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
 126
 127 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
 128 {
 129         return mlx5_query_pcam_reg(dev, dev->caps.pcam,
 130                                    MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
 131                                    MLX5_PCAM_REGS_5000_TO_507F);
 132 }
 133
 134 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
 135 {
 136         return mlx5_query_mcam_reg(dev, dev->caps.mcam,
 137                                    MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
 138                                    MLX5_MCAM_REGS_FIRST_128);
 139 }
 140
 141 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
 142 {
 143         return mlx5_query_qcam_reg(dev, dev->caps.qcam,
 144                                    MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
 145                                    MLX5_QCAM_REGS_FIRST_128);
 146 }
 147
 148 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
 149 {
 150         int err;
 151
 152         err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
 153         if (err)
 154                 return err;
 155
 156         if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
 157                 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
 158                 if (err)
 159                         return err;
 160         }
 161
 162         if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 163                 err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS);
 164                 if (err)
 165                         return err;
 166         }
 167
 168         if (MLX5_CAP_GEN(dev, pg)) {
 169                 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
 170                 if (err)
 171                         return err;
 172         }
 173
 174         if (MLX5_CAP_GEN(dev, atomic)) {
 175                 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
 176                 if (err)
 177                         return err;
 178         }
 179
 180         if (MLX5_CAP_GEN(dev, roce)) {
 181                 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
 182                 if (err)
 183                         return err;
 184         }
 185
 186         if (MLX5_CAP_GEN(dev, nic_flow_table) ||
 187             MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 188                 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
 189                 if (err)
 190                         return err;
 191         }
 192
 193         if (MLX5_CAP_GEN(dev, vport_group_manager) &&
 194             MLX5_ESWITCH_MANAGER(dev)) {
 195                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
 196                 if (err)
 197                         return err;
 198         }
 199
 200         if (MLX5_ESWITCH_MANAGER(dev)) {
 201                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
 202                 if (err)
 203                         return err;
 204         }
 205
 206         if (MLX5_CAP_GEN(dev, vector_calc)) {
 207                 err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC);
 208                 if (err)
 209                         return err;
 210         }
 211
 212         if (MLX5_CAP_GEN(dev, qos)) {
 213                 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
 214                 if (err)
 215                         return err;
 216         }
 217
 218         if (MLX5_CAP_GEN(dev, debug))
 219                 mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
 220
 221         if (MLX5_CAP_GEN(dev, pcam_reg))
 222                 mlx5_get_pcam_reg(dev);
 223
 224         if (MLX5_CAP_GEN(dev, mcam_reg))
 225                 mlx5_get_mcam_reg(dev);
 226
 227         if (MLX5_CAP_GEN(dev, qcam_reg))
 228                 mlx5_get_qcam_reg(dev);
 229
 230         if (MLX5_CAP_GEN(dev, device_memory)) {
 231                 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_MEM);
 232                 if (err)
 233                         return err;
 234         }
 235
 236         if (MLX5_CAP_GEN(dev, event_cap)) {
 237                 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_EVENT);
 238                 if (err)
 239                         return err;
 240         }
 241
 242         if (MLX5_CAP_GEN(dev, tls)) {
 243                 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
 244                 if (err)
 245                         return err;
 246         }
 247
 248         if (MLX5_CAP_GEN_64(dev, general_obj_types) &
 249                 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
 250                 err = mlx5_core_get_caps(dev, MLX5_CAP_VDPA_EMULATION);
 251                 if (err)
 252                         return err;
 253         }
 254
 255         return 0;
 256 }
 257
 258 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
 259 {
 260         u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0};
 261         u32 in[MLX5_ST_SZ_DW(init_hca_in)]   = {0};
 262         int i;
 263
 264         MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
 265
 266         if (MLX5_CAP_GEN(dev, sw_owner_id)) {
 267                 for (i = 0; i < 4; i++)
 268                         MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
 269                                        sw_owner_id[i]);
 270         }
 271
 272         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 273 }
 274
 275 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
 276 {
 277         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 278         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)]   = {0};
 279
 280         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 281         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 282 }
 283
 284 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
 285 {
 286         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 287         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 288         int force_state;
 289         int ret;
 290
 291         if (!MLX5_CAP_GEN(dev, force_teardown)) {
 292                 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
 293                 return -EOPNOTSUPP;
 294         }
 295
 296         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 297         MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
 298
 299         ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
 300         if (ret)
 301                 return ret;
 302
 303         force_state = MLX5_GET(teardown_hca_out, out, state);
 304         if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
 305                 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
 306                 return -EIO;
 307         }
 308
 309         return 0;
 310 }
 311
 312 #define MLX5_FAST_TEARDOWN_WAIT_MS   3000
 313 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
 314 {
 315         unsigned long end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
 316         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 317         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 318         int state;
 319         int ret;
 320
 321         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 322                 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
 323                 return -EOPNOTSUPP;
 324         }
 325
 326         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 327         MLX5_SET(teardown_hca_in, in, profile,
 328                  MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
 329
 330         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 331         if (ret)
 332                 return ret;
 333
 334         state = MLX5_GET(teardown_hca_out, out, state);
 335         if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
 336                 mlx5_core_warn(dev, "teardown with fast mode failed\n");
 337                 return -EIO;
 338         }
 339
 340         mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
 341
 342         /* Loop until device state turns to disable */
 343         end = jiffies + msecs_to_jiffies(delay_ms);
 344         do {
 345                 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
 346                         break;
 347
 348                 cond_resched();
 349         } while (!time_after(jiffies, end));
 350
 351         if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
 352                 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
 353                         mlx5_get_nic_state(dev), delay_ms);
 354                 return -EIO;
 355         }
 356
 357         return 0;
 358 }
 359
 360 enum mlxsw_reg_mcc_instruction {
 361         MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
 362         MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
 363         MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
 364         MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
 365         MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
 366         MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
 367 };
 368
 369 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
 370                             enum mlxsw_reg_mcc_instruction instr,
 371                             u16 component_index, u32 update_handle,
 372                             u32 component_size)
 373 {
 374         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 375         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 376
 377         memset(in, 0, sizeof(in));
 378
 379         MLX5_SET(mcc_reg, in, instruction, instr);
 380         MLX5_SET(mcc_reg, in, component_index, component_index);
 381         MLX5_SET(mcc_reg, in, update_handle, update_handle);
 382         MLX5_SET(mcc_reg, in, component_size, component_size);
 383
 384         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 385                                     sizeof(out), MLX5_REG_MCC, 0, 1);
 386 }
 387
 388 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
 389                               u32 *update_handle, u8 *error_code,
 390                               u8 *control_state)
 391 {
 392         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 393         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 394         int err;
 395
 396         memset(in, 0, sizeof(in));
 397         memset(out, 0, sizeof(out));
 398         MLX5_SET(mcc_reg, in, update_handle, *update_handle);
 399
 400         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 401                                    sizeof(out), MLX5_REG_MCC, 0, 0);
 402         if (err)
 403                 goto out;
 404
 405         *update_handle = MLX5_GET(mcc_reg, out, update_handle);
 406         *error_code = MLX5_GET(mcc_reg, out, error_code);
 407         *control_state = MLX5_GET(mcc_reg, out, control_state);
 408
 409 out:
 410         return err;
 411 }
 412
 413 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
 414                              u32 update_handle,
 415                              u32 offset, u16 size,
 416                              u8 *data)
 417 {
 418         int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
 419         u32 out[MLX5_ST_SZ_DW(mcda_reg)];
 420         int i, j, dw_size = size >> 2;
 421         __be32 data_element;
 422         u32 *in;
 423
 424         in = kzalloc(in_size, GFP_KERNEL);
 425         if (!in)
 426                 return -ENOMEM;
 427
 428         MLX5_SET(mcda_reg, in, update_handle, update_handle);
 429         MLX5_SET(mcda_reg, in, offset, offset);
 430         MLX5_SET(mcda_reg, in, size, size);
 431
 432         for (i = 0; i < dw_size; i++) {
 433                 j = i * 4;
 434                 data_element = htonl(*(u32 *)&data[j]);
 435                 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
 436         }
 437
 438         err = mlx5_core_access_reg(dev, in, in_size, out,
 439                                    sizeof(out), MLX5_REG_MCDA, 0, 1);
 440         kfree(in);
 441         return err;
 442 }
 443
 444 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
 445                                u16 component_index, bool read_pending,
 446                                u8 info_type, u16 data_size, void *mcqi_data)
 447 {
 448         u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
 449         u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
 450         void *data;
 451         int err;
 452
 453         MLX5_SET(mcqi_reg, in, component_index, component_index);
 454         MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
 455         MLX5_SET(mcqi_reg, in, info_type, info_type);
 456         MLX5_SET(mcqi_reg, in, data_size, data_size);
 457
 458         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 459                                    MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
 460                                    MLX5_REG_MCQI, 0, 0);
 461         if (err)
 462                 return err;
 463
 464         data = MLX5_ADDR_OF(mcqi_reg, out, data);
 465         memcpy(mcqi_data, data, data_size);
 466
 467         return 0;
 468 }
 469
 470 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
 471                                     u32 *max_component_size, u8 *log_mcda_word_size,
 472                                     u16 *mcda_max_write_size)
 473 {
 474         u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
 475         int err;
 476
 477         err = mlx5_reg_mcqi_query(dev, component_index, 0,
 478                                   MCQI_INFO_TYPE_CAPABILITIES,
 479                                   MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
 480         if (err)
 481                 return err;
 482
 483         *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
 484         *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
 485         *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
 486
 487         return 0;
 488 }
 489
 490 struct mlx5_mlxfw_dev {
 491         struct mlxfw_dev mlxfw_dev;
 492         struct mlx5_core_dev *mlx5_core_dev;
 493 };
 494
 495 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
 496                                 u16 component_index, u32 *p_max_size,
 497                                 u8 *p_align_bits, u16 *p_max_write_size)
 498 {
 499         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 500                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 501         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 502
 503         if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
 504                 mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
 505                 return -EOPNOTSUPP;
 506         }
 507
 508         return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
 509                                         p_align_bits, p_max_write_size);
 510 }
 511
 512 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 513 {
 514         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 515                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 516         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 517         u8 control_state, error_code;
 518         int err;
 519
 520         *fwhandle = 0;
 521         err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
 522         if (err)
 523                 return err;
 524
 525         if (control_state != MLXFW_FSM_STATE_IDLE)
 526                 return -EBUSY;
 527
 528         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 529                                 0, *fwhandle, 0);
 530 }
 531
 532 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 533                                      u16 component_index, u32 component_size)
 534 {
 535         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 536                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 537         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 538
 539         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 540                                 component_index, fwhandle, component_size);
 541 }
 542
 543 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 544                                    u8 *data, u16 size, u32 offset)
 545 {
 546         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 547                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 548         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 549
 550         return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
 551 }
 552
 553 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 554                                      u16 component_index)
 555 {
 556         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 557                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 558         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 559
 560         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 561                                 component_index, fwhandle, 0);
 562 }
 563
 564 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 565 {
 566         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 567                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 568         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 569
 570         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 571                                 fwhandle, 0);
 572 }
 573
 574 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 575                                 enum mlxfw_fsm_state *fsm_state,
 576                                 enum mlxfw_fsm_state_err *fsm_state_err)
 577 {
 578         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 579                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 580         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 581         u8 control_state, error_code;
 582         int err;
 583
 584         err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
 585         if (err)
 586                 return err;
 587
 588         *fsm_state = control_state;
 589         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 590                                MLXFW_FSM_STATE_ERR_MAX);
 591         return 0;
 592 }
 593
 594 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 595 {
 596         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 597                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 598         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 599
 600         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
 601 }
 602
 603 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 604 {
 605         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 606                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 607         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 608
 609         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 610                          fwhandle, 0);
 611 }
 612
 613 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
 614         .component_query        = mlx5_component_query,
 615         .fsm_lock               = mlx5_fsm_lock,
 616         .fsm_component_update   = mlx5_fsm_component_update,
 617         .fsm_block_download     = mlx5_fsm_block_download,
 618         .fsm_component_verify   = mlx5_fsm_component_verify,
 619         .fsm_activate           = mlx5_fsm_activate,
 620         .fsm_query_state        = mlx5_fsm_query_state,
 621         .fsm_cancel             = mlx5_fsm_cancel,
 622         .fsm_release            = mlx5_fsm_release
 623 };
 624
 625 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
 626                         const struct firmware *firmware,
 627                         struct netlink_ext_ack *extack)
 628 {
 629         struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
 630                 .mlxfw_dev = {
 631                         .ops = &mlx5_mlxfw_dev_ops,
 632                         .psid = dev->board_id,
 633                         .psid_size = strlen(dev->board_id),
 634                 },
 635                 .mlx5_core_dev = dev
 636         };
 637
 638         if (!MLX5_CAP_GEN(dev, mcam_reg)  ||
 639             !MLX5_CAP_MCAM_REG(dev, mcqi) ||
 640             !MLX5_CAP_MCAM_REG(dev, mcc)  ||
 641             !MLX5_CAP_MCAM_REG(dev, mcda)) {
 642                 pr_info("%s flashing isn't supported by the running FW\n", __func__);
 643                 return -EOPNOTSUPP;
 644         }
 645
 646         return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
 647                                     firmware, extack);
 648 }
 649
 650 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
 651                                        u16 component_index, bool read_pending,
 652                                        u32 *mcqi_version_out)
 653 {
 654         return mlx5_reg_mcqi_query(dev, component_index, read_pending,
 655                                    MCQI_INFO_TYPE_VERSION,
 656                                    MLX5_ST_SZ_BYTES(mcqi_version),
 657                                    mcqi_version_out);
 658 }
 659
 660 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
 661                                u16 component_index)
 662 {
 663         u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
 664         u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
 665         int err;
 666
 667         memset(out, 0, out_sz);
 668
 669         MLX5_SET(mcqs_reg, in, component_index, component_index);
 670
 671         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 672                                    out_sz, MLX5_REG_MCQS, 0, 0);
 673         return err;
 674 }
 675
 676 /* scans component index sequentially, to find the boot img index */
 677 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
 678 {
 679         u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
 680         u16 identifier, component_idx = 0;
 681         bool quit;
 682         int err;
 683
 684         do {
 685                 err = mlx5_reg_mcqs_query(dev, out, component_idx);
 686                 if (err)
 687                         return err;
 688
 689                 identifier = MLX5_GET(mcqs_reg, out, identifier);
 690                 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
 691                 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
 692         } while (!quit && ++component_idx);
 693
 694         if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
 695                 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
 696                                component_idx);
 697                 return -EOPNOTSUPP;
 698         }
 699
 700         return component_idx;
 701 }
 702
 703 static int
 704 mlx5_fw_image_pending(struct mlx5_core_dev *dev,
 705                       int component_index,
 706                       bool *pending_version_exists)
 707 {
 708         u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
 709         u8 component_update_state;
 710         int err;
 711
 712         err = mlx5_reg_mcqs_query(dev, out, component_index);
 713         if (err)
 714                 return err;
 715
 716         component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
 717
 718         if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
 719                 *pending_version_exists = false;
 720         } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
 721                 *pending_version_exists = true;
 722         } else {
 723                 mlx5_core_warn(dev,
 724                                "mcqs: can't read pending fw version while fw state is %d\n",
 725                                component_update_state);
 726                 return -ENODATA;
 727         }
 728         return 0;
 729 }
 730
 731 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
 732                           u32 *running_ver, u32 *pending_ver)
 733 {
 734         u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
 735         bool pending_version_exists;
 736         int component_index;
 737         int err;
 738
 739         if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
 740             !MLX5_CAP_MCAM_REG(dev, mcqs)) {
 741                 mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
 742                 return -EOPNOTSUPP;
 743         }
 744
 745         component_index = mlx5_get_boot_img_component_index(dev);
 746         if (component_index < 0)
 747                 return component_index;
 748
 749         err = mlx5_reg_mcqi_version_query(dev, component_index,
 750                                           MCQI_FW_RUNNING_VERSION,
 751                                           reg_mcqi_version);
 752         if (err)
 753                 return err;
 754
 755         *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
 756
 757         err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
 758         if (err)
 759                 return err;
 760
 761         if (!pending_version_exists) {
 762                 *pending_ver = 0;
 763                 return 0;
 764         }
 765
 766         err = mlx5_reg_mcqi_version_query(dev, component_index,
 767                                           MCQI_FW_STORED_VERSION,
 768                                           reg_mcqi_version);
 769         if (err)
 770                 return err;
 771
 772         *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
 773
 774         return 0;
 775 }