2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __MLX5_CORE_H__
34 #define __MLX5_CORE_H__
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/if_link.h>
40 #include <linux/firmware.h>
41 #include <linux/ptp_clock_kernel.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/fs.h>
45 #define DRIVER_NAME "mlx5_core"
46 #define DRIVER_VERSION "5.0-0"
48 extern uint mlx5_core_debug_mask;
50 #define mlx5_core_dbg(__dev, format, ...) \
51 pr_debug("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
52 __func__, __LINE__, current->pid, \
55 #define mlx5_core_dbg_once(__dev, format, ...) \
56 pr_debug_once("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
57 __func__, __LINE__, current->pid, \
60 #define mlx5_core_dbg_mask(__dev, mask, format, ...) \
62 if ((mask) & mlx5_core_debug_mask) \
63 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
66 #define mlx5_core_err(__dev, format, ...) \
67 pr_err("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
68 __func__, __LINE__, current->pid, \
71 #define mlx5_core_err_rl(__dev, format, ...) \
72 pr_err_ratelimited("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
73 __func__, __LINE__, current->pid, \
76 #define mlx5_core_warn(__dev, format, ...) \
77 pr_warn("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
78 __func__, __LINE__, current->pid, \
81 #define mlx5_core_warn_once(__dev, format, ...) \
82 pr_warn_once("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
83 __func__, __LINE__, current->pid, \
86 #define mlx5_core_warn_rl(__dev, format, ...) \
87 pr_warn_ratelimited("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
88 __func__, __LINE__, current->pid, \
91 #define mlx5_core_info(__dev, format, ...) \
92 pr_info("%s " format, (__dev)->priv.name, ##__VA_ARGS__)
94 #define mlx5_core_info_rl(__dev, format, ...) \
95 pr_info_ratelimited("%s:%s:%d:(pid %d): " format, (__dev)->priv.name, \
96 __func__, __LINE__, current->pid, \
100 MLX5_CMD_DATA, /* print command payload only */
101 MLX5_CMD_TIME, /* print command execution time */
105 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
106 MLX5_DRIVER_SYND = 0xbadd00de,
109 int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
110 int mlx5_query_board_id(struct mlx5_core_dev *dev);
111 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
112 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
113 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
114 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
115 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
116 void mlx5_disable_device(struct mlx5_core_dev *dev);
117 void mlx5_recover_device(struct mlx5_core_dev *dev);
118 int mlx5_sriov_init(struct mlx5_core_dev *dev);
119 void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
120 int mlx5_sriov_attach(struct mlx5_core_dev *dev);
121 void mlx5_sriov_detach(struct mlx5_core_dev *dev);
122 int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
123 bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev);
124 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
125 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
126 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
127 void *context, u32 *element_id);
128 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
129 void *context, u32 element_id,
131 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
133 int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
134 u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
135 struct ptp_system_timestamp *sts);
137 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
138 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
139 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
141 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
142 u8 access_reg_group);
143 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
144 u8 access_reg_group);
145 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
146 u8 feature_group, u8 access_reg_group);
148 void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
149 void mlx5_lag_remove(struct mlx5_core_dev *dev);
151 int mlx5_events_init(struct mlx5_core_dev *dev);
152 void mlx5_events_cleanup(struct mlx5_core_dev *dev);
153 void mlx5_events_start(struct mlx5_core_dev *dev);
154 void mlx5_events_stop(struct mlx5_core_dev *dev);
156 void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
157 void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
158 void mlx5_attach_device(struct mlx5_core_dev *dev);
159 void mlx5_detach_device(struct mlx5_core_dev *dev);
160 bool mlx5_device_registered(struct mlx5_core_dev *dev);
161 int mlx5_register_device(struct mlx5_core_dev *dev);
162 void mlx5_unregister_device(struct mlx5_core_dev *dev);
163 void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
164 void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
165 struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
166 void mlx5_dev_list_lock(void);
167 void mlx5_dev_list_unlock(void);
168 int mlx5_dev_list_trylock(void);
170 bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv);
172 int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
173 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
174 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
175 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
177 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
178 MLX5_CAP_GEN((mdev), pps_modify) && \
179 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
180 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
182 int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw);
184 void mlx5e_init(void);
185 void mlx5e_cleanup(void);
187 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
189 /* LACP owner conditions:
190 * 1) Function is physical.
191 * 2) LAG is supported by FW.
192 * 3) LAG is managed by driver (currently the only option).
194 return MLX5_CAP_GEN(dev, vport_group_manager) &&
195 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
196 MLX5_CAP_GEN(dev, lag_master);
199 void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol);
200 void mlx5_lag_update(struct mlx5_core_dev *dev);
203 MLX5_NIC_IFC_FULL = 0,
204 MLX5_NIC_IFC_DISABLED = 1,
205 MLX5_NIC_IFC_NO_DRAM_NIC = 2,
206 MLX5_NIC_IFC_INVALID = 3
209 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
210 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
211 #endif /* __MLX5_CORE_H__ */