1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
7 #include <linux/kernel.h>
8 #include <linux/string.h>
9 #include <linux/bitops.h>
10 #include <linux/if_vlan.h>
15 struct mlxsw_reg_info {
21 #define MLXSW_REG_DEFINE(_name, _id, _len) \
22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
28 #define MLXSW_REG(type) (&mlxsw_reg_##type)
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
34 * This register is used for configuration of the switch capabilities.
36 #define MLXSW_REG_SGCR_ID 0x2000
37 #define MLXSW_REG_SGCR_LEN 0x10
39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
42 * Link Local Broadcast (Default=0)
43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
44 * packets and ignore the IGMP snooping entries.
47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
57 * The SPAD register configures the switch physical MAC address.
59 #define MLXSW_REG_SPAD_ID 0x2002
60 #define MLXSW_REG_SPAD_LEN 0x10
62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
65 * Base MAC address for the switch partitions.
66 * Per switch partition MAC address is equal to:
70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
72 /* SMID - Switch Multicast ID
73 * --------------------------
74 * The MID record maps from a MID (Multicast ID), which is a unique identifier
75 * of the multicast group within the stacking domain, into a list of local
76 * ports into which the packet is replicated.
78 #define MLXSW_REG_SMID_ID 0x2007
79 #define MLXSW_REG_SMID_LEN 0x240
81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
84 * Switch partition ID.
87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
90 * Multicast identifier - global identifier that represents the multicast group
94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
97 * Local port memebership (1 bit per port).
100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
102 /* reg_smid_port_mask
103 * Local port mask (1 bit per port).
106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
111 MLXSW_REG_ZERO(smid, payload);
112 mlxsw_reg_smid_swid_set(payload, 0);
113 mlxsw_reg_smid_mid_set(payload, mid);
114 mlxsw_reg_smid_port_set(payload, port, set);
115 mlxsw_reg_smid_port_mask_set(payload, port, 1);
118 /* SSPR - Switch System Port Record Register
119 * -----------------------------------------
120 * Configures the system port to local port mapping.
122 #define MLXSW_REG_SSPR_ID 0x2008
123 #define MLXSW_REG_SSPR_LEN 0x8
125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
128 * Master - if set, then the record describes the master system port.
129 * This is needed in case a local port is mapped into several system ports
130 * (for multipathing). That number will be reported as the source system
131 * port when packets are forwarded to the CPU. Only one master port is allowed
134 * Note: Must be set for Spectrum.
137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
139 /* reg_sspr_local_port
144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
147 * Virtual port within the physical port.
148 * Should be set to 0 when virtual ports are not enabled on the port.
152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
154 /* reg_sspr_system_port
155 * Unique identifier within the stacking domain that represents all the ports
156 * that are available in the system (external ports).
158 * Currently, only single-ASIC configurations are supported, so we default to
159 * 1:1 mapping between system ports and local ports.
162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
173 /* SFDAT - Switch Filtering Database Aging Time
174 * --------------------------------------------
175 * Controls the Switch aging time. Aging time is able to be set per Switch
178 #define MLXSW_REG_SFDAT_ID 0x2009
179 #define MLXSW_REG_SFDAT_LEN 0x8
181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
184 * Switch partition ID.
187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
189 /* reg_sfdat_age_time
190 * Aging time in seconds
192 * Max - 1,000,000 seconds
193 * Default is 300 seconds.
196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
200 MLXSW_REG_ZERO(sfdat, payload);
201 mlxsw_reg_sfdat_swid_set(payload, 0);
202 mlxsw_reg_sfdat_age_time_set(payload, age_time);
205 /* SFD - Switch Filtering Database
206 * -------------------------------
207 * The following register defines the access to the filtering database.
208 * The register supports querying, adding, removing and modifying the database.
209 * The access is optimized for bulk updates in which case more than one
210 * FDB record is present in the same command.
212 #define MLXSW_REG_SFD_ID 0x200A
213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
222 * Switch partition ID for queries. Reserved on Write.
225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
227 enum mlxsw_reg_sfd_op {
228 /* Dump entire FDB a (process according to record_locator) */
229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230 /* Query records by {MAC, VID/FID} value */
231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232 /* Query and clear activity. Query records by {MAC, VID/FID} value */
233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234 /* Test. Response indicates if each of the records could be
237 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238 /* Add/modify. Aged-out records cannot be added. This command removes
239 * the learning notification of the {MAC, VID/FID}. Response includes
240 * the entries that were added to the FDB.
242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243 /* Remove record by {MAC, VID/FID}. This command also removes
244 * the learning notification and aged-out notifications
245 * of the {MAC, VID/FID}. The response provides current (pre-removal)
246 * entries as non-aged-out.
248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249 /* Remove learned notification by {MAC, VID/FID}. The response provides
250 * the removed learning notification.
252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
261 /* reg_sfd_record_locator
262 * Used for querying the FDB. Use record_locator=0 to initiate the
263 * query. When a record is returned, a new record_locator is
264 * returned to be used in the subsequent query.
265 * Reserved for database update.
268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
271 * Request: Number of records to read/add/modify/remove
272 * Response: Number of records read/added/replaced/removed
273 * See above description for more details.
277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
282 MLXSW_REG_ZERO(sfd, payload);
283 mlxsw_reg_sfd_op_set(payload, op);
284 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
288 * Switch partition ID.
291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 MLXSW_REG_SFD_REC_LEN, 0x00, false);
294 enum mlxsw_reg_sfd_rec_type {
295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 MLXSW_REG_SFD_REC_LEN, 0x00, false);
308 enum mlxsw_reg_sfd_rec_policy {
309 /* Replacement disabled, aging disabled. */
310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311 /* (mlag remote): Replacement enabled, aging disabled,
312 * learning notification enabled on this port.
314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315 /* (ingress device): Replacement enabled, aging enabled. */
316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
319 /* reg_sfd_rec_policy
323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 MLXSW_REG_SFD_REC_LEN, 0x00, false);
327 * Activity. Set for new static entries. Set for static entries if a frame SMAC
328 * lookup hits on the entry.
329 * To clear the a bit, use "query and clear activity" op.
332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 MLXSW_REG_SFD_REC_LEN, 0x00, false);
339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 MLXSW_REG_SFD_REC_LEN, 0x02);
342 enum mlxsw_reg_sfd_rec_action {
344 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345 /* forward and trap, trap_id is FDB_TRAP */
346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347 /* trap and do not forward, trap_id is FDB_TRAP */
348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349 /* forward to IP router */
350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
354 /* reg_sfd_rec_action
355 * Action to apply on the packet.
356 * Note: Dynamic entries can only be configured with NOP action.
359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
362 /* reg_sfd_uc_sub_port
363 * VEPA channel on local port.
364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
365 * VEPA is not enabled.
368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 MLXSW_REG_SFD_REC_LEN, 0x08, false);
371 /* reg_sfd_uc_fid_vid
372 * Filtering ID or VLAN ID
373 * For SwitchX and SwitchX-2:
374 * - Dynamic entries (policy 2,3) use FID
375 * - Static entries (policy 0) use VID
376 * - When independent learning is configured, VID=FID
377 * For Spectrum: use FID for both Dynamic and Static entries.
378 * VID should not be used.
381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 MLXSW_REG_SFD_REC_LEN, 0x08, false);
384 /* reg_sfd_uc_system_port
385 * Unique port identifier for the final destination of the packet.
388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 enum mlxsw_reg_sfd_rec_type rec_type,
394 enum mlxsw_reg_sfd_rec_action action)
396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
398 if (rec_index >= num_rec)
399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 char *mac, u16 *p_fid_vid,
424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
429 /* reg_sfd_uc_lag_sub_port
431 * Must be 0 if multichannel VEPA is not enabled.
434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 MLXSW_REG_SFD_REC_LEN, 0x08, false);
437 /* reg_sfd_uc_lag_fid_vid
438 * Filtering ID or VLAN ID
439 * For SwitchX and SwitchX-2:
440 * - Dynamic entries (policy 2,3) use FID
441 * - Static entries (policy 0) use VID
442 * - When independent learning is configured, VID=FID
443 * For Spectrum: use FID for both Dynamic and Static entries.
444 * VID should not be used.
447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 MLXSW_REG_SFD_REC_LEN, 0x08, false);
450 /* reg_sfd_uc_lag_lag_vid
451 * Indicates VID in case of vFIDs. Reserved for FIDs.
454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
457 /* reg_sfd_uc_lag_lag_id
458 * LAG Identifier - pointer into the LAG descriptor table.
461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 enum mlxsw_reg_sfd_rec_policy policy,
467 const char *mac, u16 fid_vid,
468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
471 mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 char *mac, u16 *p_vid,
485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
492 * Multicast port group index - index into the port group table.
493 * Value 0x1FFF indicates the pgi should point to the MID entry.
494 * For Spectrum this value must be set to 0x1FFF
497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 MLXSW_REG_SFD_REC_LEN, 0x08, false);
500 /* reg_sfd_mc_fid_vid
502 * Filtering ID or VLAN ID
505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 MLXSW_REG_SFD_REC_LEN, 0x08, false);
510 * Multicast identifier - global identifier that represents the multicast
511 * group across all devices.
514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 const char *mac, u16 fid_vid,
520 enum mlxsw_reg_sfd_rec_action action, u16 mid)
522 mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
529 /* reg_sfd_uc_tunnel_uip_msb
530 * When protocol is IPv4, the most significant byte of the underlay IPv4
532 * When protocol is IPv6, reserved.
535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
538 /* reg_sfd_uc_tunnel_fid
542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 MLXSW_REG_SFD_REC_LEN, 0x08, false);
545 enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
550 /* reg_sfd_uc_tunnel_protocol
554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
557 /* reg_sfd_uc_tunnel_uip_lsb
558 * When protocol is IPv4, the least significant bytes of the underlay
559 * IPv4 destination IP.
560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP
561 * which is configured by RIPS.
564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 enum mlxsw_reg_sfd_rec_policy policy,
570 const char *mac, u16 fid,
571 enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
574 mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
584 /* SFN - Switch FDB Notification Register
585 * -------------------------------------------
586 * The switch provides notifications on newly learned FDB entries and
587 * aged out entries. The notifications can be polled by software.
589 #define MLXSW_REG_SFN_ID 0x200B
590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
599 * Switch partition ID.
602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
605 * Forces the current session to end.
608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
611 * Request: Number of learned notifications and aged-out notification
613 * Response: Number of notification records returned (must be smaller
614 * than or equal to the value requested)
618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
620 static inline void mlxsw_reg_sfn_pack(char *payload)
622 MLXSW_REG_ZERO(sfn, payload);
623 mlxsw_reg_sfn_swid_set(payload, 0);
624 mlxsw_reg_sfn_end_set(payload, 1);
625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
629 * Switch partition ID.
632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
633 MLXSW_REG_SFN_REC_LEN, 0x00, false);
635 enum mlxsw_reg_sfn_rec_type {
636 /* MAC addresses learned on a regular port. */
637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
638 /* MAC addresses learned on a LAG port. */
639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
640 /* Aged-out MAC address on a regular port. */
641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
642 /* Aged-out MAC address on a LAG port. */
643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
644 /* Learned unicast tunnel record. */
645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
646 /* Aged-out unicast tunnel record. */
647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
651 * Notification record type.
654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
655 MLXSW_REG_SFN_REC_LEN, 0x00, false);
661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
662 MLXSW_REG_SFN_REC_LEN, 0x02);
664 /* reg_sfn_mac_sub_port
665 * VEPA channel on the local port.
666 * 0 if multichannel VEPA is not enabled.
669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
670 MLXSW_REG_SFN_REC_LEN, 0x08, false);
673 * Filtering identifier.
676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
677 MLXSW_REG_SFN_REC_LEN, 0x08, false);
679 /* reg_sfn_mac_system_port
680 * Unique port identifier for the final destination of the packet.
683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
684 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
687 char *mac, u16 *p_vid,
690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
695 /* reg_sfn_mac_lag_lag_id
696 * LAG ID (pointer into the LAG descriptor table).
699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
700 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
703 char *mac, u16 *p_vid,
706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
711 /* reg_sfn_uc_tunnel_uip_msb
712 * When protocol is IPv4, the most significant byte of the underlay IPv4
713 * address of the remote VTEP.
714 * When protocol is IPv6, reserved.
717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
720 enum mlxsw_reg_sfn_uc_tunnel_protocol {
721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
725 /* reg_sfn_uc_tunnel_protocol
729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
732 /* reg_sfn_uc_tunnel_uip_lsb
733 * When protocol is IPv4, the least significant bytes of the underlay
734 * IPv4 address of the remote VTEP.
735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
741 enum mlxsw_reg_sfn_tunnel_port {
742 MLXSW_REG_SFN_TUNNEL_PORT_NVE,
743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
748 /* reg_sfn_uc_tunnel_port
750 * Reserved on Spectrum.
753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
754 MLXSW_REG_SFN_REC_LEN, 0x10, false);
757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
758 u16 *p_fid, u32 *p_uip,
759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
761 u32 uip_msb, uip_lsb;
763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
767 *p_uip = uip_msb << 24 | uip_lsb;
768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
771 /* SPMS - Switch Port MSTP/RSTP State Register
772 * -------------------------------------------
773 * Configures the spanning tree state of a physical port.
775 #define MLXSW_REG_SPMS_ID 0x200D
776 #define MLXSW_REG_SPMS_LEN 0x404
778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
780 /* reg_spms_local_port
784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
786 enum mlxsw_reg_spms_state {
787 MLXSW_REG_SPMS_STATE_NO_CHANGE,
788 MLXSW_REG_SPMS_STATE_DISCARDING,
789 MLXSW_REG_SPMS_STATE_LEARNING,
790 MLXSW_REG_SPMS_STATE_FORWARDING,
794 * Spanning tree state of each VLAN ID (VID) of the local port.
795 * 0 - Do not change spanning tree state (used only when writing).
796 * 1 - Discarding. No learning or forwarding to/from this port (default).
797 * 2 - Learning. Port is learning, but not forwarding.
798 * 3 - Forwarding. Port is learning and forwarding.
801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
805 MLXSW_REG_ZERO(spms, payload);
806 mlxsw_reg_spms_local_port_set(payload, local_port);
809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
810 enum mlxsw_reg_spms_state state)
812 mlxsw_reg_spms_state_set(payload, vid, state);
815 /* SPVID - Switch Port VID
816 * -----------------------
817 * The switch port VID configures the default VID for a port.
819 #define MLXSW_REG_SPVID_ID 0x200E
820 #define MLXSW_REG_SPVID_LEN 0x08
822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
824 /* reg_spvid_local_port
828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
830 /* reg_spvid_sub_port
831 * Virtual port within the physical port.
832 * Should be set to 0 when virtual ports are not enabled on the port.
835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
845 MLXSW_REG_ZERO(spvid, payload);
846 mlxsw_reg_spvid_local_port_set(payload, local_port);
847 mlxsw_reg_spvid_pvid_set(payload, pvid);
850 /* SPVM - Switch Port VLAN Membership
851 * ----------------------------------
852 * The Switch Port VLAN Membership register configures the VLAN membership
853 * of a port in a VLAN denoted by VID. VLAN membership is managed per
854 * virtual port. The register can be used to add and remove VID(s) from a port.
856 #define MLXSW_REG_SPVM_ID 0x200F
857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255
860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
866 * Priority tagged. If this bit is set, packets forwarded to the port with
867 * untagged VLAN membership (u bit is set) will be tagged with priority tag
871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
875 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
880 /* reg_spvm_local_port
884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
887 * Virtual port within the physical port.
888 * Should be set to 0 when virtual ports are not enabled on the port.
891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
894 * Number of records to update. Each record contains: i, e, u, vid.
897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
900 * Ingress membership in VLAN ID.
903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
904 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
905 MLXSW_REG_SPVM_REC_LEN, 0, false);
908 * Egress membership in VLAN ID.
911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
912 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
913 MLXSW_REG_SPVM_REC_LEN, 0, false);
916 * Untagged - port is an untagged member - egress transmission uses untagged
920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
921 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
922 MLXSW_REG_SPVM_REC_LEN, 0, false);
925 * Egress membership in VLAN ID.
928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
929 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
930 MLXSW_REG_SPVM_REC_LEN, 0, false);
932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
933 u16 vid_begin, u16 vid_end,
934 bool is_member, bool untagged)
936 int size = vid_end - vid_begin + 1;
939 MLXSW_REG_ZERO(spvm, payload);
940 mlxsw_reg_spvm_local_port_set(payload, local_port);
941 mlxsw_reg_spvm_num_rec_set(payload, size);
943 for (i = 0; i < size; i++) {
944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
951 /* SPAFT - Switch Port Acceptable Frame Types
952 * ------------------------------------------
953 * The Switch Port Acceptable Frame Types register configures the frame
954 * admittance of the port.
956 #define MLXSW_REG_SPAFT_ID 0x2010
957 #define MLXSW_REG_SPAFT_LEN 0x08
959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
961 /* reg_spaft_local_port
965 * Note: CPU port is not supported (all tag types are allowed).
967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
969 /* reg_spaft_sub_port
970 * Virtual port within the physical port.
971 * Should be set to 0 when virtual ports are not enabled on the port.
974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
976 /* reg_spaft_allow_untagged
977 * When set, untagged frames on the ingress are allowed (default).
980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
982 /* reg_spaft_allow_prio_tagged
983 * When set, priority tagged frames on the ingress are allowed (default).
986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
988 /* reg_spaft_allow_tagged
989 * When set, tagged frames on the ingress are allowed (default).
992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
997 MLXSW_REG_ZERO(spaft, payload);
998 mlxsw_reg_spaft_local_port_set(payload, local_port);
999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1001 mlxsw_reg_spaft_allow_tagged_set(payload, true);
1004 /* SFGC - Switch Flooding Group Configuration
1005 * ------------------------------------------
1006 * The following register controls the association of flooding tables and MIDs
1007 * to packet types used for flooding.
1009 #define MLXSW_REG_SFGC_ID 0x2011
1010 #define MLXSW_REG_SFGC_LEN 0x10
1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1014 enum mlxsw_reg_sfgc_type {
1015 MLXSW_REG_SFGC_TYPE_BROADCAST,
1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1019 MLXSW_REG_SFGC_TYPE_RESERVED,
1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1023 MLXSW_REG_SFGC_TYPE_MAX,
1027 * The traffic type to reach the flooding table.
1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1032 enum mlxsw_reg_sfgc_bridge_type {
1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1037 /* reg_sfgc_bridge_type
1040 * Note: SwitchX-2 only supports 802.1Q mode.
1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1044 enum mlxsw_flood_table_type {
1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1052 /* reg_sfgc_table_type
1053 * See mlxsw_flood_table_type
1056 * Note: FID offset and FID types are not supported in SwitchX-2.
1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1060 /* reg_sfgc_flood_table
1061 * Flooding table index to associate with the specific type on the specific
1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1068 * The multicast ID for the swid. Not supported for Spectrum
1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1073 /* reg_sfgc_counter_set_type
1074 * Counter Set Type for flow counters.
1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1079 /* reg_sfgc_counter_index
1080 * Counter Index for flow counters.
1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1087 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1088 enum mlxsw_flood_table_type table_type,
1089 unsigned int flood_table)
1091 MLXSW_REG_ZERO(sfgc, payload);
1092 mlxsw_reg_sfgc_type_set(payload, type);
1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1094 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1099 /* SFTR - Switch Flooding Table Register
1100 * -------------------------------------
1101 * The switch flooding table is used for flooding packet replication. The table
1102 * defines a bit mask of ports for packet replication.
1104 #define MLXSW_REG_SFTR_ID 0x2012
1105 #define MLXSW_REG_SFTR_LEN 0x420
1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1110 * Switch partition ID with which to associate the port.
1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1115 /* reg_sftr_flood_table
1116 * Flooding table index to associate with the specific type on the specific
1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1123 * Index. Used as an index into the Flooding Table in case the table is
1124 * configured to use VID / FID or FID Offset.
1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1129 /* reg_sftr_table_type
1130 * See mlxsw_flood_table_type
1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1136 * Range of entries to update
1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1142 * Local port membership (1 bit per port).
1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1147 /* reg_sftr_cpu_port_mask
1148 * CPU port mask (1 bit per port).
1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1153 static inline void mlxsw_reg_sftr_pack(char *payload,
1154 unsigned int flood_table,
1156 enum mlxsw_flood_table_type table_type,
1157 unsigned int range, u8 port, bool set)
1159 MLXSW_REG_ZERO(sftr, payload);
1160 mlxsw_reg_sftr_swid_set(payload, 0);
1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1162 mlxsw_reg_sftr_index_set(payload, index);
1163 mlxsw_reg_sftr_table_type_set(payload, table_type);
1164 mlxsw_reg_sftr_range_set(payload, range);
1165 mlxsw_reg_sftr_port_set(payload, port, set);
1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1169 /* SFDF - Switch Filtering DB Flush
1170 * --------------------------------
1171 * The switch filtering DB flush register is used to flush the FDB.
1172 * Note that FDB notifications are flushed as well.
1174 #define MLXSW_REG_SFDF_ID 0x2013
1175 #define MLXSW_REG_SFDF_LEN 0x14
1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1180 * Switch partition ID.
1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1185 enum mlxsw_reg_sfdf_flush_type {
1186 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1187 MLXSW_REG_SFDF_FLUSH_PER_FID,
1188 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1190 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1192 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1196 /* reg_sfdf_flush_type
1198 * 0 - All SWID dynamic entries are flushed.
1199 * 1 - All FID dynamic entries are flushed.
1200 * 2 - All dynamic entries pointing to port are flushed.
1201 * 3 - All FID dynamic entries pointing to port are flushed.
1202 * 4 - All dynamic entries pointing to LAG are flushed.
1203 * 5 - All FID dynamic entries pointing to LAG are flushed.
1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1212 /* reg_sfdf_flush_static
1214 * 0 - Flush only dynamic entries.
1215 * 1 - Flush both dynamic and static entries.
1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1220 static inline void mlxsw_reg_sfdf_pack(char *payload,
1221 enum mlxsw_reg_sfdf_flush_type type)
1223 MLXSW_REG_ZERO(sfdf, payload);
1224 mlxsw_reg_sfdf_flush_type_set(payload, type);
1225 mlxsw_reg_sfdf_flush_static_set(payload, true);
1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1234 /* reg_sfdf_system_port
1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1240 /* reg_sfdf_port_fid_system_port
1241 * Port to flush, pointed to by FID.
1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1252 /* reg_sfdf_lag_fid_lag_id
1253 * LAG ID to flush, pointed to by FID.
1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1258 /* SLDR - Switch LAG Descriptor Register
1259 * -----------------------------------------
1260 * The switch LAG descriptor register is populated by LAG descriptors.
1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1264 #define MLXSW_REG_SLDR_ID 0x2014
1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1269 enum mlxsw_reg_sldr_op {
1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1271 MLXSW_REG_SLDR_OP_LAG_CREATE,
1272 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1273 /* Ports that appear in the list have the Distributor enabled */
1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1275 /* Removes ports from the disributor list */
1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1286 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1293 MLXSW_REG_ZERO(sldr, payload);
1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1300 MLXSW_REG_ZERO(sldr, payload);
1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1305 /* reg_sldr_num_ports
1306 * The number of member ports of the LAG.
1307 * Reserved for Create / Destroy operations
1308 * For Add / Remove operations - indicates the number of ports in the list.
1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1313 /* reg_sldr_system_port
1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1322 MLXSW_REG_ZERO(sldr, payload);
1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1325 mlxsw_reg_sldr_num_ports_set(payload, 1);
1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1332 MLXSW_REG_ZERO(sldr, payload);
1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1335 mlxsw_reg_sldr_num_ports_set(payload, 1);
1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1339 /* SLCR - Switch LAG Configuration 2 Register
1340 * -------------------------------------------
1341 * The Switch LAG Configuration register is used for configuring the
1342 * LAG properties of the switch.
1344 #define MLXSW_REG_SLCR_ID 0x2015
1345 #define MLXSW_REG_SLCR_LEN 0x10
1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1349 enum mlxsw_reg_slcr_pp {
1350 /* Global Configuration (for all ports) */
1351 MLXSW_REG_SLCR_PP_GLOBAL,
1352 /* Per port configuration, based on local_port field */
1353 MLXSW_REG_SLCR_PP_PER_PORT,
1357 * Per Port Configuration
1358 * Note: Reading at Global mode results in reading port 1 configuration.
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1363 /* reg_slcr_local_port
1365 * Supported from CPU port
1366 * Not supported from router port
1367 * Reserved when pp = Global Configuration
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1372 enum mlxsw_reg_slcr_type {
1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1374 MLXSW_REG_SLCR_TYPE_XOR,
1375 MLXSW_REG_SLCR_TYPE_RANDOM,
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1386 /* SMAC - for IPv4 and IPv6 packets */
1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1388 /* SMAC - for non-IP packets */
1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1393 /* DMAC - for IPv4 and IPv6 packets */
1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1395 /* DMAC - for non-IP packets */
1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1400 /* Ethertype - for IPv4 and IPv6 packets */
1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1402 /* Ethertype - for non-IP packets */
1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1407 /* VLAN ID - for IPv4 and IPv6 packets */
1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1409 /* VLAN ID - for non-IP packets */
1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1414 /* Source IP address (can be IPv4 or IPv6) */
1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1416 /* Destination IP address (can be IPv4 or IPv6) */
1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1418 /* TCP/UDP source port */
1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1420 /* TCP/UDP destination port*/
1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1422 /* IPv4 Protocol/IPv6 Next Header */
1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1424 /* IPv6 Flow label */
1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1426 /* SID - FCoE source ID */
1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1428 /* DID - FCoE destination ID */
1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1430 /* OXID - FCoE originator exchange ID */
1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1432 /* Destination QP number - for RoCE packets */
1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1435 /* reg_slcr_lag_hash
1436 * LAG hashing configuration. This is a bitmask, in which each set
1437 * bit includes the corresponding item in the LAG hash calculation.
1438 * The default lag_hash contains SMAC, DMAC, VLANID and
1439 * Ethertype (for all packet types).
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1445 * LAG seed value. The seed is the same for all ports.
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1452 MLXSW_REG_ZERO(slcr, payload);
1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1456 mlxsw_reg_slcr_seed_set(payload, seed);
1459 /* SLCOR - Switch LAG Collector Register
1460 * -------------------------------------
1461 * The Switch LAG Collector register controls the Local Port membership
1462 * in a LAG and enablement of the collector.
1464 #define MLXSW_REG_SLCOR_ID 0x2016
1465 #define MLXSW_REG_SLCOR_LEN 0x10
1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1469 enum mlxsw_reg_slcor_col {
1470 /* Port is added with collector disabled */
1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1478 * Collector configuration
1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1483 /* reg_slcor_local_port
1485 * Not supported for CPU port
1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1491 * LAG Identifier. Index into the LAG descriptor table.
1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1496 /* reg_slcor_port_index
1497 * Port index in the LAG list. Only valid on Add Port to LAG col.
1498 * Valid range is from 0 to cap_max_lag_members-1
1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1503 static inline void mlxsw_reg_slcor_pack(char *payload,
1504 u8 local_port, u16 lag_id,
1505 enum mlxsw_reg_slcor_col col)
1507 MLXSW_REG_ZERO(slcor, payload);
1508 mlxsw_reg_slcor_col_set(payload, col);
1509 mlxsw_reg_slcor_local_port_set(payload, local_port);
1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1514 u8 local_port, u16 lag_id,
1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1519 mlxsw_reg_slcor_port_index_set(payload, port_index);
1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1523 u8 local_port, u16 lag_id)
1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1530 u8 local_port, u16 lag_id)
1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1537 u8 local_port, u16 lag_id)
1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1543 /* SPMLR - Switch Port MAC Learning Register
1544 * -----------------------------------------
1545 * Controls the Switch MAC learning policy per port.
1547 #define MLXSW_REG_SPMLR_ID 0x2018
1548 #define MLXSW_REG_SPMLR_LEN 0x8
1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1552 /* reg_spmlr_local_port
1553 * Local port number.
1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1558 /* reg_spmlr_sub_port
1559 * Virtual port within the physical port.
1560 * Should be set to 0 when virtual ports are not enabled on the port.
1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1565 enum mlxsw_reg_spmlr_learn_mode {
1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1571 /* reg_spmlr_learn_mode
1572 * Learning mode on the port.
1573 * 0 - Learning disabled.
1574 * 2 - Learning enabled.
1575 * 3 - Security mode.
1577 * In security mode the switch does not learn MACs on the port, but uses the
1578 * SMAC to see if it exists on another ingress port. If so, the packet is
1579 * classified as a bad packet and is discarded unless the software registers
1580 * to receive port security error packets usign HPKT.
1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1585 enum mlxsw_reg_spmlr_learn_mode mode)
1587 MLXSW_REG_ZERO(spmlr, payload);
1588 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1589 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1593 /* SVFA - Switch VID to FID Allocation Register
1594 * --------------------------------------------
1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1596 * virtualized ports.
1598 #define MLXSW_REG_SVFA_ID 0x201C
1599 #define MLXSW_REG_SVFA_LEN 0x10
1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1604 * Switch partition ID.
1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1609 /* reg_svfa_local_port
1610 * Local port number.
1613 * Note: Reserved for 802.1Q FIDs.
1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1617 enum mlxsw_reg_svfa_mt {
1618 MLXSW_REG_SVFA_MT_VID_TO_FID,
1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1622 /* reg_svfa_mapping_table
1625 * 1 - {Port, VID} to FID
1628 * Note: Reserved for SwitchX-2.
1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1637 * Note: Reserved for SwitchX-2.
1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1653 /* reg_svfa_counter_set_type
1654 * Counter set type for flow counters.
1657 * Note: Reserved for SwitchX-2.
1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1661 /* reg_svfa_counter_index
1662 * Counter index for flow counters.
1665 * Note: Reserved for SwitchX-2.
1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1670 enum mlxsw_reg_svfa_mt mt, bool valid,
1673 MLXSW_REG_ZERO(svfa, payload);
1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1675 mlxsw_reg_svfa_swid_set(payload, 0);
1676 mlxsw_reg_svfa_local_port_set(payload, local_port);
1677 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1678 mlxsw_reg_svfa_v_set(payload, valid);
1679 mlxsw_reg_svfa_fid_set(payload, fid);
1680 mlxsw_reg_svfa_vid_set(payload, vid);
1683 /* SVPE - Switch Virtual-Port Enabling Register
1684 * --------------------------------------------
1685 * Enables port virtualization.
1687 #define MLXSW_REG_SVPE_ID 0x201E
1688 #define MLXSW_REG_SVPE_LEN 0x4
1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1692 /* reg_svpe_local_port
1696 * Note: CPU port is not supported (uses VLAN mode only).
1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1701 * Virtual port enable.
1702 * 0 - Disable, VLAN mode (VID to FID).
1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1711 MLXSW_REG_ZERO(svpe, payload);
1712 mlxsw_reg_svpe_local_port_set(payload, local_port);
1713 mlxsw_reg_svpe_vp_en_set(payload, enable);
1716 /* SFMR - Switch FID Management Register
1717 * -------------------------------------
1718 * Creates and configures FIDs.
1720 #define MLXSW_REG_SFMR_ID 0x201F
1721 #define MLXSW_REG_SFMR_LEN 0x18
1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1725 enum mlxsw_reg_sfmr_op {
1726 MLXSW_REG_SFMR_OP_CREATE_FID,
1727 MLXSW_REG_SFMR_OP_DESTROY_FID,
1732 * 0 - Create or edit FID.
1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1744 /* reg_sfmr_fid_offset
1746 * Used to point into the flooding table selected by SFGC register if
1747 * the table is of type FID-Offset. Otherwise, this field is reserved.
1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1753 * Valid Tunnel Flood Pointer.
1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1757 * Note: Reserved for 802.1Q FIDs.
1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1761 /* reg_sfmr_nve_tunnel_flood_ptr
1762 * Underlay Flooding and BC Pointer.
1763 * Used as a pointer to the first entry of the group based link lists of
1764 * flooding or BC entries (for NVE tunnels).
1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1771 * If not set, then vni is reserved.
1774 * Note: Reserved for 802.1Q FIDs.
1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1779 * Virtual Network Identifier.
1782 * Note: A given VNI can only be assigned to one FID.
1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1786 static inline void mlxsw_reg_sfmr_pack(char *payload,
1787 enum mlxsw_reg_sfmr_op op, u16 fid,
1790 MLXSW_REG_ZERO(sfmr, payload);
1791 mlxsw_reg_sfmr_op_set(payload, op);
1792 mlxsw_reg_sfmr_fid_set(payload, fid);
1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1794 mlxsw_reg_sfmr_vtfp_set(payload, false);
1795 mlxsw_reg_sfmr_vv_set(payload, false);
1798 /* SPVMLR - Switch Port VLAN MAC Learning Register
1799 * -----------------------------------------------
1800 * Controls the switch MAC learning policy per {Port, VID}.
1802 #define MLXSW_REG_SPVMLR_ID 0x2020
1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1807 MLXSW_REG_SPVMLR_REC_LEN * \
1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1812 /* reg_spvmlr_local_port
1813 * Local ingress port.
1816 * Note: CPU port is not supported.
1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1820 /* reg_spvmlr_num_rec
1821 * Number of records to update.
1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1826 /* reg_spvmlr_rec_learn_enable
1827 * 0 - Disable learning for {Port, VID}.
1828 * 1 - Enable learning for {Port, VID}.
1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1834 /* reg_spvmlr_rec_vid
1835 * VLAN ID to be added/removed from port or for querying.
1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1842 u16 vid_begin, u16 vid_end,
1845 int num_rec = vid_end - vid_begin + 1;
1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1850 MLXSW_REG_ZERO(spvmlr, payload);
1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1854 for (i = 0; i < num_rec; i++) {
1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1860 /* CWTP - Congetion WRED ECN TClass Profile
1861 * ----------------------------------------
1862 * Configures the profiles for queues of egress port and traffic class
1864 #define MLXSW_REG_CWTP_ID 0x2802
1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28
1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1867 #define MLXSW_REG_CWTP_LEN 0x40
1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1871 /* reg_cwtp_local_port
1873 * Not supported for CPU port
1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1878 /* reg_cwtp_traffic_class
1879 * Traffic Class to configure
1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1884 /* reg_cwtp_profile_min
1885 * Minimum Average Queue Size of the profile in cells.
1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1891 /* reg_cwtp_profile_percent
1892 * Percentage of WRED and ECN marking for maximum Average Queue size
1893 * Range is 0 to 100, units of integer percentage
1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1899 /* reg_cwtp_profile_max
1900 * Maximum Average Queue size of the profile in cells
1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1906 #define MLXSW_REG_CWTP_MIN_VALUE 64
1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2
1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1915 MLXSW_REG_ZERO(cwtp, payload);
1916 mlxsw_reg_cwtp_local_port_set(payload, local_port);
1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1920 mlxsw_reg_cwtp_profile_min_set(payload, i,
1921 MLXSW_REG_CWTP_MIN_VALUE);
1922 mlxsw_reg_cwtp_profile_max_set(payload, i,
1923 MLXSW_REG_CWTP_MIN_VALUE);
1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping
1941 * ---------------------------------------------------
1942 * The CWTPM register maps each egress port and traffic class to profile num.
1944 #define MLXSW_REG_CWTPM_ID 0x2803
1945 #define MLXSW_REG_CWTPM_LEN 0x44
1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1949 /* reg_cwtpm_local_port
1951 * Not supported for CPU port
1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1956 /* reg_cwtpm_traffic_class
1957 * Traffic Class to configure
1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1963 * Control enablement of WRED for traffic class:
1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1971 * Control enablement of ECN for traffic class:
1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1979 * TCP Green Profile.
1980 * Index of the profile within {port, traffic class} to use.
1981 * 0 for disabling both WRED and ECN for this type of traffic.
1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1987 * TCP Yellow Profile.
1988 * Index of the profile within {port, traffic class} to use.
1989 * 0 for disabling both WRED and ECN for this type of traffic.
1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1996 * Index of the profile within {port, traffic class} to use.
1997 * 0 for disabling both WRED and ECN for this type of traffic.
2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2003 * Non-TCP Green Profile.
2004 * Index of the profile within {port, traffic class} to use.
2005 * 0 for disabling both WRED and ECN for this type of traffic.
2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2011 * Non-TCP Yellow Profile.
2012 * Index of the profile within {port, traffic class} to use.
2013 * 0 for disabling both WRED and ECN for this type of traffic.
2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2019 * Non-TCP Red Profile.
2020 * Index of the profile within {port, traffic class} to use.
2021 * 0 for disabling both WRED and ECN for this type of traffic.
2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0
2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2029 u8 traffic_class, u8 profile,
2030 bool wred, bool ecn)
2032 MLXSW_REG_ZERO(cwtpm, payload);
2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2035 mlxsw_reg_cwtpm_ew_set(payload, wred);
2036 mlxsw_reg_cwtpm_ee_set(payload, ecn);
2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2045 /* PGCR - Policy-Engine General Configuration Register
2046 * ---------------------------------------------------
2047 * This register configures general Policy-Engine settings.
2049 #define MLXSW_REG_PGCR_ID 0x3001
2050 #define MLXSW_REG_PGCR_LEN 0x20
2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2054 /* reg_pgcr_default_action_pointer_base
2055 * Default action pointer base. Each region has a default action pointer
2056 * which is equal to default_action_pointer_base + region_id.
2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2063 MLXSW_REG_ZERO(pgcr, payload);
2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2067 /* PPBT - Policy-Engine Port Binding Table
2068 * ---------------------------------------
2069 * This register is used for configuration of the Port Binding Table.
2071 #define MLXSW_REG_PPBT_ID 0x3002
2072 #define MLXSW_REG_PPBT_LEN 0x14
2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2076 enum mlxsw_reg_pxbt_e {
2077 MLXSW_REG_PXBT_E_IACL,
2078 MLXSW_REG_PXBT_E_EACL,
2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2086 enum mlxsw_reg_pxbt_op {
2087 MLXSW_REG_PXBT_OP_BIND,
2088 MLXSW_REG_PXBT_OP_UNBIND,
2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2096 /* reg_ppbt_local_port
2097 * Local port. Not including CPU port.
2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2103 * group - When set, the binding is of an ACL group. When cleared,
2104 * the binding is of an ACL.
2105 * Must be set to 1 for Spectrum.
2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2110 /* reg_ppbt_acl_info
2111 * ACL/ACL group identifier. If the g bit is set, this field should hold
2112 * the acl_group_id, else it should hold the acl_id.
2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2118 enum mlxsw_reg_pxbt_op op,
2119 u8 local_port, u16 acl_info)
2121 MLXSW_REG_ZERO(ppbt, payload);
2122 mlxsw_reg_ppbt_e_set(payload, e);
2123 mlxsw_reg_ppbt_op_set(payload, op);
2124 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2125 mlxsw_reg_ppbt_g_set(payload, true);
2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2129 /* PACL - Policy-Engine ACL Register
2130 * ---------------------------------
2131 * This register is used for configuration of the ACL.
2133 #define MLXSW_REG_PACL_ID 0x3004
2134 #define MLXSW_REG_PACL_LEN 0x70
2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared
2140 * while the ACL is bounded to either a port, VLAN or ACL rule.
2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2146 * An identifier representing the ACL (managed by software)
2147 * Range 0 .. cap_max_acl_regions - 1
2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2154 /* reg_pacl_tcam_region_info
2155 * Opaque object that represents a TCAM region.
2156 * Obtained through PTAR register.
2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2163 bool valid, const char *tcam_region_info)
2165 MLXSW_REG_ZERO(pacl, payload);
2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2167 mlxsw_reg_pacl_v_set(payload, valid);
2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2171 /* PAGT - Policy-Engine ACL Group Table
2172 * ------------------------------------
2173 * This register is used for configuration of the ACL Group Table.
2175 #define MLXSW_REG_PAGT_ID 0x3005
2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30
2177 #define MLXSW_REG_PAGT_ACL_LEN 4
2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2185 * Number of ACLs in the group.
2186 * Size 0 invalidates a group.
2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now)
2188 * Total number of ACLs in all groups must be lower or equal
2189 * to cap_max_acl_tot_groups
2190 * Note: a group which is binded must not be invalidated
2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2195 /* reg_pagt_acl_group_id
2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing
2197 * the ACL Group identifier (managed by software).
2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2204 * 0 - This ACL is the last ACL in the multi-ACL
2205 * 1 - This ACL is part of a multi-ACL
2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2218 MLXSW_REG_ZERO(pagt, payload);
2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2223 u16 acl_id, bool multi)
2225 u8 size = mlxsw_reg_pagt_size_get(payload);
2228 mlxsw_reg_pagt_size_set(payload, index + 1);
2229 mlxsw_reg_pagt_multi_set(payload, index, multi);
2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2233 /* PTAR - Policy-Engine TCAM Allocation Register
2234 * ---------------------------------------------
2235 * This register is used for allocation of regions in the TCAM.
2236 * Note: Query method is not supported on this register.
2238 #define MLXSW_REG_PTAR_ID 0x3006
2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20
2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1
2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2247 enum mlxsw_reg_ptar_op {
2248 /* allocate a TCAM region */
2249 MLXSW_REG_PTAR_OP_ALLOC,
2250 /* resize a TCAM region */
2251 MLXSW_REG_PTAR_OP_RESIZE,
2252 /* deallocate TCAM region */
2253 MLXSW_REG_PTAR_OP_FREE,
2254 /* test allocation */
2255 MLXSW_REG_PTAR_OP_TEST,
2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2263 /* reg_ptar_action_set_type
2264 * Type of action set to be used on this region.
2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible"
2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2270 enum mlxsw_reg_ptar_key_type {
2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */
2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */
2275 /* reg_ptar_key_type
2276 * TCAM key type for the region.
2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2281 /* reg_ptar_region_size
2282 * TCAM region size. When allocating/resizing this is the requested size,
2283 * the response is the actual size. Note that actual size may be
2284 * larger than requested.
2285 * Allowed range 1 .. cap_max_rules-1
2286 * Reserved during op deallocate.
2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2291 /* reg_ptar_region_id
2293 * Range 0 .. cap_max_regions-1
2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2298 /* reg_ptar_tcam_region_info
2299 * Opaque object that represents the TCAM region.
2300 * Returned when allocating a region.
2301 * Provided by software for ACL generation and region deallocation and resize.
2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2307 /* reg_ptar_flexible_key_id
2308 * Identifier of the Flexible Key.
2309 * Only valid if key_type == "FLEX_KEY"
2310 * The key size will be rounded up to one of the following values:
2311 * 9B, 18B, 36B, 54B.
2312 * This field is reserved for in resize operation.
2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2319 enum mlxsw_reg_ptar_key_type key_type,
2320 u16 region_size, u16 region_id,
2321 const char *tcam_region_info)
2323 MLXSW_REG_ZERO(ptar, payload);
2324 mlxsw_reg_ptar_op_set(payload, op);
2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */
2326 mlxsw_reg_ptar_key_type_set(payload, key_type);
2327 mlxsw_reg_ptar_region_size_set(payload, region_size);
2328 mlxsw_reg_ptar_region_id_set(payload, region_id);
2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2343 /* PPBS - Policy-Engine Policy Based Switching Register
2344 * ----------------------------------------------------
2345 * This register retrieves and sets Policy Based Switching Table entries.
2347 #define MLXSW_REG_PPBS_ID 0x300C
2348 #define MLXSW_REG_PPBS_LEN 0x14
2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2353 * Index into the PBS table.
2354 * For Spectrum, the index points to the KVD Linear.
2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2359 /* reg_ppbs_system_port
2360 * Unique port identifier for the final destination of the packet.
2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2368 MLXSW_REG_ZERO(ppbs, payload);
2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2370 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2373 /* PRCR - Policy-Engine Rules Copy Register
2374 * ----------------------------------------
2375 * This register is used for accessing rules within a TCAM region.
2377 #define MLXSW_REG_PRCR_ID 0x300D
2378 #define MLXSW_REG_PRCR_LEN 0x40
2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2382 enum mlxsw_reg_prcr_op {
2383 /* Move rules. Moves the rules from "tcam_region_info" starting
2384 * at offset "offset" to "dest_tcam_region_info"
2385 * at offset "dest_offset."
2387 MLXSW_REG_PRCR_OP_MOVE,
2388 /* Copy rules. Copies the rules from "tcam_region_info" starting
2389 * at offset "offset" to "dest_tcam_region_info"
2390 * at offset "dest_offset."
2392 MLXSW_REG_PRCR_OP_COPY,
2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2401 * Offset within the source region to copy/move from.
2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2407 * The number of rules to copy/move.
2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2412 /* reg_prcr_tcam_region_info
2413 * Opaque object that represents the source TCAM region.
2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2419 /* reg_prcr_dest_offset
2420 * Offset within the source region to copy/move to.
2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2425 /* reg_prcr_dest_tcam_region_info
2426 * Opaque object that represents the destination TCAM region.
2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2433 const char *src_tcam_region_info,
2435 const char *dest_tcam_region_info,
2436 u16 dest_offset, u16 size)
2438 MLXSW_REG_ZERO(prcr, payload);
2439 mlxsw_reg_prcr_op_set(payload, op);
2440 mlxsw_reg_prcr_offset_set(payload, src_offset);
2441 mlxsw_reg_prcr_size_set(payload, size);
2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2443 src_tcam_region_info);
2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2446 dest_tcam_region_info);
2449 /* PEFA - Policy-Engine Extended Flexible Action Register
2450 * ------------------------------------------------------
2451 * This register is used for accessing an extended flexible action entry
2452 * in the central KVD Linear Database.
2454 #define MLXSW_REG_PEFA_ID 0x300F
2455 #define MLXSW_REG_PEFA_LEN 0xB0
2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2460 * Index in the KVD Linear Centralized Database.
2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2466 * Index in the KVD Linear Centralized Database.
2468 * For a new entry: set if ca=0, clear if ca=1
2469 * Set if a packet lookup has hit on the specific entry
2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2476 * When write: activity is according to this field
2477 * When read: after reading the activity is cleared according to ca
2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2484 /* reg_pefa_flex_action_set
2485 * Action-set to perform when rule is matched.
2486 * Must be zero padded if action set is shorter.
2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2492 const char *flex_action_set)
2494 MLXSW_REG_ZERO(pefa, payload);
2495 mlxsw_reg_pefa_index_set(payload, index);
2496 mlxsw_reg_pefa_ca_set(payload, ca);
2497 if (flex_action_set)
2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2504 *p_a = mlxsw_reg_pefa_a_get(payload);
2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register
2508 * --------------------------------------------------------------
2509 * This register is used for binding Multicast router to an ACL group
2510 * that serves the MC router.
2511 * This register is not supported by SwitchX/-2 and Spectrum.
2513 #define MLXSW_REG_PEMRBT_ID 0x3014
2514 #define MLXSW_REG_PEMRBT_LEN 0x14
2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2518 enum mlxsw_reg_pemrbt_protocol {
2519 MLXSW_REG_PEMRBT_PROTO_IPV4,
2520 MLXSW_REG_PEMRBT_PROTO_IPV6,
2523 /* reg_pemrbt_protocol
2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2528 /* reg_pemrbt_group_id
2529 * ACL group identifier.
2530 * Range 0..cap_max_acl_groups-1
2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2539 MLXSW_REG_ZERO(pemrbt, payload);
2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2545 * -----------------------------------------------------
2546 * This register is used for accessing rules within a TCAM region.
2547 * It is a new version of PTCE in order to support wider key,
2548 * mask and action within a TCAM region. This register is not supported
2549 * by SwitchX and SwitchX-2.
2551 #define MLXSW_REG_PTCE2_ID 0x3017
2552 #define MLXSW_REG_PTCE2_LEN 0x1D8
2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2563 * Activity. Set if a packet lookup has hit on the specific entry.
2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op.
2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2569 enum mlxsw_reg_ptce2_op {
2570 /* Read operation. */
2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2572 /* clear on read operation. Used to read entry
2573 * and clear Activity bit.
2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2576 /* Write operation. Used to write a new entry to the table.
2577 * All R/W fields are relevant for new entry. Activity bit is set
2578 * for new entries - Note write with v = 0 will delete the entry.
2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2581 /* Update action. Only action set will be updated. */
2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2583 /* Clear activity. A bit is cleared for the entry. */
2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2597 /* reg_ptce2_priority
2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1.
2599 * Note: priority does not have to be unique per rule.
2600 * Within a region, higher priority should have lower offset (no limitation
2601 * between regions in a multi-region).
2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2606 /* reg_ptce2_tcam_region_info
2607 * Opaque object that represents the TCAM region.
2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2615 /* reg_ptce2_flex_key_blocks
2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2623 * mask- in the same size as key. A bit that is set directs the TCAM
2624 * to compare the corresponding bit in key. A bit that is clear directs
2625 * the TCAM to ignore the corresponding bit in key.
2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2631 /* reg_ptce2_flex_action_set
2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2636 MLXSW_REG_FLEX_ACTION_SET_LEN);
2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2639 enum mlxsw_reg_ptce2_op op,
2640 const char *tcam_region_info,
2641 u16 offset, u32 priority)
2643 MLXSW_REG_ZERO(ptce2, payload);
2644 mlxsw_reg_ptce2_v_set(payload, valid);
2645 mlxsw_reg_ptce2_op_set(payload, op);
2646 mlxsw_reg_ptce2_offset_set(payload, offset);
2647 mlxsw_reg_ptce2_priority_set(payload, priority);
2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2651 /* PERPT - Policy-Engine ERP Table Register
2652 * ----------------------------------------
2653 * This register adds and removes eRPs from the eRP table.
2655 #define MLXSW_REG_PERPT_ID 0x3021
2656 #define MLXSW_REG_PERPT_LEN 0x80
2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2660 /* reg_perpt_erpt_bank
2662 * Range 0 .. cap_max_erp_table_banks - 1
2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2667 /* reg_perpt_erpt_index
2668 * Index to eRP table within the eRP bank.
2669 * Range is 0 .. cap_max_erp_table_bank_size - 1
2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2674 enum mlxsw_reg_perpt_key_size {
2675 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2676 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2677 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2678 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2681 /* reg_perpt_key_size
2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2686 /* reg_perpt_bf_bypass
2687 * 0 - The eRP is used only if bloom filter state is set for the given
2689 * 1 - The eRP is used regardless of bloom filter state.
2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass
2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2696 * eRP ID for use by the rules.
2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2701 /* reg_perpt_erpt_base_bank
2702 * Base eRP table bank, points to head of erp_vector
2703 * Range is 0 .. cap_max_erp_table_banks - 1
2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2708 /* reg_perpt_erpt_base_index
2709 * Base index to eRP table within the eRP bank
2710 * Range is 0 .. cap_max_erp_table_bank_size - 1
2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2715 /* reg_perpt_erp_index_in_vector
2716 * eRP index in the vector.
2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2721 /* reg_perpt_erp_vector
2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2729 * 0 - A-TCAM will ignore the bit in key
2730 * 1 - A-TCAM will compare the bit in key
2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
2736 unsigned long *erp_vector,
2741 for_each_set_bit(bit, erp_vector, size)
2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
2751 MLXSW_REG_ZERO(perpt, payload);
2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2754 mlxsw_reg_perpt_key_size_set(payload, key_size);
2755 mlxsw_reg_perpt_bf_bypass_set(payload, false);
2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
2763 /* PERAR - Policy-Engine Region Association Register
2764 * -------------------------------------------------
2765 * This register associates a hw region for region_id's. Changing on the fly
2766 * is supported by the device.
2768 #define MLXSW_REG_PERAR_ID 0x3026
2769 #define MLXSW_REG_PERAR_LEN 0x08
2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
2773 /* reg_perar_region_id
2775 * Range 0 .. cap_max_regions-1
2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
2780 static inline unsigned int
2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
2783 return DIV_ROUND_UP(block_num, 4);
2786 /* reg_perar_hw_region
2788 * Range 0 .. cap_max_regions-1
2789 * Default: hw_region = region_id
2790 * For a 8 key block region, 2 consecutive regions are used
2791 * For a 12 key block region, 3 consecutive regions are used
2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
2799 MLXSW_REG_ZERO(perar, payload);
2800 mlxsw_reg_perar_region_id_set(payload, region_id);
2801 mlxsw_reg_perar_hw_region_set(payload, hw_region);
2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3
2805 * -----------------------------------------------------
2806 * This register is a new version of PTCE-V2 in order to support the
2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum.
2809 #define MLXSW_REG_PTCE3_ID 0x3027
2810 #define MLXSW_REG_PTCE3_LEN 0xF0
2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
2820 enum mlxsw_reg_ptce3_op {
2821 /* Write operation. Used to write a new entry to the table.
2822 * All R/W fields are relevant for new entry. Activity bit is set
2823 * for new entries. Write with v = 0 will delete the entry. Must
2824 * not be used if an entry exists.
2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
2827 /* Update operation */
2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
2829 /* Read operation */
2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
2838 /* reg_ptce3_priority
2839 * Priority of the rule. Higher values win.
2840 * For Spectrum-2 range is 1..cap_kvd_size - 1
2841 * Note: Priority does not have to be unique per rule.
2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
2846 /* reg_ptce3_tcam_region_info
2847 * Opaque object that represents the TCAM region.
2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2853 /* reg_ptce3_flex2_key_blocks
2854 * ACL key. The key must be masked according to eRP (if exists) or
2855 * according to master mask.
2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
2867 /* reg_ptce3_delta_start
2868 * Start point of delta_value and delta_mask, in bits. Must not exceed
2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0.
2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
2874 /* reg_ptce3_delta_mask
2876 * 0 - Ignore relevant bit in delta_value
2877 * 1 - Compare relevant bit in delta_value
2878 * Delta mask must not be set for reserved fields in the key blocks.
2879 * Note: No delta when no eRPs. Thus, for regions with
2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0.
2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
2885 /* reg_ptce3_delta_value
2887 * Bits which are masked by delta_mask must be 0.
2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
2892 /* reg_ptce3_prune_vector
2893 * Pruning vector relative to the PERPT.erp_id.
2894 * Used for reducing lookups.
2895 * 0 - NEED: Do a lookup using the eRP.
2896 * 1 - PRUNE: Do not perform a lookup using the eRP.
2897 * Maybe be modified by PEAPBL and PEAPBM.
2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either
2899 * all 1's or all 0's.
2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
2904 /* reg_ptce3_prune_ctcam
2905 * Pruning on C-TCAM. Used for reducing lookups.
2906 * 0 - NEED: Do a lookup in the C-TCAM.
2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM.
2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
2912 /* reg_ptce3_large_exists
2913 * Large entry key ID exists.
2914 * Within the region:
2915 * 0 - SINGLE: The large_entry_key_id is not currently in use.
2916 * For rule insert: The MSB of the key (blocks 6..11) will be added.
2917 * For rule delete: The MSB of the key will be removed.
2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use.
2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added.
2920 * For rule delete: The MSB of the key will not be removed.
2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
2925 /* reg_ptce3_large_entry_key_id
2926 * Large entry key ID.
2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key
2928 * blocks. Must be different for different keys which have the same common
2929 * 6 key blocks (MSB, blocks 6..11) key within a region.
2930 * Range is 0..cap_max_pe_large_key_id - 1
2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
2935 /* reg_ptce3_action_pointer
2936 * Pointer to action.
2937 * Range is 0..cap_max_kvd_action_sets - 1
2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
2943 enum mlxsw_reg_ptce3_op op,
2945 const char *tcam_region_info,
2946 const char *key, u8 erp_id,
2947 u16 delta_start, u8 delta_mask,
2948 u8 delta_value, bool large_exists,
2949 u32 lkey_id, u32 action_pointer)
2951 MLXSW_REG_ZERO(ptce3, payload);
2952 mlxsw_reg_ptce3_v_set(payload, valid);
2953 mlxsw_reg_ptce3_op_set(payload, op);
2954 mlxsw_reg_ptce3_priority_set(payload, priority);
2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
2966 /* PERCR - Policy-Engine Region Configuration Register
2967 * ---------------------------------------------------
2968 * This register configures the region parameters. The region_id must be
2971 #define MLXSW_REG_PERCR_ID 0x302A
2972 #define MLXSW_REG_PERCR_LEN 0x80
2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
2976 /* reg_percr_region_id
2977 * Region identifier.
2978 * Range 0..cap_max_regions-1
2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
2983 /* reg_percr_atcam_ignore_prune
2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule.
2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
2989 /* reg_percr_ctcam_ignore_prune
2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule.
2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
2995 /* reg_percr_bf_bypass
2996 * Bloom filter bypass.
2997 * 0 - Bloom filter is used (default)
2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of
2999 * region_id or eRP. See PERPT.bf_bypass
3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3004 /* reg_percr_master_mask
3005 * Master mask. Logical OR mask of all masks of all rules of a region
3006 * (both A-TCAM and C-TCAM). When there are no eRPs
3007 * (erpt_pointer_valid = 0), then this provides the mask.
3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3014 MLXSW_REG_ZERO(percr, payload);
3015 mlxsw_reg_percr_region_id_set(payload, region_id);
3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3018 mlxsw_reg_percr_bf_bypass_set(payload, false);
3021 /* PERERP - Policy-Engine Region eRP Register
3022 * ------------------------------------------
3023 * This register configures the region eRP. The region_id must be
3026 #define MLXSW_REG_PERERP_ID 0x302B
3027 #define MLXSW_REG_PERERP_LEN 0x1C
3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3031 /* reg_pererp_region_id
3032 * Region identifier.
3033 * Range 0..cap_max_regions-1
3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3038 /* reg_pererp_ctcam_le
3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0.
3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3044 /* reg_pererp_erpt_pointer_valid
3045 * erpt_pointer is valid.
3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3050 /* reg_pererp_erpt_bank_pointer
3051 * Pointer to eRP table bank. May be modified at any time.
3052 * Range 0..cap_max_erp_table_banks-1
3053 * Reserved when erpt_pointer_valid = 0
3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3057 /* reg_pererp_erpt_pointer
3058 * Pointer to eRP table within the eRP bank. Can be changed for an
3060 * Range 0..cap_max_erp_table_size-1
3061 * Reserved when erpt_pointer_valid = 0
3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3066 /* reg_pererp_erpt_vector
3067 * Vector of allowed eRP indexes starting from erpt_pointer within the
3068 * erpt_bank_pointer. Next entries will be in next bank.
3069 * Note that eRP index is used and not eRP ID.
3070 * Reserved when erpt_pointer_valid = 0
3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3075 /* reg_pererp_master_rp_id
3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID
3077 * for the lookup. Can be changed for an existing region.
3078 * Reserved when erpt_pointer_valid = 1
3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3084 unsigned long *erp_vector,
3089 for_each_set_bit(bit, erp_vector, size)
3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3094 bool ctcam_le, bool erpt_pointer_valid,
3095 u8 erpt_bank_pointer, u8 erpt_pointer,
3098 MLXSW_REG_ZERO(pererp, payload);
3099 mlxsw_reg_pererp_region_id_set(payload, region_id);
3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
3108 * ----------------------------------------------------------------
3109 * This register configures the Bloom filter entries.
3111 #define MLXSW_REG_PEABFE_ID 0x3022
3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10
3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3116 MLXSW_REG_PEABFE_BF_REC_LEN * \
3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3122 * Number of BF entries to be updated.
3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3128 /* reg_peabfe_bf_entry_state
3129 * Bloom filter state
3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3138 /* reg_peabfe_bf_entry_bank
3139 * Bloom filter bank ID
3140 * Range 0..cap_max_erp_table_banks-1
3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3147 /* reg_peabfe_bf_entry_index
3148 * Bloom filter entry index
3149 * Range 0..2^cap_max_bf_log-1
3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3156 static inline void mlxsw_reg_peabfe_pack(char *payload)
3158 MLXSW_REG_ZERO(peabfe, payload);
3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3162 u8 state, u8 bank, u32 bf_index)
3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3166 if (rec_index >= num_rec)
3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3173 /* IEDR - Infrastructure Entry Delete Register
3174 * ----------------------------------------------------
3175 * This register is used for deleting entries from the entry tables.
3176 * It is legitimate to attempt to delete a nonexisting entry (the device will
3177 * respond as a good flow).
3179 #define MLXSW_REG_IEDR_ID 0x3804
3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */
3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */
3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3184 MLXSW_REG_IEDR_REC_LEN * \
3185 MLXSW_REG_IEDR_REC_MAX_COUNT)
3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3190 * Number of records.
3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3195 /* reg_iedr_rec_type
3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3202 /* reg_iedr_rec_size
3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3209 /* reg_iedr_rec_index_start
3210 * Resource index start.
3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3216 static inline void mlxsw_reg_iedr_pack(char *payload)
3218 MLXSW_REG_ZERO(iedr, payload);
3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3222 u8 rec_type, u16 rec_size,
3223 u32 rec_index_start)
3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3227 if (rec_index >= num_rec)
3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3234 /* QPTS - QoS Priority Trust State Register
3235 * ----------------------------------------
3236 * This register controls the port policy to calculate the switch priority and
3237 * packet color based on incoming packet fields.
3239 #define MLXSW_REG_QPTS_ID 0x4002
3240 #define MLXSW_REG_QPTS_LEN 0x8
3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3244 /* reg_qpts_local_port
3245 * Local port number.
3248 * Note: CPU port is supported.
3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3252 enum mlxsw_reg_qpts_trust_state {
3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */
3257 /* reg_qpts_trust_state
3258 * Trust state for a given port.
3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3264 enum mlxsw_reg_qpts_trust_state ts)
3266 MLXSW_REG_ZERO(qpts, payload);
3268 mlxsw_reg_qpts_local_port_set(payload, local_port);
3269 mlxsw_reg_qpts_trust_state_set(payload, ts);
3272 /* QPCR - QoS Policer Configuration Register
3273 * -----------------------------------------
3274 * The QPCR register is used to create policers - that limit
3275 * the rate of bytes or packets via some trap group.
3277 #define MLXSW_REG_QPCR_ID 0x4004
3278 #define MLXSW_REG_QPCR_LEN 0x28
3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3282 enum mlxsw_reg_qpcr_g {
3283 MLXSW_REG_QPCR_G_GLOBAL = 2,
3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3299 /* reg_qpcr_color_aware
3300 * Is the policer aware of colors.
3301 * Must be 0 (unaware) for cpu port.
3302 * Access: RW for unbounded policer. RO for bounded policer.
3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3307 * Is policer limit is for bytes per sec or packets per sec.
3310 * Access: RW for unbounded policer. RO for bounded policer.
3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3314 enum mlxsw_reg_qpcr_ir_units {
3315 MLXSW_REG_QPCR_IR_UNITS_M,
3316 MLXSW_REG_QPCR_IR_UNITS_K,
3319 /* reg_qpcr_ir_units
3320 * Policer's units for cir and eir fields (for bytes limits only)
3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3327 enum mlxsw_reg_qpcr_rate_type {
3328 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3329 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3332 /* reg_qpcr_rate_type
3333 * Policer can have one limit (single rate) or 2 limits with specific operation
3334 * for packets that exceed the lower rate but not the upper one.
3335 * (For cpu port must be single rate)
3336 * Access: RW for unbounded policer. RO for bounded policer.
3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3341 * Policer's committed burst size.
3342 * The policer is working with time slices of 50 nano sec. By default every
3343 * slice is granted the proportionate share of the committed rate. If we want to
3344 * allow a slice to exceed that share (while still keeping the rate per sec) we
3345 * can allow burst. The burst size is between the default proportionate share
3346 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the
3347 * committed rate will result in exceeding the rate). The burst size must be a
3348 * log of 2 and will be determined by 2^cbs.
3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3354 * Policer's committed rate.
3355 * The rate used for sungle rate, the lower rate for double rate.
3356 * For bytes limits, the rate will be this value * the unit from ir_units.
3357 * (Resolution error is up to 1%).
3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3363 * Policer's exceed rate.
3364 * The higher rate for double rate, reserved for single rate.
3365 * Lower rate for double rate policer.
3366 * For bytes limits, the rate will be this value * the unit from ir_units.
3367 * (Resolution error is up to 1%).
3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3374 /* reg_qpcr_exceed_action.
3375 * What to do with packets between the 2 limits for double rate.
3376 * Access: RW for unbounded policer. RO for bounded policer.
3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3380 enum mlxsw_reg_qpcr_action {
3382 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3383 /* Forward and set color to red.
3384 * If the packet is intended to cpu port, it will be dropped.
3386 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3389 /* reg_qpcr_violate_action
3390 * What to do with packets that cross the cir limit (for single rate) or the eir
3391 * limit (for double rate).
3392 * Access: RW for unbounded policer. RO for bounded policer.
3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3397 enum mlxsw_reg_qpcr_ir_units ir_units,
3398 bool bytes, u32 cir, u16 cbs)
3400 MLXSW_REG_ZERO(qpcr, payload);
3401 mlxsw_reg_qpcr_pid_set(payload, pid);
3402 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3403 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3404 mlxsw_reg_qpcr_violate_action_set(payload,
3405 MLXSW_REG_QPCR_ACTION_DISCARD);
3406 mlxsw_reg_qpcr_cir_set(payload, cir);
3407 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3408 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3409 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3412 /* QTCT - QoS Switch Traffic Class Table
3413 * -------------------------------------
3414 * Configures the mapping between the packet switch priority and the
3415 * traffic class on the transmit port.
3417 #define MLXSW_REG_QTCT_ID 0x400A
3418 #define MLXSW_REG_QTCT_LEN 0x08
3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3422 /* reg_qtct_local_port
3423 * Local port number.
3426 * Note: CPU port is not supported.
3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3430 /* reg_qtct_sub_port
3431 * Virtual port within the physical port.
3432 * Should be set to 0 when virtual ports are not enabled on the port.
3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3437 /* reg_qtct_switch_prio
3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3446 * switch_prio 0 : tclass 1
3447 * switch_prio 1 : tclass 0
3448 * switch_prio i : tclass i, for i > 1
3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3454 u8 switch_prio, u8 tclass)
3456 MLXSW_REG_ZERO(qtct, payload);
3457 mlxsw_reg_qtct_local_port_set(payload, local_port);
3458 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3459 mlxsw_reg_qtct_tclass_set(payload, tclass);
3462 /* QEEC - QoS ETS Element Configuration Register
3463 * ---------------------------------------------
3464 * Configures the ETS elements.
3466 #define MLXSW_REG_QEEC_ID 0x400D
3467 #define MLXSW_REG_QEEC_LEN 0x20
3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3471 /* reg_qeec_local_port
3472 * Local port number.
3475 * Note: CPU port is supported.
3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3479 enum mlxsw_reg_qeec_hr {
3480 MLXSW_REG_QEEC_HIERARCY_PORT,
3481 MLXSW_REG_QEEC_HIERARCY_GROUP,
3482 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3483 MLXSW_REG_QEEC_HIERARCY_TC,
3486 /* reg_qeec_element_hierarchy
3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3495 /* reg_qeec_element_index
3496 * The index of the element in the hierarchy.
3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3501 /* reg_qeec_next_element_index
3502 * The index of the next (lower) element in the hierarchy.
3505 * Note: Reserved for element_hierarchy 0.
3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3510 * Min shaper configuration enable. Enables configuration of the min
3511 * shaper on this ETS element
3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3520 * 0: regular shaper mode
3521 * 1: PTP oriented shaper
3522 * Allowed only for hierarchy 0
3523 * Not supported for CPU port
3524 * Note that ptps mode may affect the shaper rates of all hierarchies
3525 * Supported only on Spectrum-1
3528 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3531 MLXSW_REG_QEEC_BYTES_MODE,
3532 MLXSW_REG_QEEC_PACKETS_MODE,
3536 * Packets or bytes mode.
3541 * Note: Used for max shaper configuration. For Spectrum, packets mode
3542 * is supported only for traffic classes of CPU port.
3544 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3546 /* The smallest permitted min shaper rate. */
3547 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */
3549 /* reg_qeec_min_shaper_rate
3550 * Min shaper information rate.
3551 * For CPU port, can only be configured for port hierarchy.
3552 * When in bytes mode, value is specified in units of 1000bps.
3555 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3558 * Max shaper configuration enable. Enables configuration of the max
3559 * shaper on this ETS element.
3564 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3566 /* A large max rate will disable the max shaper. */
3567 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
3569 /* reg_qeec_max_shaper_rate
3570 * Max shaper information rate.
3571 * For CPU port, can only be configured for port hierarchy.
3572 * When in bytes mode, value is specified in units of 1000bps.
3575 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
3578 * DWRR configuration enable. Enables configuration of the dwrr and
3584 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3587 * Transmission selection algorithm to use on the link going down from
3589 * 0 - Strict priority
3593 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3595 /* reg_qeec_dwrr_weight
3596 * DWRR weight on the link going down from the ETS element. The
3597 * percentage of bandwidth guaranteed to an ETS element within
3598 * its hierarchy. The sum of all weights across all ETS elements
3599 * within one hierarchy should be equal to 100. Reserved when
3600 * transmission selection algorithm is strict priority.
3603 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3605 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3606 enum mlxsw_reg_qeec_hr hr, u8 index,
3609 MLXSW_REG_ZERO(qeec, payload);
3610 mlxsw_reg_qeec_local_port_set(payload, local_port);
3611 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3612 mlxsw_reg_qeec_element_index_set(payload, index);
3613 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3616 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3619 MLXSW_REG_ZERO(qeec, payload);
3620 mlxsw_reg_qeec_local_port_set(payload, local_port);
3621 mlxsw_reg_qeec_element_hierarchy_set(payload,
3622 MLXSW_REG_QEEC_HIERARCY_PORT);
3623 mlxsw_reg_qeec_ptps_set(payload, ptps);
3626 /* QRWE - QoS ReWrite Enable
3627 * -------------------------
3628 * This register configures the rewrite enable per receive port.
3630 #define MLXSW_REG_QRWE_ID 0x400F
3631 #define MLXSW_REG_QRWE_LEN 0x08
3633 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3635 /* reg_qrwe_local_port
3636 * Local port number.
3639 * Note: CPU port is supported. No support for router port.
3641 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3644 * Whether to enable DSCP rewrite (default is 0, don't rewrite).
3647 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3650 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite).
3653 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3655 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3656 bool rewrite_pcp, bool rewrite_dscp)
3658 MLXSW_REG_ZERO(qrwe, payload);
3659 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3660 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3661 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3664 /* QPDSM - QoS Priority to DSCP Mapping
3665 * ------------------------------------
3666 * QoS Priority to DSCP Mapping Register
3668 #define MLXSW_REG_QPDSM_ID 0x4011
3669 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */
3670 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */
3671 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3672 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3673 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3674 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3676 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3678 /* reg_qpdsm_local_port
3679 * Local Port. Supported for data packets from CPU port.
3682 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3684 /* reg_qpdsm_prio_entry_color0_e
3685 * Enable update of the entry for color 0 and a given port.
3688 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3689 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3690 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3692 /* reg_qpdsm_prio_entry_color0_dscp
3693 * DSCP field in the outer label of the packet for color 0 and a given port.
3694 * Reserved when e=0.
3697 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
3698 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
3699 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3701 /* reg_qpdsm_prio_entry_color1_e
3702 * Enable update of the entry for color 1 and a given port.
3705 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
3706 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
3707 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3709 /* reg_qpdsm_prio_entry_color1_dscp
3710 * DSCP field in the outer label of the packet for color 1 and a given port.
3711 * Reserved when e=0.
3714 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
3715 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
3716 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3718 /* reg_qpdsm_prio_entry_color2_e
3719 * Enable update of the entry for color 2 and a given port.
3722 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
3723 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
3724 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3726 /* reg_qpdsm_prio_entry_color2_dscp
3727 * DSCP field in the outer label of the packet for color 2 and a given port.
3728 * Reserved when e=0.
3731 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
3732 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
3733 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3735 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
3737 MLXSW_REG_ZERO(qpdsm, payload);
3738 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
3742 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
3744 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
3745 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
3746 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
3747 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
3748 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
3749 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3752 /* QPDPM - QoS Port DSCP to Priority Mapping Register
3753 * --------------------------------------------------
3754 * This register controls the mapping from DSCP field to
3755 * Switch Priority for IP packets.
3757 #define MLXSW_REG_QPDPM_ID 0x4013
3758 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */
3759 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */
3760 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
3761 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
3762 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
3763 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
3765 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
3767 /* reg_qpdpm_local_port
3768 * Local Port. Supported for data packets from CPU port.
3771 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
3774 * Enable update of the specific entry. When cleared, the switch_prio and color
3775 * fields are ignored and the previous switch_prio and color values are
3779 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
3780 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3782 /* reg_qpdpm_dscp_prio
3783 * The new Switch Priority value for the relevant DSCP value.
3786 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
3787 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
3788 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
3790 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
3792 MLXSW_REG_ZERO(qpdpm, payload);
3793 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
3797 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
3799 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
3800 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
3803 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register
3804 * ------------------------------------------------------------------
3805 * This register configures if the Switch Priority to Traffic Class mapping is
3806 * based on Multicast packet indication. If so, then multicast packets will get
3807 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by
3809 * By default, Switch Priority to Traffic Class mapping is not based on
3810 * Multicast packet indication.
3812 #define MLXSW_REG_QTCTM_ID 0x401A
3813 #define MLXSW_REG_QTCTM_LEN 0x08
3815 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
3817 /* reg_qtctm_local_port
3818 * Local port number.
3819 * No support for CPU port.
3822 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
3826 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet
3827 * indication (default is 0, not based on Multicast packet indication).
3829 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
3832 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
3834 MLXSW_REG_ZERO(qtctm, payload);
3835 mlxsw_reg_qtctm_local_port_set(payload, local_port);
3836 mlxsw_reg_qtctm_mc_set(payload, mc);
3839 /* QPSC - QoS PTP Shaper Configuration Register
3840 * --------------------------------------------
3841 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
3842 * Supported only on Spectrum-1.
3844 #define MLXSW_REG_QPSC_ID 0x401B
3845 #define MLXSW_REG_QPSC_LEN 0x28
3847 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
3849 enum mlxsw_reg_qpsc_port_speed {
3850 MLXSW_REG_QPSC_PORT_SPEED_100M,
3851 MLXSW_REG_QPSC_PORT_SPEED_1G,
3852 MLXSW_REG_QPSC_PORT_SPEED_10G,
3853 MLXSW_REG_QPSC_PORT_SPEED_25G,
3856 /* reg_qpsc_port_speed
3860 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
3862 /* reg_qpsc_shaper_time_exp
3863 * The base-time-interval for updating the shapers tokens (for all hierarchies).
3864 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3865 * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3868 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
3870 /* reg_qpsc_shaper_time_mantissa
3871 * The base-time-interval for updating the shapers tokens (for all hierarchies).
3872 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
3873 * shaper_rate = 64bit * shaper_inc / shaper_update_rate
3876 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
3878 /* reg_qpsc_shaper_inc
3879 * Number of tokens added to shaper on each update.
3883 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
3885 /* reg_qpsc_shaper_bs
3886 * Max shaper Burst size.
3887 * Burst size is 2 ^ max_shaper_bs * 512 [bits]
3888 * Range is: 5..25 (from 2KB..2GB)
3891 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
3894 * Write enable to port_to_shaper_credits.
3897 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
3899 /* reg_qpsc_port_to_shaper_credits
3900 * For split ports: range 1..57
3901 * For non-split ports: range 1..112
3902 * Written only when ptsc_we is set.
3905 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
3907 /* reg_qpsc_ing_timestamp_inc
3908 * Ingress timestamp increment.
3910 * The timestamp of MTPPTR at ingress will be incremented by this value. Global
3911 * value for all ports.
3912 * Same units as used by MTPPTR.
3915 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
3917 /* reg_qpsc_egr_timestamp_inc
3918 * Egress timestamp increment.
3920 * The timestamp of MTPPTR at egress will be incremented by this value. Global
3921 * value for all ports.
3922 * Same units as used by MTPPTR.
3925 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
3928 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
3929 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
3930 u8 shaper_bs, u8 port_to_shaper_credits,
3931 int ing_timestamp_inc, int egr_timestamp_inc)
3933 MLXSW_REG_ZERO(qpsc, payload);
3934 mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
3935 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
3936 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
3937 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
3938 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
3939 mlxsw_reg_qpsc_ptsc_we_set(payload, true);
3940 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
3941 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
3942 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
3945 /* PMLP - Ports Module to Local Port Register
3946 * ------------------------------------------
3947 * Configures the assignment of modules to local ports.
3949 #define MLXSW_REG_PMLP_ID 0x5002
3950 #define MLXSW_REG_PMLP_LEN 0x40
3952 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
3955 * 0 - Tx value is used for both Tx and Rx.
3956 * 1 - Rx value is taken from a separte field.
3959 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
3961 /* reg_pmlp_local_port
3962 * Local port number.
3965 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
3968 * 0 - Unmap local port.
3969 * 1 - Lane 0 is used.
3970 * 2 - Lanes 0 and 1 are used.
3971 * 4 - Lanes 0, 1, 2 and 3 are used.
3974 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
3980 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
3983 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3986 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
3989 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3993 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
3995 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3997 MLXSW_REG_ZERO(pmlp, payload);
3998 mlxsw_reg_pmlp_local_port_set(payload, local_port);
4001 /* PMTU - Port MTU Register
4002 * ------------------------
4003 * Configures and reports the port MTU.
4005 #define MLXSW_REG_PMTU_ID 0x5003
4006 #define MLXSW_REG_PMTU_LEN 0x10
4008 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4010 /* reg_pmtu_local_port
4011 * Local port number.
4014 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
4018 * When port type (e.g. Ethernet) is configured, the relevant MTU is
4019 * reported, otherwise the minimum between the max_mtu of the different
4020 * types is reported.
4023 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4025 /* reg_pmtu_admin_mtu
4026 * MTU value to set port to. Must be smaller or equal to max_mtu.
4027 * Note: If port type is Infiniband, then port must be disabled, when its
4031 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4033 /* reg_pmtu_oper_mtu
4034 * The actual MTU configured on the port. Packets exceeding this size
4036 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
4037 * oper_mtu might be smaller than admin_mtu.
4040 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4042 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
4045 MLXSW_REG_ZERO(pmtu, payload);
4046 mlxsw_reg_pmtu_local_port_set(payload, local_port);
4047 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4048 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4049 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4052 /* PTYS - Port Type and Speed Register
4053 * -----------------------------------
4054 * Configures and reports the port speed type.
4056 * Note: When set while the link is up, the changes will not take effect
4057 * until the port transitions from down to up state.
4059 #define MLXSW_REG_PTYS_ID 0x5004
4060 #define MLXSW_REG_PTYS_LEN 0x40
4062 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4065 * Auto negotiation disable administrative configuration
4066 * 0 - Device doesn't support AN disable.
4067 * 1 - Device supports AN disable.
4070 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4072 /* reg_ptys_local_port
4073 * Local port number.
4076 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
4078 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
4079 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
4081 /* reg_ptys_proto_mask
4082 * Protocol mask. Indicates which protocol is used.
4084 * 1 - Fibre Channel.
4088 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4091 MLXSW_REG_PTYS_AN_STATUS_NA,
4092 MLXSW_REG_PTYS_AN_STATUS_OK,
4093 MLXSW_REG_PTYS_AN_STATUS_FAIL,
4096 /* reg_ptys_an_status
4097 * Autonegotiation status.
4100 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4102 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
4103 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
4104 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2)
4105 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
4106 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
4107 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
4108 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
4109 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
4110 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
4111 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
4112 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
4113 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
4114 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15)
4116 /* reg_ptys_ext_eth_proto_cap
4117 * Extended Ethernet port supported speeds and protocols.
4120 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4122 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
4123 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
4124 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
4125 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
4126 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
4127 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
4128 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
4129 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
4130 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
4131 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
4132 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
4133 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
4134 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
4135 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
4136 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
4137 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
4138 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
4139 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
4140 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
4141 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
4142 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
4143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
4144 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
4145 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
4146 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
4147 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
4148 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
4150 /* reg_ptys_eth_proto_cap
4151 * Ethernet port supported speeds and protocols.
4154 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4156 /* reg_ptys_ib_link_width_cap
4157 * IB port supported widths.
4160 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4162 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
4163 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
4164 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
4165 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
4166 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
4167 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
4169 /* reg_ptys_ib_proto_cap
4170 * IB port supported speeds and protocols.
4173 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4175 /* reg_ptys_ext_eth_proto_admin
4176 * Extended speed and protocol to set port to.
4179 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4181 /* reg_ptys_eth_proto_admin
4182 * Speed and protocol to set port to.
4185 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4187 /* reg_ptys_ib_link_width_admin
4188 * IB width to set port to.
4191 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4193 /* reg_ptys_ib_proto_admin
4194 * IB speeds and protocols to set port to.
4197 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4199 /* reg_ptys_ext_eth_proto_oper
4200 * The extended current speed and protocol configured for the port.
4203 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4205 /* reg_ptys_eth_proto_oper
4206 * The current speed and protocol configured for the port.
4209 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4211 /* reg_ptys_ib_link_width_oper
4212 * The current IB width to set port to.
4215 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4217 /* reg_ptys_ib_proto_oper
4218 * The current IB speed and protocol.
4221 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4223 enum mlxsw_reg_ptys_connector_type {
4224 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4225 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4226 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4227 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4228 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4229 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4230 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4231 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4232 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4235 /* reg_ptys_connector_type
4236 * Connector type indication.
4239 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4241 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4242 u32 proto_admin, bool autoneg)
4244 MLXSW_REG_ZERO(ptys, payload);
4245 mlxsw_reg_ptys_local_port_set(payload, local_port);
4246 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4247 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4248 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4251 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4252 u32 proto_admin, bool autoneg)
4254 MLXSW_REG_ZERO(ptys, payload);
4255 mlxsw_reg_ptys_local_port_set(payload, local_port);
4256 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4257 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4258 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4261 static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4262 u32 *p_eth_proto_cap,
4263 u32 *p_eth_proto_admin,
4264 u32 *p_eth_proto_oper)
4266 if (p_eth_proto_cap)
4268 mlxsw_reg_ptys_eth_proto_cap_get(payload);
4269 if (p_eth_proto_admin)
4270 *p_eth_proto_admin =
4271 mlxsw_reg_ptys_eth_proto_admin_get(payload);
4272 if (p_eth_proto_oper)
4274 mlxsw_reg_ptys_eth_proto_oper_get(payload);
4277 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4278 u32 *p_eth_proto_cap,
4279 u32 *p_eth_proto_admin,
4280 u32 *p_eth_proto_oper)
4282 if (p_eth_proto_cap)
4284 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4285 if (p_eth_proto_admin)
4286 *p_eth_proto_admin =
4287 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4288 if (p_eth_proto_oper)
4290 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4293 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4294 u16 proto_admin, u16 link_width)
4296 MLXSW_REG_ZERO(ptys, payload);
4297 mlxsw_reg_ptys_local_port_set(payload, local_port);
4298 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4299 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4300 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4303 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4304 u16 *p_ib_link_width_cap,
4305 u16 *p_ib_proto_oper,
4306 u16 *p_ib_link_width_oper)
4309 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4310 if (p_ib_link_width_cap)
4311 *p_ib_link_width_cap =
4312 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4313 if (p_ib_proto_oper)
4314 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4315 if (p_ib_link_width_oper)
4316 *p_ib_link_width_oper =
4317 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4320 /* PPAD - Port Physical Address Register
4321 * -------------------------------------
4322 * The PPAD register configures the per port physical MAC address.
4324 #define MLXSW_REG_PPAD_ID 0x5005
4325 #define MLXSW_REG_PPAD_LEN 0x10
4327 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4329 /* reg_ppad_single_base_mac
4330 * 0: base_mac, local port should be 0 and mac[7:0] is
4331 * reserved. HW will set incremental
4332 * 1: single_mac - mac of the local_port
4335 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4337 /* reg_ppad_local_port
4338 * port number, if single_base_mac = 0 then local_port is reserved
4341 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4344 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
4345 * If single_base_mac = 1 - the per port MAC address
4348 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4350 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4353 MLXSW_REG_ZERO(ppad, payload);
4354 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4355 mlxsw_reg_ppad_local_port_set(payload, local_port);
4358 /* PAOS - Ports Administrative and Operational Status Register
4359 * -----------------------------------------------------------
4360 * Configures and retrieves per port administrative and operational status.
4362 #define MLXSW_REG_PAOS_ID 0x5006
4363 #define MLXSW_REG_PAOS_LEN 0x10
4365 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4368 * Switch partition ID with which to associate the port.
4369 * Note: while external ports uses unique local port numbers (and thus swid is
4370 * redundant), router ports use the same local port number where swid is the
4371 * only indication for the relevant port.
4374 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4376 /* reg_paos_local_port
4377 * Local port number.
4380 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4382 /* reg_paos_admin_status
4383 * Port administrative state (the desired state of the port):
4386 * 3 - Up once. This means that in case of link failure, the port won't go
4387 * into polling mode, but will wait to be re-enabled by software.
4388 * 4 - Disabled by system. Can only be set by hardware.
4391 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4393 /* reg_paos_oper_status
4394 * Port operational state (the current state):
4397 * 3 - Down by port failure. This means that the device will not let the
4398 * port up again until explicitly specified by software.
4401 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4404 * Admin state update enabled.
4407 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4410 * Event update enable. If this bit is set, event generation will be
4411 * updated based on the e field.
4414 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4417 * Event generation on operational state change:
4418 * 0 - Do not generate event.
4419 * 1 - Generate Event.
4420 * 2 - Generate Single Event.
4423 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4425 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4426 enum mlxsw_port_admin_status status)
4428 MLXSW_REG_ZERO(paos, payload);
4429 mlxsw_reg_paos_swid_set(payload, 0);
4430 mlxsw_reg_paos_local_port_set(payload, local_port);
4431 mlxsw_reg_paos_admin_status_set(payload, status);
4432 mlxsw_reg_paos_oper_status_set(payload, 0);
4433 mlxsw_reg_paos_ase_set(payload, 1);
4434 mlxsw_reg_paos_ee_set(payload, 1);
4435 mlxsw_reg_paos_e_set(payload, 1);
4438 /* PFCC - Ports Flow Control Configuration Register
4439 * ------------------------------------------------
4440 * Configures and retrieves the per port flow control configuration.
4442 #define MLXSW_REG_PFCC_ID 0x5007
4443 #define MLXSW_REG_PFCC_LEN 0x20
4445 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4447 /* reg_pfcc_local_port
4448 * Local port number.
4451 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4454 * Port number access type. Determines the way local_port is interpreted:
4455 * 0 - Local port number.
4456 * 1 - IB / label port number.
4459 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4462 * Send to higher layers capabilities:
4463 * 0 - No capability of sending Pause and PFC frames to higher layers.
4464 * 1 - Device has capability of sending Pause and PFC frames to higher
4468 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4471 * Send to higher layers operation:
4472 * 0 - Pause and PFC frames are handled by the port (default).
4473 * 1 - Pause and PFC frames are handled by the port and also sent to
4474 * higher layers. Only valid if shl_cap = 1.
4477 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4480 * Pause policy auto negotiation.
4481 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
4482 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
4483 * based on the auto-negotiation resolution.
4486 * Note: The auto-negotiation advertisement is set according to pptx and
4487 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
4489 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4491 /* reg_pfcc_prio_mask_tx
4492 * Bit per priority indicating if Tx flow control policy should be
4493 * updated based on bit pfctx.
4496 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4498 /* reg_pfcc_prio_mask_rx
4499 * Bit per priority indicating if Rx flow control policy should be
4500 * updated based on bit pfcrx.
4503 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4506 * Admin Pause policy on Tx.
4507 * 0 - Never generate Pause frames (default).
4508 * 1 - Generate Pause frames according to Rx buffer threshold.
4511 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4514 * Active (operational) Pause policy on Tx.
4515 * 0 - Never generate Pause frames.
4516 * 1 - Generate Pause frames according to Rx buffer threshold.
4519 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4522 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
4523 * 0 - Never generate priority Pause frames on the specified priority
4525 * 1 - Generate priority Pause frames according to Rx buffer threshold on
4526 * the specified priority.
4529 * Note: pfctx and pptx must be mutually exclusive.
4531 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4534 * Admin Pause policy on Rx.
4535 * 0 - Ignore received Pause frames (default).
4536 * 1 - Respect received Pause frames.
4539 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4542 * Active (operational) Pause policy on Rx.
4543 * 0 - Ignore received Pause frames.
4544 * 1 - Respect received Pause frames.
4547 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4550 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
4551 * 0 - Ignore incoming priority Pause frames on the specified priority
4553 * 1 - Respect incoming priority Pause frames on the specified priority.
4556 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4558 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4560 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4562 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4563 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4564 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4565 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4568 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4570 MLXSW_REG_ZERO(pfcc, payload);
4571 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4574 /* PPCNT - Ports Performance Counters Register
4575 * -------------------------------------------
4576 * The PPCNT register retrieves per port performance counters.
4578 #define MLXSW_REG_PPCNT_ID 0x5008
4579 #define MLXSW_REG_PPCNT_LEN 0x100
4580 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4582 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4585 * For HCA: must be always 0.
4586 * Switch partition ID to associate port with.
4587 * Switch partitions are numbered from 0 to 7 inclusively.
4588 * Switch partition 254 indicates stacking ports.
4589 * Switch partition 255 indicates all switch partitions.
4590 * Only valid on Set() operation with local_port=255.
4593 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4595 /* reg_ppcnt_local_port
4596 * Local port number.
4597 * 255 indicates all ports on the device, and is only allowed
4598 * for Set() operation.
4601 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4604 * Port number access type:
4605 * 0 - Local port number
4606 * 1 - IB port number
4609 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4611 enum mlxsw_reg_ppcnt_grp {
4612 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4613 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4614 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4615 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4616 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4617 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4618 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4619 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4620 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4624 * Performance counter group.
4625 * Group 63 indicates all groups. Only valid on Set() operation with
4627 * 0x0: IEEE 802.3 Counters
4628 * 0x1: RFC 2863 Counters
4629 * 0x2: RFC 2819 Counters
4630 * 0x3: RFC 3635 Counters
4631 * 0x5: Ethernet Extended Counters
4632 * 0x6: Ethernet Discard Counters
4633 * 0x8: Link Level Retransmission Counters
4634 * 0x10: Per Priority Counters
4635 * 0x11: Per Traffic Class Counters
4636 * 0x12: Physical Layer Counters
4637 * 0x13: Per Traffic Class Congestion Counters
4640 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4643 * Clear counters. Setting the clr bit will reset the counter value
4644 * for all counters in the counter group. This bit can be set
4645 * for both Set() and Get() operation.
4648 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4650 /* reg_ppcnt_prio_tc
4651 * Priority for counter set that support per priority, valid values: 0-7.
4652 * Traffic class for counter set that support per traffic class,
4653 * valid values: 0- cap_max_tclass-1 .
4654 * For HCA: cap_max_tclass is always 8.
4655 * Otherwise must be 0.
4658 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4660 /* Ethernet IEEE 802.3 Counter Group */
4662 /* reg_ppcnt_a_frames_transmitted_ok
4665 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
4666 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4668 /* reg_ppcnt_a_frames_received_ok
4671 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
4672 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4674 /* reg_ppcnt_a_frame_check_sequence_errors
4677 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
4678 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4680 /* reg_ppcnt_a_alignment_errors
4683 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
4684 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4686 /* reg_ppcnt_a_octets_transmitted_ok
4689 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
4690 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4692 /* reg_ppcnt_a_octets_received_ok
4695 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
4696 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4698 /* reg_ppcnt_a_multicast_frames_xmitted_ok
4701 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
4702 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4704 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
4707 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
4708 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4710 /* reg_ppcnt_a_multicast_frames_received_ok
4713 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
4714 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4716 /* reg_ppcnt_a_broadcast_frames_received_ok
4719 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
4720 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
4722 /* reg_ppcnt_a_in_range_length_errors
4725 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
4726 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4728 /* reg_ppcnt_a_out_of_range_length_field
4731 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
4732 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4734 /* reg_ppcnt_a_frame_too_long_errors
4737 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
4738 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4740 /* reg_ppcnt_a_symbol_error_during_carrier
4743 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
4744 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4746 /* reg_ppcnt_a_mac_control_frames_transmitted
4749 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
4750 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4752 /* reg_ppcnt_a_mac_control_frames_received
4755 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
4756 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4758 /* reg_ppcnt_a_unsupported_opcodes_received
4761 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
4762 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4764 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
4767 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
4768 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4770 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
4773 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4774 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4776 /* Ethernet RFC 2863 Counter Group */
4778 /* reg_ppcnt_if_in_discards
4781 MLXSW_ITEM64(reg, ppcnt, if_in_discards,
4782 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4784 /* reg_ppcnt_if_out_discards
4787 MLXSW_ITEM64(reg, ppcnt, if_out_discards,
4788 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4790 /* reg_ppcnt_if_out_errors
4793 MLXSW_ITEM64(reg, ppcnt, if_out_errors,
4794 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4796 /* Ethernet RFC 2819 Counter Group */
4798 /* reg_ppcnt_ether_stats_undersize_pkts
4801 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
4802 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4804 /* reg_ppcnt_ether_stats_oversize_pkts
4807 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
4808 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
4810 /* reg_ppcnt_ether_stats_fragments
4813 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
4814 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4816 /* reg_ppcnt_ether_stats_pkts64octets
4819 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
4820 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4822 /* reg_ppcnt_ether_stats_pkts65to127octets
4825 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
4826 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4828 /* reg_ppcnt_ether_stats_pkts128to255octets
4831 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
4832 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4834 /* reg_ppcnt_ether_stats_pkts256to511octets
4837 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
4838 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4840 /* reg_ppcnt_ether_stats_pkts512to1023octets
4843 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
4844 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
4846 /* reg_ppcnt_ether_stats_pkts1024to1518octets
4849 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
4850 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
4852 /* reg_ppcnt_ether_stats_pkts1519to2047octets
4855 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
4856 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
4858 /* reg_ppcnt_ether_stats_pkts2048to4095octets
4861 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
4862 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4864 /* reg_ppcnt_ether_stats_pkts4096to8191octets
4867 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
4868 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
4870 /* reg_ppcnt_ether_stats_pkts8192to10239octets
4873 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4874 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4876 /* Ethernet RFC 3635 Counter Group */
4878 /* reg_ppcnt_dot3stats_fcs_errors
4881 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
4882 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4884 /* reg_ppcnt_dot3stats_symbol_errors
4887 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
4888 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4890 /* reg_ppcnt_dot3control_in_unknown_opcodes
4893 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
4894 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
4896 /* reg_ppcnt_dot3in_pause_frames
4899 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
4900 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4902 /* Ethernet Extended Counter Group Counters */
4904 /* reg_ppcnt_ecn_marked
4907 MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4908 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4910 /* Ethernet Discard Counter Group Counters */
4912 /* reg_ppcnt_ingress_general
4915 MLXSW_ITEM64(reg, ppcnt, ingress_general,
4916 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4918 /* reg_ppcnt_ingress_policy_engine
4921 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
4922 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
4924 /* reg_ppcnt_ingress_vlan_membership
4927 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
4928 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
4930 /* reg_ppcnt_ingress_tag_frame_type
4933 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
4934 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
4936 /* reg_ppcnt_egress_vlan_membership
4939 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
4940 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4942 /* reg_ppcnt_loopback_filter
4945 MLXSW_ITEM64(reg, ppcnt, loopback_filter,
4946 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
4948 /* reg_ppcnt_egress_general
4951 MLXSW_ITEM64(reg, ppcnt, egress_general,
4952 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
4954 /* reg_ppcnt_egress_hoq
4957 MLXSW_ITEM64(reg, ppcnt, egress_hoq,
4958 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4960 /* reg_ppcnt_egress_policy_engine
4963 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
4964 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
4966 /* reg_ppcnt_ingress_tx_link_down
4969 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
4970 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
4972 /* reg_ppcnt_egress_stp_filter
4975 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
4976 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
4978 /* reg_ppcnt_egress_sll
4981 MLXSW_ITEM64(reg, ppcnt, egress_sll,
4982 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4984 /* Ethernet Per Priority Group Counters */
4986 /* reg_ppcnt_rx_octets
4989 MLXSW_ITEM64(reg, ppcnt, rx_octets,
4990 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
4992 /* reg_ppcnt_rx_frames
4995 MLXSW_ITEM64(reg, ppcnt, rx_frames,
4996 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
4998 /* reg_ppcnt_tx_octets
5001 MLXSW_ITEM64(reg, ppcnt, tx_octets,
5002 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5004 /* reg_ppcnt_tx_frames
5007 MLXSW_ITEM64(reg, ppcnt, tx_frames,
5008 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5010 /* reg_ppcnt_rx_pause
5013 MLXSW_ITEM64(reg, ppcnt, rx_pause,
5014 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5016 /* reg_ppcnt_rx_pause_duration
5019 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5020 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5022 /* reg_ppcnt_tx_pause
5025 MLXSW_ITEM64(reg, ppcnt, tx_pause,
5026 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5028 /* reg_ppcnt_tx_pause_duration
5031 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5032 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5034 /* reg_ppcnt_rx_pause_transition
5037 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5038 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5040 /* Ethernet Per Traffic Group Counters */
5042 /* reg_ppcnt_tc_transmit_queue
5043 * Contains the transmit queue depth in cells of traffic class
5044 * selected by prio_tc and the port selected by local_port.
5045 * The field cannot be cleared.
5048 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5049 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5051 /* reg_ppcnt_tc_no_buffer_discard_uc
5052 * The number of unicast packets dropped due to lack of shared
5056 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5057 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5059 /* Ethernet Per Traffic Class Congestion Group Counters */
5061 /* reg_ppcnt_wred_discard
5064 MLXSW_ITEM64(reg, ppcnt, wred_discard,
5065 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5067 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
5068 enum mlxsw_reg_ppcnt_grp grp,
5071 MLXSW_REG_ZERO(ppcnt, payload);
5072 mlxsw_reg_ppcnt_swid_set(payload, 0);
5073 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5074 mlxsw_reg_ppcnt_pnat_set(payload, 0);
5075 mlxsw_reg_ppcnt_grp_set(payload, grp);
5076 mlxsw_reg_ppcnt_clr_set(payload, 0);
5077 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5080 /* PLIB - Port Local to InfiniBand Port
5081 * ------------------------------------
5082 * The PLIB register performs mapping from Local Port into InfiniBand Port.
5084 #define MLXSW_REG_PLIB_ID 0x500A
5085 #define MLXSW_REG_PLIB_LEN 0x10
5087 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5089 /* reg_plib_local_port
5090 * Local port number.
5093 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
5096 * InfiniBand port remapping for local_port.
5099 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5101 /* PPTB - Port Prio To Buffer Register
5102 * -----------------------------------
5103 * Configures the switch priority to buffer table.
5105 #define MLXSW_REG_PPTB_ID 0x500B
5106 #define MLXSW_REG_PPTB_LEN 0x10
5108 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5111 MLXSW_REG_PPTB_MM_UM,
5112 MLXSW_REG_PPTB_MM_UNICAST,
5113 MLXSW_REG_PPTB_MM_MULTICAST,
5118 * 0 - Map both unicast and multicast packets to the same buffer.
5119 * 1 - Map only unicast packets.
5120 * 2 - Map only multicast packets.
5123 * Note: SwitchX-2 only supports the first option.
5125 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5127 /* reg_pptb_local_port
5128 * Local port number.
5131 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5134 * Enables the update of the untagged_buf field.
5137 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5140 * Enables the update of the prio_to_buff field.
5141 * Bit <i> is a flag for updating the mapping for switch priority <i>.
5144 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5146 /* reg_pptb_prio_to_buff
5147 * Mapping of switch priority <i> to one of the allocated receive port
5151 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5154 * Enables the update of the prio_to_buff field.
5155 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
5158 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5160 /* reg_pptb_untagged_buff
5161 * Mapping of untagged frames to one of the allocated receive port buffers.
5164 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
5165 * Spectrum, as it maps untagged packets based on the default switch priority.
5167 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5169 /* reg_pptb_prio_to_buff_msb
5170 * Mapping of switch priority <i+8> to one of the allocated receive port
5174 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5176 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5178 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5180 MLXSW_REG_ZERO(pptb, payload);
5181 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5182 mlxsw_reg_pptb_local_port_set(payload, local_port);
5183 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5184 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5187 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5190 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5191 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5194 /* PBMC - Port Buffer Management Control Register
5195 * ----------------------------------------------
5196 * The PBMC register configures and retrieves the port packet buffer
5197 * allocation for different Prios, and the Pause threshold management.
5199 #define MLXSW_REG_PBMC_ID 0x500C
5200 #define MLXSW_REG_PBMC_LEN 0x6C
5202 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5204 /* reg_pbmc_local_port
5205 * Local port number.
5208 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5210 /* reg_pbmc_xoff_timer_value
5211 * When device generates a pause frame, it uses this value as the pause
5212 * timer (time for the peer port to pause in quota-512 bit time).
5215 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5217 /* reg_pbmc_xoff_refresh
5218 * The time before a new pause frame should be sent to refresh the pause RW
5219 * state. Using the same units as xoff_timer_value above (in quota-512 bit
5223 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5225 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5227 /* reg_pbmc_buf_lossy
5228 * The field indicates if the buffer is lossy.
5233 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5235 /* reg_pbmc_buf_epsb
5236 * Eligible for Port Shared buffer.
5237 * If epsb is set, packets assigned to buffer are allowed to insert the port
5239 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
5242 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5244 /* reg_pbmc_buf_size
5245 * The part of the packet buffer array is allocated for the specific buffer.
5246 * Units are represented in cells.
5249 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5251 /* reg_pbmc_buf_xoff_threshold
5252 * Once the amount of data in the buffer goes above this value, device
5253 * starts sending PFC frames for all priorities associated with the
5254 * buffer. Units are represented in cells. Reserved in case of lossy
5258 * Note: In Spectrum, reserved for buffer[9].
5260 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5263 /* reg_pbmc_buf_xon_threshold
5264 * When the amount of data in the buffer goes below this value, device
5265 * stops sending PFC frames for the priorities associated with the
5266 * buffer. Units are represented in cells. Reserved in case of lossy
5270 * Note: In Spectrum, reserved for buffer[9].
5272 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5275 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5276 u16 xoff_timer_value, u16 xoff_refresh)
5278 MLXSW_REG_ZERO(pbmc, payload);
5279 mlxsw_reg_pbmc_local_port_set(payload, local_port);
5280 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5281 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5284 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5288 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5289 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5290 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5293 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5294 int buf_index, u16 size,
5297 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5298 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5299 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5300 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5301 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5304 /* PSPA - Port Switch Partition Allocation
5305 * ---------------------------------------
5306 * Controls the association of a port with a switch partition and enables
5307 * configuring ports as stacking ports.
5309 #define MLXSW_REG_PSPA_ID 0x500D
5310 #define MLXSW_REG_PSPA_LEN 0x8
5312 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5315 * Switch partition ID.
5318 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5320 /* reg_pspa_local_port
5321 * Local port number.
5324 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5326 /* reg_pspa_sub_port
5327 * Virtual port within the local port. Set to 0 when virtual ports are
5328 * disabled on the local port.
5331 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5333 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5335 MLXSW_REG_ZERO(pspa, payload);
5336 mlxsw_reg_pspa_swid_set(payload, swid);
5337 mlxsw_reg_pspa_local_port_set(payload, local_port);
5338 mlxsw_reg_pspa_sub_port_set(payload, 0);
5341 /* PPLR - Port Physical Loopback Register
5342 * --------------------------------------
5343 * This register allows configuration of the port's loopback mode.
5345 #define MLXSW_REG_PPLR_ID 0x5018
5346 #define MLXSW_REG_PPLR_LEN 0x8
5348 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5350 /* reg_pplr_local_port
5351 * Local port number.
5354 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5356 /* Phy local loopback. When set the port's egress traffic is looped back
5357 * to the receiver and the port transmitter is disabled.
5359 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5365 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5367 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5370 MLXSW_REG_ZERO(pplr, payload);
5371 mlxsw_reg_pplr_local_port_set(payload, local_port);
5372 mlxsw_reg_pplr_lb_en_set(payload,
5374 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5377 /* HTGT - Host Trap Group Table
5378 * ----------------------------
5379 * Configures the properties for forwarding to CPU.
5381 #define MLXSW_REG_HTGT_ID 0x7002
5382 #define MLXSW_REG_HTGT_LEN 0x20
5384 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5387 * Switch partition ID.
5390 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5392 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
5398 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5400 enum mlxsw_reg_htgt_trap_group {
5401 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5402 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
5403 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
5404 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5405 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5406 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5407 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
5408 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5409 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5410 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5411 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5412 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
5413 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
5414 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5415 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
5416 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5417 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5418 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
5419 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5420 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
5421 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
5422 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5423 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
5424 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
5426 __MLXSW_REG_HTGT_TRAP_GROUP_MAX,
5427 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
5430 enum mlxsw_reg_htgt_discard_trap_group {
5431 MLXSW_REG_HTGT_DISCARD_TRAP_GROUP_BASE = MLXSW_REG_HTGT_TRAP_GROUP_MAX,
5432 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
5435 /* reg_htgt_trap_group
5436 * Trap group number. User defined number specifying which trap groups
5437 * should be forwarded to the CPU. The mapping between trap IDs and trap
5438 * groups is configured using HPKT register.
5441 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5444 MLXSW_REG_HTGT_POLICER_DISABLE,
5445 MLXSW_REG_HTGT_POLICER_ENABLE,
5449 * Enable policer ID specified using 'pid' field.
5452 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
5454 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff
5457 * Policer ID for the trap group.
5460 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
5462 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
5464 /* reg_htgt_mirror_action
5465 * Mirror action to use.
5467 * 1 - Trap to CPU and mirror to a mirroring agent.
5468 * 2 - Mirror to a mirroring agent and do not trap to CPU.
5471 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
5473 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
5475 /* reg_htgt_mirroring_agent
5479 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
5481 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
5483 /* reg_htgt_priority
5484 * Trap group priority.
5485 * In case a packet matches multiple classification rules, the packet will
5486 * only be trapped once, based on the trap ID associated with the group (via
5487 * register HPKT) with the highest priority.
5488 * Supported values are 0-7, with 7 represnting the highest priority.
5491 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
5492 * by the 'trap_group' field.
5494 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
5496 #define MLXSW_REG_HTGT_DEFAULT_TC 7
5498 /* reg_htgt_local_path_cpu_tclass
5499 * CPU ingress traffic class for the trap group.
5502 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
5504 enum mlxsw_reg_htgt_local_path_rdq {
5505 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
5506 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
5507 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
5508 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
5510 /* reg_htgt_local_path_rdq
5511 * Receive descriptor queue (RDQ) to use for the trap group.
5514 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
5516 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
5519 MLXSW_REG_ZERO(htgt, payload);
5521 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
5522 mlxsw_reg_htgt_pide_set(payload,
5523 MLXSW_REG_HTGT_POLICER_DISABLE);
5525 mlxsw_reg_htgt_pide_set(payload,
5526 MLXSW_REG_HTGT_POLICER_ENABLE);
5527 mlxsw_reg_htgt_pid_set(payload, policer_id);
5530 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
5531 mlxsw_reg_htgt_trap_group_set(payload, group);
5532 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
5533 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
5534 mlxsw_reg_htgt_priority_set(payload, priority);
5535 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
5536 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
5539 /* HPKT - Host Packet Trap
5540 * -----------------------
5541 * Configures trap IDs inside trap groups.
5543 #define MLXSW_REG_HPKT_ID 0x7003
5544 #define MLXSW_REG_HPKT_LEN 0x10
5546 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
5549 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
5550 MLXSW_REG_HPKT_ACK_REQUIRED,
5554 * Require acknowledgements from the host for events.
5555 * If set, then the device will wait for the event it sent to be acknowledged
5556 * by the host. This option is only relevant for event trap IDs.
5559 * Note: Currently not supported by firmware.
5561 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
5563 enum mlxsw_reg_hpkt_action {
5564 MLXSW_REG_HPKT_ACTION_FORWARD,
5565 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
5566 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
5567 MLXSW_REG_HPKT_ACTION_DISCARD,
5568 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
5569 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
5570 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
5571 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
5575 * Action to perform on packet when trapped.
5576 * 0 - No action. Forward to CPU based on switching rules.
5577 * 1 - Trap to CPU (CPU receives sole copy).
5578 * 2 - Mirror to CPU (CPU receives a replica of the packet).
5580 * 4 - Soft discard (allow other traps to act on the packet).
5581 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
5582 * 6 - Trap to CPU (CPU receives sole copy) and count it as error.
5583 * 15 - Restore the firmware's default action.
5586 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
5587 * addressed to the CPU.
5589 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
5591 /* reg_hpkt_trap_group
5592 * Trap group to associate the trap with.
5595 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
5601 * Note: A trap ID can only be associated with a single trap group. The device
5602 * will associate the trap ID with the last trap group configured.
5604 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
5607 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
5608 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
5609 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
5613 * Configure dedicated buffer resources for control packets.
5614 * Ignored by SwitchX-2.
5615 * 0 - Keep factory defaults.
5616 * 1 - Do not use control buffer for this trap ID.
5617 * 2 - Use control buffer for this trap ID.
5620 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
5622 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
5623 enum mlxsw_reg_htgt_trap_group trap_group,
5626 MLXSW_REG_ZERO(hpkt, payload);
5627 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
5628 mlxsw_reg_hpkt_action_set(payload, action);
5629 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
5630 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
5631 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
5632 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
5633 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
5636 /* RGCR - Router General Configuration Register
5637 * --------------------------------------------
5638 * The register is used for setting up the router configuration.
5640 #define MLXSW_REG_RGCR_ID 0x8001
5641 #define MLXSW_REG_RGCR_LEN 0x28
5643 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
5646 * IPv4 router enable.
5649 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
5652 * IPv6 router enable.
5655 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
5657 /* reg_rgcr_max_router_interfaces
5658 * Defines the maximum number of active router interfaces for all virtual
5662 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
5665 * Update switch priority and packet color.
5666 * 0 - Preserve the value of Switch Priority and packet color.
5667 * 1 - Recalculate the value of Switch Priority and packet color.
5670 * Note: Not supported by SwitchX and SwitchX-2.
5672 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
5675 * Indicates how to handle the pcp_rewrite_en value:
5676 * 0 - Preserve the value of pcp_rewrite_en.
5677 * 2 - Disable PCP rewrite.
5678 * 3 - Enable PCP rewrite.
5681 * Note: Not supported by SwitchX and SwitchX-2.
5683 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
5685 /* reg_rgcr_activity_dis
5687 * 0 - Activity will be set when an entry is hit (default).
5688 * 1 - Activity will not be set when an entry is hit.
5690 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
5692 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
5694 * Bits 2:7 are reserved.
5697 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
5699 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
5701 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
5704 MLXSW_REG_ZERO(rgcr, payload);
5705 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
5706 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
5709 /* RITR - Router Interface Table Register
5710 * --------------------------------------
5711 * The register is used to configure the router interface table.
5713 #define MLXSW_REG_RITR_ID 0x8002
5714 #define MLXSW_REG_RITR_LEN 0x40
5716 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
5719 * Enables routing on the router interface.
5722 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
5725 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
5729 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
5732 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
5736 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
5739 * IPv4 multicast routing enable.
5742 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
5745 * IPv6 multicast routing enable.
5748 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
5750 enum mlxsw_reg_ritr_if_type {
5751 /* VLAN interface. */
5752 MLXSW_REG_RITR_VLAN_IF,
5753 /* FID interface. */
5754 MLXSW_REG_RITR_FID_IF,
5755 /* Sub-port interface. */
5756 MLXSW_REG_RITR_SP_IF,
5757 /* Loopback Interface. */
5758 MLXSW_REG_RITR_LOOPBACK_IF,
5762 * Router interface type as per enum mlxsw_reg_ritr_if_type.
5765 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
5768 MLXSW_REG_RITR_RIF_CREATE,
5769 MLXSW_REG_RITR_RIF_DEL,
5774 * 0 - Create or edit RIF.
5776 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
5777 * is not supported. An interface must be deleted and re-created in order
5778 * to update properties.
5781 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
5784 * Router interface index. A pointer to the Router Interface Table.
5787 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
5790 * IPv4 Forwarding Enable.
5791 * Enables routing of IPv4 traffic on the router interface. When disabled,
5792 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5793 * Not supported in SwitchX-2.
5796 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
5799 * IPv6 Forwarding Enable.
5800 * Enables routing of IPv6 traffic on the router interface. When disabled,
5801 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
5802 * Not supported in SwitchX-2.
5805 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
5807 /* reg_ritr_ipv4_mc_fe
5808 * IPv4 Multicast Forwarding Enable.
5809 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5813 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
5815 /* reg_ritr_ipv6_mc_fe
5816 * IPv6 Multicast Forwarding Enable.
5817 * When disabled, forwarding is blocked but local traffic (traps and IP to me)
5821 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
5824 * Loop-back filter enable for unicast packets.
5825 * If the flag is set then loop-back filter for unicast packets is
5826 * implemented on the RIF. Multicast packets are always subject to
5827 * loop-back filtering.
5830 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
5832 /* reg_ritr_virtual_router
5833 * Virtual router ID associated with the router interface.
5836 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
5839 * Router interface MTU.
5842 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
5845 * Switch partition ID.
5848 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
5851 * Router interface MAC address.
5852 * In Spectrum, all MAC addresses must have the same 38 MSBits.
5855 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
5857 /* reg_ritr_if_vrrp_id_ipv6
5859 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5862 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
5864 /* reg_ritr_if_vrrp_id_ipv4
5866 * Note: Reserved for RIF types other than VLAN, FID and Sub-port.
5869 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
5871 /* VLAN Interface */
5873 /* reg_ritr_vlan_if_vid
5877 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
5881 /* reg_ritr_fid_if_fid
5882 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
5883 * the vFID range are supported.
5886 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
5888 static inline void mlxsw_reg_ritr_fid_set(char *payload,
5889 enum mlxsw_reg_ritr_if_type rif_type,
5892 if (rif_type == MLXSW_REG_RITR_FID_IF)
5893 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
5895 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
5898 /* Sub-port Interface */
5900 /* reg_ritr_sp_if_lag
5901 * LAG indication. When this bit is set the system_port field holds the
5905 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
5907 /* reg_ritr_sp_system_port
5908 * Port unique indentifier. When lag bit is set, this field holds the
5909 * lag_id in bits 0:9.
5912 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
5914 /* reg_ritr_sp_if_vid
5918 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
5920 /* Loopback Interface */
5922 enum mlxsw_reg_ritr_loopback_protocol {
5923 /* IPinIP IPv4 underlay Unicast */
5924 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5925 /* IPinIP IPv6 underlay Unicast */
5926 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
5927 /* IPinIP generic - used for Spectrum-2 underlay RIF */
5928 MLXSW_REG_RITR_LOOPBACK_GENERIC,
5931 /* reg_ritr_loopback_protocol
5934 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
5936 enum mlxsw_reg_ritr_loopback_ipip_type {
5937 /* Tunnel is IPinIP. */
5938 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
5939 /* Tunnel is GRE, no key. */
5940 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
5941 /* Tunnel is GRE, with a key. */
5942 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
5945 /* reg_ritr_loopback_ipip_type
5946 * Encapsulation type.
5949 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
5951 enum mlxsw_reg_ritr_loopback_ipip_options {
5952 /* The key is defined by gre_key. */
5953 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
5956 /* reg_ritr_loopback_ipip_options
5959 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
5961 /* reg_ritr_loopback_ipip_uvr
5962 * Underlay Virtual Router ID.
5963 * Range is 0..cap_max_virtual_routers-1.
5964 * Reserved for Spectrum-2.
5967 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
5969 /* reg_ritr_loopback_ipip_underlay_rif
5970 * Underlay ingress router interface.
5971 * Reserved for Spectrum.
5974 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
5976 /* reg_ritr_loopback_ipip_usip*
5977 * Encapsulation Underlay source IP.
5980 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
5981 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
5983 /* reg_ritr_loopback_ipip_gre_key
5985 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP.
5988 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
5990 /* Shared between ingress/egress */
5991 enum mlxsw_reg_ritr_counter_set_type {
5993 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
5994 /* Basic. Used for router interfaces, counting the following:
5995 * - Error and Discard counters.
5996 * - Unicast, Multicast and Broadcast counters. Sharing the
5997 * same set of counters for the different type of traffic
5998 * (IPv4, IPv6 and mpls).
6000 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
6003 /* reg_ritr_ingress_counter_index
6004 * Counter Index for flow counter.
6007 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
6009 /* reg_ritr_ingress_counter_set_type
6010 * Igress Counter Set Type for router interface counter.
6013 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6015 /* reg_ritr_egress_counter_index
6016 * Counter Index for flow counter.
6019 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6021 /* reg_ritr_egress_counter_set_type
6022 * Egress Counter Set Type for router interface counter.
6025 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6027 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6028 bool enable, bool egress)
6030 enum mlxsw_reg_ritr_counter_set_type set_type;
6033 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6035 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6036 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6039 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6041 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6044 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6046 MLXSW_REG_ZERO(ritr, payload);
6047 mlxsw_reg_ritr_rif_set(payload, rif);
6050 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6051 u16 system_port, u16 vid)
6053 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6054 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6055 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6058 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6059 enum mlxsw_reg_ritr_if_type type,
6060 u16 rif, u16 vr_id, u16 mtu)
6062 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6064 MLXSW_REG_ZERO(ritr, payload);
6065 mlxsw_reg_ritr_enable_set(payload, enable);
6066 mlxsw_reg_ritr_ipv4_set(payload, 1);
6067 mlxsw_reg_ritr_ipv6_set(payload, 1);
6068 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6069 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6070 mlxsw_reg_ritr_type_set(payload, type);
6071 mlxsw_reg_ritr_op_set(payload, op);
6072 mlxsw_reg_ritr_rif_set(payload, rif);
6073 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6074 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6075 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6076 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6077 mlxsw_reg_ritr_lb_en_set(payload, 1);
6078 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6079 mlxsw_reg_ritr_mtu_set(payload, mtu);
6082 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6084 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6088 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6089 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6090 enum mlxsw_reg_ritr_loopback_ipip_options options,
6091 u16 uvr_id, u16 underlay_rif, u32 gre_key)
6093 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6094 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6095 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6096 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6097 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6101 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6102 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6103 enum mlxsw_reg_ritr_loopback_ipip_options options,
6104 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6106 mlxsw_reg_ritr_loopback_protocol_set(payload,
6107 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6108 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6109 uvr_id, underlay_rif, gre_key);
6110 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6113 /* RTAR - Router TCAM Allocation Register
6114 * --------------------------------------
6115 * This register is used for allocation of regions in the TCAM table.
6117 #define MLXSW_REG_RTAR_ID 0x8004
6118 #define MLXSW_REG_RTAR_LEN 0x20
6120 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6122 enum mlxsw_reg_rtar_op {
6123 MLXSW_REG_RTAR_OP_ALLOCATE,
6124 MLXSW_REG_RTAR_OP_RESIZE,
6125 MLXSW_REG_RTAR_OP_DEALLOCATE,
6131 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6133 enum mlxsw_reg_rtar_key_type {
6134 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6135 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6138 /* reg_rtar_key_type
6139 * TCAM key type for the region.
6142 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6144 /* reg_rtar_region_size
6145 * TCAM region size. When allocating/resizing this is the requested
6146 * size, the response is the actual size.
6147 * Note: Actual size may be larger than requested.
6148 * Reserved for op = Deallocate
6151 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6153 static inline void mlxsw_reg_rtar_pack(char *payload,
6154 enum mlxsw_reg_rtar_op op,
6155 enum mlxsw_reg_rtar_key_type key_type,
6158 MLXSW_REG_ZERO(rtar, payload);
6159 mlxsw_reg_rtar_op_set(payload, op);
6160 mlxsw_reg_rtar_key_type_set(payload, key_type);
6161 mlxsw_reg_rtar_region_size_set(payload, region_size);
6164 /* RATR - Router Adjacency Table Register
6165 * --------------------------------------
6166 * The RATR register is used to configure the Router Adjacency (next-hop)
6169 #define MLXSW_REG_RATR_ID 0x8008
6170 #define MLXSW_REG_RATR_LEN 0x2C
6172 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6174 enum mlxsw_reg_ratr_op {
6176 MLXSW_REG_RATR_OP_QUERY_READ = 0,
6177 /* Read and clear activity */
6178 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6179 /* Write Adjacency entry */
6180 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6181 /* Write Adjacency entry only if the activity is cleared.
6182 * The write may not succeed if the activity is set. There is not
6183 * direct feedback if the write has succeeded or not, however
6184 * the get will reveal the actual entry (SW can compare the get
6185 * response to the set command).
6187 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6191 * Note that Write operation may also be used for updating
6192 * counter_set_type and counter_index. In this case all other
6193 * fields must not be updated.
6196 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6199 * Valid bit. Indicates if the adjacency entry is valid.
6200 * Note: the device may need some time before reusing an invalidated
6201 * entry. During this time the entry can not be reused. It is
6202 * recommended to use another entry before reusing an invalidated
6203 * entry (e.g. software can put it at the end of the list for
6204 * reusing). Trying to access an invalidated entry not yet cleared
6205 * by the device results with failure indicating "Try Again" status.
6206 * When valid is '0' then egress_router_interface,trap_action,
6207 * adjacency_parameters and counters are reserved
6210 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6213 * Activity. Set for new entries. Set if a packet lookup has hit on
6214 * the specific entry. To clear the a bit, use "clear activity".
6217 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6219 enum mlxsw_reg_ratr_type {
6221 MLXSW_REG_RATR_TYPE_ETHERNET,
6222 /* IPoIB Unicast without GRH.
6223 * Reserved for Spectrum.
6225 MLXSW_REG_RATR_TYPE_IPOIB_UC,
6226 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast
6228 * Reserved for Spectrum.
6230 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6232 * Reserved for Spectrum.
6234 MLXSW_REG_RATR_TYPE_IPOIB_MC,
6236 * Reserved for SwitchX/-2.
6238 MLXSW_REG_RATR_TYPE_MPLS,
6240 * Reserved for SwitchX/-2.
6242 MLXSW_REG_RATR_TYPE_IPIP,
6246 * Adjacency entry type.
6249 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6251 /* reg_ratr_adjacency_index_low
6252 * Bits 15:0 of index into the adjacency table.
6253 * For SwitchX and SwitchX-2, the adjacency table is linear and
6254 * used for adjacency entries only.
6255 * For Spectrum, the index is to the KVD linear.
6258 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6260 /* reg_ratr_egress_router_interface
6261 * Range is 0 .. cap_max_router_interfaces - 1
6264 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6266 enum mlxsw_reg_ratr_trap_action {
6267 MLXSW_REG_RATR_TRAP_ACTION_NOP,
6268 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6269 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6270 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6271 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6274 /* reg_ratr_trap_action
6275 * see mlxsw_reg_ratr_trap_action
6278 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6280 /* reg_ratr_adjacency_index_high
6281 * Bits 23:16 of the adjacency_index.
6284 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6286 enum mlxsw_reg_ratr_trap_id {
6287 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6288 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6292 * Trap ID to be reported to CPU.
6293 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
6294 * For trap_action of NOP, MIRROR and DISCARD_ERROR
6297 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6299 /* reg_ratr_eth_destination_mac
6300 * MAC address of the destination next-hop.
6303 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6305 enum mlxsw_reg_ratr_ipip_type {
6306 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */
6307 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6308 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */
6309 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6312 /* reg_ratr_ipip_type
6313 * Underlay destination ip type.
6314 * Note: the type field must match the protocol of the router interface.
6317 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6319 /* reg_ratr_ipip_ipv4_udip
6320 * Underlay ipv4 dip.
6321 * Reserved when ipip_type is IPv6.
6324 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6326 /* reg_ratr_ipip_ipv6_ptr
6327 * Pointer to IPv6 underlay destination ip address.
6328 * For Spectrum: Pointer to KVD linear space.
6331 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6333 enum mlxsw_reg_flow_counter_set_type {
6335 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6336 /* Count packets and bytes */
6337 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6338 /* Count only packets */
6339 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6342 /* reg_ratr_counter_set_type
6343 * Counter set type for flow counters
6346 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6348 /* reg_ratr_counter_index
6349 * Counter index for flow counters
6352 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6355 mlxsw_reg_ratr_pack(char *payload,
6356 enum mlxsw_reg_ratr_op op, bool valid,
6357 enum mlxsw_reg_ratr_type type,
6358 u32 adjacency_index, u16 egress_rif)
6360 MLXSW_REG_ZERO(ratr, payload);
6361 mlxsw_reg_ratr_op_set(payload, op);
6362 mlxsw_reg_ratr_v_set(payload, valid);
6363 mlxsw_reg_ratr_type_set(payload, type);
6364 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6365 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6366 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6369 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6370 const char *dest_mac)
6372 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6375 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6377 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6378 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6381 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6382 bool counter_enable)
6384 enum mlxsw_reg_flow_counter_set_type set_type;
6387 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6389 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6391 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6392 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6395 /* RDPM - Router DSCP to Priority Mapping
6396 * --------------------------------------
6397 * Controls the mapping from DSCP field to switch priority on routed packets
6399 #define MLXSW_REG_RDPM_ID 0x8009
6400 #define MLXSW_REG_RDPM_BASE_LEN 0x00
6401 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6402 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6403 #define MLXSW_REG_RDPM_LEN 0x40
6404 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6405 MLXSW_REG_RDPM_LEN - \
6406 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6408 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6411 * Enable update of the specific entry
6414 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6415 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6417 /* reg_dscp_entry_prio
6421 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6422 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6424 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6427 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6428 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6431 /* RICNT - Router Interface Counter Register
6432 * -----------------------------------------
6433 * The RICNT register retrieves per port performance counters
6435 #define MLXSW_REG_RICNT_ID 0x800B
6436 #define MLXSW_REG_RICNT_LEN 0x100
6438 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6440 /* reg_ricnt_counter_index
6444 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6446 enum mlxsw_reg_ricnt_counter_set_type {
6448 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6449 /* Basic. Used for router interfaces, counting the following:
6450 * - Error and Discard counters.
6451 * - Unicast, Multicast and Broadcast counters. Sharing the
6452 * same set of counters for the different type of traffic
6453 * (IPv4, IPv6 and mpls).
6455 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
6458 /* reg_ricnt_counter_set_type
6459 * Counter Set Type for router interface counter
6462 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
6464 enum mlxsw_reg_ricnt_opcode {
6465 /* Nop. Supported only for read access*/
6466 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
6467 /* Clear. Setting the clr bit will reset the counter value for
6468 * all counters of the specified Router Interface.
6470 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
6477 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
6479 /* reg_ricnt_good_unicast_packets
6480 * good unicast packets.
6483 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
6485 /* reg_ricnt_good_multicast_packets
6486 * good multicast packets.
6489 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
6491 /* reg_ricnt_good_broadcast_packets
6492 * good broadcast packets
6495 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
6497 /* reg_ricnt_good_unicast_bytes
6498 * A count of L3 data and padding octets not including L2 headers
6499 * for good unicast frames.
6502 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
6504 /* reg_ricnt_good_multicast_bytes
6505 * A count of L3 data and padding octets not including L2 headers
6506 * for good multicast frames.
6509 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
6511 /* reg_ritr_good_broadcast_bytes
6512 * A count of L3 data and padding octets not including L2 headers
6513 * for good broadcast frames.
6516 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
6518 /* reg_ricnt_error_packets
6519 * A count of errored frames that do not pass the router checks.
6522 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
6524 /* reg_ricnt_discrad_packets
6525 * A count of non-errored frames that do not pass the router checks.
6528 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
6530 /* reg_ricnt_error_bytes
6531 * A count of L3 data and padding octets not including L2 headers
6532 * for errored frames.
6535 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
6537 /* reg_ricnt_discard_bytes
6538 * A count of L3 data and padding octets not including L2 headers
6539 * for non-errored frames that do not pass the router checks.
6542 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
6544 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
6545 enum mlxsw_reg_ricnt_opcode op)
6547 MLXSW_REG_ZERO(ricnt, payload);
6548 mlxsw_reg_ricnt_op_set(payload, op);
6549 mlxsw_reg_ricnt_counter_index_set(payload, index);
6550 mlxsw_reg_ricnt_counter_set_type_set(payload,
6551 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
6554 /* RRCR - Router Rules Copy Register Layout
6555 * ----------------------------------------
6556 * This register is used for moving and copying route entry rules.
6558 #define MLXSW_REG_RRCR_ID 0x800F
6559 #define MLXSW_REG_RRCR_LEN 0x24
6561 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
6563 enum mlxsw_reg_rrcr_op {
6565 MLXSW_REG_RRCR_OP_MOVE,
6567 MLXSW_REG_RRCR_OP_COPY,
6573 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
6576 * Offset within the region from which to copy/move.
6579 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
6582 * The number of rules to copy/move.
6585 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
6587 /* reg_rrcr_table_id
6588 * Identifier of the table on which to perform the operation. Encoding is the
6589 * same as in RTAR.key_type
6592 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
6594 /* reg_rrcr_dest_offset
6595 * Offset within the region to which to copy/move
6598 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
6600 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
6601 u16 offset, u16 size,
6602 enum mlxsw_reg_rtar_key_type table_id,
6605 MLXSW_REG_ZERO(rrcr, payload);
6606 mlxsw_reg_rrcr_op_set(payload, op);
6607 mlxsw_reg_rrcr_offset_set(payload, offset);
6608 mlxsw_reg_rrcr_size_set(payload, size);
6609 mlxsw_reg_rrcr_table_id_set(payload, table_id);
6610 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
6613 /* RALTA - Router Algorithmic LPM Tree Allocation Register
6614 * -------------------------------------------------------
6615 * RALTA is used to allocate the LPM trees of the SHSPM method.
6617 #define MLXSW_REG_RALTA_ID 0x8010
6618 #define MLXSW_REG_RALTA_LEN 0x04
6620 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
6623 * opcode (valid for Write, must be 0 on Read)
6624 * 0 - allocate a tree
6625 * 1 - deallocate a tree
6628 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
6630 enum mlxsw_reg_ralxx_protocol {
6631 MLXSW_REG_RALXX_PROTOCOL_IPV4,
6632 MLXSW_REG_RALXX_PROTOCOL_IPV6,
6635 /* reg_ralta_protocol
6637 * Deallocation opcode: Reserved.
6640 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
6642 /* reg_ralta_tree_id
6643 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing
6644 * the tree identifier (managed by software).
6645 * Note that tree_id 0 is allocated for a default-route tree.
6648 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
6650 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
6651 enum mlxsw_reg_ralxx_protocol protocol,
6654 MLXSW_REG_ZERO(ralta, payload);
6655 mlxsw_reg_ralta_op_set(payload, !alloc);
6656 mlxsw_reg_ralta_protocol_set(payload, protocol);
6657 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
6660 /* RALST - Router Algorithmic LPM Structure Tree Register
6661 * ------------------------------------------------------
6662 * RALST is used to set and query the structure of an LPM tree.
6663 * The structure of the tree must be sorted as a sorted binary tree, while
6664 * each node is a bin that is tagged as the length of the prefixes the lookup
6665 * will refer to. Therefore, bin X refers to a set of entries with prefixes
6666 * of X bits to match with the destination address. The bin 0 indicates
6667 * the default action, when there is no match of any prefix.
6669 #define MLXSW_REG_RALST_ID 0x8011
6670 #define MLXSW_REG_RALST_LEN 0x104
6672 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
6674 /* reg_ralst_root_bin
6675 * The bin number of the root bin.
6676 * 0<root_bin=<(length of IP address)
6677 * For a default-route tree configure 0xff
6680 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
6682 /* reg_ralst_tree_id
6683 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6686 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
6688 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
6689 #define MLXSW_REG_RALST_BIN_OFFSET 0x04
6690 #define MLXSW_REG_RALST_BIN_COUNT 128
6692 /* reg_ralst_left_child_bin
6693 * Holding the children of the bin according to the stored tree's structure.
6694 * For trees composed of less than 4 blocks, the bins in excess are reserved.
6695 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6698 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
6700 /* reg_ralst_right_child_bin
6701 * Holding the children of the bin according to the stored tree's structure.
6702 * For trees composed of less than 4 blocks, the bins in excess are reserved.
6703 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff
6706 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
6709 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
6711 MLXSW_REG_ZERO(ralst, payload);
6713 /* Initialize all bins to have no left or right child */
6714 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
6715 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
6717 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
6718 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
6721 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
6725 int bin_index = bin_number - 1;
6727 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
6728 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
6732 /* RALTB - Router Algorithmic LPM Tree Binding Register
6733 * ----------------------------------------------------
6734 * RALTB is used to bind virtual router and protocol to an allocated LPM tree.
6736 #define MLXSW_REG_RALTB_ID 0x8012
6737 #define MLXSW_REG_RALTB_LEN 0x04
6739 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
6741 /* reg_raltb_virtual_router
6743 * Range is 0..cap_max_virtual_routers-1
6746 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
6748 /* reg_raltb_protocol
6752 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
6754 /* reg_raltb_tree_id
6755 * Tree to be used for the {virtual_router, protocol}
6756 * Tree identifier numbered from 1..(cap_shspm_max_trees-1).
6757 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0.
6760 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
6762 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
6763 enum mlxsw_reg_ralxx_protocol protocol,
6766 MLXSW_REG_ZERO(raltb, payload);
6767 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
6768 mlxsw_reg_raltb_protocol_set(payload, protocol);
6769 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
6772 /* RALUE - Router Algorithmic LPM Unicast Entry Register
6773 * -----------------------------------------------------
6774 * RALUE is used to configure and query LPM entries that serve
6775 * the Unicast protocols.
6777 #define MLXSW_REG_RALUE_ID 0x8013
6778 #define MLXSW_REG_RALUE_LEN 0x38
6780 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
6782 /* reg_ralue_protocol
6786 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
6788 enum mlxsw_reg_ralue_op {
6789 /* Read operation. If entry doesn't exist, the operation fails. */
6790 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
6791 /* Clear on read operation. Used to read entry and
6792 * clear Activity bit.
6794 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
6795 /* Write operation. Used to write a new entry to the table. All RW
6796 * fields are written for new entry. Activity bit is set
6799 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
6800 /* Update operation. Used to update an existing route entry and
6801 * only update the RW fields that are detailed in the field
6802 * op_u_mask. If entry doesn't exist, the operation fails.
6804 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
6805 /* Clear activity. The Activity bit (the field a) is cleared
6808 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
6809 /* Delete operation. Used to delete an existing entry. If entry
6810 * doesn't exist, the operation fails.
6812 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
6819 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
6822 * Activity. Set for new entries. Set if a packet lookup has hit on the
6823 * specific entry, only if the entry is a route. To clear the a bit, use
6824 * "clear activity" op.
6825 * Enabled by activity_dis in RGCR
6828 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
6830 /* reg_ralue_virtual_router
6832 * Range is 0..cap_max_virtual_routers-1
6835 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
6837 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
6838 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
6839 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
6841 /* reg_ralue_op_u_mask
6842 * opcode update mask.
6843 * On read operation, this field is reserved.
6844 * This field is valid for update opcode, otherwise - reserved.
6845 * This field is a bitmask of the fields that should be updated.
6848 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
6850 /* reg_ralue_prefix_len
6851 * Number of bits in the prefix of the LPM route.
6852 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes
6853 * two entries in the physical HW table.
6856 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
6859 * The prefix of the route or of the marker that the object of the LPM
6860 * is compared with. The most significant bits of the dip are the prefix.
6861 * The least significant bits must be '0' if the prefix_len is smaller
6862 * than 128 for IPv6 or smaller than 32 for IPv4.
6863 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved.
6866 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
6867 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
6869 enum mlxsw_reg_ralue_entry_type {
6870 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
6871 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
6872 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
6875 /* reg_ralue_entry_type
6877 * Note - for Marker entries, the action_type and action fields are reserved.
6880 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
6882 /* reg_ralue_bmp_len
6883 * The best match prefix length in the case that there is no match for
6885 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
6886 * Note for any update operation with entry_type modification this
6887 * field must be set.
6890 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
6892 enum mlxsw_reg_ralue_action_type {
6893 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
6894 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
6895 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
6898 /* reg_ralue_action_type
6900 * Indicates how the IP address is connected.
6901 * It can be connected to a local subnet through local_erif or can be
6902 * on a remote subnet connected through a next-hop router,
6903 * or transmitted to the CPU.
6904 * Reserved when entry_type = MARKER_ENTRY
6907 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
6909 enum mlxsw_reg_ralue_trap_action {
6910 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
6911 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
6912 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
6913 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
6914 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
6917 /* reg_ralue_trap_action
6919 * For IP2ME action, only NOP and MIRROR are possible.
6922 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
6924 /* reg_ralue_trap_id
6925 * Trap ID to be reported to CPU.
6926 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1.
6927 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved.
6930 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
6932 /* reg_ralue_adjacency_index
6933 * Points to the first entry of the group-based ECMP.
6934 * Only relevant in case of REMOTE action.
6937 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
6939 /* reg_ralue_ecmp_size
6940 * Amount of sequential entries starting
6941 * from the adjacency_index (the number of ECMPs).
6942 * The valid range is 1-64, 512, 1024, 2048 and 4096.
6943 * Reserved when trap_action is TRAP or DISCARD_ERROR.
6944 * Only relevant in case of REMOTE action.
6947 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
6949 /* reg_ralue_local_erif
6950 * Egress Router Interface.
6951 * Only relevant in case of LOCAL action.
6954 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
6956 /* reg_ralue_ip2me_v
6957 * Valid bit for the tunnel_ptr field.
6958 * If valid = 0 then trap to CPU as IP2ME trap ID.
6959 * If valid = 1 and the packet format allows NVE or IPinIP tunnel
6960 * decapsulation then tunnel decapsulation is done.
6961 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel
6962 * decapsulation then trap as IP2ME trap ID.
6963 * Only relevant in case of IP2ME action.
6966 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
6968 /* reg_ralue_ip2me_tunnel_ptr
6969 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation.
6970 * For Spectrum, pointer to KVD Linear.
6971 * Only relevant in case of IP2ME action.
6974 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
6976 static inline void mlxsw_reg_ralue_pack(char *payload,
6977 enum mlxsw_reg_ralxx_protocol protocol,
6978 enum mlxsw_reg_ralue_op op,
6979 u16 virtual_router, u8 prefix_len)
6981 MLXSW_REG_ZERO(ralue, payload);
6982 mlxsw_reg_ralue_protocol_set(payload, protocol);
6983 mlxsw_reg_ralue_op_set(payload, op);
6984 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
6985 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
6986 mlxsw_reg_ralue_entry_type_set(payload,
6987 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
6988 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
6991 static inline void mlxsw_reg_ralue_pack4(char *payload,
6992 enum mlxsw_reg_ralxx_protocol protocol,
6993 enum mlxsw_reg_ralue_op op,
6994 u16 virtual_router, u8 prefix_len,
6997 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
6998 mlxsw_reg_ralue_dip4_set(payload, dip);
7001 static inline void mlxsw_reg_ralue_pack6(char *payload,
7002 enum mlxsw_reg_ralxx_protocol protocol,
7003 enum mlxsw_reg_ralue_op op,
7004 u16 virtual_router, u8 prefix_len,
7007 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7008 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
7012 mlxsw_reg_ralue_act_remote_pack(char *payload,
7013 enum mlxsw_reg_ralue_trap_action trap_action,
7014 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7016 mlxsw_reg_ralue_action_type_set(payload,
7017 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7018 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7019 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7020 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7021 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7025 mlxsw_reg_ralue_act_local_pack(char *payload,
7026 enum mlxsw_reg_ralue_trap_action trap_action,
7027 u16 trap_id, u16 local_erif)
7029 mlxsw_reg_ralue_action_type_set(payload,
7030 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7031 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7032 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7033 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7037 mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7039 mlxsw_reg_ralue_action_type_set(payload,
7040 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7044 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7046 mlxsw_reg_ralue_action_type_set(payload,
7047 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7048 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7049 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7052 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register
7053 * ----------------------------------------------------------
7054 * The RAUHT register is used to configure and query the Unicast Host table in
7055 * devices that implement the Algorithmic LPM.
7057 #define MLXSW_REG_RAUHT_ID 0x8014
7058 #define MLXSW_REG_RAUHT_LEN 0x74
7060 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7062 enum mlxsw_reg_rauht_type {
7063 MLXSW_REG_RAUHT_TYPE_IPV4,
7064 MLXSW_REG_RAUHT_TYPE_IPV6,
7070 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7072 enum mlxsw_reg_rauht_op {
7073 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7074 /* Read operation */
7075 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7076 /* Clear on read operation. Used to read entry and clear
7079 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7080 /* Add. Used to write a new entry to the table. All R/W fields are
7081 * relevant for new entry. Activity bit is set for new entries.
7083 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7084 /* Update action. Used to update an existing route entry and
7085 * only update the following fields:
7086 * trap_action, trap_id, mac, counter_set_type, counter_index
7088 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7089 /* Clear activity. A bit is cleared for the entry. */
7090 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7092 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7093 /* Delete all host entries on a RIF. In this command, dip
7094 * field is reserved.
7101 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7104 * Activity. Set for new entries. Set if a packet lookup has hit on
7105 * the specific entry.
7106 * To clear the a bit, use "clear activity" op.
7107 * Enabled by activity_dis in RGCR
7110 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7116 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7119 * Destination address.
7122 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7123 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7125 enum mlxsw_reg_rauht_trap_action {
7126 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7127 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7128 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7129 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7130 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7133 /* reg_rauht_trap_action
7136 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7138 enum mlxsw_reg_rauht_trap_id {
7139 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7140 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7143 /* reg_rauht_trap_id
7144 * Trap ID to be reported to CPU.
7145 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1.
7146 * For trap_action of NOP, MIRROR and DISCARD_ERROR,
7147 * trap_id is reserved.
7150 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7152 /* reg_rauht_counter_set_type
7153 * Counter set type for flow counters
7156 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7158 /* reg_rauht_counter_index
7159 * Counter index for flow counters
7162 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7168 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7170 static inline void mlxsw_reg_rauht_pack(char *payload,
7171 enum mlxsw_reg_rauht_op op, u16 rif,
7174 MLXSW_REG_ZERO(rauht, payload);
7175 mlxsw_reg_rauht_op_set(payload, op);
7176 mlxsw_reg_rauht_rif_set(payload, rif);
7177 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7180 static inline void mlxsw_reg_rauht_pack4(char *payload,
7181 enum mlxsw_reg_rauht_op op, u16 rif,
7182 const char *mac, u32 dip)
7184 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7185 mlxsw_reg_rauht_dip4_set(payload, dip);
7188 static inline void mlxsw_reg_rauht_pack6(char *payload,
7189 enum mlxsw_reg_rauht_op op, u16 rif,
7190 const char *mac, const char *dip)
7192 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7193 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7194 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7197 static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7200 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7201 mlxsw_reg_rauht_counter_set_type_set(payload,
7202 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7205 /* RALEU - Router Algorithmic LPM ECMP Update Register
7206 * ---------------------------------------------------
7207 * The register enables updating the ECMP section in the action for multiple
7208 * LPM Unicast entries in a single operation. The update is executed to
7209 * all entries of a {virtual router, protocol} tuple using the same ECMP group.
7211 #define MLXSW_REG_RALEU_ID 0x8015
7212 #define MLXSW_REG_RALEU_LEN 0x28
7214 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7216 /* reg_raleu_protocol
7220 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7222 /* reg_raleu_virtual_router
7224 * Range is 0..cap_max_virtual_routers-1
7227 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7229 /* reg_raleu_adjacency_index
7230 * Adjacency Index used for matching on the existing entries.
7233 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7235 /* reg_raleu_ecmp_size
7236 * ECMP Size used for matching on the existing entries.
7239 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7241 /* reg_raleu_new_adjacency_index
7242 * New Adjacency Index.
7245 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7247 /* reg_raleu_new_ecmp_size
7251 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7253 static inline void mlxsw_reg_raleu_pack(char *payload,
7254 enum mlxsw_reg_ralxx_protocol protocol,
7256 u32 adjacency_index, u16 ecmp_size,
7257 u32 new_adjacency_index,
7260 MLXSW_REG_ZERO(raleu, payload);
7261 mlxsw_reg_raleu_protocol_set(payload, protocol);
7262 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7263 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7264 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7265 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7266 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7269 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register
7270 * ----------------------------------------------------------------
7271 * The RAUHTD register allows dumping entries from the Router Unicast Host
7272 * Table. For a given session an entry is dumped no more than one time. The
7273 * first RAUHTD access after reset is a new session. A session ends when the
7274 * num_rec response is smaller than num_rec request or for IPv4 when the
7275 * num_entries is smaller than 4. The clear activity affect the current session
7276 * or the last session if a new session has not started.
7278 #define MLXSW_REG_RAUHTD_ID 0x8018
7279 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7280 #define MLXSW_REG_RAUHTD_REC_LEN 0x20
7281 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7282 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7283 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7284 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7286 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7288 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7289 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7291 /* reg_rauhtd_filter_fields
7292 * if a bit is '0' then the relevant field is ignored and dump is done
7293 * regardless of the field value
7294 * Bit0 - filter by activity: entry_a
7295 * Bit3 - filter by entry rip: entry_rif
7298 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7300 enum mlxsw_reg_rauhtd_op {
7301 MLXSW_REG_RAUHTD_OP_DUMP,
7302 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7308 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7310 /* reg_rauhtd_num_rec
7311 * At request: number of records requested
7312 * At response: number of records dumped
7313 * For IPv4, each record has 4 entries at request and up to 4 entries
7315 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM
7318 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7320 /* reg_rauhtd_entry_a
7321 * Dump only if activity has value of entry_a
7322 * Reserved if filter_fields bit0 is '0'
7325 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7327 enum mlxsw_reg_rauhtd_type {
7328 MLXSW_REG_RAUHTD_TYPE_IPV4,
7329 MLXSW_REG_RAUHTD_TYPE_IPV6,
7333 * Dump only if record type is:
7338 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7340 /* reg_rauhtd_entry_rif
7341 * Dump only if RIF has value of entry_rif
7342 * Reserved if filter_fields bit3 is '0'
7345 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7347 static inline void mlxsw_reg_rauhtd_pack(char *payload,
7348 enum mlxsw_reg_rauhtd_type type)
7350 MLXSW_REG_ZERO(rauhtd, payload);
7351 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7352 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7353 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7354 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7355 mlxsw_reg_rauhtd_type_set(payload, type);
7358 /* reg_rauhtd_ipv4_rec_num_entries
7359 * Number of valid entries in this record:
7361 * 1 - 2 valid entries
7362 * 2 - 3 valid entries
7363 * 3 - 4 valid entries
7366 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7367 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7368 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7370 /* reg_rauhtd_rec_type
7376 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7377 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7379 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7381 /* reg_rauhtd_ipv4_ent_a
7382 * Activity. Set for new entries. Set if a packet lookup has hit on the
7386 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7387 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7389 /* reg_rauhtd_ipv4_ent_rif
7393 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7394 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7396 /* reg_rauhtd_ipv4_ent_dip
7397 * Destination IPv4 address.
7400 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7401 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7403 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7405 /* reg_rauhtd_ipv6_ent_a
7406 * Activity. Set for new entries. Set if a packet lookup has hit on the
7410 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7411 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7413 /* reg_rauhtd_ipv6_ent_rif
7417 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7418 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7420 /* reg_rauhtd_ipv6_ent_dip
7421 * Destination IPv6 address.
7424 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7425 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7427 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7428 int ent_index, u16 *p_rif,
7431 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7432 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7435 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7436 int rec_index, u16 *p_rif,
7439 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7440 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7443 /* RTDP - Routing Tunnel Decap Properties Register
7444 * -----------------------------------------------
7445 * The RTDP register is used for configuring the tunnel decap properties of NVE
7448 #define MLXSW_REG_RTDP_ID 0x8020
7449 #define MLXSW_REG_RTDP_LEN 0x44
7451 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
7453 enum mlxsw_reg_rtdp_type {
7454 MLXSW_REG_RTDP_TYPE_NVE,
7455 MLXSW_REG_RTDP_TYPE_IPIP,
7459 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type.
7462 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
7464 /* reg_rtdp_tunnel_index
7465 * Index to the Decap entry.
7466 * For Spectrum, Index to KVD Linear.
7469 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
7471 /* reg_rtdp_egress_router_interface
7472 * Underlay egress router interface.
7473 * Valid range is from 0 to cap_max_router_interfaces - 1
7476 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
7480 /* reg_rtdp_ipip_irif
7481 * Ingress Router Interface for the overlay router
7484 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
7486 enum mlxsw_reg_rtdp_ipip_sip_check {
7487 /* No sip checks. */
7488 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
7489 /* Filter packet if underlay is not IPv4 or if underlay SIP does not
7492 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
7493 /* Filter packet if underlay is not IPv6 or if underlay SIP does not
7496 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
7499 /* reg_rtdp_ipip_sip_check
7500 * SIP check to perform. If decapsulation failed due to these configurations
7501 * then trap_id is IPIP_DECAP_ERROR.
7504 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
7506 /* If set, allow decapsulation of IPinIP (without GRE). */
7507 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
7508 /* If set, allow decapsulation of IPinGREinIP without a key. */
7509 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
7510 /* If set, allow decapsulation of IPinGREinIP with a key. */
7511 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
7513 /* reg_rtdp_ipip_type_check
7514 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to
7515 * these configurations then trap_id is IPIP_DECAP_ERROR.
7518 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
7520 /* reg_rtdp_ipip_gre_key_check
7521 * Whether GRE key should be checked. When check is enabled:
7522 * - A packet received as IPinIP (without GRE) will always pass.
7523 * - A packet received as IPinGREinIP without a key will not pass the check.
7524 * - A packet received as IPinGREinIP with a key will pass the check only if the
7525 * key in the packet is equal to expected_gre_key.
7526 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR.
7529 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
7531 /* reg_rtdp_ipip_ipv4_usip
7532 * Underlay IPv4 address for ipv4 source address check.
7533 * Reserved when sip_check is not '1'.
7536 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
7538 /* reg_rtdp_ipip_ipv6_usip_ptr
7539 * This field is valid when sip_check is "sipv6 check explicitly". This is a
7540 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index
7541 * is to the KVD linear.
7542 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6.
7545 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
7547 /* reg_rtdp_ipip_expected_gre_key
7548 * GRE key for checking.
7549 * Reserved when gre_key_check is '0'.
7552 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
7554 static inline void mlxsw_reg_rtdp_pack(char *payload,
7555 enum mlxsw_reg_rtdp_type type,
7558 MLXSW_REG_ZERO(rtdp, payload);
7559 mlxsw_reg_rtdp_type_set(payload, type);
7560 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
7564 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
7565 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
7566 unsigned int type_check, bool gre_key_check,
7567 u32 ipv4_usip, u32 expected_gre_key)
7569 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
7570 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
7571 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
7572 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
7573 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
7574 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
7577 /* RIGR-V2 - Router Interface Group Register Version 2
7578 * ---------------------------------------------------
7579 * The RIGR_V2 register is used to add, remove and query egress interface list
7580 * of a multicast forwarding entry.
7582 #define MLXSW_REG_RIGR2_ID 0x8023
7583 #define MLXSW_REG_RIGR2_LEN 0xB0
7585 #define MLXSW_REG_RIGR2_MAX_ERIFS 32
7587 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
7589 /* reg_rigr2_rigr_index
7593 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
7596 * Next RIGR Index is valid.
7599 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
7601 /* reg_rigr2_next_rigr_index
7602 * Next RIGR Index. The index is to the KVD linear.
7603 * Reserved when vnxet = '0'.
7606 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
7609 * RMID Index is valid.
7612 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
7614 /* reg_rigr2_rmid_index
7616 * Range 0 .. max_mid - 1
7617 * Reserved when vrmid = '0'.
7618 * The index is to the Port Group Table (PGT)
7621 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
7623 /* reg_rigr2_erif_entry_v
7624 * Egress Router Interface is valid.
7625 * Note that low-entries must be set if high-entries are set. For
7626 * example: if erif_entry[2].v is set then erif_entry[1].v and
7627 * erif_entry[0].v must be set.
7628 * Index can be from 0 to cap_mc_erif_list_entries-1
7631 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
7633 /* reg_rigr2_erif_entry_erif
7634 * Egress Router Interface.
7635 * Valid range is from 0 to cap_max_router_interfaces - 1
7636 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1
7639 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
7641 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
7642 bool vnext, u32 next_rigr_index)
7644 MLXSW_REG_ZERO(rigr2, payload);
7645 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
7646 mlxsw_reg_rigr2_vnext_set(payload, vnext);
7647 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
7648 mlxsw_reg_rigr2_vrmid_set(payload, 0);
7649 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
7652 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
7655 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
7656 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
7659 /* RECR-V2 - Router ECMP Configuration Version 2 Register
7660 * ------------------------------------------------------
7662 #define MLXSW_REG_RECR2_ID 0x8025
7663 #define MLXSW_REG_RECR2_LEN 0x38
7665 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
7668 * Per-port configuration
7671 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
7677 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
7683 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
7686 /* Enable IPv4 fields if packet is not TCP and not UDP */
7687 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
7688 /* Enable IPv4 fields if packet is TCP or UDP */
7689 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
7690 /* Enable IPv6 fields if packet is not TCP and not UDP */
7691 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
7692 /* Enable IPv6 fields if packet is TCP or UDP */
7693 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
7694 /* Enable TCP/UDP header fields if packet is IPv4 */
7695 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
7696 /* Enable TCP/UDP header fields if packet is IPv6 */
7697 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
7700 /* reg_recr2_outer_header_enables
7701 * Bit mask where each bit enables a specific layer to be included in
7702 * the hash calculation.
7705 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
7708 /* IPv4 Source IP */
7709 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
7710 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
7711 /* IPv4 Destination IP */
7712 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
7713 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
7715 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
7716 /* IPv6 Source IP */
7717 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
7718 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
7719 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
7720 /* IPv6 Destination IP */
7721 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
7722 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
7723 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
7724 /* IPv6 Next Header */
7725 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
7726 /* IPv6 Flow Label */
7727 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
7728 /* TCP/UDP Source Port */
7729 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
7730 /* TCP/UDP Destination Port */
7731 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
7734 /* reg_recr2_outer_header_fields_enable
7735 * Packet fields to enable for ECMP hash subject to outer_header_enable.
7738 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
7740 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
7744 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
7745 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7749 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
7753 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
7754 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7758 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
7760 int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
7762 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7764 i = MLXSW_REG_RECR2_IPV6_SIP8;
7765 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
7766 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7770 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
7772 int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
7774 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
7776 i = MLXSW_REG_RECR2_IPV6_DIP8;
7777 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
7778 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
7782 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
7784 MLXSW_REG_ZERO(recr2, payload);
7785 mlxsw_reg_recr2_pp_set(payload, false);
7786 mlxsw_reg_recr2_sh_set(payload, true);
7787 mlxsw_reg_recr2_seed_set(payload, seed);
7790 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
7791 * --------------------------------------------------------------
7792 * The RMFT_V2 register is used to configure and query the multicast table.
7794 #define MLXSW_REG_RMFT2_ID 0x8027
7795 #define MLXSW_REG_RMFT2_LEN 0x174
7797 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
7803 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
7805 enum mlxsw_reg_rmft2_type {
7806 MLXSW_REG_RMFT2_TYPE_IPV4,
7807 MLXSW_REG_RMFT2_TYPE_IPV6
7813 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
7815 enum mlxsw_sp_reg_rmft2_op {
7817 * Write operation. Used to write a new entry to the table. All RW
7818 * fields are relevant for new entry. Activity bit is set for new
7819 * entries - Note write with v (Valid) 0 will delete the entry.
7823 MLXSW_REG_RMFT2_OP_READ_WRITE,
7830 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
7833 * Activity. Set for new entries. Set if a packet lookup has hit on the specific
7837 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
7840 * Offset within the multicast forwarding table to write to.
7843 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
7845 /* reg_rmft2_virtual_router
7846 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1
7849 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
7851 enum mlxsw_reg_rmft2_irif_mask {
7852 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
7853 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
7856 /* reg_rmft2_irif_mask
7860 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
7863 * Ingress RIF index.
7866 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
7868 /* reg_rmft2_dip{4,6}
7869 * Destination IPv4/6 address
7872 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
7873 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
7875 /* reg_rmft2_dip{4,6}_mask
7876 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7877 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7880 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
7881 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
7883 /* reg_rmft2_sip{4,6}
7884 * Source IPv4/6 address
7887 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
7888 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
7890 /* reg_rmft2_sip{4,6}_mask
7891 * A bit that is set directs the TCAM to compare the corresponding bit in key. A
7892 * bit that is clear directs the TCAM to ignore the corresponding bit in key.
7895 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
7896 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
7898 /* reg_rmft2_flexible_action_set
7899 * ACL action set. The only supported action types in this field and in any
7900 * action-set pointed from here are as follows:
7902 * 01h: ACTION_MAC_TTL, only TTL configuration is supported.
7905 * 08h: ACTION_POLICING_MONITORING
7906 * 10h: ACTION_ROUTER_MC
7909 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
7910 MLXSW_REG_FLEX_ACTION_SET_LEN);
7913 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
7915 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7916 const char *flex_action_set)
7918 MLXSW_REG_ZERO(rmft2, payload);
7919 mlxsw_reg_rmft2_v_set(payload, v);
7920 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
7921 mlxsw_reg_rmft2_offset_set(payload, offset);
7922 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
7923 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
7924 mlxsw_reg_rmft2_irif_set(payload, irif);
7925 if (flex_action_set)
7926 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
7931 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7932 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7933 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
7934 const char *flexible_action_set)
7936 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7937 irif_mask, irif, flexible_action_set);
7938 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
7939 mlxsw_reg_rmft2_dip4_set(payload, dip4);
7940 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
7941 mlxsw_reg_rmft2_sip4_set(payload, sip4);
7942 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
7946 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
7947 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
7948 struct in6_addr dip6, struct in6_addr dip6_mask,
7949 struct in6_addr sip6, struct in6_addr sip6_mask,
7950 const char *flexible_action_set)
7952 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
7953 irif_mask, irif, flexible_action_set);
7954 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
7955 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
7956 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
7957 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
7958 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
7961 /* MFCR - Management Fan Control Register
7962 * --------------------------------------
7963 * This register controls the settings of the Fan Speed PWM mechanism.
7965 #define MLXSW_REG_MFCR_ID 0x9001
7966 #define MLXSW_REG_MFCR_LEN 0x08
7968 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
7970 enum mlxsw_reg_mfcr_pwm_frequency {
7971 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
7972 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
7973 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
7974 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
7975 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
7976 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
7977 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
7978 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
7981 /* reg_mfcr_pwm_frequency
7982 * Controls the frequency of the PWM signal.
7985 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
7987 #define MLXSW_MFCR_TACHOS_MAX 10
7989 /* reg_mfcr_tacho_active
7990 * Indicates which of the tachometer is active (bit per tachometer).
7993 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
7995 #define MLXSW_MFCR_PWMS_MAX 5
7997 /* reg_mfcr_pwm_active
7998 * Indicates which of the PWM control is active (bit per PWM).
8001 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
8004 mlxsw_reg_mfcr_pack(char *payload,
8005 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
8007 MLXSW_REG_ZERO(mfcr, payload);
8008 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
8012 mlxsw_reg_mfcr_unpack(char *payload,
8013 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
8014 u16 *p_tacho_active, u8 *p_pwm_active)
8016 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
8017 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
8018 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
8021 /* MFSC - Management Fan Speed Control Register
8022 * --------------------------------------------
8023 * This register controls the settings of the Fan Speed PWM mechanism.
8025 #define MLXSW_REG_MFSC_ID 0x9002
8026 #define MLXSW_REG_MFSC_LEN 0x08
8028 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
8031 * Fan pwm to control / monitor.
8034 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
8036 /* reg_mfsc_pwm_duty_cycle
8037 * Controls the duty cycle of the PWM. Value range from 0..255 to
8038 * represent duty cycle of 0%...100%.
8041 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
8043 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
8046 MLXSW_REG_ZERO(mfsc, payload);
8047 mlxsw_reg_mfsc_pwm_set(payload, pwm);
8048 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
8051 /* MFSM - Management Fan Speed Measurement
8052 * ---------------------------------------
8053 * This register controls the settings of the Tacho measurements and
8054 * enables reading the Tachometer measurements.
8056 #define MLXSW_REG_MFSM_ID 0x9003
8057 #define MLXSW_REG_MFSM_LEN 0x08
8059 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
8062 * Fan tachometer index.
8065 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
8068 * Fan speed (round per minute).
8071 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
8073 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
8075 MLXSW_REG_ZERO(mfsm, payload);
8076 mlxsw_reg_mfsm_tacho_set(payload, tacho);
8079 /* MFSL - Management Fan Speed Limit Register
8080 * ------------------------------------------
8081 * The Fan Speed Limit register is used to configure the fan speed
8082 * event / interrupt notification mechanism. Fan speed threshold are
8083 * defined for both under-speed and over-speed.
8085 #define MLXSW_REG_MFSL_ID 0x9004
8086 #define MLXSW_REG_MFSL_LEN 0x0C
8088 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
8091 * Fan tachometer index.
8094 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
8096 /* reg_mfsl_tach_min
8097 * Tachometer minimum value (minimum RPM).
8100 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
8102 /* reg_mfsl_tach_max
8103 * Tachometer maximum value (maximum RPM).
8106 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
8108 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
8109 u16 tach_min, u16 tach_max)
8111 MLXSW_REG_ZERO(mfsl, payload);
8112 mlxsw_reg_mfsl_tacho_set(payload, tacho);
8113 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
8114 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
8117 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
8118 u16 *p_tach_min, u16 *p_tach_max)
8121 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
8124 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
8127 /* FORE - Fan Out of Range Event Register
8128 * --------------------------------------
8129 * This register reports the status of the controlled fans compared to the
8130 * range defined by the MFSL register.
8132 #define MLXSW_REG_FORE_ID 0x9007
8133 #define MLXSW_REG_FORE_LEN 0x0C
8135 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
8138 * Fan speed is below the low limit defined in MFSL register. Each bit relates
8139 * to a single tachometer and indicates the specific tachometer reading is
8140 * below the threshold.
8143 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
8145 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
8151 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
8152 *fault = limit & BIT(tacho);
8156 /* MTCAP - Management Temperature Capabilities
8157 * -------------------------------------------
8158 * This register exposes the capabilities of the device and
8159 * system temperature sensing.
8161 #define MLXSW_REG_MTCAP_ID 0x9009
8162 #define MLXSW_REG_MTCAP_LEN 0x08
8164 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
8166 /* reg_mtcap_sensor_count
8167 * Number of sensors supported by the device.
8168 * This includes the QSFP module sensors (if exists in the QSFP module).
8171 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
8173 /* MTMP - Management Temperature
8174 * -----------------------------
8175 * This register controls the settings of the temperature measurements
8176 * and enables reading the temperature measurements. Note that temperature
8177 * is in 0.125 degrees Celsius.
8179 #define MLXSW_REG_MTMP_ID 0x900A
8180 #define MLXSW_REG_MTMP_LEN 0x20
8182 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
8184 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
8185 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
8186 /* reg_mtmp_sensor_index
8187 * Sensors index to access.
8188 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
8189 * (module 0 is mapped to sensor_index 64).
8192 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
8194 /* Convert to milli degrees Celsius */
8195 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
8196 ((v_) >= 0) ? ((v_) * 125) : \
8197 ((s16)((GENMASK(15, 0) + (v_) + 1) \
8200 /* reg_mtmp_temperature
8201 * Temperature reading from the sensor. Reading is in 0.125 Celsius
8205 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
8208 * Max Temperature Enable - enables measuring the max temperature on a sensor.
8211 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
8214 * Max Temperature Reset - clears the value of the max temperature register.
8217 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
8219 /* reg_mtmp_max_temperature
8220 * The highest measured temperature from the sensor.
8221 * When the bit mte is cleared, the field max_temperature is reserved.
8224 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
8227 * Temperature Event Enable.
8228 * 0 - Do not generate event
8229 * 1 - Generate event
8230 * 2 - Generate single event
8233 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
8235 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */
8237 /* reg_mtmp_temperature_threshold_hi
8238 * High threshold for Temperature Warning Event. In 0.125 Celsius.
8241 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
8243 /* reg_mtmp_temperature_threshold_lo
8244 * Low threshold for Temperature Warning Event. In 0.125 Celsius.
8247 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
8249 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
8251 /* reg_mtmp_sensor_name
8255 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
8257 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
8258 bool max_temp_enable,
8259 bool max_temp_reset)
8261 MLXSW_REG_ZERO(mtmp, payload);
8262 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
8263 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
8264 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
8265 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
8266 MLXSW_REG_MTMP_THRESH_HI);
8269 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
8270 int *p_max_temp, char *sensor_name)
8275 temp = mlxsw_reg_mtmp_temperature_get(payload);
8276 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8279 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
8280 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
8283 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
8286 /* MTBR - Management Temperature Bulk Register
8287 * -------------------------------------------
8288 * This register is used for bulk temperature reading.
8290 #define MLXSW_REG_MTBR_ID 0x900F
8291 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
8292 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
8293 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
8294 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \
8295 MLXSW_REG_MTBR_REC_LEN * \
8296 MLXSW_REG_MTBR_REC_MAX_COUNT)
8298 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
8300 /* reg_mtbr_base_sensor_index
8301 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
8302 * 64-127 are mapped to the SFP+/QSFP modules sequentially).
8305 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
8308 * Request: Number of records to read
8309 * Response: Number of records read
8310 * See above description for more details.
8314 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
8316 /* reg_mtbr_rec_max_temp
8317 * The highest measured temperature from the sensor.
8318 * When the bit mte is cleared, the field max_temperature is reserved.
8321 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
8322 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8324 /* reg_mtbr_rec_temp
8325 * Temperature reading from the sensor. Reading is in 0..125 Celsius
8329 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
8330 MLXSW_REG_MTBR_REC_LEN, 0x00, false);
8332 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
8335 MLXSW_REG_ZERO(mtbr, payload);
8336 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
8337 mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
8340 /* Error codes from temperatute reading */
8341 enum mlxsw_reg_mtbr_temp_status {
8342 MLXSW_REG_MTBR_NO_CONN = 0x8000,
8343 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001,
8344 MLXSW_REG_MTBR_INDEX_NA = 0x8002,
8345 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003,
8348 /* Base index for reading modules temperature */
8349 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
8351 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
8352 u16 *p_temp, u16 *p_max_temp)
8355 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
8357 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
8360 /* MCIA - Management Cable Info Access
8361 * -----------------------------------
8362 * MCIA register is used to access the SFP+ and QSFP connector's EPROM.
8365 #define MLXSW_REG_MCIA_ID 0x9014
8366 #define MLXSW_REG_MCIA_LEN 0x40
8368 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
8371 * Lock bit. Setting this bit will lock the access to the specific
8372 * cable. Used for updating a full page in a cable EPROM. Any access
8373 * other then subsequence writes will fail while the port is locked.
8376 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
8382 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
8388 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
8390 /* reg_mcia_i2c_device_address
8391 * I2C device address.
8394 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
8396 /* reg_mcia_page_number
8400 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
8402 /* reg_mcia_device_address
8406 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
8409 * Number of bytes to read/write (up to 48 bytes).
8412 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
8414 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256
8415 #define MLXSW_REG_MCIA_EEPROM_SIZE 48
8416 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50
8417 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51
8418 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0
8419 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2
8420 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3
8421 #define MLXSW_REG_MCIA_PAGE0_LO 0
8422 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80
8424 enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
8425 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
8426 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
8427 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
8430 enum mlxsw_reg_mcia_eeprom_module_info_id {
8431 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03,
8432 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
8433 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
8434 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
8435 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18,
8438 enum mlxsw_reg_mcia_eeprom_module_info {
8439 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
8440 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
8441 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
8445 * Bytes to read/write.
8448 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
8450 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
8451 u8 page_number, u16 device_addr,
8452 u8 size, u8 i2c_device_addr)
8454 MLXSW_REG_ZERO(mcia, payload);
8455 mlxsw_reg_mcia_module_set(payload, module);
8456 mlxsw_reg_mcia_l_set(payload, lock);
8457 mlxsw_reg_mcia_page_number_set(payload, page_number);
8458 mlxsw_reg_mcia_device_address_set(payload, device_addr);
8459 mlxsw_reg_mcia_size_set(payload, size);
8460 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
8463 /* MPAT - Monitoring Port Analyzer Table
8464 * -------------------------------------
8465 * MPAT Register is used to query and configure the Switch PortAnalyzer Table.
8466 * For an enabled analyzer, all fields except e (enable) cannot be modified.
8468 #define MLXSW_REG_MPAT_ID 0x901A
8469 #define MLXSW_REG_MPAT_LEN 0x78
8471 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
8477 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
8479 /* reg_mpat_system_port
8480 * A unique port identifier for the final destination of the packet.
8483 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
8486 * Enable. Indicating the Port Analyzer is enabled.
8489 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
8492 * Quality Of Service Mode.
8493 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation
8494 * PCP, DEI, DSCP or VL) are configured.
8495 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the
8496 * same as in the original packet that has triggered the mirroring. For
8497 * SPAN also the pcp,dei are maintained.
8500 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
8503 * Best effort mode. Indicates mirroring traffic should not cause packet
8504 * drop or back pressure, but will discard the mirrored packets. Mirrored
8505 * packets will be forwarded on a best effort manner.
8506 * 0: Do not discard mirrored packets
8507 * 1: Discard mirrored packets if causing congestion
8510 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
8512 enum mlxsw_reg_mpat_span_type {
8513 /* Local SPAN Ethernet.
8514 * The original packet is not encapsulated.
8516 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
8518 /* Remote SPAN Ethernet VLAN.
8519 * The packet is forwarded to the monitoring port on the monitoring
8522 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
8524 /* Encapsulated Remote SPAN Ethernet L3 GRE.
8525 * The packet is encapsulated with GRE header.
8527 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
8530 /* reg_mpat_span_type
8534 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
8536 /* Remote SPAN - Ethernet VLAN
8537 * - - - - - - - - - - - - - -
8540 /* reg_mpat_eth_rspan_vid
8541 * Encapsulation header VLAN ID.
8544 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
8546 /* Encapsulated Remote SPAN - Ethernet L2
8547 * - - - - - - - - - - - - - - - - - - -
8550 enum mlxsw_reg_mpat_eth_rspan_version {
8551 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
8554 /* reg_mpat_eth_rspan_version
8555 * RSPAN mirror header version.
8558 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
8560 /* reg_mpat_eth_rspan_mac
8561 * Destination MAC address.
8564 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
8566 /* reg_mpat_eth_rspan_tp
8567 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged.
8570 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
8572 /* Encapsulated Remote SPAN - Ethernet L3
8573 * - - - - - - - - - - - - - - - - - - -
8576 enum mlxsw_reg_mpat_eth_rspan_protocol {
8577 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
8578 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
8581 /* reg_mpat_eth_rspan_protocol
8582 * SPAN encapsulation protocol.
8585 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
8587 /* reg_mpat_eth_rspan_ttl
8588 * Encapsulation header Time-to-Live/HopLimit.
8591 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
8593 /* reg_mpat_eth_rspan_smac
8594 * Source MAC address
8597 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
8599 /* reg_mpat_eth_rspan_dip*
8600 * Destination IP address. The IP version is configured by protocol.
8603 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
8604 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
8606 /* reg_mpat_eth_rspan_sip*
8607 * Source IP address. The IP version is configured by protocol.
8610 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
8611 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
8613 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
8614 u16 system_port, bool e,
8615 enum mlxsw_reg_mpat_span_type span_type)
8617 MLXSW_REG_ZERO(mpat, payload);
8618 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
8619 mlxsw_reg_mpat_system_port_set(payload, system_port);
8620 mlxsw_reg_mpat_e_set(payload, e);
8621 mlxsw_reg_mpat_qos_set(payload, 1);
8622 mlxsw_reg_mpat_be_set(payload, 1);
8623 mlxsw_reg_mpat_span_type_set(payload, span_type);
8626 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
8628 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
8632 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
8633 enum mlxsw_reg_mpat_eth_rspan_version version,
8637 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
8638 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
8639 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
8643 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
8647 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8648 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8649 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8650 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
8651 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
8652 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
8656 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
8658 struct in6_addr sip, struct in6_addr dip)
8660 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
8661 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
8662 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
8663 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
8664 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
8665 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
8668 /* MPAR - Monitoring Port Analyzer Register
8669 * ----------------------------------------
8670 * MPAR register is used to query and configure the port analyzer port mirroring
8673 #define MLXSW_REG_MPAR_ID 0x901B
8674 #define MLXSW_REG_MPAR_LEN 0x08
8676 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
8678 /* reg_mpar_local_port
8679 * The local port to mirror the packets from.
8682 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
8684 enum mlxsw_reg_mpar_i_e {
8685 MLXSW_REG_MPAR_TYPE_EGRESS,
8686 MLXSW_REG_MPAR_TYPE_INGRESS,
8693 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
8697 * By default, port mirroring is disabled for all ports.
8700 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
8706 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
8708 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
8709 enum mlxsw_reg_mpar_i_e i_e,
8710 bool enable, u8 pa_id)
8712 MLXSW_REG_ZERO(mpar, payload);
8713 mlxsw_reg_mpar_local_port_set(payload, local_port);
8714 mlxsw_reg_mpar_enable_set(payload, enable);
8715 mlxsw_reg_mpar_i_e_set(payload, i_e);
8716 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
8719 /* MGIR - Management General Information Register
8720 * ----------------------------------------------
8721 * MGIR register allows software to query the hardware and firmware general
8724 #define MLXSW_REG_MGIR_ID 0x9020
8725 #define MLXSW_REG_MGIR_LEN 0x9C
8727 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
8729 /* reg_mgir_hw_info_device_hw_revision
8732 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
8734 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
8736 /* reg_mgir_fw_info_psid
8737 * PSID (ASCII string).
8740 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
8742 /* reg_mgir_fw_info_extended_major
8745 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
8747 /* reg_mgir_fw_info_extended_minor
8750 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
8752 /* reg_mgir_fw_info_extended_sub_minor
8755 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
8757 static inline void mlxsw_reg_mgir_pack(char *payload)
8759 MLXSW_REG_ZERO(mgir, payload);
8763 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
8764 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
8766 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
8767 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
8768 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
8769 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
8770 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
8773 /* MRSR - Management Reset and Shutdown Register
8774 * ---------------------------------------------
8775 * MRSR register is used to reset or shutdown the switch or
8776 * the entire system (when applicable).
8778 #define MLXSW_REG_MRSR_ID 0x9023
8779 #define MLXSW_REG_MRSR_LEN 0x08
8781 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
8784 * Reset/shutdown command
8786 * 1 - software reset
8789 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
8791 static inline void mlxsw_reg_mrsr_pack(char *payload)
8793 MLXSW_REG_ZERO(mrsr, payload);
8794 mlxsw_reg_mrsr_command_set(payload, 1);
8797 /* MLCR - Management LED Control Register
8798 * --------------------------------------
8799 * Controls the system LEDs.
8801 #define MLXSW_REG_MLCR_ID 0x902B
8802 #define MLXSW_REG_MLCR_LEN 0x0C
8804 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
8806 /* reg_mlcr_local_port
8807 * Local port number.
8810 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
8812 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
8814 /* reg_mlcr_beacon_duration
8815 * Duration of the beacon to be active, in seconds.
8816 * 0x0 - Will turn off the beacon.
8817 * 0xFFFF - Will turn on the beacon until explicitly turned off.
8820 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
8822 /* reg_mlcr_beacon_remain
8823 * Remaining duration of the beacon, in seconds.
8824 * 0xFFFF indicates an infinite amount of time.
8827 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
8829 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
8832 MLXSW_REG_ZERO(mlcr, payload);
8833 mlxsw_reg_mlcr_local_port_set(payload, local_port);
8834 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
8835 MLXSW_REG_MLCR_DURATION_MAX : 0);
8838 /* MTPPS - Management Pulse Per Second Register
8839 * --------------------------------------------
8840 * This register provides the device PPS capabilities, configure the PPS in and
8841 * out modules and holds the PPS in time stamp.
8843 #define MLXSW_REG_MTPPS_ID 0x9053
8844 #define MLXSW_REG_MTPPS_LEN 0x3C
8846 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
8849 * Enables the PPS functionality the specific pin.
8850 * A boolean variable.
8853 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
8855 enum mlxsw_reg_mtpps_pin_mode {
8856 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
8859 /* reg_mtpps_pin_mode
8860 * Pin mode to be used. The mode must comply with the supported modes of the
8864 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
8866 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
8869 * Pin to be configured or queried out of the supported pins.
8872 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
8874 /* reg_mtpps_time_stamp
8875 * When pin_mode = pps_in, the latched device time when it was triggered from
8876 * the external GPIO pin.
8877 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
8878 * time to generate next output signal.
8879 * Time is in units of device clock.
8882 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
8885 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
8887 MLXSW_REG_ZERO(mtpps, payload);
8888 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
8889 mlxsw_reg_mtpps_pin_mode_set(payload,
8890 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
8891 mlxsw_reg_mtpps_enable_set(payload, true);
8892 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
8895 /* MTUTC - Management UTC Register
8896 * -------------------------------
8897 * Configures the HW UTC counter.
8899 #define MLXSW_REG_MTUTC_ID 0x9055
8900 #define MLXSW_REG_MTUTC_LEN 0x1C
8902 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
8904 enum mlxsw_reg_mtutc_operation {
8905 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
8906 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
8909 /* reg_mtutc_operation
8913 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
8915 /* reg_mtutc_freq_adjustment
8916 * Frequency adjustment: Every PPS the HW frequency will be
8917 * adjusted by this value. Units of HW clock, where HW counts
8918 * 10^9 HW clocks for 1 HW second.
8921 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
8923 /* reg_mtutc_utc_sec
8927 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
8930 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
8931 u32 freq_adj, u32 utc_sec)
8933 MLXSW_REG_ZERO(mtutc, payload);
8934 mlxsw_reg_mtutc_operation_set(payload, oper);
8935 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
8936 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
8939 /* MCQI - Management Component Query Information
8940 * ---------------------------------------------
8941 * This register allows querying information about firmware components.
8943 #define MLXSW_REG_MCQI_ID 0x9061
8944 #define MLXSW_REG_MCQI_BASE_LEN 0x18
8945 #define MLXSW_REG_MCQI_CAP_LEN 0x14
8946 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
8948 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
8950 /* reg_mcqi_component_index
8951 * Index of the accessed component.
8954 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
8956 enum mlxfw_reg_mcqi_info_type {
8957 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
8960 /* reg_mcqi_info_type
8961 * Component properties set.
8964 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
8967 * The requested/returned data offset from the section start, given in bytes.
8968 * Must be DWORD aligned.
8971 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
8973 /* reg_mcqi_data_size
8974 * The requested/returned data size, given in bytes. If data_size is not DWORD
8975 * aligned, the last bytes are zero padded.
8978 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
8980 /* reg_mcqi_cap_max_component_size
8981 * Maximum size for this component, given in bytes.
8984 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
8986 /* reg_mcqi_cap_log_mcda_word_size
8987 * Log 2 of the access word size in bytes. Read and write access must be aligned
8988 * to the word size. Write access must be done for an integer number of words.
8991 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
8993 /* reg_mcqi_cap_mcda_max_write_size
8994 * Maximal write size for MCDA register
8997 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
8999 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
9001 MLXSW_REG_ZERO(mcqi, payload);
9002 mlxsw_reg_mcqi_component_index_set(payload, component_index);
9003 mlxsw_reg_mcqi_info_type_set(payload,
9004 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
9005 mlxsw_reg_mcqi_offset_set(payload, 0);
9006 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
9009 static inline void mlxsw_reg_mcqi_unpack(char *payload,
9010 u32 *p_cap_max_component_size,
9011 u8 *p_cap_log_mcda_word_size,
9012 u16 *p_cap_mcda_max_write_size)
9014 *p_cap_max_component_size =
9015 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
9016 *p_cap_log_mcda_word_size =
9017 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
9018 *p_cap_mcda_max_write_size =
9019 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
9022 /* MCC - Management Component Control
9023 * ----------------------------------
9024 * Controls the firmware component and updates the FSM.
9026 #define MLXSW_REG_MCC_ID 0x9062
9027 #define MLXSW_REG_MCC_LEN 0x1C
9029 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
9031 enum mlxsw_reg_mcc_instruction {
9032 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
9033 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
9034 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
9035 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
9036 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
9037 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
9040 /* reg_mcc_instruction
9041 * Command to be executed by the FSM.
9042 * Applicable for write operation only.
9045 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
9047 /* reg_mcc_component_index
9048 * Index of the accessed component. Applicable only for commands that
9049 * refer to components. Otherwise, this field is reserved.
9052 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
9054 /* reg_mcc_update_handle
9055 * Token representing the current flow executed by the FSM.
9058 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
9060 /* reg_mcc_error_code
9061 * Indicates the successful completion of the instruction, or the reason it
9065 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
9067 /* reg_mcc_control_state
9071 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
9073 /* reg_mcc_component_size
9074 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying
9075 * the size may shorten the update time. Value 0x0 means that size is
9079 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
9081 static inline void mlxsw_reg_mcc_pack(char *payload,
9082 enum mlxsw_reg_mcc_instruction instr,
9083 u16 component_index, u32 update_handle,
9086 MLXSW_REG_ZERO(mcc, payload);
9087 mlxsw_reg_mcc_instruction_set(payload, instr);
9088 mlxsw_reg_mcc_component_index_set(payload, component_index);
9089 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
9090 mlxsw_reg_mcc_component_size_set(payload, component_size);
9093 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
9094 u8 *p_error_code, u8 *p_control_state)
9096 if (p_update_handle)
9097 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
9099 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
9100 if (p_control_state)
9101 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
9104 /* MCDA - Management Component Data Access
9105 * ---------------------------------------
9106 * This register allows reading and writing a firmware component.
9108 #define MLXSW_REG_MCDA_ID 0x9063
9109 #define MLXSW_REG_MCDA_BASE_LEN 0x10
9110 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
9111 #define MLXSW_REG_MCDA_LEN \
9112 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
9114 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
9116 /* reg_mcda_update_handle
9117 * Token representing the current flow executed by the FSM.
9120 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
9123 * Offset of accessed address relative to component start. Accesses must be in
9124 * accordance to log_mcda_word_size in MCQI reg.
9127 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
9130 * Size of the data accessed, given in bytes.
9133 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
9136 * Data block accessed.
9139 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
9141 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
9142 u32 offset, u16 size, u8 *data)
9146 MLXSW_REG_ZERO(mcda, payload);
9147 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
9148 mlxsw_reg_mcda_offset_set(payload, offset);
9149 mlxsw_reg_mcda_size_set(payload, size);
9151 for (i = 0; i < size / 4; i++)
9152 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
9155 /* MPSC - Monitoring Packet Sampling Configuration Register
9156 * --------------------------------------------------------
9157 * MPSC Register is used to configure the Packet Sampling mechanism.
9159 #define MLXSW_REG_MPSC_ID 0x9080
9160 #define MLXSW_REG_MPSC_LEN 0x1C
9162 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
9164 /* reg_mpsc_local_port
9166 * Not supported for CPU port
9169 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
9172 * Enable sampling on port local_port
9175 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
9177 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
9180 * Sampling rate = 1 out of rate packets (with randomization around
9181 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX
9184 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
9186 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
9189 MLXSW_REG_ZERO(mpsc, payload);
9190 mlxsw_reg_mpsc_local_port_set(payload, local_port);
9191 mlxsw_reg_mpsc_e_set(payload, e);
9192 mlxsw_reg_mpsc_rate_set(payload, rate);
9195 /* MGPC - Monitoring General Purpose Counter Set Register
9196 * The MGPC register retrieves and sets the General Purpose Counter Set.
9198 #define MLXSW_REG_MGPC_ID 0x9081
9199 #define MLXSW_REG_MGPC_LEN 0x18
9201 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
9203 /* reg_mgpc_counter_set_type
9207 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
9209 /* reg_mgpc_counter_index
9213 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
9215 enum mlxsw_reg_mgpc_opcode {
9217 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
9218 /* Clear counters */
9219 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
9226 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
9228 /* reg_mgpc_byte_counter
9229 * Byte counter value.
9232 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
9234 /* reg_mgpc_packet_counter
9235 * Packet counter value.
9238 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
9240 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
9241 enum mlxsw_reg_mgpc_opcode opcode,
9242 enum mlxsw_reg_flow_counter_set_type set_type)
9244 MLXSW_REG_ZERO(mgpc, payload);
9245 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
9246 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
9247 mlxsw_reg_mgpc_opcode_set(payload, opcode);
9250 /* MPRS - Monitoring Parsing State Register
9251 * ----------------------------------------
9252 * The MPRS register is used for setting up the parsing for hash,
9253 * policy-engine and routing.
9255 #define MLXSW_REG_MPRS_ID 0x9083
9256 #define MLXSW_REG_MPRS_LEN 0x14
9258 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
9260 /* reg_mprs_parsing_depth
9261 * Minimum parsing depth.
9262 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
9263 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
9266 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
9268 /* reg_mprs_parsing_en
9270 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
9271 * NVGRE. Default is enabled. Reserved when SwitchX-2.
9274 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
9276 /* reg_mprs_vxlan_udp_dport
9277 * VxLAN UDP destination port.
9278 * Used for identifying VxLAN packets and for dport field in
9279 * encapsulation. Default is 4789.
9282 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
9284 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
9285 u16 vxlan_udp_dport)
9287 MLXSW_REG_ZERO(mprs, payload);
9288 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
9289 mlxsw_reg_mprs_parsing_en_set(payload, true);
9290 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
9293 /* MOGCR - Monitoring Global Configuration Register
9294 * ------------------------------------------------
9296 #define MLXSW_REG_MOGCR_ID 0x9086
9297 #define MLXSW_REG_MOGCR_LEN 0x20
9299 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
9301 /* reg_mogcr_ptp_iftc
9302 * PTP Ingress FIFO Trap Clear
9303 * The PTP_ING_FIFO trap provides MTPPTR with clr according
9304 * to this value. Default 0.
9305 * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9308 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
9310 /* reg_mogcr_ptp_eftc
9311 * PTP Egress FIFO Trap Clear
9312 * The PTP_EGR_FIFO trap provides MTPPTR with clr according
9313 * to this value. Default 0.
9314 * Reserved when IB switches and when SwitchX/-2, Spectrum-2
9317 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
9319 /* MTPPPC - Time Precision Packet Port Configuration
9320 * -------------------------------------------------
9321 * This register serves for configuration of which PTP messages should be
9322 * timestamped. This is a global configuration, despite the register name.
9324 * Reserved when Spectrum-2.
9326 #define MLXSW_REG_MTPPPC_ID 0x9090
9327 #define MLXSW_REG_MTPPPC_LEN 0x28
9329 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
9331 /* reg_mtpppc_ing_timestamp_message_type
9332 * Bitwise vector of PTP message types to timestamp at ingress.
9333 * MessageType field as defined by IEEE 1588
9334 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9338 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
9340 /* reg_mtpppc_egr_timestamp_message_type
9341 * Bitwise vector of PTP message types to timestamp at egress.
9342 * MessageType field as defined by IEEE 1588
9343 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
9347 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
9349 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
9351 MLXSW_REG_ZERO(mtpppc, payload);
9352 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
9353 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
9356 /* MTPPTR - Time Precision Packet Timestamping Reading
9357 * ---------------------------------------------------
9358 * The MTPPTR is used for reading the per port PTP timestamp FIFO.
9359 * There is a trap for packets which are latched to the timestamp FIFO, thus the
9360 * SW knows which FIFO to read. Note that packets enter the FIFO before been
9361 * trapped. The sequence number is used to synchronize the timestamp FIFO
9362 * entries and the trapped packets.
9363 * Reserved when Spectrum-2.
9366 #define MLXSW_REG_MTPPTR_ID 0x9091
9367 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
9368 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
9369 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
9370 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
9371 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
9373 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
9375 /* reg_mtpptr_local_port
9376 * Not supported for CPU port.
9379 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
9381 enum mlxsw_reg_mtpptr_dir {
9382 MLXSW_REG_MTPPTR_DIR_INGRESS,
9383 MLXSW_REG_MTPPTR_DIR_EGRESS,
9390 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
9393 * Clear the records.
9396 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
9398 /* reg_mtpptr_num_rec
9399 * Number of valid records in the response
9400 * Range 0.. cap_ptp_timestamp_fifo
9403 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
9405 /* reg_mtpptr_rec_message_type
9406 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
9407 * (e.g. Bit0: Sync, Bit1: Delay_Req)
9410 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
9411 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
9412 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9414 /* reg_mtpptr_rec_domain_number
9415 * DomainNumber field as defined by IEEE 1588
9418 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
9419 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
9420 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
9422 /* reg_mtpptr_rec_sequence_id
9423 * SequenceId field as defined by IEEE 1588
9426 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
9427 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
9428 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
9430 /* reg_mtpptr_rec_timestamp_high
9431 * Timestamp of when the PTP packet has passed through the port Units of PLL
9433 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
9436 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
9437 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9438 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
9440 /* reg_mtpptr_rec_timestamp_low
9441 * See rec_timestamp_high.
9444 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
9445 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
9446 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
9448 static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
9451 u8 *p_domain_number,
9455 u32 timestamp_high, timestamp_low;
9457 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
9458 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
9459 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
9460 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
9461 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
9462 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
9465 /* MTPTPT - Monitoring Precision Time Protocol Trap Register
9466 * ---------------------------------------------------------
9467 * This register is used for configuring under which trap to deliver PTP
9468 * packets depending on type of the packet.
9470 #define MLXSW_REG_MTPTPT_ID 0x9092
9471 #define MLXSW_REG_MTPTPT_LEN 0x08
9473 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
9475 enum mlxsw_reg_mtptpt_trap_id {
9476 MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
9477 MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
9480 /* reg_mtptpt_trap_id
9484 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
9486 /* reg_mtptpt_message_type
9487 * Bitwise vector of PTP message types to trap. This is a necessary but
9488 * non-sufficient condition since need to enable also per port. See MTPPPC.
9489 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
9490 * Bit0: Sync, Bit1: Delay_Req)
9492 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
9494 static inline void mlxsw_reg_mtptptp_pack(char *payload,
9495 enum mlxsw_reg_mtptpt_trap_id trap_id,
9498 MLXSW_REG_ZERO(mtptpt, payload);
9499 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
9500 mlxsw_reg_mtptpt_message_type_set(payload, message_type);
9503 /* MGPIR - Management General Peripheral Information Register
9504 * ----------------------------------------------------------
9505 * MGPIR register allows software to query the hardware and
9506 * firmware general information of peripheral entities.
9508 #define MLXSW_REG_MGPIR_ID 0x9100
9509 #define MLXSW_REG_MGPIR_LEN 0xA0
9511 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
9513 enum mlxsw_reg_mgpir_device_type {
9514 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
9515 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
9521 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
9523 /* devices_per_flash
9524 * Number of devices of device_type per flash (can be shared by few devices).
9527 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
9530 * Number of devices of device_type.
9533 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
9536 * Number of modules.
9539 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
9541 static inline void mlxsw_reg_mgpir_pack(char *payload)
9543 MLXSW_REG_ZERO(mgpir, payload);
9547 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
9548 enum mlxsw_reg_mgpir_device_type *device_type,
9549 u8 *devices_per_flash, u8 *num_of_modules)
9552 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
9554 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
9555 if (devices_per_flash)
9556 *devices_per_flash =
9557 mlxsw_reg_mgpir_devices_per_flash_get(payload);
9559 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
9562 /* TNGCR - Tunneling NVE General Configuration Register
9563 * ----------------------------------------------------
9564 * The TNGCR register is used for setting up the NVE Tunneling configuration.
9566 #define MLXSW_REG_TNGCR_ID 0xA001
9567 #define MLXSW_REG_TNGCR_LEN 0x44
9569 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
9571 enum mlxsw_reg_tngcr_type {
9572 MLXSW_REG_TNGCR_TYPE_VXLAN,
9573 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
9574 MLXSW_REG_TNGCR_TYPE_GENEVE,
9575 MLXSW_REG_TNGCR_TYPE_NVGRE,
9579 * Tunnel type for encapsulation and decapsulation. The types are mutually
9581 * Note: For Spectrum the NVE parsing must be enabled in MPRS.
9584 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
9586 /* reg_tngcr_nve_valid
9587 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
9590 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
9592 /* reg_tngcr_nve_ttl_uc
9593 * The TTL for NVE tunnel encapsulation underlay unicast packets.
9596 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
9598 /* reg_tngcr_nve_ttl_mc
9599 * The TTL for NVE tunnel encapsulation underlay multicast packets.
9602 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
9605 /* Do not copy flow label. Calculate flow label using nve_flh. */
9606 MLXSW_REG_TNGCR_FL_NO_COPY,
9607 /* Copy flow label from inner packet if packet is IPv6 and
9608 * encapsulation is by IPv6. Otherwise, calculate flow label using
9611 MLXSW_REG_TNGCR_FL_COPY,
9614 /* reg_tngcr_nve_flc
9615 * For NVE tunnel encapsulation: Flow label copy from inner packet.
9618 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
9621 /* Flow label is static. In Spectrum this means '0'. Spectrum-2
9622 * uses {nve_fl_prefix, nve_fl_suffix}.
9624 MLXSW_REG_TNGCR_FL_NO_HASH,
9625 /* 8 LSBs of the flow label are calculated from ECMP hash of the
9626 * inner packet. 12 MSBs are configured by nve_fl_prefix.
9628 MLXSW_REG_TNGCR_FL_HASH,
9631 /* reg_tngcr_nve_flh
9632 * NVE flow label hash.
9635 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
9637 /* reg_tngcr_nve_fl_prefix
9638 * NVE flow label prefix. Constant 12 MSBs of the flow label.
9641 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
9643 /* reg_tngcr_nve_fl_suffix
9644 * NVE flow label suffix. Constant 8 LSBs of the flow label.
9645 * Reserved when nve_flh=1 and for Spectrum.
9648 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
9651 /* Source UDP port is fixed (default '0') */
9652 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
9653 /* Source UDP port is calculated based on hash */
9654 MLXSW_REG_TNGCR_UDP_SPORT_HASH,
9657 /* reg_tngcr_nve_udp_sport_type
9658 * NVE UDP source port type.
9659 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
9660 * When the source UDP port is calculated based on hash, then the 8 LSBs
9661 * are calculated from hash the 8 MSBs are configured by
9662 * nve_udp_sport_prefix.
9665 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
9667 /* reg_tngcr_nve_udp_sport_prefix
9668 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
9669 * Reserved when NVE type is NVGRE.
9672 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
9674 /* reg_tngcr_nve_group_size_mc
9675 * The amount of sequential linked lists of MC entries. The first linked
9676 * list is configured by SFD.underlay_mc_ptr.
9677 * Valid values: 1, 2, 4, 8, 16, 32, 64
9678 * The linked list are configured by TNUMT.
9679 * The hash is set by LAG hash.
9682 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
9684 /* reg_tngcr_nve_group_size_flood
9685 * The amount of sequential linked lists of flooding entries. The first
9686 * linked list is configured by SFMR.nve_tunnel_flood_ptr
9687 * Valid values: 1, 2, 4, 8, 16, 32, 64
9688 * The linked list are configured by TNUMT.
9689 * The hash is set by LAG hash.
9692 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
9694 /* reg_tngcr_learn_enable
9695 * During decapsulation, whether to learn from NVE port.
9696 * Reserved when Spectrum-2. See TNPC.
9699 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
9701 /* reg_tngcr_underlay_virtual_router
9702 * Underlay virtual router.
9703 * Reserved when Spectrum-2.
9706 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
9708 /* reg_tngcr_underlay_rif
9709 * Underlay ingress router interface. RIF type should be loopback generic.
9710 * Reserved when Spectrum.
9713 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
9716 * Underlay source IPv4 address of the NVE.
9719 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
9722 * Underlay source IPv6 address of the NVE. For Spectrum, must not be
9723 * modified under traffic of NVE tunneling encapsulation.
9726 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
9728 static inline void mlxsw_reg_tngcr_pack(char *payload,
9729 enum mlxsw_reg_tngcr_type type,
9732 MLXSW_REG_ZERO(tngcr, payload);
9733 mlxsw_reg_tngcr_type_set(payload, type);
9734 mlxsw_reg_tngcr_nve_valid_set(payload, valid);
9735 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
9736 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
9737 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
9738 mlxsw_reg_tngcr_nve_flh_set(payload, 0);
9739 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
9740 MLXSW_REG_TNGCR_UDP_SPORT_HASH);
9741 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
9742 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
9743 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
9746 /* TNUMT - Tunneling NVE Underlay Multicast Table Register
9747 * -------------------------------------------------------
9748 * The TNUMT register is for building the underlay MC table. It is used
9749 * for MC, flooding and BC traffic into the NVE tunnel.
9751 #define MLXSW_REG_TNUMT_ID 0xA003
9752 #define MLXSW_REG_TNUMT_LEN 0x20
9754 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
9756 enum mlxsw_reg_tnumt_record_type {
9757 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
9758 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
9759 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
9762 /* reg_tnumt_record_type
9766 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
9768 enum mlxsw_reg_tnumt_tunnel_port {
9769 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
9770 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
9771 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
9772 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
9775 /* reg_tnumt_tunnel_port
9779 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
9781 /* reg_tnumt_underlay_mc_ptr
9782 * Index to the underlay multicast table.
9783 * For Spectrum the index is to the KVD linear.
9786 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
9789 * The next_underlay_mc_ptr is valid.
9792 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
9794 /* reg_tnumt_next_underlay_mc_ptr
9795 * The next index to the underlay multicast table.
9798 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
9800 /* reg_tnumt_record_size
9801 * Number of IP addresses in the record.
9802 * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
9805 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
9808 * The underlay IPv4 addresses. udip[i] is reserved if i >= size
9811 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
9813 /* reg_tnumt_udip_ptr
9814 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
9815 * i >= size. The IPv6 addresses are configured by RIPS.
9818 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
9820 static inline void mlxsw_reg_tnumt_pack(char *payload,
9821 enum mlxsw_reg_tnumt_record_type type,
9822 enum mlxsw_reg_tnumt_tunnel_port tport,
9823 u32 underlay_mc_ptr, bool vnext,
9824 u32 next_underlay_mc_ptr,
9827 MLXSW_REG_ZERO(tnumt, payload);
9828 mlxsw_reg_tnumt_record_type_set(payload, type);
9829 mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
9830 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
9831 mlxsw_reg_tnumt_vnext_set(payload, vnext);
9832 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
9833 mlxsw_reg_tnumt_record_size_set(payload, record_size);
9836 /* TNQCR - Tunneling NVE QoS Configuration Register
9837 * ------------------------------------------------
9838 * The TNQCR register configures how QoS is set in encapsulation into the
9841 #define MLXSW_REG_TNQCR_ID 0xA010
9842 #define MLXSW_REG_TNQCR_LEN 0x0C
9844 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
9846 /* reg_tnqcr_enc_set_dscp
9847 * For encapsulation: How to set DSCP field:
9848 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
9849 * (outer) IP header. If there is no IP header, use TNQDR.dscp
9850 * 1 - Set the DSCP field as TNQDR.dscp
9853 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
9855 static inline void mlxsw_reg_tnqcr_pack(char *payload)
9857 MLXSW_REG_ZERO(tnqcr, payload);
9858 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
9861 /* TNQDR - Tunneling NVE QoS Default Register
9862 * ------------------------------------------
9863 * The TNQDR register configures the default QoS settings for NVE
9866 #define MLXSW_REG_TNQDR_ID 0xA011
9867 #define MLXSW_REG_TNQDR_LEN 0x08
9869 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
9871 /* reg_tnqdr_local_port
9872 * Local port number (receive port). CPU port is supported.
9875 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
9878 * For encapsulation, the default DSCP.
9881 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
9883 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
9885 MLXSW_REG_ZERO(tnqdr, payload);
9886 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
9887 mlxsw_reg_tnqdr_dscp_set(payload, 0);
9890 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
9891 * --------------------------------------------------------
9892 * The TNEEM register maps ECN of the IP header at the ingress to the
9893 * encapsulation to the ECN of the underlay network.
9895 #define MLXSW_REG_TNEEM_ID 0xA012
9896 #define MLXSW_REG_TNEEM_LEN 0x0C
9898 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
9900 /* reg_tneem_overlay_ecn
9901 * ECN of the IP header in the overlay network.
9904 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
9906 /* reg_tneem_underlay_ecn
9907 * ECN of the IP header in the underlay network.
9910 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
9912 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
9915 MLXSW_REG_ZERO(tneem, payload);
9916 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
9917 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
9920 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
9921 * --------------------------------------------------------
9922 * The TNDEM register configures the actions that are done in the
9925 #define MLXSW_REG_TNDEM_ID 0xA013
9926 #define MLXSW_REG_TNDEM_LEN 0x0C
9928 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
9930 /* reg_tndem_underlay_ecn
9931 * ECN field of the IP header in the underlay network.
9934 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
9936 /* reg_tndem_overlay_ecn
9937 * ECN field of the IP header in the overlay network.
9940 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
9942 /* reg_tndem_eip_ecn
9943 * Egress IP ECN. ECN field of the IP header of the packet which goes out
9944 * from the decapsulation.
9947 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
9949 /* reg_tndem_trap_en
9951 * 0 - No trap due to decap ECN
9952 * 1 - Trap enable with trap_id
9955 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
9957 /* reg_tndem_trap_id
9958 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
9959 * Reserved when trap_en is '0'.
9962 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
9964 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
9965 u8 overlay_ecn, u8 ecn, bool trap_en,
9968 MLXSW_REG_ZERO(tndem, payload);
9969 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
9970 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
9971 mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
9972 mlxsw_reg_tndem_trap_en_set(payload, trap_en);
9973 mlxsw_reg_tndem_trap_id_set(payload, trap_id);
9976 /* TNPC - Tunnel Port Configuration Register
9977 * -----------------------------------------
9978 * The TNPC register is used for tunnel port configuration.
9979 * Reserved when Spectrum.
9981 #define MLXSW_REG_TNPC_ID 0xA020
9982 #define MLXSW_REG_TNPC_LEN 0x18
9984 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
9986 enum mlxsw_reg_tnpc_tunnel_port {
9987 MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
9988 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
9989 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
9990 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
9993 /* reg_tnpc_tunnel_port
9997 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
9999 /* reg_tnpc_learn_enable_v6
10000 * During IPv6 underlay decapsulation, whether to learn from tunnel port.
10003 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
10005 /* reg_tnpc_learn_enable_v4
10006 * During IPv4 underlay decapsulation, whether to learn from tunnel port.
10009 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
10011 static inline void mlxsw_reg_tnpc_pack(char *payload,
10012 enum mlxsw_reg_tnpc_tunnel_port tport,
10015 MLXSW_REG_ZERO(tnpc, payload);
10016 mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
10017 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
10018 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
10021 /* TIGCR - Tunneling IPinIP General Configuration Register
10022 * -------------------------------------------------------
10023 * The TIGCR register is used for setting up the IPinIP Tunnel configuration.
10025 #define MLXSW_REG_TIGCR_ID 0xA801
10026 #define MLXSW_REG_TIGCR_LEN 0x10
10028 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
10030 /* reg_tigcr_ipip_ttlc
10031 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet
10035 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
10037 /* reg_tigcr_ipip_ttl_uc
10038 * The TTL for IPinIP Tunnel encapsulation of unicast packets if
10039 * reg_tigcr_ipip_ttlc is unset.
10042 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
10044 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
10046 MLXSW_REG_ZERO(tigcr, payload);
10047 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
10048 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
10051 /* SBPR - Shared Buffer Pools Register
10052 * -----------------------------------
10053 * The SBPR configures and retrieves the shared buffer pools and configuration.
10055 #define MLXSW_REG_SBPR_ID 0xB001
10056 #define MLXSW_REG_SBPR_LEN 0x14
10058 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
10060 /* shared direstion enum for SBPR, SBCM, SBPM */
10061 enum mlxsw_reg_sbxx_dir {
10062 MLXSW_REG_SBXX_DIR_INGRESS,
10063 MLXSW_REG_SBXX_DIR_EGRESS,
10070 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
10076 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
10078 /* reg_sbpr_infi_size
10079 * Size is infinite.
10082 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
10085 * Pool size in buffer cells.
10086 * Reserved when infi_size = 1.
10089 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
10091 enum mlxsw_reg_sbpr_mode {
10092 MLXSW_REG_SBPR_MODE_STATIC,
10093 MLXSW_REG_SBPR_MODE_DYNAMIC,
10097 * Pool quota calculation mode.
10100 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
10102 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
10103 enum mlxsw_reg_sbxx_dir dir,
10104 enum mlxsw_reg_sbpr_mode mode, u32 size,
10107 MLXSW_REG_ZERO(sbpr, payload);
10108 mlxsw_reg_sbpr_pool_set(payload, pool);
10109 mlxsw_reg_sbpr_dir_set(payload, dir);
10110 mlxsw_reg_sbpr_mode_set(payload, mode);
10111 mlxsw_reg_sbpr_size_set(payload, size);
10112 mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
10115 /* SBCM - Shared Buffer Class Management Register
10116 * ----------------------------------------------
10117 * The SBCM register configures and retrieves the shared buffer allocation
10118 * and configuration according to Port-PG, including the binding to pool
10119 * and definition of the associated quota.
10121 #define MLXSW_REG_SBCM_ID 0xB002
10122 #define MLXSW_REG_SBCM_LEN 0x28
10124 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
10126 /* reg_sbcm_local_port
10127 * Local port number.
10128 * For Ingress: excludes CPU port and Router port
10129 * For Egress: excludes IP Router
10132 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
10134 /* reg_sbcm_pg_buff
10135 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
10136 * For PG buffer: range is 0..cap_max_pg_buffers - 1
10137 * For traffic class: range is 0..cap_max_tclass - 1
10138 * Note that when traffic class is in MC aware mode then the traffic
10139 * classes which are MC aware cannot be configured.
10142 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
10148 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
10150 /* reg_sbcm_min_buff
10151 * Minimum buffer size for the limiter, in cells.
10154 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
10156 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
10157 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
10158 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
10160 /* reg_sbcm_infi_max
10161 * Max buffer is infinite.
10164 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
10166 /* reg_sbcm_max_buff
10167 * When the pool associated to the port-pg/tclass is configured to
10168 * static, Maximum buffer size for the limiter configured in cells.
10169 * When the pool associated to the port-pg/tclass is configured to
10170 * dynamic, the max_buff holds the "alpha" parameter, supporting
10171 * the following values:
10173 * i: (1/128)*2^(i-1), for i=1..14
10175 * Reserved when infi_max = 1.
10178 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
10181 * Association of the port-priority to a pool.
10184 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
10186 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
10187 enum mlxsw_reg_sbxx_dir dir,
10188 u32 min_buff, u32 max_buff,
10189 bool infi_max, u8 pool)
10191 MLXSW_REG_ZERO(sbcm, payload);
10192 mlxsw_reg_sbcm_local_port_set(payload, local_port);
10193 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
10194 mlxsw_reg_sbcm_dir_set(payload, dir);
10195 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
10196 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
10197 mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
10198 mlxsw_reg_sbcm_pool_set(payload, pool);
10201 /* SBPM - Shared Buffer Port Management Register
10202 * ---------------------------------------------
10203 * The SBPM register configures and retrieves the shared buffer allocation
10204 * and configuration according to Port-Pool, including the definition
10205 * of the associated quota.
10207 #define MLXSW_REG_SBPM_ID 0xB003
10208 #define MLXSW_REG_SBPM_LEN 0x28
10210 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
10212 /* reg_sbpm_local_port
10213 * Local port number.
10214 * For Ingress: excludes CPU port and Router port
10215 * For Egress: excludes IP Router
10218 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
10221 * The pool associated to quota counting on the local_port.
10224 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
10230 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
10232 /* reg_sbpm_buff_occupancy
10233 * Current buffer occupancy in cells.
10236 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
10239 * Clear Max Buffer Occupancy
10240 * When this bit is set, max_buff_occupancy field is cleared (and a
10241 * new max value is tracked from the time the clear was performed).
10244 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
10246 /* reg_sbpm_max_buff_occupancy
10247 * Maximum value of buffer occupancy in cells monitored. Cleared by
10248 * writing to the clr field.
10251 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
10253 /* reg_sbpm_min_buff
10254 * Minimum buffer size for the limiter, in cells.
10257 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
10259 /* reg_sbpm_max_buff
10260 * When the pool associated to the port-pg/tclass is configured to
10261 * static, Maximum buffer size for the limiter configured in cells.
10262 * When the pool associated to the port-pg/tclass is configured to
10263 * dynamic, the max_buff holds the "alpha" parameter, supporting
10264 * the following values:
10266 * i: (1/128)*2^(i-1), for i=1..14
10270 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
10272 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
10273 enum mlxsw_reg_sbxx_dir dir, bool clr,
10274 u32 min_buff, u32 max_buff)
10276 MLXSW_REG_ZERO(sbpm, payload);
10277 mlxsw_reg_sbpm_local_port_set(payload, local_port);
10278 mlxsw_reg_sbpm_pool_set(payload, pool);
10279 mlxsw_reg_sbpm_dir_set(payload, dir);
10280 mlxsw_reg_sbpm_clr_set(payload, clr);
10281 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
10282 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
10285 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
10286 u32 *p_max_buff_occupancy)
10288 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
10289 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
10292 /* SBMM - Shared Buffer Multicast Management Register
10293 * --------------------------------------------------
10294 * The SBMM register configures and retrieves the shared buffer allocation
10295 * and configuration for MC packets according to Switch-Priority, including
10296 * the binding to pool and definition of the associated quota.
10298 #define MLXSW_REG_SBMM_ID 0xB004
10299 #define MLXSW_REG_SBMM_LEN 0x28
10301 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
10307 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
10309 /* reg_sbmm_min_buff
10310 * Minimum buffer size for the limiter, in cells.
10313 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
10315 /* reg_sbmm_max_buff
10316 * When the pool associated to the port-pg/tclass is configured to
10317 * static, Maximum buffer size for the limiter configured in cells.
10318 * When the pool associated to the port-pg/tclass is configured to
10319 * dynamic, the max_buff holds the "alpha" parameter, supporting
10320 * the following values:
10322 * i: (1/128)*2^(i-1), for i=1..14
10326 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
10329 * Association of the port-priority to a pool.
10332 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
10334 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
10335 u32 max_buff, u8 pool)
10337 MLXSW_REG_ZERO(sbmm, payload);
10338 mlxsw_reg_sbmm_prio_set(payload, prio);
10339 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
10340 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
10341 mlxsw_reg_sbmm_pool_set(payload, pool);
10344 /* SBSR - Shared Buffer Status Register
10345 * ------------------------------------
10346 * The SBSR register retrieves the shared buffer occupancy according to
10347 * Port-Pool. Note that this register enables reading a large amount of data.
10348 * It is the user's responsibility to limit the amount of data to ensure the
10349 * response can match the maximum transfer unit. In case the response exceeds
10350 * the maximum transport unit, it will be truncated with no special notice.
10352 #define MLXSW_REG_SBSR_ID 0xB005
10353 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
10354 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
10355 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
10356 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
10357 MLXSW_REG_SBSR_REC_LEN * \
10358 MLXSW_REG_SBSR_REC_MAX_COUNT)
10360 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
10363 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
10364 * field is cleared (and a new max value is tracked from the time the clear
10368 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
10370 /* reg_sbsr_ingress_port_mask
10371 * Bit vector for all ingress network ports.
10372 * Indicates which of the ports (for which the relevant bit is set)
10373 * are affected by the set operation. Configuration of any other port
10377 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
10379 /* reg_sbsr_pg_buff_mask
10380 * Bit vector for all switch priority groups.
10381 * Indicates which of the priorities (for which the relevant bit is set)
10382 * are affected by the set operation. Configuration of any other priority
10384 * Range is 0..cap_max_pg_buffers - 1
10387 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
10389 /* reg_sbsr_egress_port_mask
10390 * Bit vector for all egress network ports.
10391 * Indicates which of the ports (for which the relevant bit is set)
10392 * are affected by the set operation. Configuration of any other port
10396 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
10398 /* reg_sbsr_tclass_mask
10399 * Bit vector for all traffic classes.
10400 * Indicates which of the traffic classes (for which the relevant bit is
10401 * set) are affected by the set operation. Configuration of any other
10402 * traffic class does not change.
10403 * Range is 0..cap_max_tclass - 1
10406 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
10408 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
10410 MLXSW_REG_ZERO(sbsr, payload);
10411 mlxsw_reg_sbsr_clr_set(payload, clr);
10414 /* reg_sbsr_rec_buff_occupancy
10415 * Current buffer occupancy in cells.
10418 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10419 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
10421 /* reg_sbsr_rec_max_buff_occupancy
10422 * Maximum value of buffer occupancy in cells monitored. Cleared by
10423 * writing to the clr field.
10426 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
10427 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
10429 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
10430 u32 *p_buff_occupancy,
10431 u32 *p_max_buff_occupancy)
10433 *p_buff_occupancy =
10434 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
10435 *p_max_buff_occupancy =
10436 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
10439 /* SBIB - Shared Buffer Internal Buffer Register
10440 * ---------------------------------------------
10441 * The SBIB register configures per port buffers for internal use. The internal
10442 * buffers consume memory on the port buffers (note that the port buffers are
10443 * used also by PBMC).
10445 * For Spectrum this is used for egress mirroring.
10447 #define MLXSW_REG_SBIB_ID 0xB006
10448 #define MLXSW_REG_SBIB_LEN 0x10
10450 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
10452 /* reg_sbib_local_port
10453 * Local port number
10454 * Not supported for CPU port and router port
10457 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
10459 /* reg_sbib_buff_size
10460 * Units represented in cells
10461 * Allowed range is 0 to (cap_max_headroom_size - 1)
10465 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
10467 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
10470 MLXSW_REG_ZERO(sbib, payload);
10471 mlxsw_reg_sbib_local_port_set(payload, local_port);
10472 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
10475 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
10601 static inline const char *mlxsw_reg_id_str(u16 reg_id)
10603 const struct mlxsw_reg_info *reg_info;
10606 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
10607 reg_info = mlxsw_reg_infos[i];
10608 if (reg_info->id == reg_id)
10609 return reg_info->name;
10611 return "*UNKNOWN*";
10614 /* PUDE - Port Up / Down Event
10615 * ---------------------------
10616 * Reports the operational state change of a port.
10618 #define MLXSW_REG_PUDE_LEN 0x10
10621 * Switch partition ID with which to associate the port.
10624 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
10626 /* reg_pude_local_port
10627 * Local port number.
10630 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
10632 /* reg_pude_admin_status
10633 * Port administrative state (the desired state).
10636 * 3 - Up once. This means that in case of link failure, the port won't go
10637 * into polling mode, but will wait to be re-enabled by software.
10638 * 4 - Disabled by system. Can only be set by hardware.
10641 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
10643 /* reg_pude_oper_status
10644 * Port operatioanl state.
10647 * 3 - Down by port failure. This means that the device will not let the
10648 * port up again until explicitly specified by software.
10651 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);