1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/jhash.h>
25 #include <net/switchdev.h>
26 #include <net/pkt_cls.h>
27 #include <net/tc_act/tc_mirred.h>
28 #include <net/netevent.h>
29 #include <net/tc_act/tc_sample.h>
30 #include <net/addrconf.h>
40 #include "spectrum_cnt.h"
41 #include "spectrum_dpipe.h"
42 #include "spectrum_acl_flex_actions.h"
43 #include "spectrum_span.h"
44 #include "spectrum_ptp.h"
45 #include "../mlxfw/mlxfw.h"
47 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
49 #define MLXSW_SP1_FWREV_MAJOR 13
50 #define MLXSW_SP1_FWREV_MINOR 2000
51 #define MLXSW_SP1_FWREV_SUBMINOR 1886
52 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
54 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
55 .major = MLXSW_SP1_FWREV_MAJOR,
56 .minor = MLXSW_SP1_FWREV_MINOR,
57 .subminor = MLXSW_SP1_FWREV_SUBMINOR,
58 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
61 #define MLXSW_SP1_FW_FILENAME \
62 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
63 "." __stringify(MLXSW_SP1_FWREV_MINOR) \
64 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
66 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
67 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
68 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
69 static const char mlxsw_sp_driver_version[] = "1.0";
71 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
72 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
74 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
75 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
82 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
85 * Packet control type.
86 * 0 - Ethernet control (e.g. EMADs, LACP)
89 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
92 * Packet protocol type. Must be set to 1 (Ethernet).
94 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
96 /* tx_hdr_rx_is_router
97 * Packet is sent from the router. Valid for data packets only.
99 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
102 * Indicates if the 'fid' field is valid and should be used for
103 * forwarding lookup. Valid for data packets only.
105 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
108 * Switch partition ID. Must be set to 0.
110 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
112 /* tx_hdr_control_tclass
113 * Indicates if the packet should use the control TClass and not one
114 * of the data TClasses.
116 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
119 * Egress TClass to be used on the egress device on the egress port.
121 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
124 * Destination local port for unicast packets.
125 * Destination multicast ID for multicast packets.
127 * Control packets are directed to a specific egress port, while data
128 * packets are transmitted through the CPU port (0) into the switch partition,
129 * where forwarding rules are applied.
131 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
134 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
135 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
136 * Valid for data packets only.
138 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
142 * 6 - Control packets
144 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
146 struct mlxsw_sp_mlxfw_dev {
147 struct mlxfw_dev mlxfw_dev;
148 struct mlxsw_sp *mlxsw_sp;
151 struct mlxsw_sp_ptp_ops {
152 struct mlxsw_sp_ptp_clock *
153 (*clock_init)(struct mlxsw_sp *mlxsw_sp, struct device *dev);
154 void (*clock_fini)(struct mlxsw_sp_ptp_clock *clock);
156 struct mlxsw_sp_ptp_state *(*init)(struct mlxsw_sp *mlxsw_sp);
157 void (*fini)(struct mlxsw_sp_ptp_state *ptp_state);
159 /* Notify a driver that a packet that might be PTP was received. Driver
160 * is responsible for freeing the passed-in SKB.
162 void (*receive)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
165 /* Notify a driver that a timestamped packet was transmitted. Driver
166 * is responsible for freeing the passed-in SKB.
168 void (*transmitted)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
171 int (*hwtstamp_get)(struct mlxsw_sp_port *mlxsw_sp_port,
172 struct hwtstamp_config *config);
173 int (*hwtstamp_set)(struct mlxsw_sp_port *mlxsw_sp_port,
174 struct hwtstamp_config *config);
175 void (*shaper_work)(struct work_struct *work);
176 int (*get_ts_info)(struct mlxsw_sp *mlxsw_sp,
177 struct ethtool_ts_info *info);
178 int (*get_stats_count)(void);
179 void (*get_stats_strings)(u8 **p);
180 void (*get_stats)(struct mlxsw_sp_port *mlxsw_sp_port,
181 u64 *data, int data_index);
184 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
185 u16 component_index, u32 *p_max_size,
186 u8 *p_align_bits, u16 *p_max_write_size)
188 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
189 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
190 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
191 char mcqi_pl[MLXSW_REG_MCQI_LEN];
194 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
195 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
198 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
201 *p_align_bits = max_t(u8, *p_align_bits, 2);
202 *p_max_write_size = min_t(u16, *p_max_write_size,
203 MLXSW_REG_MCDA_MAX_DATA_LEN);
207 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
209 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
210 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
211 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
212 char mcc_pl[MLXSW_REG_MCC_LEN];
216 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
217 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
221 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
222 if (control_state != MLXFW_FSM_STATE_IDLE)
225 mlxsw_reg_mcc_pack(mcc_pl,
226 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
228 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
231 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
232 u32 fwhandle, u16 component_index,
235 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
236 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
237 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
238 char mcc_pl[MLXSW_REG_MCC_LEN];
240 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
241 component_index, fwhandle, component_size);
242 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
245 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
246 u32 fwhandle, u8 *data, u16 size,
249 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
250 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
251 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
252 char mcda_pl[MLXSW_REG_MCDA_LEN];
254 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
255 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
258 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
259 u32 fwhandle, u16 component_index)
261 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
262 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
263 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
264 char mcc_pl[MLXSW_REG_MCC_LEN];
266 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
267 component_index, fwhandle, 0);
268 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
271 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
273 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
274 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
275 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
276 char mcc_pl[MLXSW_REG_MCC_LEN];
278 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
280 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
283 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
284 enum mlxfw_fsm_state *fsm_state,
285 enum mlxfw_fsm_state_err *fsm_state_err)
287 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
288 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
289 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
290 char mcc_pl[MLXSW_REG_MCC_LEN];
295 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
296 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
300 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
301 *fsm_state = control_state;
302 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
303 MLXFW_FSM_STATE_ERR_MAX);
307 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
309 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
310 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
311 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
312 char mcc_pl[MLXSW_REG_MCC_LEN];
314 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
316 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
319 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
321 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
322 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
323 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
324 char mcc_pl[MLXSW_REG_MCC_LEN];
326 mlxsw_reg_mcc_pack(mcc_pl,
327 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
329 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
332 static void mlxsw_sp_status_notify(struct mlxfw_dev *mlxfw_dev,
333 const char *msg, const char *comp_name,
334 u32 done_bytes, u32 total_bytes)
336 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
337 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
338 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
340 devlink_flash_update_status_notify(priv_to_devlink(mlxsw_sp->core),
342 done_bytes, total_bytes);
345 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
346 .component_query = mlxsw_sp_component_query,
347 .fsm_lock = mlxsw_sp_fsm_lock,
348 .fsm_component_update = mlxsw_sp_fsm_component_update,
349 .fsm_block_download = mlxsw_sp_fsm_block_download,
350 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
351 .fsm_activate = mlxsw_sp_fsm_activate,
352 .fsm_query_state = mlxsw_sp_fsm_query_state,
353 .fsm_cancel = mlxsw_sp_fsm_cancel,
354 .fsm_release = mlxsw_sp_fsm_release,
355 .status_notify = mlxsw_sp_status_notify,
358 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
359 const struct firmware *firmware,
360 struct netlink_ext_ack *extack)
362 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
364 .ops = &mlxsw_sp_mlxfw_dev_ops,
365 .psid = mlxsw_sp->bus_info->psid,
366 .psid_size = strlen(mlxsw_sp->bus_info->psid),
372 mlxsw_core_fw_flash_start(mlxsw_sp->core);
373 devlink_flash_update_begin_notify(priv_to_devlink(mlxsw_sp->core));
374 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev,
376 devlink_flash_update_end_notify(priv_to_devlink(mlxsw_sp->core));
377 mlxsw_core_fw_flash_end(mlxsw_sp->core);
382 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
384 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
385 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
386 const char *fw_filename = mlxsw_sp->fw_filename;
387 union devlink_param_value value;
388 const struct firmware *firmware;
391 /* Don't check if driver does not require it */
392 if (!req_rev || !fw_filename)
395 /* Don't check if devlink 'fw_load_policy' param is 'flash' */
396 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core),
397 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
401 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)
404 /* Validate driver & FW are compatible */
405 if (rev->major != req_rev->major) {
406 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
407 rev->major, req_rev->major);
410 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
411 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
412 mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev))
415 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
416 rev->major, rev->minor, rev->subminor);
417 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
420 err = request_firmware_direct(&firmware, fw_filename,
421 mlxsw_sp->bus_info->dev);
423 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
428 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, NULL);
429 release_firmware(firmware);
431 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
433 /* On FW flash success, tell the caller FW reset is needed
434 * if current FW supports it.
436 if (rev->minor >= req_rev->can_reset_minor)
437 return err ? err : -EAGAIN;
442 static int mlxsw_sp_flash_update(struct mlxsw_core *mlxsw_core,
443 const char *file_name, const char *component,
444 struct netlink_ext_ack *extack)
446 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
447 const struct firmware *firmware;
453 err = request_firmware_direct(&firmware, file_name,
454 mlxsw_sp->bus_info->dev);
457 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, extack);
458 release_firmware(firmware);
463 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
464 unsigned int counter_index, u64 *packets,
467 char mgpc_pl[MLXSW_REG_MGPC_LEN];
470 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
471 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
472 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
476 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
478 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
482 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
483 unsigned int counter_index)
485 char mgpc_pl[MLXSW_REG_MGPC_LEN];
487 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
488 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
489 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
492 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
493 unsigned int *p_counter_index)
497 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
501 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
503 goto err_counter_clear;
507 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
512 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
513 unsigned int counter_index)
515 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
519 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
520 const struct mlxsw_tx_info *tx_info)
522 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
524 memset(txhdr, 0, MLXSW_TXHDR_LEN);
526 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
527 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
528 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
529 mlxsw_tx_hdr_swid_set(txhdr, 0);
530 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
531 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
532 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
535 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
538 case BR_STATE_FORWARDING:
539 return MLXSW_REG_SPMS_STATE_FORWARDING;
540 case BR_STATE_LEARNING:
541 return MLXSW_REG_SPMS_STATE_LEARNING;
542 case BR_STATE_LISTENING: /* fall-through */
543 case BR_STATE_DISABLED: /* fall-through */
544 case BR_STATE_BLOCKING:
545 return MLXSW_REG_SPMS_STATE_DISCARDING;
551 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
554 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
555 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
559 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
562 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
563 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
565 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
570 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
572 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
575 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
578 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
582 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
583 bool enable, u32 rate)
585 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
586 char mpsc_pl[MLXSW_REG_MPSC_LEN];
588 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
589 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
592 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
595 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
596 char paos_pl[MLXSW_REG_PAOS_LEN];
598 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
599 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
600 MLXSW_PORT_ADMIN_STATUS_DOWN);
601 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
604 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
607 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
608 char ppad_pl[MLXSW_REG_PPAD_LEN];
610 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
611 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
612 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
615 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
617 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
618 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
620 ether_addr_copy(addr, mlxsw_sp->base_mac);
621 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
622 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
625 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
627 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
628 char pmtu_pl[MLXSW_REG_PMTU_LEN];
632 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
633 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
634 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
637 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
642 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
643 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
646 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
648 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
649 char pspa_pl[MLXSW_REG_PSPA_LEN];
651 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
652 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
655 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
657 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
658 char svpe_pl[MLXSW_REG_SVPE_LEN];
660 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
661 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
664 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
667 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
671 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
674 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
676 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
681 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
684 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
685 char spvid_pl[MLXSW_REG_SPVID_LEN];
687 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
688 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
691 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
694 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
695 char spaft_pl[MLXSW_REG_SPAFT_LEN];
697 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
698 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
701 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
706 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
710 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
713 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
715 goto err_port_allow_untagged_set;
718 mlxsw_sp_port->pvid = vid;
721 err_port_allow_untagged_set:
722 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
727 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
729 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
730 char sspr_pl[MLXSW_REG_SSPR_LEN];
732 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
733 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
736 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
737 u8 local_port, u8 *p_module,
738 u8 *p_width, u8 *p_lane)
740 char pmlp_pl[MLXSW_REG_PMLP_LEN];
743 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
744 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
747 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
748 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
749 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
753 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
754 u8 module, u8 width, u8 lane)
756 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
757 char pmlp_pl[MLXSW_REG_PMLP_LEN];
760 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
761 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
762 for (i = 0; i < width; i++) {
763 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
764 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
767 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
770 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
772 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
773 char pmlp_pl[MLXSW_REG_PMLP_LEN];
775 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
776 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
777 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
780 static int mlxsw_sp_port_open(struct net_device *dev)
782 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
785 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
788 netif_start_queue(dev);
792 static int mlxsw_sp_port_stop(struct net_device *dev)
794 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
796 netif_stop_queue(dev);
797 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
800 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
801 struct net_device *dev)
803 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
804 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
805 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
806 const struct mlxsw_tx_info tx_info = {
807 .local_port = mlxsw_sp_port->local_port,
813 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
815 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
816 return NETDEV_TX_BUSY;
818 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
819 struct sk_buff *skb_orig = skb;
821 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
823 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
824 dev_kfree_skb_any(skb_orig);
827 dev_consume_skb_any(skb_orig);
830 if (eth_skb_pad(skb)) {
831 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
835 mlxsw_sp_txhdr_construct(skb, &tx_info);
836 /* TX header is consumed by HW on the way so we shouldn't count its
837 * bytes as being sent.
839 len = skb->len - MLXSW_TXHDR_LEN;
841 /* Due to a race we might fail here because of a full queue. In that
842 * unlikely case we simply drop the packet.
844 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
847 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
848 u64_stats_update_begin(&pcpu_stats->syncp);
849 pcpu_stats->tx_packets++;
850 pcpu_stats->tx_bytes += len;
851 u64_stats_update_end(&pcpu_stats->syncp);
853 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
854 dev_kfree_skb_any(skb);
859 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
863 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
865 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
866 struct sockaddr *addr = p;
869 if (!is_valid_ether_addr(addr->sa_data))
870 return -EADDRNOTAVAIL;
872 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
875 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
879 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
882 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
885 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
887 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
890 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
892 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
896 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
897 * Assumes 100m cable and maximum MTU.
899 #define MLXSW_SP_PAUSE_DELAY 58752
901 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
902 u16 delay, bool pfc, bool pause)
905 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
907 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
912 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
916 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
918 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
922 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
923 u8 *prio_tc, bool pause_en,
924 struct ieee_pfc *my_pfc)
926 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
927 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
928 u16 delay = !!my_pfc ? my_pfc->delay : 0;
929 char pbmc_pl[MLXSW_REG_PBMC_LEN];
930 u32 taken_headroom_cells = 0;
931 u32 max_headroom_cells;
934 max_headroom_cells = mlxsw_sp_sb_max_headroom_cells(mlxsw_sp);
936 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
937 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
941 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
942 bool configure = false;
949 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
950 if (prio_tc[j] == i) {
951 pfc = pfc_en & BIT(j);
960 lossy = !(pfc || pause_en);
961 thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
962 delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
964 total_cells = thres_cells + delay_cells;
966 taken_headroom_cells += total_cells;
967 if (taken_headroom_cells > max_headroom_cells)
970 mlxsw_sp_pg_buf_pack(pbmc_pl, i, total_cells,
974 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
977 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
978 int mtu, bool pause_en)
980 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
981 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
982 struct ieee_pfc *my_pfc;
985 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
986 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
988 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
992 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
994 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
995 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
998 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
1001 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1003 goto err_span_port_mtu_update;
1004 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1006 goto err_port_mtu_set;
1011 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1012 err_span_port_mtu_update:
1013 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1018 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1019 struct rtnl_link_stats64 *stats)
1021 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1022 struct mlxsw_sp_port_pcpu_stats *p;
1023 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1028 for_each_possible_cpu(i) {
1029 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1031 start = u64_stats_fetch_begin_irq(&p->syncp);
1032 rx_packets = p->rx_packets;
1033 rx_bytes = p->rx_bytes;
1034 tx_packets = p->tx_packets;
1035 tx_bytes = p->tx_bytes;
1036 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1038 stats->rx_packets += rx_packets;
1039 stats->rx_bytes += rx_bytes;
1040 stats->tx_packets += tx_packets;
1041 stats->tx_bytes += tx_bytes;
1042 /* tx_dropped is u32, updated without syncp protection. */
1043 tx_dropped += p->tx_dropped;
1045 stats->tx_dropped = tx_dropped;
1049 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
1052 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1059 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1063 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1064 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1070 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1071 int prio, char *ppcnt_pl)
1073 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1074 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1076 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1077 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1080 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1081 struct rtnl_link_stats64 *stats)
1083 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1086 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1092 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1094 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1096 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1098 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1100 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1102 stats->rx_crc_errors =
1103 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1104 stats->rx_frame_errors =
1105 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1107 stats->rx_length_errors = (
1108 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1109 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1110 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1112 stats->rx_errors = (stats->rx_crc_errors +
1113 stats->rx_frame_errors + stats->rx_length_errors);
1120 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1121 struct mlxsw_sp_port_xstats *xstats)
1123 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1126 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1129 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1131 for (i = 0; i < TC_MAX_QUEUE; i++) {
1132 err = mlxsw_sp_port_get_stats_raw(dev,
1133 MLXSW_REG_PPCNT_TC_CONG_TC,
1136 xstats->wred_drop[i] =
1137 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1139 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1144 xstats->backlog[i] =
1145 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1146 xstats->tail_drop[i] =
1147 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1150 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1151 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1156 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1157 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1161 static void update_stats_cache(struct work_struct *work)
1163 struct mlxsw_sp_port *mlxsw_sp_port =
1164 container_of(work, struct mlxsw_sp_port,
1165 periodic_hw_stats.update_dw.work);
1167 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1170 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1171 &mlxsw_sp_port->periodic_hw_stats.stats);
1172 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1173 &mlxsw_sp_port->periodic_hw_stats.xstats);
1176 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1177 MLXSW_HW_STATS_UPDATE_TIME);
1180 /* Return the stats from a cache that is updated periodically,
1181 * as this function might get called in an atomic context.
1184 mlxsw_sp_port_get_stats64(struct net_device *dev,
1185 struct rtnl_link_stats64 *stats)
1187 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1189 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1192 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1193 u16 vid_begin, u16 vid_end,
1194 bool is_member, bool untagged)
1196 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1200 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1204 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1205 vid_end, is_member, untagged);
1206 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1211 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1212 u16 vid_end, bool is_member, bool untagged)
1217 for (vid = vid_begin; vid <= vid_end;
1218 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1219 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1222 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1223 is_member, untagged);
1231 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1234 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1236 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1237 &mlxsw_sp_port->vlans_list, list) {
1238 if (!flush_default &&
1239 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1241 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1246 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1248 if (mlxsw_sp_port_vlan->bridge_port)
1249 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1250 else if (mlxsw_sp_port_vlan->fid)
1251 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1254 struct mlxsw_sp_port_vlan *
1255 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1257 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1258 bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1261 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1262 if (mlxsw_sp_port_vlan)
1263 return ERR_PTR(-EEXIST);
1265 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1267 return ERR_PTR(err);
1269 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1270 if (!mlxsw_sp_port_vlan) {
1272 goto err_port_vlan_alloc;
1275 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1276 mlxsw_sp_port_vlan->vid = vid;
1277 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1279 return mlxsw_sp_port_vlan;
1281 err_port_vlan_alloc:
1282 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1283 return ERR_PTR(err);
1286 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1288 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1289 u16 vid = mlxsw_sp_port_vlan->vid;
1291 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1292 list_del(&mlxsw_sp_port_vlan->list);
1293 kfree(mlxsw_sp_port_vlan);
1294 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1297 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1298 __be16 __always_unused proto, u16 vid)
1300 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1302 /* VLAN 0 is added to HW filter when device goes up, but it is
1303 * reserved in our case, so simply return.
1308 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1311 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1312 __be16 __always_unused proto, u16 vid)
1314 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1315 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1317 /* VLAN 0 is removed from HW filter when device goes down, but
1318 * it is reserved in our case, so simply return.
1323 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1324 if (!mlxsw_sp_port_vlan)
1326 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1331 static struct mlxsw_sp_port_mall_tc_entry *
1332 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1333 unsigned long cookie) {
1334 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1336 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1337 if (mall_tc_entry->cookie == cookie)
1338 return mall_tc_entry;
1344 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1345 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1346 const struct flow_action_entry *act,
1349 enum mlxsw_sp_span_type span_type;
1352 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1356 mirror->ingress = ingress;
1357 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1358 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, act->dev, span_type,
1359 true, &mirror->span_id);
1363 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1364 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1366 enum mlxsw_sp_span_type span_type;
1368 span_type = mirror->ingress ?
1369 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1370 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1375 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1376 struct tc_cls_matchall_offload *cls,
1377 const struct flow_action_entry *act,
1382 if (!mlxsw_sp_port->sample)
1384 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1385 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1388 if (act->sample.rate > MLXSW_REG_MPSC_RATE_MAX) {
1389 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1393 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1394 act->sample.psample_group);
1395 mlxsw_sp_port->sample->truncate = act->sample.truncate;
1396 mlxsw_sp_port->sample->trunc_size = act->sample.trunc_size;
1397 mlxsw_sp_port->sample->rate = act->sample.rate;
1399 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, act->sample.rate);
1401 goto err_port_sample_set;
1404 err_port_sample_set:
1405 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1410 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1412 if (!mlxsw_sp_port->sample)
1415 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1416 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1419 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1420 struct tc_cls_matchall_offload *f,
1423 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1424 __be16 protocol = f->common.protocol;
1425 struct flow_action_entry *act;
1428 if (!flow_offload_has_one_action(&f->rule->action)) {
1429 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1433 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1436 mall_tc_entry->cookie = f->cookie;
1438 act = &f->rule->action.entries[0];
1440 if (act->id == FLOW_ACTION_MIRRED && protocol == htons(ETH_P_ALL)) {
1441 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1443 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1444 mirror = &mall_tc_entry->mirror;
1445 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1448 } else if (act->id == FLOW_ACTION_SAMPLE &&
1449 protocol == htons(ETH_P_ALL)) {
1450 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1451 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1458 goto err_add_action;
1460 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1464 kfree(mall_tc_entry);
1468 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1469 struct tc_cls_matchall_offload *f)
1471 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1473 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1475 if (!mall_tc_entry) {
1476 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1479 list_del(&mall_tc_entry->list);
1481 switch (mall_tc_entry->type) {
1482 case MLXSW_SP_PORT_MALL_MIRROR:
1483 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1484 &mall_tc_entry->mirror);
1486 case MLXSW_SP_PORT_MALL_SAMPLE:
1487 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1493 kfree(mall_tc_entry);
1496 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1497 struct tc_cls_matchall_offload *f,
1500 switch (f->command) {
1501 case TC_CLSMATCHALL_REPLACE:
1502 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1504 case TC_CLSMATCHALL_DESTROY:
1505 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1513 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1514 struct flow_cls_offload *f)
1516 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1518 switch (f->command) {
1519 case FLOW_CLS_REPLACE:
1520 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1521 case FLOW_CLS_DESTROY:
1522 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1524 case FLOW_CLS_STATS:
1525 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1526 case FLOW_CLS_TMPLT_CREATE:
1527 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1528 case FLOW_CLS_TMPLT_DESTROY:
1529 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1536 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1538 void *cb_priv, bool ingress)
1540 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1543 case TC_SETUP_CLSMATCHALL:
1544 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1548 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1550 case TC_SETUP_CLSFLOWER:
1557 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1561 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1565 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1569 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1573 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1574 void *type_data, void *cb_priv)
1576 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1579 case TC_SETUP_CLSMATCHALL:
1581 case TC_SETUP_CLSFLOWER:
1582 if (mlxsw_sp_acl_block_disabled(acl_block))
1585 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1591 static void mlxsw_sp_tc_block_flower_release(void *cb_priv)
1593 struct mlxsw_sp_acl_block *acl_block = cb_priv;
1595 mlxsw_sp_acl_block_destroy(acl_block);
1598 static LIST_HEAD(mlxsw_sp_block_cb_list);
1601 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1602 struct flow_block_offload *f, bool ingress)
1604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1605 struct mlxsw_sp_acl_block *acl_block;
1606 struct flow_block_cb *block_cb;
1607 bool register_block = false;
1610 block_cb = flow_block_cb_lookup(f->block,
1611 mlxsw_sp_setup_tc_block_cb_flower,
1614 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, f->net);
1617 block_cb = flow_block_cb_alloc(mlxsw_sp_setup_tc_block_cb_flower,
1618 mlxsw_sp, acl_block,
1619 mlxsw_sp_tc_block_flower_release);
1620 if (IS_ERR(block_cb)) {
1621 mlxsw_sp_acl_block_destroy(acl_block);
1622 err = PTR_ERR(block_cb);
1623 goto err_cb_register;
1625 register_block = true;
1627 acl_block = flow_block_cb_priv(block_cb);
1629 flow_block_cb_incref(block_cb);
1630 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1631 mlxsw_sp_port, ingress, f->extack);
1633 goto err_block_bind;
1636 mlxsw_sp_port->ing_acl_block = acl_block;
1638 mlxsw_sp_port->eg_acl_block = acl_block;
1640 if (register_block) {
1641 flow_block_cb_add(block_cb, f);
1642 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1648 if (!flow_block_cb_decref(block_cb))
1649 flow_block_cb_free(block_cb);
1655 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1656 struct flow_block_offload *f, bool ingress)
1658 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1659 struct mlxsw_sp_acl_block *acl_block;
1660 struct flow_block_cb *block_cb;
1663 block_cb = flow_block_cb_lookup(f->block,
1664 mlxsw_sp_setup_tc_block_cb_flower,
1670 mlxsw_sp_port->ing_acl_block = NULL;
1672 mlxsw_sp_port->eg_acl_block = NULL;
1674 acl_block = flow_block_cb_priv(block_cb);
1675 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1676 mlxsw_sp_port, ingress);
1677 if (!err && !flow_block_cb_decref(block_cb)) {
1678 flow_block_cb_remove(block_cb, f);
1679 list_del(&block_cb->driver_list);
1683 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1684 struct flow_block_offload *f)
1686 struct flow_block_cb *block_cb;
1687 flow_setup_cb_t *cb;
1691 if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1692 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1694 } else if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1695 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1701 f->driver_block_list = &mlxsw_sp_block_cb_list;
1703 switch (f->command) {
1704 case FLOW_BLOCK_BIND:
1705 if (flow_block_cb_is_busy(cb, mlxsw_sp_port,
1706 &mlxsw_sp_block_cb_list))
1709 block_cb = flow_block_cb_alloc(cb, mlxsw_sp_port,
1710 mlxsw_sp_port, NULL);
1711 if (IS_ERR(block_cb))
1712 return PTR_ERR(block_cb);
1713 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, f,
1716 flow_block_cb_free(block_cb);
1719 flow_block_cb_add(block_cb, f);
1720 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1722 case FLOW_BLOCK_UNBIND:
1723 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1725 block_cb = flow_block_cb_lookup(f->block, cb, mlxsw_sp_port);
1729 flow_block_cb_remove(block_cb, f);
1730 list_del(&block_cb->driver_list);
1737 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1740 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1743 case TC_SETUP_BLOCK:
1744 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1745 case TC_SETUP_QDISC_RED:
1746 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1747 case TC_SETUP_QDISC_PRIO:
1748 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1755 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1757 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1760 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1761 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1762 !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1763 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1766 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1767 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1769 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1770 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1775 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1777 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1778 char pplr_pl[MLXSW_REG_PPLR_LEN];
1781 if (netif_running(dev))
1782 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1784 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1785 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1788 if (netif_running(dev))
1789 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1794 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1796 static int mlxsw_sp_handle_feature(struct net_device *dev,
1797 netdev_features_t wanted_features,
1798 netdev_features_t feature,
1799 mlxsw_sp_feature_handler feature_handler)
1801 netdev_features_t changes = wanted_features ^ dev->features;
1802 bool enable = !!(wanted_features & feature);
1805 if (!(changes & feature))
1808 err = feature_handler(dev, enable);
1810 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1811 enable ? "Enable" : "Disable", &feature, err);
1816 dev->features |= feature;
1818 dev->features &= ~feature;
1822 static int mlxsw_sp_set_features(struct net_device *dev,
1823 netdev_features_t features)
1825 netdev_features_t oper_features = dev->features;
1828 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1829 mlxsw_sp_feature_hw_tc);
1830 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1831 mlxsw_sp_feature_loopback);
1834 dev->features = oper_features;
1841 static struct devlink_port *
1842 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1844 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1845 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1847 return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1848 mlxsw_sp_port->local_port);
1851 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1854 struct hwtstamp_config config;
1857 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1860 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1865 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1871 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1874 struct hwtstamp_config config;
1877 err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1882 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1888 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1890 struct hwtstamp_config config = {0};
1892 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1896 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1898 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1902 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1904 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1910 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1911 .ndo_open = mlxsw_sp_port_open,
1912 .ndo_stop = mlxsw_sp_port_stop,
1913 .ndo_start_xmit = mlxsw_sp_port_xmit,
1914 .ndo_setup_tc = mlxsw_sp_setup_tc,
1915 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
1916 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1917 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1918 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
1919 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1920 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
1921 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1922 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1923 .ndo_set_features = mlxsw_sp_set_features,
1924 .ndo_get_devlink_port = mlxsw_sp_port_get_devlink_port,
1925 .ndo_do_ioctl = mlxsw_sp_port_ioctl,
1928 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1929 struct ethtool_drvinfo *drvinfo)
1931 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1932 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1934 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1935 sizeof(drvinfo->driver));
1936 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1937 sizeof(drvinfo->version));
1938 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1940 mlxsw_sp->bus_info->fw_rev.major,
1941 mlxsw_sp->bus_info->fw_rev.minor,
1942 mlxsw_sp->bus_info->fw_rev.subminor);
1943 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1944 sizeof(drvinfo->bus_info));
1947 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1948 struct ethtool_pauseparam *pause)
1950 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1952 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1953 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1956 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1957 struct ethtool_pauseparam *pause)
1959 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1961 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1962 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1963 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1965 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1969 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1970 struct ethtool_pauseparam *pause)
1972 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1973 bool pause_en = pause->tx_pause || pause->rx_pause;
1976 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1977 netdev_err(dev, "PFC already enabled on port\n");
1981 if (pause->autoneg) {
1982 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1986 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1988 netdev_err(dev, "Failed to configure port's headroom\n");
1992 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1994 netdev_err(dev, "Failed to set PAUSE parameters\n");
1995 goto err_port_pause_configure;
1998 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1999 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2003 err_port_pause_configure:
2004 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2005 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2009 struct mlxsw_sp_port_hw_stats {
2010 char str[ETH_GSTRING_LEN];
2011 u64 (*getter)(const char *payload);
2015 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
2017 .str = "a_frames_transmitted_ok",
2018 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2021 .str = "a_frames_received_ok",
2022 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2025 .str = "a_frame_check_sequence_errors",
2026 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2029 .str = "a_alignment_errors",
2030 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2033 .str = "a_octets_transmitted_ok",
2034 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2037 .str = "a_octets_received_ok",
2038 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2041 .str = "a_multicast_frames_xmitted_ok",
2042 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2045 .str = "a_broadcast_frames_xmitted_ok",
2046 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2049 .str = "a_multicast_frames_received_ok",
2050 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2053 .str = "a_broadcast_frames_received_ok",
2054 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2057 .str = "a_in_range_length_errors",
2058 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2061 .str = "a_out_of_range_length_field",
2062 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2065 .str = "a_frame_too_long_errors",
2066 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2069 .str = "a_symbol_error_during_carrier",
2070 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2073 .str = "a_mac_control_frames_transmitted",
2074 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2077 .str = "a_mac_control_frames_received",
2078 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2081 .str = "a_unsupported_opcodes_received",
2082 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2085 .str = "a_pause_mac_ctrl_frames_received",
2086 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2089 .str = "a_pause_mac_ctrl_frames_xmitted",
2090 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2094 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2096 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
2098 .str = "if_in_discards",
2099 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
2102 .str = "if_out_discards",
2103 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
2106 .str = "if_out_errors",
2107 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
2111 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
2112 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
2114 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
2116 .str = "ether_stats_undersize_pkts",
2117 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
2120 .str = "ether_stats_oversize_pkts",
2121 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
2124 .str = "ether_stats_fragments",
2125 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
2128 .str = "ether_pkts64octets",
2129 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
2132 .str = "ether_pkts65to127octets",
2133 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
2136 .str = "ether_pkts128to255octets",
2137 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
2140 .str = "ether_pkts256to511octets",
2141 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
2144 .str = "ether_pkts512to1023octets",
2145 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
2148 .str = "ether_pkts1024to1518octets",
2149 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
2152 .str = "ether_pkts1519to2047octets",
2153 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
2156 .str = "ether_pkts2048to4095octets",
2157 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
2160 .str = "ether_pkts4096to8191octets",
2161 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
2164 .str = "ether_pkts8192to10239octets",
2165 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
2169 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
2170 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
2172 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
2174 .str = "dot3stats_fcs_errors",
2175 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
2178 .str = "dot3stats_symbol_errors",
2179 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
2182 .str = "dot3control_in_unknown_opcodes",
2183 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
2186 .str = "dot3in_pause_frames",
2187 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
2191 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
2192 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
2194 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
2196 .str = "discard_ingress_general",
2197 .getter = mlxsw_reg_ppcnt_ingress_general_get,
2200 .str = "discard_ingress_policy_engine",
2201 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
2204 .str = "discard_ingress_vlan_membership",
2205 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
2208 .str = "discard_ingress_tag_frame_type",
2209 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
2212 .str = "discard_egress_vlan_membership",
2213 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
2216 .str = "discard_loopback_filter",
2217 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
2220 .str = "discard_egress_general",
2221 .getter = mlxsw_reg_ppcnt_egress_general_get,
2224 .str = "discard_egress_hoq",
2225 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
2228 .str = "discard_egress_policy_engine",
2229 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
2232 .str = "discard_ingress_tx_link_down",
2233 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
2236 .str = "discard_egress_stp_filter",
2237 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
2240 .str = "discard_egress_sll",
2241 .getter = mlxsw_reg_ppcnt_egress_sll_get,
2245 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
2246 ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
2248 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2250 .str = "rx_octets_prio",
2251 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2254 .str = "rx_frames_prio",
2255 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2258 .str = "tx_octets_prio",
2259 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2262 .str = "tx_frames_prio",
2263 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2266 .str = "rx_pause_prio",
2267 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2270 .str = "rx_pause_duration_prio",
2271 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2274 .str = "tx_pause_prio",
2275 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2278 .str = "tx_pause_duration_prio",
2279 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2283 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2285 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2287 .str = "tc_transmit_queue_tc",
2288 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2289 .cells_bytes = true,
2292 .str = "tc_no_buffer_discard_uc_tc",
2293 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2297 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2299 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
2300 MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
2301 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
2302 MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
2303 MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
2304 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
2305 IEEE_8021QAZ_MAX_TCS) + \
2306 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
2309 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2313 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2314 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2315 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2316 *p += ETH_GSTRING_LEN;
2320 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2324 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2325 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2326 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2327 *p += ETH_GSTRING_LEN;
2331 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2332 u32 stringset, u8 *data)
2334 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2338 switch (stringset) {
2340 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2341 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2343 p += ETH_GSTRING_LEN;
2346 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
2347 memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
2349 p += ETH_GSTRING_LEN;
2352 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2353 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2355 p += ETH_GSTRING_LEN;
2358 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
2359 memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
2361 p += ETH_GSTRING_LEN;
2364 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
2365 memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
2367 p += ETH_GSTRING_LEN;
2370 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2371 mlxsw_sp_port_get_prio_strings(&p, i);
2373 for (i = 0; i < TC_MAX_QUEUE; i++)
2374 mlxsw_sp_port_get_tc_strings(&p, i);
2376 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
2381 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2382 enum ethtool_phys_id_state state)
2384 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2385 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2386 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2390 case ETHTOOL_ID_ACTIVE:
2393 case ETHTOOL_ID_INACTIVE:
2400 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2401 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2405 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2406 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2409 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2410 *p_hw_stats = mlxsw_sp_port_hw_stats;
2411 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2413 case MLXSW_REG_PPCNT_RFC_2863_CNT:
2414 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
2415 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2417 case MLXSW_REG_PPCNT_RFC_2819_CNT:
2418 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2419 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2421 case MLXSW_REG_PPCNT_RFC_3635_CNT:
2422 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
2423 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2425 case MLXSW_REG_PPCNT_DISCARD_CNT:
2426 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
2427 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2429 case MLXSW_REG_PPCNT_PRIO_CNT:
2430 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2431 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2433 case MLXSW_REG_PPCNT_TC_CNT:
2434 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2435 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2444 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2445 enum mlxsw_reg_ppcnt_grp grp, int prio,
2446 u64 *data, int data_index)
2448 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2449 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2450 struct mlxsw_sp_port_hw_stats *hw_stats;
2451 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2455 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2458 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2459 for (i = 0; i < len; i++) {
2460 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2461 if (!hw_stats[i].cells_bytes)
2463 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2464 data[data_index + i]);
2468 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2469 struct ethtool_stats *stats, u64 *data)
2471 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2472 int i, data_index = 0;
2474 /* IEEE 802.3 Counters */
2475 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2477 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2479 /* RFC 2863 Counters */
2480 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
2482 data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2484 /* RFC 2819 Counters */
2485 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2487 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2489 /* RFC 3635 Counters */
2490 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
2492 data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2494 /* Discard Counters */
2495 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
2497 data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2499 /* Per-Priority Counters */
2500 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2501 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2503 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2506 /* Per-TC Counters */
2507 for (i = 0; i < TC_MAX_QUEUE; i++) {
2508 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2510 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2514 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
2516 data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2519 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2521 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2525 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
2526 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2532 struct mlxsw_sp1_port_link_mode {
2533 enum ethtool_link_mode_bit_indices mask_ethtool;
2538 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
2540 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2541 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2545 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2546 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2547 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2548 .speed = SPEED_1000,
2551 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2552 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2553 .speed = SPEED_10000,
2556 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2557 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2558 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2559 .speed = SPEED_10000,
2562 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2563 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2564 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2565 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2566 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2567 .speed = SPEED_10000,
2570 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2571 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2572 .speed = SPEED_20000,
2575 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2576 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2577 .speed = SPEED_40000,
2580 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2581 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2582 .speed = SPEED_40000,
2585 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2586 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2587 .speed = SPEED_40000,
2590 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2591 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2592 .speed = SPEED_40000,
2595 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2596 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2597 .speed = SPEED_25000,
2600 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2601 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2602 .speed = SPEED_25000,
2605 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2606 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2607 .speed = SPEED_25000,
2610 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2611 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2612 .speed = SPEED_50000,
2615 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2616 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2617 .speed = SPEED_50000,
2620 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2621 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2622 .speed = SPEED_50000,
2625 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2626 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2627 .speed = SPEED_100000,
2630 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2631 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2632 .speed = SPEED_100000,
2635 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2636 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2637 .speed = SPEED_100000,
2640 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2641 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2642 .speed = SPEED_100000,
2646 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
2649 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
2651 struct ethtool_link_ksettings *cmd)
2653 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2654 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2655 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2656 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2657 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2658 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2659 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2661 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2662 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2663 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2664 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2665 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2666 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2670 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
2671 u8 width, unsigned long *mode)
2675 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2676 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2677 __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2683 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
2687 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2688 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2689 return mlxsw_sp1_port_link_mode[i].speed;
2692 return SPEED_UNKNOWN;
2696 mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
2698 struct ethtool_link_ksettings *cmd)
2700 cmd->base.speed = SPEED_UNKNOWN;
2701 cmd->base.duplex = DUPLEX_UNKNOWN;
2706 cmd->base.speed = mlxsw_sp1_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
2707 if (cmd->base.speed != SPEED_UNKNOWN)
2708 cmd->base.duplex = DUPLEX_FULL;
2712 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
2713 const struct ethtool_link_ksettings *cmd)
2718 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2719 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2720 cmd->link_modes.advertising))
2721 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2726 static u32 mlxsw_sp1_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u8 width,
2732 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2733 if (speed == mlxsw_sp1_port_link_mode[i].speed)
2734 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2740 mlxsw_sp1_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
2745 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2746 if (mlxsw_sp1_port_link_mode[i].speed <= upper_speed)
2747 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2753 mlxsw_sp1_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2756 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
2761 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
2762 u8 local_port, u32 proto_admin, bool autoneg)
2764 mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
2768 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
2769 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
2770 u32 *p_eth_proto_oper)
2772 mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
2776 static const struct mlxsw_sp_port_type_speed_ops
2777 mlxsw_sp1_port_type_speed_ops = {
2778 .from_ptys_supported_port = mlxsw_sp1_from_ptys_supported_port,
2779 .from_ptys_link = mlxsw_sp1_from_ptys_link,
2780 .from_ptys_speed = mlxsw_sp1_from_ptys_speed,
2781 .from_ptys_speed_duplex = mlxsw_sp1_from_ptys_speed_duplex,
2782 .to_ptys_advert_link = mlxsw_sp1_to_ptys_advert_link,
2783 .to_ptys_speed = mlxsw_sp1_to_ptys_speed,
2784 .to_ptys_upper_speed = mlxsw_sp1_to_ptys_upper_speed,
2785 .port_speed_base = mlxsw_sp1_port_speed_base,
2786 .reg_ptys_eth_pack = mlxsw_sp1_reg_ptys_eth_pack,
2787 .reg_ptys_eth_unpack = mlxsw_sp1_reg_ptys_eth_unpack,
2790 static const enum ethtool_link_mode_bit_indices
2791 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
2792 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2795 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
2796 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
2798 static const enum ethtool_link_mode_bit_indices
2799 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
2800 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2801 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2804 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
2805 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
2807 static const enum ethtool_link_mode_bit_indices
2808 mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {
2809 ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
2812 #define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \
2813 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)
2815 static const enum ethtool_link_mode_bit_indices
2816 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
2817 ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2820 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
2821 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
2823 static const enum ethtool_link_mode_bit_indices
2824 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
2825 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2826 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2827 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
2828 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2829 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2830 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2831 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
2834 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
2835 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
2837 static const enum ethtool_link_mode_bit_indices
2838 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
2839 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2840 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2841 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2842 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2845 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
2846 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
2848 static const enum ethtool_link_mode_bit_indices
2849 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
2850 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2851 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2852 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2855 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
2856 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
2858 static const enum ethtool_link_mode_bit_indices
2859 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
2860 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2861 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2862 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2865 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
2866 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
2868 static const enum ethtool_link_mode_bit_indices
2869 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
2870 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2871 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2872 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2873 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2874 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
2877 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
2878 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
2880 static const enum ethtool_link_mode_bit_indices
2881 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
2882 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2883 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2884 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2885 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2888 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
2889 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
2891 static const enum ethtool_link_mode_bit_indices
2892 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
2893 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2894 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2895 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2896 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2897 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
2900 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
2901 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
2903 static const enum ethtool_link_mode_bit_indices
2904 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
2905 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2906 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2907 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2908 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
2909 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2912 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
2913 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
2915 #define MLXSW_SP_PORT_MASK_WIDTH_1X BIT(0)
2916 #define MLXSW_SP_PORT_MASK_WIDTH_2X BIT(1)
2917 #define MLXSW_SP_PORT_MASK_WIDTH_4X BIT(2)
2919 static u8 mlxsw_sp_port_mask_width_get(u8 width)
2923 return MLXSW_SP_PORT_MASK_WIDTH_1X;
2925 return MLXSW_SP_PORT_MASK_WIDTH_2X;
2927 return MLXSW_SP_PORT_MASK_WIDTH_4X;
2934 struct mlxsw_sp2_port_link_mode {
2935 const enum ethtool_link_mode_bit_indices *mask_ethtool;
2942 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
2944 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
2945 .mask_ethtool = mlxsw_sp2_mask_ethtool_sgmii_100m,
2946 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
2947 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2948 MLXSW_SP_PORT_MASK_WIDTH_2X |
2949 MLXSW_SP_PORT_MASK_WIDTH_4X,
2953 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
2954 .mask_ethtool = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
2955 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
2956 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2957 MLXSW_SP_PORT_MASK_WIDTH_2X |
2958 MLXSW_SP_PORT_MASK_WIDTH_4X,
2959 .speed = SPEED_1000,
2962 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,
2963 .mask_ethtool = mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,
2964 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
2965 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2966 MLXSW_SP_PORT_MASK_WIDTH_2X |
2967 MLXSW_SP_PORT_MASK_WIDTH_4X,
2968 .speed = SPEED_2500,
2971 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
2972 .mask_ethtool = mlxsw_sp2_mask_ethtool_5gbase_r,
2973 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
2974 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2975 MLXSW_SP_PORT_MASK_WIDTH_2X |
2976 MLXSW_SP_PORT_MASK_WIDTH_4X,
2977 .speed = SPEED_5000,
2980 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
2981 .mask_ethtool = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
2982 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
2983 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
2984 MLXSW_SP_PORT_MASK_WIDTH_2X |
2985 MLXSW_SP_PORT_MASK_WIDTH_4X,
2986 .speed = SPEED_10000,
2989 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
2990 .mask_ethtool = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
2991 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
2992 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X,
2993 .speed = SPEED_40000,
2996 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
2997 .mask_ethtool = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
2998 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
2999 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
3000 MLXSW_SP_PORT_MASK_WIDTH_2X |
3001 MLXSW_SP_PORT_MASK_WIDTH_4X,
3002 .speed = SPEED_25000,
3005 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
3006 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
3007 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
3008 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_2X |
3009 MLXSW_SP_PORT_MASK_WIDTH_4X,
3010 .speed = SPEED_50000,
3013 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
3014 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
3015 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
3016 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_1X,
3017 .speed = SPEED_50000,
3020 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
3021 .mask_ethtool = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
3022 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
3023 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X,
3024 .speed = SPEED_100000,
3027 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
3028 .mask_ethtool = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
3029 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
3030 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_2X,
3031 .speed = SPEED_100000,
3034 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
3035 .mask_ethtool = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
3036 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
3037 .mask_width = MLXSW_SP_PORT_MASK_WIDTH_4X,
3038 .speed = SPEED_200000,
3042 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
3045 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
3047 struct ethtool_link_ksettings *cmd)
3049 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
3050 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
3054 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3055 unsigned long *mode)
3059 for (i = 0; i < link_mode->m_ethtool_len; i++)
3060 __set_bit(link_mode->mask_ethtool[i], mode);
3064 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
3065 u8 width, unsigned long *mode)
3067 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3070 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3071 if ((ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) &&
3072 (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3073 mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3079 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
3083 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3084 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
3085 return mlxsw_sp2_port_link_mode[i].speed;
3088 return SPEED_UNKNOWN;
3092 mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
3094 struct ethtool_link_ksettings *cmd)
3096 cmd->base.speed = SPEED_UNKNOWN;
3097 cmd->base.duplex = DUPLEX_UNKNOWN;
3102 cmd->base.speed = mlxsw_sp2_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
3103 if (cmd->base.speed != SPEED_UNKNOWN)
3104 cmd->base.duplex = DUPLEX_FULL;
3108 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3109 const unsigned long *mode)
3114 for (i = 0; i < link_mode->m_ethtool_len; i++) {
3115 if (test_bit(link_mode->mask_ethtool[i], mode))
3119 return cnt == link_mode->m_ethtool_len;
3123 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
3124 const struct ethtool_link_ksettings *cmd)
3126 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3130 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3131 if ((mask_width & mlxsw_sp2_port_link_mode[i].mask_width) &&
3132 mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3133 cmd->link_modes.advertising))
3134 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3139 static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp,
3140 u8 width, u32 speed)
3142 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3146 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3147 if ((speed == mlxsw_sp2_port_link_mode[i].speed) &&
3148 (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3149 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3155 mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
3160 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3161 if (mlxsw_sp2_port_link_mode[i].speed <= upper_speed)
3162 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3168 mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3171 char ptys_pl[MLXSW_REG_PTYS_LEN];
3175 /* In Spectrum-2, the speed of 1x can change from port to port, so query
3178 mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false);
3179 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3182 mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL);
3185 MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) {
3186 *base_speed = MLXSW_SP_PORT_BASE_SPEED_50G;
3191 MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) {
3192 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
3200 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
3201 u8 local_port, u32 proto_admin,
3204 mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
3208 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
3209 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
3210 u32 *p_eth_proto_oper)
3212 mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
3213 p_eth_proto_admin, p_eth_proto_oper);
3216 static const struct mlxsw_sp_port_type_speed_ops
3217 mlxsw_sp2_port_type_speed_ops = {
3218 .from_ptys_supported_port = mlxsw_sp2_from_ptys_supported_port,
3219 .from_ptys_link = mlxsw_sp2_from_ptys_link,
3220 .from_ptys_speed = mlxsw_sp2_from_ptys_speed,
3221 .from_ptys_speed_duplex = mlxsw_sp2_from_ptys_speed_duplex,
3222 .to_ptys_advert_link = mlxsw_sp2_to_ptys_advert_link,
3223 .to_ptys_speed = mlxsw_sp2_to_ptys_speed,
3224 .to_ptys_upper_speed = mlxsw_sp2_to_ptys_upper_speed,
3225 .port_speed_base = mlxsw_sp2_port_speed_base,
3226 .reg_ptys_eth_pack = mlxsw_sp2_reg_ptys_eth_pack,
3227 .reg_ptys_eth_unpack = mlxsw_sp2_reg_ptys_eth_unpack,
3231 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
3232 u8 width, struct ethtool_link_ksettings *cmd)
3234 const struct mlxsw_sp_port_type_speed_ops *ops;
3236 ops = mlxsw_sp->port_type_speed_ops;
3238 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
3239 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
3240 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
3242 ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
3243 ops->from_ptys_link(mlxsw_sp, eth_proto_cap, width,
3244 cmd->link_modes.supported);
3248 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
3249 u32 eth_proto_admin, bool autoneg, u8 width,
3250 struct ethtool_link_ksettings *cmd)
3252 const struct mlxsw_sp_port_type_speed_ops *ops;
3254 ops = mlxsw_sp->port_type_speed_ops;
3259 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
3260 ops->from_ptys_link(mlxsw_sp, eth_proto_admin, width,
3261 cmd->link_modes.advertising);
3265 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
3267 switch (connector_type) {
3268 case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
3270 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
3272 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
3274 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
3276 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
3278 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
3280 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
3282 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
3284 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
3292 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
3293 struct ethtool_link_ksettings *cmd)
3295 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
3296 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3297 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3298 const struct mlxsw_sp_port_type_speed_ops *ops;
3299 char ptys_pl[MLXSW_REG_PTYS_LEN];
3304 ops = mlxsw_sp->port_type_speed_ops;
3306 autoneg = mlxsw_sp_port->link.autoneg;
3307 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3309 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3312 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap,
3313 ð_proto_admin, ð_proto_oper);
3315 mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap,
3316 mlxsw_sp_port->mapping.width, cmd);
3318 mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg,
3319 mlxsw_sp_port->mapping.width, cmd);
3321 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3322 connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
3323 cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
3324 ops->from_ptys_speed_duplex(mlxsw_sp, netif_carrier_ok(dev),
3325 eth_proto_oper, cmd);
3331 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
3332 const struct ethtool_link_ksettings *cmd)
3334 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3335 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3336 const struct mlxsw_sp_port_type_speed_ops *ops;
3337 char ptys_pl[MLXSW_REG_PTYS_LEN];
3338 u32 eth_proto_cap, eth_proto_new;
3342 ops = mlxsw_sp->port_type_speed_ops;
3344 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3346 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3349 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, NULL, NULL);
3351 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
3352 eth_proto_new = autoneg ?
3353 ops->to_ptys_advert_link(mlxsw_sp, mlxsw_sp_port->mapping.width,
3355 ops->to_ptys_speed(mlxsw_sp, mlxsw_sp_port->mapping.width,
3358 eth_proto_new = eth_proto_new & eth_proto_cap;
3359 if (!eth_proto_new) {
3360 netdev_err(dev, "No supported speed requested\n");
3364 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3365 eth_proto_new, autoneg);
3366 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3370 mlxsw_sp_port->link.autoneg = autoneg;
3372 if (!netif_running(dev))
3375 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3376 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
3381 static int mlxsw_sp_get_module_info(struct net_device *netdev,
3382 struct ethtool_modinfo *modinfo)
3384 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3385 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3388 err = mlxsw_env_get_module_info(mlxsw_sp->core,
3389 mlxsw_sp_port->mapping.module,
3395 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
3396 struct ethtool_eeprom *ee,
3399 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3400 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3403 err = mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core,
3404 mlxsw_sp_port->mapping.module, ee,
3411 mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
3413 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3414 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3416 return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
3419 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
3420 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
3421 .get_link = ethtool_op_get_link,
3422 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
3423 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
3424 .get_strings = mlxsw_sp_port_get_strings,
3425 .set_phys_id = mlxsw_sp_port_set_phys_id,
3426 .get_ethtool_stats = mlxsw_sp_port_get_stats,
3427 .get_sset_count = mlxsw_sp_port_get_sset_count,
3428 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
3429 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
3430 .get_module_info = mlxsw_sp_get_module_info,
3431 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
3432 .get_ts_info = mlxsw_sp_get_ts_info,
3436 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
3438 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3439 const struct mlxsw_sp_port_type_speed_ops *ops;
3440 char ptys_pl[MLXSW_REG_PTYS_LEN];
3441 u32 eth_proto_admin;
3446 ops = mlxsw_sp->port_type_speed_ops;
3448 err = ops->port_speed_base(mlxsw_sp, mlxsw_sp_port->local_port,
3452 upper_speed = base_speed * width;
3454 eth_proto_admin = ops->to_ptys_upper_speed(mlxsw_sp, upper_speed);
3455 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3456 eth_proto_admin, mlxsw_sp_port->link.autoneg);
3457 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3460 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
3461 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
3462 bool dwrr, u8 dwrr_weight)
3464 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3465 char qeec_pl[MLXSW_REG_QEEC_LEN];
3467 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3469 mlxsw_reg_qeec_de_set(qeec_pl, true);
3470 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
3471 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
3472 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3475 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
3476 enum mlxsw_reg_qeec_hr hr, u8 index,
3477 u8 next_index, u32 maxrate)
3479 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3480 char qeec_pl[MLXSW_REG_QEEC_LEN];
3482 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3484 mlxsw_reg_qeec_mase_set(qeec_pl, true);
3485 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3486 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3489 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
3490 enum mlxsw_reg_qeec_hr hr, u8 index,
3491 u8 next_index, u32 minrate)
3493 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3494 char qeec_pl[MLXSW_REG_QEEC_LEN];
3496 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3498 mlxsw_reg_qeec_mise_set(qeec_pl, true);
3499 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
3501 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3504 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3505 u8 switch_prio, u8 tclass)
3507 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3508 char qtct_pl[MLXSW_REG_QTCT_LEN];
3510 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3512 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3515 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3519 /* Setup the elements hierarcy, so that each TC is linked to
3520 * one subgroup, which are all member in the same group.
3522 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3523 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3527 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3528 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3529 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3534 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3535 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3536 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3541 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3542 MLXSW_REG_QEEC_HIERARCY_TC,
3549 /* Make sure the max shaper is disabled in all hierarchies that support
3550 * it. Note that this disables ptps (PTP shaper), but that is intended
3551 * for the initial configuration.
3553 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3554 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3555 MLXSW_REG_QEEC_MAS_DIS);
3558 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3559 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3560 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3562 MLXSW_REG_QEEC_MAS_DIS);
3566 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3567 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3568 MLXSW_REG_QEEC_HIERARCY_TC,
3570 MLXSW_REG_QEEC_MAS_DIS);
3574 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3575 MLXSW_REG_QEEC_HIERARCY_TC,
3577 MLXSW_REG_QEEC_MAS_DIS);
3582 /* Configure the min shaper for multicast TCs. */
3583 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3584 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
3585 MLXSW_REG_QEEC_HIERARCY_TC,
3587 MLXSW_REG_QEEC_MIS_MIN);
3592 /* Map all priorities to traffic class 0. */
3593 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3594 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3602 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
3605 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3606 char qtctm_pl[MLXSW_REG_QTCTM_LEN];
3608 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
3609 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
3612 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3613 bool split, u8 module, u8 width, u8 lane)
3615 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
3616 struct mlxsw_sp_port *mlxsw_sp_port;
3617 struct net_device *dev;
3620 err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
3621 module + 1, split, lane / width,
3623 sizeof(mlxsw_sp->base_mac));
3625 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3630 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
3633 goto err_alloc_etherdev;
3635 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
3636 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
3637 mlxsw_sp_port = netdev_priv(dev);
3638 mlxsw_sp_port->dev = dev;
3639 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3640 mlxsw_sp_port->local_port = local_port;
3641 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
3642 mlxsw_sp_port->split = split;
3643 mlxsw_sp_port->mapping.module = module;
3644 mlxsw_sp_port->mapping.width = width;
3645 mlxsw_sp_port->mapping.lane = lane;
3646 mlxsw_sp_port->link.autoneg = 1;
3647 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
3648 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
3650 mlxsw_sp_port->pcpu_stats =
3651 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3652 if (!mlxsw_sp_port->pcpu_stats) {
3654 goto err_alloc_stats;
3657 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3659 if (!mlxsw_sp_port->sample) {
3661 goto err_alloc_sample;
3664 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
3665 &update_stats_cache);
3667 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3668 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3670 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
3672 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3673 mlxsw_sp_port->local_port);
3674 goto err_port_module_map;
3677 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3679 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3680 mlxsw_sp_port->local_port);
3681 goto err_port_swid_set;
3684 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3686 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3687 mlxsw_sp_port->local_port);
3688 goto err_dev_addr_init;
3691 netif_carrier_off(dev);
3693 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
3694 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3695 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
3698 dev->max_mtu = ETH_MAX_MTU;
3700 /* Each packet needs to have a Tx header (metadata) on top all other
3703 dev->needed_headroom = MLXSW_TXHDR_LEN;
3705 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3707 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3708 mlxsw_sp_port->local_port);
3709 goto err_port_system_port_mapping_set;
3712 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3714 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3715 mlxsw_sp_port->local_port);
3716 goto err_port_speed_by_width_set;
3719 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3721 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3722 mlxsw_sp_port->local_port);
3723 goto err_port_mtu_set;
3726 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3728 goto err_port_admin_status_set;
3730 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3732 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3733 mlxsw_sp_port->local_port);
3734 goto err_port_buffers_init;
3737 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3739 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3740 mlxsw_sp_port->local_port);
3741 goto err_port_ets_init;
3744 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3746 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3747 mlxsw_sp_port->local_port);
3748 goto err_port_tc_mc_mode;
3751 /* ETS and buffers must be initialized before DCB. */
3752 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3754 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3755 mlxsw_sp_port->local_port);
3756 goto err_port_dcb_init;
3759 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3761 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3762 mlxsw_sp_port->local_port);
3763 goto err_port_fids_init;
3766 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3768 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3769 mlxsw_sp_port->local_port);
3770 goto err_port_qdiscs_init;
3773 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
3776 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
3777 mlxsw_sp_port->local_port);
3778 goto err_port_vlan_clear;
3781 err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3783 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3784 mlxsw_sp_port->local_port);
3785 goto err_port_nve_init;
3788 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3790 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
3791 mlxsw_sp_port->local_port);
3792 goto err_port_pvid_set;
3795 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
3796 MLXSW_SP_DEFAULT_VID);
3797 if (IS_ERR(mlxsw_sp_port_vlan)) {
3798 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3799 mlxsw_sp_port->local_port);
3800 err = PTR_ERR(mlxsw_sp_port_vlan);
3801 goto err_port_vlan_create;
3803 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
3805 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
3806 mlxsw_sp->ptp_ops->shaper_work);
3808 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3809 err = register_netdev(dev);
3811 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3812 mlxsw_sp_port->local_port);
3813 goto err_register_netdev;
3816 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3817 mlxsw_sp_port, dev);
3818 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3821 err_register_netdev:
3822 mlxsw_sp->ports[local_port] = NULL;
3823 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
3824 err_port_vlan_create:
3826 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3828 err_port_vlan_clear:
3829 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3830 err_port_qdiscs_init:
3831 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3833 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3835 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3836 err_port_tc_mc_mode:
3838 err_port_buffers_init:
3839 err_port_admin_status_set:
3841 err_port_speed_by_width_set:
3842 err_port_system_port_mapping_set:
3844 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3846 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3847 err_port_module_map:
3848 kfree(mlxsw_sp_port->sample);
3850 free_percpu(mlxsw_sp_port->pcpu_stats);
3854 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3858 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3860 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3862 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3863 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
3864 mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
3865 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3866 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3867 mlxsw_sp->ports[local_port] = NULL;
3868 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
3869 mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3870 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3871 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3872 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3873 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3874 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3875 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3876 kfree(mlxsw_sp_port->sample);
3877 free_percpu(mlxsw_sp_port->pcpu_stats);
3878 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3879 free_netdev(mlxsw_sp_port->dev);
3880 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3883 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
3885 struct mlxsw_sp_port *mlxsw_sp_port;
3888 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
3892 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3893 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
3895 err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
3898 sizeof(mlxsw_sp->base_mac));
3900 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
3901 goto err_core_cpu_port_init;
3904 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
3907 err_core_cpu_port_init:
3908 kfree(mlxsw_sp_port);
3912 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
3914 struct mlxsw_sp_port *mlxsw_sp_port =
3915 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
3917 mlxsw_core_cpu_port_fini(mlxsw_sp->core);
3918 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
3919 kfree(mlxsw_sp_port);
3922 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3924 return mlxsw_sp->ports[local_port] != NULL;
3927 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3931 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3932 if (mlxsw_sp_port_created(mlxsw_sp, i))
3933 mlxsw_sp_port_remove(mlxsw_sp, i);
3934 mlxsw_sp_cpu_port_remove(mlxsw_sp);
3935 kfree(mlxsw_sp->port_to_module);
3936 kfree(mlxsw_sp->ports);
3939 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3941 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3942 u8 module, width, lane;
3947 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3948 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3949 if (!mlxsw_sp->ports)
3952 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3954 if (!mlxsw_sp->port_to_module) {
3956 goto err_port_to_module_alloc;
3959 err = mlxsw_sp_cpu_port_create(mlxsw_sp);
3961 goto err_cpu_port_create;
3963 for (i = 1; i < max_ports; i++) {
3964 /* Mark as invalid */
3965 mlxsw_sp->port_to_module[i] = -1;
3967 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3970 goto err_port_module_info_get;
3973 mlxsw_sp->port_to_module[i] = module;
3974 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3975 module, width, lane);
3977 goto err_port_create;
3982 err_port_module_info_get:
3983 for (i--; i >= 1; i--)
3984 if (mlxsw_sp_port_created(mlxsw_sp, i))
3985 mlxsw_sp_port_remove(mlxsw_sp, i);
3986 mlxsw_sp_cpu_port_remove(mlxsw_sp);
3987 err_cpu_port_create:
3988 kfree(mlxsw_sp->port_to_module);
3989 err_port_to_module_alloc:
3990 kfree(mlxsw_sp->ports);
3994 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3996 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3998 return local_port - offset;
4001 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
4002 u8 module, unsigned int count, u8 offset)
4004 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
4007 for (i = 0; i < count; i++) {
4008 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
4009 true, module, width, i * width);
4011 goto err_port_create;
4017 for (i--; i >= 0; i--)
4018 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4019 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4023 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
4024 u8 base_port, unsigned int count)
4026 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
4029 /* Split by four means we need to re-create two ports, otherwise
4034 for (i = 0; i < count; i++) {
4035 local_port = base_port + i * 2;
4036 if (mlxsw_sp->port_to_module[local_port] < 0)
4038 module = mlxsw_sp->port_to_module[local_port];
4040 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
4045 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
4047 struct netlink_ext_ack *extack)
4049 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4050 u8 local_ports_in_1x, local_ports_in_2x, offset;
4051 struct mlxsw_sp_port *mlxsw_sp_port;
4052 u8 module, cur_width, base_port;
4056 if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4057 !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4060 local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4061 local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4063 mlxsw_sp_port = mlxsw_sp->ports[local_port];
4064 if (!mlxsw_sp_port) {
4065 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4067 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4071 module = mlxsw_sp_port->mapping.module;
4072 cur_width = mlxsw_sp_port->mapping.width;
4074 if (count != 2 && count != 4) {
4075 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
4076 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
4080 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
4081 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
4082 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
4086 /* Make sure we have enough slave (even) ports for the split. */
4088 offset = local_ports_in_2x;
4089 base_port = local_port;
4090 if (mlxsw_sp->ports[base_port + local_ports_in_2x]) {
4091 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4092 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4096 offset = local_ports_in_1x;
4097 base_port = mlxsw_sp_cluster_base_port_get(local_port);
4098 if (mlxsw_sp->ports[base_port + 1] ||
4099 mlxsw_sp->ports[base_port + 3]) {
4100 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4101 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4106 for (i = 0; i < count; i++)
4107 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4108 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4110 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count,
4113 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
4114 goto err_port_split_create;
4119 err_port_split_create:
4120 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4124 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
4125 struct netlink_ext_ack *extack)
4127 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4128 u8 local_ports_in_1x, local_ports_in_2x, offset;
4129 struct mlxsw_sp_port *mlxsw_sp_port;
4130 u8 cur_width, base_port;
4134 if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4135 !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4138 local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4139 local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4141 mlxsw_sp_port = mlxsw_sp->ports[local_port];
4142 if (!mlxsw_sp_port) {
4143 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4145 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4149 if (!mlxsw_sp_port->split) {
4150 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
4151 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
4155 cur_width = mlxsw_sp_port->mapping.width;
4156 count = cur_width == 1 ? 4 : 2;
4159 offset = local_ports_in_2x;
4161 offset = local_ports_in_1x;
4163 base_port = mlxsw_sp_cluster_base_port_get(local_port);
4165 /* Determine which ports to remove. */
4166 if (count == 2 && local_port >= base_port + 2)
4167 base_port = base_port + 2;
4169 for (i = 0; i < count; i++)
4170 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4171 mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4173 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4178 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
4179 char *pude_pl, void *priv)
4181 struct mlxsw_sp *mlxsw_sp = priv;
4182 struct mlxsw_sp_port *mlxsw_sp_port;
4183 enum mlxsw_reg_pude_oper_status status;
4186 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
4187 mlxsw_sp_port = mlxsw_sp->ports[local_port];
4191 status = mlxsw_reg_pude_oper_status_get(pude_pl);
4192 if (status == MLXSW_PORT_OPER_STATUS_UP) {
4193 netdev_info(mlxsw_sp_port->dev, "link up\n");
4194 netif_carrier_on(mlxsw_sp_port->dev);
4195 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
4197 netdev_info(mlxsw_sp_port->dev, "link down\n");
4198 netif_carrier_off(mlxsw_sp_port->dev);
4202 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
4203 char *mtpptr_pl, bool ingress)
4209 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
4210 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
4211 for (i = 0; i < num_rec; i++) {
4217 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
4218 &domain_number, &sequence_id,
4220 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
4221 message_type, domain_number,
4222 sequence_id, timestamp);
4226 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
4227 char *mtpptr_pl, void *priv)
4229 struct mlxsw_sp *mlxsw_sp = priv;
4231 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
4234 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
4235 char *mtpptr_pl, void *priv)
4237 struct mlxsw_sp *mlxsw_sp = priv;
4239 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
4242 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
4243 u8 local_port, void *priv)
4245 struct mlxsw_sp *mlxsw_sp = priv;
4246 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4247 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
4249 if (unlikely(!mlxsw_sp_port)) {
4250 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
4255 skb->dev = mlxsw_sp_port->dev;
4257 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
4258 u64_stats_update_begin(&pcpu_stats->syncp);
4259 pcpu_stats->rx_packets++;
4260 pcpu_stats->rx_bytes += skb->len;
4261 u64_stats_update_end(&pcpu_stats->syncp);
4263 skb->protocol = eth_type_trans(skb, skb->dev);
4264 netif_receive_skb(skb);
4267 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
4270 skb->offload_fwd_mark = 1;
4271 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4274 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
4275 u8 local_port, void *priv)
4277 skb->offload_l3_fwd_mark = 1;
4278 skb->offload_fwd_mark = 1;
4279 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4282 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
4285 struct mlxsw_sp *mlxsw_sp = priv;
4286 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4287 struct psample_group *psample_group;
4290 if (unlikely(!mlxsw_sp_port)) {
4291 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
4295 if (unlikely(!mlxsw_sp_port->sample)) {
4296 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
4301 size = mlxsw_sp_port->sample->truncate ?
4302 mlxsw_sp_port->sample->trunc_size : skb->len;
4305 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
4308 psample_sample_packet(psample_group, skb, size,
4309 mlxsw_sp_port->dev->ifindex, 0,
4310 mlxsw_sp_port->sample->rate);
4317 static void mlxsw_sp_rx_listener_ptp(struct sk_buff *skb, u8 local_port,
4320 struct mlxsw_sp *mlxsw_sp = priv;
4322 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
4325 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4326 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
4327 _is_ctrl, SP_##_trap_group, DISCARD)
4329 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4330 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
4331 _is_ctrl, SP_##_trap_group, DISCARD)
4333 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
4334 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
4335 _is_ctrl, SP_##_trap_group, DISCARD)
4337 #define MLXSW_SP_EVENTL(_func, _trap_id) \
4338 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
4340 static const struct mlxsw_listener mlxsw_sp_listener[] = {
4342 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
4344 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
4345 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
4346 MLXSW_RXL(mlxsw_sp_rx_listener_ptp, LLDP, TRAP_TO_CPU,
4347 false, SP_LLDP, DISCARD),
4348 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
4349 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
4350 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
4351 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
4352 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
4353 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
4354 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
4355 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
4356 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
4357 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
4359 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4361 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
4363 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4366 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4367 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4368 MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false),
4369 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
4370 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
4372 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
4373 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
4374 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
4375 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
4377 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
4378 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
4379 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
4380 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
4381 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
4382 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
4383 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4385 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4387 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4389 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4391 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
4392 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
4394 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
4395 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
4396 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
4397 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
4398 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4399 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
4400 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
4401 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
4402 /* PKT Sample trap */
4403 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
4404 false, SP_IP2ME, DISCARD),
4406 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
4407 /* Multicast Router Traps */
4408 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
4409 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
4410 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
4411 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
4412 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
4414 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
4415 MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false),
4417 MLXSW_RXL(mlxsw_sp_rx_listener_ptp, PTP0, TRAP_TO_CPU,
4418 false, SP_PTP0, DISCARD),
4419 MLXSW_SP_RXL_NO_MARK(PTP1, TRAP_TO_CPU, PTP1, false),
4422 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
4424 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
4425 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
4428 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
4430 char qpcr_pl[MLXSW_REG_QPCR_LEN];
4431 enum mlxsw_reg_qpcr_ir_units ir_units;
4432 int max_cpu_policers;
4438 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
4441 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4443 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
4444 for (i = 0; i < max_cpu_policers; i++) {
4447 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4448 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4449 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4450 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4451 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4452 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4453 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4457 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4458 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4462 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4463 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4464 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4465 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4466 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4467 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4468 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4469 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4473 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4477 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4481 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4489 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
4491 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
4499 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
4501 char htgt_pl[MLXSW_REG_HTGT_LEN];
4502 enum mlxsw_reg_htgt_trap_group i;
4503 int max_cpu_policers;
4504 int max_trap_groups;
4509 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
4512 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
4513 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4515 for (i = 0; i < max_trap_groups; i++) {
4518 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4519 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4520 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4521 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4522 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4523 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4527 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4528 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4532 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4533 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4534 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4538 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4539 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4540 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4541 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4545 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4546 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4547 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4548 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4549 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4553 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
4554 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
4555 tc = MLXSW_REG_HTGT_DEFAULT_TC;
4556 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
4562 if (max_cpu_policers <= policer_id &&
4563 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
4566 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
4567 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4575 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
4576 const struct mlxsw_listener listeners[],
4577 size_t listeners_count)
4582 for (i = 0; i < listeners_count; i++) {
4583 err = mlxsw_core_trap_register(mlxsw_sp->core,
4587 goto err_listener_register;
4592 err_listener_register:
4593 for (i--; i >= 0; i--) {
4594 mlxsw_core_trap_unregister(mlxsw_sp->core,
4601 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
4602 const struct mlxsw_listener listeners[],
4603 size_t listeners_count)
4607 for (i = 0; i < listeners_count; i++) {
4608 mlxsw_core_trap_unregister(mlxsw_sp->core,
4614 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
4618 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
4622 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
4626 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
4627 ARRAY_SIZE(mlxsw_sp_listener));
4631 err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
4632 mlxsw_sp->listeners_count);
4634 goto err_extra_traps_init;
4638 err_extra_traps_init:
4639 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4640 ARRAY_SIZE(mlxsw_sp_listener));
4644 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
4646 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
4647 mlxsw_sp->listeners_count);
4648 mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4649 ARRAY_SIZE(mlxsw_sp_listener));
4652 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
4654 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
4656 char slcr_pl[MLXSW_REG_SLCR_LEN];
4660 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
4661 MLXSW_SP_LAG_SEED_INIT);
4662 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
4663 MLXSW_REG_SLCR_LAG_HASH_DMAC |
4664 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
4665 MLXSW_REG_SLCR_LAG_HASH_VLANID |
4666 MLXSW_REG_SLCR_LAG_HASH_SIP |
4667 MLXSW_REG_SLCR_LAG_HASH_DIP |
4668 MLXSW_REG_SLCR_LAG_HASH_SPORT |
4669 MLXSW_REG_SLCR_LAG_HASH_DPORT |
4670 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
4671 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
4675 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
4676 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
4679 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
4680 sizeof(struct mlxsw_sp_upper),
4682 if (!mlxsw_sp->lags)
4688 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
4690 kfree(mlxsw_sp->lags);
4693 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
4695 char htgt_pl[MLXSW_REG_HTGT_LEN];
4697 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4698 MLXSW_REG_HTGT_INVALID_POLICER,
4699 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
4700 MLXSW_REG_HTGT_DEFAULT_TC);
4701 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4704 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
4705 .clock_init = mlxsw_sp1_ptp_clock_init,
4706 .clock_fini = mlxsw_sp1_ptp_clock_fini,
4707 .init = mlxsw_sp1_ptp_init,
4708 .fini = mlxsw_sp1_ptp_fini,
4709 .receive = mlxsw_sp1_ptp_receive,
4710 .transmitted = mlxsw_sp1_ptp_transmitted,
4711 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get,
4712 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set,
4713 .shaper_work = mlxsw_sp1_ptp_shaper_work,
4714 .get_ts_info = mlxsw_sp1_ptp_get_ts_info,
4715 .get_stats_count = mlxsw_sp1_get_stats_count,
4716 .get_stats_strings = mlxsw_sp1_get_stats_strings,
4717 .get_stats = mlxsw_sp1_get_stats,
4720 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
4721 .clock_init = mlxsw_sp2_ptp_clock_init,
4722 .clock_fini = mlxsw_sp2_ptp_clock_fini,
4723 .init = mlxsw_sp2_ptp_init,
4724 .fini = mlxsw_sp2_ptp_fini,
4725 .receive = mlxsw_sp2_ptp_receive,
4726 .transmitted = mlxsw_sp2_ptp_transmitted,
4727 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get,
4728 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set,
4729 .shaper_work = mlxsw_sp2_ptp_shaper_work,
4730 .get_ts_info = mlxsw_sp2_ptp_get_ts_info,
4731 .get_stats_count = mlxsw_sp2_get_stats_count,
4732 .get_stats_strings = mlxsw_sp2_get_stats_strings,
4733 .get_stats = mlxsw_sp2_get_stats,
4736 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4737 unsigned long event, void *ptr);
4739 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
4740 const struct mlxsw_bus_info *mlxsw_bus_info,
4741 struct netlink_ext_ack *extack)
4743 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4746 mlxsw_sp->core = mlxsw_core;
4747 mlxsw_sp->bus_info = mlxsw_bus_info;
4749 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
4753 err = mlxsw_sp_base_mac_get(mlxsw_sp);
4755 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
4759 err = mlxsw_sp_kvdl_init(mlxsw_sp);
4761 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
4765 err = mlxsw_sp_fids_init(mlxsw_sp);
4767 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
4771 err = mlxsw_sp_traps_init(mlxsw_sp);
4773 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
4774 goto err_traps_init;
4777 err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
4779 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
4780 goto err_devlink_traps_init;
4783 err = mlxsw_sp_buffers_init(mlxsw_sp);
4785 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
4786 goto err_buffers_init;
4789 err = mlxsw_sp_lag_init(mlxsw_sp);
4791 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
4795 /* Initialize SPAN before router and switchdev, so that those components
4796 * can call mlxsw_sp_span_respin().
4798 err = mlxsw_sp_span_init(mlxsw_sp);
4800 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4804 err = mlxsw_sp_switchdev_init(mlxsw_sp);
4806 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
4807 goto err_switchdev_init;
4810 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
4812 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
4813 goto err_counter_pool_init;
4816 err = mlxsw_sp_afa_init(mlxsw_sp);
4818 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
4822 err = mlxsw_sp_nve_init(mlxsw_sp);
4824 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
4828 err = mlxsw_sp_acl_init(mlxsw_sp);
4830 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4834 err = mlxsw_sp_router_init(mlxsw_sp, extack);
4836 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4837 goto err_router_init;
4840 if (mlxsw_sp->bus_info->read_frc_capable) {
4841 /* NULL is a valid return value from clock_init */
4843 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
4844 mlxsw_sp->bus_info->dev);
4845 if (IS_ERR(mlxsw_sp->clock)) {
4846 err = PTR_ERR(mlxsw_sp->clock);
4847 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
4848 goto err_ptp_clock_init;
4852 if (mlxsw_sp->clock) {
4853 /* NULL is a valid return value from ptp_ops->init */
4854 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
4855 if (IS_ERR(mlxsw_sp->ptp_state)) {
4856 err = PTR_ERR(mlxsw_sp->ptp_state);
4857 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
4862 /* Initialize netdevice notifier after router and SPAN is initialized,
4863 * so that the event handler can use router structures and call SPAN
4866 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4867 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
4868 &mlxsw_sp->netdevice_nb);
4870 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4871 goto err_netdev_notifier;
4874 err = mlxsw_sp_dpipe_init(mlxsw_sp);
4876 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4877 goto err_dpipe_init;
4880 err = mlxsw_sp_ports_create(mlxsw_sp);
4882 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4883 goto err_ports_create;
4889 mlxsw_sp_dpipe_fini(mlxsw_sp);
4891 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
4892 &mlxsw_sp->netdevice_nb);
4893 err_netdev_notifier:
4894 if (mlxsw_sp->clock)
4895 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4897 if (mlxsw_sp->clock)
4898 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
4900 mlxsw_sp_router_fini(mlxsw_sp);
4902 mlxsw_sp_acl_fini(mlxsw_sp);
4904 mlxsw_sp_nve_fini(mlxsw_sp);
4906 mlxsw_sp_afa_fini(mlxsw_sp);
4908 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4909 err_counter_pool_init:
4910 mlxsw_sp_switchdev_fini(mlxsw_sp);
4912 mlxsw_sp_span_fini(mlxsw_sp);
4914 mlxsw_sp_lag_fini(mlxsw_sp);
4916 mlxsw_sp_buffers_fini(mlxsw_sp);
4918 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
4919 err_devlink_traps_init:
4920 mlxsw_sp_traps_fini(mlxsw_sp);
4922 mlxsw_sp_fids_fini(mlxsw_sp);
4924 mlxsw_sp_kvdl_fini(mlxsw_sp);
4928 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
4929 const struct mlxsw_bus_info *mlxsw_bus_info,
4930 struct netlink_ext_ack *extack)
4932 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4934 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
4935 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
4936 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
4937 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
4938 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
4939 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
4940 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
4941 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
4942 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
4943 mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr;
4944 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
4945 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
4946 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
4947 mlxsw_sp->listeners = mlxsw_sp1_listener;
4948 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
4950 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
4953 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
4954 const struct mlxsw_bus_info *mlxsw_bus_info,
4955 struct netlink_ext_ack *extack)
4957 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4959 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
4960 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
4961 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
4962 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
4963 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
4964 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
4965 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
4966 mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
4967 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
4968 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
4969 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
4971 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
4974 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
4976 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4978 mlxsw_sp_ports_remove(mlxsw_sp);
4979 mlxsw_sp_dpipe_fini(mlxsw_sp);
4980 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
4981 &mlxsw_sp->netdevice_nb);
4982 if (mlxsw_sp->clock) {
4983 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4984 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
4986 mlxsw_sp_router_fini(mlxsw_sp);
4987 mlxsw_sp_acl_fini(mlxsw_sp);
4988 mlxsw_sp_nve_fini(mlxsw_sp);
4989 mlxsw_sp_afa_fini(mlxsw_sp);
4990 mlxsw_sp_counter_pool_fini(mlxsw_sp);
4991 mlxsw_sp_switchdev_fini(mlxsw_sp);
4992 mlxsw_sp_span_fini(mlxsw_sp);
4993 mlxsw_sp_lag_fini(mlxsw_sp);
4994 mlxsw_sp_buffers_fini(mlxsw_sp);
4995 mlxsw_sp_devlink_traps_fini(mlxsw_sp);
4996 mlxsw_sp_traps_fini(mlxsw_sp);
4997 mlxsw_sp_fids_fini(mlxsw_sp);
4998 mlxsw_sp_kvdl_fini(mlxsw_sp);
5001 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
5004 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE (MLXSW_SP_FID_8021D_MAX + \
5007 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
5009 .max_mid = MLXSW_SP_MID_MAX,
5010 .used_flood_tables = 1,
5011 .used_flood_mode = 1,
5013 .max_fid_flood_tables = 3,
5014 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5015 .used_max_ib_mc = 1,
5019 .used_kvd_sizes = 1,
5020 .kvd_hash_single_parts = 59,
5021 .kvd_hash_double_parts = 41,
5022 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
5026 .type = MLXSW_PORT_SWID_TYPE_ETH,
5031 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
5033 .max_mid = MLXSW_SP_MID_MAX,
5034 .used_flood_tables = 1,
5035 .used_flood_mode = 1,
5037 .max_fid_flood_tables = 3,
5038 .fid_flood_table_size = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5039 .used_max_ib_mc = 1,
5046 .type = MLXSW_PORT_SWID_TYPE_ETH,
5052 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
5053 struct devlink_resource_size_params *kvd_size_params,
5054 struct devlink_resource_size_params *linear_size_params,
5055 struct devlink_resource_size_params *hash_double_size_params,
5056 struct devlink_resource_size_params *hash_single_size_params)
5058 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5059 KVD_SINGLE_MIN_SIZE);
5060 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5061 KVD_DOUBLE_MIN_SIZE);
5062 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5063 u32 linear_size_min = 0;
5065 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
5066 MLXSW_SP_KVD_GRANULARITY,
5067 DEVLINK_RESOURCE_UNIT_ENTRY);
5068 devlink_resource_size_params_init(linear_size_params, linear_size_min,
5069 kvd_size - single_size_min -
5071 MLXSW_SP_KVD_GRANULARITY,
5072 DEVLINK_RESOURCE_UNIT_ENTRY);
5073 devlink_resource_size_params_init(hash_double_size_params,
5075 kvd_size - single_size_min -
5077 MLXSW_SP_KVD_GRANULARITY,
5078 DEVLINK_RESOURCE_UNIT_ENTRY);
5079 devlink_resource_size_params_init(hash_single_size_params,
5081 kvd_size - double_size_min -
5083 MLXSW_SP_KVD_GRANULARITY,
5084 DEVLINK_RESOURCE_UNIT_ENTRY);
5087 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5089 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5090 struct devlink_resource_size_params hash_single_size_params;
5091 struct devlink_resource_size_params hash_double_size_params;
5092 struct devlink_resource_size_params linear_size_params;
5093 struct devlink_resource_size_params kvd_size_params;
5094 u32 kvd_size, single_size, double_size, linear_size;
5095 const struct mlxsw_config_profile *profile;
5098 profile = &mlxsw_sp1_config_profile;
5099 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5102 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
5103 &linear_size_params,
5104 &hash_double_size_params,
5105 &hash_single_size_params);
5107 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5108 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5109 kvd_size, MLXSW_SP_RESOURCE_KVD,
5110 DEVLINK_RESOURCE_ID_PARENT_TOP,
5115 linear_size = profile->kvd_linear_size;
5116 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
5118 MLXSW_SP_RESOURCE_KVD_LINEAR,
5119 MLXSW_SP_RESOURCE_KVD,
5120 &linear_size_params);
5124 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
5128 double_size = kvd_size - linear_size;
5129 double_size *= profile->kvd_hash_double_parts;
5130 double_size /= profile->kvd_hash_double_parts +
5131 profile->kvd_hash_single_parts;
5132 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
5133 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
5135 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5136 MLXSW_SP_RESOURCE_KVD,
5137 &hash_double_size_params);
5141 single_size = kvd_size - double_size - linear_size;
5142 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
5144 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5145 MLXSW_SP_RESOURCE_KVD,
5146 &hash_single_size_params);
5153 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5155 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5156 struct devlink_resource_size_params kvd_size_params;
5159 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5162 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5163 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
5164 MLXSW_SP_KVD_GRANULARITY,
5165 DEVLINK_RESOURCE_UNIT_ENTRY);
5167 return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5168 kvd_size, MLXSW_SP_RESOURCE_KVD,
5169 DEVLINK_RESOURCE_ID_PARENT_TOP,
5173 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
5175 return mlxsw_sp1_resources_kvd_register(mlxsw_core);
5178 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
5180 return mlxsw_sp2_resources_kvd_register(mlxsw_core);
5183 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
5184 const struct mlxsw_config_profile *profile,
5185 u64 *p_single_size, u64 *p_double_size,
5188 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5192 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5193 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
5196 /* The hash part is what left of the kvd without the
5197 * linear part. It is split to the single size and
5198 * double size by the parts ratio from the profile.
5199 * Both sizes must be a multiplications of the
5200 * granularity from the profile. In case the user
5201 * provided the sizes they are obtained via devlink.
5203 err = devlink_resource_size_get(devlink,
5204 MLXSW_SP_RESOURCE_KVD_LINEAR,
5207 *p_linear_size = profile->kvd_linear_size;
5209 err = devlink_resource_size_get(devlink,
5210 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5213 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5215 double_size *= profile->kvd_hash_double_parts;
5216 double_size /= profile->kvd_hash_double_parts +
5217 profile->kvd_hash_single_parts;
5218 *p_double_size = rounddown(double_size,
5219 MLXSW_SP_KVD_GRANULARITY);
5222 err = devlink_resource_size_get(devlink,
5223 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5226 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5227 *p_double_size - *p_linear_size;
5229 /* Check results are legal. */
5230 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5231 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
5232 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
5239 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
5240 union devlink_param_value val,
5241 struct netlink_ext_ack *extack)
5243 if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) &&
5244 (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) {
5245 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
5252 static const struct devlink_param mlxsw_sp_devlink_params[] = {
5253 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY,
5254 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
5256 mlxsw_sp_devlink_param_fw_load_policy_validate),
5259 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core)
5261 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5262 union devlink_param_value value;
5265 err = devlink_params_register(devlink, mlxsw_sp_devlink_params,
5266 ARRAY_SIZE(mlxsw_sp_devlink_params));
5270 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
5271 devlink_param_driverinit_value_set(devlink,
5272 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
5277 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core)
5279 devlink_params_unregister(priv_to_devlink(mlxsw_core),
5280 mlxsw_sp_devlink_params,
5281 ARRAY_SIZE(mlxsw_sp_devlink_params));
5285 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
5286 struct devlink_param_gset_ctx *ctx)
5288 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5289 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5291 ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
5296 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
5297 struct devlink_param_gset_ctx *ctx)
5299 struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5300 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5302 return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
5305 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
5306 DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5307 "acl_region_rehash_interval",
5308 DEVLINK_PARAM_TYPE_U32,
5309 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
5310 mlxsw_sp_params_acl_region_rehash_intrvl_get,
5311 mlxsw_sp_params_acl_region_rehash_intrvl_set,
5315 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
5317 struct devlink *devlink = priv_to_devlink(mlxsw_core);
5318 union devlink_param_value value;
5321 err = mlxsw_sp_params_register(mlxsw_core);
5325 err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
5326 ARRAY_SIZE(mlxsw_sp2_devlink_params));
5328 goto err_devlink_params_register;
5331 devlink_param_driverinit_value_set(devlink,
5332 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5336 err_devlink_params_register:
5337 mlxsw_sp_params_unregister(mlxsw_core);
5341 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
5343 devlink_params_unregister(priv_to_devlink(mlxsw_core),
5344 mlxsw_sp2_devlink_params,
5345 ARRAY_SIZE(mlxsw_sp2_devlink_params));
5346 mlxsw_sp_params_unregister(mlxsw_core);
5349 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
5350 struct sk_buff *skb, u8 local_port)
5352 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5354 skb_pull(skb, MLXSW_TXHDR_LEN);
5355 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
5358 static struct mlxsw_driver mlxsw_sp1_driver = {
5359 .kind = mlxsw_sp1_driver_name,
5360 .priv_size = sizeof(struct mlxsw_sp),
5361 .init = mlxsw_sp1_init,
5362 .fini = mlxsw_sp_fini,
5363 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5364 .port_split = mlxsw_sp_port_split,
5365 .port_unsplit = mlxsw_sp_port_unsplit,
5366 .sb_pool_get = mlxsw_sp_sb_pool_get,
5367 .sb_pool_set = mlxsw_sp_sb_pool_set,
5368 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5369 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5370 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5371 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5372 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5373 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5374 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5375 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5376 .flash_update = mlxsw_sp_flash_update,
5377 .trap_init = mlxsw_sp_trap_init,
5378 .trap_fini = mlxsw_sp_trap_fini,
5379 .trap_action_set = mlxsw_sp_trap_action_set,
5380 .trap_group_init = mlxsw_sp_trap_group_init,
5381 .txhdr_construct = mlxsw_sp_txhdr_construct,
5382 .resources_register = mlxsw_sp1_resources_register,
5383 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get,
5384 .params_register = mlxsw_sp_params_register,
5385 .params_unregister = mlxsw_sp_params_unregister,
5386 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5387 .txhdr_len = MLXSW_TXHDR_LEN,
5388 .profile = &mlxsw_sp1_config_profile,
5389 .res_query_enabled = true,
5392 static struct mlxsw_driver mlxsw_sp2_driver = {
5393 .kind = mlxsw_sp2_driver_name,
5394 .priv_size = sizeof(struct mlxsw_sp),
5395 .init = mlxsw_sp2_init,
5396 .fini = mlxsw_sp_fini,
5397 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5398 .port_split = mlxsw_sp_port_split,
5399 .port_unsplit = mlxsw_sp_port_unsplit,
5400 .sb_pool_get = mlxsw_sp_sb_pool_get,
5401 .sb_pool_set = mlxsw_sp_sb_pool_set,
5402 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5403 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5404 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5405 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5406 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5407 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5408 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5409 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5410 .flash_update = mlxsw_sp_flash_update,
5411 .trap_init = mlxsw_sp_trap_init,
5412 .trap_fini = mlxsw_sp_trap_fini,
5413 .trap_action_set = mlxsw_sp_trap_action_set,
5414 .trap_group_init = mlxsw_sp_trap_group_init,
5415 .txhdr_construct = mlxsw_sp_txhdr_construct,
5416 .resources_register = mlxsw_sp2_resources_register,
5417 .params_register = mlxsw_sp2_params_register,
5418 .params_unregister = mlxsw_sp2_params_unregister,
5419 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5420 .txhdr_len = MLXSW_TXHDR_LEN,
5421 .profile = &mlxsw_sp2_config_profile,
5422 .res_query_enabled = true,
5425 static struct mlxsw_driver mlxsw_sp3_driver = {
5426 .kind = mlxsw_sp3_driver_name,
5427 .priv_size = sizeof(struct mlxsw_sp),
5428 .init = mlxsw_sp2_init,
5429 .fini = mlxsw_sp_fini,
5430 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
5431 .port_split = mlxsw_sp_port_split,
5432 .port_unsplit = mlxsw_sp_port_unsplit,
5433 .sb_pool_get = mlxsw_sp_sb_pool_get,
5434 .sb_pool_set = mlxsw_sp_sb_pool_set,
5435 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
5436 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
5437 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
5438 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
5439 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
5440 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
5441 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
5442 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
5443 .flash_update = mlxsw_sp_flash_update,
5444 .trap_init = mlxsw_sp_trap_init,
5445 .trap_fini = mlxsw_sp_trap_fini,
5446 .trap_action_set = mlxsw_sp_trap_action_set,
5447 .trap_group_init = mlxsw_sp_trap_group_init,
5448 .txhdr_construct = mlxsw_sp_txhdr_construct,
5449 .resources_register = mlxsw_sp2_resources_register,
5450 .params_register = mlxsw_sp2_params_register,
5451 .params_unregister = mlxsw_sp2_params_unregister,
5452 .ptp_transmitted = mlxsw_sp_ptp_transmitted,
5453 .txhdr_len = MLXSW_TXHDR_LEN,
5454 .profile = &mlxsw_sp2_config_profile,
5455 .res_query_enabled = true,
5458 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
5460 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
5463 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
5465 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
5468 if (mlxsw_sp_port_dev_check(lower_dev)) {
5469 *p_mlxsw_sp_port = netdev_priv(lower_dev);
5476 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
5478 struct mlxsw_sp_port *mlxsw_sp_port;
5480 if (mlxsw_sp_port_dev_check(dev))
5481 return netdev_priv(dev);
5483 mlxsw_sp_port = NULL;
5484 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
5486 return mlxsw_sp_port;
5489 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
5491 struct mlxsw_sp_port *mlxsw_sp_port;
5493 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
5494 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
5497 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
5499 struct mlxsw_sp_port *mlxsw_sp_port;
5501 if (mlxsw_sp_port_dev_check(dev))
5502 return netdev_priv(dev);
5504 mlxsw_sp_port = NULL;
5505 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
5508 return mlxsw_sp_port;
5511 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
5513 struct mlxsw_sp_port *mlxsw_sp_port;
5516 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
5518 dev_hold(mlxsw_sp_port->dev);
5520 return mlxsw_sp_port;
5523 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
5525 dev_put(mlxsw_sp_port->dev);
5529 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
5530 struct net_device *lag_dev)
5532 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
5533 struct net_device *upper_dev;
5534 struct list_head *iter;
5536 if (netif_is_bridge_port(lag_dev))
5537 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
5539 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
5540 if (!netif_is_bridge_port(upper_dev))
5542 br_dev = netdev_master_upper_dev_get(upper_dev);
5543 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
5547 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5549 char sldr_pl[MLXSW_REG_SLDR_LEN];
5551 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
5552 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5555 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5557 char sldr_pl[MLXSW_REG_SLDR_LEN];
5559 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
5560 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5563 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5564 u16 lag_id, u8 port_index)
5566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5567 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5569 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
5570 lag_id, port_index);
5571 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5574 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5577 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5578 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5580 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
5582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5585 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
5588 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5589 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5591 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
5593 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5596 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
5599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5600 char slcor_pl[MLXSW_REG_SLCOR_LEN];
5602 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
5604 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5607 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5608 struct net_device *lag_dev,
5611 struct mlxsw_sp_upper *lag;
5612 int free_lag_id = -1;
5616 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
5617 for (i = 0; i < max_lag; i++) {
5618 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
5619 if (lag->ref_count) {
5620 if (lag->dev == lag_dev) {
5624 } else if (free_lag_id < 0) {
5628 if (free_lag_id < 0)
5630 *p_lag_id = free_lag_id;
5635 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
5636 struct net_device *lag_dev,
5637 struct netdev_lag_upper_info *lag_upper_info,
5638 struct netlink_ext_ack *extack)
5642 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
5643 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
5646 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
5647 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
5653 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5654 u16 lag_id, u8 *p_port_index)
5656 u64 max_lag_members;
5659 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
5661 for (i = 0; i < max_lag_members; i++) {
5662 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
5670 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
5671 struct net_device *lag_dev)
5673 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5674 struct mlxsw_sp_upper *lag;
5679 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
5682 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5683 if (!lag->ref_count) {
5684 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
5690 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
5693 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
5695 goto err_col_port_add;
5697 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
5698 mlxsw_sp_port->local_port);
5699 mlxsw_sp_port->lag_id = lag_id;
5700 mlxsw_sp_port->lagged = 1;
5703 /* Port is no longer usable as a router interface */
5704 if (mlxsw_sp_port->default_vlan->fid)
5705 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
5710 if (!lag->ref_count)
5711 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5715 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
5716 struct net_device *lag_dev)
5718 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5719 u16 lag_id = mlxsw_sp_port->lag_id;
5720 struct mlxsw_sp_upper *lag;
5722 if (!mlxsw_sp_port->lagged)
5724 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5725 WARN_ON(lag->ref_count == 0);
5727 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
5729 /* Any VLANs configured on the port are no longer valid */
5730 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
5731 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
5732 /* Make the LAG and its directly linked uppers leave bridges they
5735 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
5737 if (lag->ref_count == 1)
5738 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5740 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
5741 mlxsw_sp_port->local_port);
5742 mlxsw_sp_port->lagged = 0;
5745 /* Make sure untagged frames are allowed to ingress */
5746 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
5749 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5752 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5753 char sldr_pl[MLXSW_REG_SLDR_LEN];
5755 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
5756 mlxsw_sp_port->local_port);
5757 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5760 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5763 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5764 char sldr_pl[MLXSW_REG_SLDR_LEN];
5766 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
5767 mlxsw_sp_port->local_port);
5768 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5772 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
5776 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
5777 mlxsw_sp_port->lag_id);
5781 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5783 goto err_dist_port_add;
5788 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5793 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
5797 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
5798 mlxsw_sp_port->lag_id);
5802 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
5803 mlxsw_sp_port->lag_id);
5805 goto err_col_port_disable;
5809 err_col_port_disable:
5810 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5814 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
5815 struct netdev_lag_lower_state_info *info)
5817 if (info->tx_enabled)
5818 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
5820 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
5823 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
5826 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5827 enum mlxsw_reg_spms_state spms_state;
5832 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
5833 MLXSW_REG_SPMS_STATE_DISCARDING;
5835 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
5838 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
5840 for (vid = 0; vid < VLAN_N_VID; vid++)
5841 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
5843 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
5848 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
5853 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
5856 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
5858 goto err_port_stp_set;
5859 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5862 goto err_port_vlan_set;
5864 for (; vid <= VLAN_N_VID - 1; vid++) {
5865 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5868 goto err_vid_learning_set;
5873 err_vid_learning_set:
5874 for (vid--; vid >= 1; vid--)
5875 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
5877 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5879 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5883 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
5887 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
5888 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5891 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5893 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5894 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5897 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
5899 unsigned int num_vxlans = 0;
5900 struct net_device *dev;
5901 struct list_head *iter;
5903 netdev_for_each_lower_dev(br_dev, dev, iter) {
5904 if (netif_is_vxlan(dev))
5908 return num_vxlans > 1;
5911 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
5913 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
5914 struct net_device *dev;
5915 struct list_head *iter;
5917 netdev_for_each_lower_dev(br_dev, dev, iter) {
5921 if (!netif_is_vxlan(dev))
5924 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
5928 if (test_and_set_bit(pvid, vlans))
5935 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
5936 struct netlink_ext_ack *extack)
5938 if (br_multicast_enabled(br_dev)) {
5939 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
5943 if (!br_vlan_enabled(br_dev) &&
5944 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
5945 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
5949 if (br_vlan_enabled(br_dev) &&
5950 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
5951 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
5958 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
5959 struct net_device *dev,
5960 unsigned long event, void *ptr)
5962 struct netdev_notifier_changeupper_info *info;
5963 struct mlxsw_sp_port *mlxsw_sp_port;
5964 struct netlink_ext_ack *extack;
5965 struct net_device *upper_dev;
5966 struct mlxsw_sp *mlxsw_sp;
5969 mlxsw_sp_port = netdev_priv(dev);
5970 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5972 extack = netdev_notifier_info_to_extack(&info->info);
5975 case NETDEV_PRECHANGEUPPER:
5976 upper_dev = info->upper_dev;
5977 if (!is_vlan_dev(upper_dev) &&
5978 !netif_is_lag_master(upper_dev) &&
5979 !netif_is_bridge_master(upper_dev) &&
5980 !netif_is_ovs_master(upper_dev) &&
5981 !netif_is_macvlan(upper_dev)) {
5982 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5987 if (netif_is_bridge_master(upper_dev) &&
5988 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
5989 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
5990 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5992 if (netdev_has_any_upper_dev(upper_dev) &&
5993 (!netif_is_bridge_master(upper_dev) ||
5994 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
5996 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
5999 if (netif_is_lag_master(upper_dev) &&
6000 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
6001 info->upper_info, extack))
6003 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
6004 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
6007 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
6008 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
6009 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
6012 if (netif_is_macvlan(upper_dev) &&
6013 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
6014 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6017 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
6018 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
6021 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
6022 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
6026 case NETDEV_CHANGEUPPER:
6027 upper_dev = info->upper_dev;
6028 if (netif_is_bridge_master(upper_dev)) {
6030 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6035 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6038 } else if (netif_is_lag_master(upper_dev)) {
6039 if (info->linking) {
6040 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
6043 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
6044 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
6047 } else if (netif_is_ovs_master(upper_dev)) {
6049 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
6051 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
6052 } else if (netif_is_macvlan(upper_dev)) {
6054 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6055 } else if (is_vlan_dev(upper_dev)) {
6056 struct net_device *br_dev;
6058 if (!netif_is_bridge_port(upper_dev))
6062 br_dev = netdev_master_upper_dev_get(upper_dev);
6063 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
6072 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
6073 unsigned long event, void *ptr)
6075 struct netdev_notifier_changelowerstate_info *info;
6076 struct mlxsw_sp_port *mlxsw_sp_port;
6079 mlxsw_sp_port = netdev_priv(dev);
6083 case NETDEV_CHANGELOWERSTATE:
6084 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
6085 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
6086 info->lower_state_info);
6088 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
6096 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
6097 struct net_device *port_dev,
6098 unsigned long event, void *ptr)
6101 case NETDEV_PRECHANGEUPPER:
6102 case NETDEV_CHANGEUPPER:
6103 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
6105 case NETDEV_CHANGELOWERSTATE:
6106 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
6113 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
6114 unsigned long event, void *ptr)
6116 struct net_device *dev;
6117 struct list_head *iter;
6120 netdev_for_each_lower_dev(lag_dev, dev, iter) {
6121 if (mlxsw_sp_port_dev_check(dev)) {
6122 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
6132 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
6133 struct net_device *dev,
6134 unsigned long event, void *ptr,
6137 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
6138 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6139 struct netdev_notifier_changeupper_info *info = ptr;
6140 struct netlink_ext_ack *extack;
6141 struct net_device *upper_dev;
6144 extack = netdev_notifier_info_to_extack(&info->info);
6147 case NETDEV_PRECHANGEUPPER:
6148 upper_dev = info->upper_dev;
6149 if (!netif_is_bridge_master(upper_dev) &&
6150 !netif_is_macvlan(upper_dev)) {
6151 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6156 if (netif_is_bridge_master(upper_dev) &&
6157 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6158 mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6159 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6161 if (netdev_has_any_upper_dev(upper_dev) &&
6162 (!netif_is_bridge_master(upper_dev) ||
6163 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6165 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6168 if (netif_is_macvlan(upper_dev) &&
6169 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6170 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6174 case NETDEV_CHANGEUPPER:
6175 upper_dev = info->upper_dev;
6176 if (netif_is_bridge_master(upper_dev)) {
6178 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6183 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6186 } else if (netif_is_macvlan(upper_dev)) {
6188 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6199 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
6200 struct net_device *lag_dev,
6201 unsigned long event,
6204 struct net_device *dev;
6205 struct list_head *iter;
6208 netdev_for_each_lower_dev(lag_dev, dev, iter) {
6209 if (mlxsw_sp_port_dev_check(dev)) {
6210 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
6221 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
6222 struct net_device *br_dev,
6223 unsigned long event, void *ptr,
6226 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
6227 struct netdev_notifier_changeupper_info *info = ptr;
6228 struct netlink_ext_ack *extack;
6229 struct net_device *upper_dev;
6234 extack = netdev_notifier_info_to_extack(&info->info);
6237 case NETDEV_PRECHANGEUPPER:
6238 upper_dev = info->upper_dev;
6239 if (!netif_is_macvlan(upper_dev)) {
6240 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6245 if (netif_is_macvlan(upper_dev) &&
6246 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6247 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6251 case NETDEV_CHANGEUPPER:
6252 upper_dev = info->upper_dev;
6255 if (netif_is_macvlan(upper_dev))
6256 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6263 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
6264 unsigned long event, void *ptr)
6266 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
6267 u16 vid = vlan_dev_vlan_id(vlan_dev);
6269 if (mlxsw_sp_port_dev_check(real_dev))
6270 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
6272 else if (netif_is_lag_master(real_dev))
6273 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
6276 else if (netif_is_bridge_master(real_dev))
6277 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
6283 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
6284 unsigned long event, void *ptr)
6286 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
6287 struct netdev_notifier_changeupper_info *info = ptr;
6288 struct netlink_ext_ack *extack;
6289 struct net_device *upper_dev;
6294 extack = netdev_notifier_info_to_extack(&info->info);
6297 case NETDEV_PRECHANGEUPPER:
6298 upper_dev = info->upper_dev;
6299 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
6300 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6305 if (netif_is_macvlan(upper_dev) &&
6306 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
6307 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6311 case NETDEV_CHANGEUPPER:
6312 upper_dev = info->upper_dev;
6315 if (is_vlan_dev(upper_dev))
6316 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
6317 if (netif_is_macvlan(upper_dev))
6318 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6325 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
6326 unsigned long event, void *ptr)
6328 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
6329 struct netdev_notifier_changeupper_info *info = ptr;
6330 struct netlink_ext_ack *extack;
6332 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
6335 extack = netdev_notifier_info_to_extack(&info->info);
6337 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
6338 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6343 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
6345 struct netdev_notifier_changeupper_info *info = ptr;
6347 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
6349 return netif_is_l3_master(info->upper_dev);
6352 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
6353 struct net_device *dev,
6354 unsigned long event, void *ptr)
6356 struct netdev_notifier_changeupper_info *cu_info;
6357 struct netdev_notifier_info *info = ptr;
6358 struct netlink_ext_ack *extack;
6359 struct net_device *upper_dev;
6361 extack = netdev_notifier_info_to_extack(info);
6364 case NETDEV_CHANGEUPPER:
6365 cu_info = container_of(info,
6366 struct netdev_notifier_changeupper_info,
6368 upper_dev = cu_info->upper_dev;
6369 if (!netif_is_bridge_master(upper_dev))
6371 if (!mlxsw_sp_lower_get(upper_dev))
6373 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6375 if (cu_info->linking) {
6376 if (!netif_running(dev))
6378 /* When the bridge is VLAN-aware, the VNI of the VxLAN
6379 * device needs to be mapped to a VLAN, but at this
6380 * point no VLANs are configured on the VxLAN device
6382 if (br_vlan_enabled(upper_dev))
6384 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
6387 /* VLANs were already flushed, which triggered the
6390 if (br_vlan_enabled(upper_dev))
6392 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6396 upper_dev = netdev_master_upper_dev_get(dev);
6399 if (!netif_is_bridge_master(upper_dev))
6401 if (!mlxsw_sp_lower_get(upper_dev))
6403 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
6406 upper_dev = netdev_master_upper_dev_get(dev);
6409 if (!netif_is_bridge_master(upper_dev))
6411 if (!mlxsw_sp_lower_get(upper_dev))
6413 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6420 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
6421 unsigned long event, void *ptr)
6423 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6424 struct mlxsw_sp_span_entry *span_entry;
6425 struct mlxsw_sp *mlxsw_sp;
6428 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
6429 if (event == NETDEV_UNREGISTER) {
6430 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
6432 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
6434 mlxsw_sp_span_respin(mlxsw_sp);
6436 if (netif_is_vxlan(dev))
6437 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
6438 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
6439 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
6441 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
6442 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
6444 else if (event == NETDEV_PRE_CHANGEADDR ||
6445 event == NETDEV_CHANGEADDR ||
6446 event == NETDEV_CHANGEMTU)
6447 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
6448 else if (mlxsw_sp_is_vrf_event(event, ptr))
6449 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6450 else if (mlxsw_sp_port_dev_check(dev))
6451 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
6452 else if (netif_is_lag_master(dev))
6453 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
6454 else if (is_vlan_dev(dev))
6455 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
6456 else if (netif_is_bridge_master(dev))
6457 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
6458 else if (netif_is_macvlan(dev))
6459 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
6461 return notifier_from_errno(err);
6464 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
6465 .notifier_call = mlxsw_sp_inetaddr_valid_event,
6468 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
6469 .notifier_call = mlxsw_sp_inet6addr_valid_event,
6472 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
6473 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
6477 static struct pci_driver mlxsw_sp1_pci_driver = {
6478 .name = mlxsw_sp1_driver_name,
6479 .id_table = mlxsw_sp1_pci_id_table,
6482 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
6483 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
6487 static struct pci_driver mlxsw_sp2_pci_driver = {
6488 .name = mlxsw_sp2_driver_name,
6489 .id_table = mlxsw_sp2_pci_id_table,
6492 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
6493 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
6497 static struct pci_driver mlxsw_sp3_pci_driver = {
6498 .name = mlxsw_sp3_driver_name,
6499 .id_table = mlxsw_sp3_pci_id_table,
6502 static int __init mlxsw_sp_module_init(void)
6506 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6507 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6509 err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
6511 goto err_sp1_core_driver_register;
6513 err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
6515 goto err_sp2_core_driver_register;
6517 err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
6519 goto err_sp3_core_driver_register;
6521 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
6523 goto err_sp1_pci_driver_register;
6525 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
6527 goto err_sp2_pci_driver_register;
6529 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
6531 goto err_sp3_pci_driver_register;
6535 err_sp3_pci_driver_register:
6536 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6537 err_sp2_pci_driver_register:
6538 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6539 err_sp1_pci_driver_register:
6540 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6541 err_sp3_core_driver_register:
6542 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6543 err_sp2_core_driver_register:
6544 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6545 err_sp1_core_driver_register:
6546 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6547 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6551 static void __exit mlxsw_sp_module_exit(void)
6553 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
6554 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6555 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6556 mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6557 mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6558 mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6559 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6560 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6563 module_init(mlxsw_sp_module_init);
6564 module_exit(mlxsw_sp_module_exit);
6566 MODULE_LICENSE("Dual BSD/GPL");
6567 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
6568 MODULE_DESCRIPTION("Mellanox Spectrum driver");
6569 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
6570 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
6571 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
6572 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);