drivers/net/ethernet/mellanox/mlxsw/spectrum.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/slab.h>
  12 #include <linux/device.h>
  13 #include <linux/skbuff.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/if_bridge.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/bitops.h>
  19 #include <linux/list.h>
  20 #include <linux/notifier.h>
  21 #include <linux/dcbnl.h>
  22 #include <linux/inetdevice.h>
  23 #include <linux/netlink.h>
  24 #include <linux/jhash.h>
  25 #include <net/switchdev.h>
  26 #include <net/pkt_cls.h>
  27 #include <net/tc_act/tc_mirred.h>
  28 #include <net/netevent.h>
  29 #include <net/tc_act/tc_sample.h>
  30 #include <net/addrconf.h>
  31
  32 #include "spectrum.h"
  33 #include "pci.h"
  34 #include "core.h"
  35 #include "core_env.h"
  36 #include "reg.h"
  37 #include "port.h"
  38 #include "trap.h"
  39 #include "txheader.h"
  40 #include "spectrum_cnt.h"
  41 #include "spectrum_dpipe.h"
  42 #include "spectrum_acl_flex_actions.h"
  43 #include "spectrum_span.h"
  44 #include "spectrum_ptp.h"
  45 #include "../mlxfw/mlxfw.h"
  46
  47 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
  48
  49 #define MLXSW_SP1_FWREV_MAJOR 13
  50 #define MLXSW_SP1_FWREV_MINOR 2000
  51 #define MLXSW_SP1_FWREV_SUBMINOR 1886
  52 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  53
  54 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  55         .major = MLXSW_SP1_FWREV_MAJOR,
  56         .minor = MLXSW_SP1_FWREV_MINOR,
  57         .subminor = MLXSW_SP1_FWREV_SUBMINOR,
  58         .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  59 };
  60
  61 #define MLXSW_SP1_FW_FILENAME \
  62         "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
  63         "." __stringify(MLXSW_SP1_FWREV_MINOR) \
  64         "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2"
  65
  66 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  67 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  68 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
  69 static const char mlxsw_sp_driver_version[] = "1.0";
  70
  71 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
  72         0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
  73 };
  74 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
  75         0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
  76 };
  77
  78 /* tx_hdr_version
  79  * Tx header version.
  80  * Must be set to 1.
  81  */
  82 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  83
  84 /* tx_hdr_ctl
  85  * Packet control type.
  86  * 0 - Ethernet control (e.g. EMADs, LACP)
  87  * 1 - Ethernet data
  88  */
  89 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  90
  91 /* tx_hdr_proto
  92  * Packet protocol type. Must be set to 1 (Ethernet).
  93  */
  94 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  95
  96 /* tx_hdr_rx_is_router
  97  * Packet is sent from the router. Valid for data packets only.
  98  */
  99 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
 100
 101 /* tx_hdr_fid_valid
 102  * Indicates if the 'fid' field is valid and should be used for
 103  * forwarding lookup. Valid for data packets only.
 104  */
 105 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
 106
 107 /* tx_hdr_swid
 108  * Switch partition ID. Must be set to 0.
 109  */
 110 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
 111
 112 /* tx_hdr_control_tclass
 113  * Indicates if the packet should use the control TClass and not one
 114  * of the data TClasses.
 115  */
 116 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
 117
 118 /* tx_hdr_etclass
 119  * Egress TClass to be used on the egress device on the egress port.
 120  */
 121 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
 122
 123 /* tx_hdr_port_mid
 124  * Destination local port for unicast packets.
 125  * Destination multicast ID for multicast packets.
 126  *
 127  * Control packets are directed to a specific egress port, while data
 128  * packets are transmitted through the CPU port (0) into the switch partition,
 129  * where forwarding rules are applied.
 130  */
 131 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 132
 133 /* tx_hdr_fid
 134  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
 135  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
 136  * Valid for data packets only.
 137  */
 138 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
 139
 140 /* tx_hdr_type
 141  * 0 - Data packets
 142  * 6 - Control packets
 143  */
 144 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 145
 146 struct mlxsw_sp_mlxfw_dev {
 147         struct mlxfw_dev mlxfw_dev;
 148         struct mlxsw_sp *mlxsw_sp;
 149 };
 150
 151 struct mlxsw_sp_ptp_ops {
 152         struct mlxsw_sp_ptp_clock *
 153                 (*clock_init)(struct mlxsw_sp *mlxsw_sp, struct device *dev);
 154         void (*clock_fini)(struct mlxsw_sp_ptp_clock *clock);
 155
 156         struct mlxsw_sp_ptp_state *(*init)(struct mlxsw_sp *mlxsw_sp);
 157         void (*fini)(struct mlxsw_sp_ptp_state *ptp_state);
 158
 159         /* Notify a driver that a packet that might be PTP was received. Driver
 160          * is responsible for freeing the passed-in SKB.
 161          */
 162         void (*receive)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
 163                         u8 local_port);
 164
 165         /* Notify a driver that a timestamped packet was transmitted. Driver
 166          * is responsible for freeing the passed-in SKB.
 167          */
 168         void (*transmitted)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
 169                             u8 local_port);
 170
 171         int (*hwtstamp_get)(struct mlxsw_sp_port *mlxsw_sp_port,
 172                             struct hwtstamp_config *config);
 173         int (*hwtstamp_set)(struct mlxsw_sp_port *mlxsw_sp_port,
 174                             struct hwtstamp_config *config);
 175         void (*shaper_work)(struct work_struct *work);
 176         int (*get_ts_info)(struct mlxsw_sp *mlxsw_sp,
 177                            struct ethtool_ts_info *info);
 178         int (*get_stats_count)(void);
 179         void (*get_stats_strings)(u8 **p);
 180         void (*get_stats)(struct mlxsw_sp_port *mlxsw_sp_port,
 181                           u64 *data, int data_index);
 182 };
 183
 184 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
 185                                     u16 component_index, u32 *p_max_size,
 186                                     u8 *p_align_bits, u16 *p_max_write_size)
 187 {
 188         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 189                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 190         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 191         char mcqi_pl[MLXSW_REG_MCQI_LEN];
 192         int err;
 193
 194         mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
 195         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
 196         if (err)
 197                 return err;
 198         mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
 199                               p_max_write_size);
 200
 201         *p_align_bits = max_t(u8, *p_align_bits, 2);
 202         *p_max_write_size = min_t(u16, *p_max_write_size,
 203                                   MLXSW_REG_MCDA_MAX_DATA_LEN);
 204         return 0;
 205 }
 206
 207 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 208 {
 209         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 210                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 211         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 212         char mcc_pl[MLXSW_REG_MCC_LEN];
 213         u8 control_state;
 214         int err;
 215
 216         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
 217         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 218         if (err)
 219                 return err;
 220
 221         mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
 222         if (control_state != MLXFW_FSM_STATE_IDLE)
 223                 return -EBUSY;
 224
 225         mlxsw_reg_mcc_pack(mcc_pl,
 226                            MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 227                            0, *fwhandle, 0);
 228         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 229 }
 230
 231 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
 232                                          u32 fwhandle, u16 component_index,
 233                                          u32 component_size)
 234 {
 235         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 236                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 237         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 238         char mcc_pl[MLXSW_REG_MCC_LEN];
 239
 240         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 241                            component_index, fwhandle, component_size);
 242         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 243 }
 244
 245 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
 246                                        u32 fwhandle, u8 *data, u16 size,
 247                                        u32 offset)
 248 {
 249         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 250                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 251         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 252         char mcda_pl[MLXSW_REG_MCDA_LEN];
 253
 254         mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
 255         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
 256 }
 257
 258 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
 259                                          u32 fwhandle, u16 component_index)
 260 {
 261         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 262                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 263         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 264         char mcc_pl[MLXSW_REG_MCC_LEN];
 265
 266         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 267                            component_index, fwhandle, 0);
 268         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 269 }
 270
 271 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 272 {
 273         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 274                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 275         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 276         char mcc_pl[MLXSW_REG_MCC_LEN];
 277
 278         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 279                            fwhandle, 0);
 280         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 281 }
 282
 283 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 284                                     enum mlxfw_fsm_state *fsm_state,
 285                                     enum mlxfw_fsm_state_err *fsm_state_err)
 286 {
 287         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 288                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 289         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 290         char mcc_pl[MLXSW_REG_MCC_LEN];
 291         u8 control_state;
 292         u8 error_code;
 293         int err;
 294
 295         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
 296         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 297         if (err)
 298                 return err;
 299
 300         mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
 301         *fsm_state = control_state;
 302         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 303                                MLXFW_FSM_STATE_ERR_MAX);
 304         return 0;
 305 }
 306
 307 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 308 {
 309         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 310                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 311         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 312         char mcc_pl[MLXSW_REG_MCC_LEN];
 313
 314         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
 315                            fwhandle, 0);
 316         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 317 }
 318
 319 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 320 {
 321         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 322                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 323         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 324         char mcc_pl[MLXSW_REG_MCC_LEN];
 325
 326         mlxsw_reg_mcc_pack(mcc_pl,
 327                            MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 328                            fwhandle, 0);
 329         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 330 }
 331
 332 static void mlxsw_sp_status_notify(struct mlxfw_dev *mlxfw_dev,
 333                                    const char *msg, const char *comp_name,
 334                                    u32 done_bytes, u32 total_bytes)
 335 {
 336         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 337                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 338         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 339
 340         devlink_flash_update_status_notify(priv_to_devlink(mlxsw_sp->core),
 341                                            msg, comp_name,
 342                                            done_bytes, total_bytes);
 343 }
 344
 345 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
 346         .component_query        = mlxsw_sp_component_query,
 347         .fsm_lock               = mlxsw_sp_fsm_lock,
 348         .fsm_component_update   = mlxsw_sp_fsm_component_update,
 349         .fsm_block_download     = mlxsw_sp_fsm_block_download,
 350         .fsm_component_verify   = mlxsw_sp_fsm_component_verify,
 351         .fsm_activate           = mlxsw_sp_fsm_activate,
 352         .fsm_query_state        = mlxsw_sp_fsm_query_state,
 353         .fsm_cancel             = mlxsw_sp_fsm_cancel,
 354         .fsm_release            = mlxsw_sp_fsm_release,
 355         .status_notify          = mlxsw_sp_status_notify,
 356 };
 357
 358 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
 359                                    const struct firmware *firmware,
 360                                    struct netlink_ext_ack *extack)
 361 {
 362         struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
 363                 .mlxfw_dev = {
 364                         .ops = &mlxsw_sp_mlxfw_dev_ops,
 365                         .psid = mlxsw_sp->bus_info->psid,
 366                         .psid_size = strlen(mlxsw_sp->bus_info->psid),
 367                 },
 368                 .mlxsw_sp = mlxsw_sp
 369         };
 370         int err;
 371
 372         mlxsw_core_fw_flash_start(mlxsw_sp->core);
 373         devlink_flash_update_begin_notify(priv_to_devlink(mlxsw_sp->core));
 374         err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev,
 375                                    firmware, extack);
 376         devlink_flash_update_end_notify(priv_to_devlink(mlxsw_sp->core));
 377         mlxsw_core_fw_flash_end(mlxsw_sp->core);
 378
 379         return err;
 380 }
 381
 382 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
 383 {
 384         const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
 385         const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
 386         const char *fw_filename = mlxsw_sp->fw_filename;
 387         union devlink_param_value value;
 388         const struct firmware *firmware;
 389         int err;
 390
 391         /* Don't check if driver does not require it */
 392         if (!req_rev || !fw_filename)
 393                 return 0;
 394
 395         /* Don't check if devlink 'fw_load_policy' param is 'flash' */
 396         err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core),
 397                                                  DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
 398                                                  &value);
 399         if (err)
 400                 return err;
 401         if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)
 402                 return 0;
 403
 404         /* Validate driver & FW are compatible */
 405         if (rev->major != req_rev->major) {
 406                 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
 407                      rev->major, req_rev->major);
 408                 return -EINVAL;
 409         }
 410         if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
 411             MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
 412             mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev))
 413                 return 0;
 414
 415         dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
 416                  rev->major, rev->minor, rev->subminor);
 417         dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
 418                  fw_filename);
 419
 420         err = request_firmware_direct(&firmware, fw_filename,
 421                                       mlxsw_sp->bus_info->dev);
 422         if (err) {
 423                 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
 424                         fw_filename);
 425                 return err;
 426         }
 427
 428         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, NULL);
 429         release_firmware(firmware);
 430         if (err)
 431                 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
 432
 433         /* On FW flash success, tell the caller FW reset is needed
 434          * if current FW supports it.
 435          */
 436         if (rev->minor >= req_rev->can_reset_minor)
 437                 return err ? err : -EAGAIN;
 438         else
 439                 return 0;
 440 }
 441
 442 static int mlxsw_sp_flash_update(struct mlxsw_core *mlxsw_core,
 443                                  const char *file_name, const char *component,
 444                                  struct netlink_ext_ack *extack)
 445 {
 446         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
 447         const struct firmware *firmware;
 448         int err;
 449
 450         if (component)
 451                 return -EOPNOTSUPP;
 452
 453         err = request_firmware_direct(&firmware, file_name,
 454                                       mlxsw_sp->bus_info->dev);
 455         if (err)
 456                 return err;
 457         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, extack);
 458         release_firmware(firmware);
 459
 460         return err;
 461 }
 462
 463 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
 464                               unsigned int counter_index, u64 *packets,
 465                               u64 *bytes)
 466 {
 467         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 468         int err;
 469
 470         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
 471                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 472         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 473         if (err)
 474                 return err;
 475         if (packets)
 476                 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
 477         if (bytes)
 478                 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
 479         return 0;
 480 }
 481
 482 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
 483                                        unsigned int counter_index)
 484 {
 485         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 486
 487         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
 488                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 489         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 490 }
 491
 492 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
 493                                 unsigned int *p_counter_index)
 494 {
 495         int err;
 496
 497         err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 498                                      p_counter_index);
 499         if (err)
 500                 return err;
 501         err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
 502         if (err)
 503                 goto err_counter_clear;
 504         return 0;
 505
 506 err_counter_clear:
 507         mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 508                               *p_counter_index);
 509         return err;
 510 }
 511
 512 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
 513                                 unsigned int counter_index)
 514 {
 515          mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 516                                counter_index);
 517 }
 518
 519 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
 520                                      const struct mlxsw_tx_info *tx_info)
 521 {
 522         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 523
 524         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 525
 526         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
 527         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 528         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 529         mlxsw_tx_hdr_swid_set(txhdr, 0);
 530         mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
 531         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 532         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 533 }
 534
 535 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
 536 {
 537         switch (state) {
 538         case BR_STATE_FORWARDING:
 539                 return MLXSW_REG_SPMS_STATE_FORWARDING;
 540         case BR_STATE_LEARNING:
 541                 return MLXSW_REG_SPMS_STATE_LEARNING;
 542         case BR_STATE_LISTENING: /* fall-through */
 543         case BR_STATE_DISABLED: /* fall-through */
 544         case BR_STATE_BLOCKING:
 545                 return MLXSW_REG_SPMS_STATE_DISCARDING;
 546         default:
 547                 BUG();
 548         }
 549 }
 550
 551 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 552                               u8 state)
 553 {
 554         enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
 555         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 556         char *spms_pl;
 557         int err;
 558
 559         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 560         if (!spms_pl)
 561                 return -ENOMEM;
 562         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
 563         mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
 564
 565         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
 566         kfree(spms_pl);
 567         return err;
 568 }
 569
 570 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
 571 {
 572         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 573         int err;
 574
 575         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
 576         if (err)
 577                 return err;
 578         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
 579         return 0;
 580 }
 581
 582 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
 583                                     bool enable, u32 rate)
 584 {
 585         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 586         char mpsc_pl[MLXSW_REG_MPSC_LEN];
 587
 588         mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
 589         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
 590 }
 591
 592 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
 593                                           bool is_up)
 594 {
 595         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 596         char paos_pl[MLXSW_REG_PAOS_LEN];
 597
 598         mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
 599                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 600                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 601         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
 602 }
 603
 604 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
 605                                       unsigned char *addr)
 606 {
 607         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 608         char ppad_pl[MLXSW_REG_PPAD_LEN];
 609
 610         mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
 611         mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
 612         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
 613 }
 614
 615 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
 616 {
 617         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 618         unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
 619
 620         ether_addr_copy(addr, mlxsw_sp->base_mac);
 621         addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
 622         return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
 623 }
 624
 625 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
 626 {
 627         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 628         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 629         int max_mtu;
 630         int err;
 631
 632         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 633         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
 634         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 635         if (err)
 636                 return err;
 637         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 638
 639         if (mtu > max_mtu)
 640                 return -EINVAL;
 641
 642         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
 643         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 644 }
 645
 646 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
 647 {
 648         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 649         char pspa_pl[MLXSW_REG_PSPA_LEN];
 650
 651         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
 652         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
 653 }
 654
 655 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
 656 {
 657         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 658         char svpe_pl[MLXSW_REG_SVPE_LEN];
 659
 660         mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
 661         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
 662 }
 663
 664 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 665                                    bool learn_enable)
 666 {
 667         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 668         char *spvmlr_pl;
 669         int err;
 670
 671         spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
 672         if (!spvmlr_pl)
 673                 return -ENOMEM;
 674         mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
 675                               learn_enable);
 676         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
 677         kfree(spvmlr_pl);
 678         return err;
 679 }
 680
 681 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
 682                                     u16 vid)
 683 {
 684         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 685         char spvid_pl[MLXSW_REG_SPVID_LEN];
 686
 687         mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
 688         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
 689 }
 690
 691 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
 692                                             bool allow)
 693 {
 694         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 695         char spaft_pl[MLXSW_REG_SPAFT_LEN];
 696
 697         mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
 698         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
 699 }
 700
 701 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
 702 {
 703         int err;
 704
 705         if (!vid) {
 706                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
 707                 if (err)
 708                         return err;
 709         } else {
 710                 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
 711                 if (err)
 712                         return err;
 713                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
 714                 if (err)
 715                         goto err_port_allow_untagged_set;
 716         }
 717
 718         mlxsw_sp_port->pvid = vid;
 719         return 0;
 720
 721 err_port_allow_untagged_set:
 722         __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
 723         return err;
 724 }
 725
 726 static int
 727 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
 728 {
 729         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 730         char sspr_pl[MLXSW_REG_SSPR_LEN];
 731
 732         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
 733         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
 734 }
 735
 736 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
 737                                          u8 local_port, u8 *p_module,
 738                                          u8 *p_width, u8 *p_lane)
 739 {
 740         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 741         int err;
 742
 743         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 744         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 745         if (err)
 746                 return err;
 747         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 748         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 749         *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
 750         return 0;
 751 }
 752
 753 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
 754                                     u8 module, u8 width, u8 lane)
 755 {
 756         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 757         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 758         int i;
 759
 760         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 761         mlxsw_reg_pmlp_width_set(pmlp_pl, width);
 762         for (i = 0; i < width; i++) {
 763                 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
 764                 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);  /* Rx & Tx */
 765         }
 766
 767         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 768 }
 769
 770 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
 771 {
 772         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 773         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 774
 775         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 776         mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
 777         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 778 }
 779
 780 static int mlxsw_sp_port_open(struct net_device *dev)
 781 {
 782         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 783         int err;
 784
 785         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
 786         if (err)
 787                 return err;
 788         netif_start_queue(dev);
 789         return 0;
 790 }
 791
 792 static int mlxsw_sp_port_stop(struct net_device *dev)
 793 {
 794         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 795
 796         netif_stop_queue(dev);
 797         return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
 798 }
 799
 800 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
 801                                       struct net_device *dev)
 802 {
 803         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 804         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 805         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
 806         const struct mlxsw_tx_info tx_info = {
 807                 .local_port = mlxsw_sp_port->local_port,
 808                 .is_emad = false,
 809         };
 810         u64 len;
 811         int err;
 812
 813         memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
 814
 815         if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
 816                 return NETDEV_TX_BUSY;
 817
 818         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 819                 struct sk_buff *skb_orig = skb;
 820
 821                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 822                 if (!skb) {
 823                         this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 824                         dev_kfree_skb_any(skb_orig);
 825                         return NETDEV_TX_OK;
 826                 }
 827                 dev_consume_skb_any(skb_orig);
 828         }
 829
 830         if (eth_skb_pad(skb)) {
 831                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 832                 return NETDEV_TX_OK;
 833         }
 834
 835         mlxsw_sp_txhdr_construct(skb, &tx_info);
 836         /* TX header is consumed by HW on the way so we shouldn't count its
 837          * bytes as being sent.
 838          */
 839         len = skb->len - MLXSW_TXHDR_LEN;
 840
 841         /* Due to a race we might fail here because of a full queue. In that
 842          * unlikely case we simply drop the packet.
 843          */
 844         err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
 845
 846         if (!err) {
 847                 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
 848                 u64_stats_update_begin(&pcpu_stats->syncp);
 849                 pcpu_stats->tx_packets++;
 850                 pcpu_stats->tx_bytes += len;
 851                 u64_stats_update_end(&pcpu_stats->syncp);
 852         } else {
 853                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 854                 dev_kfree_skb_any(skb);
 855         }
 856         return NETDEV_TX_OK;
 857 }
 858
 859 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
 860 {
 861 }
 862
 863 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
 864 {
 865         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 866         struct sockaddr *addr = p;
 867         int err;
 868
 869         if (!is_valid_ether_addr(addr->sa_data))
 870                 return -EADDRNOTAVAIL;
 871
 872         err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
 873         if (err)
 874                 return err;
 875         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 876         return 0;
 877 }
 878
 879 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
 880                                          int mtu)
 881 {
 882         return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
 883 }
 884
 885 #define MLXSW_SP_CELL_FACTOR 2  /* 2 * cell_size / (IPG + cell_size + 1) */
 886
 887 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 888                                   u16 delay)
 889 {
 890         delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
 891                                                             BITS_PER_BYTE));
 892         return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
 893                                                                    mtu);
 894 }
 895
 896 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
 897  * Assumes 100m cable and maximum MTU.
 898  */
 899 #define MLXSW_SP_PAUSE_DELAY 58752
 900
 901 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 902                                      u16 delay, bool pfc, bool pause)
 903 {
 904         if (pfc)
 905                 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
 906         else if (pause)
 907                 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
 908         else
 909                 return 0;
 910 }
 911
 912 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
 913                                  bool lossy)
 914 {
 915         if (lossy)
 916                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
 917         else
 918                 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
 919                                                     thres);
 920 }
 921
 922 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
 923                                  u8 *prio_tc, bool pause_en,
 924                                  struct ieee_pfc *my_pfc)
 925 {
 926         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 927         u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
 928         u16 delay = !!my_pfc ? my_pfc->delay : 0;
 929         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 930         u32 taken_headroom_cells = 0;
 931         u32 max_headroom_cells;
 932         int i, j, err;
 933
 934         max_headroom_cells = mlxsw_sp_sb_max_headroom_cells(mlxsw_sp);
 935
 936         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
 937         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 938         if (err)
 939                 return err;
 940
 941         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 942                 bool configure = false;
 943                 bool pfc = false;
 944                 u16 thres_cells;
 945                 u16 delay_cells;
 946                 u16 total_cells;
 947                 bool lossy;
 948
 949                 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
 950                         if (prio_tc[j] == i) {
 951                                 pfc = pfc_en & BIT(j);
 952                                 configure = true;
 953                                 break;
 954                         }
 955                 }
 956
 957                 if (!configure)
 958                         continue;
 959
 960                 lossy = !(pfc || pause_en);
 961                 thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
 962                 delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
 963                                                         pfc, pause_en);
 964                 total_cells = thres_cells + delay_cells;
 965
 966                 taken_headroom_cells += total_cells;
 967                 if (taken_headroom_cells > max_headroom_cells)
 968                         return -ENOBUFS;
 969
 970                 mlxsw_sp_pg_buf_pack(pbmc_pl, i, total_cells,
 971                                      thres_cells, lossy);
 972         }
 973
 974         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 975 }
 976
 977 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
 978                                       int mtu, bool pause_en)
 979 {
 980         u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
 981         bool dcb_en = !!mlxsw_sp_port->dcb.ets;
 982         struct ieee_pfc *my_pfc;
 983         u8 *prio_tc;
 984
 985         prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
 986         my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
 987
 988         return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
 989                                             pause_en, my_pfc);
 990 }
 991
 992 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
 993 {
 994         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 995         bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
 996         int err;
 997
 998         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
 999         if (err)
1000                 return err;
1001         err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1002         if (err)
1003                 goto err_span_port_mtu_update;
1004         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1005         if (err)
1006                 goto err_port_mtu_set;
1007         dev->mtu = mtu;
1008         return 0;
1009
1010 err_port_mtu_set:
1011         mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1012 err_span_port_mtu_update:
1013         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1014         return err;
1015 }
1016
1017 static int
1018 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1019                              struct rtnl_link_stats64 *stats)
1020 {
1021         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1022         struct mlxsw_sp_port_pcpu_stats *p;
1023         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1024         u32 tx_dropped = 0;
1025         unsigned int start;
1026         int i;
1027
1028         for_each_possible_cpu(i) {
1029                 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1030                 do {
1031                         start = u64_stats_fetch_begin_irq(&p->syncp);
1032                         rx_packets      = p->rx_packets;
1033                         rx_bytes        = p->rx_bytes;
1034                         tx_packets      = p->tx_packets;
1035                         tx_bytes        = p->tx_bytes;
1036                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1037
1038                 stats->rx_packets       += rx_packets;
1039                 stats->rx_bytes         += rx_bytes;
1040                 stats->tx_packets       += tx_packets;
1041                 stats->tx_bytes         += tx_bytes;
1042                 /* tx_dropped is u32, updated without syncp protection. */
1043                 tx_dropped      += p->tx_dropped;
1044         }
1045         stats->tx_dropped       = tx_dropped;
1046         return 0;
1047 }
1048
1049 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
1050 {
1051         switch (attr_id) {
1052         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1053                 return true;
1054         }
1055
1056         return false;
1057 }
1058
1059 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1060                                            void *sp)
1061 {
1062         switch (attr_id) {
1063         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1064                 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1065         }
1066
1067         return -EINVAL;
1068 }
1069
1070 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1071                                        int prio, char *ppcnt_pl)
1072 {
1073         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1074         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1075
1076         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1077         return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1078 }
1079
1080 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1081                                       struct rtnl_link_stats64 *stats)
1082 {
1083         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1084         int err;
1085
1086         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1087                                           0, ppcnt_pl);
1088         if (err)
1089                 goto out;
1090
1091         stats->tx_packets =
1092                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1093         stats->rx_packets =
1094                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1095         stats->tx_bytes =
1096                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1097         stats->rx_bytes =
1098                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1099         stats->multicast =
1100                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1101
1102         stats->rx_crc_errors =
1103                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1104         stats->rx_frame_errors =
1105                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1106
1107         stats->rx_length_errors = (
1108                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1109                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1110                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1111
1112         stats->rx_errors = (stats->rx_crc_errors +
1113                 stats->rx_frame_errors + stats->rx_length_errors);
1114
1115 out:
1116         return err;
1117 }
1118
1119 static void
1120 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1121                             struct mlxsw_sp_port_xstats *xstats)
1122 {
1123         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1124         int err, i;
1125
1126         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1127                                           ppcnt_pl);
1128         if (!err)
1129                 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1130
1131         for (i = 0; i < TC_MAX_QUEUE; i++) {
1132                 err = mlxsw_sp_port_get_stats_raw(dev,
1133                                                   MLXSW_REG_PPCNT_TC_CONG_TC,
1134                                                   i, ppcnt_pl);
1135                 if (!err)
1136                         xstats->wred_drop[i] =
1137                                 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1138
1139                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1140                                                   i, ppcnt_pl);
1141                 if (err)
1142                         continue;
1143
1144                 xstats->backlog[i] =
1145                         mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1146                 xstats->tail_drop[i] =
1147                         mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1148         }
1149
1150         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1151                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1152                                                   i, ppcnt_pl);
1153                 if (err)
1154                         continue;
1155
1156                 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1157                 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1158         }
1159 }
1160
1161 static void update_stats_cache(struct work_struct *work)
1162 {
1163         struct mlxsw_sp_port *mlxsw_sp_port =
1164                 container_of(work, struct mlxsw_sp_port,
1165                              periodic_hw_stats.update_dw.work);
1166
1167         if (!netif_carrier_ok(mlxsw_sp_port->dev))
1168                 goto out;
1169
1170         mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1171                                    &mlxsw_sp_port->periodic_hw_stats.stats);
1172         mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1173                                     &mlxsw_sp_port->periodic_hw_stats.xstats);
1174
1175 out:
1176         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1177                                MLXSW_HW_STATS_UPDATE_TIME);
1178 }
1179
1180 /* Return the stats from a cache that is updated periodically,
1181  * as this function might get called in an atomic context.
1182  */
1183 static void
1184 mlxsw_sp_port_get_stats64(struct net_device *dev,
1185                           struct rtnl_link_stats64 *stats)
1186 {
1187         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1188
1189         memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1190 }
1191
1192 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1193                                     u16 vid_begin, u16 vid_end,
1194                                     bool is_member, bool untagged)
1195 {
1196         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1197         char *spvm_pl;
1198         int err;
1199
1200         spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1201         if (!spvm_pl)
1202                 return -ENOMEM;
1203
1204         mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1205                             vid_end, is_member, untagged);
1206         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1207         kfree(spvm_pl);
1208         return err;
1209 }
1210
1211 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1212                            u16 vid_end, bool is_member, bool untagged)
1213 {
1214         u16 vid, vid_e;
1215         int err;
1216
1217         for (vid = vid_begin; vid <= vid_end;
1218              vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1219                 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1220                             vid_end);
1221
1222                 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1223                                                is_member, untagged);
1224                 if (err)
1225                         return err;
1226         }
1227
1228         return 0;
1229 }
1230
1231 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1232                                      bool flush_default)
1233 {
1234         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1235
1236         list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1237                                  &mlxsw_sp_port->vlans_list, list) {
1238                 if (!flush_default &&
1239                     mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1240                         continue;
1241                 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1242         }
1243 }
1244
1245 static void
1246 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1247 {
1248         if (mlxsw_sp_port_vlan->bridge_port)
1249                 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1250         else if (mlxsw_sp_port_vlan->fid)
1251                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1252 }
1253
1254 struct mlxsw_sp_port_vlan *
1255 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1256 {
1257         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1258         bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1259         int err;
1260
1261         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1262         if (mlxsw_sp_port_vlan)
1263                 return ERR_PTR(-EEXIST);
1264
1265         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1266         if (err)
1267                 return ERR_PTR(err);
1268
1269         mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1270         if (!mlxsw_sp_port_vlan) {
1271                 err = -ENOMEM;
1272                 goto err_port_vlan_alloc;
1273         }
1274
1275         mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1276         mlxsw_sp_port_vlan->vid = vid;
1277         list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1278
1279         return mlxsw_sp_port_vlan;
1280
1281 err_port_vlan_alloc:
1282         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1283         return ERR_PTR(err);
1284 }
1285
1286 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1287 {
1288         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1289         u16 vid = mlxsw_sp_port_vlan->vid;
1290
1291         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1292         list_del(&mlxsw_sp_port_vlan->list);
1293         kfree(mlxsw_sp_port_vlan);
1294         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1295 }
1296
1297 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1298                                  __be16 __always_unused proto, u16 vid)
1299 {
1300         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1301
1302         /* VLAN 0 is added to HW filter when device goes up, but it is
1303          * reserved in our case, so simply return.
1304          */
1305         if (!vid)
1306                 return 0;
1307
1308         return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1309 }
1310
1311 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1312                                   __be16 __always_unused proto, u16 vid)
1313 {
1314         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1315         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1316
1317         /* VLAN 0 is removed from HW filter when device goes down, but
1318          * it is reserved in our case, so simply return.
1319          */
1320         if (!vid)
1321                 return 0;
1322
1323         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1324         if (!mlxsw_sp_port_vlan)
1325                 return 0;
1326         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1327
1328         return 0;
1329 }
1330
1331 static struct mlxsw_sp_port_mall_tc_entry *
1332 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1333                                  unsigned long cookie) {
1334         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1335
1336         list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1337                 if (mall_tc_entry->cookie == cookie)
1338                         return mall_tc_entry;
1339
1340         return NULL;
1341 }
1342
1343 static int
1344 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1345                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1346                                       const struct flow_action_entry *act,
1347                                       bool ingress)
1348 {
1349         enum mlxsw_sp_span_type span_type;
1350
1351         if (!act->dev) {
1352                 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1353                 return -EINVAL;
1354         }
1355
1356         mirror->ingress = ingress;
1357         span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1358         return mlxsw_sp_span_mirror_add(mlxsw_sp_port, act->dev, span_type,
1359                                         true, &mirror->span_id);
1360 }
1361
1362 static void
1363 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1364                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1365 {
1366         enum mlxsw_sp_span_type span_type;
1367
1368         span_type = mirror->ingress ?
1369                         MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1370         mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1371                                  span_type, true);
1372 }
1373
1374 static int
1375 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1376                                       struct tc_cls_matchall_offload *cls,
1377                                       const struct flow_action_entry *act,
1378                                       bool ingress)
1379 {
1380         int err;
1381
1382         if (!mlxsw_sp_port->sample)
1383                 return -EOPNOTSUPP;
1384         if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1385                 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1386                 return -EEXIST;
1387         }
1388         if (act->sample.rate > MLXSW_REG_MPSC_RATE_MAX) {
1389                 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1390                 return -EOPNOTSUPP;
1391         }
1392
1393         rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1394                            act->sample.psample_group);
1395         mlxsw_sp_port->sample->truncate = act->sample.truncate;
1396         mlxsw_sp_port->sample->trunc_size = act->sample.trunc_size;
1397         mlxsw_sp_port->sample->rate = act->sample.rate;
1398
1399         err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, act->sample.rate);
1400         if (err)
1401                 goto err_port_sample_set;
1402         return 0;
1403
1404 err_port_sample_set:
1405         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1406         return err;
1407 }
1408
1409 static void
1410 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1411 {
1412         if (!mlxsw_sp_port->sample)
1413                 return;
1414
1415         mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1416         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1417 }
1418
1419 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1420                                           struct tc_cls_matchall_offload *f,
1421                                           bool ingress)
1422 {
1423         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1424         __be16 protocol = f->common.protocol;
1425         struct flow_action_entry *act;
1426         int err;
1427
1428         if (!flow_offload_has_one_action(&f->rule->action)) {
1429                 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1430                 return -EOPNOTSUPP;
1431         }
1432
1433         mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1434         if (!mall_tc_entry)
1435                 return -ENOMEM;
1436         mall_tc_entry->cookie = f->cookie;
1437
1438         act = &f->rule->action.entries[0];
1439
1440         if (act->id == FLOW_ACTION_MIRRED && protocol == htons(ETH_P_ALL)) {
1441                 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1442
1443                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1444                 mirror = &mall_tc_entry->mirror;
1445                 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1446                                                             mirror, act,
1447                                                             ingress);
1448         } else if (act->id == FLOW_ACTION_SAMPLE &&
1449                    protocol == htons(ETH_P_ALL)) {
1450                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1451                 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1452                                                             act, ingress);
1453         } else {
1454                 err = -EOPNOTSUPP;
1455         }
1456
1457         if (err)
1458                 goto err_add_action;
1459
1460         list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1461         return 0;
1462
1463 err_add_action:
1464         kfree(mall_tc_entry);
1465         return err;
1466 }
1467
1468 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1469                                            struct tc_cls_matchall_offload *f)
1470 {
1471         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1472
1473         mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1474                                                          f->cookie);
1475         if (!mall_tc_entry) {
1476                 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1477                 return;
1478         }
1479         list_del(&mall_tc_entry->list);
1480
1481         switch (mall_tc_entry->type) {
1482         case MLXSW_SP_PORT_MALL_MIRROR:
1483                 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1484                                                       &mall_tc_entry->mirror);
1485                 break;
1486         case MLXSW_SP_PORT_MALL_SAMPLE:
1487                 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1488                 break;
1489         default:
1490                 WARN_ON(1);
1491         }
1492
1493         kfree(mall_tc_entry);
1494 }
1495
1496 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1497                                           struct tc_cls_matchall_offload *f,
1498                                           bool ingress)
1499 {
1500         switch (f->command) {
1501         case TC_CLSMATCHALL_REPLACE:
1502                 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1503                                                       ingress);
1504         case TC_CLSMATCHALL_DESTROY:
1505                 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1506                 return 0;
1507         default:
1508                 return -EOPNOTSUPP;
1509         }
1510 }
1511
1512 static int
1513 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1514                              struct flow_cls_offload *f)
1515 {
1516         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1517
1518         switch (f->command) {
1519         case FLOW_CLS_REPLACE:
1520                 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1521         case FLOW_CLS_DESTROY:
1522                 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1523                 return 0;
1524         case FLOW_CLS_STATS:
1525                 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1526         case FLOW_CLS_TMPLT_CREATE:
1527                 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1528         case FLOW_CLS_TMPLT_DESTROY:
1529                 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1530                 return 0;
1531         default:
1532                 return -EOPNOTSUPP;
1533         }
1534 }
1535
1536 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1537                                                void *type_data,
1538                                                void *cb_priv, bool ingress)
1539 {
1540         struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1541
1542         switch (type) {
1543         case TC_SETUP_CLSMATCHALL:
1544                 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1545                                                    type_data))
1546                         return -EOPNOTSUPP;
1547
1548                 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1549                                                       ingress);
1550         case TC_SETUP_CLSFLOWER:
1551                 return 0;
1552         default:
1553                 return -EOPNOTSUPP;
1554         }
1555 }
1556
1557 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1558                                                   void *type_data,
1559                                                   void *cb_priv)
1560 {
1561         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1562                                                    cb_priv, true);
1563 }
1564
1565 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1566                                                   void *type_data,
1567                                                   void *cb_priv)
1568 {
1569         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1570                                                    cb_priv, false);
1571 }
1572
1573 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1574                                              void *type_data, void *cb_priv)
1575 {
1576         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1577
1578         switch (type) {
1579         case TC_SETUP_CLSMATCHALL:
1580                 return 0;
1581         case TC_SETUP_CLSFLOWER:
1582                 if (mlxsw_sp_acl_block_disabled(acl_block))
1583                         return -EOPNOTSUPP;
1584
1585                 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1586         default:
1587                 return -EOPNOTSUPP;
1588         }
1589 }
1590
1591 static void mlxsw_sp_tc_block_flower_release(void *cb_priv)
1592 {
1593         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1594
1595         mlxsw_sp_acl_block_destroy(acl_block);
1596 }
1597
1598 static LIST_HEAD(mlxsw_sp_block_cb_list);
1599
1600 static int
1601 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1602                                     struct flow_block_offload *f, bool ingress)
1603 {
1604         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1605         struct mlxsw_sp_acl_block *acl_block;
1606         struct flow_block_cb *block_cb;
1607         bool register_block = false;
1608         int err;
1609
1610         block_cb = flow_block_cb_lookup(f->block,
1611                                         mlxsw_sp_setup_tc_block_cb_flower,
1612                                         mlxsw_sp);
1613         if (!block_cb) {
1614                 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, f->net);
1615                 if (!acl_block)
1616                         return -ENOMEM;
1617                 block_cb = flow_block_cb_alloc(mlxsw_sp_setup_tc_block_cb_flower,
1618                                                mlxsw_sp, acl_block,
1619                                                mlxsw_sp_tc_block_flower_release);
1620                 if (IS_ERR(block_cb)) {
1621                         mlxsw_sp_acl_block_destroy(acl_block);
1622                         err = PTR_ERR(block_cb);
1623                         goto err_cb_register;
1624                 }
1625                 register_block = true;
1626         } else {
1627                 acl_block = flow_block_cb_priv(block_cb);
1628         }
1629         flow_block_cb_incref(block_cb);
1630         err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1631                                       mlxsw_sp_port, ingress, f->extack);
1632         if (err)
1633                 goto err_block_bind;
1634
1635         if (ingress)
1636                 mlxsw_sp_port->ing_acl_block = acl_block;
1637         else
1638                 mlxsw_sp_port->eg_acl_block = acl_block;
1639
1640         if (register_block) {
1641                 flow_block_cb_add(block_cb, f);
1642                 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1643         }
1644
1645         return 0;
1646
1647 err_block_bind:
1648         if (!flow_block_cb_decref(block_cb))
1649                 flow_block_cb_free(block_cb);
1650 err_cb_register:
1651         return err;
1652 }
1653
1654 static void
1655 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1656                                       struct flow_block_offload *f, bool ingress)
1657 {
1658         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1659         struct mlxsw_sp_acl_block *acl_block;
1660         struct flow_block_cb *block_cb;
1661         int err;
1662
1663         block_cb = flow_block_cb_lookup(f->block,
1664                                         mlxsw_sp_setup_tc_block_cb_flower,
1665                                         mlxsw_sp);
1666         if (!block_cb)
1667                 return;
1668
1669         if (ingress)
1670                 mlxsw_sp_port->ing_acl_block = NULL;
1671         else
1672                 mlxsw_sp_port->eg_acl_block = NULL;
1673
1674         acl_block = flow_block_cb_priv(block_cb);
1675         err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1676                                         mlxsw_sp_port, ingress);
1677         if (!err && !flow_block_cb_decref(block_cb)) {
1678                 flow_block_cb_remove(block_cb, f);
1679                 list_del(&block_cb->driver_list);
1680         }
1681 }
1682
1683 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1684                                    struct flow_block_offload *f)
1685 {
1686         struct flow_block_cb *block_cb;
1687         flow_setup_cb_t *cb;
1688         bool ingress;
1689         int err;
1690
1691         if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1692                 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1693                 ingress = true;
1694         } else if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1695                 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1696                 ingress = false;
1697         } else {
1698                 return -EOPNOTSUPP;
1699         }
1700
1701         f->driver_block_list = &mlxsw_sp_block_cb_list;
1702
1703         switch (f->command) {
1704         case FLOW_BLOCK_BIND:
1705                 if (flow_block_cb_is_busy(cb, mlxsw_sp_port,
1706                                           &mlxsw_sp_block_cb_list))
1707                         return -EBUSY;
1708
1709                 block_cb = flow_block_cb_alloc(cb, mlxsw_sp_port,
1710                                                mlxsw_sp_port, NULL);
1711                 if (IS_ERR(block_cb))
1712                         return PTR_ERR(block_cb);
1713                 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, f,
1714                                                           ingress);
1715                 if (err) {
1716                         flow_block_cb_free(block_cb);
1717                         return err;
1718                 }
1719                 flow_block_cb_add(block_cb, f);
1720                 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1721                 return 0;
1722         case FLOW_BLOCK_UNBIND:
1723                 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1724                                                       f, ingress);
1725                 block_cb = flow_block_cb_lookup(f->block, cb, mlxsw_sp_port);
1726                 if (!block_cb)
1727                         return -ENOENT;
1728
1729                 flow_block_cb_remove(block_cb, f);
1730                 list_del(&block_cb->driver_list);
1731                 return 0;
1732         default:
1733                 return -EOPNOTSUPP;
1734         }
1735 }
1736
1737 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1738                              void *type_data)
1739 {
1740         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1741
1742         switch (type) {
1743         case TC_SETUP_BLOCK:
1744                 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1745         case TC_SETUP_QDISC_RED:
1746                 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1747         case TC_SETUP_QDISC_PRIO:
1748                 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1749         default:
1750                 return -EOPNOTSUPP;
1751         }
1752 }
1753
1754
1755 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1756 {
1757         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1758
1759         if (!enable) {
1760                 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1761                     mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1762                     !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1763                         netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1764                         return -EINVAL;
1765                 }
1766                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1767                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1768         } else {
1769                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1770                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1771         }
1772         return 0;
1773 }
1774
1775 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1776 {
1777         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1778         char pplr_pl[MLXSW_REG_PPLR_LEN];
1779         int err;
1780
1781         if (netif_running(dev))
1782                 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1783
1784         mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1785         err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1786                               pplr_pl);
1787
1788         if (netif_running(dev))
1789                 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1790
1791         return err;
1792 }
1793
1794 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1795
1796 static int mlxsw_sp_handle_feature(struct net_device *dev,
1797                                    netdev_features_t wanted_features,
1798                                    netdev_features_t feature,
1799                                    mlxsw_sp_feature_handler feature_handler)
1800 {
1801         netdev_features_t changes = wanted_features ^ dev->features;
1802         bool enable = !!(wanted_features & feature);
1803         int err;
1804
1805         if (!(changes & feature))
1806                 return 0;
1807
1808         err = feature_handler(dev, enable);
1809         if (err) {
1810                 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1811                            enable ? "Enable" : "Disable", &feature, err);
1812                 return err;
1813         }
1814
1815         if (enable)
1816                 dev->features |= feature;
1817         else
1818                 dev->features &= ~feature;
1819
1820         return 0;
1821 }
1822 static int mlxsw_sp_set_features(struct net_device *dev,
1823                                  netdev_features_t features)
1824 {
1825         netdev_features_t oper_features = dev->features;
1826         int err = 0;
1827
1828         err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1829                                        mlxsw_sp_feature_hw_tc);
1830         err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1831                                        mlxsw_sp_feature_loopback);
1832
1833         if (err) {
1834                 dev->features = oper_features;
1835                 return -EINVAL;
1836         }
1837
1838         return 0;
1839 }
1840
1841 static struct devlink_port *
1842 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1843 {
1844         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1845         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1846
1847         return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1848                                                 mlxsw_sp_port->local_port);
1849 }
1850
1851 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1852                                       struct ifreq *ifr)
1853 {
1854         struct hwtstamp_config config;
1855         int err;
1856
1857         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1858                 return -EFAULT;
1859
1860         err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1861                                                              &config);
1862         if (err)
1863                 return err;
1864
1865         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1866                 return -EFAULT;
1867
1868         return 0;
1869 }
1870
1871 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1872                                       struct ifreq *ifr)
1873 {
1874         struct hwtstamp_config config;
1875         int err;
1876
1877         err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1878                                                              &config);
1879         if (err)
1880                 return err;
1881
1882         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1883                 return -EFAULT;
1884
1885         return 0;
1886 }
1887
1888 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1889 {
1890         struct hwtstamp_config config = {0};
1891
1892         mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1893 }
1894
1895 static int
1896 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1897 {
1898         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1899
1900         switch (cmd) {
1901         case SIOCSHWTSTAMP:
1902                 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1903         case SIOCGHWTSTAMP:
1904                 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1905         default:
1906                 return -EOPNOTSUPP;
1907         }
1908 }
1909
1910 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1911         .ndo_open               = mlxsw_sp_port_open,
1912         .ndo_stop               = mlxsw_sp_port_stop,
1913         .ndo_start_xmit         = mlxsw_sp_port_xmit,
1914         .ndo_setup_tc           = mlxsw_sp_setup_tc,
1915         .ndo_set_rx_mode        = mlxsw_sp_set_rx_mode,
1916         .ndo_set_mac_address    = mlxsw_sp_port_set_mac_address,
1917         .ndo_change_mtu         = mlxsw_sp_port_change_mtu,
1918         .ndo_get_stats64        = mlxsw_sp_port_get_stats64,
1919         .ndo_has_offload_stats  = mlxsw_sp_port_has_offload_stats,
1920         .ndo_get_offload_stats  = mlxsw_sp_port_get_offload_stats,
1921         .ndo_vlan_rx_add_vid    = mlxsw_sp_port_add_vid,
1922         .ndo_vlan_rx_kill_vid   = mlxsw_sp_port_kill_vid,
1923         .ndo_set_features       = mlxsw_sp_set_features,
1924         .ndo_get_devlink_port   = mlxsw_sp_port_get_devlink_port,
1925         .ndo_do_ioctl           = mlxsw_sp_port_ioctl,
1926 };
1927
1928 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1929                                       struct ethtool_drvinfo *drvinfo)
1930 {
1931         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1932         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1933
1934         strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1935                 sizeof(drvinfo->driver));
1936         strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1937                 sizeof(drvinfo->version));
1938         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1939                  "%d.%d.%d",
1940                  mlxsw_sp->bus_info->fw_rev.major,
1941                  mlxsw_sp->bus_info->fw_rev.minor,
1942                  mlxsw_sp->bus_info->fw_rev.subminor);
1943         strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1944                 sizeof(drvinfo->bus_info));
1945 }
1946
1947 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1948                                          struct ethtool_pauseparam *pause)
1949 {
1950         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1951
1952         pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1953         pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1954 }
1955
1956 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1957                                    struct ethtool_pauseparam *pause)
1958 {
1959         char pfcc_pl[MLXSW_REG_PFCC_LEN];
1960
1961         mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1962         mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1963         mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1964
1965         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1966                                pfcc_pl);
1967 }
1968
1969 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1970                                         struct ethtool_pauseparam *pause)
1971 {
1972         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1973         bool pause_en = pause->tx_pause || pause->rx_pause;
1974         int err;
1975
1976         if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1977                 netdev_err(dev, "PFC already enabled on port\n");
1978                 return -EINVAL;
1979         }
1980
1981         if (pause->autoneg) {
1982                 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1983                 return -EINVAL;
1984         }
1985
1986         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1987         if (err) {
1988                 netdev_err(dev, "Failed to configure port's headroom\n");
1989                 return err;
1990         }
1991
1992         err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1993         if (err) {
1994                 netdev_err(dev, "Failed to set PAUSE parameters\n");
1995                 goto err_port_pause_configure;
1996         }
1997
1998         mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1999         mlxsw_sp_port->link.tx_pause = pause->tx_pause;
2000
2001         return 0;
2002
2003 err_port_pause_configure:
2004         pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2005         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2006         return err;
2007 }
2008
2009 struct mlxsw_sp_port_hw_stats {
2010         char str[ETH_GSTRING_LEN];
2011         u64 (*getter)(const char *payload);
2012         bool cells_bytes;
2013 };
2014
2015 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
2016         {
2017                 .str = "a_frames_transmitted_ok",
2018                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2019         },
2020         {
2021                 .str = "a_frames_received_ok",
2022                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2023         },
2024         {
2025                 .str = "a_frame_check_sequence_errors",
2026                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2027         },
2028         {
2029                 .str = "a_alignment_errors",
2030                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2031         },
2032         {
2033                 .str = "a_octets_transmitted_ok",
2034                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2035         },
2036         {
2037                 .str = "a_octets_received_ok",
2038                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2039         },
2040         {
2041                 .str = "a_multicast_frames_xmitted_ok",
2042                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2043         },
2044         {
2045                 .str = "a_broadcast_frames_xmitted_ok",
2046                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2047         },
2048         {
2049                 .str = "a_multicast_frames_received_ok",
2050                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2051         },
2052         {
2053                 .str = "a_broadcast_frames_received_ok",
2054                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2055         },
2056         {
2057                 .str = "a_in_range_length_errors",
2058                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2059         },
2060         {
2061                 .str = "a_out_of_range_length_field",
2062                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2063         },
2064         {
2065                 .str = "a_frame_too_long_errors",
2066                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2067         },
2068         {
2069                 .str = "a_symbol_error_during_carrier",
2070                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2071         },
2072         {
2073                 .str = "a_mac_control_frames_transmitted",
2074                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2075         },
2076         {
2077                 .str = "a_mac_control_frames_received",
2078                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2079         },
2080         {
2081                 .str = "a_unsupported_opcodes_received",
2082                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2083         },
2084         {
2085                 .str = "a_pause_mac_ctrl_frames_received",
2086                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2087         },
2088         {
2089                 .str = "a_pause_mac_ctrl_frames_xmitted",
2090                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2091         },
2092 };
2093
2094 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2095
2096 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
2097         {
2098                 .str = "if_in_discards",
2099                 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
2100         },
2101         {
2102                 .str = "if_out_discards",
2103                 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
2104         },
2105         {
2106                 .str = "if_out_errors",
2107                 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
2108         },
2109 };
2110
2111 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
2112         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
2113
2114 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
2115         {
2116                 .str = "ether_stats_undersize_pkts",
2117                 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
2118         },
2119         {
2120                 .str = "ether_stats_oversize_pkts",
2121                 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
2122         },
2123         {
2124                 .str = "ether_stats_fragments",
2125                 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
2126         },
2127         {
2128                 .str = "ether_pkts64octets",
2129                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
2130         },
2131         {
2132                 .str = "ether_pkts65to127octets",
2133                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
2134         },
2135         {
2136                 .str = "ether_pkts128to255octets",
2137                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
2138         },
2139         {
2140                 .str = "ether_pkts256to511octets",
2141                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
2142         },
2143         {
2144                 .str = "ether_pkts512to1023octets",
2145                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
2146         },
2147         {
2148                 .str = "ether_pkts1024to1518octets",
2149                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
2150         },
2151         {
2152                 .str = "ether_pkts1519to2047octets",
2153                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
2154         },
2155         {
2156                 .str = "ether_pkts2048to4095octets",
2157                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
2158         },
2159         {
2160                 .str = "ether_pkts4096to8191octets",
2161                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
2162         },
2163         {
2164                 .str = "ether_pkts8192to10239octets",
2165                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
2166         },
2167 };
2168
2169 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
2170         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
2171
2172 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
2173         {
2174                 .str = "dot3stats_fcs_errors",
2175                 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
2176         },
2177         {
2178                 .str = "dot3stats_symbol_errors",
2179                 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
2180         },
2181         {
2182                 .str = "dot3control_in_unknown_opcodes",
2183                 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
2184         },
2185         {
2186                 .str = "dot3in_pause_frames",
2187                 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
2188         },
2189 };
2190
2191 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
2192         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
2193
2194 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
2195         {
2196                 .str = "discard_ingress_general",
2197                 .getter = mlxsw_reg_ppcnt_ingress_general_get,
2198         },
2199         {
2200                 .str = "discard_ingress_policy_engine",
2201                 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
2202         },
2203         {
2204                 .str = "discard_ingress_vlan_membership",
2205                 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
2206         },
2207         {
2208                 .str = "discard_ingress_tag_frame_type",
2209                 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
2210         },
2211         {
2212                 .str = "discard_egress_vlan_membership",
2213                 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
2214         },
2215         {
2216                 .str = "discard_loopback_filter",
2217                 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
2218         },
2219         {
2220                 .str = "discard_egress_general",
2221                 .getter = mlxsw_reg_ppcnt_egress_general_get,
2222         },
2223         {
2224                 .str = "discard_egress_hoq",
2225                 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
2226         },
2227         {
2228                 .str = "discard_egress_policy_engine",
2229                 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
2230         },
2231         {
2232                 .str = "discard_ingress_tx_link_down",
2233                 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
2234         },
2235         {
2236                 .str = "discard_egress_stp_filter",
2237                 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
2238         },
2239         {
2240                 .str = "discard_egress_sll",
2241                 .getter = mlxsw_reg_ppcnt_egress_sll_get,
2242         },
2243 };
2244
2245 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
2246         ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
2247
2248 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2249         {
2250                 .str = "rx_octets_prio",
2251                 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2252         },
2253         {
2254                 .str = "rx_frames_prio",
2255                 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2256         },
2257         {
2258                 .str = "tx_octets_prio",
2259                 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2260         },
2261         {
2262                 .str = "tx_frames_prio",
2263                 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2264         },
2265         {
2266                 .str = "rx_pause_prio",
2267                 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2268         },
2269         {
2270                 .str = "rx_pause_duration_prio",
2271                 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2272         },
2273         {
2274                 .str = "tx_pause_prio",
2275                 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2276         },
2277         {
2278                 .str = "tx_pause_duration_prio",
2279                 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2280         },
2281 };
2282
2283 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2284
2285 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2286         {
2287                 .str = "tc_transmit_queue_tc",
2288                 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2289                 .cells_bytes = true,
2290         },
2291         {
2292                 .str = "tc_no_buffer_discard_uc_tc",
2293                 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2294         },
2295 };
2296
2297 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2298
2299 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
2300                                          MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
2301                                          MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
2302                                          MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
2303                                          MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
2304                                          (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
2305                                           IEEE_8021QAZ_MAX_TCS) + \
2306                                          (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
2307                                           TC_MAX_QUEUE))
2308
2309 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2310 {
2311         int i;
2312
2313         for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2314                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2315                          mlxsw_sp_port_hw_prio_stats[i].str, prio);
2316                 *p += ETH_GSTRING_LEN;
2317         }
2318 }
2319
2320 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2321 {
2322         int i;
2323
2324         for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2325                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2326                          mlxsw_sp_port_hw_tc_stats[i].str, tc);
2327                 *p += ETH_GSTRING_LEN;
2328         }
2329 }
2330
2331 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2332                                       u32 stringset, u8 *data)
2333 {
2334         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2335         u8 *p = data;
2336         int i;
2337
2338         switch (stringset) {
2339         case ETH_SS_STATS:
2340                 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2341                         memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2342                                ETH_GSTRING_LEN);
2343                         p += ETH_GSTRING_LEN;
2344                 }
2345
2346                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
2347                         memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
2348                                ETH_GSTRING_LEN);
2349                         p += ETH_GSTRING_LEN;
2350                 }
2351
2352                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2353                         memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2354                                ETH_GSTRING_LEN);
2355                         p += ETH_GSTRING_LEN;
2356                 }
2357
2358                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
2359                         memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
2360                                ETH_GSTRING_LEN);
2361                         p += ETH_GSTRING_LEN;
2362                 }
2363
2364                 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
2365                         memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
2366                                ETH_GSTRING_LEN);
2367                         p += ETH_GSTRING_LEN;
2368                 }
2369
2370                 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2371                         mlxsw_sp_port_get_prio_strings(&p, i);
2372
2373                 for (i = 0; i < TC_MAX_QUEUE; i++)
2374                         mlxsw_sp_port_get_tc_strings(&p, i);
2375
2376                 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
2377                 break;
2378         }
2379 }
2380
2381 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2382                                      enum ethtool_phys_id_state state)
2383 {
2384         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2385         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2386         char mlcr_pl[MLXSW_REG_MLCR_LEN];
2387         bool active;
2388
2389         switch (state) {
2390         case ETHTOOL_ID_ACTIVE:
2391                 active = true;
2392                 break;
2393         case ETHTOOL_ID_INACTIVE:
2394                 active = false;
2395                 break;
2396         default:
2397                 return -EOPNOTSUPP;
2398         }
2399
2400         mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2401         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2402 }
2403
2404 static int
2405 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2406                                int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2407 {
2408         switch (grp) {
2409         case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2410                 *p_hw_stats = mlxsw_sp_port_hw_stats;
2411                 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2412                 break;
2413         case MLXSW_REG_PPCNT_RFC_2863_CNT:
2414                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
2415                 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2416                 break;
2417         case MLXSW_REG_PPCNT_RFC_2819_CNT:
2418                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2419                 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2420                 break;
2421         case MLXSW_REG_PPCNT_RFC_3635_CNT:
2422                 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
2423                 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2424                 break;
2425         case MLXSW_REG_PPCNT_DISCARD_CNT:
2426                 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
2427                 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2428                 break;
2429         case MLXSW_REG_PPCNT_PRIO_CNT:
2430                 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2431                 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2432                 break;
2433         case MLXSW_REG_PPCNT_TC_CNT:
2434                 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2435                 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2436                 break;
2437         default:
2438                 WARN_ON(1);
2439                 return -EOPNOTSUPP;
2440         }
2441         return 0;
2442 }
2443
2444 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2445                                       enum mlxsw_reg_ppcnt_grp grp, int prio,
2446                                       u64 *data, int data_index)
2447 {
2448         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2449         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2450         struct mlxsw_sp_port_hw_stats *hw_stats;
2451         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2452         int i, len;
2453         int err;
2454
2455         err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2456         if (err)
2457                 return;
2458         mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2459         for (i = 0; i < len; i++) {
2460                 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2461                 if (!hw_stats[i].cells_bytes)
2462                         continue;
2463                 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2464                                                             data[data_index + i]);
2465         }
2466 }
2467
2468 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2469                                     struct ethtool_stats *stats, u64 *data)
2470 {
2471         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2472         int i, data_index = 0;
2473
2474         /* IEEE 802.3 Counters */
2475         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2476                                   data, data_index);
2477         data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2478
2479         /* RFC 2863 Counters */
2480         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
2481                                   data, data_index);
2482         data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2483
2484         /* RFC 2819 Counters */
2485         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2486                                   data, data_index);
2487         data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2488
2489         /* RFC 3635 Counters */
2490         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
2491                                   data, data_index);
2492         data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2493
2494         /* Discard Counters */
2495         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
2496                                   data, data_index);
2497         data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2498
2499         /* Per-Priority Counters */
2500         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2501                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2502                                           data, data_index);
2503                 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2504         }
2505
2506         /* Per-TC Counters */
2507         for (i = 0; i < TC_MAX_QUEUE; i++) {
2508                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2509                                           data, data_index);
2510                 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2511         }
2512
2513         /* PTP counters */
2514         mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
2515                                                     data, data_index);
2516         data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2517 }
2518
2519 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2520 {
2521         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2522
2523         switch (sset) {
2524         case ETH_SS_STATS:
2525                 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
2526                        mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2527         default:
2528                 return -EOPNOTSUPP;
2529         }
2530 }
2531
2532 struct mlxsw_sp1_port_link_mode {
2533         enum ethtool_link_mode_bit_indices mask_ethtool;
2534         u32 mask;
2535         u32 speed;
2536 };
2537
2538 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
2539         {
2540                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2541                 .mask_ethtool   = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2542                 .speed          = SPEED_100,
2543         },
2544         {
2545                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2546                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2547                 .mask_ethtool   = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2548                 .speed          = SPEED_1000,
2549         },
2550         {
2551                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2552                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2553                 .speed          = SPEED_10000,
2554         },
2555         {
2556                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2557                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2558                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2559                 .speed          = SPEED_10000,
2560         },
2561         {
2562                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2563                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2564                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2565                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2566                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2567                 .speed          = SPEED_10000,
2568         },
2569         {
2570                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2571                 .mask_ethtool   = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2572                 .speed          = SPEED_20000,
2573         },
2574         {
2575                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2576                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2577                 .speed          = SPEED_40000,
2578         },
2579         {
2580                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2581                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2582                 .speed          = SPEED_40000,
2583         },
2584         {
2585                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2586                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2587                 .speed          = SPEED_40000,
2588         },
2589         {
2590                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2591                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2592                 .speed          = SPEED_40000,
2593         },
2594         {
2595                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2596                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2597                 .speed          = SPEED_25000,
2598         },
2599         {
2600                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2601                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2602                 .speed          = SPEED_25000,
2603         },
2604         {
2605                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2606                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2607                 .speed          = SPEED_25000,
2608         },
2609         {
2610                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2611                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2612                 .speed          = SPEED_50000,
2613         },
2614         {
2615                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2616                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2617                 .speed          = SPEED_50000,
2618         },
2619         {
2620                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2621                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2622                 .speed          = SPEED_50000,
2623         },
2624         {
2625                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2626                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2627                 .speed          = SPEED_100000,
2628         },
2629         {
2630                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2631                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2632                 .speed          = SPEED_100000,
2633         },
2634         {
2635                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2636                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2637                 .speed          = SPEED_100000,
2638         },
2639         {
2640                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2641                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2642                 .speed          = SPEED_100000,
2643         },
2644 };
2645
2646 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
2647
2648 static void
2649 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
2650                                    u32 ptys_eth_proto,
2651                                    struct ethtool_link_ksettings *cmd)
2652 {
2653         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2654                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2655                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2656                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2657                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2658                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2659                 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2660
2661         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2662                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2663                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2664                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2665                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2666                 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2667 }
2668
2669 static void
2670 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
2671                          u8 width, unsigned long *mode)
2672 {
2673         int i;
2674
2675         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2676                 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2677                         __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2678                                   mode);
2679         }
2680 }
2681
2682 static u32
2683 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
2684 {
2685         int i;
2686
2687         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2688                 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2689                         return mlxsw_sp1_port_link_mode[i].speed;
2690         }
2691
2692         return SPEED_UNKNOWN;
2693 }
2694
2695 static void
2696 mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
2697                                  u32 ptys_eth_proto,
2698                                  struct ethtool_link_ksettings *cmd)
2699 {
2700         cmd->base.speed = SPEED_UNKNOWN;
2701         cmd->base.duplex = DUPLEX_UNKNOWN;
2702
2703         if (!carrier_ok)
2704                 return;
2705
2706         cmd->base.speed = mlxsw_sp1_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
2707         if (cmd->base.speed != SPEED_UNKNOWN)
2708                 cmd->base.duplex = DUPLEX_FULL;
2709 }
2710
2711 static u32
2712 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
2713                               const struct ethtool_link_ksettings *cmd)
2714 {
2715         u32 ptys_proto = 0;
2716         int i;
2717
2718         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2719                 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2720                              cmd->link_modes.advertising))
2721                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2722         }
2723         return ptys_proto;
2724 }
2725
2726 static u32 mlxsw_sp1_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u8 width,
2727                                    u32 speed)
2728 {
2729         u32 ptys_proto = 0;
2730         int i;
2731
2732         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2733                 if (speed == mlxsw_sp1_port_link_mode[i].speed)
2734                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2735         }
2736         return ptys_proto;
2737 }
2738
2739 static u32
2740 mlxsw_sp1_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
2741 {
2742         u32 ptys_proto = 0;
2743         int i;
2744
2745         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2746                 if (mlxsw_sp1_port_link_mode[i].speed <= upper_speed)
2747                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2748         }
2749         return ptys_proto;
2750 }
2751
2752 static int
2753 mlxsw_sp1_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2754                           u32 *base_speed)
2755 {
2756         *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
2757         return 0;
2758 }
2759
2760 static void
2761 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
2762                             u8 local_port, u32 proto_admin, bool autoneg)
2763 {
2764         mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
2765 }
2766
2767 static void
2768 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
2769                               u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
2770                               u32 *p_eth_proto_oper)
2771 {
2772         mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
2773                                   p_eth_proto_oper);
2774 }
2775
2776 static const struct mlxsw_sp_port_type_speed_ops
2777 mlxsw_sp1_port_type_speed_ops = {
2778         .from_ptys_supported_port       = mlxsw_sp1_from_ptys_supported_port,
2779         .from_ptys_link                 = mlxsw_sp1_from_ptys_link,
2780         .from_ptys_speed                = mlxsw_sp1_from_ptys_speed,
2781         .from_ptys_speed_duplex         = mlxsw_sp1_from_ptys_speed_duplex,
2782         .to_ptys_advert_link            = mlxsw_sp1_to_ptys_advert_link,
2783         .to_ptys_speed                  = mlxsw_sp1_to_ptys_speed,
2784         .to_ptys_upper_speed            = mlxsw_sp1_to_ptys_upper_speed,
2785         .port_speed_base                = mlxsw_sp1_port_speed_base,
2786         .reg_ptys_eth_pack              = mlxsw_sp1_reg_ptys_eth_pack,
2787         .reg_ptys_eth_unpack            = mlxsw_sp1_reg_ptys_eth_unpack,
2788 };
2789
2790 static const enum ethtool_link_mode_bit_indices
2791 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
2792         ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2793 };
2794
2795 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
2796         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
2797
2798 static const enum ethtool_link_mode_bit_indices
2799 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
2800         ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2801         ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2802 };
2803
2804 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
2805         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
2806
2807 static const enum ethtool_link_mode_bit_indices
2808 mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {
2809         ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
2810 };
2811
2812 #define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \
2813         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)
2814
2815 static const enum ethtool_link_mode_bit_indices
2816 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
2817         ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2818 };
2819
2820 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
2821         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
2822
2823 static const enum ethtool_link_mode_bit_indices
2824 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
2825         ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2826         ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2827         ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
2828         ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2829         ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2830         ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2831         ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
2832 };
2833
2834 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
2835         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
2836
2837 static const enum ethtool_link_mode_bit_indices
2838 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
2839         ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2840         ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2841         ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2842         ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2843 };
2844
2845 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
2846         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
2847
2848 static const enum ethtool_link_mode_bit_indices
2849 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
2850         ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2851         ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2852         ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2853 };
2854
2855 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
2856         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
2857
2858 static const enum ethtool_link_mode_bit_indices
2859 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
2860         ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2861         ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2862         ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2863 };
2864
2865 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
2866         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
2867
2868 static const enum ethtool_link_mode_bit_indices
2869 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
2870         ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2871         ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2872         ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2873         ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2874         ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
2875 };
2876
2877 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
2878         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
2879
2880 static const enum ethtool_link_mode_bit_indices
2881 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
2882         ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2883         ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2884         ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2885         ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2886 };
2887
2888 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
2889         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
2890
2891 static const enum ethtool_link_mode_bit_indices
2892 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
2893         ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2894         ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2895         ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2896         ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2897         ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
2898 };
2899
2900 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
2901         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
2902
2903 static const enum ethtool_link_mode_bit_indices
2904 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
2905         ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2906         ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2907         ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2908         ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
2909         ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2910 };
2911
2912 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
2913         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
2914
2915 static const enum ethtool_link_mode_bit_indices
2916 mlxsw_sp2_mask_ethtool_400gaui_8[] = {
2917         ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
2918         ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
2919         ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
2920         ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
2921         ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
2922 };
2923
2924 #define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \
2925         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)
2926
2927 #define MLXSW_SP_PORT_MASK_WIDTH_1X     BIT(0)
2928 #define MLXSW_SP_PORT_MASK_WIDTH_2X     BIT(1)
2929 #define MLXSW_SP_PORT_MASK_WIDTH_4X     BIT(2)
2930 #define MLXSW_SP_PORT_MASK_WIDTH_8X     BIT(3)
2931
2932 static u8 mlxsw_sp_port_mask_width_get(u8 width)
2933 {
2934         switch (width) {
2935         case 1:
2936                 return MLXSW_SP_PORT_MASK_WIDTH_1X;
2937         case 2:
2938                 return MLXSW_SP_PORT_MASK_WIDTH_2X;
2939         case 4:
2940                 return MLXSW_SP_PORT_MASK_WIDTH_4X;
2941         case 8:
2942                 return MLXSW_SP_PORT_MASK_WIDTH_8X;
2943         default:
2944                 WARN_ON_ONCE(1);
2945                 return 0;
2946         }
2947 }
2948
2949 struct mlxsw_sp2_port_link_mode {
2950         const enum ethtool_link_mode_bit_indices *mask_ethtool;
2951         int m_ethtool_len;
2952         u32 mask;
2953         u32 speed;
2954         u8 mask_width;
2955 };
2956
2957 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
2958         {
2959                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
2960                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_sgmii_100m,
2961                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
2962                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2963                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2964                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
2965                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
2966                 .speed          = SPEED_100,
2967         },
2968         {
2969                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
2970                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
2971                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
2972                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2973                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2974                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
2975                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
2976                 .speed          = SPEED_1000,
2977         },
2978         {
2979                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,
2980                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,
2981                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
2982                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2983                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2984                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
2985                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
2986                 .speed          = SPEED_2500,
2987         },
2988         {
2989                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
2990                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_5gbase_r,
2991                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
2992                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2993                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2994                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
2995                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
2996                 .speed          = SPEED_5000,
2997         },
2998         {
2999                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
3000                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
3001                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
3002                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
3003                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
3004                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
3005                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
3006                 .speed          = SPEED_10000,
3007         },
3008         {
3009                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
3010                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
3011                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
3012                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X |
3013                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
3014                 .speed          = SPEED_40000,
3015         },
3016         {
3017                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
3018                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
3019                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
3020                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
3021                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
3022                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
3023                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
3024                 .speed          = SPEED_25000,
3025         },
3026         {
3027                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
3028                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
3029                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
3030                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_2X |
3031                                   MLXSW_SP_PORT_MASK_WIDTH_4X |
3032                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
3033                 .speed          = SPEED_50000,
3034         },
3035         {
3036                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
3037                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
3038                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
3039                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X,
3040                 .speed          = SPEED_50000,
3041         },
3042         {
3043                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
3044                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
3045                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
3046                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X |
3047                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
3048                 .speed          = SPEED_100000,
3049         },
3050         {
3051                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
3052                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
3053                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
3054                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_2X,
3055                 .speed          = SPEED_100000,
3056         },
3057         {
3058                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
3059                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
3060                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
3061                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X |
3062                                   MLXSW_SP_PORT_MASK_WIDTH_8X,
3063                 .speed          = SPEED_200000,
3064         },
3065         {
3066                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,
3067                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_400gaui_8,
3068                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN,
3069                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_8X,
3070                 .speed          = SPEED_400000,
3071         },
3072 };
3073
3074 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
3075
3076 static void
3077 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
3078                                    u32 ptys_eth_proto,
3079                                    struct ethtool_link_ksettings *cmd)
3080 {
3081         ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
3082         ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
3083 }
3084
3085 static void
3086 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3087                           unsigned long *mode)
3088 {
3089         int i;
3090
3091         for (i = 0; i < link_mode->m_ethtool_len; i++)
3092                 __set_bit(link_mode->mask_ethtool[i], mode);
3093 }
3094
3095 static void
3096 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
3097                          u8 width, unsigned long *mode)
3098 {
3099         u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3100         int i;
3101
3102         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3103                 if ((ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) &&
3104                     (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3105                         mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3106                                                   mode);
3107         }
3108 }
3109
3110 static u32
3111 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
3112 {
3113         int i;
3114
3115         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3116                 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
3117                         return mlxsw_sp2_port_link_mode[i].speed;
3118         }
3119
3120         return SPEED_UNKNOWN;
3121 }
3122
3123 static void
3124 mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
3125                                  u32 ptys_eth_proto,
3126                                  struct ethtool_link_ksettings *cmd)
3127 {
3128         cmd->base.speed = SPEED_UNKNOWN;
3129         cmd->base.duplex = DUPLEX_UNKNOWN;
3130
3131         if (!carrier_ok)
3132                 return;
3133
3134         cmd->base.speed = mlxsw_sp2_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
3135         if (cmd->base.speed != SPEED_UNKNOWN)
3136                 cmd->base.duplex = DUPLEX_FULL;
3137 }
3138
3139 static bool
3140 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3141                            const unsigned long *mode)
3142 {
3143         int cnt = 0;
3144         int i;
3145
3146         for (i = 0; i < link_mode->m_ethtool_len; i++) {
3147                 if (test_bit(link_mode->mask_ethtool[i], mode))
3148                         cnt++;
3149         }
3150
3151         return cnt == link_mode->m_ethtool_len;
3152 }
3153
3154 static u32
3155 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
3156                               const struct ethtool_link_ksettings *cmd)
3157 {
3158         u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3159         u32 ptys_proto = 0;
3160         int i;
3161
3162         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3163                 if ((mask_width & mlxsw_sp2_port_link_mode[i].mask_width) &&
3164                     mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3165                                                cmd->link_modes.advertising))
3166                         ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3167         }
3168         return ptys_proto;
3169 }
3170
3171 static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp,
3172                                    u8 width, u32 speed)
3173 {
3174         u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3175         u32 ptys_proto = 0;
3176         int i;
3177
3178         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3179                 if ((speed == mlxsw_sp2_port_link_mode[i].speed) &&
3180                     (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3181                         ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3182         }
3183         return ptys_proto;
3184 }
3185
3186 static u32
3187 mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
3188 {
3189         u32 ptys_proto = 0;
3190         int i;
3191
3192         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3193                 if (mlxsw_sp2_port_link_mode[i].speed <= upper_speed)
3194                         ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3195         }
3196         return ptys_proto;
3197 }
3198
3199 static int
3200 mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3201                           u32 *base_speed)
3202 {
3203         char ptys_pl[MLXSW_REG_PTYS_LEN];
3204         u32 eth_proto_cap;
3205         int err;
3206
3207         /* In Spectrum-2, the speed of 1x can change from port to port, so query
3208          * it from firmware.
3209          */
3210         mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false);
3211         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3212         if (err)
3213                 return err;
3214         mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
3215
3216         if (eth_proto_cap &
3217             MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) {
3218                 *base_speed = MLXSW_SP_PORT_BASE_SPEED_50G;
3219                 return 0;
3220         }
3221
3222         if (eth_proto_cap &
3223             MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) {
3224                 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
3225                 return 0;
3226         }
3227
3228         return -EIO;
3229 }
3230
3231 static void
3232 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
3233                             u8 local_port, u32 proto_admin,
3234                             bool autoneg)
3235 {
3236         mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
3237 }
3238
3239 static void
3240 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
3241                               u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
3242                               u32 *p_eth_proto_oper)
3243 {
3244         mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
3245                                       p_eth_proto_admin, p_eth_proto_oper);
3246 }
3247
3248 static const struct mlxsw_sp_port_type_speed_ops
3249 mlxsw_sp2_port_type_speed_ops = {
3250         .from_ptys_supported_port       = mlxsw_sp2_from_ptys_supported_port,
3251         .from_ptys_link                 = mlxsw_sp2_from_ptys_link,
3252         .from_ptys_speed                = mlxsw_sp2_from_ptys_speed,
3253         .from_ptys_speed_duplex         = mlxsw_sp2_from_ptys_speed_duplex,
3254         .to_ptys_advert_link            = mlxsw_sp2_to_ptys_advert_link,
3255         .to_ptys_speed                  = mlxsw_sp2_to_ptys_speed,
3256         .to_ptys_upper_speed            = mlxsw_sp2_to_ptys_upper_speed,
3257         .port_speed_base                = mlxsw_sp2_port_speed_base,
3258         .reg_ptys_eth_pack              = mlxsw_sp2_reg_ptys_eth_pack,
3259         .reg_ptys_eth_unpack            = mlxsw_sp2_reg_ptys_eth_unpack,
3260 };
3261
3262 static void
3263 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
3264                                  u8 width, struct ethtool_link_ksettings *cmd)
3265 {
3266         const struct mlxsw_sp_port_type_speed_ops *ops;
3267
3268         ops = mlxsw_sp->port_type_speed_ops;
3269
3270         ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
3271         ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
3272         ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
3273
3274         ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
3275         ops->from_ptys_link(mlxsw_sp, eth_proto_cap, width,
3276                             cmd->link_modes.supported);
3277 }
3278
3279 static void
3280 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
3281                                  u32 eth_proto_admin, bool autoneg, u8 width,
3282                                  struct ethtool_link_ksettings *cmd)
3283 {
3284         const struct mlxsw_sp_port_type_speed_ops *ops;
3285
3286         ops = mlxsw_sp->port_type_speed_ops;
3287
3288         if (!autoneg)
3289                 return;
3290
3291         ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
3292         ops->from_ptys_link(mlxsw_sp, eth_proto_admin, width,
3293                             cmd->link_modes.advertising);
3294 }
3295
3296 static u8
3297 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
3298 {
3299         switch (connector_type) {
3300         case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
3301                 return PORT_OTHER;
3302         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
3303                 return PORT_NONE;
3304         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
3305                 return PORT_TP;
3306         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
3307                 return PORT_AUI;
3308         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
3309                 return PORT_BNC;
3310         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
3311                 return PORT_MII;
3312         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
3313                 return PORT_FIBRE;
3314         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
3315                 return PORT_DA;
3316         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
3317                 return PORT_OTHER;
3318         default:
3319                 WARN_ON_ONCE(1);
3320                 return PORT_OTHER;
3321         }
3322 }
3323
3324 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
3325                                             struct ethtool_link_ksettings *cmd)
3326 {
3327         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
3328         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3329         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3330         const struct mlxsw_sp_port_type_speed_ops *ops;
3331         char ptys_pl[MLXSW_REG_PTYS_LEN];
3332         u8 connector_type;
3333         bool autoneg;
3334         int err;
3335
3336         ops = mlxsw_sp->port_type_speed_ops;
3337
3338         autoneg = mlxsw_sp_port->link.autoneg;
3339         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3340                                0, false);
3341         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3342         if (err)
3343                 return err;
3344         ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap,
3345                                  &eth_proto_admin, &eth_proto_oper);
3346
3347         mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap,
3348                                          mlxsw_sp_port->mapping.width, cmd);
3349
3350         mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg,
3351                                          mlxsw_sp_port->mapping.width, cmd);
3352
3353         cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3354         connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
3355         cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
3356         ops->from_ptys_speed_duplex(mlxsw_sp, netif_carrier_ok(dev),
3357                                     eth_proto_oper, cmd);
3358
3359         return 0;
3360 }
3361
3362 static int
3363 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
3364                                  const struct ethtool_link_ksettings *cmd)
3365 {
3366         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3367         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3368         const struct mlxsw_sp_port_type_speed_ops *ops;
3369         char ptys_pl[MLXSW_REG_PTYS_LEN];
3370         u32 eth_proto_cap, eth_proto_new;
3371         bool autoneg;
3372         int err;
3373
3374         ops = mlxsw_sp->port_type_speed_ops;
3375
3376         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3377                                0, false);
3378         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3379         if (err)
3380                 return err;
3381         ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap, NULL, NULL);
3382
3383         autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
3384         eth_proto_new = autoneg ?
3385                 ops->to_ptys_advert_link(mlxsw_sp, mlxsw_sp_port->mapping.width,
3386                                          cmd) :
3387                 ops->to_ptys_speed(mlxsw_sp, mlxsw_sp_port->mapping.width,
3388                                    cmd->base.speed);
3389
3390         eth_proto_new = eth_proto_new & eth_proto_cap;
3391         if (!eth_proto_new) {
3392                 netdev_err(dev, "No supported speed requested\n");
3393                 return -EINVAL;
3394         }
3395
3396         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3397                                eth_proto_new, autoneg);
3398         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3399         if (err)
3400                 return err;
3401
3402         mlxsw_sp_port->link.autoneg = autoneg;
3403
3404         if (!netif_running(dev))
3405                 return 0;
3406
3407         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3408         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
3409
3410         return 0;
3411 }
3412
3413 static int mlxsw_sp_get_module_info(struct net_device *netdev,
3414                                     struct ethtool_modinfo *modinfo)
3415 {
3416         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3417         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3418         int err;
3419
3420         err = mlxsw_env_get_module_info(mlxsw_sp->core,
3421                                         mlxsw_sp_port->mapping.module,
3422                                         modinfo);
3423
3424         return err;
3425 }
3426
3427 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
3428                                       struct ethtool_eeprom *ee,
3429                                       u8 *data)
3430 {
3431         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3432         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3433         int err;
3434
3435         err = mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core,
3436                                           mlxsw_sp_port->mapping.module, ee,
3437                                           data);
3438
3439         return err;
3440 }
3441
3442 static int
3443 mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
3444 {
3445         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3446         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3447
3448         return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
3449 }
3450
3451 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
3452         .get_drvinfo            = mlxsw_sp_port_get_drvinfo,
3453         .get_link               = ethtool_op_get_link,
3454         .get_pauseparam         = mlxsw_sp_port_get_pauseparam,
3455         .set_pauseparam         = mlxsw_sp_port_set_pauseparam,
3456         .get_strings            = mlxsw_sp_port_get_strings,
3457         .set_phys_id            = mlxsw_sp_port_set_phys_id,
3458         .get_ethtool_stats      = mlxsw_sp_port_get_stats,
3459         .get_sset_count         = mlxsw_sp_port_get_sset_count,
3460         .get_link_ksettings     = mlxsw_sp_port_get_link_ksettings,
3461         .set_link_ksettings     = mlxsw_sp_port_set_link_ksettings,
3462         .get_module_info        = mlxsw_sp_get_module_info,
3463         .get_module_eeprom      = mlxsw_sp_get_module_eeprom,
3464         .get_ts_info            = mlxsw_sp_get_ts_info,
3465 };
3466
3467 static int
3468 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
3469 {
3470         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3471         const struct mlxsw_sp_port_type_speed_ops *ops;
3472         char ptys_pl[MLXSW_REG_PTYS_LEN];
3473         u32 eth_proto_admin;
3474         u32 upper_speed;
3475         u32 base_speed;
3476         int err;
3477
3478         ops = mlxsw_sp->port_type_speed_ops;
3479
3480         err = ops->port_speed_base(mlxsw_sp, mlxsw_sp_port->local_port,
3481                                    &base_speed);
3482         if (err)
3483                 return err;
3484         upper_speed = base_speed * width;
3485
3486         eth_proto_admin = ops->to_ptys_upper_speed(mlxsw_sp, upper_speed);
3487         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3488                                eth_proto_admin, mlxsw_sp_port->link.autoneg);
3489         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3490 }
3491
3492 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
3493                           enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
3494                           bool dwrr, u8 dwrr_weight)
3495 {
3496         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3497         char qeec_pl[MLXSW_REG_QEEC_LEN];
3498
3499         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3500                             next_index);
3501         mlxsw_reg_qeec_de_set(qeec_pl, true);
3502         mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
3503         mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
3504         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3505 }
3506
3507 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
3508                                   enum mlxsw_reg_qeec_hr hr, u8 index,
3509                                   u8 next_index, u32 maxrate)
3510 {
3511         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3512         char qeec_pl[MLXSW_REG_QEEC_LEN];
3513
3514         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3515                             next_index);
3516         mlxsw_reg_qeec_mase_set(qeec_pl, true);
3517         mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3518         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3519 }
3520
3521 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
3522                                     enum mlxsw_reg_qeec_hr hr, u8 index,
3523                                     u8 next_index, u32 minrate)
3524 {
3525         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3526         char qeec_pl[MLXSW_REG_QEEC_LEN];
3527
3528         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3529                             next_index);
3530         mlxsw_reg_qeec_mise_set(qeec_pl, true);
3531         mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
3532
3533         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3534 }
3535
3536 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3537                               u8 switch_prio, u8 tclass)
3538 {
3539         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3540         char qtct_pl[MLXSW_REG_QTCT_LEN];
3541
3542         mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3543                             tclass);
3544         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3545 }
3546
3547 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3548 {
3549         int err, i;
3550
3551         /* Setup the elements hierarcy, so that each TC is linked to
3552          * one subgroup, which are all member in the same group.
3553          */
3554         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3555                                     MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3556                                     0);
3557         if (err)
3558                 return err;
3559         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3560                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3561                                             MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3562                                             0, false, 0);
3563                 if (err)
3564                         return err;
3565         }
3566         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3567                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3568                                             MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3569                                             false, 0);
3570                 if (err)
3571                         return err;
3572
3573                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3574                                             MLXSW_REG_QEEC_HIERARCY_TC,
3575                                             i + 8, i,
3576                                             true, 100);
3577                 if (err)
3578                         return err;
3579         }
3580
3581         /* Make sure the max shaper is disabled in all hierarchies that support
3582          * it. Note that this disables ptps (PTP shaper), but that is intended
3583          * for the initial configuration.
3584          */
3585         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3586                                             MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3587                                             MLXSW_REG_QEEC_MAS_DIS);
3588         if (err)
3589                 return err;
3590         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3591                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3592                                                     MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3593                                                     i, 0,
3594                                                     MLXSW_REG_QEEC_MAS_DIS);
3595                 if (err)
3596                         return err;
3597         }
3598         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3599                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3600                                                     MLXSW_REG_QEEC_HIERARCY_TC,
3601                                                     i, i,
3602                                                     MLXSW_REG_QEEC_MAS_DIS);
3603                 if (err)
3604                         return err;
3605
3606                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3607                                                     MLXSW_REG_QEEC_HIERARCY_TC,
3608                                                     i + 8, i,
3609                                                     MLXSW_REG_QEEC_MAS_DIS);
3610                 if (err)
3611                         return err;
3612         }
3613
3614         /* Configure the min shaper for multicast TCs. */
3615         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3616                 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
3617                                                MLXSW_REG_QEEC_HIERARCY_TC,
3618                                                i + 8, i,
3619                                                MLXSW_REG_QEEC_MIS_MIN);
3620                 if (err)
3621                         return err;
3622         }
3623
3624         /* Map all priorities to traffic class 0. */
3625         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3626                 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3627                 if (err)
3628                         return err;
3629         }
3630
3631         return 0;
3632 }
3633
3634 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
3635                                         bool enable)
3636 {
3637         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3638         char qtctm_pl[MLXSW_REG_QTCTM_LEN];
3639
3640         mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
3641         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
3642 }
3643
3644 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3645                                 bool split, u8 module, u8 width, u8 lane)
3646 {
3647         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
3648         struct mlxsw_sp_port *mlxsw_sp_port;
3649         struct net_device *dev;
3650         int err;
3651
3652         err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
3653                                    module + 1, split, lane / width,
3654                                    mlxsw_sp->base_mac,
3655                                    sizeof(mlxsw_sp->base_mac));
3656         if (err) {
3657                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3658                         local_port);
3659                 return err;
3660         }
3661
3662         dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
3663         if (!dev) {
3664                 err = -ENOMEM;
3665                 goto err_alloc_etherdev;
3666         }
3667         SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
3668         dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
3669         mlxsw_sp_port = netdev_priv(dev);
3670         mlxsw_sp_port->dev = dev;
3671         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3672         mlxsw_sp_port->local_port = local_port;
3673         mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
3674         mlxsw_sp_port->split = split;
3675         mlxsw_sp_port->mapping.module = module;
3676         mlxsw_sp_port->mapping.width = width;
3677         mlxsw_sp_port->mapping.lane = lane;
3678         mlxsw_sp_port->link.autoneg = 1;
3679         INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
3680         INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
3681
3682         mlxsw_sp_port->pcpu_stats =
3683                 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3684         if (!mlxsw_sp_port->pcpu_stats) {
3685                 err = -ENOMEM;
3686                 goto err_alloc_stats;
3687         }
3688
3689         mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3690                                         GFP_KERNEL);
3691         if (!mlxsw_sp_port->sample) {
3692                 err = -ENOMEM;
3693                 goto err_alloc_sample;
3694         }
3695
3696         INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
3697                           &update_stats_cache);
3698
3699         dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3700         dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3701
3702         err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
3703         if (err) {
3704                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3705                         mlxsw_sp_port->local_port);
3706                 goto err_port_module_map;
3707         }
3708
3709         err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3710         if (err) {
3711                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3712                         mlxsw_sp_port->local_port);
3713                 goto err_port_swid_set;
3714         }
3715
3716         err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3717         if (err) {
3718                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3719                         mlxsw_sp_port->local_port);
3720                 goto err_dev_addr_init;
3721         }
3722
3723         netif_carrier_off(dev);
3724
3725         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
3726                          NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3727         dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
3728
3729         dev->min_mtu = 0;
3730         dev->max_mtu = ETH_MAX_MTU;
3731
3732         /* Each packet needs to have a Tx header (metadata) on top all other
3733          * headers.
3734          */
3735         dev->needed_headroom = MLXSW_TXHDR_LEN;
3736
3737         err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3738         if (err) {
3739                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3740                         mlxsw_sp_port->local_port);
3741                 goto err_port_system_port_mapping_set;
3742         }
3743
3744         err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3745         if (err) {
3746                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3747                         mlxsw_sp_port->local_port);
3748                 goto err_port_speed_by_width_set;
3749         }
3750
3751         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3752         if (err) {
3753                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3754                         mlxsw_sp_port->local_port);
3755                 goto err_port_mtu_set;
3756         }
3757
3758         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3759         if (err)
3760                 goto err_port_admin_status_set;
3761
3762         err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3763         if (err) {
3764                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3765                         mlxsw_sp_port->local_port);
3766                 goto err_port_buffers_init;
3767         }
3768
3769         err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3770         if (err) {
3771                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3772                         mlxsw_sp_port->local_port);
3773                 goto err_port_ets_init;
3774         }
3775
3776         err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3777         if (err) {
3778                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3779                         mlxsw_sp_port->local_port);
3780                 goto err_port_tc_mc_mode;
3781         }
3782
3783         /* ETS and buffers must be initialized before DCB. */
3784         err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3785         if (err) {
3786                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3787                         mlxsw_sp_port->local_port);
3788                 goto err_port_dcb_init;
3789         }
3790
3791         err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3792         if (err) {
3793                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3794                         mlxsw_sp_port->local_port);
3795                 goto err_port_fids_init;
3796         }
3797
3798         err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3799         if (err) {
3800                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3801                         mlxsw_sp_port->local_port);
3802                 goto err_port_qdiscs_init;
3803         }
3804
3805         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
3806                                      false);
3807         if (err) {
3808                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
3809                         mlxsw_sp_port->local_port);
3810                 goto err_port_vlan_clear;
3811         }
3812
3813         err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3814         if (err) {
3815                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3816                         mlxsw_sp_port->local_port);
3817                 goto err_port_nve_init;
3818         }
3819
3820         err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3821         if (err) {
3822                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
3823                         mlxsw_sp_port->local_port);
3824                 goto err_port_pvid_set;
3825         }
3826
3827         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
3828                                                        MLXSW_SP_DEFAULT_VID);
3829         if (IS_ERR(mlxsw_sp_port_vlan)) {
3830                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3831                         mlxsw_sp_port->local_port);
3832                 err = PTR_ERR(mlxsw_sp_port_vlan);
3833                 goto err_port_vlan_create;
3834         }
3835         mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
3836
3837         INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
3838                           mlxsw_sp->ptp_ops->shaper_work);
3839
3840         mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3841         err = register_netdev(dev);
3842         if (err) {
3843                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3844                         mlxsw_sp_port->local_port);
3845                 goto err_register_netdev;
3846         }
3847
3848         mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3849                                 mlxsw_sp_port, dev);
3850         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3851         return 0;
3852
3853 err_register_netdev:
3854         mlxsw_sp->ports[local_port] = NULL;
3855         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
3856 err_port_vlan_create:
3857 err_port_pvid_set:
3858         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3859 err_port_nve_init:
3860 err_port_vlan_clear:
3861         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3862 err_port_qdiscs_init:
3863         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3864 err_port_fids_init:
3865         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3866 err_port_dcb_init:
3867         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3868 err_port_tc_mc_mode:
3869 err_port_ets_init:
3870 err_port_buffers_init:
3871 err_port_admin_status_set:
3872 err_port_mtu_set:
3873 err_port_speed_by_width_set:
3874 err_port_system_port_mapping_set:
3875 err_dev_addr_init:
3876         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3877 err_port_swid_set:
3878         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3879 err_port_module_map:
3880         kfree(mlxsw_sp_port->sample);
3881 err_alloc_sample:
3882         free_percpu(mlxsw_sp_port->pcpu_stats);
3883 err_alloc_stats:
3884         free_netdev(dev);
3885 err_alloc_etherdev:
3886         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3887         return err;
3888 }
3889
3890 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3891 {
3892         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3893
3894         cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3895         cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
3896         mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
3897         mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3898         unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3899         mlxsw_sp->ports[local_port] = NULL;
3900         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
3901         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3902         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3903         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3904         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3905         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3906         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3907         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3908         kfree(mlxsw_sp_port->sample);
3909         free_percpu(mlxsw_sp_port->pcpu_stats);
3910         WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3911         free_netdev(mlxsw_sp_port->dev);
3912         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3913 }
3914
3915 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
3916 {
3917         struct mlxsw_sp_port *mlxsw_sp_port;
3918         int err;
3919
3920         mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
3921         if (!mlxsw_sp_port)
3922                 return -ENOMEM;
3923
3924         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3925         mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
3926
3927         err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
3928                                        mlxsw_sp_port,
3929                                        mlxsw_sp->base_mac,
3930                                        sizeof(mlxsw_sp->base_mac));
3931         if (err) {
3932                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
3933                 goto err_core_cpu_port_init;
3934         }
3935
3936         mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
3937         return 0;
3938
3939 err_core_cpu_port_init:
3940         kfree(mlxsw_sp_port);
3941         return err;
3942 }
3943
3944 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
3945 {
3946         struct mlxsw_sp_port *mlxsw_sp_port =
3947                                 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
3948
3949         mlxsw_core_cpu_port_fini(mlxsw_sp->core);
3950         mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
3951         kfree(mlxsw_sp_port);
3952 }
3953
3954 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3955 {
3956         return mlxsw_sp->ports[local_port] != NULL;
3957 }
3958
3959 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3960 {
3961         int i;
3962
3963         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3964                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3965                         mlxsw_sp_port_remove(mlxsw_sp, i);
3966         mlxsw_sp_cpu_port_remove(mlxsw_sp);
3967         kfree(mlxsw_sp->port_to_module);
3968         kfree(mlxsw_sp->ports);
3969 }
3970
3971 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3972 {
3973         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3974         u8 module, width, lane;
3975         size_t alloc_size;
3976         int i;
3977         int err;
3978
3979         alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3980         mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3981         if (!mlxsw_sp->ports)
3982                 return -ENOMEM;
3983
3984         mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3985                                                  GFP_KERNEL);
3986         if (!mlxsw_sp->port_to_module) {
3987                 err = -ENOMEM;
3988                 goto err_port_to_module_alloc;
3989         }
3990
3991         err = mlxsw_sp_cpu_port_create(mlxsw_sp);
3992         if (err)
3993                 goto err_cpu_port_create;
3994
3995         for (i = 1; i < max_ports; i++) {
3996                 /* Mark as invalid */
3997                 mlxsw_sp->port_to_module[i] = -1;
3998
3999                 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
4000                                                     &width, &lane);
4001                 if (err)
4002                         goto err_port_module_info_get;
4003                 if (!width)
4004                         continue;
4005                 mlxsw_sp->port_to_module[i] = module;
4006                 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
4007                                            module, width, lane);
4008                 if (err)
4009                         goto err_port_create;
4010         }
4011         return 0;
4012
4013 err_port_create:
4014 err_port_module_info_get:
4015         for (i--; i >= 1; i--)
4016                 if (mlxsw_sp_port_created(mlxsw_sp, i))
4017                         mlxsw_sp_port_remove(mlxsw_sp, i);
4018         mlxsw_sp_cpu_port_remove(mlxsw_sp);
4019 err_cpu_port_create:
4020         kfree(mlxsw_sp->port_to_module);
4021 err_port_to_module_alloc:
4022         kfree(mlxsw_sp->ports);
4023         return err;
4024 }
4025
4026 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
4027 {
4028         u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
4029
4030         return local_port - offset;
4031 }
4032
4033 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
4034                                       u8 module, unsigned int count, u8 offset)
4035 {
4036         u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
4037         int err, i;
4038
4039         for (i = 0; i < count; i++) {
4040                 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
4041                                            true, module, width, i * width);
4042                 if (err)
4043                         goto err_port_create;
4044         }
4045
4046         return 0;
4047
4048 err_port_create:
4049         for (i--; i >= 0; i--)
4050                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4051                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4052         return err;
4053 }
4054
4055 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
4056                                          u8 base_port, unsigned int count)
4057 {
4058         u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
4059         int i;
4060
4061         /* Split by four means we need to re-create two ports, otherwise
4062          * only one.
4063          */
4064         count = count / 2;
4065
4066         for (i = 0; i < count; i++) {
4067                 local_port = base_port + i * 2;
4068                 if (mlxsw_sp->port_to_module[local_port] < 0)
4069                         continue;
4070                 module = mlxsw_sp->port_to_module[local_port];
4071
4072                 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
4073                                      width, 0);
4074         }
4075 }
4076
4077 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
4078                                unsigned int count,
4079                                struct netlink_ext_ack *extack)
4080 {
4081         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4082         u8 local_ports_in_1x, local_ports_in_2x, offset;
4083         struct mlxsw_sp_port *mlxsw_sp_port;
4084         u8 module, cur_width, base_port;
4085         int i;
4086         int err;
4087
4088         if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4089             !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4090                 return -EIO;
4091
4092         local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4093         local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4094
4095         mlxsw_sp_port = mlxsw_sp->ports[local_port];
4096         if (!mlxsw_sp_port) {
4097                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4098                         local_port);
4099                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4100                 return -EINVAL;
4101         }
4102
4103         module = mlxsw_sp_port->mapping.module;
4104         cur_width = mlxsw_sp_port->mapping.width;
4105
4106         if (count != 2 && count != 4) {
4107                 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
4108                 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
4109                 return -EINVAL;
4110         }
4111
4112         if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
4113                 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
4114                 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
4115                 return -EINVAL;
4116         }
4117
4118         /* Make sure we have enough slave (even) ports for the split. */
4119         if (count == 2) {
4120                 offset = local_ports_in_2x;
4121                 base_port = local_port;
4122                 if (mlxsw_sp->ports[base_port + local_ports_in_2x]) {
4123                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4124                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4125                         return -EINVAL;
4126                 }
4127         } else {
4128                 offset = local_ports_in_1x;
4129                 base_port = mlxsw_sp_cluster_base_port_get(local_port);
4130                 if (mlxsw_sp->ports[base_port + 1] ||
4131                     mlxsw_sp->ports[base_port + 3]) {
4132                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4133                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4134                         return -EINVAL;
4135                 }
4136         }
4137
4138         for (i = 0; i < count; i++)
4139                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4140                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4141
4142         err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count,
4143                                          offset);
4144         if (err) {
4145                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
4146                 goto err_port_split_create;
4147         }
4148
4149         return 0;
4150
4151 err_port_split_create:
4152         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4153         return err;
4154 }
4155
4156 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
4157                                  struct netlink_ext_ack *extack)
4158 {
4159         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4160         u8 local_ports_in_1x, local_ports_in_2x, offset;
4161         struct mlxsw_sp_port *mlxsw_sp_port;
4162         u8 cur_width, base_port;
4163         unsigned int count;
4164         int i;
4165
4166         if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4167             !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4168                 return -EIO;
4169
4170         local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4171         local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4172
4173         mlxsw_sp_port = mlxsw_sp->ports[local_port];
4174         if (!mlxsw_sp_port) {
4175                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4176                         local_port);
4177                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4178                 return -EINVAL;
4179         }
4180
4181         if (!mlxsw_sp_port->split) {
4182                 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
4183                 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
4184                 return -EINVAL;
4185         }
4186
4187         cur_width = mlxsw_sp_port->mapping.width;
4188         count = cur_width == 1 ? 4 : 2;
4189
4190         if (count == 2)
4191                 offset = local_ports_in_2x;
4192         else
4193                 offset = local_ports_in_1x;
4194
4195         base_port = mlxsw_sp_cluster_base_port_get(local_port);
4196
4197         /* Determine which ports to remove. */
4198         if (count == 2 && local_port >= base_port + 2)
4199                 base_port = base_port + 2;
4200
4201         for (i = 0; i < count; i++)
4202                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4203                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4204
4205         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4206
4207         return 0;
4208 }
4209
4210 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
4211                                      char *pude_pl, void *priv)
4212 {
4213         struct mlxsw_sp *mlxsw_sp = priv;
4214         struct mlxsw_sp_port *mlxsw_sp_port;
4215         enum mlxsw_reg_pude_oper_status status;
4216         u8 local_port;
4217
4218         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
4219         mlxsw_sp_port = mlxsw_sp->ports[local_port];
4220         if (!mlxsw_sp_port)
4221                 return;
4222
4223         status = mlxsw_reg_pude_oper_status_get(pude_pl);
4224         if (status == MLXSW_PORT_OPER_STATUS_UP) {
4225                 netdev_info(mlxsw_sp_port->dev, "link up\n");
4226                 netif_carrier_on(mlxsw_sp_port->dev);
4227                 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
4228         } else {
4229                 netdev_info(mlxsw_sp_port->dev, "link down\n");
4230                 netif_carrier_off(mlxsw_sp_port->dev);
4231         }
4232 }
4233
4234 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
4235                                           char *mtpptr_pl, bool ingress)
4236 {
4237         u8 local_port;
4238         u8 num_rec;
4239         int i;
4240
4241         local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
4242         num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
4243         for (i = 0; i < num_rec; i++) {
4244                 u8 domain_number;
4245                 u8 message_type;
4246                 u16 sequence_id;
4247                 u64 timestamp;
4248
4249                 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
4250                                         &domain_number, &sequence_id,
4251                                         &timestamp);
4252                 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
4253                                             message_type, domain_number,
4254                                             sequence_id, timestamp);
4255         }
4256 }
4257
4258 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
4259                                               char *mtpptr_pl, void *priv)
4260 {
4261         struct mlxsw_sp *mlxsw_sp = priv;
4262
4263         mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
4264 }
4265
4266 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
4267                                               char *mtpptr_pl, void *priv)
4268 {
4269         struct mlxsw_sp *mlxsw_sp = priv;
4270
4271         mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
4272 }
4273
4274 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
4275                                        u8 local_port, void *priv)
4276 {
4277         struct mlxsw_sp *mlxsw_sp = priv;
4278         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4279         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
4280
4281         if (unlikely(!mlxsw_sp_port)) {
4282                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
4283                                      local_port);
4284                 return;
4285         }
4286
4287         skb->dev = mlxsw_sp_port->dev;
4288
4289         pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
4290         u64_stats_update_begin(&pcpu_stats->syncp);
4291         pcpu_stats->rx_packets++;
4292         pcpu_stats->rx_bytes += skb->len;
4293         u64_stats_update_end(&pcpu_stats->syncp);
4294
4295         skb->protocol = eth_type_trans(skb, skb->dev);
4296         netif_receive_skb(skb);
4297 }
4298
4299 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
4300                                            void *priv)
4301 {
4302         skb->offload_fwd_mark = 1;
4303         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4304 }
4305
4306 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
4307                                               u8 local_port, void *priv)
4308 {
4309         skb->offload_l3_fwd_mark = 1;
4310         skb->offload_fwd_mark = 1;
4311         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4312 }
4313
4314 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
4315                                              void *priv)
4316 {
4317         struct mlxsw_sp *mlxsw_sp = priv;
4318         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4319         struct psample_group *psample_group;
4320         u32 size;
4321
4322         if (unlikely(!mlxsw_sp_port)) {
4323                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
4324                                      local_port);
4325                 goto out;
4326         }
4327         if (unlikely(!mlxsw_sp_port->sample)) {
4328                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
4329                                      local_port);
4330                 goto out;
4331         }
4332
4333         size = mlxsw_sp_port->sample->truncate ?
4334                   mlxsw_sp_port->sample->trunc_size : skb->len;
4335
4336         rcu_read_lock();
4337         psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
4338         if (!psample_group)
4339                 goto out_unlock;
4340         psample_sample_packet(psample_group, skb, size,
4341                               mlxsw_sp_port->dev->ifindex, 0,
4342                               mlxsw_sp_port->sample->rate);
4343 out_unlock:
4344         rcu_read_unlock();
4345 out:
4346         consume_skb(skb);
4347 }
4348
4349 static void mlxsw_sp_rx_listener_ptp(struct sk_buff *skb, u8 local_port,
4350                                      void *priv)
4351 {
4352         struct mlxsw_sp *mlxsw_sp = priv;
4353
4354         mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
4355 }
4356
4357 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
4358         MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
4359                   _is_ctrl, SP_##_trap_group, DISCARD)
4360
4361 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)     \
4362         MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,    \
4363                 _is_ctrl, SP_##_trap_group, DISCARD)
4364
4365 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
4366         MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
4367                 _is_ctrl, SP_##_trap_group, DISCARD)
4368
4369 #define MLXSW_SP_EVENTL(_func, _trap_id)                \
4370         MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
4371
4372 static const struct mlxsw_listener mlxsw_sp_listener[] = {
4373         /* Events */
4374         MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
4375         /* L2 traps */
4376         MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
4377         MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
4378         MLXSW_RXL(mlxsw_sp_rx_listener_ptp, LLDP, TRAP_TO_CPU,
4379                   false, SP_LLDP, DISCARD),
4380         MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
4381         MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
4382         MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
4383         MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
4384         MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
4385         MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
4386         MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
4387         MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
4388         MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
4389         MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
4390                           false),
4391         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4392                              false),
4393         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
4394                              false),
4395         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4396                              false),
4397         /* L3 traps */
4398         MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4399         MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4400         MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false),
4401         MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
4402         MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
4403                           false),
4404         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
4405         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
4406         MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
4407         MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
4408                           false),
4409         MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
4410         MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
4411         MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
4412         MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
4413         MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
4414         MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
4415         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4416                           false),
4417         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4418                           false),
4419         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4420                           false),
4421         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4422                           false),
4423         MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
4424         MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
4425                           false),
4426         MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
4427         MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
4428         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
4429         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
4430         MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4431         MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
4432         MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
4433         MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false),
4434         /* PKT Sample trap */
4435         MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
4436                   false, SP_IP2ME, DISCARD),
4437         /* ACL trap */
4438         MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
4439         /* Multicast Router Traps */
4440         MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
4441         MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
4442         MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
4443         MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
4444         MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
4445         /* NVE traps */
4446         MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
4447         MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false),
4448         /* PTP traps */
4449         MLXSW_RXL(mlxsw_sp_rx_listener_ptp, PTP0, TRAP_TO_CPU,
4450                   false, SP_PTP0, DISCARD),
4451         MLXSW_SP_RXL_NO_MARK(PTP1, TRAP_TO_CPU, PTP1, false),
4452 };
4453
4454 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
4455         /* Events */
4456         MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
4457         MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
4458 };
4459
4460 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
4461 {
4462         char qpcr_pl[MLXSW_REG_QPCR_LEN];
4463         enum mlxsw_reg_qpcr_ir_units ir_units;
4464         int max_cpu_policers;
4465         bool is_bytes;
4466         u8 burst_size;
4467         u32 rate;
4468         int i, err;
4469
4470         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
4471                 return -EIO;
4472
4473         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4474
4475         ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
4476         for (i = 0; i < max_cpu_policers; i++) {
4477                 is_bytes = false;
4478                 switch (i) {
4479                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4480                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4481                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4482                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4483                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4484                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4485                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4486                         rate = 128;
4487                         burst_size = 7;
4488                         break;
4489                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4490                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4491                         rate = 16 * 1024;
4492                         burst_size = 10;
4493                         break;
4494                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4495                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4496                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4497                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4498                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4499                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4500                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4501                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4502                         rate = 1024;
4503                         burst_size = 7;
4504                         break;
4505                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4506                         rate = 1024;
4507                         burst_size = 7;
4508                         break;
4509                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4510                         rate = 24 * 1024;
4511                         burst_size = 12;
4512                         break;
4513                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4514                         rate = 19 * 1024;
4515                         burst_size = 12;
4516                         break;
4517                 default:
4518                         continue;
4519                 }
4520
4521                 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
4522                                     burst_size);
4523                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
4524                 if (err)
4525                         return err;
4526         }
4527
4528         return 0;
4529 }
4530
4531 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
4532 {
4533         char htgt_pl[MLXSW_REG_HTGT_LEN];
4534         enum mlxsw_reg_htgt_trap_group i;
4535         int max_cpu_policers;
4536         int max_trap_groups;
4537         u8 priority, tc;
4538         u16 policer_id;
4539         int err;
4540
4541         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
4542                 return -EIO;
4543
4544         max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
4545         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4546
4547         for (i = 0; i < max_trap_groups; i++) {
4548                 policer_id = i;
4549                 switch (i) {
4550                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4551                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4552                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4553                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4554                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4555                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4556                         priority = 5;
4557                         tc = 5;
4558                         break;
4559                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4560                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4561                         priority = 4;
4562                         tc = 4;
4563                         break;
4564                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4565                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4566                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4567                         priority = 3;
4568                         tc = 3;
4569                         break;
4570                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4571                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4572                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4573                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4574                         priority = 2;
4575                         tc = 2;
4576                         break;
4577                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4578                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4579                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4580                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4581                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4582                         priority = 1;
4583                         tc = 1;
4584                         break;
4585                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
4586                         priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
4587                         tc = MLXSW_REG_HTGT_DEFAULT_TC;
4588                         policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
4589                         break;
4590                 default:
4591                         continue;
4592                 }
4593
4594                 if (max_cpu_policers <= policer_id &&
4595                     policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
4596                         return -EIO;
4597
4598                 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
4599                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4600                 if (err)
4601                         return err;
4602         }
4603
4604         return 0;
4605 }
4606
4607 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
4608                                    const struct mlxsw_listener listeners[],
4609                                    size_t listeners_count)
4610 {
4611         int i;
4612         int err;
4613
4614         for (i = 0; i < listeners_count; i++) {
4615                 err = mlxsw_core_trap_register(mlxsw_sp->core,
4616                                                &listeners[i],
4617                                                mlxsw_sp);
4618                 if (err)
4619                         goto err_listener_register;
4620
4621         }
4622         return 0;
4623
4624 err_listener_register:
4625         for (i--; i >= 0; i--) {
4626                 mlxsw_core_trap_unregister(mlxsw_sp->core,
4627                                            &listeners[i],
4628                                            mlxsw_sp);
4629         }
4630         return err;
4631 }
4632
4633 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
4634                                       const struct mlxsw_listener listeners[],
4635                                       size_t listeners_count)
4636 {
4637         int i;
4638
4639         for (i = 0; i < listeners_count; i++) {
4640                 mlxsw_core_trap_unregister(mlxsw_sp->core,
4641                                            &listeners[i],
4642                                            mlxsw_sp);
4643         }
4644 }
4645
4646 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
4647 {
4648         int err;
4649
4650         err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
4651         if (err)
4652                 return err;
4653
4654         err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
4655         if (err)
4656                 return err;
4657
4658         err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
4659                                       ARRAY_SIZE(mlxsw_sp_listener));
4660         if (err)
4661                 return err;
4662
4663         err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
4664                                       mlxsw_sp->listeners_count);
4665         if (err)
4666                 goto err_extra_traps_init;
4667
4668         return 0;
4669
4670 err_extra_traps_init:
4671         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4672                                   ARRAY_SIZE(mlxsw_sp_listener));
4673         return err;
4674 }
4675
4676 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
4677 {
4678         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
4679                                   mlxsw_sp->listeners_count);
4680         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4681                                   ARRAY_SIZE(mlxsw_sp_listener));
4682 }
4683
4684 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
4685
4686 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
4687 {
4688         char slcr_pl[MLXSW_REG_SLCR_LEN];
4689         u32 seed;
4690         int err;
4691
4692         seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
4693                      MLXSW_SP_LAG_SEED_INIT);
4694         mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
4695                                      MLXSW_REG_SLCR_LAG_HASH_DMAC |
4696                                      MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
4697                                      MLXSW_REG_SLCR_LAG_HASH_VLANID |
4698                                      MLXSW_REG_SLCR_LAG_HASH_SIP |
4699                                      MLXSW_REG_SLCR_LAG_HASH_DIP |
4700                                      MLXSW_REG_SLCR_LAG_HASH_SPORT |
4701                                      MLXSW_REG_SLCR_LAG_HASH_DPORT |
4702                                      MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
4703         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
4704         if (err)
4705                 return err;
4706
4707         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
4708             !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
4709                 return -EIO;
4710
4711         mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
4712                                  sizeof(struct mlxsw_sp_upper),
4713                                  GFP_KERNEL);
4714         if (!mlxsw_sp->lags)
4715                 return -ENOMEM;
4716
4717         return 0;
4718 }
4719
4720 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
4721 {
4722         kfree(mlxsw_sp->lags);
4723 }
4724
4725 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
4726 {
4727         char htgt_pl[MLXSW_REG_HTGT_LEN];
4728
4729         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4730                             MLXSW_REG_HTGT_INVALID_POLICER,
4731                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
4732                             MLXSW_REG_HTGT_DEFAULT_TC);
4733         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4734 }
4735
4736 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
4737         .clock_init     = mlxsw_sp1_ptp_clock_init,
4738         .clock_fini     = mlxsw_sp1_ptp_clock_fini,
4739         .init           = mlxsw_sp1_ptp_init,
4740         .fini           = mlxsw_sp1_ptp_fini,
4741         .receive        = mlxsw_sp1_ptp_receive,
4742         .transmitted    = mlxsw_sp1_ptp_transmitted,
4743         .hwtstamp_get   = mlxsw_sp1_ptp_hwtstamp_get,
4744         .hwtstamp_set   = mlxsw_sp1_ptp_hwtstamp_set,
4745         .shaper_work    = mlxsw_sp1_ptp_shaper_work,
4746         .get_ts_info    = mlxsw_sp1_ptp_get_ts_info,
4747         .get_stats_count = mlxsw_sp1_get_stats_count,
4748         .get_stats_strings = mlxsw_sp1_get_stats_strings,
4749         .get_stats      = mlxsw_sp1_get_stats,
4750 };
4751
4752 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
4753         .clock_init     = mlxsw_sp2_ptp_clock_init,
4754         .clock_fini     = mlxsw_sp2_ptp_clock_fini,
4755         .init           = mlxsw_sp2_ptp_init,
4756         .fini           = mlxsw_sp2_ptp_fini,
4757         .receive        = mlxsw_sp2_ptp_receive,
4758         .transmitted    = mlxsw_sp2_ptp_transmitted,
4759         .hwtstamp_get   = mlxsw_sp2_ptp_hwtstamp_get,
4760         .hwtstamp_set   = mlxsw_sp2_ptp_hwtstamp_set,
4761         .shaper_work    = mlxsw_sp2_ptp_shaper_work,
4762         .get_ts_info    = mlxsw_sp2_ptp_get_ts_info,
4763         .get_stats_count = mlxsw_sp2_get_stats_count,
4764         .get_stats_strings = mlxsw_sp2_get_stats_strings,
4765         .get_stats      = mlxsw_sp2_get_stats,
4766 };
4767
4768 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4769                                     unsigned long event, void *ptr);
4770
4771 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
4772                          const struct mlxsw_bus_info *mlxsw_bus_info,
4773                          struct netlink_ext_ack *extack)
4774 {
4775         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4776         int err;
4777
4778         mlxsw_sp->core = mlxsw_core;
4779         mlxsw_sp->bus_info = mlxsw_bus_info;
4780
4781         err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
4782         if (err)
4783                 return err;
4784
4785         err = mlxsw_sp_base_mac_get(mlxsw_sp);
4786         if (err) {
4787                 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
4788                 return err;
4789         }
4790
4791         err = mlxsw_sp_kvdl_init(mlxsw_sp);
4792         if (err) {
4793                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
4794                 return err;
4795         }
4796
4797         err = mlxsw_sp_fids_init(mlxsw_sp);
4798         if (err) {
4799                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
4800                 goto err_fids_init;
4801         }
4802
4803         err = mlxsw_sp_traps_init(mlxsw_sp);
4804         if (err) {
4805                 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
4806                 goto err_traps_init;
4807         }
4808
4809         err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
4810         if (err) {
4811                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
4812                 goto err_devlink_traps_init;
4813         }
4814
4815         err = mlxsw_sp_buffers_init(mlxsw_sp);
4816         if (err) {
4817                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
4818                 goto err_buffers_init;
4819         }
4820
4821         err = mlxsw_sp_lag_init(mlxsw_sp);
4822         if (err) {
4823                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
4824                 goto err_lag_init;
4825         }
4826
4827         /* Initialize SPAN before router and switchdev, so that those components
4828          * can call mlxsw_sp_span_respin().
4829          */
4830         err = mlxsw_sp_span_init(mlxsw_sp);
4831         if (err) {
4832                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4833                 goto err_span_init;
4834         }
4835
4836         err = mlxsw_sp_switchdev_init(mlxsw_sp);
4837         if (err) {
4838                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
4839                 goto err_switchdev_init;
4840         }
4841
4842         err = mlxsw_sp_counter_pool_init(mlxsw_sp);
4843         if (err) {
4844                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
4845                 goto err_counter_pool_init;
4846         }
4847
4848         err = mlxsw_sp_afa_init(mlxsw_sp);
4849         if (err) {
4850                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
4851                 goto err_afa_init;
4852         }
4853
4854         err = mlxsw_sp_nve_init(mlxsw_sp);
4855         if (err) {
4856                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
4857                 goto err_nve_init;
4858         }
4859
4860         err = mlxsw_sp_acl_init(mlxsw_sp);
4861         if (err) {
4862                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4863                 goto err_acl_init;
4864         }
4865
4866         err = mlxsw_sp_router_init(mlxsw_sp, extack);
4867         if (err) {
4868                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4869                 goto err_router_init;
4870         }
4871
4872         if (mlxsw_sp->bus_info->read_frc_capable) {
4873                 /* NULL is a valid return value from clock_init */
4874                 mlxsw_sp->clock =
4875                         mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
4876                                                       mlxsw_sp->bus_info->dev);
4877                 if (IS_ERR(mlxsw_sp->clock)) {
4878                         err = PTR_ERR(mlxsw_sp->clock);
4879                         dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
4880                         goto err_ptp_clock_init;
4881                 }
4882         }
4883
4884         if (mlxsw_sp->clock) {
4885                 /* NULL is a valid return value from ptp_ops->init */
4886                 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
4887                 if (IS_ERR(mlxsw_sp->ptp_state)) {
4888                         err = PTR_ERR(mlxsw_sp->ptp_state);
4889                         dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
4890                         goto err_ptp_init;
4891                 }
4892         }
4893
4894         /* Initialize netdevice notifier after router and SPAN is initialized,
4895          * so that the event handler can use router structures and call SPAN
4896          * respin.
4897          */
4898         mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4899         err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
4900                                               &mlxsw_sp->netdevice_nb);
4901         if (err) {
4902                 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4903                 goto err_netdev_notifier;
4904         }
4905
4906         err = mlxsw_sp_dpipe_init(mlxsw_sp);
4907         if (err) {
4908                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4909                 goto err_dpipe_init;
4910         }
4911
4912         err = mlxsw_sp_ports_create(mlxsw_sp);
4913         if (err) {
4914                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4915                 goto err_ports_create;
4916         }
4917
4918         return 0;
4919
4920 err_ports_create:
4921         mlxsw_sp_dpipe_fini(mlxsw_sp);
4922 err_dpipe_init:
4923         unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
4924                                           &mlxsw_sp->netdevice_nb);
4925 err_netdev_notifier:
4926         if (mlxsw_sp->clock)
4927                 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4928 err_ptp_init:
4929         if (mlxsw_sp->clock)
4930                 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
4931 err_ptp_clock_init:
4932         mlxsw_sp_router_fini(mlxsw_sp);
4933 err_router_init:
4934         mlxsw_sp_acl_fini(mlxsw_sp);
4935 err_acl_init:
4936         mlxsw_sp_nve_fini(mlxsw_sp);
4937 err_nve_init:
4938         mlxsw_sp_afa_fini(mlxsw_sp);
4939 err_afa_init:
4940         mlxsw_sp_counter_pool_fini(mlxsw_sp);
4941 err_counter_pool_init:
4942         mlxsw_sp_switchdev_fini(mlxsw_sp);
4943 err_switchdev_init:
4944         mlxsw_sp_span_fini(mlxsw_sp);
4945 err_span_init:
4946         mlxsw_sp_lag_fini(mlxsw_sp);
4947 err_lag_init:
4948         mlxsw_sp_buffers_fini(mlxsw_sp);
4949 err_buffers_init:
4950         mlxsw_sp_devlink_traps_fini(mlxsw_sp);
4951 err_devlink_traps_init:
4952         mlxsw_sp_traps_fini(mlxsw_sp);
4953 err_traps_init:
4954         mlxsw_sp_fids_fini(mlxsw_sp);
4955 err_fids_init:
4956         mlxsw_sp_kvdl_fini(mlxsw_sp);
4957         return err;
4958 }
4959
4960 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
4961                           const struct mlxsw_bus_info *mlxsw_bus_info,
4962                           struct netlink_ext_ack *extack)
4963 {
4964         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4965
4966         mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
4967         mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
4968         mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
4969         mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
4970         mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
4971         mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
4972         mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
4973         mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
4974         mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
4975         mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr;
4976         mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
4977         mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
4978         mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
4979         mlxsw_sp->listeners = mlxsw_sp1_listener;
4980         mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
4981
4982         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
4983 }
4984
4985 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
4986                           const struct mlxsw_bus_info *mlxsw_bus_info,
4987                           struct netlink_ext_ack *extack)
4988 {
4989         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4990
4991         mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
4992         mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
4993         mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
4994         mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
4995         mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
4996         mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
4997         mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
4998         mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
4999         mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
5000         mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
5001         mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
5002
5003         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
5004 }
5005
5006 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
5007 {
5008         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5009
5010         mlxsw_sp_ports_remove(mlxsw_sp);
5011         mlxsw_sp_dpipe_fini(mlxsw_sp);
5012         unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
5013                                           &mlxsw_sp->netdevice_nb);
5014         if (mlxsw_sp->clock) {
5015                 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
5016                 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
5017         }
5018         mlxsw_sp_router_fini(mlxsw_sp);
5019         mlxsw_sp_acl_fini(mlxsw_sp);
5020         mlxsw_sp_nve_fini(mlxsw_sp);
5021         mlxsw_sp_afa_fini(mlxsw_sp);
5022         mlxsw_sp_counter_pool_fini(mlxsw_sp);
5023         mlxsw_sp_switchdev_fini(mlxsw_sp);
5024         mlxsw_sp_span_fini(mlxsw_sp);
5025         mlxsw_sp_lag_fini(mlxsw_sp);
5026         mlxsw_sp_buffers_fini(mlxsw_sp);
5027         mlxsw_sp_devlink_traps_fini(mlxsw_sp);
5028         mlxsw_sp_traps_fini(mlxsw_sp);
5029         mlxsw_sp_fids_fini(mlxsw_sp);
5030         mlxsw_sp_kvdl_fini(mlxsw_sp);
5031 }
5032
5033 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
5034  * 802.1Q FIDs
5035  */
5036 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE   (MLXSW_SP_FID_8021D_MAX + \
5037                                          VLAN_VID_MASK - 1)
5038
5039 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
5040         .used_max_mid                   = 1,
5041         .max_mid                        = MLXSW_SP_MID_MAX,
5042         .used_flood_tables              = 1,
5043         .used_flood_mode                = 1,
5044         .flood_mode                     = 3,
5045         .max_fid_flood_tables           = 3,
5046         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5047         .used_max_ib_mc                 = 1,
5048         .max_ib_mc                      = 0,
5049         .used_max_pkey                  = 1,
5050         .max_pkey                       = 0,
5051         .used_kvd_sizes                 = 1,
5052         .kvd_hash_single_parts          = 59,
5053         .kvd_hash_double_parts          = 41,
5054         .kvd_linear_size                = MLXSW_SP_KVD_LINEAR_SIZE,
5055         .swid_config                    = {
5056                 {
5057                         .used_type      = 1,
5058                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
5059                 }
5060         },
5061 };
5062
5063 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
5064         .used_max_mid                   = 1,
5065         .max_mid                        = MLXSW_SP_MID_MAX,
5066         .used_flood_tables              = 1,
5067         .used_flood_mode                = 1,
5068         .flood_mode                     = 3,
5069         .max_fid_flood_tables           = 3,
5070         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5071         .used_max_ib_mc                 = 1,
5072         .max_ib_mc                      = 0,
5073         .used_max_pkey                  = 1,
5074         .max_pkey                       = 0,
5075         .swid_config                    = {
5076                 {
5077                         .used_type      = 1,
5078                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
5079                 }
5080         },
5081 };
5082
5083 static void
5084 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
5085                                       struct devlink_resource_size_params *kvd_size_params,
5086                                       struct devlink_resource_size_params *linear_size_params,
5087                                       struct devlink_resource_size_params *hash_double_size_params,
5088                                       struct devlink_resource_size_params *hash_single_size_params)
5089 {
5090         u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5091                                                  KVD_SINGLE_MIN_SIZE);
5092         u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5093                                                  KVD_DOUBLE_MIN_SIZE);
5094         u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5095         u32 linear_size_min = 0;
5096
5097         devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
5098                                           MLXSW_SP_KVD_GRANULARITY,
5099                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5100         devlink_resource_size_params_init(linear_size_params, linear_size_min,
5101                                           kvd_size - single_size_min -
5102                                           double_size_min,
5103                                           MLXSW_SP_KVD_GRANULARITY,
5104                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5105         devlink_resource_size_params_init(hash_double_size_params,
5106                                           double_size_min,
5107                                           kvd_size - single_size_min -
5108                                           linear_size_min,
5109                                           MLXSW_SP_KVD_GRANULARITY,
5110                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5111         devlink_resource_size_params_init(hash_single_size_params,
5112                                           single_size_min,
5113                                           kvd_size - double_size_min -
5114                                           linear_size_min,
5115                                           MLXSW_SP_KVD_GRANULARITY,
5116                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5117 }
5118
5119 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5120 {
5121         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5122         struct devlink_resource_size_params hash_single_size_params;
5123         struct devlink_resource_size_params hash_double_size_params;
5124         struct devlink_resource_size_params linear_size_params;
5125         struct devlink_resource_size_params kvd_size_params;
5126         u32 kvd_size, single_size, double_size, linear_size;
5127         const struct mlxsw_config_profile *profile;
5128         int err;
5129
5130         profile = &mlxsw_sp1_config_profile;
5131         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5132                 return -EIO;
5133
5134         mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
5135                                               &linear_size_params,
5136                                               &hash_double_size_params,
5137                                               &hash_single_size_params);
5138
5139         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5140         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5141                                         kvd_size, MLXSW_SP_RESOURCE_KVD,
5142                                         DEVLINK_RESOURCE_ID_PARENT_TOP,
5143                                         &kvd_size_params);
5144         if (err)
5145                 return err;
5146
5147         linear_size = profile->kvd_linear_size;
5148         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
5149                                         linear_size,
5150                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
5151                                         MLXSW_SP_RESOURCE_KVD,
5152                                         &linear_size_params);
5153         if (err)
5154                 return err;
5155
5156         err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
5157         if  (err)
5158                 return err;
5159
5160         double_size = kvd_size - linear_size;
5161         double_size *= profile->kvd_hash_double_parts;
5162         double_size /= profile->kvd_hash_double_parts +
5163                        profile->kvd_hash_single_parts;
5164         double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
5165         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
5166                                         double_size,
5167                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5168                                         MLXSW_SP_RESOURCE_KVD,
5169                                         &hash_double_size_params);
5170         if (err)
5171                 return err;
5172
5173         single_size = kvd_size - double_size - linear_size;
5174         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
5175                                         single_size,
5176                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5177                                         MLXSW_SP_RESOURCE_KVD,
5178                                         &hash_single_size_params);
5179         if (err)
5180                 return err;
5181
5182         return 0;
5183 }
5184
5185 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5186 {
5187         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5188         struct devlink_resource_size_params kvd_size_params;
5189         u32 kvd_size;
5190
5191         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5192                 return -EIO;
5193
5194         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5195         devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
5196                                           MLXSW_SP_KVD_GRANULARITY,
5197                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5198
5199         return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5200                                          kvd_size, MLXSW_SP_RESOURCE_KVD,
5201                                          DEVLINK_RESOURCE_ID_PARENT_TOP,
5202                                          &kvd_size_params);
5203 }
5204
5205 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
5206 {
5207         return mlxsw_sp1_resources_kvd_register(mlxsw_core);
5208 }
5209
5210 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
5211 {
5212         return mlxsw_sp2_resources_kvd_register(mlxsw_core);
5213 }
5214
5215 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
5216                                   const struct mlxsw_config_profile *profile,
5217                                   u64 *p_single_size, u64 *p_double_size,
5218                                   u64 *p_linear_size)
5219 {
5220         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5221         u32 double_size;
5222         int err;
5223
5224         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5225             !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
5226                 return -EIO;
5227
5228         /* The hash part is what left of the kvd without the
5229          * linear part. It is split to the single size and
5230          * double size by the parts ratio from the profile.
5231          * Both sizes must be a multiplications of the
5232          * granularity from the profile. In case the user
5233          * provided the sizes they are obtained via devlink.
5234          */
5235         err = devlink_resource_size_get(devlink,
5236                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
5237                                         p_linear_size);
5238         if (err)
5239                 *p_linear_size = profile->kvd_linear_size;
5240
5241         err = devlink_resource_size_get(devlink,
5242                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5243                                         p_double_size);
5244         if (err) {
5245                 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5246                               *p_linear_size;
5247                 double_size *= profile->kvd_hash_double_parts;
5248                 double_size /= profile->kvd_hash_double_parts +
5249                                profile->kvd_hash_single_parts;
5250                 *p_double_size = rounddown(double_size,
5251                                            MLXSW_SP_KVD_GRANULARITY);
5252         }
5253
5254         err = devlink_resource_size_get(devlink,
5255                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5256                                         p_single_size);
5257         if (err)
5258                 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5259                                  *p_double_size - *p_linear_size;
5260
5261         /* Check results are legal. */
5262         if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5263             *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
5264             MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
5265                 return -EIO;
5266
5267         return 0;
5268 }
5269
5270 static int
5271 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
5272                                                union devlink_param_value val,
5273                                                struct netlink_ext_ack *extack)
5274 {
5275         if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) &&
5276             (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) {
5277                 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
5278                 return -EINVAL;
5279         }
5280
5281         return 0;
5282 }
5283
5284 static const struct devlink_param mlxsw_sp_devlink_params[] = {
5285         DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY,
5286                               BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
5287                               NULL, NULL,
5288                               mlxsw_sp_devlink_param_fw_load_policy_validate),
5289 };
5290
5291 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core)
5292 {
5293         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5294         union devlink_param_value value;
5295         int err;
5296
5297         err = devlink_params_register(devlink, mlxsw_sp_devlink_params,
5298                                       ARRAY_SIZE(mlxsw_sp_devlink_params));
5299         if (err)
5300                 return err;
5301
5302         value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
5303         devlink_param_driverinit_value_set(devlink,
5304                                            DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
5305                                            value);
5306         return 0;
5307 }
5308
5309 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core)
5310 {
5311         devlink_params_unregister(priv_to_devlink(mlxsw_core),
5312                                   mlxsw_sp_devlink_params,
5313                                   ARRAY_SIZE(mlxsw_sp_devlink_params));
5314 }
5315
5316 static int
5317 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
5318                                              struct devlink_param_gset_ctx *ctx)
5319 {
5320         struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5321         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5322
5323         ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
5324         return 0;
5325 }
5326
5327 static int
5328 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
5329                                              struct devlink_param_gset_ctx *ctx)
5330 {
5331         struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5332         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5333
5334         return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
5335 }
5336
5337 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
5338         DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5339                              "acl_region_rehash_interval",
5340                              DEVLINK_PARAM_TYPE_U32,
5341                              BIT(DEVLINK_PARAM_CMODE_RUNTIME),
5342                              mlxsw_sp_params_acl_region_rehash_intrvl_get,
5343                              mlxsw_sp_params_acl_region_rehash_intrvl_set,
5344                              NULL),
5345 };
5346
5347 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
5348 {
5349         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5350         union devlink_param_value value;
5351         int err;
5352
5353         err = mlxsw_sp_params_register(mlxsw_core);
5354         if (err)
5355                 return err;
5356
5357         err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
5358                                       ARRAY_SIZE(mlxsw_sp2_devlink_params));
5359         if (err)
5360                 goto err_devlink_params_register;
5361
5362         value.vu32 = 0;
5363         devlink_param_driverinit_value_set(devlink,
5364                                            MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5365                                            value);
5366         return 0;
5367
5368 err_devlink_params_register:
5369         mlxsw_sp_params_unregister(mlxsw_core);
5370         return err;
5371 }
5372
5373 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
5374 {
5375         devlink_params_unregister(priv_to_devlink(mlxsw_core),
5376                                   mlxsw_sp2_devlink_params,
5377                                   ARRAY_SIZE(mlxsw_sp2_devlink_params));
5378         mlxsw_sp_params_unregister(mlxsw_core);
5379 }
5380
5381 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
5382                                      struct sk_buff *skb, u8 local_port)
5383 {
5384         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5385
5386         skb_pull(skb, MLXSW_TXHDR_LEN);
5387         mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
5388 }
5389
5390 static struct mlxsw_driver mlxsw_sp1_driver = {
5391         .kind                           = mlxsw_sp1_driver_name,
5392         .priv_size                      = sizeof(struct mlxsw_sp),
5393         .init                           = mlxsw_sp1_init,
5394         .fini                           = mlxsw_sp_fini,
5395         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
5396         .port_split                     = mlxsw_sp_port_split,
5397         .port_unsplit                   = mlxsw_sp_port_unsplit,
5398         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
5399         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
5400         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
5401         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
5402         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
5403         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
5404         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
5405         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
5406         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
5407         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
5408         .flash_update                   = mlxsw_sp_flash_update,
5409         .trap_init                      = mlxsw_sp_trap_init,
5410         .trap_fini                      = mlxsw_sp_trap_fini,
5411         .trap_action_set                = mlxsw_sp_trap_action_set,
5412         .trap_group_init                = mlxsw_sp_trap_group_init,
5413         .txhdr_construct                = mlxsw_sp_txhdr_construct,
5414         .resources_register             = mlxsw_sp1_resources_register,
5415         .kvd_sizes_get                  = mlxsw_sp_kvd_sizes_get,
5416         .params_register                = mlxsw_sp_params_register,
5417         .params_unregister              = mlxsw_sp_params_unregister,
5418         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
5419         .txhdr_len                      = MLXSW_TXHDR_LEN,
5420         .profile                        = &mlxsw_sp1_config_profile,
5421         .res_query_enabled              = true,
5422 };
5423
5424 static struct mlxsw_driver mlxsw_sp2_driver = {
5425         .kind                           = mlxsw_sp2_driver_name,
5426         .priv_size                      = sizeof(struct mlxsw_sp),
5427         .init                           = mlxsw_sp2_init,
5428         .fini                           = mlxsw_sp_fini,
5429         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
5430         .port_split                     = mlxsw_sp_port_split,
5431         .port_unsplit                   = mlxsw_sp_port_unsplit,
5432         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
5433         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
5434         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
5435         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
5436         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
5437         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
5438         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
5439         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
5440         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
5441         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
5442         .flash_update                   = mlxsw_sp_flash_update,
5443         .trap_init                      = mlxsw_sp_trap_init,
5444         .trap_fini                      = mlxsw_sp_trap_fini,
5445         .trap_action_set                = mlxsw_sp_trap_action_set,
5446         .trap_group_init                = mlxsw_sp_trap_group_init,
5447         .txhdr_construct                = mlxsw_sp_txhdr_construct,
5448         .resources_register             = mlxsw_sp2_resources_register,
5449         .params_register                = mlxsw_sp2_params_register,
5450         .params_unregister              = mlxsw_sp2_params_unregister,
5451         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
5452         .txhdr_len                      = MLXSW_TXHDR_LEN,
5453         .profile                        = &mlxsw_sp2_config_profile,
5454         .res_query_enabled              = true,
5455 };
5456
5457 static struct mlxsw_driver mlxsw_sp3_driver = {
5458         .kind                           = mlxsw_sp3_driver_name,
5459         .priv_size                      = sizeof(struct mlxsw_sp),
5460         .init                           = mlxsw_sp2_init,
5461         .fini                           = mlxsw_sp_fini,
5462         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
5463         .port_split                     = mlxsw_sp_port_split,
5464         .port_unsplit                   = mlxsw_sp_port_unsplit,
5465         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
5466         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
5467         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
5468         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
5469         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
5470         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
5471         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
5472         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
5473         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
5474         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
5475         .flash_update                   = mlxsw_sp_flash_update,
5476         .trap_init                      = mlxsw_sp_trap_init,
5477         .trap_fini                      = mlxsw_sp_trap_fini,
5478         .trap_action_set                = mlxsw_sp_trap_action_set,
5479         .trap_group_init                = mlxsw_sp_trap_group_init,
5480         .txhdr_construct                = mlxsw_sp_txhdr_construct,
5481         .resources_register             = mlxsw_sp2_resources_register,
5482         .params_register                = mlxsw_sp2_params_register,
5483         .params_unregister              = mlxsw_sp2_params_unregister,
5484         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
5485         .txhdr_len                      = MLXSW_TXHDR_LEN,
5486         .profile                        = &mlxsw_sp2_config_profile,
5487         .res_query_enabled              = true,
5488 };
5489
5490 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
5491 {
5492         return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
5493 }
5494
5495 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
5496 {
5497         struct mlxsw_sp_port **p_mlxsw_sp_port = data;
5498         int ret = 0;
5499
5500         if (mlxsw_sp_port_dev_check(lower_dev)) {
5501                 *p_mlxsw_sp_port = netdev_priv(lower_dev);
5502                 ret = 1;
5503         }
5504
5505         return ret;
5506 }
5507
5508 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
5509 {
5510         struct mlxsw_sp_port *mlxsw_sp_port;
5511
5512         if (mlxsw_sp_port_dev_check(dev))
5513                 return netdev_priv(dev);
5514
5515         mlxsw_sp_port = NULL;
5516         netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
5517
5518         return mlxsw_sp_port;
5519 }
5520
5521 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
5522 {
5523         struct mlxsw_sp_port *mlxsw_sp_port;
5524
5525         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
5526         return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
5527 }
5528
5529 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
5530 {
5531         struct mlxsw_sp_port *mlxsw_sp_port;
5532
5533         if (mlxsw_sp_port_dev_check(dev))
5534                 return netdev_priv(dev);
5535
5536         mlxsw_sp_port = NULL;
5537         netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
5538                                       &mlxsw_sp_port);
5539
5540         return mlxsw_sp_port;
5541 }
5542
5543 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
5544 {
5545         struct mlxsw_sp_port *mlxsw_sp_port;
5546
5547         rcu_read_lock();
5548         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
5549         if (mlxsw_sp_port)
5550                 dev_hold(mlxsw_sp_port->dev);
5551         rcu_read_unlock();
5552         return mlxsw_sp_port;
5553 }
5554
5555 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
5556 {
5557         dev_put(mlxsw_sp_port->dev);
5558 }
5559
5560 static void
5561 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
5562                                  struct net_device *lag_dev)
5563 {
5564         struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
5565         struct net_device *upper_dev;
5566         struct list_head *iter;
5567
5568         if (netif_is_bridge_port(lag_dev))
5569                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
5570
5571         netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
5572                 if (!netif_is_bridge_port(upper_dev))
5573                         continue;
5574                 br_dev = netdev_master_upper_dev_get(upper_dev);
5575                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
5576         }
5577 }
5578
5579 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5580 {
5581         char sldr_pl[MLXSW_REG_SLDR_LEN];
5582
5583         mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
5584         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5585 }
5586
5587 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5588 {
5589         char sldr_pl[MLXSW_REG_SLDR_LEN];
5590
5591         mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
5592         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5593 }
5594
5595 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5596                                      u16 lag_id, u8 port_index)
5597 {
5598         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5599         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5600
5601         mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
5602                                       lag_id, port_index);
5603         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5604 }
5605
5606 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5607                                         u16 lag_id)
5608 {
5609         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5610         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5611
5612         mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
5613                                          lag_id);
5614         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5615 }
5616
5617 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
5618                                         u16 lag_id)
5619 {
5620         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5621         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5622
5623         mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
5624                                         lag_id);
5625         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5626 }
5627
5628 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
5629                                          u16 lag_id)
5630 {
5631         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5632         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5633
5634         mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
5635                                          lag_id);
5636         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5637 }
5638
5639 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5640                                   struct net_device *lag_dev,
5641                                   u16 *p_lag_id)
5642 {
5643         struct mlxsw_sp_upper *lag;
5644         int free_lag_id = -1;
5645         u64 max_lag;
5646         int i;
5647
5648         max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
5649         for (i = 0; i < max_lag; i++) {
5650                 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
5651                 if (lag->ref_count) {
5652                         if (lag->dev == lag_dev) {
5653                                 *p_lag_id = i;
5654                                 return 0;
5655                         }
5656                 } else if (free_lag_id < 0) {
5657                         free_lag_id = i;
5658                 }
5659         }
5660         if (free_lag_id < 0)
5661                 return -EBUSY;
5662         *p_lag_id = free_lag_id;
5663         return 0;
5664 }
5665
5666 static bool
5667 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
5668                           struct net_device *lag_dev,
5669                           struct netdev_lag_upper_info *lag_upper_info,
5670                           struct netlink_ext_ack *extack)
5671 {
5672         u16 lag_id;
5673
5674         if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
5675                 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
5676                 return false;
5677         }
5678         if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
5679                 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
5680                 return false;
5681         }
5682         return true;
5683 }
5684
5685 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5686                                        u16 lag_id, u8 *p_port_index)
5687 {
5688         u64 max_lag_members;
5689         int i;
5690
5691         max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
5692                                              MAX_LAG_MEMBERS);
5693         for (i = 0; i < max_lag_members; i++) {
5694                 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
5695                         *p_port_index = i;
5696                         return 0;
5697                 }
5698         }
5699         return -EBUSY;
5700 }
5701
5702 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
5703                                   struct net_device *lag_dev)
5704 {
5705         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5706         struct mlxsw_sp_upper *lag;
5707         u16 lag_id;
5708         u8 port_index;
5709         int err;
5710
5711         err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
5712         if (err)
5713                 return err;
5714         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5715         if (!lag->ref_count) {
5716                 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
5717                 if (err)
5718                         return err;
5719                 lag->dev = lag_dev;
5720         }
5721
5722         err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
5723         if (err)
5724                 return err;
5725         err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
5726         if (err)
5727                 goto err_col_port_add;
5728
5729         mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
5730                                    mlxsw_sp_port->local_port);
5731         mlxsw_sp_port->lag_id = lag_id;
5732         mlxsw_sp_port->lagged = 1;
5733         lag->ref_count++;
5734
5735         /* Port is no longer usable as a router interface */
5736         if (mlxsw_sp_port->default_vlan->fid)
5737                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
5738
5739         return 0;
5740
5741 err_col_port_add:
5742         if (!lag->ref_count)
5743                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5744         return err;
5745 }
5746
5747 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
5748                                     struct net_device *lag_dev)
5749 {
5750         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5751         u16 lag_id = mlxsw_sp_port->lag_id;
5752         struct mlxsw_sp_upper *lag;
5753
5754         if (!mlxsw_sp_port->lagged)
5755                 return;
5756         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5757         WARN_ON(lag->ref_count == 0);
5758
5759         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
5760
5761         /* Any VLANs configured on the port are no longer valid */
5762         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
5763         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
5764         /* Make the LAG and its directly linked uppers leave bridges they
5765          * are memeber in
5766          */
5767         mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
5768
5769         if (lag->ref_count == 1)
5770                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5771
5772         mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
5773                                      mlxsw_sp_port->local_port);
5774         mlxsw_sp_port->lagged = 0;
5775         lag->ref_count--;
5776
5777         /* Make sure untagged frames are allowed to ingress */
5778         mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
5779 }
5780
5781 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5782                                       u16 lag_id)
5783 {
5784         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5785         char sldr_pl[MLXSW_REG_SLDR_LEN];
5786
5787         mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
5788                                          mlxsw_sp_port->local_port);
5789         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5790 }
5791
5792 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5793                                          u16 lag_id)
5794 {
5795         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5796         char sldr_pl[MLXSW_REG_SLDR_LEN];
5797
5798         mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
5799                                             mlxsw_sp_port->local_port);
5800         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5801 }
5802
5803 static int
5804 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
5805 {
5806         int err;
5807
5808         err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
5809                                            mlxsw_sp_port->lag_id);
5810         if (err)
5811                 return err;
5812
5813         err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5814         if (err)
5815                 goto err_dist_port_add;
5816
5817         return 0;
5818
5819 err_dist_port_add:
5820         mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5821         return err;
5822 }
5823
5824 static int
5825 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
5826 {
5827         int err;
5828
5829         err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
5830                                             mlxsw_sp_port->lag_id);
5831         if (err)
5832                 return err;
5833
5834         err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
5835                                             mlxsw_sp_port->lag_id);
5836         if (err)
5837                 goto err_col_port_disable;
5838
5839         return 0;
5840
5841 err_col_port_disable:
5842         mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5843         return err;
5844 }
5845
5846 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
5847                                      struct netdev_lag_lower_state_info *info)
5848 {
5849         if (info->tx_enabled)
5850                 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
5851         else
5852                 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
5853 }
5854
5855 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
5856                                  bool enable)
5857 {
5858         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5859         enum mlxsw_reg_spms_state spms_state;
5860         char *spms_pl;
5861         u16 vid;
5862         int err;
5863
5864         spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
5865                               MLXSW_REG_SPMS_STATE_DISCARDING;
5866
5867         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
5868         if (!spms_pl)
5869                 return -ENOMEM;
5870         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
5871
5872         for (vid = 0; vid < VLAN_N_VID; vid++)
5873                 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
5874
5875         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
5876         kfree(spms_pl);
5877         return err;
5878 }
5879
5880 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
5881 {
5882         u16 vid = 1;
5883         int err;
5884
5885         err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
5886         if (err)
5887                 return err;
5888         err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
5889         if (err)
5890                 goto err_port_stp_set;
5891         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5892                                      true, false);
5893         if (err)
5894                 goto err_port_vlan_set;
5895
5896         for (; vid <= VLAN_N_VID - 1; vid++) {
5897                 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5898                                                      vid, false);
5899                 if (err)
5900                         goto err_vid_learning_set;
5901         }
5902
5903         return 0;
5904
5905 err_vid_learning_set:
5906         for (vid--; vid >= 1; vid--)
5907                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
5908 err_port_vlan_set:
5909         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5910 err_port_stp_set:
5911         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5912         return err;
5913 }
5914
5915 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
5916 {
5917         u16 vid;
5918
5919         for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
5920                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5921                                                vid, true);
5922
5923         mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5924                                false, false);
5925         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5926         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5927 }
5928
5929 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
5930 {
5931         unsigned int num_vxlans = 0;
5932         struct net_device *dev;
5933         struct list_head *iter;
5934
5935         netdev_for_each_lower_dev(br_dev, dev, iter) {
5936                 if (netif_is_vxlan(dev))
5937                         num_vxlans++;
5938         }
5939
5940         return num_vxlans > 1;
5941 }
5942
5943 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
5944 {
5945         DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
5946         struct net_device *dev;
5947         struct list_head *iter;
5948
5949         netdev_for_each_lower_dev(br_dev, dev, iter) {
5950                 u16 pvid;
5951                 int err;
5952
5953                 if (!netif_is_vxlan(dev))
5954                         continue;
5955
5956                 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
5957                 if (err || !pvid)
5958                         continue;
5959
5960                 if (test_and_set_bit(pvid, vlans))
5961                         return false;
5962         }
5963
5964         return true;
5965 }
5966
5967 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
5968                                            struct netlink_ext_ack *extack)
5969 {
5970         if (br_multicast_enabled(br_dev)) {
5971                 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
5972                 return false;
5973         }
5974
5975         if (!br_vlan_enabled(br_dev) &&
5976             mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
5977                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
5978                 return false;
5979         }
5980
5981         if (br_vlan_enabled(br_dev) &&
5982             !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
5983                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
5984                 return false;
5985         }
5986
5987         return true;
5988 }
5989
5990 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
5991                                                struct net_device *dev,
5992                                                unsigned long event, void *ptr)
5993 {
5994         struct netdev_notifier_changeupper_info *info;
5995         struct mlxsw_sp_port *mlxsw_sp_port;
5996         struct netlink_ext_ack *extack;
5997         struct net_device *upper_dev;
5998         struct mlxsw_sp *mlxsw_sp;
5999         int err = 0;
6000
6001         mlxsw_sp_port = netdev_priv(dev);
6002         mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6003         info = ptr;
6004         extack = netdev_notifier_info_to_extack(&info->info);
6005
6006         switch (event) {
6007         case NETDEV_PRECHANGEUPPER:
6008                 upper_dev = info->upper_dev;
6009                 if (!is_vlan_dev(upper_dev) &&
6010                     !netif_is_lag_master(upper_dev) &&
6011                     !netif_is_bridge_master(upper_dev) &&
6012                     !netif_is_ovs_master(upper_dev) &&
6013                     !netif_is_macvlan(upper_dev)) {
6014                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6015                         return -EINVAL;
6016                 }
6017                 if (!info->linking)
6018                         break;
6019                 if (netif_is_bridge_master(upper_dev) &&
6020                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6021                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6022                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6023                         return -EOPNOTSUPP;
6024                 if (netdev_has_any_upper_dev(upper_dev) &&
6025                     (!netif_is_bridge_master(upper_dev) ||
6026                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6027                                                           upper_dev))) {
6028                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6029                         return -EINVAL;
6030                 }
6031                 if (netif_is_lag_master(upper_dev) &&
6032                     !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
6033                                                info->upper_info, extack))
6034                         return -EINVAL;
6035                 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
6036                         NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
6037                         return -EINVAL;
6038                 }
6039                 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
6040                     !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
6041                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
6042                         return -EINVAL;
6043                 }
6044                 if (netif_is_macvlan(upper_dev) &&
6045                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
6046                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6047                         return -EOPNOTSUPP;
6048                 }
6049                 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
6050                         NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
6051                         return -EINVAL;
6052                 }
6053                 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
6054                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
6055                         return -EINVAL;
6056                 }
6057                 break;
6058         case NETDEV_CHANGEUPPER:
6059                 upper_dev = info->upper_dev;
6060                 if (netif_is_bridge_master(upper_dev)) {
6061                         if (info->linking)
6062                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6063                                                                 lower_dev,
6064                                                                 upper_dev,
6065                                                                 extack);
6066                         else
6067                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6068                                                            lower_dev,
6069                                                            upper_dev);
6070                 } else if (netif_is_lag_master(upper_dev)) {
6071                         if (info->linking) {
6072                                 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
6073                                                              upper_dev);
6074                         } else {
6075                                 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
6076                                 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
6077                                                         upper_dev);
6078                         }
6079                 } else if (netif_is_ovs_master(upper_dev)) {
6080                         if (info->linking)
6081                                 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
6082                         else
6083                                 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
6084                 } else if (netif_is_macvlan(upper_dev)) {
6085                         if (!info->linking)
6086                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6087                 } else if (is_vlan_dev(upper_dev)) {
6088                         struct net_device *br_dev;
6089
6090                         if (!netif_is_bridge_port(upper_dev))
6091                                 break;
6092                         if (info->linking)
6093                                 break;
6094                         br_dev = netdev_master_upper_dev_get(upper_dev);
6095                         mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
6096                                                    br_dev);
6097                 }
6098                 break;
6099         }
6100
6101         return err;
6102 }
6103
6104 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
6105                                                unsigned long event, void *ptr)
6106 {
6107         struct netdev_notifier_changelowerstate_info *info;
6108         struct mlxsw_sp_port *mlxsw_sp_port;
6109         int err;
6110
6111         mlxsw_sp_port = netdev_priv(dev);
6112         info = ptr;
6113
6114         switch (event) {
6115         case NETDEV_CHANGELOWERSTATE:
6116                 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
6117                         err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
6118                                                         info->lower_state_info);
6119                         if (err)
6120                                 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
6121                 }
6122                 break;
6123         }
6124
6125         return 0;
6126 }
6127
6128 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
6129                                          struct net_device *port_dev,
6130                                          unsigned long event, void *ptr)
6131 {
6132         switch (event) {
6133         case NETDEV_PRECHANGEUPPER:
6134         case NETDEV_CHANGEUPPER:
6135                 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
6136                                                            event, ptr);
6137         case NETDEV_CHANGELOWERSTATE:
6138                 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
6139                                                            ptr);
6140         }
6141
6142         return 0;
6143 }
6144
6145 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
6146                                         unsigned long event, void *ptr)
6147 {
6148         struct net_device *dev;
6149         struct list_head *iter;
6150         int ret;
6151
6152         netdev_for_each_lower_dev(lag_dev, dev, iter) {
6153                 if (mlxsw_sp_port_dev_check(dev)) {
6154                         ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
6155                                                             ptr);
6156                         if (ret)
6157                                 return ret;
6158                 }
6159         }
6160
6161         return 0;
6162 }
6163
6164 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
6165                                               struct net_device *dev,
6166                                               unsigned long event, void *ptr,
6167                                               u16 vid)
6168 {
6169         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
6170         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6171         struct netdev_notifier_changeupper_info *info = ptr;
6172         struct netlink_ext_ack *extack;
6173         struct net_device *upper_dev;
6174         int err = 0;
6175
6176         extack = netdev_notifier_info_to_extack(&info->info);
6177
6178         switch (event) {
6179         case NETDEV_PRECHANGEUPPER:
6180                 upper_dev = info->upper_dev;
6181                 if (!netif_is_bridge_master(upper_dev) &&
6182                     !netif_is_macvlan(upper_dev)) {
6183                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6184                         return -EINVAL;
6185                 }
6186                 if (!info->linking)
6187                         break;
6188                 if (netif_is_bridge_master(upper_dev) &&
6189                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6190                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6191                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6192                         return -EOPNOTSUPP;
6193                 if (netdev_has_any_upper_dev(upper_dev) &&
6194                     (!netif_is_bridge_master(upper_dev) ||
6195                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6196                                                           upper_dev))) {
6197                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6198                         return -EINVAL;
6199                 }
6200                 if (netif_is_macvlan(upper_dev) &&
6201                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6202                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6203                         return -EOPNOTSUPP;
6204                 }
6205                 break;
6206         case NETDEV_CHANGEUPPER:
6207                 upper_dev = info->upper_dev;
6208                 if (netif_is_bridge_master(upper_dev)) {
6209                         if (info->linking)
6210                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6211                                                                 vlan_dev,
6212                                                                 upper_dev,
6213                                                                 extack);
6214                         else
6215                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6216                                                            vlan_dev,
6217                                                            upper_dev);
6218                 } else if (netif_is_macvlan(upper_dev)) {
6219                         if (!info->linking)
6220                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6221                 } else {
6222                         err = -EINVAL;
6223                         WARN_ON(1);
6224                 }
6225                 break;
6226         }
6227
6228         return err;
6229 }
6230
6231 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
6232                                                   struct net_device *lag_dev,
6233                                                   unsigned long event,
6234                                                   void *ptr, u16 vid)
6235 {
6236         struct net_device *dev;
6237         struct list_head *iter;
6238         int ret;
6239
6240         netdev_for_each_lower_dev(lag_dev, dev, iter) {
6241                 if (mlxsw_sp_port_dev_check(dev)) {
6242                         ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
6243                                                                  event, ptr,
6244                                                                  vid);
6245                         if (ret)
6246                                 return ret;
6247                 }
6248         }
6249
6250         return 0;
6251 }
6252
6253 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
6254                                                 struct net_device *br_dev,
6255                                                 unsigned long event, void *ptr,
6256                                                 u16 vid)
6257 {
6258         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
6259         struct netdev_notifier_changeupper_info *info = ptr;
6260         struct netlink_ext_ack *extack;
6261         struct net_device *upper_dev;
6262
6263         if (!mlxsw_sp)
6264                 return 0;
6265
6266         extack = netdev_notifier_info_to_extack(&info->info);
6267
6268         switch (event) {
6269         case NETDEV_PRECHANGEUPPER:
6270                 upper_dev = info->upper_dev;
6271                 if (!netif_is_macvlan(upper_dev)) {
6272                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6273                         return -EOPNOTSUPP;
6274                 }
6275                 if (!info->linking)
6276                         break;
6277                 if (netif_is_macvlan(upper_dev) &&
6278                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6279                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6280                         return -EOPNOTSUPP;
6281                 }
6282                 break;
6283         case NETDEV_CHANGEUPPER:
6284                 upper_dev = info->upper_dev;
6285                 if (info->linking)
6286                         break;
6287                 if (netif_is_macvlan(upper_dev))
6288                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6289                 break;
6290         }
6291
6292         return 0;
6293 }
6294
6295 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
6296                                          unsigned long event, void *ptr)
6297 {
6298         struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
6299         u16 vid = vlan_dev_vlan_id(vlan_dev);
6300
6301         if (mlxsw_sp_port_dev_check(real_dev))
6302                 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
6303                                                           event, ptr, vid);
6304         else if (netif_is_lag_master(real_dev))
6305                 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
6306                                                               real_dev, event,
6307                                                               ptr, vid);
6308         else if (netif_is_bridge_master(real_dev))
6309                 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
6310                                                             event, ptr, vid);
6311
6312         return 0;
6313 }
6314
6315 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
6316                                            unsigned long event, void *ptr)
6317 {
6318         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
6319         struct netdev_notifier_changeupper_info *info = ptr;
6320         struct netlink_ext_ack *extack;
6321         struct net_device *upper_dev;
6322
6323         if (!mlxsw_sp)
6324                 return 0;
6325
6326         extack = netdev_notifier_info_to_extack(&info->info);
6327
6328         switch (event) {
6329         case NETDEV_PRECHANGEUPPER:
6330                 upper_dev = info->upper_dev;
6331                 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
6332                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6333                         return -EOPNOTSUPP;
6334                 }
6335                 if (!info->linking)
6336                         break;
6337                 if (netif_is_macvlan(upper_dev) &&
6338                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
6339                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6340                         return -EOPNOTSUPP;
6341                 }
6342                 break;
6343         case NETDEV_CHANGEUPPER:
6344                 upper_dev = info->upper_dev;
6345                 if (info->linking)
6346                         break;
6347                 if (is_vlan_dev(upper_dev))
6348                         mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
6349                 if (netif_is_macvlan(upper_dev))
6350                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6351                 break;
6352         }
6353
6354         return 0;
6355 }
6356
6357 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
6358                                             unsigned long event, void *ptr)
6359 {
6360         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
6361         struct netdev_notifier_changeupper_info *info = ptr;
6362         struct netlink_ext_ack *extack;
6363
6364         if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
6365                 return 0;
6366
6367         extack = netdev_notifier_info_to_extack(&info->info);
6368
6369         /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
6370         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6371
6372         return -EOPNOTSUPP;
6373 }
6374
6375 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
6376 {
6377         struct netdev_notifier_changeupper_info *info = ptr;
6378
6379         if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
6380                 return false;
6381         return netif_is_l3_master(info->upper_dev);
6382 }
6383
6384 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
6385                                           struct net_device *dev,
6386                                           unsigned long event, void *ptr)
6387 {
6388         struct netdev_notifier_changeupper_info *cu_info;
6389         struct netdev_notifier_info *info = ptr;
6390         struct netlink_ext_ack *extack;
6391         struct net_device *upper_dev;
6392
6393         extack = netdev_notifier_info_to_extack(info);
6394
6395         switch (event) {
6396         case NETDEV_CHANGEUPPER:
6397                 cu_info = container_of(info,
6398                                        struct netdev_notifier_changeupper_info,
6399                                        info);
6400                 upper_dev = cu_info->upper_dev;
6401                 if (!netif_is_bridge_master(upper_dev))
6402                         return 0;
6403                 if (!mlxsw_sp_lower_get(upper_dev))
6404                         return 0;
6405                 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6406                         return -EOPNOTSUPP;
6407                 if (cu_info->linking) {
6408                         if (!netif_running(dev))
6409                                 return 0;
6410                         /* When the bridge is VLAN-aware, the VNI of the VxLAN
6411                          * device needs to be mapped to a VLAN, but at this
6412                          * point no VLANs are configured on the VxLAN device
6413                          */
6414                         if (br_vlan_enabled(upper_dev))
6415                                 return 0;
6416                         return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
6417                                                           dev, 0, extack);
6418                 } else {
6419                         /* VLANs were already flushed, which triggered the
6420                          * necessary cleanup
6421                          */
6422                         if (br_vlan_enabled(upper_dev))
6423                                 return 0;
6424                         mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6425                 }
6426                 break;
6427         case NETDEV_PRE_UP:
6428                 upper_dev = netdev_master_upper_dev_get(dev);
6429                 if (!upper_dev)
6430                         return 0;
6431                 if (!netif_is_bridge_master(upper_dev))
6432                         return 0;
6433                 if (!mlxsw_sp_lower_get(upper_dev))
6434                         return 0;
6435                 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
6436                                                   extack);
6437         case NETDEV_DOWN:
6438                 upper_dev = netdev_master_upper_dev_get(dev);
6439                 if (!upper_dev)
6440                         return 0;
6441                 if (!netif_is_bridge_master(upper_dev))
6442                         return 0;
6443                 if (!mlxsw_sp_lower_get(upper_dev))
6444                         return 0;
6445                 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6446                 break;
6447         }
6448
6449         return 0;
6450 }
6451
6452 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
6453                                     unsigned long event, void *ptr)
6454 {
6455         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6456         struct mlxsw_sp_span_entry *span_entry;
6457         struct mlxsw_sp *mlxsw_sp;
6458         int err = 0;
6459
6460         mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
6461         if (event == NETDEV_UNREGISTER) {
6462                 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
6463                 if (span_entry)
6464                         mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
6465         }
6466         mlxsw_sp_span_respin(mlxsw_sp);
6467
6468         if (netif_is_vxlan(dev))
6469                 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
6470         if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
6471                 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
6472                                                        event, ptr);
6473         else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
6474                 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
6475                                                        event, ptr);
6476         else if (event == NETDEV_PRE_CHANGEADDR ||
6477                  event == NETDEV_CHANGEADDR ||
6478                  event == NETDEV_CHANGEMTU)
6479                 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
6480         else if (mlxsw_sp_is_vrf_event(event, ptr))
6481                 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6482         else if (mlxsw_sp_port_dev_check(dev))
6483                 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
6484         else if (netif_is_lag_master(dev))
6485                 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
6486         else if (is_vlan_dev(dev))
6487                 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
6488         else if (netif_is_bridge_master(dev))
6489                 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
6490         else if (netif_is_macvlan(dev))
6491                 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
6492
6493         return notifier_from_errno(err);
6494 }
6495
6496 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
6497         .notifier_call = mlxsw_sp_inetaddr_valid_event,
6498 };
6499
6500 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
6501         .notifier_call = mlxsw_sp_inet6addr_valid_event,
6502 };
6503
6504 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
6505         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
6506         {0, },
6507 };
6508
6509 static struct pci_driver mlxsw_sp1_pci_driver = {
6510         .name = mlxsw_sp1_driver_name,
6511         .id_table = mlxsw_sp1_pci_id_table,
6512 };
6513
6514 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
6515         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
6516         {0, },
6517 };
6518
6519 static struct pci_driver mlxsw_sp2_pci_driver = {
6520         .name = mlxsw_sp2_driver_name,
6521         .id_table = mlxsw_sp2_pci_id_table,
6522 };
6523
6524 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
6525         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
6526         {0, },
6527 };
6528
6529 static struct pci_driver mlxsw_sp3_pci_driver = {
6530         .name = mlxsw_sp3_driver_name,
6531         .id_table = mlxsw_sp3_pci_id_table,
6532 };
6533
6534 static int __init mlxsw_sp_module_init(void)
6535 {
6536         int err;
6537
6538         register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6539         register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6540
6541         err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
6542         if (err)
6543                 goto err_sp1_core_driver_register;
6544
6545         err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
6546         if (err)
6547                 goto err_sp2_core_driver_register;
6548
6549         err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
6550         if (err)
6551                 goto err_sp3_core_driver_register;
6552
6553         err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
6554         if (err)
6555                 goto err_sp1_pci_driver_register;
6556
6557         err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
6558         if (err)
6559                 goto err_sp2_pci_driver_register;
6560
6561         err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
6562         if (err)
6563                 goto err_sp3_pci_driver_register;
6564
6565         return 0;
6566
6567 err_sp3_pci_driver_register:
6568         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6569 err_sp2_pci_driver_register:
6570         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6571 err_sp1_pci_driver_register:
6572         mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6573 err_sp3_core_driver_register:
6574         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6575 err_sp2_core_driver_register:
6576         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6577 err_sp1_core_driver_register:
6578         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6579         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6580         return err;
6581 }
6582
6583 static void __exit mlxsw_sp_module_exit(void)
6584 {
6585         mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
6586         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6587         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6588         mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6589         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6590         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6591         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6592         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6593 }
6594
6595 module_init(mlxsw_sp_module_init);
6596 module_exit(mlxsw_sp_module_exit);
6597
6598 MODULE_LICENSE("Dual BSD/GPL");
6599 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
6600 MODULE_DESCRIPTION("Mellanox Spectrum driver");
6601 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
6602 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
6603 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
6604 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);