drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/types.h>
   6 #include <linux/dcbnl.h>
   7 #include <linux/if_ether.h>
   8 #include <linux/list.h>
   9
  10 #include "spectrum.h"
  11 #include "core.h"
  12 #include "port.h"
  13 #include "reg.h"
  14
  15 struct mlxsw_sp_sb_pr {
  16         enum mlxsw_reg_sbpr_mode mode;
  17         u32 size;
  18 };
  19
  20 struct mlxsw_cp_sb_occ {
  21         u32 cur;
  22         u32 max;
  23 };
  24
  25 struct mlxsw_sp_sb_cm {
  26         u32 min_buff;
  27         u32 max_buff;
  28         u16 pool_index;
  29         struct mlxsw_cp_sb_occ occ;
  30 };
  31
  32 struct mlxsw_sp_sb_pm {
  33         u32 min_buff;
  34         u32 max_buff;
  35         struct mlxsw_cp_sb_occ occ;
  36 };
  37
  38 struct mlxsw_sp_sb_pool_des {
  39         enum mlxsw_reg_sbxx_dir dir;
  40         u8 pool;
  41 };
  42
  43 /* Order ingress pools before egress pools. */
  44 static const struct mlxsw_sp_sb_pool_des mlxsw_sp_sb_pool_dess[] = {
  45         {MLXSW_REG_SBXX_DIR_INGRESS, 0},
  46         {MLXSW_REG_SBXX_DIR_INGRESS, 1},
  47         {MLXSW_REG_SBXX_DIR_INGRESS, 2},
  48         {MLXSW_REG_SBXX_DIR_INGRESS, 3},
  49         {MLXSW_REG_SBXX_DIR_EGRESS, 0},
  50         {MLXSW_REG_SBXX_DIR_EGRESS, 1},
  51         {MLXSW_REG_SBXX_DIR_EGRESS, 2},
  52         {MLXSW_REG_SBXX_DIR_EGRESS, 3},
  53         {MLXSW_REG_SBXX_DIR_EGRESS, 15},
  54 };
  55
  56 #define MLXSW_SP_SB_POOL_DESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pool_dess)
  57
  58 #define MLXSW_SP_SB_TC_COUNT    8
  59
  60 struct mlxsw_sp_sb_port {
  61         struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
  62         struct mlxsw_sp_sb_pm pms[MLXSW_SP_SB_POOL_DESS_LEN];
  63 };
  64
  65 struct mlxsw_sp_sb {
  66         struct mlxsw_sp_sb_pr prs[MLXSW_SP_SB_POOL_DESS_LEN];
  67         struct mlxsw_sp_sb_port *ports;
  68         u32 cell_size;
  69 };
  70
  71 u32 mlxsw_sp_cells_bytes(const struct mlxsw_sp *mlxsw_sp, u32 cells)
  72 {
  73         return mlxsw_sp->sb->cell_size * cells;
  74 }
  75
  76 u32 mlxsw_sp_bytes_cells(const struct mlxsw_sp *mlxsw_sp, u32 bytes)
  77 {
  78         return DIV_ROUND_UP(bytes, mlxsw_sp->sb->cell_size);
  79 }
  80
  81 static struct mlxsw_sp_sb_pr *mlxsw_sp_sb_pr_get(struct mlxsw_sp *mlxsw_sp,
  82                                                  u16 pool_index)
  83 {
  84         return &mlxsw_sp->sb->prs[pool_index];
  85 }
  86
  87 static struct mlxsw_sp_sb_cm *mlxsw_sp_sb_cm_get(struct mlxsw_sp *mlxsw_sp,
  88                                                  u8 local_port, u8 pg_buff,
  89                                                  enum mlxsw_reg_sbxx_dir dir)
  90 {
  91         return &mlxsw_sp->sb->ports[local_port].cms[dir][pg_buff];
  92 }
  93
  94 static struct mlxsw_sp_sb_pm *mlxsw_sp_sb_pm_get(struct mlxsw_sp *mlxsw_sp,
  95                                                  u8 local_port, u16 pool_index)
  96 {
  97         return &mlxsw_sp->sb->ports[local_port].pms[pool_index];
  98 }
  99
 100 static int mlxsw_sp_sb_pr_write(struct mlxsw_sp *mlxsw_sp, u16 pool_index,
 101                                 enum mlxsw_reg_sbpr_mode mode, u32 size)
 102 {
 103         const struct mlxsw_sp_sb_pool_des *des =
 104                 &mlxsw_sp_sb_pool_dess[pool_index];
 105         char sbpr_pl[MLXSW_REG_SBPR_LEN];
 106         struct mlxsw_sp_sb_pr *pr;
 107         int err;
 108
 109         mlxsw_reg_sbpr_pack(sbpr_pl, des->pool, des->dir, mode, size);
 110         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
 111         if (err)
 112                 return err;
 113
 114         pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool_index);
 115         pr->mode = mode;
 116         pr->size = size;
 117         return 0;
 118 }
 119
 120 static int mlxsw_sp_sb_cm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 121                                 u8 pg_buff, u32 min_buff, u32 max_buff,
 122                                 u16 pool_index)
 123 {
 124         const struct mlxsw_sp_sb_pool_des *des =
 125                 &mlxsw_sp_sb_pool_dess[pool_index];
 126         char sbcm_pl[MLXSW_REG_SBCM_LEN];
 127         int err;
 128
 129         mlxsw_reg_sbcm_pack(sbcm_pl, local_port, pg_buff, des->dir,
 130                             min_buff, max_buff, des->pool);
 131         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
 132         if (err)
 133                 return err;
 134         if (pg_buff < MLXSW_SP_SB_TC_COUNT) {
 135                 struct mlxsw_sp_sb_cm *cm;
 136
 137                 cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, pg_buff,
 138                                         des->dir);
 139                 cm->min_buff = min_buff;
 140                 cm->max_buff = max_buff;
 141                 cm->pool_index = pool_index;
 142         }
 143         return 0;
 144 }
 145
 146 static int mlxsw_sp_sb_pm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 147                                 u16 pool_index, u32 min_buff, u32 max_buff)
 148 {
 149         const struct mlxsw_sp_sb_pool_des *des =
 150                 &mlxsw_sp_sb_pool_dess[pool_index];
 151         char sbpm_pl[MLXSW_REG_SBPM_LEN];
 152         struct mlxsw_sp_sb_pm *pm;
 153         int err;
 154
 155         mlxsw_reg_sbpm_pack(sbpm_pl, local_port, des->pool, des->dir, false,
 156                             min_buff, max_buff);
 157         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl);
 158         if (err)
 159                 return err;
 160
 161         pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool_index);
 162         pm->min_buff = min_buff;
 163         pm->max_buff = max_buff;
 164         return 0;
 165 }
 166
 167 static int mlxsw_sp_sb_pm_occ_clear(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 168                                     u16 pool_index, struct list_head *bulk_list)
 169 {
 170         const struct mlxsw_sp_sb_pool_des *des =
 171                 &mlxsw_sp_sb_pool_dess[pool_index];
 172         char sbpm_pl[MLXSW_REG_SBPM_LEN];
 173
 174         mlxsw_reg_sbpm_pack(sbpm_pl, local_port, des->pool, des->dir,
 175                             true, 0, 0);
 176         return mlxsw_reg_trans_query(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl,
 177                                      bulk_list, NULL, 0);
 178 }
 179
 180 static void mlxsw_sp_sb_pm_occ_query_cb(struct mlxsw_core *mlxsw_core,
 181                                         char *sbpm_pl, size_t sbpm_pl_len,
 182                                         unsigned long cb_priv)
 183 {
 184         struct mlxsw_sp_sb_pm *pm = (struct mlxsw_sp_sb_pm *) cb_priv;
 185
 186         mlxsw_reg_sbpm_unpack(sbpm_pl, &pm->occ.cur, &pm->occ.max);
 187 }
 188
 189 static int mlxsw_sp_sb_pm_occ_query(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 190                                     u16 pool_index, struct list_head *bulk_list)
 191 {
 192         const struct mlxsw_sp_sb_pool_des *des =
 193                 &mlxsw_sp_sb_pool_dess[pool_index];
 194         char sbpm_pl[MLXSW_REG_SBPM_LEN];
 195         struct mlxsw_sp_sb_pm *pm;
 196
 197         pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool_index);
 198         mlxsw_reg_sbpm_pack(sbpm_pl, local_port, des->pool, des->dir,
 199                             false, 0, 0);
 200         return mlxsw_reg_trans_query(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl,
 201                                      bulk_list,
 202                                      mlxsw_sp_sb_pm_occ_query_cb,
 203                                      (unsigned long) pm);
 204 }
 205
 206 static const u16 mlxsw_sp_pbs[] = {
 207         [0] = 2 * ETH_FRAME_LEN,
 208         [9] = 2 * MLXSW_PORT_MAX_MTU,
 209 };
 210
 211 #define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
 212 #define MLXSW_SP_PB_UNUSED 8
 213
 214 static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
 215 {
 216         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 217         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 218         int i;
 219
 220         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
 221                             0xffff, 0xffff / 2);
 222         for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
 223                 u16 size = mlxsw_sp_bytes_cells(mlxsw_sp, mlxsw_sp_pbs[i]);
 224
 225                 if (i == MLXSW_SP_PB_UNUSED)
 226                         continue;
 227                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, i, size);
 228         }
 229         mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl,
 230                                          MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX, 0);
 231         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 232 }
 233
 234 static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
 235 {
 236         char pptb_pl[MLXSW_REG_PPTB_LEN];
 237         int i;
 238
 239         mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
 240         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
 241                 mlxsw_reg_pptb_prio_to_buff_pack(pptb_pl, i, 0);
 242         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
 243                                pptb_pl);
 244 }
 245
 246 static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
 247 {
 248         int err;
 249
 250         err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
 251         if (err)
 252                 return err;
 253         return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
 254 }
 255
 256 static int mlxsw_sp_sb_ports_init(struct mlxsw_sp *mlxsw_sp)
 257 {
 258         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
 259
 260         mlxsw_sp->sb->ports = kcalloc(max_ports,
 261                                       sizeof(struct mlxsw_sp_sb_port),
 262                                       GFP_KERNEL);
 263         if (!mlxsw_sp->sb->ports)
 264                 return -ENOMEM;
 265         return 0;
 266 }
 267
 268 static void mlxsw_sp_sb_ports_fini(struct mlxsw_sp *mlxsw_sp)
 269 {
 270         kfree(mlxsw_sp->sb->ports);
 271 }
 272
 273 #define MLXSW_SP_SB_PR_INGRESS_SIZE     12440000
 274 #define MLXSW_SP_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
 275 #define MLXSW_SP_SB_PR_EGRESS_SIZE      13232000
 276
 277 #define MLXSW_SP_SB_PR(_mode, _size)    \
 278         {                               \
 279                 .mode = _mode,          \
 280                 .size = _size,          \
 281         }
 282
 283 static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs[] = {
 284         /* Ingress pools. */
 285         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
 286                        MLXSW_SP_SB_PR_INGRESS_SIZE),
 287         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 288         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 289         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
 290                        MLXSW_SP_SB_PR_INGRESS_MNG_SIZE),
 291         /* Egress pools. */
 292         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, MLXSW_SP_SB_PR_EGRESS_SIZE),
 293         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 294         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 295         MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
 296 };
 297
 298 #define MLXSW_SP_SB_PRS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs)
 299
 300 static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
 301                                 const struct mlxsw_sp_sb_pr *prs,
 302                                 size_t prs_len)
 303 {
 304         int i;
 305         int err;
 306
 307         for (i = 0; i < prs_len; i++) {
 308                 u32 size = mlxsw_sp_bytes_cells(mlxsw_sp, prs[i].size);
 309
 310                 err = mlxsw_sp_sb_pr_write(mlxsw_sp, i, prs[i].mode, size);
 311                 if (err)
 312                         return err;
 313         }
 314         return 0;
 315 }
 316
 317 #define MLXSW_SP_SB_CM(_min_buff, _max_buff, _pool)     \
 318         {                                               \
 319                 .min_buff = _min_buff,                  \
 320                 .max_buff = _max_buff,                  \
 321                 .pool_index = _pool,                    \
 322         }
 323
 324 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
 325         MLXSW_SP_SB_CM(10000, 8, 0),
 326         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 327         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 328         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 329         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 330         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 331         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 332         MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
 333         MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */
 334         MLXSW_SP_SB_CM(20000, 1, 3),
 335 };
 336
 337 #define MLXSW_SP_SB_CMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_ingress)
 338
 339 static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
 340         MLXSW_SP_SB_CM(1500, 9, 4),
 341         MLXSW_SP_SB_CM(1500, 9, 4),
 342         MLXSW_SP_SB_CM(1500, 9, 4),
 343         MLXSW_SP_SB_CM(1500, 9, 4),
 344         MLXSW_SP_SB_CM(1500, 9, 4),
 345         MLXSW_SP_SB_CM(1500, 9, 4),
 346         MLXSW_SP_SB_CM(1500, 9, 4),
 347         MLXSW_SP_SB_CM(1500, 9, 4),
 348         MLXSW_SP_SB_CM(0, 140000, 8),
 349         MLXSW_SP_SB_CM(0, 140000, 8),
 350         MLXSW_SP_SB_CM(0, 140000, 8),
 351         MLXSW_SP_SB_CM(0, 140000, 8),
 352         MLXSW_SP_SB_CM(0, 140000, 8),
 353         MLXSW_SP_SB_CM(0, 140000, 8),
 354         MLXSW_SP_SB_CM(0, 140000, 8),
 355         MLXSW_SP_SB_CM(0, 140000, 8),
 356         MLXSW_SP_SB_CM(1, 0xff, 4),
 357 };
 358
 359 #define MLXSW_SP_SB_CMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_egress)
 360
 361 #define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 4)
 362
 363 static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
 364         MLXSW_SP_CPU_PORT_SB_CM,
 365         MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4),
 366         MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4),
 367         MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4),
 368         MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4),
 369         MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4),
 370         MLXSW_SP_CPU_PORT_SB_CM,
 371         MLXSW_SP_SB_CM(MLXSW_PORT_MAX_MTU, 0, 4),
 372         MLXSW_SP_CPU_PORT_SB_CM,
 373         MLXSW_SP_CPU_PORT_SB_CM,
 374         MLXSW_SP_CPU_PORT_SB_CM,
 375         MLXSW_SP_CPU_PORT_SB_CM,
 376         MLXSW_SP_CPU_PORT_SB_CM,
 377         MLXSW_SP_CPU_PORT_SB_CM,
 378         MLXSW_SP_CPU_PORT_SB_CM,
 379         MLXSW_SP_CPU_PORT_SB_CM,
 380         MLXSW_SP_CPU_PORT_SB_CM,
 381         MLXSW_SP_CPU_PORT_SB_CM,
 382         MLXSW_SP_CPU_PORT_SB_CM,
 383         MLXSW_SP_CPU_PORT_SB_CM,
 384         MLXSW_SP_CPU_PORT_SB_CM,
 385         MLXSW_SP_CPU_PORT_SB_CM,
 386         MLXSW_SP_CPU_PORT_SB_CM,
 387         MLXSW_SP_CPU_PORT_SB_CM,
 388         MLXSW_SP_CPU_PORT_SB_CM,
 389         MLXSW_SP_CPU_PORT_SB_CM,
 390         MLXSW_SP_CPU_PORT_SB_CM,
 391         MLXSW_SP_CPU_PORT_SB_CM,
 392         MLXSW_SP_CPU_PORT_SB_CM,
 393         MLXSW_SP_CPU_PORT_SB_CM,
 394         MLXSW_SP_CPU_PORT_SB_CM,
 395         MLXSW_SP_CPU_PORT_SB_CM,
 396 };
 397
 398 #define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
 399         ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
 400
 401 static int __mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
 402                                   enum mlxsw_reg_sbxx_dir dir,
 403                                   const struct mlxsw_sp_sb_cm *cms,
 404                                   size_t cms_len)
 405 {
 406         int i;
 407         int err;
 408
 409         for (i = 0; i < cms_len; i++) {
 410                 const struct mlxsw_sp_sb_cm *cm;
 411                 u32 min_buff;
 412
 413                 if (i == 8 && dir == MLXSW_REG_SBXX_DIR_INGRESS)
 414                         continue; /* PG number 8 does not exist, skip it */
 415                 cm = &cms[i];
 416                 if (WARN_ON(mlxsw_sp_sb_pool_dess[cm->pool_index].dir != dir))
 417                         continue;
 418
 419                 /* All pools are initialized using dynamic thresholds,
 420                  * therefore 'max_buff' isn't specified in cells.
 421                  */
 422                 min_buff = mlxsw_sp_bytes_cells(mlxsw_sp, cm->min_buff);
 423                 err = mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, i,
 424                                            min_buff, cm->max_buff,
 425                                            cm->pool_index);
 426                 if (err)
 427                         return err;
 428         }
 429         return 0;
 430 }
 431
 432 static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 433 {
 434         int err;
 435
 436         err = __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 437                                      mlxsw_sp_port->local_port,
 438                                      MLXSW_REG_SBXX_DIR_INGRESS,
 439                                      mlxsw_sp_sb_cms_ingress,
 440                                      MLXSW_SP_SB_CMS_INGRESS_LEN);
 441         if (err)
 442                 return err;
 443         return __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
 444                                       mlxsw_sp_port->local_port,
 445                                       MLXSW_REG_SBXX_DIR_EGRESS,
 446                                       mlxsw_sp_sb_cms_egress,
 447                                       MLXSW_SP_SB_CMS_EGRESS_LEN);
 448 }
 449
 450 static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
 451 {
 452         return __mlxsw_sp_sb_cms_init(mlxsw_sp, 0, MLXSW_REG_SBXX_DIR_EGRESS,
 453                                       mlxsw_sp_cpu_port_sb_cms,
 454                                       MLXSW_SP_CPU_PORT_SB_MCS_LEN);
 455 }
 456
 457 #define MLXSW_SP_SB_PM(_min_buff, _max_buff)    \
 458         {                                       \
 459                 .min_buff = _min_buff,          \
 460                 .max_buff = _max_buff,          \
 461         }
 462
 463 static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
 464         /* Ingress pools. */
 465         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
 466         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 467         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 468         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
 469         /* Egress pools. */
 470         MLXSW_SP_SB_PM(0, 7),
 471         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 472         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 473         MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
 474 };
 475
 476 #define MLXSW_SP_SB_PMS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms)
 477
 478 static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
 479 {
 480         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 481         int i;
 482         int err;
 483
 484         for (i = 0; i < MLXSW_SP_SB_PMS_LEN; i++) {
 485                 const struct mlxsw_sp_sb_pm *pm = &mlxsw_sp_sb_pms[i];
 486
 487                 err = mlxsw_sp_sb_pm_write(mlxsw_sp, mlxsw_sp_port->local_port,
 488                                            i, pm->min_buff, pm->max_buff);
 489                 if (err)
 490                         return err;
 491         }
 492         return 0;
 493 }
 494
 495 struct mlxsw_sp_sb_mm {
 496         u32 min_buff;
 497         u32 max_buff;
 498         u16 pool_index;
 499 };
 500
 501 #define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool)     \
 502         {                                               \
 503                 .min_buff = _min_buff,                  \
 504                 .max_buff = _max_buff,                  \
 505                 .pool_index = _pool,                    \
 506         }
 507
 508 static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
 509         MLXSW_SP_SB_MM(20000, 0xff, 4),
 510         MLXSW_SP_SB_MM(20000, 0xff, 4),
 511         MLXSW_SP_SB_MM(20000, 0xff, 4),
 512         MLXSW_SP_SB_MM(20000, 0xff, 4),
 513         MLXSW_SP_SB_MM(20000, 0xff, 4),
 514         MLXSW_SP_SB_MM(20000, 0xff, 4),
 515         MLXSW_SP_SB_MM(20000, 0xff, 4),
 516         MLXSW_SP_SB_MM(20000, 0xff, 4),
 517         MLXSW_SP_SB_MM(20000, 0xff, 4),
 518         MLXSW_SP_SB_MM(20000, 0xff, 4),
 519         MLXSW_SP_SB_MM(20000, 0xff, 4),
 520         MLXSW_SP_SB_MM(20000, 0xff, 4),
 521         MLXSW_SP_SB_MM(20000, 0xff, 4),
 522         MLXSW_SP_SB_MM(20000, 0xff, 4),
 523         MLXSW_SP_SB_MM(20000, 0xff, 4),
 524 };
 525
 526 #define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
 527
 528 static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
 529 {
 530         char sbmm_pl[MLXSW_REG_SBMM_LEN];
 531         int i;
 532         int err;
 533
 534         for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
 535                 const struct mlxsw_sp_sb_pool_des *des;
 536                 const struct mlxsw_sp_sb_mm *mc;
 537                 u32 min_buff;
 538
 539                 mc = &mlxsw_sp_sb_mms[i];
 540                 des = &mlxsw_sp_sb_pool_dess[mc->pool_index];
 541                 /* All pools are initialized using dynamic thresholds,
 542                  * therefore 'max_buff' isn't specified in cells.
 543                  */
 544                 min_buff = mlxsw_sp_bytes_cells(mlxsw_sp, mc->min_buff);
 545                 mlxsw_reg_sbmm_pack(sbmm_pl, i, min_buff, mc->max_buff,
 546                                     des->pool);
 547                 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
 548                 if (err)
 549                         return err;
 550         }
 551         return 0;
 552 }
 553
 554 static void mlxsw_sp_pool_count(u16 *p_ingress_len, u16 *p_egress_len)
 555 {
 556         int i;
 557
 558         for (i = 0; i < MLXSW_SP_SB_POOL_DESS_LEN; ++i)
 559                 if (mlxsw_sp_sb_pool_dess[i].dir == MLXSW_REG_SBXX_DIR_EGRESS)
 560                         goto out;
 561         WARN(1, "No egress pools\n");
 562
 563 out:
 564         *p_ingress_len = i;
 565         *p_egress_len = MLXSW_SP_SB_POOL_DESS_LEN - i;
 566 }
 567
 568 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
 569 {
 570         u16 ing_pool_count;
 571         u16 eg_pool_count;
 572         u64 sb_size;
 573         int err;
 574
 575         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, CELL_SIZE))
 576                 return -EIO;
 577
 578         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_BUFFER_SIZE))
 579                 return -EIO;
 580         sb_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_BUFFER_SIZE);
 581
 582         mlxsw_sp->sb = kzalloc(sizeof(*mlxsw_sp->sb), GFP_KERNEL);
 583         if (!mlxsw_sp->sb)
 584                 return -ENOMEM;
 585         mlxsw_sp->sb->cell_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, CELL_SIZE);
 586
 587         err = mlxsw_sp_sb_ports_init(mlxsw_sp);
 588         if (err)
 589                 goto err_sb_ports_init;
 590         err = mlxsw_sp_sb_prs_init(mlxsw_sp, mlxsw_sp_sb_prs,
 591                                    MLXSW_SP_SB_PRS_LEN);
 592         if (err)
 593                 goto err_sb_prs_init;
 594         err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
 595         if (err)
 596                 goto err_sb_cpu_port_sb_cms_init;
 597         err = mlxsw_sp_sb_mms_init(mlxsw_sp);
 598         if (err)
 599                 goto err_sb_mms_init;
 600         mlxsw_sp_pool_count(&ing_pool_count, &eg_pool_count);
 601         err = devlink_sb_register(priv_to_devlink(mlxsw_sp->core), 0, sb_size,
 602                                   ing_pool_count,
 603                                   eg_pool_count,
 604                                   MLXSW_SP_SB_TC_COUNT,
 605                                   MLXSW_SP_SB_TC_COUNT);
 606         if (err)
 607                 goto err_devlink_sb_register;
 608
 609         return 0;
 610
 611 err_devlink_sb_register:
 612 err_sb_mms_init:
 613 err_sb_cpu_port_sb_cms_init:
 614 err_sb_prs_init:
 615         mlxsw_sp_sb_ports_fini(mlxsw_sp);
 616 err_sb_ports_init:
 617         kfree(mlxsw_sp->sb);
 618         return err;
 619 }
 620
 621 void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp)
 622 {
 623         devlink_sb_unregister(priv_to_devlink(mlxsw_sp->core), 0);
 624         mlxsw_sp_sb_ports_fini(mlxsw_sp);
 625         kfree(mlxsw_sp->sb);
 626 }
 627
 628 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
 629 {
 630         int err;
 631
 632         err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
 633         if (err)
 634                 return err;
 635         err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
 636         if (err)
 637                 return err;
 638         err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
 639
 640         return err;
 641 }
 642
 643 int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
 644                          unsigned int sb_index, u16 pool_index,
 645                          struct devlink_sb_pool_info *pool_info)
 646 {
 647         enum mlxsw_reg_sbxx_dir dir = mlxsw_sp_sb_pool_dess[pool_index].dir;
 648         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
 649         struct mlxsw_sp_sb_pr *pr;
 650
 651         pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool_index);
 652         pool_info->pool_type = (enum devlink_sb_pool_type) dir;
 653         pool_info->size = mlxsw_sp_cells_bytes(mlxsw_sp, pr->size);
 654         pool_info->threshold_type = (enum devlink_sb_threshold_type) pr->mode;
 655         return 0;
 656 }
 657
 658 int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
 659                          unsigned int sb_index, u16 pool_index, u32 size,
 660                          enum devlink_sb_threshold_type threshold_type)
 661 {
 662         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
 663         u32 pool_size = mlxsw_sp_bytes_cells(mlxsw_sp, size);
 664         enum mlxsw_reg_sbpr_mode mode;
 665
 666         if (size > MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_BUFFER_SIZE))
 667                 return -EINVAL;
 668
 669         mode = (enum mlxsw_reg_sbpr_mode) threshold_type;
 670         return mlxsw_sp_sb_pr_write(mlxsw_sp, pool_index, mode, pool_size);
 671 }
 672
 673 #define MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET (-2) /* 3->1, 16->14 */
 674
 675 static u32 mlxsw_sp_sb_threshold_out(struct mlxsw_sp *mlxsw_sp, u16 pool_index,
 676                                      u32 max_buff)
 677 {
 678         struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool_index);
 679
 680         if (pr->mode == MLXSW_REG_SBPR_MODE_DYNAMIC)
 681                 return max_buff - MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET;
 682         return mlxsw_sp_cells_bytes(mlxsw_sp, max_buff);
 683 }
 684
 685 static int mlxsw_sp_sb_threshold_in(struct mlxsw_sp *mlxsw_sp, u16 pool_index,
 686                                     u32 threshold, u32 *p_max_buff)
 687 {
 688         struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool_index);
 689
 690         if (pr->mode == MLXSW_REG_SBPR_MODE_DYNAMIC) {
 691                 int val;
 692
 693                 val = threshold + MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET;
 694                 if (val < MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN ||
 695                     val > MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX)
 696                         return -EINVAL;
 697                 *p_max_buff = val;
 698         } else {
 699                 *p_max_buff = mlxsw_sp_bytes_cells(mlxsw_sp, threshold);
 700         }
 701         return 0;
 702 }
 703
 704 int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
 705                               unsigned int sb_index, u16 pool_index,
 706                               u32 *p_threshold)
 707 {
 708         struct mlxsw_sp_port *mlxsw_sp_port =
 709                         mlxsw_core_port_driver_priv(mlxsw_core_port);
 710         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 711         u8 local_port = mlxsw_sp_port->local_port;
 712         struct mlxsw_sp_sb_pm *pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port,
 713                                                        pool_index);
 714
 715         *p_threshold = mlxsw_sp_sb_threshold_out(mlxsw_sp, pool_index,
 716                                                  pm->max_buff);
 717         return 0;
 718 }
 719
 720 int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
 721                               unsigned int sb_index, u16 pool_index,
 722                               u32 threshold)
 723 {
 724         struct mlxsw_sp_port *mlxsw_sp_port =
 725                         mlxsw_core_port_driver_priv(mlxsw_core_port);
 726         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 727         u8 local_port = mlxsw_sp_port->local_port;
 728         u32 max_buff;
 729         int err;
 730
 731         err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool_index,
 732                                        threshold, &max_buff);
 733         if (err)
 734                 return err;
 735
 736         return mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, pool_index,
 737                                     0, max_buff);
 738 }
 739
 740 int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
 741                                  unsigned int sb_index, u16 tc_index,
 742                                  enum devlink_sb_pool_type pool_type,
 743                                  u16 *p_pool_index, u32 *p_threshold)
 744 {
 745         struct mlxsw_sp_port *mlxsw_sp_port =
 746                         mlxsw_core_port_driver_priv(mlxsw_core_port);
 747         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 748         u8 local_port = mlxsw_sp_port->local_port;
 749         u8 pg_buff = tc_index;
 750         enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type;
 751         struct mlxsw_sp_sb_cm *cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port,
 752                                                        pg_buff, dir);
 753
 754         *p_threshold = mlxsw_sp_sb_threshold_out(mlxsw_sp, cm->pool_index,
 755                                                  cm->max_buff);
 756         *p_pool_index = cm->pool_index;
 757         return 0;
 758 }
 759
 760 int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
 761                                  unsigned int sb_index, u16 tc_index,
 762                                  enum devlink_sb_pool_type pool_type,
 763                                  u16 pool_index, u32 threshold)
 764 {
 765         struct mlxsw_sp_port *mlxsw_sp_port =
 766                         mlxsw_core_port_driver_priv(mlxsw_core_port);
 767         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 768         u8 local_port = mlxsw_sp_port->local_port;
 769         u8 pg_buff = tc_index;
 770         enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type;
 771         u32 max_buff;
 772         int err;
 773
 774         if (dir != mlxsw_sp_sb_pool_dess[pool_index].dir)
 775                 return -EINVAL;
 776
 777         err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool_index,
 778                                        threshold, &max_buff);
 779         if (err)
 780                 return err;
 781
 782         return mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, pg_buff,
 783                                     0, max_buff, pool_index);
 784 }
 785
 786 #define MASKED_COUNT_MAX \
 787         (MLXSW_REG_SBSR_REC_MAX_COUNT / (MLXSW_SP_SB_TC_COUNT * 2))
 788
 789 struct mlxsw_sp_sb_sr_occ_query_cb_ctx {
 790         u8 masked_count;
 791         u8 local_port_1;
 792 };
 793
 794 static void mlxsw_sp_sb_sr_occ_query_cb(struct mlxsw_core *mlxsw_core,
 795                                         char *sbsr_pl, size_t sbsr_pl_len,
 796                                         unsigned long cb_priv)
 797 {
 798         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
 799         struct mlxsw_sp_sb_sr_occ_query_cb_ctx cb_ctx;
 800         u8 masked_count;
 801         u8 local_port;
 802         int rec_index = 0;
 803         struct mlxsw_sp_sb_cm *cm;
 804         int i;
 805
 806         memcpy(&cb_ctx, &cb_priv, sizeof(cb_ctx));
 807
 808         masked_count = 0;
 809         for (local_port = cb_ctx.local_port_1;
 810              local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
 811                 if (!mlxsw_sp->ports[local_port])
 812                         continue;
 813                 for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
 814                         cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, i,
 815                                                 MLXSW_REG_SBXX_DIR_INGRESS);
 816                         mlxsw_reg_sbsr_rec_unpack(sbsr_pl, rec_index++,
 817                                                   &cm->occ.cur, &cm->occ.max);
 818                 }
 819                 if (++masked_count == cb_ctx.masked_count)
 820                         break;
 821         }
 822         masked_count = 0;
 823         for (local_port = cb_ctx.local_port_1;
 824              local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
 825                 if (!mlxsw_sp->ports[local_port])
 826                         continue;
 827                 for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
 828                         cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, i,
 829                                                 MLXSW_REG_SBXX_DIR_EGRESS);
 830                         mlxsw_reg_sbsr_rec_unpack(sbsr_pl, rec_index++,
 831                                                   &cm->occ.cur, &cm->occ.max);
 832                 }
 833                 if (++masked_count == cb_ctx.masked_count)
 834                         break;
 835         }
 836 }
 837
 838 int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
 839                              unsigned int sb_index)
 840 {
 841         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
 842         struct mlxsw_sp_sb_sr_occ_query_cb_ctx cb_ctx;
 843         unsigned long cb_priv;
 844         LIST_HEAD(bulk_list);
 845         char *sbsr_pl;
 846         u8 masked_count;
 847         u8 local_port_1;
 848         u8 local_port = 0;
 849         int i;
 850         int err;
 851         int err2;
 852
 853         sbsr_pl = kmalloc(MLXSW_REG_SBSR_LEN, GFP_KERNEL);
 854         if (!sbsr_pl)
 855                 return -ENOMEM;
 856
 857 next_batch:
 858         local_port++;
 859         local_port_1 = local_port;
 860         masked_count = 0;
 861         mlxsw_reg_sbsr_pack(sbsr_pl, false);
 862         for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
 863                 mlxsw_reg_sbsr_pg_buff_mask_set(sbsr_pl, i, 1);
 864                 mlxsw_reg_sbsr_tclass_mask_set(sbsr_pl, i, 1);
 865         }
 866         for (; local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
 867                 if (!mlxsw_sp->ports[local_port])
 868                         continue;
 869                 mlxsw_reg_sbsr_ingress_port_mask_set(sbsr_pl, local_port, 1);
 870                 mlxsw_reg_sbsr_egress_port_mask_set(sbsr_pl, local_port, 1);
 871                 for (i = 0; i < MLXSW_SP_SB_POOL_DESS_LEN; i++) {
 872                         err = mlxsw_sp_sb_pm_occ_query(mlxsw_sp, local_port, i,
 873                                                        &bulk_list);
 874                         if (err)
 875                                 goto out;
 876                 }
 877                 if (++masked_count == MASKED_COUNT_MAX)
 878                         goto do_query;
 879         }
 880
 881 do_query:
 882         cb_ctx.masked_count = masked_count;
 883         cb_ctx.local_port_1 = local_port_1;
 884         memcpy(&cb_priv, &cb_ctx, sizeof(cb_ctx));
 885         err = mlxsw_reg_trans_query(mlxsw_core, MLXSW_REG(sbsr), sbsr_pl,
 886                                     &bulk_list, mlxsw_sp_sb_sr_occ_query_cb,
 887                                     cb_priv);
 888         if (err)
 889                 goto out;
 890         if (local_port < mlxsw_core_max_ports(mlxsw_core))
 891                 goto next_batch;
 892
 893 out:
 894         err2 = mlxsw_reg_trans_bulk_wait(&bulk_list);
 895         if (!err)
 896                 err = err2;
 897         kfree(sbsr_pl);
 898         return err;
 899 }
 900
 901 int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
 902                               unsigned int sb_index)
 903 {
 904         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
 905         LIST_HEAD(bulk_list);
 906         char *sbsr_pl;
 907         unsigned int masked_count;
 908         u8 local_port = 0;
 909         int i;
 910         int err;
 911         int err2;
 912
 913         sbsr_pl = kmalloc(MLXSW_REG_SBSR_LEN, GFP_KERNEL);
 914         if (!sbsr_pl)
 915                 return -ENOMEM;
 916
 917 next_batch:
 918         local_port++;
 919         masked_count = 0;
 920         mlxsw_reg_sbsr_pack(sbsr_pl, true);
 921         for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
 922                 mlxsw_reg_sbsr_pg_buff_mask_set(sbsr_pl, i, 1);
 923                 mlxsw_reg_sbsr_tclass_mask_set(sbsr_pl, i, 1);
 924         }
 925         for (; local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
 926                 if (!mlxsw_sp->ports[local_port])
 927                         continue;
 928                 mlxsw_reg_sbsr_ingress_port_mask_set(sbsr_pl, local_port, 1);
 929                 mlxsw_reg_sbsr_egress_port_mask_set(sbsr_pl, local_port, 1);
 930                 for (i = 0; i < MLXSW_SP_SB_POOL_DESS_LEN; i++) {
 931                         err = mlxsw_sp_sb_pm_occ_clear(mlxsw_sp, local_port, i,
 932                                                        &bulk_list);
 933                         if (err)
 934                                 goto out;
 935                 }
 936                 if (++masked_count == MASKED_COUNT_MAX)
 937                         goto do_query;
 938         }
 939
 940 do_query:
 941         err = mlxsw_reg_trans_query(mlxsw_core, MLXSW_REG(sbsr), sbsr_pl,
 942                                     &bulk_list, NULL, 0);
 943         if (err)
 944                 goto out;
 945         if (local_port < mlxsw_core_max_ports(mlxsw_core))
 946                 goto next_batch;
 947
 948 out:
 949         err2 = mlxsw_reg_trans_bulk_wait(&bulk_list);
 950         if (!err)
 951                 err = err2;
 952         kfree(sbsr_pl);
 953         return err;
 954 }
 955
 956 int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
 957                                   unsigned int sb_index, u16 pool_index,
 958                                   u32 *p_cur, u32 *p_max)
 959 {
 960         struct mlxsw_sp_port *mlxsw_sp_port =
 961                         mlxsw_core_port_driver_priv(mlxsw_core_port);
 962         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 963         u8 local_port = mlxsw_sp_port->local_port;
 964         struct mlxsw_sp_sb_pm *pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port,
 965                                                        pool_index);
 966
 967         *p_cur = mlxsw_sp_cells_bytes(mlxsw_sp, pm->occ.cur);
 968         *p_max = mlxsw_sp_cells_bytes(mlxsw_sp, pm->occ.max);
 969         return 0;
 970 }
 971
 972 int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
 973                                      unsigned int sb_index, u16 tc_index,
 974                                      enum devlink_sb_pool_type pool_type,
 975                                      u32 *p_cur, u32 *p_max)
 976 {
 977         struct mlxsw_sp_port *mlxsw_sp_port =
 978                         mlxsw_core_port_driver_priv(mlxsw_core_port);
 979         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 980         u8 local_port = mlxsw_sp_port->local_port;
 981         u8 pg_buff = tc_index;
 982         enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type;
 983         struct mlxsw_sp_sb_cm *cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port,
 984                                                        pg_buff, dir);
 985
 986         *p_cur = mlxsw_sp_cells_bytes(mlxsw_sp, cm->occ.cur);
 987         *p_max = mlxsw_sp_cells_bytes(mlxsw_sp, cm->occ.max);
 988         return 0;
 989 }