2 * drivers/net/ethernet/micrel/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * KS8851 16bit MLL chip from Micrel Inc.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/cache.h>
32 #include <linux/crc32.h>
33 #include <linux/crc32poly.h>
34 #include <linux/mii.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
37 #include <linux/slab.h>
38 #include <linux/ks8851_mll.h>
40 #include <linux/of_device.h>
41 #include <linux/of_net.h>
45 #define DRV_NAME "ks8851_mll"
47 static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
48 #define MAX_RECV_FRAMES 255
49 #define MAX_BUF_SIZE 2048
50 #define TX_BUF_SIZE 2000
51 #define RX_BUF_SIZE 2000
53 #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
54 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
55 #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
57 #define ENUM_BUS_NONE 0
58 #define ENUM_BUS_8BIT 1
59 #define ENUM_BUS_16BIT 2
60 #define ENUM_BUS_32BIT 3
62 #define MAX_MCAST_LST 32
63 #define HW_MCAST_SIZE 8
66 * union ks_tx_hdr - tx header data
67 * @txb: The header as bytes
68 * @txw: The header as 16bit, little-endian words
70 * A dual representation of the tx header data to allow
71 * access to individual bytes, and to allow 16bit accesses
72 * with 16bit alignment.
80 * struct ks_net - KS8851 driver private data
81 * @net_device : The network device we're bound to
82 * @hw_addr : start address of data register.
83 * @hw_addr_cmd : start address of command register.
84 * @txh : temporaly buffer to save status/length.
85 * @lock : Lock to ensure that the device is not accessed when busy.
86 * @pdev : Pointer to platform device.
87 * @mii : The MII state information for the mii calls.
88 * @frame_head_info : frame header information for multi-pkt rx.
89 * @statelock : Lock on this structure for tx list.
90 * @msg_enable : The message flags controlling driver output (see ethtool).
91 * @frame_cnt : number of frames received.
92 * @bus_width : i/o bus width.
93 * @rc_rxqcr : Cached copy of KS_RXQCR.
94 * @rc_txcr : Cached copy of KS_TXCR.
95 * @rc_ier : Cached copy of KS_IER.
96 * @sharedbus : Multipex(addr and data bus) mode indicator.
97 * @cmd_reg_cache : command register cached.
98 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
99 * @promiscuous : promiscuous mode indicator.
100 * @all_mcast : mutlicast indicator.
101 * @mcast_lst_size : size of multicast list.
102 * @mcast_lst : multicast list.
103 * @mcast_bits : multicast enabed.
104 * @mac_addr : MAC address assigned to this device.
106 * @extra_byte : number of extra byte prepended rx pkt.
107 * @enabled : indicator this device works.
109 * The @lock ensures that the chip is protected when certain operations are
110 * in progress. When the read or write packet transfer is in progress, most
111 * of the chip registers are not accessible until the transfer is finished and
112 * the DMA has been de-asserted.
114 * The @statelock is used to protect information in the structure which may
115 * need to be accessed via several sources, such as the network driver layer
116 * or one of the work queues.
120 /* Receive multiplex framer header info */
121 struct type_frame_head {
122 u16 sts; /* Frame status */
123 u16 len; /* Byte count */
127 struct net_device *netdev;
128 void __iomem *hw_addr;
129 void __iomem *hw_addr_cmd;
130 union ks_tx_hdr txh ____cacheline_aligned;
131 struct mutex lock; /* spinlock to be interrupt safe */
132 struct platform_device *pdev;
133 struct mii_if_info mii;
134 struct type_frame_head *frame_head_info;
135 spinlock_t statelock;
145 u16 cmd_reg_cache_int;
149 u8 mcast_lst[MAX_MCAST_LST][ETH_ALEN];
150 u8 mcast_bits[HW_MCAST_SIZE];
157 static int msg_enable;
159 #define BE3 0x8000 /* Byte Enable 3 */
160 #define BE2 0x4000 /* Byte Enable 2 */
161 #define BE1 0x2000 /* Byte Enable 1 */
162 #define BE0 0x1000 /* Byte Enable 0 */
164 /* register read/write calls.
166 * All these calls issue transactions to access the chip's registers. They
167 * all require that the necessary lock is held to prevent accesses when the
168 * chip is busy transferring packet data (RX/TX FIFO accesses).
172 * ks_rdreg8 - read 8 bit register from device
173 * @ks : The chip information
174 * @offset: The register address
176 * Read a 8bit register from the chip, returning the result
178 static u8 ks_rdreg8(struct ks_net *ks, int offset)
181 u8 shift_bit = offset & 0x03;
182 u8 shift_data = (offset & 1) << 3;
183 ks->cmd_reg_cache = (u16) offset | (u16)(BE0 << shift_bit);
184 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
185 data = ioread16(ks->hw_addr);
186 return (u8)(data >> shift_data);
190 * ks_rdreg16 - read 16 bit register from device
191 * @ks : The chip information
192 * @offset: The register address
194 * Read a 16bit register from the chip, returning the result
197 static u16 ks_rdreg16(struct ks_net *ks, int offset)
199 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
200 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
201 return ioread16(ks->hw_addr);
205 * ks_wrreg8 - write 8bit register value to chip
206 * @ks: The chip information
207 * @offset: The register address
208 * @value: The value to write
211 static void ks_wrreg8(struct ks_net *ks, int offset, u8 value)
213 u8 shift_bit = (offset & 0x03);
214 u16 value_write = (u16)(value << ((offset & 1) << 3));
215 ks->cmd_reg_cache = (u16)offset | (BE0 << shift_bit);
216 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
217 iowrite16(value_write, ks->hw_addr);
221 * ks_wrreg16 - write 16bit register value to chip
222 * @ks: The chip information
223 * @offset: The register address
224 * @value: The value to write
228 static void ks_wrreg16(struct ks_net *ks, int offset, u16 value)
230 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
231 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
232 iowrite16(value, ks->hw_addr);
236 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
237 * @ks: The chip state
238 * @wptr: buffer address to save data
239 * @len: length in byte to read
242 static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
246 *wptr++ = (u16)ioread16(ks->hw_addr);
250 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
251 * @ks: The chip information
252 * @wptr: buffer address
253 * @len: length in byte to write
256 static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
260 iowrite16(*wptr++, ks->hw_addr);
263 static void ks_disable_int(struct ks_net *ks)
265 ks_wrreg16(ks, KS_IER, 0x0000);
266 } /* ks_disable_int */
268 static void ks_enable_int(struct ks_net *ks)
270 ks_wrreg16(ks, KS_IER, ks->rc_ier);
271 } /* ks_enable_int */
274 * ks_tx_fifo_space - return the available hardware buffer size.
275 * @ks: The chip information
278 static inline u16 ks_tx_fifo_space(struct ks_net *ks)
280 return ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
284 * ks_save_cmd_reg - save the command register from the cache.
285 * @ks: The chip information
288 static inline void ks_save_cmd_reg(struct ks_net *ks)
290 /*ks8851 MLL has a bug to read back the command register.
291 * So rely on software to save the content of command register.
293 ks->cmd_reg_cache_int = ks->cmd_reg_cache;
297 * ks_restore_cmd_reg - restore the command register from the cache and
298 * write to hardware register.
299 * @ks: The chip information
302 static inline void ks_restore_cmd_reg(struct ks_net *ks)
304 ks->cmd_reg_cache = ks->cmd_reg_cache_int;
305 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
309 * ks_set_powermode - set power mode of the device
310 * @ks: The chip information
311 * @pwrmode: The power mode value to write to KS_PMECR.
313 * Change the power mode of the chip.
315 static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode)
319 netif_dbg(ks, hw, ks->netdev, "setting power mode %d\n", pwrmode);
321 ks_rdreg16(ks, KS_GRR);
322 pmecr = ks_rdreg16(ks, KS_PMECR);
323 pmecr &= ~PMECR_PM_MASK;
326 ks_wrreg16(ks, KS_PMECR, pmecr);
330 * ks_read_config - read chip configuration of bus width.
331 * @ks: The chip information
334 static void ks_read_config(struct ks_net *ks)
338 /* Regardless of bus width, 8 bit read should always work.*/
339 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
340 reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8;
342 /* addr/data bus are multiplexed */
343 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
345 /* There are garbage data when reading data from QMU,
346 depending on bus-width.
349 if (reg_data & CCR_8BIT) {
350 ks->bus_width = ENUM_BUS_8BIT;
352 } else if (reg_data & CCR_16BIT) {
353 ks->bus_width = ENUM_BUS_16BIT;
356 ks->bus_width = ENUM_BUS_32BIT;
362 * ks_soft_reset - issue one of the soft reset to the device
363 * @ks: The device state.
364 * @op: The bit(s) to set in the GRR
366 * Issue the relevant soft-reset command to the device's GRR register
369 * Note, the delays are in there as a caution to ensure that the reset
370 * has time to take effect and then complete. Since the datasheet does
371 * not currently specify the exact sequence, we have chosen something
372 * that seems to work with our device.
374 static void ks_soft_reset(struct ks_net *ks, unsigned op)
376 /* Disable interrupt first */
377 ks_wrreg16(ks, KS_IER, 0x0000);
378 ks_wrreg16(ks, KS_GRR, op);
379 mdelay(10); /* wait a short time to effect reset */
380 ks_wrreg16(ks, KS_GRR, 0);
381 mdelay(1); /* wait for condition to clear */
385 static void ks_enable_qmu(struct ks_net *ks)
389 w = ks_rdreg16(ks, KS_TXCR);
390 /* Enables QMU Transmit (TXCR). */
391 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
394 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
398 w = ks_rdreg16(ks, KS_RXQCR);
399 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
401 /* Enables QMU Receive (RXCR1). */
402 w = ks_rdreg16(ks, KS_RXCR1);
403 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
405 } /* ks_enable_qmu */
407 static void ks_disable_qmu(struct ks_net *ks)
411 w = ks_rdreg16(ks, KS_TXCR);
413 /* Disables QMU Transmit (TXCR). */
415 ks_wrreg16(ks, KS_TXCR, w);
417 /* Disables QMU Receive (RXCR1). */
418 w = ks_rdreg16(ks, KS_RXCR1);
420 ks_wrreg16(ks, KS_RXCR1, w);
424 } /* ks_disable_qmu */
427 * ks_read_qmu - read 1 pkt data from the QMU.
428 * @ks: The chip information
429 * @buf: buffer address to save 1 pkt
431 * Here is the sequence to read 1 pkt:
432 * 1. set sudo DMA mode
433 * 2. read prepend data
435 * 4. reset sudo DMA Mode
437 static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
439 u32 r = ks->extra_byte & 0x1 ;
440 u32 w = ks->extra_byte - r;
442 /* 1. set sudo DMA mode */
443 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
444 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
446 /* 2. read prepend data */
448 * read 4 + extra bytes and discard them.
449 * extra bytes for dummy, 2 for status, 2 for len
452 /* use likely(r) for 8 bit access for performance */
454 ioread8(ks->hw_addr);
455 ks_inblk(ks, buf, w + 2 + 2);
457 /* 3. read pkt data */
458 ks_inblk(ks, buf, ALIGN(len, 4));
460 /* 4. reset sudo DMA Mode */
461 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
465 * ks_rcv - read multiple pkts data from the QMU.
466 * @ks: The chip information
467 * @netdev: The network device being opened.
469 * Read all of header information before reading pkt content.
470 * It is not allowed only port of pkts in QMU after issuing
473 static void ks_rcv(struct ks_net *ks, struct net_device *netdev)
476 struct type_frame_head *frame_hdr = ks->frame_head_info;
479 ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
481 /* read all header information */
482 for (i = 0; i < ks->frame_cnt; i++) {
483 /* Checking Received packet status */
484 frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR);
485 /* Get packet len from hardware */
486 frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR);
490 frame_hdr = ks->frame_head_info;
491 while (ks->frame_cnt--) {
492 if (unlikely(!(frame_hdr->sts & RXFSHR_RXFV) ||
493 frame_hdr->len >= RX_BUF_SIZE ||
494 frame_hdr->len <= 0)) {
496 /* discard an invalid packet */
497 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
498 netdev->stats.rx_dropped++;
499 if (!(frame_hdr->sts & RXFSHR_RXFV))
500 netdev->stats.rx_frame_errors++;
502 netdev->stats.rx_length_errors++;
507 skb = netdev_alloc_skb(netdev, frame_hdr->len + 16);
510 /* read data block including CRC 4 bytes */
511 ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len);
512 skb_put(skb, frame_hdr->len - 4);
513 skb->protocol = eth_type_trans(skb, netdev);
515 /* exclude CRC size */
516 netdev->stats.rx_bytes += frame_hdr->len - 4;
517 netdev->stats.rx_packets++;
519 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
520 netdev->stats.rx_dropped++;
527 * ks_update_link_status - link status update.
528 * @netdev: The network device being opened.
529 * @ks: The chip information
533 static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks)
535 /* check the status of the link */
537 if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) {
538 netif_carrier_on(netdev);
539 link_up_status = true;
541 netif_carrier_off(netdev);
542 link_up_status = false;
544 netif_dbg(ks, link, ks->netdev,
545 "%s: %s\n", __func__, link_up_status ? "UP" : "DOWN");
549 * ks_irq - device interrupt handler
550 * @irq: Interrupt number passed from the IRQ handler.
551 * @pw: The private word passed to register_irq(), our struct ks_net.
553 * This is the handler invoked to find out what happened
555 * Read the interrupt status, work out what needs to be done and then clear
556 * any of the interrupts that are not needed.
559 static irqreturn_t ks_irq(int irq, void *pw)
561 struct net_device *netdev = pw;
562 struct ks_net *ks = netdev_priv(netdev);
565 /*this should be the first in IRQ handler */
568 status = ks_rdreg16(ks, KS_ISR);
569 if (unlikely(!status)) {
570 ks_restore_cmd_reg(ks);
574 ks_wrreg16(ks, KS_ISR, status);
576 if (likely(status & IRQ_RXI))
579 if (unlikely(status & IRQ_LCI))
580 ks_update_link_status(netdev, ks);
582 if (unlikely(status & IRQ_TXI))
583 netif_wake_queue(netdev);
585 if (unlikely(status & IRQ_LDI)) {
587 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
588 pmecr &= ~PMECR_WKEVT_MASK;
589 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
592 if (unlikely(status & IRQ_RXOI))
593 ks->netdev->stats.rx_over_errors++;
594 /* this should be the last in IRQ handler*/
595 ks_restore_cmd_reg(ks);
601 * ks_net_open - open network device
602 * @netdev: The network device being opened.
604 * Called when the network device is marked active, such as a user executing
605 * 'ifconfig up' on the device.
607 static int ks_net_open(struct net_device *netdev)
609 struct ks_net *ks = netdev_priv(netdev);
612 #define KS_INT_FLAGS IRQF_TRIGGER_LOW
613 /* lock the card, even if we may not actually do anything
614 * else at the moment.
617 netif_dbg(ks, ifup, ks->netdev, "%s - entry\n", __func__);
620 err = request_irq(netdev->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, netdev);
623 pr_err("Failed to request IRQ: %d: %d\n", netdev->irq, err);
627 /* wake up powermode to normal mode */
628 ks_set_powermode(ks, PMECR_PM_NORMAL);
629 mdelay(1); /* wait for normal mode to take effect */
631 ks_wrreg16(ks, KS_ISR, 0xffff);
634 netif_start_queue(ks->netdev);
636 netif_dbg(ks, ifup, ks->netdev, "network device up\n");
642 * ks_net_stop - close network device
643 * @netdev: The device being closed.
645 * Called to close down a network device which has been active. Cancell any
646 * work, shutdown the RX and TX process and then place the chip into a low
647 * power state whilst it is not being used.
649 static int ks_net_stop(struct net_device *netdev)
651 struct ks_net *ks = netdev_priv(netdev);
653 netif_info(ks, ifdown, netdev, "shutting down\n");
655 netif_stop_queue(netdev);
657 mutex_lock(&ks->lock);
659 /* turn off the IRQs and ack any outstanding */
660 ks_wrreg16(ks, KS_IER, 0x0000);
661 ks_wrreg16(ks, KS_ISR, 0xffff);
663 /* shutdown RX/TX QMU */
666 /* set powermode to soft power down to save power */
667 ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
668 free_irq(netdev->irq, netdev);
669 mutex_unlock(&ks->lock);
675 * ks_write_qmu - write 1 pkt data to the QMU.
676 * @ks: The chip information
677 * @pdata: buffer address to save 1 pkt
678 * @len: Pkt length in byte
679 * Here is the sequence to write 1 pkt:
680 * 1. set sudo DMA mode
681 * 2. write status/length
683 * 4. reset sudo DMA Mode
684 * 5. reset sudo DMA mode
685 * 6. Wait until pkt is out
687 static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
689 /* start header at txb[0] to align txw entries */
691 ks->txh.txw[1] = cpu_to_le16(len);
693 /* 1. set sudo-DMA mode */
694 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
695 /* 2. write status/lenth info */
696 ks_outblk(ks, ks->txh.txw, 4);
697 /* 3. write pkt data */
698 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
699 /* 4. reset sudo-DMA mode */
700 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
701 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
702 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
703 /* 6. wait until TXQCR_METFE is auto-cleared */
704 while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE)
709 * ks_start_xmit - transmit packet
710 * @skb : The buffer to transmit
711 * @netdev : The device used to transmit the packet.
713 * Called by the network layer to transmit the @skb.
714 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
715 * So while tx is in-progress, prevent IRQ interrupt from happenning.
717 static netdev_tx_t ks_start_xmit(struct sk_buff *skb, struct net_device *netdev)
719 netdev_tx_t retv = NETDEV_TX_OK;
720 struct ks_net *ks = netdev_priv(netdev);
722 disable_irq(netdev->irq);
724 spin_lock(&ks->statelock);
726 /* Extra space are required:
727 * 4 byte for alignment, 4 for status/length, 4 for CRC
730 if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) {
731 ks_write_qmu(ks, skb->data, skb->len);
732 /* add tx statistics */
733 netdev->stats.tx_bytes += skb->len;
734 netdev->stats.tx_packets++;
737 retv = NETDEV_TX_BUSY;
738 spin_unlock(&ks->statelock);
740 enable_irq(netdev->irq);
745 * ks_start_rx - ready to serve pkts
746 * @ks : The chip information
749 static void ks_start_rx(struct ks_net *ks)
753 /* Enables QMU Receive (RXCR1). */
754 cntl = ks_rdreg16(ks, KS_RXCR1);
756 ks_wrreg16(ks, KS_RXCR1, cntl);
760 * ks_stop_rx - stop to serve pkts
761 * @ks : The chip information
764 static void ks_stop_rx(struct ks_net *ks)
768 /* Disables QMU Receive (RXCR1). */
769 cntl = ks_rdreg16(ks, KS_RXCR1);
771 ks_wrreg16(ks, KS_RXCR1, cntl);
775 static unsigned long const ethernet_polynomial = CRC32_POLY_BE;
777 static unsigned long ether_gen_crc(int length, u8 *data)
780 while (--length >= 0) {
781 u8 current_octet = *data++;
784 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
786 ((crc < 0) ^ (current_octet & 1) ?
787 ethernet_polynomial : 0);
790 return (unsigned long)crc;
791 } /* ether_gen_crc */
794 * ks_set_grpaddr - set multicast information
795 * @ks : The chip information
798 static void ks_set_grpaddr(struct ks_net *ks)
801 u32 index, position, value;
803 memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE);
805 for (i = 0; i < ks->mcast_lst_size; i++) {
806 position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f;
807 index = position >> 3;
808 value = 1 << (position & 7);
809 ks->mcast_bits[index] |= (u8)value;
812 for (i = 0; i < HW_MCAST_SIZE; i++) {
814 ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1),
815 (ks->mcast_bits[i] << 8) |
816 ks->mcast_bits[i - 1]);
819 } /* ks_set_grpaddr */
822 * ks_clear_mcast - clear multicast information
824 * @ks : The chip information
825 * This routine removes all mcast addresses set in the hardware.
828 static void ks_clear_mcast(struct ks_net *ks)
831 for (i = 0; i < HW_MCAST_SIZE; i++)
832 ks->mcast_bits[i] = 0;
834 mcast_size = HW_MCAST_SIZE >> 2;
835 for (i = 0; i < mcast_size; i++)
836 ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0);
839 static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode)
842 ks->promiscuous = promiscuous_mode;
843 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
844 cntl = ks_rdreg16(ks, KS_RXCR1);
846 cntl &= ~RXCR1_FILTER_MASK;
847 if (promiscuous_mode)
848 /* Enable Promiscuous mode */
849 cntl |= RXCR1_RXAE | RXCR1_RXINVF;
851 /* Disable Promiscuous mode (default normal mode) */
852 cntl |= RXCR1_RXPAFMA;
854 ks_wrreg16(ks, KS_RXCR1, cntl);
859 } /* ks_set_promis */
861 static void ks_set_mcast(struct ks_net *ks, u16 mcast)
865 ks->all_mcast = mcast;
866 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
867 cntl = ks_rdreg16(ks, KS_RXCR1);
868 cntl &= ~RXCR1_FILTER_MASK;
870 /* Enable "Perfect with Multicast address passed mode" */
871 cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
874 * Disable "Perfect with Multicast address passed
875 * mode" (normal mode).
877 cntl |= RXCR1_RXPAFMA;
879 ks_wrreg16(ks, KS_RXCR1, cntl);
885 static void ks_set_rx_mode(struct net_device *netdev)
887 struct ks_net *ks = netdev_priv(netdev);
888 struct netdev_hw_addr *ha;
890 /* Turn on/off promiscuous mode. */
891 if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC)
893 (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC));
894 /* Turn on/off all mcast mode. */
895 else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)
897 (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI));
899 ks_set_promis(ks, false);
901 if ((netdev->flags & IFF_MULTICAST) && netdev_mc_count(netdev)) {
902 if (netdev_mc_count(netdev) <= MAX_MCAST_LST) {
905 netdev_for_each_mc_addr(ha, netdev) {
906 if (i >= MAX_MCAST_LST)
908 memcpy(ks->mcast_lst[i++], ha->addr, ETH_ALEN);
910 ks->mcast_lst_size = (u8)i;
914 * List too big to support so
915 * turn on all mcast mode.
917 ks->mcast_lst_size = MAX_MCAST_LST;
918 ks_set_mcast(ks, true);
921 ks->mcast_lst_size = 0;
924 } /* ks_set_rx_mode */
926 static void ks_set_mac(struct ks_net *ks, u8 *data)
928 u16 *pw = (u16 *)data;
931 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
934 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
935 ks_wrreg16(ks, KS_MARH, w);
938 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
939 ks_wrreg16(ks, KS_MARM, w);
942 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
943 ks_wrreg16(ks, KS_MARL, w);
945 memcpy(ks->mac_addr, data, ETH_ALEN);
951 static int ks_set_mac_address(struct net_device *netdev, void *paddr)
953 struct ks_net *ks = netdev_priv(netdev);
954 struct sockaddr *addr = paddr;
957 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
959 da = (u8 *)netdev->dev_addr;
965 static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
967 struct ks_net *ks = netdev_priv(netdev);
969 if (!netif_running(netdev))
972 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
975 static const struct net_device_ops ks_netdev_ops = {
976 .ndo_open = ks_net_open,
977 .ndo_stop = ks_net_stop,
978 .ndo_do_ioctl = ks_net_ioctl,
979 .ndo_start_xmit = ks_start_xmit,
980 .ndo_set_mac_address = ks_set_mac_address,
981 .ndo_set_rx_mode = ks_set_rx_mode,
982 .ndo_validate_addr = eth_validate_addr,
985 /* ethtool support */
987 static void ks_get_drvinfo(struct net_device *netdev,
988 struct ethtool_drvinfo *di)
990 strlcpy(di->driver, DRV_NAME, sizeof(di->driver));
991 strlcpy(di->version, "1.00", sizeof(di->version));
992 strlcpy(di->bus_info, dev_name(netdev->dev.parent),
993 sizeof(di->bus_info));
996 static u32 ks_get_msglevel(struct net_device *netdev)
998 struct ks_net *ks = netdev_priv(netdev);
999 return ks->msg_enable;
1002 static void ks_set_msglevel(struct net_device *netdev, u32 to)
1004 struct ks_net *ks = netdev_priv(netdev);
1005 ks->msg_enable = to;
1008 static int ks_get_link_ksettings(struct net_device *netdev,
1009 struct ethtool_link_ksettings *cmd)
1011 struct ks_net *ks = netdev_priv(netdev);
1013 mii_ethtool_get_link_ksettings(&ks->mii, cmd);
1018 static int ks_set_link_ksettings(struct net_device *netdev,
1019 const struct ethtool_link_ksettings *cmd)
1021 struct ks_net *ks = netdev_priv(netdev);
1022 return mii_ethtool_set_link_ksettings(&ks->mii, cmd);
1025 static u32 ks_get_link(struct net_device *netdev)
1027 struct ks_net *ks = netdev_priv(netdev);
1028 return mii_link_ok(&ks->mii);
1031 static int ks_nway_reset(struct net_device *netdev)
1033 struct ks_net *ks = netdev_priv(netdev);
1034 return mii_nway_restart(&ks->mii);
1037 static const struct ethtool_ops ks_ethtool_ops = {
1038 .get_drvinfo = ks_get_drvinfo,
1039 .get_msglevel = ks_get_msglevel,
1040 .set_msglevel = ks_set_msglevel,
1041 .get_link = ks_get_link,
1042 .nway_reset = ks_nway_reset,
1043 .get_link_ksettings = ks_get_link_ksettings,
1044 .set_link_ksettings = ks_set_link_ksettings,
1047 /* MII interface controls */
1050 * ks_phy_reg - convert MII register into a KS8851 register
1051 * @reg: MII register number.
1053 * Return the KS8851 register number for the corresponding MII PHY register
1054 * if possible. Return zero if the MII register has no direct mapping to the
1055 * KS8851 register set.
1057 static int ks_phy_reg(int reg)
1078 * ks_phy_read - MII interface PHY register read.
1079 * @netdev: The network device the PHY is on.
1080 * @phy_addr: Address of PHY (ignored as we only have one)
1081 * @reg: The register to read.
1083 * This call reads data from the PHY register specified in @reg. Since the
1084 * device does not support all the MII registers, the non-existent values
1085 * are always returned as zero.
1087 * We return zero for unsupported registers as the MII code does not check
1088 * the value returned for any error status, and simply returns it to the
1089 * caller. The mii-tool that the driver was tested with takes any -ve error
1090 * as real PHY capabilities, thus displaying incorrect data to the user.
1092 static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg)
1094 struct ks_net *ks = netdev_priv(netdev);
1098 ksreg = ks_phy_reg(reg);
1100 return 0x0; /* no error return allowed, so use zero */
1102 mutex_lock(&ks->lock);
1103 result = ks_rdreg16(ks, ksreg);
1104 mutex_unlock(&ks->lock);
1109 static void ks_phy_write(struct net_device *netdev,
1110 int phy, int reg, int value)
1112 struct ks_net *ks = netdev_priv(netdev);
1115 ksreg = ks_phy_reg(reg);
1117 mutex_lock(&ks->lock);
1118 ks_wrreg16(ks, ksreg, value);
1119 mutex_unlock(&ks->lock);
1124 * ks_read_selftest - read the selftest memory info.
1125 * @ks: The device state
1127 * Read and check the TX/RX memory selftest information.
1129 static int ks_read_selftest(struct ks_net *ks)
1131 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1135 rd = ks_rdreg16(ks, KS_MBIR);
1137 if ((rd & both_done) != both_done) {
1138 netdev_warn(ks->netdev, "Memory selftest not finished\n");
1142 if (rd & MBIR_TXMBFA) {
1143 netdev_err(ks->netdev, "TX memory selftest fails\n");
1147 if (rd & MBIR_RXMBFA) {
1148 netdev_err(ks->netdev, "RX memory selftest fails\n");
1152 netdev_info(ks->netdev, "the selftest passes\n");
1156 static void ks_setup(struct ks_net *ks)
1161 * Configure QMU Transmit
1164 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1165 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
1167 /* Setup Receive Frame Data Pointer Auto-Increment */
1168 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
1170 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1171 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_RXFCT_MASK);
1173 /* Setup RxQ Command Control (RXQCR) */
1174 ks->rc_rxqcr = RXQCR_CMD_CNTL;
1175 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
1178 * set the force mode to half duplex, default is full duplex
1179 * because if the auto-negotiation fails, most switch uses
1183 w = ks_rdreg16(ks, KS_P1MBCR);
1184 w &= ~BMCR_FULLDPLX;
1185 ks_wrreg16(ks, KS_P1MBCR, w);
1187 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
1188 ks_wrreg16(ks, KS_TXCR, w);
1190 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
1192 if (ks->promiscuous) /* bPromiscuous */
1193 w |= (RXCR1_RXAE | RXCR1_RXINVF);
1194 else if (ks->all_mcast) /* Multicast address passed mode */
1195 w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1196 else /* Normal mode */
1199 ks_wrreg16(ks, KS_RXCR1, w);
1203 static void ks_setup_int(struct ks_net *ks)
1206 /* Clear the interrupts status of the hardware. */
1207 ks_wrreg16(ks, KS_ISR, 0xffff);
1209 /* Enables the interrupts of the hardware. */
1210 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
1211 } /* ks_setup_int */
1213 static int ks_hw_init(struct ks_net *ks)
1215 #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1216 ks->promiscuous = 0;
1218 ks->mcast_lst_size = 0;
1220 ks->frame_head_info = devm_kmalloc(&ks->pdev->dev, MHEADER_SIZE,
1222 if (!ks->frame_head_info)
1225 ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS);
1229 #if defined(CONFIG_OF)
1230 static const struct of_device_id ks8851_ml_dt_ids[] = {
1231 { .compatible = "micrel,ks8851-mll" },
1234 MODULE_DEVICE_TABLE(of, ks8851_ml_dt_ids);
1237 static int ks8851_probe(struct platform_device *pdev)
1240 struct resource *io_d, *io_c;
1241 struct net_device *netdev;
1246 netdev = alloc_etherdev(sizeof(struct ks_net));
1250 SET_NETDEV_DEV(netdev, &pdev->dev);
1252 ks = netdev_priv(netdev);
1253 ks->netdev = netdev;
1255 io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1256 ks->hw_addr = devm_ioremap_resource(&pdev->dev, io_d);
1257 if (IS_ERR(ks->hw_addr)) {
1258 err = PTR_ERR(ks->hw_addr);
1262 io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1263 ks->hw_addr_cmd = devm_ioremap_resource(&pdev->dev, io_c);
1264 if (IS_ERR(ks->hw_addr_cmd)) {
1265 err = PTR_ERR(ks->hw_addr_cmd);
1269 netdev->irq = platform_get_irq(pdev, 0);
1271 if ((int)netdev->irq < 0) {
1278 mutex_init(&ks->lock);
1279 spin_lock_init(&ks->statelock);
1281 netdev->netdev_ops = &ks_netdev_ops;
1282 netdev->ethtool_ops = &ks_ethtool_ops;
1284 /* setup mii state */
1285 ks->mii.dev = netdev;
1287 ks->mii.phy_id_mask = 1;
1288 ks->mii.reg_num_mask = 0xf;
1289 ks->mii.mdio_read = ks_phy_read;
1290 ks->mii.mdio_write = ks_phy_write;
1292 netdev_info(netdev, "message enable is %d\n", msg_enable);
1293 /* set the default message enable */
1294 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1299 /* simple check for a valid chip being connected to the bus */
1300 if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1301 netdev_err(netdev, "failed to read device ID\n");
1306 if (ks_read_selftest(ks)) {
1307 netdev_err(netdev, "failed to read device ID\n");
1312 err = register_netdev(netdev);
1316 platform_set_drvdata(pdev, netdev);
1318 ks_soft_reset(ks, GRR_GSR);
1324 data = ks_rdreg16(ks, KS_OBCR);
1325 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16mA);
1327 /* overwriting the default MAC address */
1328 if (pdev->dev.of_node) {
1329 mac = of_get_mac_address(pdev->dev.of_node);
1331 memcpy(ks->mac_addr, mac, ETH_ALEN);
1333 struct ks8851_mll_platform_data *pdata;
1335 pdata = dev_get_platdata(&pdev->dev);
1337 netdev_err(netdev, "No platform data\n");
1341 memcpy(ks->mac_addr, pdata->mac_addr, ETH_ALEN);
1343 if (!is_valid_ether_addr(ks->mac_addr)) {
1344 /* Use random MAC address if none passed */
1345 eth_random_addr(ks->mac_addr);
1346 netdev_info(netdev, "Using random mac address\n");
1348 netdev_info(netdev, "Mac address is: %pM\n", ks->mac_addr);
1350 memcpy(netdev->dev_addr, ks->mac_addr, ETH_ALEN);
1352 ks_set_mac(ks, netdev->dev_addr);
1354 id = ks_rdreg16(ks, KS_CIDER);
1356 netdev_info(netdev, "Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1357 (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7);
1361 unregister_netdev(netdev);
1363 free_netdev(netdev);
1367 static int ks8851_remove(struct platform_device *pdev)
1369 struct net_device *netdev = platform_get_drvdata(pdev);
1371 unregister_netdev(netdev);
1372 free_netdev(netdev);
1377 static struct platform_driver ks8851_platform_driver = {
1380 .of_match_table = of_match_ptr(ks8851_ml_dt_ids),
1382 .probe = ks8851_probe,
1383 .remove = ks8851_remove,
1386 module_platform_driver(ks8851_platform_driver);
1388 MODULE_DESCRIPTION("KS8851 MLL Network driver");
1389 MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1390 MODULE_LICENSE("GPL");
1391 module_param_named(message, msg_enable, int, 0);
1392 MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");