1 // SPDX-License-Identifier: GPL-2.0-only
3 * Register map access API - ENCX24J600 support
5 * Copyright 2015 Gridpoint
7 * Author: Jon Ringle <jringle@gridpoint.com>
10 #include <linux/delay.h>
11 #include <linux/errno.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/regmap.h>
16 #include <linux/spi/spi.h>
18 #include "encx24j600_hw.h"
20 static inline bool is_bits_set(int value, int mask)
22 return (value & mask) == mask;
25 static int encx24j600_switch_bank(struct encx24j600_context *ctx,
29 int bank_opcode = BANK_SELECT(bank);
31 ret = spi_write(ctx->spi, &bank_opcode, 1);
38 static int encx24j600_cmdn(struct encx24j600_context *ctx, u8 opcode,
39 const void *buf, size_t len)
42 struct spi_transfer t[2] = { { .tx_buf = &opcode, .len = 1, },
43 { .tx_buf = buf, .len = len }, };
45 spi_message_add_tail(&t[0], &m);
46 spi_message_add_tail(&t[1], &m);
48 return spi_sync(ctx->spi, &m);
51 static void regmap_lock_mutex(void *context)
53 struct encx24j600_context *ctx = context;
55 mutex_lock(&ctx->mutex);
58 static void regmap_unlock_mutex(void *context)
60 struct encx24j600_context *ctx = context;
62 mutex_unlock(&ctx->mutex);
65 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val,
68 struct encx24j600_context *ctx = context;
69 u8 banked_reg = reg & ADDR_MASK;
70 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
77 cmd = RCRCODE | banked_reg;
78 if ((banked_reg < 0x16) && (ctx->bank != bank))
79 ret = encx24j600_switch_bank(ctx, bank);
83 /* Translate registers that are more effecient using
96 cmd = RUDARDPT; break;
98 cmd = RUDAWRPT; break;
111 ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len);
116 static int regmap_encx24j600_sfr_update(struct encx24j600_context *ctx,
117 u8 reg, u8 *val, size_t len,
118 u8 unbanked_cmd, u8 banked_code)
120 u8 banked_reg = reg & ADDR_MASK;
121 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);
122 u8 cmd = unbanked_cmd;
123 struct spi_message m;
124 struct spi_transfer t[3] = { { .tx_buf = &cmd, .len = sizeof(cmd), },
125 { .tx_buf = ®, .len = sizeof(reg), },
126 { .tx_buf = val, .len = len }, };
131 cmd = banked_code | banked_reg;
132 if ((banked_reg < 0x16) && (ctx->bank != bank))
133 ret = encx24j600_switch_bank(ctx, bank);
137 /* Translate registers that are more effecient using
138 * 3-byte SPI commands
142 cmd = WGPRDPT; break;
144 cmd = WGPWRPT; break;
146 cmd = WRXRDPT; break;
148 cmd = WRXWRPT; break;
150 cmd = WUDARDPT; break;
152 cmd = WUDAWRPT; break;
161 spi_message_init(&m);
162 spi_message_add_tail(&t[0], &m);
164 if (cmd == unbanked_cmd) {
166 spi_message_add_tail(&t[1], &m);
169 spi_message_add_tail(&t[2], &m);
170 return spi_sync(ctx->spi, &m);
173 static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val,
176 struct encx24j600_context *ctx = context;
178 return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);
181 static int regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx,
184 return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);
187 static int regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx,
190 return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);
193 static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg,
197 struct encx24j600_context *ctx = context;
200 unsigned int set_mask = mask & val;
201 unsigned int clr_mask = mask & ~val;
203 if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80)
207 ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
209 set_mask = (set_mask & 0xff00) >> 8;
211 if ((set_mask & 0xff) && (ret == 0))
212 ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
214 if ((clr_mask & 0xff) && (ret == 0))
215 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);
217 clr_mask = (clr_mask & 0xff00) >> 8;
219 if ((clr_mask & 0xff) && (ret == 0))
220 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);
225 int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
228 struct encx24j600_context *ctx = context;
231 return encx24j600_cmdn(ctx, reg, data, count);
233 /* SPI 1-byte command. Ignore data */
234 return spi_write(ctx->spi, ®, 1);
236 EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_write);
238 int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count)
240 struct encx24j600_context *ctx = context;
242 if (reg == RBSEL && count > 1)
245 return spi_write_then_read(ctx->spi, ®, sizeof(reg), data, count);
247 EXPORT_SYMBOL_GPL(regmap_encx24j600_spi_read);
249 static int regmap_encx24j600_write(void *context, const void *data,
252 u8 *dout = (u8 *)data;
258 return regmap_encx24j600_spi_write(context, reg, dout, len);
263 return regmap_encx24j600_sfr_write(context, reg, dout, len);
266 static int regmap_encx24j600_read(void *context,
267 const void *reg_buf, size_t reg_size,
268 void *val, size_t val_size)
270 u8 reg = *(const u8 *)reg_buf;
273 pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size);
278 return regmap_encx24j600_spi_read(context, reg, val, val_size);
281 pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size);
285 return regmap_encx24j600_sfr_read(context, reg, val, val_size);
288 static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg)
291 ((reg >= 0x40) && (reg < 0x4c)) ||
292 ((reg >= 0x52) && (reg < 0x56)) ||
293 ((reg >= 0x60) && (reg < 0x66)) ||
294 ((reg >= 0x68) && (reg < 0x80)) ||
295 ((reg >= 0x86) && (reg < 0x92)) ||
302 static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg)
305 ((reg >= 0x14) && (reg < 0x1a)) ||
306 ((reg >= 0x1c) && (reg < 0x36)) ||
307 ((reg >= 0x40) && (reg < 0x4c)) ||
308 ((reg >= 0x52) && (reg < 0x56)) ||
309 ((reg >= 0x60) && (reg < 0x68)) ||
310 ((reg >= 0x6c) && (reg < 0x80)) ||
311 ((reg >= 0x86) && (reg < 0x92)) ||
312 ((reg >= 0xc0) && (reg < 0xc8)) ||
313 ((reg >= 0xca) && (reg < 0xf0)))
319 static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg)
326 case ECON1: /* Can be modified via single byte cmds */
327 case ECON2: /* Can be modified via single byte cmds */
329 case EIR: /* Can be modified via single byte cmds */
340 static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg)
342 /* single byte cmds are precious */
343 if (((reg >= 0xc0) && (reg < 0xc8)) ||
344 ((reg >= 0xca) && (reg < 0xf0)))
350 static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg,
353 struct encx24j600_context *ctx = context;
357 reg = MIREGADR_VAL | (reg & PHREG_MASK);
358 ret = regmap_write(ctx->regmap, MIREGADR, reg);
362 ret = regmap_write(ctx->regmap, MICMD, MIIRD);
366 usleep_range(26, 100);
367 while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
374 ret = regmap_write(ctx->regmap, MICMD, 0);
378 ret = regmap_read(ctx->regmap, MIRD, val);
382 pr_err("%s: error %d reading reg %02x\n", __func__, ret,
388 static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg,
391 struct encx24j600_context *ctx = context;
395 reg = MIREGADR_VAL | (reg & PHREG_MASK);
396 ret = regmap_write(ctx->regmap, MIREGADR, reg);
400 ret = regmap_write(ctx->regmap, MIWR, val);
404 usleep_range(26, 100);
405 while ((ret = regmap_read(ctx->regmap, MISTAT, &mistat) != 0) &&
411 pr_err("%s: error %d writing reg %02x=%04x\n", __func__, ret,
412 reg & PHREG_MASK, val);
417 static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg)
434 static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg)
451 static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg)
466 static struct regmap_config regcfg = {
470 .max_register = 0xee,
472 .cache_type = REGCACHE_RBTREE,
473 .val_format_endian = REGMAP_ENDIAN_LITTLE,
474 .readable_reg = encx24j600_regmap_readable,
475 .writeable_reg = encx24j600_regmap_writeable,
476 .volatile_reg = encx24j600_regmap_volatile,
477 .precious_reg = encx24j600_regmap_precious,
478 .lock = regmap_lock_mutex,
479 .unlock = regmap_unlock_mutex,
482 static struct regmap_bus regmap_encx24j600 = {
483 .write = regmap_encx24j600_write,
484 .read = regmap_encx24j600_read,
485 .reg_update_bits = regmap_encx24j600_reg_update_bits,
488 static struct regmap_config phycfg = {
492 .max_register = 0x1f,
493 .cache_type = REGCACHE_RBTREE,
494 .val_format_endian = REGMAP_ENDIAN_LITTLE,
495 .readable_reg = encx24j600_phymap_readable,
496 .writeable_reg = encx24j600_phymap_writeable,
497 .volatile_reg = encx24j600_phymap_volatile,
500 static struct regmap_bus phymap_encx24j600 = {
501 .reg_write = regmap_encx24j600_phy_reg_write,
502 .reg_read = regmap_encx24j600_phy_reg_read,
505 void devm_regmap_init_encx24j600(struct device *dev,
506 struct encx24j600_context *ctx)
508 mutex_init(&ctx->mutex);
509 regcfg.lock_arg = ctx;
510 ctx->regmap = devm_regmap_init(dev, ®map_encx24j600, ctx, ®cfg);
511 ctx->phymap = devm_regmap_init(dev, &phymap_encx24j600, ctx, &phycfg);
513 EXPORT_SYMBOL_GPL(devm_regmap_init_encx24j600);
515 MODULE_LICENSE("GPL");