drivers/net/ethernet/neterion/vxge/vxge-config.c

   1 /******************************************************************************
   2  * This software may be used and distributed according to the terms of
   3  * the GNU General Public License (GPL), incorporated herein by reference.
   4  * Drivers based on or derived from this code fall under the GPL and must
   5  * retain the authorship, copyright and license notice.  This file is not
   6  * a complete program and may only be used when the entire operating
   7  * system is licensed under the GPL.
   8  * See the file COPYING in this distribution for more information.
   9  *
  10  * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
  11  *                Virtualized Server Adapter.
  12  * Copyright(c) 2002-2010 Exar Corp.
  13  ******************************************************************************/
  14 #include <linux/vmalloc.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18
  19 #include "vxge-traffic.h"
  20 #include "vxge-config.h"
  21 #include "vxge-main.h"
  22
  23 #define VXGE_HW_VPATH_STATS_PIO_READ(offset) {                          \
  24         status = __vxge_hw_vpath_stats_access(vpath,                    \
  25                                               VXGE_HW_STATS_OP_READ,    \
  26                                               offset,                   \
  27                                               &val64);                  \
  28         if (status != VXGE_HW_OK)                                       \
  29                 return status;                                          \
  30 }
  31
  32 static void
  33 vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
  34 {
  35         u64 val64;
  36
  37         val64 = readq(&vp_reg->rxmac_vcfg0);
  38         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
  39         writeq(val64, &vp_reg->rxmac_vcfg0);
  40         val64 = readq(&vp_reg->rxmac_vcfg0);
  41 }
  42
  43 /*
  44  * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
  45  */
  46 int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
  47 {
  48         struct vxge_hw_vpath_reg __iomem *vp_reg;
  49         struct __vxge_hw_virtualpath *vpath;
  50         u64 val64, rxd_count, rxd_spat;
  51         int count = 0, total_count = 0;
  52
  53         vpath = &hldev->virtual_paths[vp_id];
  54         vp_reg = vpath->vp_reg;
  55
  56         vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
  57
  58         /* Check that the ring controller for this vpath has enough free RxDs
  59          * to send frames to the host.  This is done by reading the
  60          * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
  61          * RXD_SPAT value for the vpath.
  62          */
  63         val64 = readq(&vp_reg->prc_cfg6);
  64         rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
  65         /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
  66          * leg room.
  67          */
  68         rxd_spat *= 2;
  69
  70         do {
  71                 mdelay(1);
  72
  73                 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
  74
  75                 /* Check that the ring controller for this vpath does
  76                  * not have any frame in its pipeline.
  77                  */
  78                 val64 = readq(&vp_reg->frm_in_progress_cnt);
  79                 if ((rxd_count <= rxd_spat) || (val64 > 0))
  80                         count = 0;
  81                 else
  82                         count++;
  83                 total_count++;
  84         } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
  85                         (total_count < VXGE_HW_MAX_POLLING_COUNT));
  86
  87         if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
  88                 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
  89                         __func__);
  90
  91         return total_count;
  92 }
  93
  94 /* vxge_hw_device_wait_receive_idle - This function waits until all frames
  95  * stored in the frame buffer for each vpath assigned to the given
  96  * function (hldev) have been sent to the host.
  97  */
  98 void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
  99 {
 100         int i, total_count = 0;
 101
 102         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 103                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 104                         continue;
 105
 106                 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
 107                 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
 108                         break;
 109         }
 110 }
 111
 112 /*
 113  * __vxge_hw_device_register_poll
 114  * Will poll certain register for specified amount of time.
 115  * Will poll until masked bit is not cleared.
 116  */
 117 static enum vxge_hw_status
 118 __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
 119 {
 120         u64 val64;
 121         u32 i = 0;
 122
 123         udelay(10);
 124
 125         do {
 126                 val64 = readq(reg);
 127                 if (!(val64 & mask))
 128                         return VXGE_HW_OK;
 129                 udelay(100);
 130         } while (++i <= 9);
 131
 132         i = 0;
 133         do {
 134                 val64 = readq(reg);
 135                 if (!(val64 & mask))
 136                         return VXGE_HW_OK;
 137                 mdelay(1);
 138         } while (++i <= max_millis);
 139
 140         return VXGE_HW_FAIL;
 141 }
 142
 143 static inline enum vxge_hw_status
 144 __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
 145                           u64 mask, u32 max_millis)
 146 {
 147         __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
 148         wmb();
 149         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
 150         wmb();
 151
 152         return __vxge_hw_device_register_poll(addr, mask, max_millis);
 153 }
 154
 155 static enum vxge_hw_status
 156 vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
 157                      u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
 158                      u64 *steer_ctrl)
 159 {
 160         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
 161         enum vxge_hw_status status;
 162         u64 val64;
 163         u32 retry = 0, max_retry = 3;
 164
 165         spin_lock(&vpath->lock);
 166         if (!vpath->vp_open) {
 167                 spin_unlock(&vpath->lock);
 168                 max_retry = 100;
 169         }
 170
 171         writeq(*data0, &vp_reg->rts_access_steer_data0);
 172         writeq(*data1, &vp_reg->rts_access_steer_data1);
 173         wmb();
 174
 175         val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
 176                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
 177                 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
 178                 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
 179                 *steer_ctrl;
 180
 181         status = __vxge_hw_pio_mem_write64(val64,
 182                                            &vp_reg->rts_access_steer_ctrl,
 183                                            VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
 184                                            VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 185
 186         /* The __vxge_hw_device_register_poll can udelay for a significant
 187          * amount of time, blocking other process from the CPU.  If it delays
 188          * for ~5secs, a NMI error can occur.  A way around this is to give up
 189          * the processor via msleep, but this is not allowed is under lock.
 190          * So, only allow it to sleep for ~4secs if open.  Otherwise, delay for
 191          * 1sec and sleep for 10ms until the firmware operation has completed
 192          * or timed-out.
 193          */
 194         while ((status != VXGE_HW_OK) && retry++ < max_retry) {
 195                 if (!vpath->vp_open)
 196                         msleep(20);
 197                 status = __vxge_hw_device_register_poll(
 198                                         &vp_reg->rts_access_steer_ctrl,
 199                                         VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
 200                                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 201         }
 202
 203         if (status != VXGE_HW_OK)
 204                 goto out;
 205
 206         val64 = readq(&vp_reg->rts_access_steer_ctrl);
 207         if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
 208                 *data0 = readq(&vp_reg->rts_access_steer_data0);
 209                 *data1 = readq(&vp_reg->rts_access_steer_data1);
 210                 *steer_ctrl = val64;
 211         } else
 212                 status = VXGE_HW_FAIL;
 213
 214 out:
 215         if (vpath->vp_open)
 216                 spin_unlock(&vpath->lock);
 217         return status;
 218 }
 219
 220 enum vxge_hw_status
 221 vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
 222                              u32 *minor, u32 *build)
 223 {
 224         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 225         struct __vxge_hw_virtualpath *vpath;
 226         enum vxge_hw_status status;
 227
 228         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 229
 230         status = vxge_hw_vpath_fw_api(vpath,
 231                                       VXGE_HW_FW_UPGRADE_ACTION,
 232                                       VXGE_HW_FW_UPGRADE_MEMO,
 233                                       VXGE_HW_FW_UPGRADE_OFFSET_READ,
 234                                       &data0, &data1, &steer_ctrl);
 235         if (status != VXGE_HW_OK)
 236                 return status;
 237
 238         *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
 239         *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
 240         *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
 241
 242         return status;
 243 }
 244
 245 enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
 246 {
 247         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 248         struct __vxge_hw_virtualpath *vpath;
 249         enum vxge_hw_status status;
 250         u32 ret;
 251
 252         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 253
 254         status = vxge_hw_vpath_fw_api(vpath,
 255                                       VXGE_HW_FW_UPGRADE_ACTION,
 256                                       VXGE_HW_FW_UPGRADE_MEMO,
 257                                       VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
 258                                       &data0, &data1, &steer_ctrl);
 259         if (status != VXGE_HW_OK) {
 260                 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
 261                 goto exit;
 262         }
 263
 264         ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
 265         if (ret != 1) {
 266                 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
 267                                 __func__, ret);
 268                 status = VXGE_HW_FAIL;
 269         }
 270
 271 exit:
 272         return status;
 273 }
 274
 275 enum vxge_hw_status
 276 vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
 277 {
 278         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 279         struct __vxge_hw_virtualpath *vpath;
 280         enum vxge_hw_status status;
 281         int ret_code, sec_code;
 282
 283         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 284
 285         /* send upgrade start command */
 286         status = vxge_hw_vpath_fw_api(vpath,
 287                                       VXGE_HW_FW_UPGRADE_ACTION,
 288                                       VXGE_HW_FW_UPGRADE_MEMO,
 289                                       VXGE_HW_FW_UPGRADE_OFFSET_START,
 290                                       &data0, &data1, &steer_ctrl);
 291         if (status != VXGE_HW_OK) {
 292                 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
 293                                 __func__);
 294                 return status;
 295         }
 296
 297         /* Transfer fw image to adapter 16 bytes at a time */
 298         for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
 299                 steer_ctrl = 0;
 300
 301                 /* The next 128bits of fwdata to be loaded onto the adapter */
 302                 data0 = *((u64 *)fwdata);
 303                 data1 = *((u64 *)fwdata + 1);
 304
 305                 status = vxge_hw_vpath_fw_api(vpath,
 306                                               VXGE_HW_FW_UPGRADE_ACTION,
 307                                               VXGE_HW_FW_UPGRADE_MEMO,
 308                                               VXGE_HW_FW_UPGRADE_OFFSET_SEND,
 309                                               &data0, &data1, &steer_ctrl);
 310                 if (status != VXGE_HW_OK) {
 311                         vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
 312                                         __func__);
 313                         goto out;
 314                 }
 315
 316                 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
 317                 switch (ret_code) {
 318                 case VXGE_HW_FW_UPGRADE_OK:
 319                         /* All OK, send next 16 bytes. */
 320                         break;
 321                 case VXGE_FW_UPGRADE_BYTES2SKIP:
 322                         /* skip bytes in the stream */
 323                         fwdata += (data0 >> 8) & 0xFFFFFFFF;
 324                         break;
 325                 case VXGE_HW_FW_UPGRADE_DONE:
 326                         goto out;
 327                 case VXGE_HW_FW_UPGRADE_ERR:
 328                         sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
 329                         switch (sec_code) {
 330                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
 331                         case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
 332                                 printk(KERN_ERR
 333                                        "corrupted data from .ncf file\n");
 334                                 break;
 335                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
 336                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
 337                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
 338                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
 339                         case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
 340                                 printk(KERN_ERR "invalid .ncf file\n");
 341                                 break;
 342                         case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
 343                                 printk(KERN_ERR "buffer overflow\n");
 344                                 break;
 345                         case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
 346                                 printk(KERN_ERR "failed to flash the image\n");
 347                                 break;
 348                         case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
 349                                 printk(KERN_ERR
 350                                        "generic error. Unknown error type\n");
 351                                 break;
 352                         default:
 353                                 printk(KERN_ERR "Unknown error of type %d\n",
 354                                        sec_code);
 355                                 break;
 356                         }
 357                         status = VXGE_HW_FAIL;
 358                         goto out;
 359                 default:
 360                         printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
 361                         status = VXGE_HW_FAIL;
 362                         goto out;
 363                 }
 364                 /* point to next 16 bytes */
 365                 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
 366         }
 367 out:
 368         return status;
 369 }
 370
 371 enum vxge_hw_status
 372 vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
 373                                 struct eprom_image *img)
 374 {
 375         u64 data0 = 0, data1 = 0, steer_ctrl = 0;
 376         struct __vxge_hw_virtualpath *vpath;
 377         enum vxge_hw_status status;
 378         int i;
 379
 380         vpath = &hldev->virtual_paths[hldev->first_vp_id];
 381
 382         for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
 383                 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
 384                 data1 = steer_ctrl = 0;
 385
 386                 status = vxge_hw_vpath_fw_api(vpath,
 387                         VXGE_HW_FW_API_GET_EPROM_REV,
 388                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 389                         0, &data0, &data1, &steer_ctrl);
 390                 if (status != VXGE_HW_OK)
 391                         break;
 392
 393                 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
 394                 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
 395                 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
 396                 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
 397         }
 398
 399         return status;
 400 }
 401
 402 /*
 403  * __vxge_hw_channel_free - Free memory allocated for channel
 404  * This function deallocates memory from the channel and various arrays
 405  * in the channel
 406  */
 407 static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
 408 {
 409         kfree(channel->work_arr);
 410         kfree(channel->free_arr);
 411         kfree(channel->reserve_arr);
 412         kfree(channel->orig_arr);
 413         kfree(channel);
 414 }
 415
 416 /*
 417  * __vxge_hw_channel_initialize - Initialize a channel
 418  * This function initializes a channel by properly setting the
 419  * various references
 420  */
 421 static enum vxge_hw_status
 422 __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
 423 {
 424         u32 i;
 425         struct __vxge_hw_virtualpath *vpath;
 426
 427         vpath = channel->vph->vpath;
 428
 429         if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
 430                 for (i = 0; i < channel->length; i++)
 431                         channel->orig_arr[i] = channel->reserve_arr[i];
 432         }
 433
 434         switch (channel->type) {
 435         case VXGE_HW_CHANNEL_TYPE_FIFO:
 436                 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
 437                 channel->stats = &((struct __vxge_hw_fifo *)
 438                                 channel)->stats->common_stats;
 439                 break;
 440         case VXGE_HW_CHANNEL_TYPE_RING:
 441                 vpath->ringh = (struct __vxge_hw_ring *)channel;
 442                 channel->stats = &((struct __vxge_hw_ring *)
 443                                 channel)->stats->common_stats;
 444                 break;
 445         default:
 446                 break;
 447         }
 448
 449         return VXGE_HW_OK;
 450 }
 451
 452 /*
 453  * __vxge_hw_channel_reset - Resets a channel
 454  * This function resets a channel by properly setting the various references
 455  */
 456 static enum vxge_hw_status
 457 __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
 458 {
 459         u32 i;
 460
 461         for (i = 0; i < channel->length; i++) {
 462                 if (channel->reserve_arr != NULL)
 463                         channel->reserve_arr[i] = channel->orig_arr[i];
 464                 if (channel->free_arr != NULL)
 465                         channel->free_arr[i] = NULL;
 466                 if (channel->work_arr != NULL)
 467                         channel->work_arr[i] = NULL;
 468         }
 469         channel->free_ptr = channel->length;
 470         channel->reserve_ptr = channel->length;
 471         channel->reserve_top = 0;
 472         channel->post_index = 0;
 473         channel->compl_index = 0;
 474
 475         return VXGE_HW_OK;
 476 }
 477
 478 /*
 479  * __vxge_hw_device_pci_e_init
 480  * Initialize certain PCI/PCI-X configuration registers
 481  * with recommended values. Save config space for future hw resets.
 482  */
 483 static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
 484 {
 485         u16 cmd = 0;
 486
 487         /* Set the PErr Repconse bit and SERR in PCI command register. */
 488         pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
 489         cmd |= 0x140;
 490         pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
 491
 492         pci_save_state(hldev->pdev);
 493 }
 494
 495 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
 496  * in progress
 497  * This routine checks the vpath reset in progress register is turned zero
 498  */
 499 static enum vxge_hw_status
 500 __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
 501 {
 502         enum vxge_hw_status status;
 503         status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
 504                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
 505                         VXGE_HW_DEF_DEVICE_POLL_MILLIS);
 506         return status;
 507 }
 508
 509 /*
 510  * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
 511  * Set the swapper bits appropriately for the lagacy section.
 512  */
 513 static enum vxge_hw_status
 514 __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
 515 {
 516         u64 val64;
 517         enum vxge_hw_status status = VXGE_HW_OK;
 518
 519         val64 = readq(&legacy_reg->toc_swapper_fb);
 520
 521         wmb();
 522
 523         switch (val64) {
 524         case VXGE_HW_SWAPPER_INITIAL_VALUE:
 525                 return status;
 526
 527         case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
 528                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
 529                         &legacy_reg->pifm_rd_swap_en);
 530                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
 531                         &legacy_reg->pifm_rd_flip_en);
 532                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
 533                         &legacy_reg->pifm_wr_swap_en);
 534                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
 535                         &legacy_reg->pifm_wr_flip_en);
 536                 break;
 537
 538         case VXGE_HW_SWAPPER_BYTE_SWAPPED:
 539                 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
 540                         &legacy_reg->pifm_rd_swap_en);
 541                 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
 542                         &legacy_reg->pifm_wr_swap_en);
 543                 break;
 544
 545         case VXGE_HW_SWAPPER_BIT_FLIPPED:
 546                 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
 547                         &legacy_reg->pifm_rd_flip_en);
 548                 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
 549                         &legacy_reg->pifm_wr_flip_en);
 550                 break;
 551         }
 552
 553         wmb();
 554
 555         val64 = readq(&legacy_reg->toc_swapper_fb);
 556
 557         if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
 558                 status = VXGE_HW_ERR_SWAPPER_CTRL;
 559
 560         return status;
 561 }
 562
 563 /*
 564  * __vxge_hw_device_toc_get
 565  * This routine sets the swapper and reads the toc pointer and returns the
 566  * memory mapped address of the toc
 567  */
 568 static struct vxge_hw_toc_reg __iomem *
 569 __vxge_hw_device_toc_get(void __iomem *bar0)
 570 {
 571         u64 val64;
 572         struct vxge_hw_toc_reg __iomem *toc = NULL;
 573         enum vxge_hw_status status;
 574
 575         struct vxge_hw_legacy_reg __iomem *legacy_reg =
 576                 (struct vxge_hw_legacy_reg __iomem *)bar0;
 577
 578         status = __vxge_hw_legacy_swapper_set(legacy_reg);
 579         if (status != VXGE_HW_OK)
 580                 goto exit;
 581
 582         val64 = readq(&legacy_reg->toc_first_pointer);
 583         toc = bar0 + val64;
 584 exit:
 585         return toc;
 586 }
 587
 588 /*
 589  * __vxge_hw_device_reg_addr_get
 590  * This routine sets the swapper and reads the toc pointer and initializes the
 591  * register location pointers in the device object. It waits until the ric is
 592  * completed initializing registers.
 593  */
 594 static enum vxge_hw_status
 595 __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
 596 {
 597         u64 val64;
 598         u32 i;
 599         enum vxge_hw_status status = VXGE_HW_OK;
 600
 601         hldev->legacy_reg = hldev->bar0;
 602
 603         hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
 604         if (hldev->toc_reg  == NULL) {
 605                 status = VXGE_HW_FAIL;
 606                 goto exit;
 607         }
 608
 609         val64 = readq(&hldev->toc_reg->toc_common_pointer);
 610         hldev->common_reg = hldev->bar0 + val64;
 611
 612         val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
 613         hldev->mrpcim_reg = hldev->bar0 + val64;
 614
 615         for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
 616                 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
 617                 hldev->srpcim_reg[i] = hldev->bar0 + val64;
 618         }
 619
 620         for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
 621                 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
 622                 hldev->vpmgmt_reg[i] = hldev->bar0 + val64;
 623         }
 624
 625         for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
 626                 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
 627                 hldev->vpath_reg[i] = hldev->bar0 + val64;
 628         }
 629
 630         val64 = readq(&hldev->toc_reg->toc_kdfc);
 631
 632         switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
 633         case 0:
 634                 hldev->kdfc = hldev->bar0 + VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64) ;
 635                 break;
 636         default:
 637                 break;
 638         }
 639
 640         status = __vxge_hw_device_vpath_reset_in_prog_check(
 641                         (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
 642 exit:
 643         return status;
 644 }
 645
 646 /*
 647  * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
 648  * This routine returns the Access Rights of the driver
 649  */
 650 static u32
 651 __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
 652 {
 653         u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
 654
 655         switch (host_type) {
 656         case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
 657                 if (func_id == 0) {
 658                         access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 659                                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 660                 }
 661                 break;
 662         case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
 663                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 664                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 665                 break;
 666         case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
 667                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
 668                                 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 669                 break;
 670         case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
 671         case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
 672         case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
 673                 break;
 674         case VXGE_HW_SR_VH_FUNCTION0:
 675         case VXGE_HW_VH_NORMAL_FUNCTION:
 676                 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
 677                 break;
 678         }
 679
 680         return access_rights;
 681 }
 682 /*
 683  * __vxge_hw_device_is_privilaged
 684  * This routine checks if the device function is privilaged or not
 685  */
 686
 687 enum vxge_hw_status
 688 __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
 689 {
 690         if (__vxge_hw_device_access_rights_get(host_type,
 691                 func_id) &
 692                 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
 693                 return VXGE_HW_OK;
 694         else
 695                 return VXGE_HW_ERR_PRIVILEGED_OPERATION;
 696 }
 697
 698 /*
 699  * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
 700  * Returns the function number of the vpath.
 701  */
 702 static u32
 703 __vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
 704 {
 705         u64 val64;
 706
 707         val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
 708
 709         return
 710          (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
 711 }
 712
 713 /*
 714  * __vxge_hw_device_host_info_get
 715  * This routine returns the host type assignments
 716  */
 717 static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
 718 {
 719         u64 val64;
 720         u32 i;
 721
 722         val64 = readq(&hldev->common_reg->host_type_assignments);
 723
 724         hldev->host_type =
 725            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
 726
 727         hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
 728
 729         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 730                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
 731                         continue;
 732
 733                 hldev->func_id =
 734                         __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
 735
 736                 hldev->access_rights = __vxge_hw_device_access_rights_get(
 737                         hldev->host_type, hldev->func_id);
 738
 739                 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
 740                 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
 741
 742                 hldev->first_vp_id = i;
 743                 break;
 744         }
 745 }
 746
 747 /*
 748  * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
 749  * link width and signalling rate.
 750  */
 751 static enum vxge_hw_status
 752 __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
 753 {
 754         struct pci_dev *dev = hldev->pdev;
 755         u16 lnk;
 756
 757         /* Get the negotiated link width and speed from PCI config space */
 758         pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
 759
 760         if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
 761                 return VXGE_HW_ERR_INVALID_PCI_INFO;
 762
 763         switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
 764         case PCIE_LNK_WIDTH_RESRV:
 765         case PCIE_LNK_X1:
 766         case PCIE_LNK_X2:
 767         case PCIE_LNK_X4:
 768         case PCIE_LNK_X8:
 769                 break;
 770         default:
 771                 return VXGE_HW_ERR_INVALID_PCI_INFO;
 772         }
 773
 774         return VXGE_HW_OK;
 775 }
 776
 777 /*
 778  * __vxge_hw_device_initialize
 779  * Initialize Titan-V hardware.
 780  */
 781 static enum vxge_hw_status
 782 __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
 783 {
 784         enum vxge_hw_status status = VXGE_HW_OK;
 785
 786         if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
 787                                 hldev->func_id)) {
 788                 /* Validate the pci-e link width and speed */
 789                 status = __vxge_hw_verify_pci_e_info(hldev);
 790                 if (status != VXGE_HW_OK)
 791                         goto exit;
 792         }
 793
 794 exit:
 795         return status;
 796 }
 797
 798 /*
 799  * __vxge_hw_vpath_fw_ver_get - Get the fw version
 800  * Returns FW Version
 801  */
 802 static enum vxge_hw_status
 803 __vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
 804                            struct vxge_hw_device_hw_info *hw_info)
 805 {
 806         struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
 807         struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
 808         struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
 809         struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
 810         u64 data0, data1 = 0, steer_ctrl = 0;
 811         enum vxge_hw_status status;
 812
 813         status = vxge_hw_vpath_fw_api(vpath,
 814                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
 815                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 816                         0, &data0, &data1, &steer_ctrl);
 817         if (status != VXGE_HW_OK)
 818                 goto exit;
 819
 820         fw_date->day =
 821             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
 822         fw_date->month =
 823             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
 824         fw_date->year =
 825             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
 826
 827         snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
 828                  fw_date->month, fw_date->day, fw_date->year);
 829
 830         fw_version->major =
 831             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
 832         fw_version->minor =
 833             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
 834         fw_version->build =
 835             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
 836
 837         snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
 838                  fw_version->major, fw_version->minor, fw_version->build);
 839
 840         flash_date->day =
 841             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
 842         flash_date->month =
 843             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
 844         flash_date->year =
 845             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
 846
 847         snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
 848                  flash_date->month, flash_date->day, flash_date->year);
 849
 850         flash_version->major =
 851             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
 852         flash_version->minor =
 853             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
 854         flash_version->build =
 855             (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
 856
 857         snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
 858                  flash_version->major, flash_version->minor,
 859                  flash_version->build);
 860
 861 exit:
 862         return status;
 863 }
 864
 865 /*
 866  * __vxge_hw_vpath_card_info_get - Get the serial numbers,
 867  * part number and product description.
 868  */
 869 static enum vxge_hw_status
 870 __vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
 871                               struct vxge_hw_device_hw_info *hw_info)
 872 {
 873         enum vxge_hw_status status;
 874         u64 data0, data1 = 0, steer_ctrl = 0;
 875         u8 *serial_number = hw_info->serial_number;
 876         u8 *part_number = hw_info->part_number;
 877         u8 *product_desc = hw_info->product_desc;
 878         u32 i, j = 0;
 879
 880         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
 881
 882         status = vxge_hw_vpath_fw_api(vpath,
 883                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 884                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 885                         0, &data0, &data1, &steer_ctrl);
 886         if (status != VXGE_HW_OK)
 887                 return status;
 888
 889         ((u64 *)serial_number)[0] = be64_to_cpu(data0);
 890         ((u64 *)serial_number)[1] = be64_to_cpu(data1);
 891
 892         data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
 893         data1 = steer_ctrl = 0;
 894
 895         status = vxge_hw_vpath_fw_api(vpath,
 896                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 897                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 898                         0, &data0, &data1, &steer_ctrl);
 899         if (status != VXGE_HW_OK)
 900                 return status;
 901
 902         ((u64 *)part_number)[0] = be64_to_cpu(data0);
 903         ((u64 *)part_number)[1] = be64_to_cpu(data1);
 904
 905         for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
 906              i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
 907                 data0 = i;
 908                 data1 = steer_ctrl = 0;
 909
 910                 status = vxge_hw_vpath_fw_api(vpath,
 911                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
 912                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 913                         0, &data0, &data1, &steer_ctrl);
 914                 if (status != VXGE_HW_OK)
 915                         return status;
 916
 917                 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
 918                 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
 919         }
 920
 921         return status;
 922 }
 923
 924 /*
 925  * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
 926  * Returns pci function mode
 927  */
 928 static enum vxge_hw_status
 929 __vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
 930                                   struct vxge_hw_device_hw_info *hw_info)
 931 {
 932         u64 data0, data1 = 0, steer_ctrl = 0;
 933         enum vxge_hw_status status;
 934
 935         data0 = 0;
 936
 937         status = vxge_hw_vpath_fw_api(vpath,
 938                         VXGE_HW_FW_API_GET_FUNC_MODE,
 939                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
 940                         0, &data0, &data1, &steer_ctrl);
 941         if (status != VXGE_HW_OK)
 942                 return status;
 943
 944         hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
 945         return status;
 946 }
 947
 948 /*
 949  * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
 950  *               from MAC address table.
 951  */
 952 static enum vxge_hw_status
 953 __vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
 954                          u8 *macaddr, u8 *macaddr_mask)
 955 {
 956         u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
 957             data0 = 0, data1 = 0, steer_ctrl = 0;
 958         enum vxge_hw_status status;
 959         int i;
 960
 961         do {
 962                 status = vxge_hw_vpath_fw_api(vpath, action,
 963                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
 964                         0, &data0, &data1, &steer_ctrl);
 965                 if (status != VXGE_HW_OK)
 966                         goto exit;
 967
 968                 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
 969                 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
 970                                                                         data1);
 971
 972                 for (i = ETH_ALEN; i > 0; i--) {
 973                         macaddr[i - 1] = (u8) (data0 & 0xFF);
 974                         data0 >>= 8;
 975
 976                         macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
 977                         data1 >>= 8;
 978                 }
 979
 980                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
 981                 data0 = 0, data1 = 0, steer_ctrl = 0;
 982
 983         } while (!is_valid_ether_addr(macaddr));
 984 exit:
 985         return status;
 986 }
 987
 988 /**
 989  * vxge_hw_device_hw_info_get - Get the hw information
 990  * Returns the vpath mask that has the bits set for each vpath allocated
 991  * for the driver, FW version information, and the first mac address for
 992  * each vpath
 993  */
 994 enum vxge_hw_status
 995 vxge_hw_device_hw_info_get(void __iomem *bar0,
 996                            struct vxge_hw_device_hw_info *hw_info)
 997 {
 998         u32 i;
 999         u64 val64;
1000         struct vxge_hw_toc_reg __iomem *toc;
1001         struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1002         struct vxge_hw_common_reg __iomem *common_reg;
1003         struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1004         enum vxge_hw_status status;
1005         struct __vxge_hw_virtualpath vpath;
1006
1007         memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1008
1009         toc = __vxge_hw_device_toc_get(bar0);
1010         if (toc == NULL) {
1011                 status = VXGE_HW_ERR_CRITICAL;
1012                 goto exit;
1013         }
1014
1015         val64 = readq(&toc->toc_common_pointer);
1016         common_reg = bar0 + val64;
1017
1018         status = __vxge_hw_device_vpath_reset_in_prog_check(
1019                 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1020         if (status != VXGE_HW_OK)
1021                 goto exit;
1022
1023         hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1024
1025         val64 = readq(&common_reg->host_type_assignments);
1026
1027         hw_info->host_type =
1028            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1029
1030         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1031                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1032                         continue;
1033
1034                 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1035
1036                 vpmgmt_reg = bar0 + val64;
1037
1038                 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
1039                 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1040                         hw_info->func_id) &
1041                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1042
1043                         val64 = readq(&toc->toc_mrpcim_pointer);
1044
1045                         mrpcim_reg = bar0 + val64;
1046
1047                         writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1048                         wmb();
1049                 }
1050
1051                 val64 = readq(&toc->toc_vpath_pointer[i]);
1052
1053                 spin_lock_init(&vpath.lock);
1054                 vpath.vp_reg = bar0 + val64;
1055                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1056
1057                 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1058                 if (status != VXGE_HW_OK)
1059                         goto exit;
1060
1061                 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
1062                 if (status != VXGE_HW_OK)
1063                         goto exit;
1064
1065                 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
1066                 if (status != VXGE_HW_OK)
1067                         goto exit;
1068
1069                 break;
1070         }
1071
1072         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1073                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1074                         continue;
1075
1076                 val64 = readq(&toc->toc_vpath_pointer[i]);
1077                 vpath.vp_reg = bar0 + val64;
1078                 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
1079
1080                 status =  __vxge_hw_vpath_addr_get(&vpath,
1081                                 hw_info->mac_addrs[i],
1082                                 hw_info->mac_addr_masks[i]);
1083                 if (status != VXGE_HW_OK)
1084                         goto exit;
1085         }
1086 exit:
1087         return status;
1088 }
1089
1090 /*
1091  * __vxge_hw_blockpool_destroy - Deallocates the block pool
1092  */
1093 static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
1094 {
1095         struct __vxge_hw_device *hldev;
1096         struct list_head *p, *n;
1097         u16 ret;
1098
1099         if (blockpool == NULL) {
1100                 ret = 1;
1101                 goto exit;
1102         }
1103
1104         hldev = blockpool->hldev;
1105
1106         list_for_each_safe(p, n, &blockpool->free_block_list) {
1107                 pci_unmap_single(hldev->pdev,
1108                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
1109                         ((struct __vxge_hw_blockpool_entry *)p)->length,
1110                         PCI_DMA_BIDIRECTIONAL);
1111
1112                 vxge_os_dma_free(hldev->pdev,
1113                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
1114                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
1115
1116                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1117                 kfree(p);
1118                 blockpool->pool_size--;
1119         }
1120
1121         list_for_each_safe(p, n, &blockpool->free_entry_list) {
1122                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1123                 kfree((void *)p);
1124         }
1125         ret = 0;
1126 exit:
1127         return;
1128 }
1129
1130 /*
1131  * __vxge_hw_blockpool_create - Create block pool
1132  */
1133 static enum vxge_hw_status
1134 __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1135                            struct __vxge_hw_blockpool *blockpool,
1136                            u32 pool_size,
1137                            u32 pool_max)
1138 {
1139         u32 i;
1140         struct __vxge_hw_blockpool_entry *entry = NULL;
1141         void *memblock;
1142         dma_addr_t dma_addr;
1143         struct pci_dev *dma_handle;
1144         struct pci_dev *acc_handle;
1145         enum vxge_hw_status status = VXGE_HW_OK;
1146
1147         if (blockpool == NULL) {
1148                 status = VXGE_HW_FAIL;
1149                 goto blockpool_create_exit;
1150         }
1151
1152         blockpool->hldev = hldev;
1153         blockpool->block_size = VXGE_HW_BLOCK_SIZE;
1154         blockpool->pool_size = 0;
1155         blockpool->pool_max = pool_max;
1156         blockpool->req_out = 0;
1157
1158         INIT_LIST_HEAD(&blockpool->free_block_list);
1159         INIT_LIST_HEAD(&blockpool->free_entry_list);
1160
1161         for (i = 0; i < pool_size + pool_max; i++) {
1162                 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1163                                 GFP_KERNEL);
1164                 if (entry == NULL) {
1165                         __vxge_hw_blockpool_destroy(blockpool);
1166                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1167                         goto blockpool_create_exit;
1168                 }
1169                 list_add(&entry->item, &blockpool->free_entry_list);
1170         }
1171
1172         for (i = 0; i < pool_size; i++) {
1173                 memblock = vxge_os_dma_malloc(
1174                                 hldev->pdev,
1175                                 VXGE_HW_BLOCK_SIZE,
1176                                 &dma_handle,
1177                                 &acc_handle);
1178                 if (memblock == NULL) {
1179                         __vxge_hw_blockpool_destroy(blockpool);
1180                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1181                         goto blockpool_create_exit;
1182                 }
1183
1184                 dma_addr = pci_map_single(hldev->pdev, memblock,
1185                                 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
1186                 if (unlikely(pci_dma_mapping_error(hldev->pdev,
1187                                 dma_addr))) {
1188                         vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
1189                         __vxge_hw_blockpool_destroy(blockpool);
1190                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1191                         goto blockpool_create_exit;
1192                 }
1193
1194                 if (!list_empty(&blockpool->free_entry_list))
1195                         entry = (struct __vxge_hw_blockpool_entry *)
1196                                 list_first_entry(&blockpool->free_entry_list,
1197                                         struct __vxge_hw_blockpool_entry,
1198                                         item);
1199
1200                 if (entry == NULL)
1201                         entry =
1202                             kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1203                                         GFP_KERNEL);
1204                 if (entry != NULL) {
1205                         list_del(&entry->item);
1206                         entry->length = VXGE_HW_BLOCK_SIZE;
1207                         entry->memblock = memblock;
1208                         entry->dma_addr = dma_addr;
1209                         entry->acc_handle = acc_handle;
1210                         entry->dma_handle = dma_handle;
1211                         list_add(&entry->item,
1212                                           &blockpool->free_block_list);
1213                         blockpool->pool_size++;
1214                 } else {
1215                         __vxge_hw_blockpool_destroy(blockpool);
1216                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
1217                         goto blockpool_create_exit;
1218                 }
1219         }
1220
1221 blockpool_create_exit:
1222         return status;
1223 }
1224
1225 /*
1226  * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1227  * Check the fifo configuration
1228  */
1229 static enum vxge_hw_status
1230 __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1231 {
1232         if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1233             (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1234                 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1235
1236         return VXGE_HW_OK;
1237 }
1238
1239 /*
1240  * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1241  * Check the vpath configuration
1242  */
1243 static enum vxge_hw_status
1244 __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1245 {
1246         enum vxge_hw_status status;
1247
1248         if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1249             (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
1250                 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1251
1252         status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1253         if (status != VXGE_HW_OK)
1254                 return status;
1255
1256         if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1257                 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1258                 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1259                 return VXGE_HW_BADCFG_VPATH_MTU;
1260
1261         if ((vp_config->rpa_strip_vlan_tag !=
1262                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1263                 (vp_config->rpa_strip_vlan_tag !=
1264                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1265                 (vp_config->rpa_strip_vlan_tag !=
1266                 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1267                 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1268
1269         return VXGE_HW_OK;
1270 }
1271
1272 /*
1273  * __vxge_hw_device_config_check - Check device configuration.
1274  * Check the device configuration
1275  */
1276 static enum vxge_hw_status
1277 __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1278 {
1279         u32 i;
1280         enum vxge_hw_status status;
1281
1282         if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1283             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1284             (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1285             (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1286                 return VXGE_HW_BADCFG_INTR_MODE;
1287
1288         if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1289             (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1290                 return VXGE_HW_BADCFG_RTS_MAC_EN;
1291
1292         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1293                 status = __vxge_hw_device_vpath_config_check(
1294                                 &new_config->vp_config[i]);
1295                 if (status != VXGE_HW_OK)
1296                         return status;
1297         }
1298
1299         return VXGE_HW_OK;
1300 }
1301
1302 /*
1303  * vxge_hw_device_initialize - Initialize Titan device.
1304  * Initialize Titan device. Note that all the arguments of this public API
1305  * are 'IN', including @hldev. Driver cooperates with
1306  * OS to find new Titan device, locate its PCI and memory spaces.
1307  *
1308  * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1309  * to enable the latter to perform Titan hardware initialization.
1310  */
1311 enum vxge_hw_status
1312 vxge_hw_device_initialize(
1313         struct __vxge_hw_device **devh,
1314         struct vxge_hw_device_attr *attr,
1315         struct vxge_hw_device_config *device_config)
1316 {
1317         u32 i;
1318         u32 nblocks = 0;
1319         struct __vxge_hw_device *hldev = NULL;
1320         enum vxge_hw_status status = VXGE_HW_OK;
1321
1322         status = __vxge_hw_device_config_check(device_config);
1323         if (status != VXGE_HW_OK)
1324                 goto exit;
1325
1326         hldev = vzalloc(sizeof(struct __vxge_hw_device));
1327         if (hldev == NULL) {
1328                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1329                 goto exit;
1330         }
1331
1332         hldev->magic = VXGE_HW_DEVICE_MAGIC;
1333
1334         vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1335
1336         /* apply config */
1337         memcpy(&hldev->config, device_config,
1338                 sizeof(struct vxge_hw_device_config));
1339
1340         hldev->bar0 = attr->bar0;
1341         hldev->pdev = attr->pdev;
1342
1343         hldev->uld_callbacks = attr->uld_callbacks;
1344
1345         __vxge_hw_device_pci_e_init(hldev);
1346
1347         status = __vxge_hw_device_reg_addr_get(hldev);
1348         if (status != VXGE_HW_OK) {
1349                 vfree(hldev);
1350                 goto exit;
1351         }
1352
1353         __vxge_hw_device_host_info_get(hldev);
1354
1355         /* Incrementing for stats blocks */
1356         nblocks++;
1357
1358         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1359                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1360                         continue;
1361
1362                 if (device_config->vp_config[i].ring.enable ==
1363                         VXGE_HW_RING_ENABLE)
1364                         nblocks += device_config->vp_config[i].ring.ring_blocks;
1365
1366                 if (device_config->vp_config[i].fifo.enable ==
1367                         VXGE_HW_FIFO_ENABLE)
1368                         nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1369                 nblocks++;
1370         }
1371
1372         if (__vxge_hw_blockpool_create(hldev,
1373                 &hldev->block_pool,
1374                 device_config->dma_blockpool_initial + nblocks,
1375                 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1376
1377                 vxge_hw_device_terminate(hldev);
1378                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1379                 goto exit;
1380         }
1381
1382         status = __vxge_hw_device_initialize(hldev);
1383         if (status != VXGE_HW_OK) {
1384                 vxge_hw_device_terminate(hldev);
1385                 goto exit;
1386         }
1387
1388         *devh = hldev;
1389 exit:
1390         return status;
1391 }
1392
1393 /*
1394  * vxge_hw_device_terminate - Terminate Titan device.
1395  * Terminate HW device.
1396  */
1397 void
1398 vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1399 {
1400         vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1401
1402         hldev->magic = VXGE_HW_DEVICE_DEAD;
1403         __vxge_hw_blockpool_destroy(&hldev->block_pool);
1404         vfree(hldev);
1405 }
1406
1407 /*
1408  * __vxge_hw_vpath_stats_access - Get the statistics from the given location
1409  *                           and offset and perform an operation
1410  */
1411 static enum vxge_hw_status
1412 __vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
1413                              u32 operation, u32 offset, u64 *stat)
1414 {
1415         u64 val64;
1416         enum vxge_hw_status status = VXGE_HW_OK;
1417         struct vxge_hw_vpath_reg __iomem *vp_reg;
1418
1419         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1420                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1421                 goto vpath_stats_access_exit;
1422         }
1423
1424         vp_reg = vpath->vp_reg;
1425
1426         val64 =  VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
1427                  VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
1428                  VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
1429
1430         status = __vxge_hw_pio_mem_write64(val64,
1431                                 &vp_reg->xmac_stats_access_cmd,
1432                                 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
1433                                 vpath->hldev->config.device_poll_millis);
1434         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1435                 *stat = readq(&vp_reg->xmac_stats_access_data);
1436         else
1437                 *stat = 0;
1438
1439 vpath_stats_access_exit:
1440         return status;
1441 }
1442
1443 /*
1444  * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
1445  */
1446 static enum vxge_hw_status
1447 __vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
1448                         struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
1449 {
1450         u64 *val64;
1451         int i;
1452         u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
1453         enum vxge_hw_status status = VXGE_HW_OK;
1454
1455         val64 = (u64 *)vpath_tx_stats;
1456
1457         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1458                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1459                 goto exit;
1460         }
1461
1462         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
1463                 status = __vxge_hw_vpath_stats_access(vpath,
1464                                         VXGE_HW_STATS_OP_READ,
1465                                         offset, val64);
1466                 if (status != VXGE_HW_OK)
1467                         goto exit;
1468                 offset++;
1469                 val64++;
1470         }
1471 exit:
1472         return status;
1473 }
1474
1475 /*
1476  * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
1477  */
1478 static enum vxge_hw_status
1479 __vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
1480                         struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
1481 {
1482         u64 *val64;
1483         enum vxge_hw_status status = VXGE_HW_OK;
1484         int i;
1485         u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
1486         val64 = (u64 *) vpath_rx_stats;
1487
1488         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1489                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1490                 goto exit;
1491         }
1492         for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
1493                 status = __vxge_hw_vpath_stats_access(vpath,
1494                                         VXGE_HW_STATS_OP_READ,
1495                                         offset >> 3, val64);
1496                 if (status != VXGE_HW_OK)
1497                         goto exit;
1498
1499                 offset += 8;
1500                 val64++;
1501         }
1502 exit:
1503         return status;
1504 }
1505
1506 /*
1507  * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
1508  */
1509 static enum vxge_hw_status
1510 __vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
1511                           struct vxge_hw_vpath_stats_hw_info *hw_stats)
1512 {
1513         u64 val64;
1514         enum vxge_hw_status status = VXGE_HW_OK;
1515         struct vxge_hw_vpath_reg __iomem *vp_reg;
1516
1517         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1518                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1519                 goto exit;
1520         }
1521         vp_reg = vpath->vp_reg;
1522
1523         val64 = readq(&vp_reg->vpath_debug_stats0);
1524         hw_stats->ini_num_mwr_sent =
1525                 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
1526
1527         val64 = readq(&vp_reg->vpath_debug_stats1);
1528         hw_stats->ini_num_mrd_sent =
1529                 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
1530
1531         val64 = readq(&vp_reg->vpath_debug_stats2);
1532         hw_stats->ini_num_cpl_rcvd =
1533                 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
1534
1535         val64 = readq(&vp_reg->vpath_debug_stats3);
1536         hw_stats->ini_num_mwr_byte_sent =
1537                 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
1538
1539         val64 = readq(&vp_reg->vpath_debug_stats4);
1540         hw_stats->ini_num_cpl_byte_rcvd =
1541                 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
1542
1543         val64 = readq(&vp_reg->vpath_debug_stats5);
1544         hw_stats->wrcrdtarb_xoff =
1545                 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
1546
1547         val64 = readq(&vp_reg->vpath_debug_stats6);
1548         hw_stats->rdcrdtarb_xoff =
1549                 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
1550
1551         val64 = readq(&vp_reg->vpath_genstats_count01);
1552         hw_stats->vpath_genstats_count0 =
1553         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
1554                 val64);
1555
1556         val64 = readq(&vp_reg->vpath_genstats_count01);
1557         hw_stats->vpath_genstats_count1 =
1558         (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
1559                 val64);
1560
1561         val64 = readq(&vp_reg->vpath_genstats_count23);
1562         hw_stats->vpath_genstats_count2 =
1563         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
1564                 val64);
1565
1566         val64 = readq(&vp_reg->vpath_genstats_count01);
1567         hw_stats->vpath_genstats_count3 =
1568         (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
1569                 val64);
1570
1571         val64 = readq(&vp_reg->vpath_genstats_count4);
1572         hw_stats->vpath_genstats_count4 =
1573         (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
1574                 val64);
1575
1576         val64 = readq(&vp_reg->vpath_genstats_count5);
1577         hw_stats->vpath_genstats_count5 =
1578         (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
1579                 val64);
1580
1581         status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
1582         if (status != VXGE_HW_OK)
1583                 goto exit;
1584
1585         status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
1586         if (status != VXGE_HW_OK)
1587                 goto exit;
1588
1589         VXGE_HW_VPATH_STATS_PIO_READ(
1590                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
1591
1592         hw_stats->prog_event_vnum0 =
1593                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
1594
1595         hw_stats->prog_event_vnum1 =
1596                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
1597
1598         VXGE_HW_VPATH_STATS_PIO_READ(
1599                 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
1600
1601         hw_stats->prog_event_vnum2 =
1602                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
1603
1604         hw_stats->prog_event_vnum3 =
1605                         (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
1606
1607         val64 = readq(&vp_reg->rx_multi_cast_stats);
1608         hw_stats->rx_multi_cast_frame_discard =
1609                 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
1610
1611         val64 = readq(&vp_reg->rx_frm_transferred);
1612         hw_stats->rx_frm_transferred =
1613                 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
1614
1615         val64 = readq(&vp_reg->rxd_returned);
1616         hw_stats->rxd_returned =
1617                 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
1618
1619         val64 = readq(&vp_reg->dbg_stats_rx_mpa);
1620         hw_stats->rx_mpa_len_fail_frms =
1621                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
1622         hw_stats->rx_mpa_mrk_fail_frms =
1623                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
1624         hw_stats->rx_mpa_crc_fail_frms =
1625                 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
1626
1627         val64 = readq(&vp_reg->dbg_stats_rx_fau);
1628         hw_stats->rx_permitted_frms =
1629                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
1630         hw_stats->rx_vp_reset_discarded_frms =
1631         (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
1632         hw_stats->rx_wol_frms =
1633                 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
1634
1635         val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
1636         hw_stats->tx_vp_reset_discarded_frms =
1637         (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
1638                 val64);
1639 exit:
1640         return status;
1641 }
1642
1643 /*
1644  * vxge_hw_device_stats_get - Get the device hw statistics.
1645  * Returns the vpath h/w stats for the device.
1646  */
1647 enum vxge_hw_status
1648 vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1649                         struct vxge_hw_device_stats_hw_info *hw_stats)
1650 {
1651         u32 i;
1652         enum vxge_hw_status status = VXGE_HW_OK;
1653
1654         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1655                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1656                         (hldev->virtual_paths[i].vp_open ==
1657                                 VXGE_HW_VP_NOT_OPEN))
1658                         continue;
1659
1660                 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1661                                 hldev->virtual_paths[i].hw_stats,
1662                                 sizeof(struct vxge_hw_vpath_stats_hw_info));
1663
1664                 status = __vxge_hw_vpath_stats_get(
1665                         &hldev->virtual_paths[i],
1666                         hldev->virtual_paths[i].hw_stats);
1667         }
1668
1669         memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1670                         sizeof(struct vxge_hw_device_stats_hw_info));
1671
1672         return status;
1673 }
1674
1675 /*
1676  * vxge_hw_driver_stats_get - Get the device sw statistics.
1677  * Returns the vpath s/w stats for the device.
1678  */
1679 enum vxge_hw_status vxge_hw_driver_stats_get(
1680                         struct __vxge_hw_device *hldev,
1681                         struct vxge_hw_device_stats_sw_info *sw_stats)
1682 {
1683         memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1684                 sizeof(struct vxge_hw_device_stats_sw_info));
1685
1686         return VXGE_HW_OK;
1687 }
1688
1689 /*
1690  * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1691  *                           and offset and perform an operation
1692  * Get the statistics from the given location and offset.
1693  */
1694 enum vxge_hw_status
1695 vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1696                             u32 operation, u32 location, u32 offset, u64 *stat)
1697 {
1698         u64 val64;
1699         enum vxge_hw_status status = VXGE_HW_OK;
1700
1701         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1702                         hldev->func_id);
1703         if (status != VXGE_HW_OK)
1704                 goto exit;
1705
1706         val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1707                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1708                 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1709                 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1710
1711         status = __vxge_hw_pio_mem_write64(val64,
1712                                 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1713                                 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1714                                 hldev->config.device_poll_millis);
1715
1716         if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1717                 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1718         else
1719                 *stat = 0;
1720 exit:
1721         return status;
1722 }
1723
1724 /*
1725  * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1726  * Get the Statistics on aggregate port
1727  */
1728 static enum vxge_hw_status
1729 vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1730                                    struct vxge_hw_xmac_aggr_stats *aggr_stats)
1731 {
1732         u64 *val64;
1733         int i;
1734         u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1735         enum vxge_hw_status status = VXGE_HW_OK;
1736
1737         val64 = (u64 *)aggr_stats;
1738
1739         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1740                         hldev->func_id);
1741         if (status != VXGE_HW_OK)
1742                 goto exit;
1743
1744         for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1745                 status = vxge_hw_mrpcim_stats_access(hldev,
1746                                         VXGE_HW_STATS_OP_READ,
1747                                         VXGE_HW_STATS_LOC_AGGR,
1748                                         ((offset + (104 * port)) >> 3), val64);
1749                 if (status != VXGE_HW_OK)
1750                         goto exit;
1751
1752                 offset += 8;
1753                 val64++;
1754         }
1755 exit:
1756         return status;
1757 }
1758
1759 /*
1760  * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1761  * Get the Statistics on port
1762  */
1763 static enum vxge_hw_status
1764 vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1765                                    struct vxge_hw_xmac_port_stats *port_stats)
1766 {
1767         u64 *val64;
1768         enum vxge_hw_status status = VXGE_HW_OK;
1769         int i;
1770         u32 offset = 0x0;
1771         val64 = (u64 *) port_stats;
1772
1773         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1774                         hldev->func_id);
1775         if (status != VXGE_HW_OK)
1776                 goto exit;
1777
1778         for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1779                 status = vxge_hw_mrpcim_stats_access(hldev,
1780                                         VXGE_HW_STATS_OP_READ,
1781                                         VXGE_HW_STATS_LOC_AGGR,
1782                                         ((offset + (608 * port)) >> 3), val64);
1783                 if (status != VXGE_HW_OK)
1784                         goto exit;
1785
1786                 offset += 8;
1787                 val64++;
1788         }
1789
1790 exit:
1791         return status;
1792 }
1793
1794 /*
1795  * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1796  * Get the XMAC Statistics
1797  */
1798 enum vxge_hw_status
1799 vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1800                               struct vxge_hw_xmac_stats *xmac_stats)
1801 {
1802         enum vxge_hw_status status = VXGE_HW_OK;
1803         u32 i;
1804
1805         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1806                                         0, &xmac_stats->aggr_stats[0]);
1807         if (status != VXGE_HW_OK)
1808                 goto exit;
1809
1810         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1811                                 1, &xmac_stats->aggr_stats[1]);
1812         if (status != VXGE_HW_OK)
1813                 goto exit;
1814
1815         for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1816
1817                 status = vxge_hw_device_xmac_port_stats_get(hldev,
1818                                         i, &xmac_stats->port_stats[i]);
1819                 if (status != VXGE_HW_OK)
1820                         goto exit;
1821         }
1822
1823         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1824
1825                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1826                         continue;
1827
1828                 status = __vxge_hw_vpath_xmac_tx_stats_get(
1829                                         &hldev->virtual_paths[i],
1830                                         &xmac_stats->vpath_tx_stats[i]);
1831                 if (status != VXGE_HW_OK)
1832                         goto exit;
1833
1834                 status = __vxge_hw_vpath_xmac_rx_stats_get(
1835                                         &hldev->virtual_paths[i],
1836                                         &xmac_stats->vpath_rx_stats[i]);
1837                 if (status != VXGE_HW_OK)
1838                         goto exit;
1839         }
1840 exit:
1841         return status;
1842 }
1843
1844 /*
1845  * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1846  * This routine is used to dynamically change the debug output
1847  */
1848 void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1849                               enum vxge_debug_level level, u32 mask)
1850 {
1851         if (hldev == NULL)
1852                 return;
1853
1854 #if defined(VXGE_DEBUG_TRACE_MASK) || \
1855         defined(VXGE_DEBUG_ERR_MASK)
1856         hldev->debug_module_mask = mask;
1857         hldev->debug_level = level;
1858 #endif
1859
1860 #if defined(VXGE_DEBUG_ERR_MASK)
1861         hldev->level_err = level & VXGE_ERR;
1862 #endif
1863
1864 #if defined(VXGE_DEBUG_TRACE_MASK)
1865         hldev->level_trace = level & VXGE_TRACE;
1866 #endif
1867 }
1868
1869 /*
1870  * vxge_hw_device_error_level_get - Get the error level
1871  * This routine returns the current error level set
1872  */
1873 u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1874 {
1875 #if defined(VXGE_DEBUG_ERR_MASK)
1876         if (hldev == NULL)
1877                 return VXGE_ERR;
1878         else
1879                 return hldev->level_err;
1880 #else
1881         return 0;
1882 #endif
1883 }
1884
1885 /*
1886  * vxge_hw_device_trace_level_get - Get the trace level
1887  * This routine returns the current trace level set
1888  */
1889 u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1890 {
1891 #if defined(VXGE_DEBUG_TRACE_MASK)
1892         if (hldev == NULL)
1893                 return VXGE_TRACE;
1894         else
1895                 return hldev->level_trace;
1896 #else
1897         return 0;
1898 #endif
1899 }
1900
1901 /*
1902  * vxge_hw_getpause_data -Pause frame frame generation and reception.
1903  * Returns the Pause frame generation and reception capability of the NIC.
1904  */
1905 enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1906                                                  u32 port, u32 *tx, u32 *rx)
1907 {
1908         u64 val64;
1909         enum vxge_hw_status status = VXGE_HW_OK;
1910
1911         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1912                 status = VXGE_HW_ERR_INVALID_DEVICE;
1913                 goto exit;
1914         }
1915
1916         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1917                 status = VXGE_HW_ERR_INVALID_PORT;
1918                 goto exit;
1919         }
1920
1921         if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1922                 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
1923                 goto exit;
1924         }
1925
1926         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1927         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1928                 *tx = 1;
1929         if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1930                 *rx = 1;
1931 exit:
1932         return status;
1933 }
1934
1935 /*
1936  * vxge_hw_device_setpause_data -  set/reset pause frame generation.
1937  * It can be used to set or reset Pause frame generation or reception
1938  * support of the NIC.
1939  */
1940 enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1941                                                  u32 port, u32 tx, u32 rx)
1942 {
1943         u64 val64;
1944         enum vxge_hw_status status = VXGE_HW_OK;
1945
1946         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1947                 status = VXGE_HW_ERR_INVALID_DEVICE;
1948                 goto exit;
1949         }
1950
1951         if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1952                 status = VXGE_HW_ERR_INVALID_PORT;
1953                 goto exit;
1954         }
1955
1956         status = __vxge_hw_device_is_privilaged(hldev->host_type,
1957                         hldev->func_id);
1958         if (status != VXGE_HW_OK)
1959                 goto exit;
1960
1961         val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1962         if (tx)
1963                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1964         else
1965                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1966         if (rx)
1967                 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1968         else
1969                 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1970
1971         writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1972 exit:
1973         return status;
1974 }
1975
1976 u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1977 {
1978         struct pci_dev *dev = hldev->pdev;
1979         u16 lnk;
1980
1981         pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
1982         return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1983 }
1984
1985 /*
1986  * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1987  * This function returns the index of memory block
1988  */
1989 static inline u32
1990 __vxge_hw_ring_block_memblock_idx(u8 *block)
1991 {
1992         return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1993 }
1994
1995 /*
1996  * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1997  * This function sets index to a memory block
1998  */
1999 static inline void
2000 __vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
2001 {
2002         *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
2003 }
2004
2005 /*
2006  * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
2007  * in RxD block
2008  * Sets the next block pointer in RxD block
2009  */
2010 static inline void
2011 __vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
2012 {
2013         *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
2014 }
2015
2016 /*
2017  * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
2018  *             first block
2019  * Returns the dma address of the first RxD block
2020  */
2021 static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
2022 {
2023         struct vxge_hw_mempool_dma *dma_object;
2024
2025         dma_object = ring->mempool->memblocks_dma_arr;
2026         vxge_assert(dma_object != NULL);
2027
2028         return dma_object->addr;
2029 }
2030
2031 /*
2032  * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
2033  * This function returns the dma address of a given item
2034  */
2035 static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
2036                                                void *item)
2037 {
2038         u32 memblock_idx;
2039         void *memblock;
2040         struct vxge_hw_mempool_dma *memblock_dma_object;
2041         ptrdiff_t dma_item_offset;
2042
2043         /* get owner memblock index */
2044         memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
2045
2046         /* get owner memblock by memblock index */
2047         memblock = mempoolh->memblocks_arr[memblock_idx];
2048
2049         /* get memblock DMA object by memblock index */
2050         memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
2051
2052         /* calculate offset in the memblock of this item */
2053         dma_item_offset = (u8 *)item - (u8 *)memblock;
2054
2055         return memblock_dma_object->addr + dma_item_offset;
2056 }
2057
2058 /*
2059  * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
2060  * This function returns the dma address of a given item
2061  */
2062 static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
2063                                          struct __vxge_hw_ring *ring, u32 from,
2064                                          u32 to)
2065 {
2066         u8 *to_item , *from_item;
2067         dma_addr_t to_dma;
2068
2069         /* get "from" RxD block */
2070         from_item = mempoolh->items_arr[from];
2071         vxge_assert(from_item);
2072
2073         /* get "to" RxD block */
2074         to_item = mempoolh->items_arr[to];
2075         vxge_assert(to_item);
2076
2077         /* return address of the beginning of previous RxD block */
2078         to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
2079
2080         /* set next pointer for this RxD block to point on
2081          * previous item's DMA start address */
2082         __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
2083 }
2084
2085 /*
2086  * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
2087  * block callback
2088  * This function is callback passed to __vxge_hw_mempool_create to create memory
2089  * pool for RxD block
2090  */
2091 static void
2092 __vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
2093                                   u32 memblock_index,
2094                                   struct vxge_hw_mempool_dma *dma_object,
2095                                   u32 index, u32 is_last)
2096 {
2097         u32 i;
2098         void *item = mempoolh->items_arr[index];
2099         struct __vxge_hw_ring *ring =
2100                 (struct __vxge_hw_ring *)mempoolh->userdata;
2101
2102         /* format rxds array */
2103         for (i = 0; i < ring->rxds_per_block; i++) {
2104                 void *rxdblock_priv;
2105                 void *uld_priv;
2106                 struct vxge_hw_ring_rxd_1 *rxdp;
2107
2108                 u32 reserve_index = ring->channel.reserve_ptr -
2109                                 (index * ring->rxds_per_block + i + 1);
2110                 u32 memblock_item_idx;
2111
2112                 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
2113                                                 i * ring->rxd_size;
2114
2115                 /* Note: memblock_item_idx is index of the item within
2116                  *       the memblock. For instance, in case of three RxD-blocks
2117                  *       per memblock this value can be 0, 1 or 2. */
2118                 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
2119                                         memblock_index, item,
2120                                         &memblock_item_idx);
2121
2122                 rxdp = ring->channel.reserve_arr[reserve_index];
2123
2124                 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
2125
2126                 /* pre-format Host_Control */
2127                 rxdp->host_control = (u64)(size_t)uld_priv;
2128         }
2129
2130         __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
2131
2132         if (is_last) {
2133                 /* link last one with first one */
2134                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
2135         }
2136
2137         if (index > 0) {
2138                 /* link this RxD block with previous one */
2139                 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
2140         }
2141 }
2142
2143 /*
2144  * __vxge_hw_ring_replenish - Initial replenish of RxDs
2145  * This function replenishes the RxDs from reserve array to work array
2146  */
2147 static enum vxge_hw_status
2148 vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
2149 {
2150         void *rxd;
2151         struct __vxge_hw_channel *channel;
2152         enum vxge_hw_status status = VXGE_HW_OK;
2153
2154         channel = &ring->channel;
2155
2156         while (vxge_hw_channel_dtr_count(channel) > 0) {
2157
2158                 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
2159
2160                 vxge_assert(status == VXGE_HW_OK);
2161
2162                 if (ring->rxd_init) {
2163                         status = ring->rxd_init(rxd, channel->userdata);
2164                         if (status != VXGE_HW_OK) {
2165                                 vxge_hw_ring_rxd_free(ring, rxd);
2166                                 goto exit;
2167                         }
2168                 }
2169
2170                 vxge_hw_ring_rxd_post(ring, rxd);
2171         }
2172         status = VXGE_HW_OK;
2173 exit:
2174         return status;
2175 }
2176
2177 /*
2178  * __vxge_hw_channel_allocate - Allocate memory for channel
2179  * This function allocates required memory for the channel and various arrays
2180  * in the channel
2181  */
2182 static struct __vxge_hw_channel *
2183 __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2184                            enum __vxge_hw_channel_type type,
2185                            u32 length, u32 per_dtr_space,
2186                            void *userdata)
2187 {
2188         struct __vxge_hw_channel *channel;
2189         struct __vxge_hw_device *hldev;
2190         int size = 0;
2191         u32 vp_id;
2192
2193         hldev = vph->vpath->hldev;
2194         vp_id = vph->vpath->vp_id;
2195
2196         switch (type) {
2197         case VXGE_HW_CHANNEL_TYPE_FIFO:
2198                 size = sizeof(struct __vxge_hw_fifo);
2199                 break;
2200         case VXGE_HW_CHANNEL_TYPE_RING:
2201                 size = sizeof(struct __vxge_hw_ring);
2202                 break;
2203         default:
2204                 break;
2205         }
2206
2207         channel = kzalloc(size, GFP_KERNEL);
2208         if (channel == NULL)
2209                 goto exit0;
2210         INIT_LIST_HEAD(&channel->item);
2211
2212         channel->common_reg = hldev->common_reg;
2213         channel->first_vp_id = hldev->first_vp_id;
2214         channel->type = type;
2215         channel->devh = hldev;
2216         channel->vph = vph;
2217         channel->userdata = userdata;
2218         channel->per_dtr_space = per_dtr_space;
2219         channel->length = length;
2220         channel->vp_id = vp_id;
2221
2222         channel->work_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2223         if (channel->work_arr == NULL)
2224                 goto exit1;
2225
2226         channel->free_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2227         if (channel->free_arr == NULL)
2228                 goto exit1;
2229         channel->free_ptr = length;
2230
2231         channel->reserve_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2232         if (channel->reserve_arr == NULL)
2233                 goto exit1;
2234         channel->reserve_ptr = length;
2235         channel->reserve_top = 0;
2236
2237         channel->orig_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
2238         if (channel->orig_arr == NULL)
2239                 goto exit1;
2240
2241         return channel;
2242 exit1:
2243         __vxge_hw_channel_free(channel);
2244
2245 exit0:
2246         return NULL;
2247 }
2248
2249 /*
2250  * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
2251  * Adds a block to block pool
2252  */
2253 static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
2254                                         void *block_addr,
2255                                         u32 length,
2256                                         struct pci_dev *dma_h,
2257                                         struct pci_dev *acc_handle)
2258 {
2259         struct __vxge_hw_blockpool *blockpool;
2260         struct __vxge_hw_blockpool_entry *entry = NULL;
2261         dma_addr_t dma_addr;
2262         enum vxge_hw_status status = VXGE_HW_OK;
2263         u32 req_out;
2264
2265         blockpool = &devh->block_pool;
2266
2267         if (block_addr == NULL) {
2268                 blockpool->req_out--;
2269                 status = VXGE_HW_FAIL;
2270                 goto exit;
2271         }
2272
2273         dma_addr = pci_map_single(devh->pdev, block_addr, length,
2274                                 PCI_DMA_BIDIRECTIONAL);
2275
2276         if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
2277                 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
2278                 blockpool->req_out--;
2279                 status = VXGE_HW_FAIL;
2280                 goto exit;
2281         }
2282
2283         if (!list_empty(&blockpool->free_entry_list))
2284                 entry = (struct __vxge_hw_blockpool_entry *)
2285                         list_first_entry(&blockpool->free_entry_list,
2286                                 struct __vxge_hw_blockpool_entry,
2287                                 item);
2288
2289         if (entry == NULL)
2290                 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
2291         else
2292                 list_del(&entry->item);
2293
2294         if (entry != NULL) {
2295                 entry->length = length;
2296                 entry->memblock = block_addr;
2297                 entry->dma_addr = dma_addr;
2298                 entry->acc_handle = acc_handle;
2299                 entry->dma_handle = dma_h;
2300                 list_add(&entry->item, &blockpool->free_block_list);
2301                 blockpool->pool_size++;
2302                 status = VXGE_HW_OK;
2303         } else
2304                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2305
2306         blockpool->req_out--;
2307
2308         req_out = blockpool->req_out;
2309 exit:
2310         return;
2311 }
2312
2313 static inline void
2314 vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
2315 {
2316         gfp_t flags;
2317         void *vaddr;
2318
2319         if (in_interrupt())
2320                 flags = GFP_ATOMIC | GFP_DMA;
2321         else
2322                 flags = GFP_KERNEL | GFP_DMA;
2323
2324         vaddr = kmalloc((size), flags);
2325
2326         vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
2327 }
2328
2329 /*
2330  * __vxge_hw_blockpool_blocks_add - Request additional blocks
2331  */
2332 static
2333 void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
2334 {
2335         u32 nreq = 0, i;
2336
2337         if ((blockpool->pool_size  +  blockpool->req_out) <
2338                 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
2339                 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
2340                 blockpool->req_out += nreq;
2341         }
2342
2343         for (i = 0; i < nreq; i++)
2344                 vxge_os_dma_malloc_async(
2345                         (blockpool->hldev)->pdev,
2346                         blockpool->hldev, VXGE_HW_BLOCK_SIZE);
2347 }
2348
2349 /*
2350  * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
2351  * Allocates a block of memory of given size, either from block pool
2352  * or by calling vxge_os_dma_malloc()
2353  */
2354 static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
2355                                         struct vxge_hw_mempool_dma *dma_object)
2356 {
2357         struct __vxge_hw_blockpool_entry *entry = NULL;
2358         struct __vxge_hw_blockpool  *blockpool;
2359         void *memblock = NULL;
2360         enum vxge_hw_status status = VXGE_HW_OK;
2361
2362         blockpool = &devh->block_pool;
2363
2364         if (size != blockpool->block_size) {
2365
2366                 memblock = vxge_os_dma_malloc(devh->pdev, size,
2367                                                 &dma_object->handle,
2368                                                 &dma_object->acc_handle);
2369
2370                 if (memblock == NULL) {
2371                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2372                         goto exit;
2373                 }
2374
2375                 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
2376                                         PCI_DMA_BIDIRECTIONAL);
2377
2378                 if (unlikely(pci_dma_mapping_error(devh->pdev,
2379                                 dma_object->addr))) {
2380                         vxge_os_dma_free(devh->pdev, memblock,
2381                                 &dma_object->acc_handle);
2382                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2383                         goto exit;
2384                 }
2385
2386         } else {
2387
2388                 if (!list_empty(&blockpool->free_block_list))
2389                         entry = (struct __vxge_hw_blockpool_entry *)
2390                                 list_first_entry(&blockpool->free_block_list,
2391                                         struct __vxge_hw_blockpool_entry,
2392                                         item);
2393
2394                 if (entry != NULL) {
2395                         list_del(&entry->item);
2396                         dma_object->addr = entry->dma_addr;
2397                         dma_object->handle = entry->dma_handle;
2398                         dma_object->acc_handle = entry->acc_handle;
2399                         memblock = entry->memblock;
2400
2401                         list_add(&entry->item,
2402                                 &blockpool->free_entry_list);
2403                         blockpool->pool_size--;
2404                 }
2405
2406                 if (memblock != NULL)
2407                         __vxge_hw_blockpool_blocks_add(blockpool);
2408         }
2409 exit:
2410         return memblock;
2411 }
2412
2413 /*
2414  * __vxge_hw_blockpool_blocks_remove - Free additional blocks
2415  */
2416 static void
2417 __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
2418 {
2419         struct list_head *p, *n;
2420
2421         list_for_each_safe(p, n, &blockpool->free_block_list) {
2422
2423                 if (blockpool->pool_size < blockpool->pool_max)
2424                         break;
2425
2426                 pci_unmap_single(
2427                         (blockpool->hldev)->pdev,
2428                         ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
2429                         ((struct __vxge_hw_blockpool_entry *)p)->length,
2430                         PCI_DMA_BIDIRECTIONAL);
2431
2432                 vxge_os_dma_free(
2433                         (blockpool->hldev)->pdev,
2434                         ((struct __vxge_hw_blockpool_entry *)p)->memblock,
2435                         &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
2436
2437                 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
2438
2439                 list_add(p, &blockpool->free_entry_list);
2440
2441                 blockpool->pool_size--;
2442
2443         }
2444 }
2445
2446 /*
2447  * __vxge_hw_blockpool_free - Frees the memory allcoated with
2448  *                              __vxge_hw_blockpool_malloc
2449  */
2450 static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
2451                                      void *memblock, u32 size,
2452                                      struct vxge_hw_mempool_dma *dma_object)
2453 {
2454         struct __vxge_hw_blockpool_entry *entry = NULL;
2455         struct __vxge_hw_blockpool  *blockpool;
2456         enum vxge_hw_status status = VXGE_HW_OK;
2457
2458         blockpool = &devh->block_pool;
2459
2460         if (size != blockpool->block_size) {
2461                 pci_unmap_single(devh->pdev, dma_object->addr, size,
2462                         PCI_DMA_BIDIRECTIONAL);
2463                 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
2464         } else {
2465
2466                 if (!list_empty(&blockpool->free_entry_list))
2467                         entry = (struct __vxge_hw_blockpool_entry *)
2468                                 list_first_entry(&blockpool->free_entry_list,
2469                                         struct __vxge_hw_blockpool_entry,
2470                                         item);
2471
2472                 if (entry == NULL)
2473                         entry = vmalloc(sizeof(
2474                                         struct __vxge_hw_blockpool_entry));
2475                 else
2476                         list_del(&entry->item);
2477
2478                 if (entry != NULL) {
2479                         entry->length = size;
2480                         entry->memblock = memblock;
2481                         entry->dma_addr = dma_object->addr;
2482                         entry->acc_handle = dma_object->acc_handle;
2483                         entry->dma_handle = dma_object->handle;
2484                         list_add(&entry->item,
2485                                         &blockpool->free_block_list);
2486                         blockpool->pool_size++;
2487                         status = VXGE_HW_OK;
2488                 } else
2489                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2490
2491                 if (status == VXGE_HW_OK)
2492                         __vxge_hw_blockpool_blocks_remove(blockpool);
2493         }
2494 }
2495
2496 /*
2497  * vxge_hw_mempool_destroy
2498  */
2499 static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
2500 {
2501         u32 i, j;
2502         struct __vxge_hw_device *devh = mempool->devh;
2503
2504         for (i = 0; i < mempool->memblocks_allocated; i++) {
2505                 struct vxge_hw_mempool_dma *dma_object;
2506
2507                 vxge_assert(mempool->memblocks_arr[i]);
2508                 vxge_assert(mempool->memblocks_dma_arr + i);
2509
2510                 dma_object = mempool->memblocks_dma_arr + i;
2511
2512                 for (j = 0; j < mempool->items_per_memblock; j++) {
2513                         u32 index = i * mempool->items_per_memblock + j;
2514
2515                         /* to skip last partially filled(if any) memblock */
2516                         if (index >= mempool->items_current)
2517                                 break;
2518                 }
2519
2520                 vfree(mempool->memblocks_priv_arr[i]);
2521
2522                 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2523                                 mempool->memblock_size, dma_object);
2524         }
2525
2526         vfree(mempool->items_arr);
2527         vfree(mempool->memblocks_dma_arr);
2528         vfree(mempool->memblocks_priv_arr);
2529         vfree(mempool->memblocks_arr);
2530         vfree(mempool);
2531 }
2532
2533 /*
2534  * __vxge_hw_mempool_grow
2535  * Will resize mempool up to %num_allocate value.
2536  */
2537 static enum vxge_hw_status
2538 __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2539                        u32 *num_allocated)
2540 {
2541         u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2542         u32 n_items = mempool->items_per_memblock;
2543         u32 start_block_idx = mempool->memblocks_allocated;
2544         u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2545         enum vxge_hw_status status = VXGE_HW_OK;
2546
2547         *num_allocated = 0;
2548
2549         if (end_block_idx > mempool->memblocks_max) {
2550                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2551                 goto exit;
2552         }
2553
2554         for (i = start_block_idx; i < end_block_idx; i++) {
2555                 u32 j;
2556                 u32 is_last = ((end_block_idx - 1) == i);
2557                 struct vxge_hw_mempool_dma *dma_object =
2558                         mempool->memblocks_dma_arr + i;
2559                 void *the_memblock;
2560
2561                 /* allocate memblock's private part. Each DMA memblock
2562                  * has a space allocated for item's private usage upon
2563                  * mempool's user request. Each time mempool grows, it will
2564                  * allocate new memblock and its private part at once.
2565                  * This helps to minimize memory usage a lot. */
2566                 mempool->memblocks_priv_arr[i] =
2567                         vzalloc(array_size(mempool->items_priv_size, n_items));
2568                 if (mempool->memblocks_priv_arr[i] == NULL) {
2569                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2570                         goto exit;
2571                 }
2572
2573                 /* allocate DMA-capable memblock */
2574                 mempool->memblocks_arr[i] =
2575                         __vxge_hw_blockpool_malloc(mempool->devh,
2576                                 mempool->memblock_size, dma_object);
2577                 if (mempool->memblocks_arr[i] == NULL) {
2578                         vfree(mempool->memblocks_priv_arr[i]);
2579                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
2580                         goto exit;
2581                 }
2582
2583                 (*num_allocated)++;
2584                 mempool->memblocks_allocated++;
2585
2586                 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2587
2588                 the_memblock = mempool->memblocks_arr[i];
2589
2590                 /* fill the items hash array */
2591                 for (j = 0; j < n_items; j++) {
2592                         u32 index = i * n_items + j;
2593
2594                         if (first_time && index >= mempool->items_initial)
2595                                 break;
2596
2597                         mempool->items_arr[index] =
2598                                 ((char *)the_memblock + j*mempool->item_size);
2599
2600                         /* let caller to do more job on each item */
2601                         if (mempool->item_func_alloc != NULL)
2602                                 mempool->item_func_alloc(mempool, i,
2603                                         dma_object, index, is_last);
2604
2605                         mempool->items_current = index + 1;
2606                 }
2607
2608                 if (first_time && mempool->items_current ==
2609                                         mempool->items_initial)
2610                         break;
2611         }
2612 exit:
2613         return status;
2614 }
2615
2616 /*
2617  * vxge_hw_mempool_create
2618  * This function will create memory pool object. Pool may grow but will
2619  * never shrink. Pool consists of number of dynamically allocated blocks
2620  * with size enough to hold %items_initial number of items. Memory is
2621  * DMA-able but client must map/unmap before interoperating with the device.
2622  */
2623 static struct vxge_hw_mempool *
2624 __vxge_hw_mempool_create(struct __vxge_hw_device *devh,
2625                          u32 memblock_size,
2626                          u32 item_size,
2627                          u32 items_priv_size,
2628                          u32 items_initial,
2629                          u32 items_max,
2630                          const struct vxge_hw_mempool_cbs *mp_callback,
2631                          void *userdata)
2632 {
2633         enum vxge_hw_status status = VXGE_HW_OK;
2634         u32 memblocks_to_allocate;
2635         struct vxge_hw_mempool *mempool = NULL;
2636         u32 allocated;
2637
2638         if (memblock_size < item_size) {
2639                 status = VXGE_HW_FAIL;
2640                 goto exit;
2641         }
2642
2643         mempool = vzalloc(sizeof(struct vxge_hw_mempool));
2644         if (mempool == NULL) {
2645                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2646                 goto exit;
2647         }
2648
2649         mempool->devh                   = devh;
2650         mempool->memblock_size          = memblock_size;
2651         mempool->items_max              = items_max;
2652         mempool->items_initial          = items_initial;
2653         mempool->item_size              = item_size;
2654         mempool->items_priv_size        = items_priv_size;
2655         mempool->item_func_alloc        = mp_callback->item_func_alloc;
2656         mempool->userdata               = userdata;
2657
2658         mempool->memblocks_allocated = 0;
2659
2660         mempool->items_per_memblock = memblock_size / item_size;
2661
2662         mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2663                                         mempool->items_per_memblock;
2664
2665         /* allocate array of memblocks */
2666         mempool->memblocks_arr =
2667                 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2668         if (mempool->memblocks_arr == NULL) {
2669                 __vxge_hw_mempool_destroy(mempool);
2670                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2671                 mempool = NULL;
2672                 goto exit;
2673         }
2674
2675         /* allocate array of private parts of items per memblocks */
2676         mempool->memblocks_priv_arr =
2677                 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
2678         if (mempool->memblocks_priv_arr == NULL) {
2679                 __vxge_hw_mempool_destroy(mempool);
2680                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2681                 mempool = NULL;
2682                 goto exit;
2683         }
2684
2685         /* allocate array of memblocks DMA objects */
2686         mempool->memblocks_dma_arr =
2687                 vzalloc(array_size(sizeof(struct vxge_hw_mempool_dma),
2688                                    mempool->memblocks_max));
2689         if (mempool->memblocks_dma_arr == NULL) {
2690                 __vxge_hw_mempool_destroy(mempool);
2691                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2692                 mempool = NULL;
2693                 goto exit;
2694         }
2695
2696         /* allocate hash array of items */
2697         mempool->items_arr = vzalloc(array_size(sizeof(void *),
2698                                                 mempool->items_max));
2699         if (mempool->items_arr == NULL) {
2700                 __vxge_hw_mempool_destroy(mempool);
2701                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2702                 mempool = NULL;
2703                 goto exit;
2704         }
2705
2706         /* calculate initial number of memblocks */
2707         memblocks_to_allocate = (mempool->items_initial +
2708                                  mempool->items_per_memblock - 1) /
2709                                                 mempool->items_per_memblock;
2710
2711         /* pre-allocate the mempool */
2712         status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2713                                         &allocated);
2714         if (status != VXGE_HW_OK) {
2715                 __vxge_hw_mempool_destroy(mempool);
2716                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2717                 mempool = NULL;
2718                 goto exit;
2719         }
2720
2721 exit:
2722         return mempool;
2723 }
2724
2725 /*
2726  * __vxge_hw_ring_abort - Returns the RxD
2727  * This function terminates the RxDs of ring
2728  */
2729 static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
2730 {
2731         void *rxdh;
2732         struct __vxge_hw_channel *channel;
2733
2734         channel = &ring->channel;
2735
2736         for (;;) {
2737                 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
2738
2739                 if (rxdh == NULL)
2740                         break;
2741
2742                 vxge_hw_channel_dtr_complete(channel);
2743
2744                 if (ring->rxd_term)
2745                         ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
2746                                 channel->userdata);
2747
2748                 vxge_hw_channel_dtr_free(channel, rxdh);
2749         }
2750
2751         return VXGE_HW_OK;
2752 }
2753
2754 /*
2755  * __vxge_hw_ring_reset - Resets the ring
2756  * This function resets the ring during vpath reset operation
2757  */
2758 static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
2759 {
2760         enum vxge_hw_status status = VXGE_HW_OK;
2761         struct __vxge_hw_channel *channel;
2762
2763         channel = &ring->channel;
2764
2765         __vxge_hw_ring_abort(ring);
2766
2767         status = __vxge_hw_channel_reset(channel);
2768
2769         if (status != VXGE_HW_OK)
2770                 goto exit;
2771
2772         if (ring->rxd_init) {
2773                 status = vxge_hw_ring_replenish(ring);
2774                 if (status != VXGE_HW_OK)
2775                         goto exit;
2776         }
2777 exit:
2778         return status;
2779 }
2780
2781 /*
2782  * __vxge_hw_ring_delete - Removes the ring
2783  * This function freeup the memory pool and removes the ring
2784  */
2785 static enum vxge_hw_status
2786 __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
2787 {
2788         struct __vxge_hw_ring *ring = vp->vpath->ringh;
2789
2790         __vxge_hw_ring_abort(ring);
2791
2792         if (ring->mempool)
2793                 __vxge_hw_mempool_destroy(ring->mempool);
2794
2795         vp->vpath->ringh = NULL;
2796         __vxge_hw_channel_free(&ring->channel);
2797
2798         return VXGE_HW_OK;
2799 }
2800
2801 /*
2802  * __vxge_hw_ring_create - Create a Ring
2803  * This function creates Ring and initializes it.
2804  */
2805 static enum vxge_hw_status
2806 __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
2807                       struct vxge_hw_ring_attr *attr)
2808 {
2809         enum vxge_hw_status status = VXGE_HW_OK;
2810         struct __vxge_hw_ring *ring;
2811         u32 ring_length;
2812         struct vxge_hw_ring_config *config;
2813         struct __vxge_hw_device *hldev;
2814         u32 vp_id;
2815         static const struct vxge_hw_mempool_cbs ring_mp_callback = {
2816                 .item_func_alloc = __vxge_hw_ring_mempool_item_alloc,
2817         };
2818
2819         if ((vp == NULL) || (attr == NULL)) {
2820                 status = VXGE_HW_FAIL;
2821                 goto exit;
2822         }
2823
2824         hldev = vp->vpath->hldev;
2825         vp_id = vp->vpath->vp_id;
2826
2827         config = &hldev->config.vp_config[vp_id].ring;
2828
2829         ring_length = config->ring_blocks *
2830                         vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2831
2832         ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
2833                                                 VXGE_HW_CHANNEL_TYPE_RING,
2834                                                 ring_length,
2835                                                 attr->per_rxd_space,
2836                                                 attr->userdata);
2837         if (ring == NULL) {
2838                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2839                 goto exit;
2840         }
2841
2842         vp->vpath->ringh = ring;
2843         ring->vp_id = vp_id;
2844         ring->vp_reg = vp->vpath->vp_reg;
2845         ring->common_reg = hldev->common_reg;
2846         ring->stats = &vp->vpath->sw_stats->ring_stats;
2847         ring->config = config;
2848         ring->callback = attr->callback;
2849         ring->rxd_init = attr->rxd_init;
2850         ring->rxd_term = attr->rxd_term;
2851         ring->buffer_mode = config->buffer_mode;
2852         ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
2853         ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
2854         ring->rxds_limit = config->rxds_limit;
2855
2856         ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
2857         ring->rxd_priv_size =
2858                 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
2859         ring->per_rxd_space = attr->per_rxd_space;
2860
2861         ring->rxd_priv_size =
2862                 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2863                 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2864
2865         /* how many RxDs can fit into one block. Depends on configured
2866          * buffer_mode. */
2867         ring->rxds_per_block =
2868                 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2869
2870         /* calculate actual RxD block private size */
2871         ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
2872         ring->mempool = __vxge_hw_mempool_create(hldev,
2873                                 VXGE_HW_BLOCK_SIZE,
2874                                 VXGE_HW_BLOCK_SIZE,
2875                                 ring->rxdblock_priv_size,
2876                                 ring->config->ring_blocks,
2877                                 ring->config->ring_blocks,
2878                                 &ring_mp_callback,
2879                                 ring);
2880         if (ring->mempool == NULL) {
2881                 __vxge_hw_ring_delete(vp);
2882                 return VXGE_HW_ERR_OUT_OF_MEMORY;
2883         }
2884
2885         status = __vxge_hw_channel_initialize(&ring->channel);
2886         if (status != VXGE_HW_OK) {
2887                 __vxge_hw_ring_delete(vp);
2888                 goto exit;
2889         }
2890
2891         /* Note:
2892          * Specifying rxd_init callback means two things:
2893          * 1) rxds need to be initialized by driver at channel-open time;
2894          * 2) rxds need to be posted at channel-open time
2895          *    (that's what the initial_replenish() below does)
2896          * Currently we don't have a case when the 1) is done without the 2).
2897          */
2898         if (ring->rxd_init) {
2899                 status = vxge_hw_ring_replenish(ring);
2900                 if (status != VXGE_HW_OK) {
2901                         __vxge_hw_ring_delete(vp);
2902                         goto exit;
2903                 }
2904         }
2905
2906         /* initial replenish will increment the counter in its post() routine,
2907          * we have to reset it */
2908         ring->stats->common_stats.usage_cnt = 0;
2909 exit:
2910         return status;
2911 }
2912
2913 /*
2914  * vxge_hw_device_config_default_get - Initialize device config with defaults.
2915  * Initialize Titan device config with default values.
2916  */
2917 enum vxge_hw_status
2918 vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2919 {
2920         u32 i;
2921
2922         device_config->dma_blockpool_initial =
2923                                         VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2924         device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2925         device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2926         device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2927         device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2928         device_config->device_poll_millis =  VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2929         device_config->rts_mac_en =  VXGE_HW_RTS_MAC_DEFAULT;
2930
2931         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2932                 device_config->vp_config[i].vp_id = i;
2933
2934                 device_config->vp_config[i].min_bandwidth =
2935                                 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2936
2937                 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2938
2939                 device_config->vp_config[i].ring.ring_blocks =
2940                                 VXGE_HW_DEF_RING_BLOCKS;
2941
2942                 device_config->vp_config[i].ring.buffer_mode =
2943                                 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2944
2945                 device_config->vp_config[i].ring.scatter_mode =
2946                                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2947
2948                 device_config->vp_config[i].ring.rxds_limit =
2949                                 VXGE_HW_DEF_RING_RXDS_LIMIT;
2950
2951                 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2952
2953                 device_config->vp_config[i].fifo.fifo_blocks =
2954                                 VXGE_HW_MIN_FIFO_BLOCKS;
2955
2956                 device_config->vp_config[i].fifo.max_frags =
2957                                 VXGE_HW_MAX_FIFO_FRAGS;
2958
2959                 device_config->vp_config[i].fifo.memblock_size =
2960                                 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2961
2962                 device_config->vp_config[i].fifo.alignment_size =
2963                                 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2964
2965                 device_config->vp_config[i].fifo.intr =
2966                                 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2967
2968                 device_config->vp_config[i].fifo.no_snoop_bits =
2969                                 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2970                 device_config->vp_config[i].tti.intr_enable =
2971                                 VXGE_HW_TIM_INTR_DEFAULT;
2972
2973                 device_config->vp_config[i].tti.btimer_val =
2974                                 VXGE_HW_USE_FLASH_DEFAULT;
2975
2976                 device_config->vp_config[i].tti.timer_ac_en =
2977                                 VXGE_HW_USE_FLASH_DEFAULT;
2978
2979                 device_config->vp_config[i].tti.timer_ci_en =
2980                                 VXGE_HW_USE_FLASH_DEFAULT;
2981
2982                 device_config->vp_config[i].tti.timer_ri_en =
2983                                 VXGE_HW_USE_FLASH_DEFAULT;
2984
2985                 device_config->vp_config[i].tti.rtimer_val =
2986                                 VXGE_HW_USE_FLASH_DEFAULT;
2987
2988                 device_config->vp_config[i].tti.util_sel =
2989                                 VXGE_HW_USE_FLASH_DEFAULT;
2990
2991                 device_config->vp_config[i].tti.ltimer_val =
2992                                 VXGE_HW_USE_FLASH_DEFAULT;
2993
2994                 device_config->vp_config[i].tti.urange_a =
2995                                 VXGE_HW_USE_FLASH_DEFAULT;
2996
2997                 device_config->vp_config[i].tti.uec_a =
2998                                 VXGE_HW_USE_FLASH_DEFAULT;
2999
3000                 device_config->vp_config[i].tti.urange_b =
3001                                 VXGE_HW_USE_FLASH_DEFAULT;
3002
3003                 device_config->vp_config[i].tti.uec_b =
3004                                 VXGE_HW_USE_FLASH_DEFAULT;
3005
3006                 device_config->vp_config[i].tti.urange_c =
3007                                 VXGE_HW_USE_FLASH_DEFAULT;
3008
3009                 device_config->vp_config[i].tti.uec_c =
3010                                 VXGE_HW_USE_FLASH_DEFAULT;
3011
3012                 device_config->vp_config[i].tti.uec_d =
3013                                 VXGE_HW_USE_FLASH_DEFAULT;
3014
3015                 device_config->vp_config[i].rti.intr_enable =
3016                                 VXGE_HW_TIM_INTR_DEFAULT;
3017
3018                 device_config->vp_config[i].rti.btimer_val =
3019                                 VXGE_HW_USE_FLASH_DEFAULT;
3020
3021                 device_config->vp_config[i].rti.timer_ac_en =
3022                                 VXGE_HW_USE_FLASH_DEFAULT;
3023
3024                 device_config->vp_config[i].rti.timer_ci_en =
3025                                 VXGE_HW_USE_FLASH_DEFAULT;
3026
3027                 device_config->vp_config[i].rti.timer_ri_en =
3028                                 VXGE_HW_USE_FLASH_DEFAULT;
3029
3030                 device_config->vp_config[i].rti.rtimer_val =
3031                                 VXGE_HW_USE_FLASH_DEFAULT;
3032
3033                 device_config->vp_config[i].rti.util_sel =
3034                                 VXGE_HW_USE_FLASH_DEFAULT;
3035
3036                 device_config->vp_config[i].rti.ltimer_val =
3037                                 VXGE_HW_USE_FLASH_DEFAULT;
3038
3039                 device_config->vp_config[i].rti.urange_a =
3040                                 VXGE_HW_USE_FLASH_DEFAULT;
3041
3042                 device_config->vp_config[i].rti.uec_a =
3043                                 VXGE_HW_USE_FLASH_DEFAULT;
3044
3045                 device_config->vp_config[i].rti.urange_b =
3046                                 VXGE_HW_USE_FLASH_DEFAULT;
3047
3048                 device_config->vp_config[i].rti.uec_b =
3049                                 VXGE_HW_USE_FLASH_DEFAULT;
3050
3051                 device_config->vp_config[i].rti.urange_c =
3052                                 VXGE_HW_USE_FLASH_DEFAULT;
3053
3054                 device_config->vp_config[i].rti.uec_c =
3055                                 VXGE_HW_USE_FLASH_DEFAULT;
3056
3057                 device_config->vp_config[i].rti.uec_d =
3058                                 VXGE_HW_USE_FLASH_DEFAULT;
3059
3060                 device_config->vp_config[i].mtu =
3061                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
3062
3063                 device_config->vp_config[i].rpa_strip_vlan_tag =
3064                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
3065         }
3066
3067         return VXGE_HW_OK;
3068 }
3069
3070 /*
3071  * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
3072  * Set the swapper bits appropriately for the vpath.
3073  */
3074 static enum vxge_hw_status
3075 __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
3076 {
3077 #ifndef __BIG_ENDIAN
3078         u64 val64;
3079
3080         val64 = readq(&vpath_reg->vpath_general_cfg1);
3081         wmb();
3082         val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
3083         writeq(val64, &vpath_reg->vpath_general_cfg1);
3084         wmb();
3085 #endif
3086         return VXGE_HW_OK;
3087 }
3088
3089 /*
3090  * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
3091  * Set the swapper bits appropriately for the vpath.
3092  */
3093 static enum vxge_hw_status
3094 __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
3095                            struct vxge_hw_vpath_reg __iomem *vpath_reg)
3096 {
3097         u64 val64;
3098
3099         val64 = readq(&legacy_reg->pifm_wr_swap_en);
3100
3101         if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
3102                 val64 = readq(&vpath_reg->kdfcctl_cfg0);
3103                 wmb();
3104
3105                 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
3106                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1  |
3107                         VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
3108
3109                 writeq(val64, &vpath_reg->kdfcctl_cfg0);
3110                 wmb();
3111         }
3112
3113         return VXGE_HW_OK;
3114 }
3115
3116 /*
3117  * vxge_hw_mgmt_reg_read - Read Titan register.
3118  */
3119 enum vxge_hw_status
3120 vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
3121                       enum vxge_hw_mgmt_reg_type type,
3122                       u32 index, u32 offset, u64 *value)
3123 {
3124         enum vxge_hw_status status = VXGE_HW_OK;
3125
3126         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3127                 status = VXGE_HW_ERR_INVALID_DEVICE;
3128                 goto exit;
3129         }
3130
3131         switch (type) {
3132         case vxge_hw_mgmt_reg_type_legacy:
3133                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3134                         status = VXGE_HW_ERR_INVALID_OFFSET;
3135                         break;
3136                 }
3137                 *value = readq((void __iomem *)hldev->legacy_reg + offset);
3138                 break;
3139         case vxge_hw_mgmt_reg_type_toc:
3140                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3141                         status = VXGE_HW_ERR_INVALID_OFFSET;
3142                         break;
3143                 }
3144                 *value = readq((void __iomem *)hldev->toc_reg + offset);
3145                 break;
3146         case vxge_hw_mgmt_reg_type_common:
3147                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3148                         status = VXGE_HW_ERR_INVALID_OFFSET;
3149                         break;
3150                 }
3151                 *value = readq((void __iomem *)hldev->common_reg + offset);
3152                 break;
3153         case vxge_hw_mgmt_reg_type_mrpcim:
3154                 if (!(hldev->access_rights &
3155                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3156                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3157                         break;
3158                 }
3159                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3160                         status = VXGE_HW_ERR_INVALID_OFFSET;
3161                         break;
3162                 }
3163                 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
3164                 break;
3165         case vxge_hw_mgmt_reg_type_srpcim:
3166                 if (!(hldev->access_rights &
3167                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3168                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3169                         break;
3170                 }
3171                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3172                         status = VXGE_HW_ERR_INVALID_INDEX;
3173                         break;
3174                 }
3175                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3176                         status = VXGE_HW_ERR_INVALID_OFFSET;
3177                         break;
3178                 }
3179                 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
3180                                 offset);
3181                 break;
3182         case vxge_hw_mgmt_reg_type_vpmgmt:
3183                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3184                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3185                         status = VXGE_HW_ERR_INVALID_INDEX;
3186                         break;
3187                 }
3188                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3189                         status = VXGE_HW_ERR_INVALID_OFFSET;
3190                         break;
3191                 }
3192                 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
3193                                 offset);
3194                 break;
3195         case vxge_hw_mgmt_reg_type_vpath:
3196                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
3197                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3198                         status = VXGE_HW_ERR_INVALID_INDEX;
3199                         break;
3200                 }
3201                 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
3202                         status = VXGE_HW_ERR_INVALID_INDEX;
3203                         break;
3204                 }
3205                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3206                         status = VXGE_HW_ERR_INVALID_OFFSET;
3207                         break;
3208                 }
3209                 *value = readq((void __iomem *)hldev->vpath_reg[index] +
3210                                 offset);
3211                 break;
3212         default:
3213                 status = VXGE_HW_ERR_INVALID_TYPE;
3214                 break;
3215         }
3216
3217 exit:
3218         return status;
3219 }
3220
3221 /*
3222  * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
3223  */
3224 enum vxge_hw_status
3225 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
3226 {
3227         struct vxge_hw_vpmgmt_reg       __iomem *vpmgmt_reg;
3228         int i = 0, j = 0;
3229
3230         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3231                 if (!((vpath_mask) & vxge_mBIT(i)))
3232                         continue;
3233                 vpmgmt_reg = hldev->vpmgmt_reg[i];
3234                 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
3235                         if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
3236                         & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
3237                                 return VXGE_HW_FAIL;
3238                 }
3239         }
3240         return VXGE_HW_OK;
3241 }
3242 /*
3243  * vxge_hw_mgmt_reg_Write - Write Titan register.
3244  */
3245 enum vxge_hw_status
3246 vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
3247                       enum vxge_hw_mgmt_reg_type type,
3248                       u32 index, u32 offset, u64 value)
3249 {
3250         enum vxge_hw_status status = VXGE_HW_OK;
3251
3252         if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3253                 status = VXGE_HW_ERR_INVALID_DEVICE;
3254                 goto exit;
3255         }
3256
3257         switch (type) {
3258         case vxge_hw_mgmt_reg_type_legacy:
3259                 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3260                         status = VXGE_HW_ERR_INVALID_OFFSET;
3261                         break;
3262                 }
3263                 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
3264                 break;
3265         case vxge_hw_mgmt_reg_type_toc:
3266                 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3267                         status = VXGE_HW_ERR_INVALID_OFFSET;
3268                         break;
3269                 }
3270                 writeq(value, (void __iomem *)hldev->toc_reg + offset);
3271                 break;
3272         case vxge_hw_mgmt_reg_type_common:
3273                 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3274                         status = VXGE_HW_ERR_INVALID_OFFSET;
3275                         break;
3276                 }
3277                 writeq(value, (void __iomem *)hldev->common_reg + offset);
3278                 break;
3279         case vxge_hw_mgmt_reg_type_mrpcim:
3280                 if (!(hldev->access_rights &
3281                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
3282                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3283                         break;
3284                 }
3285                 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3286                         status = VXGE_HW_ERR_INVALID_OFFSET;
3287                         break;
3288                 }
3289                 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
3290                 break;
3291         case vxge_hw_mgmt_reg_type_srpcim:
3292                 if (!(hldev->access_rights &
3293                         VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
3294                         status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
3295                         break;
3296                 }
3297                 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3298                         status = VXGE_HW_ERR_INVALID_INDEX;
3299                         break;
3300                 }
3301                 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3302                         status = VXGE_HW_ERR_INVALID_OFFSET;
3303                         break;
3304                 }
3305                 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
3306                         offset);
3307
3308                 break;
3309         case vxge_hw_mgmt_reg_type_vpmgmt:
3310                 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3311                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3312                         status = VXGE_HW_ERR_INVALID_INDEX;
3313                         break;
3314                 }
3315                 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3316                         status = VXGE_HW_ERR_INVALID_OFFSET;
3317                         break;
3318                 }
3319                 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
3320                         offset);
3321                 break;
3322         case vxge_hw_mgmt_reg_type_vpath:
3323                 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
3324                         (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3325                         status = VXGE_HW_ERR_INVALID_INDEX;
3326                         break;
3327                 }
3328                 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3329                         status = VXGE_HW_ERR_INVALID_OFFSET;
3330                         break;
3331                 }
3332                 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
3333                         offset);
3334                 break;
3335         default:
3336                 status = VXGE_HW_ERR_INVALID_TYPE;
3337                 break;
3338         }
3339 exit:
3340         return status;
3341 }
3342
3343 /*
3344  * __vxge_hw_fifo_abort - Returns the TxD
3345  * This function terminates the TxDs of fifo
3346  */
3347 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3348 {
3349         void *txdlh;
3350
3351         for (;;) {
3352                 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3353
3354                 if (txdlh == NULL)
3355                         break;
3356
3357                 vxge_hw_channel_dtr_complete(&fifo->channel);
3358
3359                 if (fifo->txdl_term) {
3360                         fifo->txdl_term(txdlh,
3361                         VXGE_HW_TXDL_STATE_POSTED,
3362                         fifo->channel.userdata);
3363                 }
3364
3365                 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3366         }
3367
3368         return VXGE_HW_OK;
3369 }
3370
3371 /*
3372  * __vxge_hw_fifo_reset - Resets the fifo
3373  * This function resets the fifo during vpath reset operation
3374  */
3375 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3376 {
3377         enum vxge_hw_status status = VXGE_HW_OK;
3378
3379         __vxge_hw_fifo_abort(fifo);
3380         status = __vxge_hw_channel_reset(&fifo->channel);
3381
3382         return status;
3383 }
3384
3385 /*
3386  * __vxge_hw_fifo_delete - Removes the FIFO
3387  * This function freeup the memory pool and removes the FIFO
3388  */
3389 static enum vxge_hw_status
3390 __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
3391 {
3392         struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3393
3394         __vxge_hw_fifo_abort(fifo);
3395
3396         if (fifo->mempool)
3397                 __vxge_hw_mempool_destroy(fifo->mempool);
3398
3399         vp->vpath->fifoh = NULL;
3400
3401         __vxge_hw_channel_free(&fifo->channel);
3402
3403         return VXGE_HW_OK;
3404 }
3405
3406 /*
3407  * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
3408  * list callback
3409  * This function is callback passed to __vxge_hw_mempool_create to create memory
3410  * pool for TxD list
3411  */
3412 static void
3413 __vxge_hw_fifo_mempool_item_alloc(
3414         struct vxge_hw_mempool *mempoolh,
3415         u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
3416         u32 index, u32 is_last)
3417 {
3418         u32 memblock_item_idx;
3419         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
3420         struct vxge_hw_fifo_txd *txdp =
3421                 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
3422         struct __vxge_hw_fifo *fifo =
3423                         (struct __vxge_hw_fifo *)mempoolh->userdata;
3424         void *memblock = mempoolh->memblocks_arr[memblock_index];
3425
3426         vxge_assert(txdp);
3427
3428         txdp->host_control = (u64) (size_t)
3429         __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
3430                                         &memblock_item_idx);
3431
3432         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3433
3434         vxge_assert(txdl_priv);
3435
3436         fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3437
3438         /* pre-format HW's TxDL's private */
3439         txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
3440         txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
3441         txdl_priv->dma_handle = dma_object->handle;
3442         txdl_priv->memblock   = memblock;
3443         txdl_priv->first_txdp = txdp;
3444         txdl_priv->next_txdl_priv = NULL;
3445         txdl_priv->alloc_frags = 0;
3446 }
3447
3448 /*
3449  * __vxge_hw_fifo_create - Create a FIFO
3450  * This function creates FIFO and initializes it.
3451  */
3452 static enum vxge_hw_status
3453 __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
3454                       struct vxge_hw_fifo_attr *attr)
3455 {
3456         enum vxge_hw_status status = VXGE_HW_OK;
3457         struct __vxge_hw_fifo *fifo;
3458         struct vxge_hw_fifo_config *config;
3459         u32 txdl_size, txdl_per_memblock;
3460         struct vxge_hw_mempool_cbs fifo_mp_callback;
3461         struct __vxge_hw_virtualpath *vpath;
3462
3463         if ((vp == NULL) || (attr == NULL)) {
3464                 status = VXGE_HW_ERR_INVALID_HANDLE;
3465                 goto exit;
3466         }
3467         vpath = vp->vpath;
3468         config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3469
3470         txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
3471
3472         txdl_per_memblock = config->memblock_size / txdl_size;
3473
3474         fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3475                                         VXGE_HW_CHANNEL_TYPE_FIFO,
3476                                         config->fifo_blocks * txdl_per_memblock,
3477                                         attr->per_txdl_space, attr->userdata);
3478
3479         if (fifo == NULL) {
3480                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3481                 goto exit;
3482         }
3483
3484         vpath->fifoh = fifo;
3485         fifo->nofl_db = vpath->nofl_db;
3486
3487         fifo->vp_id = vpath->vp_id;
3488         fifo->vp_reg = vpath->vp_reg;
3489         fifo->stats = &vpath->sw_stats->fifo_stats;
3490
3491         fifo->config = config;
3492
3493         /* apply "interrupts per txdl" attribute */
3494         fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3495         fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3496         fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3497
3498         if (fifo->config->intr)
3499                 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3500
3501         fifo->no_snoop_bits = config->no_snoop_bits;
3502
3503         /*
3504          * FIFO memory management strategy:
3505          *
3506          * TxDL split into three independent parts:
3507          *      - set of TxD's
3508          *      - TxD HW private part
3509          *      - driver private part
3510          *
3511          * Adaptative memory allocation used. i.e. Memory allocated on
3512          * demand with the size which will fit into one memory block.
3513          * One memory block may contain more than one TxDL.
3514          *
3515          * During "reserve" operations more memory can be allocated on demand
3516          * for example due to FIFO full condition.
3517          *
3518          * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
3519          * routine which will essentially stop the channel and free resources.
3520          */
3521
3522         /* TxDL common private size == TxDL private  +  driver private */
3523         fifo->priv_size =
3524                 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
3525         fifo->priv_size = ((fifo->priv_size  +  VXGE_CACHE_LINE_SIZE - 1) /
3526                         VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
3527
3528         fifo->per_txdl_space = attr->per_txdl_space;
3529
3530         /* recompute txdl size to be cacheline aligned */
3531         fifo->txdl_size = txdl_size;
3532         fifo->txdl_per_memblock = txdl_per_memblock;
3533
3534         fifo->txdl_term = attr->txdl_term;
3535         fifo->callback = attr->callback;
3536
3537         if (fifo->txdl_per_memblock == 0) {
3538                 __vxge_hw_fifo_delete(vp);
3539                 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
3540                 goto exit;
3541         }
3542
3543         fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
3544
3545         fifo->mempool =
3546                 __vxge_hw_mempool_create(vpath->hldev,
3547                         fifo->config->memblock_size,
3548                         fifo->txdl_size,
3549                         fifo->priv_size,
3550                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3551                         (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3552                         &fifo_mp_callback,
3553                         fifo);
3554
3555         if (fifo->mempool == NULL) {
3556                 __vxge_hw_fifo_delete(vp);
3557                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3558                 goto exit;
3559         }
3560
3561         status = __vxge_hw_channel_initialize(&fifo->channel);
3562         if (status != VXGE_HW_OK) {
3563                 __vxge_hw_fifo_delete(vp);
3564                 goto exit;
3565         }
3566
3567         vxge_assert(fifo->channel.reserve_ptr);
3568 exit:
3569         return status;
3570 }
3571
3572 /*
3573  * __vxge_hw_vpath_pci_read - Read the content of given address
3574  *                          in pci config space.
3575  * Read from the vpath pci config space.
3576  */
3577 static enum vxge_hw_status
3578 __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3579                          u32 phy_func_0, u32 offset, u32 *val)
3580 {
3581         u64 val64;
3582         enum vxge_hw_status status = VXGE_HW_OK;
3583         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3584
3585         val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3586
3587         if (phy_func_0)
3588                 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3589
3590         writeq(val64, &vp_reg->pci_config_access_cfg1);
3591         wmb();
3592         writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3593                         &vp_reg->pci_config_access_cfg2);
3594         wmb();
3595
3596         status = __vxge_hw_device_register_poll(
3597                         &vp_reg->pci_config_access_cfg2,
3598                         VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3599
3600         if (status != VXGE_HW_OK)
3601                 goto exit;
3602
3603         val64 = readq(&vp_reg->pci_config_access_status);
3604
3605         if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3606                 status = VXGE_HW_FAIL;
3607                 *val = 0;
3608         } else
3609                 *val = (u32)vxge_bVALn(val64, 32, 32);
3610 exit:
3611         return status;
3612 }
3613
3614 /**
3615  * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3616  * @hldev: HW device.
3617  * @on_off: TRUE if flickering to be on, FALSE to be off
3618  *
3619  * Flicker the link LED.
3620  */
3621 enum vxge_hw_status
3622 vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
3623 {
3624         struct __vxge_hw_virtualpath *vpath;
3625         u64 data0, data1 = 0, steer_ctrl = 0;
3626         enum vxge_hw_status status;
3627
3628         if (hldev == NULL) {
3629                 status = VXGE_HW_ERR_INVALID_DEVICE;
3630                 goto exit;
3631         }
3632
3633         vpath = &hldev->virtual_paths[hldev->first_vp_id];
3634
3635         data0 = on_off;
3636         status = vxge_hw_vpath_fw_api(vpath,
3637                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3638                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3639                         0, &data0, &data1, &steer_ctrl);
3640 exit:
3641         return status;
3642 }
3643
3644 /*
3645  * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3646  */
3647 enum vxge_hw_status
3648 __vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3649                               u32 action, u32 rts_table, u32 offset,
3650                               u64 *data0, u64 *data1)
3651 {
3652         enum vxge_hw_status status;
3653         u64 steer_ctrl = 0;
3654
3655         if (vp == NULL) {
3656                 status = VXGE_HW_ERR_INVALID_HANDLE;
3657                 goto exit;
3658         }
3659
3660         if ((rts_table ==
3661              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
3662             (rts_table ==
3663              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
3664             (rts_table ==
3665              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
3666             (rts_table ==
3667              VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3668                 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
3669         }
3670
3671         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3672                                       data0, data1, &steer_ctrl);
3673         if (status != VXGE_HW_OK)
3674                 goto exit;
3675
3676         if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) &&
3677             (rts_table !=
3678              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3679                 *data1 = 0;
3680 exit:
3681         return status;
3682 }
3683
3684 /*
3685  * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3686  */
3687 enum vxge_hw_status
3688 __vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3689                               u32 rts_table, u32 offset, u64 steer_data0,
3690                               u64 steer_data1)
3691 {
3692         u64 data0, data1 = 0, steer_ctrl = 0;
3693         enum vxge_hw_status status;
3694
3695         if (vp == NULL) {
3696                 status = VXGE_HW_ERR_INVALID_HANDLE;
3697                 goto exit;
3698         }
3699
3700         data0 = steer_data0;
3701
3702         if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3703             (rts_table ==
3704              VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3705                 data1 = steer_data1;
3706
3707         status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3708                                       &data0, &data1, &steer_ctrl);
3709 exit:
3710         return status;
3711 }
3712
3713 /*
3714  * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3715  */
3716 enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3717                         struct __vxge_hw_vpath_handle *vp,
3718                         enum vxge_hw_rth_algoritms algorithm,
3719                         struct vxge_hw_rth_hash_types *hash_type,
3720                         u16 bucket_size)
3721 {
3722         u64 data0, data1;
3723         enum vxge_hw_status status = VXGE_HW_OK;
3724
3725         if (vp == NULL) {
3726                 status = VXGE_HW_ERR_INVALID_HANDLE;
3727                 goto exit;
3728         }
3729
3730         status = __vxge_hw_vpath_rts_table_get(vp,
3731                      VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3732                      VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3733                         0, &data0, &data1);
3734         if (status != VXGE_HW_OK)
3735                 goto exit;
3736
3737         data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3738                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3739
3740         data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3741         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3742         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3743
3744         if (hash_type->hash_type_tcpipv4_en)
3745                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3746
3747         if (hash_type->hash_type_ipv4_en)
3748                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3749
3750         if (hash_type->hash_type_tcpipv6_en)
3751                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3752
3753         if (hash_type->hash_type_ipv6_en)
3754                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3755
3756         if (hash_type->hash_type_tcpipv6ex_en)
3757                 data0 |=
3758                 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3759
3760         if (hash_type->hash_type_ipv6ex_en)
3761                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3762
3763         if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3764                 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3765         else
3766                 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3767
3768         status = __vxge_hw_vpath_rts_table_set(vp,
3769                 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3770                 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3771                 0, data0, 0);
3772 exit:
3773         return status;
3774 }
3775
3776 static void
3777 vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3778                                 u16 flag, u8 *itable)
3779 {
3780         switch (flag) {
3781         case 1:
3782                 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3783                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3784                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3785                         itable[j]);
3786         case 2:
3787                 *data0 |=
3788                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3789                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3790                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3791                         itable[j]);
3792         case 3:
3793                 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3794                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3795                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3796                         itable[j]);
3797         case 4:
3798                 *data1 |=
3799                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3800                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3801                         VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3802                         itable[j]);
3803         default:
3804                 return;
3805         }
3806 }
3807 /*
3808  * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3809  */
3810 enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3811                         struct __vxge_hw_vpath_handle **vpath_handles,
3812                         u32 vpath_count,
3813                         u8 *mtable,
3814                         u8 *itable,
3815                         u32 itable_size)
3816 {
3817         u32 i, j, action, rts_table;
3818         u64 data0;
3819         u64 data1;
3820         u32 max_entries;
3821         enum vxge_hw_status status = VXGE_HW_OK;
3822         struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3823
3824         if (vp == NULL) {
3825                 status = VXGE_HW_ERR_INVALID_HANDLE;
3826                 goto exit;
3827         }
3828
3829         max_entries = (((u32)1) << itable_size);
3830
3831         if (vp->vpath->hldev->config.rth_it_type
3832                                 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3833                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3834                 rts_table =
3835                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3836
3837                 for (j = 0; j < max_entries; j++) {
3838
3839                         data1 = 0;
3840
3841                         data0 =
3842                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3843                                 itable[j]);
3844
3845                         status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3846                                 action, rts_table, j, data0, data1);
3847
3848                         if (status != VXGE_HW_OK)
3849                                 goto exit;
3850                 }
3851
3852                 for (j = 0; j < max_entries; j++) {
3853
3854                         data1 = 0;
3855
3856                         data0 =
3857                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3858                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3859                                 itable[j]);
3860
3861                         status = __vxge_hw_vpath_rts_table_set(
3862                                 vpath_handles[mtable[itable[j]]], action,
3863                                 rts_table, j, data0, data1);
3864
3865                         if (status != VXGE_HW_OK)
3866                                 goto exit;
3867                 }
3868         } else {
3869                 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3870                 rts_table =
3871                         VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3872                 for (i = 0; i < vpath_count; i++) {
3873
3874                         for (j = 0; j < max_entries;) {
3875
3876                                 data0 = 0;
3877                                 data1 = 0;
3878
3879                                 while (j < max_entries) {
3880                                         if (mtable[itable[j]] != i) {
3881                                                 j++;
3882                                                 continue;
3883                                         }
3884                                         vxge_hw_rts_rth_data0_data1_get(j,
3885                                                 &data0, &data1, 1, itable);
3886                                         j++;
3887                                         break;
3888                                 }
3889
3890                                 while (j < max_entries) {
3891                                         if (mtable[itable[j]] != i) {
3892                                                 j++;
3893                                                 continue;
3894                                         }
3895                                         vxge_hw_rts_rth_data0_data1_get(j,
3896                                                 &data0, &data1, 2, itable);
3897                                         j++;
3898                                         break;
3899                                 }
3900
3901                                 while (j < max_entries) {
3902                                         if (mtable[itable[j]] != i) {
3903                                                 j++;
3904                                                 continue;
3905                                         }
3906                                         vxge_hw_rts_rth_data0_data1_get(j,
3907                                                 &data0, &data1, 3, itable);
3908                                         j++;
3909                                         break;
3910                                 }
3911
3912                                 while (j < max_entries) {
3913                                         if (mtable[itable[j]] != i) {
3914                                                 j++;
3915                                                 continue;
3916                                         }
3917                                         vxge_hw_rts_rth_data0_data1_get(j,
3918                                                 &data0, &data1, 4, itable);
3919                                         j++;
3920                                         break;
3921                                 }
3922
3923                                 if (data0 != 0) {
3924                                         status = __vxge_hw_vpath_rts_table_set(
3925                                                         vpath_handles[i],
3926                                                         action, rts_table,
3927                                                         0, data0, data1);
3928
3929                                         if (status != VXGE_HW_OK)
3930                                                 goto exit;
3931                                 }
3932                         }
3933                 }
3934         }
3935 exit:
3936         return status;
3937 }
3938
3939 /**
3940  * vxge_hw_vpath_check_leak - Check for memory leak
3941  * @ringh: Handle to the ring object used for receive
3942  *
3943  * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3944  * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3945  * Returns: VXGE_HW_FAIL, if leak has occurred.
3946  *
3947  */
3948 enum vxge_hw_status
3949 vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3950 {
3951         enum vxge_hw_status status = VXGE_HW_OK;
3952         u64 rxd_new_count, rxd_spat;
3953
3954         if (ring == NULL)
3955                 return status;
3956
3957         rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3958         rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3959         rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3960
3961         if (rxd_new_count >= rxd_spat)
3962                 status = VXGE_HW_FAIL;
3963
3964         return status;
3965 }
3966
3967 /*
3968  * __vxge_hw_vpath_mgmt_read
3969  * This routine reads the vpath_mgmt registers
3970  */
3971 static enum vxge_hw_status
3972 __vxge_hw_vpath_mgmt_read(
3973         struct __vxge_hw_device *hldev,
3974         struct __vxge_hw_virtualpath *vpath)
3975 {
3976         u32 i, mtu = 0, max_pyld = 0;
3977         u64 val64;
3978
3979         for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3980
3981                 val64 = readq(&vpath->vpmgmt_reg->
3982                                 rxmac_cfg0_port_vpmgmt_clone[i]);
3983                 max_pyld =
3984                         (u32)
3985                         VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3986                         (val64);
3987                 if (mtu < max_pyld)
3988                         mtu = max_pyld;
3989         }
3990
3991         vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3992
3993         val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3994
3995         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3996                 if (val64 & vxge_mBIT(i))
3997                         vpath->vsport_number = i;
3998         }
3999
4000         val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
4001
4002         if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
4003                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
4004         else
4005                 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
4006
4007         return VXGE_HW_OK;
4008 }
4009
4010 /*
4011  * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
4012  * This routine checks the vpath_rst_in_prog register to see if
4013  * adapter completed the reset process for the vpath
4014  */
4015 static enum vxge_hw_status
4016 __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
4017 {
4018         enum vxge_hw_status status;
4019
4020         status = __vxge_hw_device_register_poll(
4021                         &vpath->hldev->common_reg->vpath_rst_in_prog,
4022                         VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
4023                                 1 << (16 - vpath->vp_id)),
4024                         vpath->hldev->config.device_poll_millis);
4025
4026         return status;
4027 }
4028
4029 /*
4030  * __vxge_hw_vpath_reset
4031  * This routine resets the vpath on the device
4032  */
4033 static enum vxge_hw_status
4034 __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4035 {
4036         u64 val64;
4037
4038         val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
4039
4040         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4041                                 &hldev->common_reg->cmn_rsthdlr_cfg0);
4042
4043         return VXGE_HW_OK;
4044 }
4045
4046 /*
4047  * __vxge_hw_vpath_sw_reset
4048  * This routine resets the vpath structures
4049  */
4050 static enum vxge_hw_status
4051 __vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4052 {
4053         enum vxge_hw_status status = VXGE_HW_OK;
4054         struct __vxge_hw_virtualpath *vpath;
4055
4056         vpath = &hldev->virtual_paths[vp_id];
4057
4058         if (vpath->ringh) {
4059                 status = __vxge_hw_ring_reset(vpath->ringh);
4060                 if (status != VXGE_HW_OK)
4061                         goto exit;
4062         }
4063
4064         if (vpath->fifoh)
4065                 status = __vxge_hw_fifo_reset(vpath->fifoh);
4066 exit:
4067         return status;
4068 }
4069
4070 /*
4071  * __vxge_hw_vpath_prc_configure
4072  * This routine configures the prc registers of virtual path using the config
4073  * passed
4074  */
4075 static void
4076 __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4077 {
4078         u64 val64;
4079         struct __vxge_hw_virtualpath *vpath;
4080         struct vxge_hw_vp_config *vp_config;
4081         struct vxge_hw_vpath_reg __iomem *vp_reg;
4082
4083         vpath = &hldev->virtual_paths[vp_id];
4084         vp_reg = vpath->vp_reg;
4085         vp_config = vpath->vp_config;
4086
4087         if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
4088                 return;
4089
4090         val64 = readq(&vp_reg->prc_cfg1);
4091         val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
4092         writeq(val64, &vp_reg->prc_cfg1);
4093
4094         val64 = readq(&vpath->vp_reg->prc_cfg6);
4095         val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
4096         writeq(val64, &vpath->vp_reg->prc_cfg6);
4097
4098         val64 = readq(&vp_reg->prc_cfg7);
4099
4100         if (vpath->vp_config->ring.scatter_mode !=
4101                 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
4102
4103                 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
4104
4105                 switch (vpath->vp_config->ring.scatter_mode) {
4106                 case VXGE_HW_RING_SCATTER_MODE_A:
4107                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4108                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
4109                         break;
4110                 case VXGE_HW_RING_SCATTER_MODE_B:
4111                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4112                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
4113                         break;
4114                 case VXGE_HW_RING_SCATTER_MODE_C:
4115                         val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4116                                         VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
4117                         break;
4118                 }
4119         }
4120
4121         writeq(val64, &vp_reg->prc_cfg7);
4122
4123         writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
4124                                 __vxge_hw_ring_first_block_address_get(
4125                                         vpath->ringh) >> 3), &vp_reg->prc_cfg5);
4126
4127         val64 = readq(&vp_reg->prc_cfg4);
4128         val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
4129         val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
4130
4131         val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
4132                         VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
4133
4134         if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
4135                 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
4136         else
4137                 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
4138
4139         writeq(val64, &vp_reg->prc_cfg4);
4140 }
4141
4142 /*
4143  * __vxge_hw_vpath_kdfc_configure
4144  * This routine configures the kdfc registers of virtual path using the
4145  * config passed
4146  */
4147 static enum vxge_hw_status
4148 __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4149 {
4150         u64 val64;
4151         u64 vpath_stride;
4152         enum vxge_hw_status status = VXGE_HW_OK;
4153         struct __vxge_hw_virtualpath *vpath;
4154         struct vxge_hw_vpath_reg __iomem *vp_reg;
4155
4156         vpath = &hldev->virtual_paths[vp_id];
4157         vp_reg = vpath->vp_reg;
4158         status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
4159
4160         if (status != VXGE_HW_OK)
4161                 goto exit;
4162
4163         val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
4164
4165         vpath->max_kdfc_db =
4166                 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
4167                         val64+1)/2;
4168
4169         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4170
4171                 vpath->max_nofl_db = vpath->max_kdfc_db;
4172
4173                 if (vpath->max_nofl_db <
4174                         ((vpath->vp_config->fifo.memblock_size /
4175                         (vpath->vp_config->fifo.max_frags *
4176                         sizeof(struct vxge_hw_fifo_txd))) *
4177                         vpath->vp_config->fifo.fifo_blocks)) {
4178
4179                         return VXGE_HW_BADCFG_FIFO_BLOCKS;
4180                 }
4181                 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
4182                                 (vpath->max_nofl_db*2)-1);
4183         }
4184
4185         writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
4186
4187         writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
4188                 &vp_reg->kdfc_fifo_trpl_ctrl);
4189
4190         val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
4191
4192         val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
4193                    VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
4194
4195         val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
4196                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
4197 #ifndef __BIG_ENDIAN
4198                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
4199 #endif
4200                  VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
4201
4202         writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
4203         writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
4204         wmb();
4205         vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
4206
4207         vpath->nofl_db =
4208                 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
4209                 (hldev->kdfc + (vp_id *
4210                 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
4211                                         vpath_stride)));
4212 exit:
4213         return status;
4214 }
4215
4216 /*
4217  * __vxge_hw_vpath_mac_configure
4218  * This routine configures the mac of virtual path using the config passed
4219  */
4220 static enum vxge_hw_status
4221 __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4222 {
4223         u64 val64;
4224         struct __vxge_hw_virtualpath *vpath;
4225         struct vxge_hw_vp_config *vp_config;
4226         struct vxge_hw_vpath_reg __iomem *vp_reg;
4227
4228         vpath = &hldev->virtual_paths[vp_id];
4229         vp_reg = vpath->vp_reg;
4230         vp_config = vpath->vp_config;
4231
4232         writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
4233                         vpath->vsport_number), &vp_reg->xmac_vsport_choice);
4234
4235         if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4236
4237                 val64 = readq(&vp_reg->xmac_rpa_vcfg);
4238
4239                 if (vp_config->rpa_strip_vlan_tag !=
4240                         VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
4241                         if (vp_config->rpa_strip_vlan_tag)
4242                                 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4243                         else
4244                                 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4245                 }
4246
4247                 writeq(val64, &vp_reg->xmac_rpa_vcfg);
4248                 val64 = readq(&vp_reg->rxmac_vcfg0);
4249
4250                 if (vp_config->mtu !=
4251                                 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
4252                         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4253                         if ((vp_config->mtu  +
4254                                 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
4255                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4256                                         vp_config->mtu  +
4257                                         VXGE_HW_MAC_HEADER_MAX_SIZE);
4258                         else
4259                                 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4260                                         vpath->max_mtu);
4261                 }
4262
4263                 writeq(val64, &vp_reg->rxmac_vcfg0);
4264
4265                 val64 = readq(&vp_reg->rxmac_vcfg1);
4266
4267                 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
4268                         VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
4269
4270                 if (hldev->config.rth_it_type ==
4271                                 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
4272                         val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
4273                                 0x2) |
4274                                 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
4275                 }
4276
4277                 writeq(val64, &vp_reg->rxmac_vcfg1);
4278         }
4279         return VXGE_HW_OK;
4280 }
4281
4282 /*
4283  * __vxge_hw_vpath_tim_configure
4284  * This routine configures the tim registers of virtual path using the config
4285  * passed
4286  */
4287 static enum vxge_hw_status
4288 __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4289 {
4290         u64 val64;
4291         struct __vxge_hw_virtualpath *vpath;
4292         struct vxge_hw_vpath_reg __iomem *vp_reg;
4293         struct vxge_hw_vp_config *config;
4294
4295         vpath = &hldev->virtual_paths[vp_id];
4296         vp_reg = vpath->vp_reg;
4297         config = vpath->vp_config;
4298
4299         writeq(0, &vp_reg->tim_dest_addr);
4300         writeq(0, &vp_reg->tim_vpath_map);
4301         writeq(0, &vp_reg->tim_bitmap);
4302         writeq(0, &vp_reg->tim_remap);
4303
4304         if (config->ring.enable == VXGE_HW_RING_ENABLE)
4305                 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
4306                         (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4307                         VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
4308
4309         val64 = readq(&vp_reg->tim_pci_cfg);
4310         val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
4311         writeq(val64, &vp_reg->tim_pci_cfg);
4312
4313         if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4314
4315                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4316
4317                 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4318                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4319                                 0x3ffffff);
4320                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4321                                         config->tti.btimer_val);
4322                 }
4323
4324                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4325
4326                 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4327                         if (config->tti.timer_ac_en)
4328                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4329                         else
4330                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4331                 }
4332
4333                 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4334                         if (config->tti.timer_ci_en)
4335                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4336                         else
4337                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4338                 }
4339
4340                 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4341                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4342                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4343                                         config->tti.urange_a);
4344                 }
4345
4346                 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4347                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4348                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4349                                         config->tti.urange_b);
4350                 }
4351
4352                 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4353                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4354                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4355                                         config->tti.urange_c);
4356                 }
4357
4358                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4359                 vpath->tim_tti_cfg1_saved = val64;
4360
4361                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4362
4363                 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4364                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4365                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4366                                                 config->tti.uec_a);
4367                 }
4368
4369                 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4370                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4371                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4372                                                 config->tti.uec_b);
4373                 }
4374
4375                 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4376                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4377                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4378                                                 config->tti.uec_c);
4379                 }
4380
4381                 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4382                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4383                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4384                                                 config->tti.uec_d);
4385                 }
4386
4387                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4388                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4389
4390                 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4391                         if (config->tti.timer_ri_en)
4392                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4393                         else
4394                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4395                 }
4396
4397                 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4398                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4399                                         0x3ffffff);
4400                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4401                                         config->tti.rtimer_val);
4402                 }
4403
4404                 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4405                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4406                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4407                 }
4408
4409                 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4410                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4411                                         0x3ffffff);
4412                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4413                                         config->tti.ltimer_val);
4414                 }
4415
4416                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4417                 vpath->tim_tti_cfg3_saved = val64;
4418         }
4419
4420         if (config->ring.enable == VXGE_HW_RING_ENABLE) {
4421
4422                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4423
4424                 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4425                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4426                                         0x3ffffff);
4427                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4428                                         config->rti.btimer_val);
4429                 }
4430
4431                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4432
4433                 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4434                         if (config->rti.timer_ac_en)
4435                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4436                         else
4437                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4438                 }
4439
4440                 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4441                         if (config->rti.timer_ci_en)
4442                                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4443                         else
4444                                 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4445                 }
4446
4447                 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4448                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4449                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4450                                         config->rti.urange_a);
4451                 }
4452
4453                 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4454                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4455                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4456                                         config->rti.urange_b);
4457                 }
4458
4459                 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4460                         val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4461                         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4462                                         config->rti.urange_c);
4463                 }
4464
4465                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
4466                 vpath->tim_rti_cfg1_saved = val64;
4467
4468                 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4469
4470                 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4471                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4472                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4473                                                 config->rti.uec_a);
4474                 }
4475
4476                 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4477                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4478                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4479                                                 config->rti.uec_b);
4480                 }
4481
4482                 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4483                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4484                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4485                                                 config->rti.uec_c);
4486                 }
4487
4488                 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4489                         val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4490                         val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4491                                                 config->rti.uec_d);
4492                 }
4493
4494                 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4495                 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4496
4497                 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4498                         if (config->rti.timer_ri_en)
4499                                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4500                         else
4501                                 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4502                 }
4503
4504                 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4505                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4506                                         0x3ffffff);
4507                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4508                                         config->rti.rtimer_val);
4509                 }
4510
4511                 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4512                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4513                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
4514                 }
4515
4516                 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4517                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4518                                         0x3ffffff);
4519                         val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4520                                         config->rti.ltimer_val);
4521                 }
4522
4523                 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4524                 vpath->tim_rti_cfg3_saved = val64;
4525         }
4526
4527         val64 = 0;
4528         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4529         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4530         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4531         writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4532         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4533         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4534
4535         val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
4536         val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
4537         val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
4538         writeq(val64, &vp_reg->tim_wrkld_clc);
4539
4540         return VXGE_HW_OK;
4541 }
4542
4543 /*
4544  * __vxge_hw_vpath_initialize
4545  * This routine is the final phase of init which initializes the
4546  * registers of the vpath using the configuration passed.
4547  */
4548 static enum vxge_hw_status
4549 __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4550 {
4551         u64 val64;
4552         u32 val32;
4553         enum vxge_hw_status status = VXGE_HW_OK;
4554         struct __vxge_hw_virtualpath *vpath;
4555         struct vxge_hw_vpath_reg __iomem *vp_reg;
4556
4557         vpath = &hldev->virtual_paths[vp_id];
4558
4559         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4560                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4561                 goto exit;
4562         }
4563         vp_reg = vpath->vp_reg;
4564
4565         status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4566         if (status != VXGE_HW_OK)
4567                 goto exit;
4568
4569         status =  __vxge_hw_vpath_mac_configure(hldev, vp_id);
4570         if (status != VXGE_HW_OK)
4571                 goto exit;
4572
4573         status =  __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4574         if (status != VXGE_HW_OK)
4575                 goto exit;
4576
4577         status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4578         if (status != VXGE_HW_OK)
4579                 goto exit;
4580
4581         val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4582
4583         /* Get MRRS value from device control */
4584         status  = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4585         if (status == VXGE_HW_OK) {
4586                 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4587                 val64 &=
4588                     ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4589                 val64 |=
4590                     VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4591
4592                 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4593         }
4594
4595         val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4596         val64 |=
4597             VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4598                     VXGE_HW_MAX_PAYLOAD_SIZE_512);
4599
4600         val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4601         writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4602
4603 exit:
4604         return status;
4605 }
4606
4607 /*
4608  * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4609  * This routine closes all channels it opened and freeup memory
4610  */
4611 static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4612 {
4613         struct __vxge_hw_virtualpath *vpath;
4614
4615         vpath = &hldev->virtual_paths[vp_id];
4616
4617         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4618                 goto exit;
4619
4620         VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4621                 vpath->hldev->tim_int_mask1, vpath->vp_id);
4622         hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4623
4624         /* If the whole struct __vxge_hw_virtualpath is zeroed, nothing will
4625          * work after the interface is brought down.
4626          */
4627         spin_lock(&vpath->lock);
4628         vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4629         spin_unlock(&vpath->lock);
4630
4631         vpath->vpmgmt_reg = NULL;
4632         vpath->nofl_db = NULL;
4633         vpath->max_mtu = 0;
4634         vpath->vsport_number = 0;
4635         vpath->max_kdfc_db = 0;
4636         vpath->max_nofl_db = 0;
4637         vpath->ringh = NULL;
4638         vpath->fifoh = NULL;
4639         memset(&vpath->vpath_handles, 0, sizeof(struct list_head));
4640         vpath->stats_block = NULL;
4641         vpath->hw_stats = NULL;
4642         vpath->hw_stats_sav = NULL;
4643         vpath->sw_stats = NULL;
4644
4645 exit:
4646         return;
4647 }
4648
4649 /*
4650  * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4651  * This routine is the initial phase of init which resets the vpath and
4652  * initializes the software support structures.
4653  */
4654 static enum vxge_hw_status
4655 __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4656                         struct vxge_hw_vp_config *config)
4657 {
4658         struct __vxge_hw_virtualpath *vpath;
4659         enum vxge_hw_status status = VXGE_HW_OK;
4660
4661         if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4662                 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4663                 goto exit;
4664         }
4665
4666         vpath = &hldev->virtual_paths[vp_id];
4667
4668         spin_lock_init(&vpath->lock);
4669         vpath->vp_id = vp_id;
4670         vpath->vp_open = VXGE_HW_VP_OPEN;
4671         vpath->hldev = hldev;
4672         vpath->vp_config = config;
4673         vpath->vp_reg = hldev->vpath_reg[vp_id];
4674         vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4675
4676         __vxge_hw_vpath_reset(hldev, vp_id);
4677
4678         status = __vxge_hw_vpath_reset_check(vpath);
4679         if (status != VXGE_HW_OK) {
4680                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4681                 goto exit;
4682         }
4683
4684         status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4685         if (status != VXGE_HW_OK) {
4686                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4687                 goto exit;
4688         }
4689
4690         INIT_LIST_HEAD(&vpath->vpath_handles);
4691
4692         vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4693
4694         VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4695                 hldev->tim_int_mask1, vp_id);
4696
4697         status = __vxge_hw_vpath_initialize(hldev, vp_id);
4698         if (status != VXGE_HW_OK)
4699                 __vxge_hw_vp_terminate(hldev, vp_id);
4700 exit:
4701         return status;
4702 }
4703
4704 /*
4705  * vxge_hw_vpath_mtu_set - Set MTU.
4706  * Set new MTU value. Example, to use jumbo frames:
4707  * vxge_hw_vpath_mtu_set(my_device, 9600);
4708  */
4709 enum vxge_hw_status
4710 vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4711 {
4712         u64 val64;
4713         enum vxge_hw_status status = VXGE_HW_OK;
4714         struct __vxge_hw_virtualpath *vpath;
4715
4716         if (vp == NULL) {
4717                 status = VXGE_HW_ERR_INVALID_HANDLE;
4718                 goto exit;
4719         }
4720         vpath = vp->vpath;
4721
4722         new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4723
4724         if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4725                 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4726
4727         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4728
4729         val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4730         val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4731
4732         writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4733
4734         vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4735
4736 exit:
4737         return status;
4738 }
4739
4740 /*
4741  * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4742  * Enable the DMA vpath statistics. The function is to be called to re-enable
4743  * the adapter to update stats into the host memory
4744  */
4745 static enum vxge_hw_status
4746 vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4747 {
4748         enum vxge_hw_status status = VXGE_HW_OK;
4749         struct __vxge_hw_virtualpath *vpath;
4750
4751         vpath = vp->vpath;
4752
4753         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4754                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4755                 goto exit;
4756         }
4757
4758         memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4759                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4760
4761         status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4762 exit:
4763         return status;
4764 }
4765
4766 /*
4767  * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
4768  * This function allocates a block from block pool or from the system
4769  */
4770 static struct __vxge_hw_blockpool_entry *
4771 __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
4772 {
4773         struct __vxge_hw_blockpool_entry *entry = NULL;
4774         struct __vxge_hw_blockpool  *blockpool;
4775
4776         blockpool = &devh->block_pool;
4777
4778         if (size == blockpool->block_size) {
4779
4780                 if (!list_empty(&blockpool->free_block_list))
4781                         entry = (struct __vxge_hw_blockpool_entry *)
4782                                 list_first_entry(&blockpool->free_block_list,
4783                                         struct __vxge_hw_blockpool_entry,
4784                                         item);
4785
4786                 if (entry != NULL) {
4787                         list_del(&entry->item);
4788                         blockpool->pool_size--;
4789                 }
4790         }
4791
4792         if (entry != NULL)
4793                 __vxge_hw_blockpool_blocks_add(blockpool);
4794
4795         return entry;
4796 }
4797
4798 /*
4799  * vxge_hw_vpath_open - Open a virtual path on a given adapter
4800  * This function is used to open access to virtual path of an
4801  * adapter for offload, GRO operations. This function returns
4802  * synchronously.
4803  */
4804 enum vxge_hw_status
4805 vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4806                    struct vxge_hw_vpath_attr *attr,
4807                    struct __vxge_hw_vpath_handle **vpath_handle)
4808 {
4809         struct __vxge_hw_virtualpath *vpath;
4810         struct __vxge_hw_vpath_handle *vp;
4811         enum vxge_hw_status status;
4812
4813         vpath = &hldev->virtual_paths[attr->vp_id];
4814
4815         if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4816                 status = VXGE_HW_ERR_INVALID_STATE;
4817                 goto vpath_open_exit1;
4818         }
4819
4820         status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4821                         &hldev->config.vp_config[attr->vp_id]);
4822         if (status != VXGE_HW_OK)
4823                 goto vpath_open_exit1;
4824
4825         vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
4826         if (vp == NULL) {
4827                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4828                 goto vpath_open_exit2;
4829         }
4830
4831         vp->vpath = vpath;
4832
4833         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4834                 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4835                 if (status != VXGE_HW_OK)
4836                         goto vpath_open_exit6;
4837         }
4838
4839         if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4840                 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4841                 if (status != VXGE_HW_OK)
4842                         goto vpath_open_exit7;
4843
4844                 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4845         }
4846
4847         vpath->fifoh->tx_intr_num =
4848                 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP)  +
4849                         VXGE_HW_VPATH_INTR_TX;
4850
4851         vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4852                                 VXGE_HW_BLOCK_SIZE);
4853         if (vpath->stats_block == NULL) {
4854                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4855                 goto vpath_open_exit8;
4856         }
4857
4858         vpath->hw_stats = vpath->stats_block->memblock;
4859         memset(vpath->hw_stats, 0,
4860                 sizeof(struct vxge_hw_vpath_stats_hw_info));
4861
4862         hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4863                                                 vpath->hw_stats;
4864
4865         vpath->hw_stats_sav =
4866                 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4867         memset(vpath->hw_stats_sav, 0,
4868                         sizeof(struct vxge_hw_vpath_stats_hw_info));
4869
4870         writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4871
4872         status = vxge_hw_vpath_stats_enable(vp);
4873         if (status != VXGE_HW_OK)
4874                 goto vpath_open_exit8;
4875
4876         list_add(&vp->item, &vpath->vpath_handles);
4877
4878         hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4879
4880         *vpath_handle = vp;
4881
4882         attr->fifo_attr.userdata = vpath->fifoh;
4883         attr->ring_attr.userdata = vpath->ringh;
4884
4885         return VXGE_HW_OK;
4886
4887 vpath_open_exit8:
4888         if (vpath->ringh != NULL)
4889                 __vxge_hw_ring_delete(vp);
4890 vpath_open_exit7:
4891         if (vpath->fifoh != NULL)
4892                 __vxge_hw_fifo_delete(vp);
4893 vpath_open_exit6:
4894         vfree(vp);
4895 vpath_open_exit2:
4896         __vxge_hw_vp_terminate(hldev, attr->vp_id);
4897 vpath_open_exit1:
4898
4899         return status;
4900 }
4901
4902 /**
4903  * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4904  * (vpath) open
4905  * @vp: Handle got from previous vpath open
4906  *
4907  * This function is used to close access to virtual path opened
4908  * earlier.
4909  */
4910 void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4911 {
4912         struct __vxge_hw_virtualpath *vpath = vp->vpath;
4913         struct __vxge_hw_ring *ring = vpath->ringh;
4914         struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
4915         u64 new_count, val64, val164;
4916
4917         if (vdev->titan1) {
4918                 new_count = readq(&vpath->vp_reg->rxdmem_size);
4919                 new_count &= 0x1fff;
4920         } else
4921                 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
4922
4923         val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
4924
4925         writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4926                 &vpath->vp_reg->prc_rxd_doorbell);
4927         readl(&vpath->vp_reg->prc_rxd_doorbell);
4928
4929         val164 /= 2;
4930         val64 = readq(&vpath->vp_reg->prc_cfg6);
4931         val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4932         val64 &= 0x1ff;
4933
4934         /*
4935          * Each RxD is of 4 qwords
4936          */
4937         new_count -= (val64 + 1);
4938         val64 = min(val164, new_count) / 4;
4939
4940         ring->rxds_limit = min(ring->rxds_limit, val64);
4941         if (ring->rxds_limit < 4)
4942                 ring->rxds_limit = 4;
4943 }
4944
4945 /*
4946  * __vxge_hw_blockpool_block_free - Frees a block from block pool
4947  * @devh: Hal device
4948  * @entry: Entry of block to be freed
4949  *
4950  * This function frees a block from block pool
4951  */
4952 static void
4953 __vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
4954                                struct __vxge_hw_blockpool_entry *entry)
4955 {
4956         struct __vxge_hw_blockpool  *blockpool;
4957
4958         blockpool = &devh->block_pool;
4959
4960         if (entry->length == blockpool->block_size) {
4961                 list_add(&entry->item, &blockpool->free_block_list);
4962                 blockpool->pool_size++;
4963         }
4964
4965         __vxge_hw_blockpool_blocks_remove(blockpool);
4966 }
4967
4968 /*
4969  * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4970  * This function is used to close access to virtual path opened
4971  * earlier.
4972  */
4973 enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4974 {
4975         struct __vxge_hw_virtualpath *vpath = NULL;
4976         struct __vxge_hw_device *devh = NULL;
4977         u32 vp_id = vp->vpath->vp_id;
4978         u32 is_empty = TRUE;
4979         enum vxge_hw_status status = VXGE_HW_OK;
4980
4981         vpath = vp->vpath;
4982         devh = vpath->hldev;
4983
4984         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4985                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4986                 goto vpath_close_exit;
4987         }
4988
4989         list_del(&vp->item);
4990
4991         if (!list_empty(&vpath->vpath_handles)) {
4992                 list_add(&vp->item, &vpath->vpath_handles);
4993                 is_empty = FALSE;
4994         }
4995
4996         if (!is_empty) {
4997                 status = VXGE_HW_FAIL;
4998                 goto vpath_close_exit;
4999         }
5000
5001         devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
5002
5003         if (vpath->ringh != NULL)
5004                 __vxge_hw_ring_delete(vp);
5005
5006         if (vpath->fifoh != NULL)
5007                 __vxge_hw_fifo_delete(vp);
5008
5009         if (vpath->stats_block != NULL)
5010                 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
5011
5012         vfree(vp);
5013
5014         __vxge_hw_vp_terminate(devh, vp_id);
5015
5016 vpath_close_exit:
5017         return status;
5018 }
5019
5020 /*
5021  * vxge_hw_vpath_reset - Resets vpath
5022  * This function is used to request a reset of vpath
5023  */
5024 enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
5025 {
5026         enum vxge_hw_status status;
5027         u32 vp_id;
5028         struct __vxge_hw_virtualpath *vpath = vp->vpath;
5029
5030         vp_id = vpath->vp_id;
5031
5032         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5033                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5034                 goto exit;
5035         }
5036
5037         status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
5038         if (status == VXGE_HW_OK)
5039                 vpath->sw_stats->soft_reset_cnt++;
5040 exit:
5041         return status;
5042 }
5043
5044 /*
5045  * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
5046  * This function poll's for the vpath reset completion and re initializes
5047  * the vpath.
5048  */
5049 enum vxge_hw_status
5050 vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
5051 {
5052         struct __vxge_hw_virtualpath *vpath = NULL;
5053         enum vxge_hw_status status;
5054         struct __vxge_hw_device *hldev;
5055         u32 vp_id;
5056
5057         vp_id = vp->vpath->vp_id;
5058         vpath = vp->vpath;
5059         hldev = vpath->hldev;
5060
5061         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5062                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5063                 goto exit;
5064         }
5065
5066         status = __vxge_hw_vpath_reset_check(vpath);
5067         if (status != VXGE_HW_OK)
5068                 goto exit;
5069
5070         status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
5071         if (status != VXGE_HW_OK)
5072                 goto exit;
5073
5074         status = __vxge_hw_vpath_initialize(hldev, vp_id);
5075         if (status != VXGE_HW_OK)
5076                 goto exit;
5077
5078         if (vpath->ringh != NULL)
5079                 __vxge_hw_vpath_prc_configure(hldev, vp_id);
5080
5081         memset(vpath->hw_stats, 0,
5082                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5083
5084         memset(vpath->hw_stats_sav, 0,
5085                 sizeof(struct vxge_hw_vpath_stats_hw_info));
5086
5087         writeq(vpath->stats_block->dma_addr,
5088                 &vpath->vp_reg->stats_cfg);
5089
5090         status = vxge_hw_vpath_stats_enable(vp);
5091
5092 exit:
5093         return status;
5094 }
5095
5096 /*
5097  * vxge_hw_vpath_enable - Enable vpath.
5098  * This routine clears the vpath reset thereby enabling a vpath
5099  * to start forwarding frames and generating interrupts.
5100  */
5101 void
5102 vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
5103 {
5104         struct __vxge_hw_device *hldev;
5105         u64 val64;
5106
5107         hldev = vp->vpath->hldev;
5108
5109         val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
5110                 1 << (16 - vp->vpath->vp_id));
5111
5112         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
5113                 &hldev->common_reg->cmn_rsthdlr_cfg1);
5114 }