drivers/net/ethernet/neterion/vxge/vxge-traffic.c

   1 /******************************************************************************
   2  * This software may be used and distributed according to the terms of
   3  * the GNU General Public License (GPL), incorporated herein by reference.
   4  * Drivers based on or derived from this code fall under the GPL and must
   5  * retain the authorship, copyright and license notice.  This file is not
   6  * a complete program and may only be used when the entire operating
   7  * system is licensed under the GPL.
   8  * See the file COPYING in this distribution for more information.
   9  *
  10  * vxge-traffic.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
  11  *                 Virtualized Server Adapter.
  12  * Copyright(c) 2002-2010 Exar Corp.
  13  ******************************************************************************/
  14 #include <linux/etherdevice.h>
  15 #include <linux/io-64-nonatomic-lo-hi.h>
  16 #include <linux/prefetch.h>
  17
  18 #include "vxge-traffic.h"
  19 #include "vxge-config.h"
  20 #include "vxge-main.h"
  21
  22 /*
  23  * vxge_hw_vpath_intr_enable - Enable vpath interrupts.
  24  * @vp: Virtual Path handle.
  25  *
  26  * Enable vpath interrupts. The function is to be executed the last in
  27  * vpath initialization sequence.
  28  *
  29  * See also: vxge_hw_vpath_intr_disable()
  30  */
  31 enum vxge_hw_status vxge_hw_vpath_intr_enable(struct __vxge_hw_vpath_handle *vp)
  32 {
  33         u64 val64;
  34
  35         struct __vxge_hw_virtualpath *vpath;
  36         struct vxge_hw_vpath_reg __iomem *vp_reg;
  37         enum vxge_hw_status status = VXGE_HW_OK;
  38         if (vp == NULL) {
  39                 status = VXGE_HW_ERR_INVALID_HANDLE;
  40                 goto exit;
  41         }
  42
  43         vpath = vp->vpath;
  44
  45         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
  46                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
  47                 goto exit;
  48         }
  49
  50         vp_reg = vpath->vp_reg;
  51
  52         writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg);
  53
  54         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  55                         &vp_reg->general_errors_reg);
  56
  57         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  58                         &vp_reg->pci_config_errors_reg);
  59
  60         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  61                         &vp_reg->mrpcim_to_vpath_alarm_reg);
  62
  63         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  64                         &vp_reg->srpcim_to_vpath_alarm_reg);
  65
  66         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  67                         &vp_reg->vpath_ppif_int_status);
  68
  69         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  70                         &vp_reg->srpcim_msg_to_vpath_reg);
  71
  72         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  73                         &vp_reg->vpath_pcipif_int_status);
  74
  75         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  76                         &vp_reg->prc_alarm_reg);
  77
  78         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  79                         &vp_reg->wrdma_alarm_status);
  80
  81         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  82                         &vp_reg->asic_ntwk_vp_err_reg);
  83
  84         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  85                         &vp_reg->xgmac_vp_int_status);
  86
  87         val64 = readq(&vp_reg->vpath_general_int_status);
  88
  89         /* Mask unwanted interrupts */
  90
  91         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  92                         &vp_reg->vpath_pcipif_int_mask);
  93
  94         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  95                         &vp_reg->srpcim_msg_to_vpath_mask);
  96
  97         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  98                         &vp_reg->srpcim_to_vpath_alarm_mask);
  99
 100         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 101                         &vp_reg->mrpcim_to_vpath_alarm_mask);
 102
 103         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 104                         &vp_reg->pci_config_errors_mask);
 105
 106         /* Unmask the individual interrupts */
 107
 108         writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW|
 109                 VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW|
 110                 VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ|
 111                 VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32),
 112                 &vp_reg->general_errors_mask);
 113
 114         __vxge_hw_pio_mem_write32_upper(
 115                 (u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR|
 116                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR|
 117                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON|
 118                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON|
 119                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR|
 120                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR), 0, 32),
 121                 &vp_reg->kdfcctl_errors_mask);
 122
 123         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask);
 124
 125         __vxge_hw_pio_mem_write32_upper(
 126                 (u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32),
 127                 &vp_reg->prc_alarm_mask);
 128
 129         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask);
 130         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask);
 131
 132         if (vpath->hldev->first_vp_id != vpath->vp_id)
 133                 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 134                         &vp_reg->asic_ntwk_vp_err_mask);
 135         else
 136                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn((
 137                 VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT |
 138                 VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK), 0, 32),
 139                 &vp_reg->asic_ntwk_vp_err_mask);
 140
 141         __vxge_hw_pio_mem_write32_upper(0,
 142                 &vp_reg->vpath_general_int_mask);
 143 exit:
 144         return status;
 145
 146 }
 147
 148 /*
 149  * vxge_hw_vpath_intr_disable - Disable vpath interrupts.
 150  * @vp: Virtual Path handle.
 151  *
 152  * Disable vpath interrupts. The function is to be executed the last in
 153  * vpath initialization sequence.
 154  *
 155  * See also: vxge_hw_vpath_intr_enable()
 156  */
 157 enum vxge_hw_status vxge_hw_vpath_intr_disable(
 158                         struct __vxge_hw_vpath_handle *vp)
 159 {
 160         u64 val64;
 161
 162         struct __vxge_hw_virtualpath *vpath;
 163         enum vxge_hw_status status = VXGE_HW_OK;
 164         struct vxge_hw_vpath_reg __iomem *vp_reg;
 165         if (vp == NULL) {
 166                 status = VXGE_HW_ERR_INVALID_HANDLE;
 167                 goto exit;
 168         }
 169
 170         vpath = vp->vpath;
 171
 172         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
 173                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
 174                 goto exit;
 175         }
 176         vp_reg = vpath->vp_reg;
 177
 178         __vxge_hw_pio_mem_write32_upper(
 179                 (u32)VXGE_HW_INTR_MASK_ALL,
 180                 &vp_reg->vpath_general_int_mask);
 181
 182         val64 = VXGE_HW_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id));
 183
 184         writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask);
 185
 186         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 187                         &vp_reg->general_errors_mask);
 188
 189         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 190                         &vp_reg->pci_config_errors_mask);
 191
 192         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 193                         &vp_reg->mrpcim_to_vpath_alarm_mask);
 194
 195         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 196                         &vp_reg->srpcim_to_vpath_alarm_mask);
 197
 198         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 199                         &vp_reg->vpath_ppif_int_mask);
 200
 201         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 202                         &vp_reg->srpcim_msg_to_vpath_mask);
 203
 204         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 205                         &vp_reg->vpath_pcipif_int_mask);
 206
 207         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 208                         &vp_reg->wrdma_alarm_mask);
 209
 210         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 211                         &vp_reg->prc_alarm_mask);
 212
 213         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 214                         &vp_reg->xgmac_vp_int_mask);
 215
 216         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
 217                         &vp_reg->asic_ntwk_vp_err_mask);
 218
 219 exit:
 220         return status;
 221 }
 222
 223 void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo)
 224 {
 225         struct vxge_hw_vpath_reg __iomem *vp_reg;
 226         struct vxge_hw_vp_config *config;
 227         u64 val64;
 228
 229         if (fifo->config->enable != VXGE_HW_FIFO_ENABLE)
 230                 return;
 231
 232         vp_reg = fifo->vp_reg;
 233         config = container_of(fifo->config, struct vxge_hw_vp_config, fifo);
 234
 235         if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
 236                 config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
 237                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
 238                 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
 239                 fifo->tim_tti_cfg1_saved = val64;
 240                 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
 241         }
 242 }
 243
 244 void vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring)
 245 {
 246         u64 val64 = ring->tim_rti_cfg1_saved;
 247
 248         val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
 249         ring->tim_rti_cfg1_saved = val64;
 250         writeq(val64, &ring->vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
 251 }
 252
 253 void vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo)
 254 {
 255         u64 val64 = fifo->tim_tti_cfg3_saved;
 256         u64 timer = (fifo->rtimer * 1000) / 272;
 257
 258         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
 259         if (timer)
 260                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
 261                         VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5);
 262
 263         writeq(val64, &fifo->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
 264         /* tti_cfg3_saved is not updated again because it is
 265          * initialized at one place only - init time.
 266          */
 267 }
 268
 269 void vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring)
 270 {
 271         u64 val64 = ring->tim_rti_cfg3_saved;
 272         u64 timer = (ring->rtimer * 1000) / 272;
 273
 274         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
 275         if (timer)
 276                 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
 277                         VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4);
 278
 279         writeq(val64, &ring->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
 280         /* rti_cfg3_saved is not updated again because it is
 281          * initialized at one place only - init time.
 282          */
 283 }
 284
 285 /**
 286  * vxge_hw_channel_msix_mask - Mask MSIX Vector.
 287  * @channeh: Channel for rx or tx handle
 288  * @msix_id:  MSIX ID
 289  *
 290  * The function masks the msix interrupt for the given msix_id
 291  *
 292  * Returns: 0
 293  */
 294 void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id)
 295 {
 296
 297         __vxge_hw_pio_mem_write32_upper(
 298                 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
 299                 &channel->common_reg->set_msix_mask_vect[msix_id%4]);
 300 }
 301
 302 /**
 303  * vxge_hw_channel_msix_unmask - Unmask the MSIX Vector.
 304  * @channeh: Channel for rx or tx handle
 305  * @msix_id:  MSI ID
 306  *
 307  * The function unmasks the msix interrupt for the given msix_id
 308  *
 309  * Returns: 0
 310  */
 311 void
 312 vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
 313 {
 314
 315         __vxge_hw_pio_mem_write32_upper(
 316                 (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
 317                 &channel->common_reg->clear_msix_mask_vect[msix_id%4]);
 318 }
 319
 320 /**
 321  * vxge_hw_channel_msix_clear - Unmask the MSIX Vector.
 322  * @channel: Channel for rx or tx handle
 323  * @msix_id:  MSI ID
 324  *
 325  * The function unmasks the msix interrupt for the given msix_id
 326  * if configured in MSIX oneshot mode
 327  *
 328  * Returns: 0
 329  */
 330 void vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channel, int msix_id)
 331 {
 332         __vxge_hw_pio_mem_write32_upper(
 333                 (u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
 334                 &channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
 335 }
 336
 337 /**
 338  * vxge_hw_device_set_intr_type - Updates the configuration
 339  *              with new interrupt type.
 340  * @hldev: HW device handle.
 341  * @intr_mode: New interrupt type
 342  */
 343 u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *hldev, u32 intr_mode)
 344 {
 345
 346         if ((intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
 347            (intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
 348            (intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
 349            (intr_mode != VXGE_HW_INTR_MODE_DEF))
 350                 intr_mode = VXGE_HW_INTR_MODE_IRQLINE;
 351
 352         hldev->config.intr_mode = intr_mode;
 353         return intr_mode;
 354 }
 355
 356 /**
 357  * vxge_hw_device_intr_enable - Enable interrupts.
 358  * @hldev: HW device handle.
 359  * @op: One of the enum vxge_hw_device_intr enumerated values specifying
 360  *      the type(s) of interrupts to enable.
 361  *
 362  * Enable Titan interrupts. The function is to be executed the last in
 363  * Titan initialization sequence.
 364  *
 365  * See also: vxge_hw_device_intr_disable()
 366  */
 367 void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev)
 368 {
 369         u32 i;
 370         u64 val64;
 371         u32 val32;
 372
 373         vxge_hw_device_mask_all(hldev);
 374
 375         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 376
 377                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 378                         continue;
 379
 380                 vxge_hw_vpath_intr_enable(
 381                         VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
 382         }
 383
 384         if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE) {
 385                 val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
 386                         hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
 387
 388                 if (val64 != 0) {
 389                         writeq(val64, &hldev->common_reg->tim_int_status0);
 390
 391                         writeq(~val64, &hldev->common_reg->tim_int_mask0);
 392                 }
 393
 394                 val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
 395                         hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX];
 396
 397                 if (val32 != 0) {
 398                         __vxge_hw_pio_mem_write32_upper(val32,
 399                                         &hldev->common_reg->tim_int_status1);
 400
 401                         __vxge_hw_pio_mem_write32_upper(~val32,
 402                                         &hldev->common_reg->tim_int_mask1);
 403                 }
 404         }
 405
 406         val64 = readq(&hldev->common_reg->titan_general_int_status);
 407
 408         vxge_hw_device_unmask_all(hldev);
 409 }
 410
 411 /**
 412  * vxge_hw_device_intr_disable - Disable Titan interrupts.
 413  * @hldev: HW device handle.
 414  * @op: One of the enum vxge_hw_device_intr enumerated values specifying
 415  *      the type(s) of interrupts to disable.
 416  *
 417  * Disable Titan interrupts.
 418  *
 419  * See also: vxge_hw_device_intr_enable()
 420  */
 421 void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev)
 422 {
 423         u32 i;
 424
 425         vxge_hw_device_mask_all(hldev);
 426
 427         /* mask all the tim interrupts */
 428         writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
 429         __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32,
 430                 &hldev->common_reg->tim_int_mask1);
 431
 432         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 433
 434                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 435                         continue;
 436
 437                 vxge_hw_vpath_intr_disable(
 438                         VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
 439         }
 440 }
 441
 442 /**
 443  * vxge_hw_device_mask_all - Mask all device interrupts.
 444  * @hldev: HW device handle.
 445  *
 446  * Mask all device interrupts.
 447  *
 448  * See also: vxge_hw_device_unmask_all()
 449  */
 450 void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
 451 {
 452         u64 val64;
 453
 454         val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM |
 455                 VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
 456
 457         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
 458                                 &hldev->common_reg->titan_mask_all_int);
 459 }
 460
 461 /**
 462  * vxge_hw_device_unmask_all - Unmask all device interrupts.
 463  * @hldev: HW device handle.
 464  *
 465  * Unmask all device interrupts.
 466  *
 467  * See also: vxge_hw_device_mask_all()
 468  */
 469 void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev)
 470 {
 471         u64 val64 = 0;
 472
 473         if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE)
 474                 val64 =  VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
 475
 476         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
 477                         &hldev->common_reg->titan_mask_all_int);
 478 }
 479
 480 /**
 481  * vxge_hw_device_flush_io - Flush io writes.
 482  * @hldev: HW device handle.
 483  *
 484  * The function performs a read operation to flush io writes.
 485  *
 486  * Returns: void
 487  */
 488 void vxge_hw_device_flush_io(struct __vxge_hw_device *hldev)
 489 {
 490         u32 val32;
 491
 492         val32 = readl(&hldev->common_reg->titan_general_int_status);
 493 }
 494
 495 /**
 496  * __vxge_hw_device_handle_error - Handle error
 497  * @hldev: HW device
 498  * @vp_id: Vpath Id
 499  * @type: Error type. Please see enum vxge_hw_event{}
 500  *
 501  * Handle error.
 502  */
 503 static enum vxge_hw_status
 504 __vxge_hw_device_handle_error(struct __vxge_hw_device *hldev, u32 vp_id,
 505                               enum vxge_hw_event type)
 506 {
 507         switch (type) {
 508         case VXGE_HW_EVENT_UNKNOWN:
 509                 break;
 510         case VXGE_HW_EVENT_RESET_START:
 511         case VXGE_HW_EVENT_RESET_COMPLETE:
 512         case VXGE_HW_EVENT_LINK_DOWN:
 513         case VXGE_HW_EVENT_LINK_UP:
 514                 goto out;
 515         case VXGE_HW_EVENT_ALARM_CLEARED:
 516                 goto out;
 517         case VXGE_HW_EVENT_ECCERR:
 518         case VXGE_HW_EVENT_MRPCIM_ECCERR:
 519                 goto out;
 520         case VXGE_HW_EVENT_FIFO_ERR:
 521         case VXGE_HW_EVENT_VPATH_ERR:
 522         case VXGE_HW_EVENT_CRITICAL_ERR:
 523         case VXGE_HW_EVENT_SERR:
 524                 break;
 525         case VXGE_HW_EVENT_SRPCIM_SERR:
 526         case VXGE_HW_EVENT_MRPCIM_SERR:
 527                 goto out;
 528         case VXGE_HW_EVENT_SLOT_FREEZE:
 529                 break;
 530         default:
 531                 vxge_assert(0);
 532                 goto out;
 533         }
 534
 535         /* notify driver */
 536         if (hldev->uld_callbacks->crit_err)
 537                 hldev->uld_callbacks->crit_err(hldev,
 538                         type, vp_id);
 539 out:
 540
 541         return VXGE_HW_OK;
 542 }
 543
 544 /*
 545  * __vxge_hw_device_handle_link_down_ind
 546  * @hldev: HW device handle.
 547  *
 548  * Link down indication handler. The function is invoked by HW when
 549  * Titan indicates that the link is down.
 550  */
 551 static enum vxge_hw_status
 552 __vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev)
 553 {
 554         /*
 555          * If the previous link state is not down, return.
 556          */
 557         if (hldev->link_state == VXGE_HW_LINK_DOWN)
 558                 goto exit;
 559
 560         hldev->link_state = VXGE_HW_LINK_DOWN;
 561
 562         /* notify driver */
 563         if (hldev->uld_callbacks->link_down)
 564                 hldev->uld_callbacks->link_down(hldev);
 565 exit:
 566         return VXGE_HW_OK;
 567 }
 568
 569 /*
 570  * __vxge_hw_device_handle_link_up_ind
 571  * @hldev: HW device handle.
 572  *
 573  * Link up indication handler. The function is invoked by HW when
 574  * Titan indicates that the link is up for programmable amount of time.
 575  */
 576 static enum vxge_hw_status
 577 __vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev)
 578 {
 579         /*
 580          * If the previous link state is not down, return.
 581          */
 582         if (hldev->link_state == VXGE_HW_LINK_UP)
 583                 goto exit;
 584
 585         hldev->link_state = VXGE_HW_LINK_UP;
 586
 587         /* notify driver */
 588         if (hldev->uld_callbacks->link_up)
 589                 hldev->uld_callbacks->link_up(hldev);
 590 exit:
 591         return VXGE_HW_OK;
 592 }
 593
 594 /*
 595  * __vxge_hw_vpath_alarm_process - Process Alarms.
 596  * @vpath: Virtual Path.
 597  * @skip_alarms: Do not clear the alarms
 598  *
 599  * Process vpath alarms.
 600  *
 601  */
 602 static enum vxge_hw_status
 603 __vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath,
 604                               u32 skip_alarms)
 605 {
 606         u64 val64;
 607         u64 alarm_status;
 608         u64 pic_status;
 609         struct __vxge_hw_device *hldev = NULL;
 610         enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN;
 611         u64 mask64;
 612         struct vxge_hw_vpath_stats_sw_info *sw_stats;
 613         struct vxge_hw_vpath_reg __iomem *vp_reg;
 614
 615         if (vpath == NULL) {
 616                 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
 617                         alarm_event);
 618                 goto out2;
 619         }
 620
 621         hldev = vpath->hldev;
 622         vp_reg = vpath->vp_reg;
 623         alarm_status = readq(&vp_reg->vpath_general_int_status);
 624
 625         if (alarm_status == VXGE_HW_ALL_FOXES) {
 626                 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_SLOT_FREEZE,
 627                         alarm_event);
 628                 goto out;
 629         }
 630
 631         sw_stats = vpath->sw_stats;
 632
 633         if (alarm_status & ~(
 634                 VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
 635                 VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
 636                 VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
 637                 VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
 638                 sw_stats->error_stats.unknown_alarms++;
 639
 640                 alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
 641                         alarm_event);
 642                 goto out;
 643         }
 644
 645         if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
 646
 647                 val64 = readq(&vp_reg->xgmac_vp_int_status);
 648
 649                 if (val64 &
 650                 VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
 651
 652                         val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
 653
 654                         if (((val64 &
 655                               VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
 656                              (!(val64 &
 657                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
 658                             ((val64 &
 659                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) &&
 660                              (!(val64 &
 661                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
 662                                      ))) {
 663                                 sw_stats->error_stats.network_sustained_fault++;
 664
 665                                 writeq(
 666                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
 667                                         &vp_reg->asic_ntwk_vp_err_mask);
 668
 669                                 __vxge_hw_device_handle_link_down_ind(hldev);
 670                                 alarm_event = VXGE_HW_SET_LEVEL(
 671                                         VXGE_HW_EVENT_LINK_DOWN, alarm_event);
 672                         }
 673
 674                         if (((val64 &
 675                               VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
 676                              (!(val64 &
 677                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
 678                             ((val64 &
 679                               VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) &&
 680                              (!(val64 &
 681                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
 682                                      ))) {
 683
 684                                 sw_stats->error_stats.network_sustained_ok++;
 685
 686                                 writeq(
 687                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
 688                                         &vp_reg->asic_ntwk_vp_err_mask);
 689
 690                                 __vxge_hw_device_handle_link_up_ind(hldev);
 691                                 alarm_event = VXGE_HW_SET_LEVEL(
 692                                         VXGE_HW_EVENT_LINK_UP, alarm_event);
 693                         }
 694
 695                         writeq(VXGE_HW_INTR_MASK_ALL,
 696                                 &vp_reg->asic_ntwk_vp_err_reg);
 697
 698                         alarm_event = VXGE_HW_SET_LEVEL(
 699                                 VXGE_HW_EVENT_ALARM_CLEARED, alarm_event);
 700
 701                         if (skip_alarms)
 702                                 return VXGE_HW_OK;
 703                 }
 704         }
 705
 706         if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) {
 707
 708                 pic_status = readq(&vp_reg->vpath_ppif_int_status);
 709
 710                 if (pic_status &
 711                     VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) {
 712
 713                         val64 = readq(&vp_reg->general_errors_reg);
 714                         mask64 = readq(&vp_reg->general_errors_mask);
 715
 716                         if ((val64 &
 717                                 VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) &
 718                                 ~mask64) {
 719                                 sw_stats->error_stats.ini_serr_det++;
 720
 721                                 alarm_event = VXGE_HW_SET_LEVEL(
 722                                         VXGE_HW_EVENT_SERR, alarm_event);
 723                         }
 724
 725                         if ((val64 &
 726                             VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) &
 727                                 ~mask64) {
 728                                 sw_stats->error_stats.dblgen_fifo0_overflow++;
 729
 730                                 alarm_event = VXGE_HW_SET_LEVEL(
 731                                         VXGE_HW_EVENT_FIFO_ERR, alarm_event);
 732                         }
 733
 734                         if ((val64 &
 735                             VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) &
 736                                 ~mask64)
 737                                 sw_stats->error_stats.statsb_pif_chain_error++;
 738
 739                         if ((val64 &
 740                            VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) &
 741                                 ~mask64)
 742                                 sw_stats->error_stats.statsb_drop_timeout++;
 743
 744                         if ((val64 &
 745                                 VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) &
 746                                 ~mask64)
 747                                 sw_stats->error_stats.target_illegal_access++;
 748
 749                         if (!skip_alarms) {
 750                                 writeq(VXGE_HW_INTR_MASK_ALL,
 751                                         &vp_reg->general_errors_reg);
 752                                 alarm_event = VXGE_HW_SET_LEVEL(
 753                                         VXGE_HW_EVENT_ALARM_CLEARED,
 754                                         alarm_event);
 755                         }
 756                 }
 757
 758                 if (pic_status &
 759                     VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) {
 760
 761                         val64 = readq(&vp_reg->kdfcctl_errors_reg);
 762                         mask64 = readq(&vp_reg->kdfcctl_errors_mask);
 763
 764                         if ((val64 &
 765                             VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) &
 766                                 ~mask64) {
 767                                 sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
 768
 769                                 alarm_event = VXGE_HW_SET_LEVEL(
 770                                         VXGE_HW_EVENT_FIFO_ERR,
 771                                         alarm_event);
 772                         }
 773
 774                         if ((val64 &
 775                             VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) &
 776                                 ~mask64) {
 777                                 sw_stats->error_stats.kdfcctl_fifo0_poison++;
 778
 779                                 alarm_event = VXGE_HW_SET_LEVEL(
 780                                         VXGE_HW_EVENT_FIFO_ERR,
 781                                         alarm_event);
 782                         }
 783
 784                         if ((val64 &
 785                             VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) &
 786                                 ~mask64) {
 787                                 sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
 788
 789                                 alarm_event = VXGE_HW_SET_LEVEL(
 790                                         VXGE_HW_EVENT_FIFO_ERR,
 791                                         alarm_event);
 792                         }
 793
 794                         if (!skip_alarms) {
 795                                 writeq(VXGE_HW_INTR_MASK_ALL,
 796                                         &vp_reg->kdfcctl_errors_reg);
 797                                 alarm_event = VXGE_HW_SET_LEVEL(
 798                                         VXGE_HW_EVENT_ALARM_CLEARED,
 799                                         alarm_event);
 800                         }
 801                 }
 802
 803         }
 804
 805         if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
 806
 807                 val64 = readq(&vp_reg->wrdma_alarm_status);
 808
 809                 if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
 810
 811                         val64 = readq(&vp_reg->prc_alarm_reg);
 812                         mask64 = readq(&vp_reg->prc_alarm_mask);
 813
 814                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)&
 815                                 ~mask64)
 816                                 sw_stats->error_stats.prc_ring_bumps++;
 817
 818                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) &
 819                                 ~mask64) {
 820                                 sw_stats->error_stats.prc_rxdcm_sc_err++;
 821
 822                                 alarm_event = VXGE_HW_SET_LEVEL(
 823                                         VXGE_HW_EVENT_VPATH_ERR,
 824                                         alarm_event);
 825                         }
 826
 827                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT)
 828                                 & ~mask64) {
 829                                 sw_stats->error_stats.prc_rxdcm_sc_abort++;
 830
 831                                 alarm_event = VXGE_HW_SET_LEVEL(
 832                                                 VXGE_HW_EVENT_VPATH_ERR,
 833                                                 alarm_event);
 834                         }
 835
 836                         if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR)
 837                                  & ~mask64) {
 838                                 sw_stats->error_stats.prc_quanta_size_err++;
 839
 840                                 alarm_event = VXGE_HW_SET_LEVEL(
 841                                         VXGE_HW_EVENT_VPATH_ERR,
 842                                         alarm_event);
 843                         }
 844
 845                         if (!skip_alarms) {
 846                                 writeq(VXGE_HW_INTR_MASK_ALL,
 847                                         &vp_reg->prc_alarm_reg);
 848                                 alarm_event = VXGE_HW_SET_LEVEL(
 849                                                 VXGE_HW_EVENT_ALARM_CLEARED,
 850                                                 alarm_event);
 851                         }
 852                 }
 853         }
 854 out:
 855         hldev->stats.sw_dev_err_stats.vpath_alarms++;
 856 out2:
 857         if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) ||
 858                 (alarm_event == VXGE_HW_EVENT_UNKNOWN))
 859                 return VXGE_HW_OK;
 860
 861         __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event);
 862
 863         if (alarm_event == VXGE_HW_EVENT_SERR)
 864                 return VXGE_HW_ERR_CRITICAL;
 865
 866         return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ?
 867                 VXGE_HW_ERR_SLOT_FREEZE :
 868                 (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO :
 869                 VXGE_HW_ERR_VPATH;
 870 }
 871
 872 /**
 873  * vxge_hw_device_begin_irq - Begin IRQ processing.
 874  * @hldev: HW device handle.
 875  * @skip_alarms: Do not clear the alarms
 876  * @reason: "Reason" for the interrupt, the value of Titan's
 877  *      general_int_status register.
 878  *
 879  * The function performs two actions, It first checks whether (shared IRQ) the
 880  * interrupt was raised by the device. Next, it masks the device interrupts.
 881  *
 882  * Note:
 883  * vxge_hw_device_begin_irq() does not flush MMIO writes through the
 884  * bridge. Therefore, two back-to-back interrupts are potentially possible.
 885  *
 886  * Returns: 0, if the interrupt is not "ours" (note that in this case the
 887  * device remain enabled).
 888  * Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter
 889  * status.
 890  */
 891 enum vxge_hw_status vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev,
 892                                              u32 skip_alarms, u64 *reason)
 893 {
 894         u32 i;
 895         u64 val64;
 896         u64 adapter_status;
 897         u64 vpath_mask;
 898         enum vxge_hw_status ret = VXGE_HW_OK;
 899
 900         val64 = readq(&hldev->common_reg->titan_general_int_status);
 901
 902         if (unlikely(!val64)) {
 903                 /* not Titan interrupt  */
 904                 *reason = 0;
 905                 ret = VXGE_HW_ERR_WRONG_IRQ;
 906                 goto exit;
 907         }
 908
 909         if (unlikely(val64 == VXGE_HW_ALL_FOXES)) {
 910
 911                 adapter_status = readq(&hldev->common_reg->adapter_status);
 912
 913                 if (adapter_status == VXGE_HW_ALL_FOXES) {
 914
 915                         __vxge_hw_device_handle_error(hldev,
 916                                 NULL_VPID, VXGE_HW_EVENT_SLOT_FREEZE);
 917                         *reason = 0;
 918                         ret = VXGE_HW_ERR_SLOT_FREEZE;
 919                         goto exit;
 920                 }
 921         }
 922
 923         hldev->stats.sw_dev_info_stats.total_intr_cnt++;
 924
 925         *reason = val64;
 926
 927         vpath_mask = hldev->vpaths_deployed >>
 928                                 (64 - VXGE_HW_MAX_VIRTUAL_PATHS);
 929
 930         if (val64 &
 931             VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(vpath_mask)) {
 932                 hldev->stats.sw_dev_info_stats.traffic_intr_cnt++;
 933
 934                 return VXGE_HW_OK;
 935         }
 936
 937         hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++;
 938
 939         if (unlikely(val64 &
 940                         VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) {
 941
 942                 enum vxge_hw_status error_level = VXGE_HW_OK;
 943
 944                 hldev->stats.sw_dev_err_stats.vpath_alarms++;
 945
 946                 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
 947
 948                         if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
 949                                 continue;
 950
 951                         ret = __vxge_hw_vpath_alarm_process(
 952                                 &hldev->virtual_paths[i], skip_alarms);
 953
 954                         error_level = VXGE_HW_SET_LEVEL(ret, error_level);
 955
 956                         if (unlikely((ret == VXGE_HW_ERR_CRITICAL) ||
 957                                 (ret == VXGE_HW_ERR_SLOT_FREEZE)))
 958                                 break;
 959                 }
 960
 961                 ret = error_level;
 962         }
 963 exit:
 964         return ret;
 965 }
 966
 967 /**
 968  * vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the
 969  * condition that has caused the Tx and RX interrupt.
 970  * @hldev: HW device.
 971  *
 972  * Acknowledge (that is, clear) the condition that has caused
 973  * the Tx and Rx interrupt.
 974  * See also: vxge_hw_device_begin_irq(),
 975  * vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx().
 976  */
 977 void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev)
 978 {
 979
 980         if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
 981            (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
 982                 writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
 983                                  hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]),
 984                                 &hldev->common_reg->tim_int_status0);
 985         }
 986
 987         if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
 988            (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
 989                 __vxge_hw_pio_mem_write32_upper(
 990                                 (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
 991                                  hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]),
 992                                 &hldev->common_reg->tim_int_status1);
 993         }
 994 }
 995
 996 /*
 997  * vxge_hw_channel_dtr_alloc - Allocate a dtr from the channel
 998  * @channel: Channel
 999  * @dtrh: Buffer to return the DTR pointer
1000  *
1001  * Allocates a dtr from the reserve array. If the reserve array is empty,
1002  * it swaps the reserve and free arrays.
1003  *
1004  */
1005 static enum vxge_hw_status
1006 vxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh)
1007 {
1008         if (channel->reserve_ptr - channel->reserve_top > 0) {
1009 _alloc_after_swap:
1010                 *dtrh = channel->reserve_arr[--channel->reserve_ptr];
1011
1012                 return VXGE_HW_OK;
1013         }
1014
1015         /* switch between empty and full arrays */
1016
1017         /* the idea behind such a design is that by having free and reserved
1018          * arrays separated we basically separated irq and non-irq parts.
1019          * i.e. no additional lock need to be done when we free a resource */
1020
1021         if (channel->length - channel->free_ptr > 0) {
1022                 swap(channel->reserve_arr, channel->free_arr);
1023                 channel->reserve_ptr = channel->length;
1024                 channel->reserve_top = channel->free_ptr;
1025                 channel->free_ptr = channel->length;
1026
1027                 channel->stats->reserve_free_swaps_cnt++;
1028
1029                 goto _alloc_after_swap;
1030         }
1031
1032         channel->stats->full_cnt++;
1033
1034         *dtrh = NULL;
1035         return VXGE_HW_INF_OUT_OF_DESCRIPTORS;
1036 }
1037
1038 /*
1039  * vxge_hw_channel_dtr_post - Post a dtr to the channel
1040  * @channelh: Channel
1041  * @dtrh: DTR pointer
1042  *
1043  * Posts a dtr to work array.
1044  *
1045  */
1046 static void
1047 vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh)
1048 {
1049         vxge_assert(channel->work_arr[channel->post_index] == NULL);
1050
1051         channel->work_arr[channel->post_index++] = dtrh;
1052
1053         /* wrap-around */
1054         if (channel->post_index == channel->length)
1055                 channel->post_index = 0;
1056 }
1057
1058 /*
1059  * vxge_hw_channel_dtr_try_complete - Returns next completed dtr
1060  * @channel: Channel
1061  * @dtr: Buffer to return the next completed DTR pointer
1062  *
1063  * Returns the next completed dtr with out removing it from work array
1064  *
1065  */
1066 void
1067 vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel, void **dtrh)
1068 {
1069         vxge_assert(channel->compl_index < channel->length);
1070
1071         *dtrh = channel->work_arr[channel->compl_index];
1072         prefetch(*dtrh);
1073 }
1074
1075 /*
1076  * vxge_hw_channel_dtr_complete - Removes next completed dtr from the work array
1077  * @channel: Channel handle
1078  *
1079  * Removes the next completed dtr from work array
1080  *
1081  */
1082 void vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel)
1083 {
1084         channel->work_arr[channel->compl_index] = NULL;
1085
1086         /* wrap-around */
1087         if (++channel->compl_index == channel->length)
1088                 channel->compl_index = 0;
1089
1090         channel->stats->total_compl_cnt++;
1091 }
1092
1093 /*
1094  * vxge_hw_channel_dtr_free - Frees a dtr
1095  * @channel: Channel handle
1096  * @dtr:  DTR pointer
1097  *
1098  * Returns the dtr to free array
1099  *
1100  */
1101 void vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh)
1102 {
1103         channel->free_arr[--channel->free_ptr] = dtrh;
1104 }
1105
1106 /*
1107  * vxge_hw_channel_dtr_count
1108  * @channel: Channel handle. Obtained via vxge_hw_channel_open().
1109  *
1110  * Retrieve number of DTRs available. This function can not be called
1111  * from data path. ring_initial_replenishi() is the only user.
1112  */
1113 int vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel)
1114 {
1115         return (channel->reserve_ptr - channel->reserve_top) +
1116                 (channel->length - channel->free_ptr);
1117 }
1118
1119 /**
1120  * vxge_hw_ring_rxd_reserve     - Reserve ring descriptor.
1121  * @ring: Handle to the ring object used for receive
1122  * @rxdh: Reserved descriptor. On success HW fills this "out" parameter
1123  * with a valid handle.
1124  *
1125  * Reserve Rx descriptor for the subsequent filling-in driver
1126  * and posting on the corresponding channel (@channelh)
1127  * via vxge_hw_ring_rxd_post().
1128  *
1129  * Returns: VXGE_HW_OK - success.
1130  * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available.
1131  *
1132  */
1133 enum vxge_hw_status vxge_hw_ring_rxd_reserve(struct __vxge_hw_ring *ring,
1134         void **rxdh)
1135 {
1136         enum vxge_hw_status status;
1137         struct __vxge_hw_channel *channel;
1138
1139         channel = &ring->channel;
1140
1141         status = vxge_hw_channel_dtr_alloc(channel, rxdh);
1142
1143         if (status == VXGE_HW_OK) {
1144                 struct vxge_hw_ring_rxd_1 *rxdp =
1145                         (struct vxge_hw_ring_rxd_1 *)*rxdh;
1146
1147                 rxdp->control_0 = rxdp->control_1 = 0;
1148         }
1149
1150         return status;
1151 }
1152
1153 /**
1154  * vxge_hw_ring_rxd_free - Free descriptor.
1155  * @ring: Handle to the ring object used for receive
1156  * @rxdh: Descriptor handle.
1157  *
1158  * Free the reserved descriptor. This operation is "symmetrical" to
1159  * vxge_hw_ring_rxd_reserve. The "free-ing" completes the descriptor's
1160  * lifecycle.
1161  *
1162  * After free-ing (see vxge_hw_ring_rxd_free()) the descriptor again can
1163  * be:
1164  *
1165  * - reserved (vxge_hw_ring_rxd_reserve);
1166  *
1167  * - posted     (vxge_hw_ring_rxd_post);
1168  *
1169  * - completed (vxge_hw_ring_rxd_next_completed);
1170  *
1171  * - and recycled again (vxge_hw_ring_rxd_free).
1172  *
1173  * For alternative state transitions and more details please refer to
1174  * the design doc.
1175  *
1176  */
1177 void vxge_hw_ring_rxd_free(struct __vxge_hw_ring *ring, void *rxdh)
1178 {
1179         struct __vxge_hw_channel *channel;
1180
1181         channel = &ring->channel;
1182
1183         vxge_hw_channel_dtr_free(channel, rxdh);
1184
1185 }
1186
1187 /**
1188  * vxge_hw_ring_rxd_pre_post - Prepare rxd and post
1189  * @ring: Handle to the ring object used for receive
1190  * @rxdh: Descriptor handle.
1191  *
1192  * This routine prepares a rxd and posts
1193  */
1194 void vxge_hw_ring_rxd_pre_post(struct __vxge_hw_ring *ring, void *rxdh)
1195 {
1196         struct __vxge_hw_channel *channel;
1197
1198         channel = &ring->channel;
1199
1200         vxge_hw_channel_dtr_post(channel, rxdh);
1201 }
1202
1203 /**
1204  * vxge_hw_ring_rxd_post_post - Process rxd after post.
1205  * @ring: Handle to the ring object used for receive
1206  * @rxdh: Descriptor handle.
1207  *
1208  * Processes rxd after post
1209  */
1210 void vxge_hw_ring_rxd_post_post(struct __vxge_hw_ring *ring, void *rxdh)
1211 {
1212         struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1213
1214         rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1215
1216         if (ring->stats->common_stats.usage_cnt > 0)
1217                 ring->stats->common_stats.usage_cnt--;
1218 }
1219
1220 /**
1221  * vxge_hw_ring_rxd_post - Post descriptor on the ring.
1222  * @ring: Handle to the ring object used for receive
1223  * @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve().
1224  *
1225  * Post descriptor on the ring.
1226  * Prior to posting the descriptor should be filled in accordance with
1227  * Host/Titan interface specification for a given service (LL, etc.).
1228  *
1229  */
1230 void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring, void *rxdh)
1231 {
1232         struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
1233         struct __vxge_hw_channel *channel;
1234
1235         channel = &ring->channel;
1236
1237         wmb();
1238         rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1239
1240         vxge_hw_channel_dtr_post(channel, rxdh);
1241
1242         if (ring->stats->common_stats.usage_cnt > 0)
1243                 ring->stats->common_stats.usage_cnt--;
1244 }
1245
1246 /**
1247  * vxge_hw_ring_rxd_post_post_wmb - Process rxd after post with memory barrier.
1248  * @ring: Handle to the ring object used for receive
1249  * @rxdh: Descriptor handle.
1250  *
1251  * Processes rxd after post with memory barrier.
1252  */
1253 void vxge_hw_ring_rxd_post_post_wmb(struct __vxge_hw_ring *ring, void *rxdh)
1254 {
1255         wmb();
1256         vxge_hw_ring_rxd_post_post(ring, rxdh);
1257 }
1258
1259 /**
1260  * vxge_hw_ring_rxd_next_completed - Get the _next_ completed descriptor.
1261  * @ring: Handle to the ring object used for receive
1262  * @rxdh: Descriptor handle. Returned by HW.
1263  * @t_code:     Transfer code, as per Titan User Guide,
1264  *       Receive Descriptor Format. Returned by HW.
1265  *
1266  * Retrieve the _next_ completed descriptor.
1267  * HW uses ring callback (*vxge_hw_ring_callback_f) to notifiy
1268  * driver of new completed descriptors. After that
1269  * the driver can use vxge_hw_ring_rxd_next_completed to retrieve the rest
1270  * completions (the very first completion is passed by HW via
1271  * vxge_hw_ring_callback_f).
1272  *
1273  * Implementation-wise, the driver is free to call
1274  * vxge_hw_ring_rxd_next_completed either immediately from inside the
1275  * ring callback, or in a deferred fashion and separate (from HW)
1276  * context.
1277  *
1278  * Non-zero @t_code means failure to fill-in receive buffer(s)
1279  * of the descriptor.
1280  * For instance, parity error detected during the data transfer.
1281  * In this case Titan will complete the descriptor and indicate
1282  * for the host that the received data is not to be used.
1283  * For details please refer to Titan User Guide.
1284  *
1285  * Returns: VXGE_HW_OK - success.
1286  * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
1287  * are currently available for processing.
1288  *
1289  * See also: vxge_hw_ring_callback_f{},
1290  * vxge_hw_fifo_rxd_next_completed(), enum vxge_hw_status{}.
1291  */
1292 enum vxge_hw_status vxge_hw_ring_rxd_next_completed(
1293         struct __vxge_hw_ring *ring, void **rxdh, u8 *t_code)
1294 {
1295         struct __vxge_hw_channel *channel;
1296         struct vxge_hw_ring_rxd_1 *rxdp;
1297         enum vxge_hw_status status = VXGE_HW_OK;
1298         u64 control_0, own;
1299
1300         channel = &ring->channel;
1301
1302         vxge_hw_channel_dtr_try_complete(channel, rxdh);
1303
1304         rxdp = *rxdh;
1305         if (rxdp == NULL) {
1306                 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1307                 goto exit;
1308         }
1309
1310         control_0 = rxdp->control_0;
1311         own = control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
1312         *t_code = (u8)VXGE_HW_RING_RXD_T_CODE_GET(control_0);
1313
1314         /* check whether it is not the end */
1315         if (!own || *t_code == VXGE_HW_RING_T_CODE_FRM_DROP) {
1316
1317                 vxge_assert((rxdp)->host_control !=
1318                                 0);
1319
1320                 ++ring->cmpl_cnt;
1321                 vxge_hw_channel_dtr_complete(channel);
1322
1323                 vxge_assert(*t_code != VXGE_HW_RING_RXD_T_CODE_UNUSED);
1324
1325                 ring->stats->common_stats.usage_cnt++;
1326                 if (ring->stats->common_stats.usage_max <
1327                                 ring->stats->common_stats.usage_cnt)
1328                         ring->stats->common_stats.usage_max =
1329                                 ring->stats->common_stats.usage_cnt;
1330
1331                 status = VXGE_HW_OK;
1332                 goto exit;
1333         }
1334
1335         /* reset it. since we don't want to return
1336          * garbage to the driver */
1337         *rxdh = NULL;
1338         status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1339 exit:
1340         return status;
1341 }
1342
1343 /**
1344  * vxge_hw_ring_handle_tcode - Handle transfer code.
1345  * @ring: Handle to the ring object used for receive
1346  * @rxdh: Descriptor handle.
1347  * @t_code: One of the enumerated (and documented in the Titan user guide)
1348  * "transfer codes".
1349  *
1350  * Handle descriptor's transfer code. The latter comes with each completed
1351  * descriptor.
1352  *
1353  * Returns: one of the enum vxge_hw_status{} enumerated types.
1354  * VXGE_HW_OK                   - for success.
1355  * VXGE_HW_ERR_CRITICAL         - when encounters critical error.
1356  */
1357 enum vxge_hw_status vxge_hw_ring_handle_tcode(
1358         struct __vxge_hw_ring *ring, void *rxdh, u8 t_code)
1359 {
1360         enum vxge_hw_status status = VXGE_HW_OK;
1361
1362         /* If the t_code is not supported and if the
1363          * t_code is other than 0x5 (unparseable packet
1364          * such as unknown UPV6 header), Drop it !!!
1365          */
1366
1367         if (t_code ==  VXGE_HW_RING_T_CODE_OK ||
1368                 t_code == VXGE_HW_RING_T_CODE_L3_PKT_ERR) {
1369                 status = VXGE_HW_OK;
1370                 goto exit;
1371         }
1372
1373         if (t_code > VXGE_HW_RING_T_CODE_MULTI_ERR) {
1374                 status = VXGE_HW_ERR_INVALID_TCODE;
1375                 goto exit;
1376         }
1377
1378         ring->stats->rxd_t_code_err_cnt[t_code]++;
1379 exit:
1380         return status;
1381 }
1382
1383 /**
1384  * __vxge_hw_non_offload_db_post - Post non offload doorbell
1385  *
1386  * @fifo: fifohandle
1387  * @txdl_ptr: The starting location of the TxDL in host memory
1388  * @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)
1389  * @no_snoop: No snoop flags
1390  *
1391  * This function posts a non-offload doorbell to doorbell FIFO
1392  *
1393  */
1394 static void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo,
1395         u64 txdl_ptr, u32 num_txds, u32 no_snoop)
1396 {
1397         writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) |
1398                 VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds) |
1399                 VXGE_HW_NODBW_GET_NO_SNOOP(no_snoop),
1400                 &fifo->nofl_db->control_0);
1401
1402         mmiowb();
1403
1404         writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr);
1405
1406         mmiowb();
1407 }
1408
1409 /**
1410  * vxge_hw_fifo_free_txdl_count_get - returns the number of txdls available in
1411  * the fifo
1412  * @fifoh: Handle to the fifo object used for non offload send
1413  */
1414 u32 vxge_hw_fifo_free_txdl_count_get(struct __vxge_hw_fifo *fifoh)
1415 {
1416         return vxge_hw_channel_dtr_count(&fifoh->channel);
1417 }
1418
1419 /**
1420  * vxge_hw_fifo_txdl_reserve - Reserve fifo descriptor.
1421  * @fifoh: Handle to the fifo object used for non offload send
1422  * @txdlh: Reserved descriptor. On success HW fills this "out" parameter
1423  *        with a valid handle.
1424  * @txdl_priv: Buffer to return the pointer to per txdl space
1425  *
1426  * Reserve a single TxDL (that is, fifo descriptor)
1427  * for the subsequent filling-in by driver)
1428  * and posting on the corresponding channel (@channelh)
1429  * via vxge_hw_fifo_txdl_post().
1430  *
1431  * Note: it is the responsibility of driver to reserve multiple descriptors
1432  * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor
1433  * carries up to configured number (fifo.max_frags) of contiguous buffers.
1434  *
1435  * Returns: VXGE_HW_OK - success;
1436  * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
1437  *
1438  */
1439 enum vxge_hw_status vxge_hw_fifo_txdl_reserve(
1440         struct __vxge_hw_fifo *fifo,
1441         void **txdlh, void **txdl_priv)
1442 {
1443         struct __vxge_hw_channel *channel;
1444         enum vxge_hw_status status;
1445         int i;
1446
1447         channel = &fifo->channel;
1448
1449         status = vxge_hw_channel_dtr_alloc(channel, txdlh);
1450
1451         if (status == VXGE_HW_OK) {
1452                 struct vxge_hw_fifo_txd *txdp =
1453                         (struct vxge_hw_fifo_txd *)*txdlh;
1454                 struct __vxge_hw_fifo_txdl_priv *priv;
1455
1456                 priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
1457
1458                 /* reset the TxDL's private */
1459                 priv->align_dma_offset = 0;
1460                 priv->align_vaddr_start = priv->align_vaddr;
1461                 priv->align_used_frags = 0;
1462                 priv->frags = 0;
1463                 priv->alloc_frags = fifo->config->max_frags;
1464                 priv->next_txdl_priv = NULL;
1465
1466                 *txdl_priv = (void *)(size_t)txdp->host_control;
1467
1468                 for (i = 0; i < fifo->config->max_frags; i++) {
1469                         txdp = ((struct vxge_hw_fifo_txd *)*txdlh) + i;
1470                         txdp->control_0 = txdp->control_1 = 0;
1471                 }
1472         }
1473
1474         return status;
1475 }
1476
1477 /**
1478  * vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the
1479  * descriptor.
1480  * @fifo: Handle to the fifo object used for non offload send
1481  * @txdlh: Descriptor handle.
1482  * @frag_idx: Index of the data buffer in the caller's scatter-gather list
1483  *            (of buffers).
1484  * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
1485  * @size: Size of the data buffer (in bytes).
1486  *
1487  * This API is part of the preparation of the transmit descriptor for posting
1488  * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
1489  * vxge_hw_fifo_txdl_mss_set() and vxge_hw_fifo_txdl_cksum_set_bits().
1490  * All three APIs fill in the fields of the fifo descriptor,
1491  * in accordance with the Titan specification.
1492  *
1493  */
1494 void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo,
1495                                   void *txdlh, u32 frag_idx,
1496                                   dma_addr_t dma_pointer, u32 size)
1497 {
1498         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
1499         struct vxge_hw_fifo_txd *txdp, *txdp_last;
1500
1501         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
1502         txdp = (struct vxge_hw_fifo_txd *)txdlh  +  txdl_priv->frags;
1503
1504         if (frag_idx != 0)
1505                 txdp->control_0 = txdp->control_1 = 0;
1506         else {
1507                 txdp->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
1508                         VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST);
1509                 txdp->control_1 |= fifo->interrupt_type;
1510                 txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_NUMBER(
1511                         fifo->tx_intr_num);
1512                 if (txdl_priv->frags) {
1513                         txdp_last = (struct vxge_hw_fifo_txd *)txdlh  +
1514                         (txdl_priv->frags - 1);
1515                         txdp_last->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
1516                                 VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
1517                 }
1518         }
1519
1520         vxge_assert(frag_idx < txdl_priv->alloc_frags);
1521
1522         txdp->buffer_pointer = (u64)dma_pointer;
1523         txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(size);
1524         fifo->stats->total_buffers++;
1525         txdl_priv->frags++;
1526 }
1527
1528 /**
1529  * vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
1530  * @fifo: Handle to the fifo object used for non offload send
1531  * @txdlh: Descriptor obtained via vxge_hw_fifo_txdl_reserve()
1532  * @frags: Number of contiguous buffers that are part of a single
1533  *         transmit operation.
1534  *
1535  * Post descriptor on the 'fifo' type channel for transmission.
1536  * Prior to posting the descriptor should be filled in accordance with
1537  * Host/Titan interface specification for a given service (LL, etc.).
1538  *
1539  */
1540 void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo, void *txdlh)
1541 {
1542         struct __vxge_hw_fifo_txdl_priv *txdl_priv;
1543         struct vxge_hw_fifo_txd *txdp_last;
1544         struct vxge_hw_fifo_txd *txdp_first;
1545
1546         txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
1547         txdp_first = txdlh;
1548
1549         txdp_last = (struct vxge_hw_fifo_txd *)txdlh  +  (txdl_priv->frags - 1);
1550         txdp_last->control_0 |=
1551               VXGE_HW_FIFO_TXD_GATHER_CODE(VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
1552         txdp_first->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER;
1553
1554         vxge_hw_channel_dtr_post(&fifo->channel, txdlh);
1555
1556         __vxge_hw_non_offload_db_post(fifo,
1557                 (u64)txdl_priv->dma_addr,
1558                 txdl_priv->frags - 1,
1559                 fifo->no_snoop_bits);
1560
1561         fifo->stats->total_posts++;
1562         fifo->stats->common_stats.usage_cnt++;
1563         if (fifo->stats->common_stats.usage_max <
1564                 fifo->stats->common_stats.usage_cnt)
1565                 fifo->stats->common_stats.usage_max =
1566                         fifo->stats->common_stats.usage_cnt;
1567 }
1568
1569 /**
1570  * vxge_hw_fifo_txdl_next_completed - Retrieve next completed descriptor.
1571  * @fifo: Handle to the fifo object used for non offload send
1572  * @txdlh: Descriptor handle. Returned by HW.
1573  * @t_code: Transfer code, as per Titan User Guide,
1574  *          Transmit Descriptor Format.
1575  *          Returned by HW.
1576  *
1577  * Retrieve the _next_ completed descriptor.
1578  * HW uses channel callback (*vxge_hw_channel_callback_f) to notifiy
1579  * driver of new completed descriptors. After that
1580  * the driver can use vxge_hw_fifo_txdl_next_completed to retrieve the rest
1581  * completions (the very first completion is passed by HW via
1582  * vxge_hw_channel_callback_f).
1583  *
1584  * Implementation-wise, the driver is free to call
1585  * vxge_hw_fifo_txdl_next_completed either immediately from inside the
1586  * channel callback, or in a deferred fashion and separate (from HW)
1587  * context.
1588  *
1589  * Non-zero @t_code means failure to process the descriptor.
1590  * The failure could happen, for instance, when the link is
1591  * down, in which case Titan completes the descriptor because it
1592  * is not able to send the data out.
1593  *
1594  * For details please refer to Titan User Guide.
1595  *
1596  * Returns: VXGE_HW_OK - success.
1597  * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
1598  * are currently available for processing.
1599  *
1600  */
1601 enum vxge_hw_status vxge_hw_fifo_txdl_next_completed(
1602         struct __vxge_hw_fifo *fifo, void **txdlh,
1603         enum vxge_hw_fifo_tcode *t_code)
1604 {
1605         struct __vxge_hw_channel *channel;
1606         struct vxge_hw_fifo_txd *txdp;
1607         enum vxge_hw_status status = VXGE_HW_OK;
1608
1609         channel = &fifo->channel;
1610
1611         vxge_hw_channel_dtr_try_complete(channel, txdlh);
1612
1613         txdp = *txdlh;
1614         if (txdp == NULL) {
1615                 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1616                 goto exit;
1617         }
1618
1619         /* check whether host owns it */
1620         if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)) {
1621
1622                 vxge_assert(txdp->host_control != 0);
1623
1624                 vxge_hw_channel_dtr_complete(channel);
1625
1626                 *t_code = (u8)VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0);
1627
1628                 if (fifo->stats->common_stats.usage_cnt > 0)
1629                         fifo->stats->common_stats.usage_cnt--;
1630
1631                 status = VXGE_HW_OK;
1632                 goto exit;
1633         }
1634
1635         /* no more completions */
1636         *txdlh = NULL;
1637         status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
1638 exit:
1639         return status;
1640 }
1641
1642 /**
1643  * vxge_hw_fifo_handle_tcode - Handle transfer code.
1644  * @fifo: Handle to the fifo object used for non offload send
1645  * @txdlh: Descriptor handle.
1646  * @t_code: One of the enumerated (and documented in the Titan user guide)
1647  *          "transfer codes".
1648  *
1649  * Handle descriptor's transfer code. The latter comes with each completed
1650  * descriptor.
1651  *
1652  * Returns: one of the enum vxge_hw_status{} enumerated types.
1653  * VXGE_HW_OK - for success.
1654  * VXGE_HW_ERR_CRITICAL - when encounters critical error.
1655  */
1656 enum vxge_hw_status vxge_hw_fifo_handle_tcode(struct __vxge_hw_fifo *fifo,
1657                                               void *txdlh,
1658                                               enum vxge_hw_fifo_tcode t_code)
1659 {
1660         enum vxge_hw_status status = VXGE_HW_OK;
1661
1662         if (((t_code & 0x7) < 0) || ((t_code & 0x7) > 0x4)) {
1663                 status = VXGE_HW_ERR_INVALID_TCODE;
1664                 goto exit;
1665         }
1666
1667         fifo->stats->txd_t_code_err_cnt[t_code]++;
1668 exit:
1669         return status;
1670 }
1671
1672 /**
1673  * vxge_hw_fifo_txdl_free - Free descriptor.
1674  * @fifo: Handle to the fifo object used for non offload send
1675  * @txdlh: Descriptor handle.
1676  *
1677  * Free the reserved descriptor. This operation is "symmetrical" to
1678  * vxge_hw_fifo_txdl_reserve. The "free-ing" completes the descriptor's
1679  * lifecycle.
1680  *
1681  * After free-ing (see vxge_hw_fifo_txdl_free()) the descriptor again can
1682  * be:
1683  *
1684  * - reserved (vxge_hw_fifo_txdl_reserve);
1685  *
1686  * - posted (vxge_hw_fifo_txdl_post);
1687  *
1688  * - completed (vxge_hw_fifo_txdl_next_completed);
1689  *
1690  * - and recycled again (vxge_hw_fifo_txdl_free).
1691  *
1692  * For alternative state transitions and more details please refer to
1693  * the design doc.
1694  *
1695  */
1696 void vxge_hw_fifo_txdl_free(struct __vxge_hw_fifo *fifo, void *txdlh)
1697 {
1698         struct __vxge_hw_channel *channel;
1699
1700         channel = &fifo->channel;
1701
1702         vxge_hw_channel_dtr_free(channel, txdlh);
1703 }
1704
1705 /**
1706  * vxge_hw_vpath_mac_addr_add - Add the mac address entry for this vpath
1707  *               to MAC address table.
1708  * @vp: Vpath handle.
1709  * @macaddr: MAC address to be added for this vpath into the list
1710  * @macaddr_mask: MAC address mask for macaddr
1711  * @duplicate_mode: Duplicate MAC address add mode. Please see
1712  *             enum vxge_hw_vpath_mac_addr_add_mode{}
1713  *
1714  * Adds the given mac address and mac address mask into the list for this
1715  * vpath.
1716  * see also: vxge_hw_vpath_mac_addr_delete, vxge_hw_vpath_mac_addr_get and
1717  * vxge_hw_vpath_mac_addr_get_next
1718  *
1719  */
1720 enum vxge_hw_status
1721 vxge_hw_vpath_mac_addr_add(
1722         struct __vxge_hw_vpath_handle *vp,
1723         u8 (macaddr)[ETH_ALEN],
1724         u8 (macaddr_mask)[ETH_ALEN],
1725         enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode)
1726 {
1727         u32 i;
1728         u64 data1 = 0ULL;
1729         u64 data2 = 0ULL;
1730         enum vxge_hw_status status = VXGE_HW_OK;
1731
1732         if (vp == NULL) {
1733                 status = VXGE_HW_ERR_INVALID_HANDLE;
1734                 goto exit;
1735         }
1736
1737         for (i = 0; i < ETH_ALEN; i++) {
1738                 data1 <<= 8;
1739                 data1 |= (u8)macaddr[i];
1740
1741                 data2 <<= 8;
1742                 data2 |= (u8)macaddr_mask[i];
1743         }
1744
1745         switch (duplicate_mode) {
1746         case VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE:
1747                 i = 0;
1748                 break;
1749         case VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE:
1750                 i = 1;
1751                 break;
1752         case VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE:
1753                 i = 2;
1754                 break;
1755         default:
1756                 i = 0;
1757                 break;
1758         }
1759
1760         status = __vxge_hw_vpath_rts_table_set(vp,
1761                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
1762                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1763                         0,
1764                         VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1765                         VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2)|
1766                         VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i));
1767 exit:
1768         return status;
1769 }
1770
1771 /**
1772  * vxge_hw_vpath_mac_addr_get - Get the first mac address entry for this vpath
1773  *               from MAC address table.
1774  * @vp: Vpath handle.
1775  * @macaddr: First MAC address entry for this vpath in the list
1776  * @macaddr_mask: MAC address mask for macaddr
1777  *
1778  * Returns the first mac address and mac address mask in the list for this
1779  * vpath.
1780  * see also: vxge_hw_vpath_mac_addr_get_next
1781  *
1782  */
1783 enum vxge_hw_status
1784 vxge_hw_vpath_mac_addr_get(
1785         struct __vxge_hw_vpath_handle *vp,
1786         u8 (macaddr)[ETH_ALEN],
1787         u8 (macaddr_mask)[ETH_ALEN])
1788 {
1789         u32 i;
1790         u64 data1 = 0ULL;
1791         u64 data2 = 0ULL;
1792         enum vxge_hw_status status = VXGE_HW_OK;
1793
1794         if (vp == NULL) {
1795                 status = VXGE_HW_ERR_INVALID_HANDLE;
1796                 goto exit;
1797         }
1798
1799         status = __vxge_hw_vpath_rts_table_get(vp,
1800                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
1801                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1802                         0, &data1, &data2);
1803
1804         if (status != VXGE_HW_OK)
1805                 goto exit;
1806
1807         data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1808
1809         data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1810
1811         for (i = ETH_ALEN; i > 0; i--) {
1812                 macaddr[i-1] = (u8)(data1 & 0xFF);
1813                 data1 >>= 8;
1814
1815                 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
1816                 data2 >>= 8;
1817         }
1818 exit:
1819         return status;
1820 }
1821
1822 /**
1823  * vxge_hw_vpath_mac_addr_get_next - Get the next mac address entry for this
1824  * vpath
1825  *               from MAC address table.
1826  * @vp: Vpath handle.
1827  * @macaddr: Next MAC address entry for this vpath in the list
1828  * @macaddr_mask: MAC address mask for macaddr
1829  *
1830  * Returns the next mac address and mac address mask in the list for this
1831  * vpath.
1832  * see also: vxge_hw_vpath_mac_addr_get
1833  *
1834  */
1835 enum vxge_hw_status
1836 vxge_hw_vpath_mac_addr_get_next(
1837         struct __vxge_hw_vpath_handle *vp,
1838         u8 (macaddr)[ETH_ALEN],
1839         u8 (macaddr_mask)[ETH_ALEN])
1840 {
1841         u32 i;
1842         u64 data1 = 0ULL;
1843         u64 data2 = 0ULL;
1844         enum vxge_hw_status status = VXGE_HW_OK;
1845
1846         if (vp == NULL) {
1847                 status = VXGE_HW_ERR_INVALID_HANDLE;
1848                 goto exit;
1849         }
1850
1851         status = __vxge_hw_vpath_rts_table_get(vp,
1852                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
1853                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1854                         0, &data1, &data2);
1855
1856         if (status != VXGE_HW_OK)
1857                 goto exit;
1858
1859         data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
1860
1861         data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
1862
1863         for (i = ETH_ALEN; i > 0; i--) {
1864                 macaddr[i-1] = (u8)(data1 & 0xFF);
1865                 data1 >>= 8;
1866
1867                 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
1868                 data2 >>= 8;
1869         }
1870
1871 exit:
1872         return status;
1873 }
1874
1875 /**
1876  * vxge_hw_vpath_mac_addr_delete - Delete the mac address entry for this vpath
1877  *               to MAC address table.
1878  * @vp: Vpath handle.
1879  * @macaddr: MAC address to be added for this vpath into the list
1880  * @macaddr_mask: MAC address mask for macaddr
1881  *
1882  * Delete the given mac address and mac address mask into the list for this
1883  * vpath.
1884  * see also: vxge_hw_vpath_mac_addr_add, vxge_hw_vpath_mac_addr_get and
1885  * vxge_hw_vpath_mac_addr_get_next
1886  *
1887  */
1888 enum vxge_hw_status
1889 vxge_hw_vpath_mac_addr_delete(
1890         struct __vxge_hw_vpath_handle *vp,
1891         u8 (macaddr)[ETH_ALEN],
1892         u8 (macaddr_mask)[ETH_ALEN])
1893 {
1894         u32 i;
1895         u64 data1 = 0ULL;
1896         u64 data2 = 0ULL;
1897         enum vxge_hw_status status = VXGE_HW_OK;
1898
1899         if (vp == NULL) {
1900                 status = VXGE_HW_ERR_INVALID_HANDLE;
1901                 goto exit;
1902         }
1903
1904         for (i = 0; i < ETH_ALEN; i++) {
1905                 data1 <<= 8;
1906                 data1 |= (u8)macaddr[i];
1907
1908                 data2 <<= 8;
1909                 data2 |= (u8)macaddr_mask[i];
1910         }
1911
1912         status = __vxge_hw_vpath_rts_table_set(vp,
1913                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
1914                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1915                         0,
1916                         VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
1917                         VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2));
1918 exit:
1919         return status;
1920 }
1921
1922 /**
1923  * vxge_hw_vpath_vid_add - Add the vlan id entry for this vpath
1924  *               to vlan id table.
1925  * @vp: Vpath handle.
1926  * @vid: vlan id to be added for this vpath into the list
1927  *
1928  * Adds the given vlan id into the list for this  vpath.
1929  * see also: vxge_hw_vpath_vid_delete
1930  *
1931  */
1932 enum vxge_hw_status
1933 vxge_hw_vpath_vid_add(struct __vxge_hw_vpath_handle *vp, u64 vid)
1934 {
1935         enum vxge_hw_status status = VXGE_HW_OK;
1936
1937         if (vp == NULL) {
1938                 status = VXGE_HW_ERR_INVALID_HANDLE;
1939                 goto exit;
1940         }
1941
1942         status = __vxge_hw_vpath_rts_table_set(vp,
1943                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
1944                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
1945                         0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
1946 exit:
1947         return status;
1948 }
1949
1950 /**
1951  * vxge_hw_vpath_vid_delete - Delete the vlan id entry for this vpath
1952  *               to vlan id table.
1953  * @vp: Vpath handle.
1954  * @vid: vlan id to be added for this vpath into the list
1955  *
1956  * Adds the given vlan id into the list for this  vpath.
1957  * see also: vxge_hw_vpath_vid_add
1958  *
1959  */
1960 enum vxge_hw_status
1961 vxge_hw_vpath_vid_delete(struct __vxge_hw_vpath_handle *vp, u64 vid)
1962 {
1963         enum vxge_hw_status status = VXGE_HW_OK;
1964
1965         if (vp == NULL) {
1966                 status = VXGE_HW_ERR_INVALID_HANDLE;
1967                 goto exit;
1968         }
1969
1970         status = __vxge_hw_vpath_rts_table_set(vp,
1971                         VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
1972                         VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
1973                         0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
1974 exit:
1975         return status;
1976 }
1977
1978 /**
1979  * vxge_hw_vpath_promisc_enable - Enable promiscuous mode.
1980  * @vp: Vpath handle.
1981  *
1982  * Enable promiscuous mode of Titan-e operation.
1983  *
1984  * See also: vxge_hw_vpath_promisc_disable().
1985  */
1986 enum vxge_hw_status vxge_hw_vpath_promisc_enable(
1987                         struct __vxge_hw_vpath_handle *vp)
1988 {
1989         u64 val64;
1990         struct __vxge_hw_virtualpath *vpath;
1991         enum vxge_hw_status status = VXGE_HW_OK;
1992
1993         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
1994                 status = VXGE_HW_ERR_INVALID_HANDLE;
1995                 goto exit;
1996         }
1997
1998         vpath = vp->vpath;
1999
2000         /* Enable promiscuous mode for function 0 only */
2001         if (!(vpath->hldev->access_rights &
2002                 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM))
2003                 return VXGE_HW_OK;
2004
2005         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2006
2007         if (!(val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN)) {
2008
2009                 val64 |= VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
2010                          VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
2011                          VXGE_HW_RXMAC_VCFG0_BCAST_EN |
2012                          VXGE_HW_RXMAC_VCFG0_ALL_VID_EN;
2013
2014                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2015         }
2016 exit:
2017         return status;
2018 }
2019
2020 /**
2021  * vxge_hw_vpath_promisc_disable - Disable promiscuous mode.
2022  * @vp: Vpath handle.
2023  *
2024  * Disable promiscuous mode of Titan-e operation.
2025  *
2026  * See also: vxge_hw_vpath_promisc_enable().
2027  */
2028 enum vxge_hw_status vxge_hw_vpath_promisc_disable(
2029                         struct __vxge_hw_vpath_handle *vp)
2030 {
2031         u64 val64;
2032         struct __vxge_hw_virtualpath *vpath;
2033         enum vxge_hw_status status = VXGE_HW_OK;
2034
2035         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2036                 status = VXGE_HW_ERR_INVALID_HANDLE;
2037                 goto exit;
2038         }
2039
2040         vpath = vp->vpath;
2041
2042         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2043
2044         if (val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) {
2045
2046                 val64 &= ~(VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
2047                            VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
2048                            VXGE_HW_RXMAC_VCFG0_ALL_VID_EN);
2049
2050                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2051         }
2052 exit:
2053         return status;
2054 }
2055
2056 /*
2057  * vxge_hw_vpath_bcast_enable - Enable broadcast
2058  * @vp: Vpath handle.
2059  *
2060  * Enable receiving broadcasts.
2061  */
2062 enum vxge_hw_status vxge_hw_vpath_bcast_enable(
2063                         struct __vxge_hw_vpath_handle *vp)
2064 {
2065         u64 val64;
2066         struct __vxge_hw_virtualpath *vpath;
2067         enum vxge_hw_status status = VXGE_HW_OK;
2068
2069         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2070                 status = VXGE_HW_ERR_INVALID_HANDLE;
2071                 goto exit;
2072         }
2073
2074         vpath = vp->vpath;
2075
2076         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2077
2078         if (!(val64 & VXGE_HW_RXMAC_VCFG0_BCAST_EN)) {
2079                 val64 |= VXGE_HW_RXMAC_VCFG0_BCAST_EN;
2080                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2081         }
2082 exit:
2083         return status;
2084 }
2085
2086 /**
2087  * vxge_hw_vpath_mcast_enable - Enable multicast addresses.
2088  * @vp: Vpath handle.
2089  *
2090  * Enable Titan-e multicast addresses.
2091  * Returns: VXGE_HW_OK on success.
2092  *
2093  */
2094 enum vxge_hw_status vxge_hw_vpath_mcast_enable(
2095                         struct __vxge_hw_vpath_handle *vp)
2096 {
2097         u64 val64;
2098         struct __vxge_hw_virtualpath *vpath;
2099         enum vxge_hw_status status = VXGE_HW_OK;
2100
2101         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2102                 status = VXGE_HW_ERR_INVALID_HANDLE;
2103                 goto exit;
2104         }
2105
2106         vpath = vp->vpath;
2107
2108         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2109
2110         if (!(val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN)) {
2111                 val64 |= VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
2112                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2113         }
2114 exit:
2115         return status;
2116 }
2117
2118 /**
2119  * vxge_hw_vpath_mcast_disable - Disable  multicast addresses.
2120  * @vp: Vpath handle.
2121  *
2122  * Disable Titan-e multicast addresses.
2123  * Returns: VXGE_HW_OK - success.
2124  * VXGE_HW_ERR_INVALID_HANDLE - Invalid handle
2125  *
2126  */
2127 enum vxge_hw_status
2128 vxge_hw_vpath_mcast_disable(struct __vxge_hw_vpath_handle *vp)
2129 {
2130         u64 val64;
2131         struct __vxge_hw_virtualpath *vpath;
2132         enum vxge_hw_status status = VXGE_HW_OK;
2133
2134         if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
2135                 status = VXGE_HW_ERR_INVALID_HANDLE;
2136                 goto exit;
2137         }
2138
2139         vpath = vp->vpath;
2140
2141         val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
2142
2143         if (val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) {
2144                 val64 &= ~VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
2145                 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
2146         }
2147 exit:
2148         return status;
2149 }
2150
2151 /*
2152  * vxge_hw_vpath_alarm_process - Process Alarms.
2153  * @vpath: Virtual Path.
2154  * @skip_alarms: Do not clear the alarms
2155  *
2156  * Process vpath alarms.
2157  *
2158  */
2159 enum vxge_hw_status vxge_hw_vpath_alarm_process(
2160                         struct __vxge_hw_vpath_handle *vp,
2161                         u32 skip_alarms)
2162 {
2163         enum vxge_hw_status status = VXGE_HW_OK;
2164
2165         if (vp == NULL) {
2166                 status = VXGE_HW_ERR_INVALID_HANDLE;
2167                 goto exit;
2168         }
2169
2170         status = __vxge_hw_vpath_alarm_process(vp->vpath, skip_alarms);
2171 exit:
2172         return status;
2173 }
2174
2175 /**
2176  * vxge_hw_vpath_msix_set - Associate MSIX vectors with TIM interrupts and
2177  *                            alrms
2178  * @vp: Virtual Path handle.
2179  * @tim_msix_id: MSIX vectors associated with VXGE_HW_MAX_INTR_PER_VP number of
2180  *             interrupts(Can be repeated). If fifo or ring are not enabled
2181  *             the MSIX vector for that should be set to 0
2182  * @alarm_msix_id: MSIX vector for alarm.
2183  *
2184  * This API will associate a given MSIX vector numbers with the four TIM
2185  * interrupts and alarm interrupt.
2186  */
2187 void
2188 vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
2189                        int alarm_msix_id)
2190 {
2191         u64 val64;
2192         struct __vxge_hw_virtualpath *vpath = vp->vpath;
2193         struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
2194         u32 vp_id = vp->vpath->vp_id;
2195
2196         val64 =  VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
2197                   (vp_id * 4) + tim_msix_id[0]) |
2198                  VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
2199                   (vp_id * 4) + tim_msix_id[1]);
2200
2201         writeq(val64, &vp_reg->interrupt_cfg0);
2202
2203         writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
2204                         (vpath->hldev->first_vp_id * 4) + alarm_msix_id),
2205                         &vp_reg->interrupt_cfg2);
2206
2207         if (vpath->hldev->config.intr_mode ==
2208                                         VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
2209                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2210                                 VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN,
2211                                 0, 32), &vp_reg->one_shot_vect0_en);
2212                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2213                                 VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN,
2214                                 0, 32), &vp_reg->one_shot_vect1_en);
2215                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
2216                                 VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN,
2217                                 0, 32), &vp_reg->one_shot_vect2_en);
2218         }
2219 }
2220
2221 /**
2222  * vxge_hw_vpath_msix_mask - Mask MSIX Vector.
2223  * @vp: Virtual Path handle.
2224  * @msix_id:  MSIX ID
2225  *
2226  * The function masks the msix interrupt for the given msix_id
2227  *
2228  * Returns: 0,
2229  * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2230  * status.
2231  * See also:
2232  */
2233 void
2234 vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2235 {
2236         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2237         __vxge_hw_pio_mem_write32_upper(
2238                 (u32) vxge_bVALn(vxge_mBIT(msix_id  >> 2), 0, 32),
2239                 &hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
2240 }
2241
2242 /**
2243  * vxge_hw_vpath_msix_clear - Clear MSIX Vector.
2244  * @vp: Virtual Path handle.
2245  * @msix_id:  MSI ID
2246  *
2247  * The function clears the msix interrupt for the given msix_id
2248  *
2249  * Returns: 0,
2250  * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2251  * status.
2252  * See also:
2253  */
2254 void vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
2255 {
2256         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2257
2258         if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_MSIX_ONE_SHOT)
2259                 __vxge_hw_pio_mem_write32_upper(
2260                         (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2261                         &hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
2262         else
2263                 __vxge_hw_pio_mem_write32_upper(
2264                         (u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
2265                         &hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);
2266 }
2267
2268 /**
2269  * vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector.
2270  * @vp: Virtual Path handle.
2271  * @msix_id:  MSI ID
2272  *
2273  * The function unmasks the msix interrupt for the given msix_id
2274  *
2275  * Returns: 0,
2276  * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
2277  * status.
2278  * See also:
2279  */
2280 void
2281 vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id)
2282 {
2283         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2284         __vxge_hw_pio_mem_write32_upper(
2285                         (u32)vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
2286                         &hldev->common_reg->clear_msix_mask_vect[msix_id%4]);
2287 }
2288
2289 /**
2290  * vxge_hw_vpath_inta_mask_tx_rx - Mask Tx and Rx interrupts.
2291  * @vp: Virtual Path handle.
2292  *
2293  * Mask Tx and Rx vpath interrupts.
2294  *
2295  * See also: vxge_hw_vpath_inta_mask_tx_rx()
2296  */
2297 void vxge_hw_vpath_inta_mask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2298 {
2299         u64     tim_int_mask0[4] = {[0 ...3] = 0};
2300         u32     tim_int_mask1[4] = {[0 ...3] = 0};
2301         u64     val64;
2302         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2303
2304         VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2305                 tim_int_mask1, vp->vpath->vp_id);
2306
2307         val64 = readq(&hldev->common_reg->tim_int_mask0);
2308
2309         if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2310                 (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2311                 writeq((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2312                         tim_int_mask0[VXGE_HW_VPATH_INTR_RX] | val64),
2313                         &hldev->common_reg->tim_int_mask0);
2314         }
2315
2316         val64 = readl(&hldev->common_reg->tim_int_mask1);
2317
2318         if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
2319                 (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
2320                 __vxge_hw_pio_mem_write32_upper(
2321                         (tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
2322                         tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64),
2323                         &hldev->common_reg->tim_int_mask1);
2324         }
2325 }
2326
2327 /**
2328  * vxge_hw_vpath_inta_unmask_tx_rx - Unmask Tx and Rx interrupts.
2329  * @vp: Virtual Path handle.
2330  *
2331  * Unmask Tx and Rx vpath interrupts.
2332  *
2333  * See also: vxge_hw_vpath_inta_mask_tx_rx()
2334  */
2335 void vxge_hw_vpath_inta_unmask_tx_rx(struct __vxge_hw_vpath_handle *vp)
2336 {
2337         u64     tim_int_mask0[4] = {[0 ...3] = 0};
2338         u32     tim_int_mask1[4] = {[0 ...3] = 0};
2339         u64     val64;
2340         struct __vxge_hw_device *hldev = vp->vpath->hldev;
2341
2342         VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
2343                 tim_int_mask1, vp->vpath->vp_id);
2344
2345         val64 = readq(&hldev->common_reg->tim_int_mask0);
2346
2347         if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
2348            (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
2349                 writeq((~(tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
2350                         tim_int_mask0[VXGE_HW_VPATH_INTR_RX])) & val64,
2351                         &hldev->common_reg->tim_int_mask0);
2352         }
2353
2354         if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
2355            (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
2356                 __vxge_hw_pio_mem_write32_upper(
2357                         (~(tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
2358                           tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64,
2359                         &hldev->common_reg->tim_int_mask1);
2360         }
2361 }
2362
2363 /**
2364  * vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed
2365  * descriptors and process the same.
2366  * @ring: Handle to the ring object used for receive
2367  *
2368  * The function polls the Rx for the completed  descriptors and calls
2369  * the driver via supplied completion   callback.
2370  *
2371  * Returns: VXGE_HW_OK, if the polling is completed successful.
2372  * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
2373  * descriptors available which are yet to be processed.
2374  *
2375  * See also: vxge_hw_vpath_poll_rx()
2376  */
2377 enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ring)
2378 {
2379         u8 t_code;
2380         enum vxge_hw_status status = VXGE_HW_OK;
2381         void *first_rxdh;
2382         u64 val64 = 0;
2383         int new_count = 0;
2384
2385         ring->cmpl_cnt = 0;
2386
2387         status = vxge_hw_ring_rxd_next_completed(ring, &first_rxdh, &t_code);
2388         if (status == VXGE_HW_OK)
2389                 ring->callback(ring, first_rxdh,
2390                         t_code, ring->channel.userdata);
2391
2392         if (ring->cmpl_cnt != 0) {
2393                 ring->doorbell_cnt += ring->cmpl_cnt;
2394                 if (ring->doorbell_cnt >= ring->rxds_limit) {
2395                         /*
2396                          * Each RxD is of 4 qwords, update the number of
2397                          * qwords replenished
2398                          */
2399                         new_count = (ring->doorbell_cnt * 4);
2400
2401                         /* For each block add 4 more qwords */
2402                         ring->total_db_cnt += ring->doorbell_cnt;
2403                         if (ring->total_db_cnt >= ring->rxds_per_block) {
2404                                 new_count += 4;
2405                                 /* Reset total count */
2406                                 ring->total_db_cnt %= ring->rxds_per_block;
2407                         }
2408                         writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(new_count),
2409                                 &ring->vp_reg->prc_rxd_doorbell);
2410                         val64 =
2411                           readl(&ring->common_reg->titan_general_int_status);
2412                         ring->doorbell_cnt = 0;
2413                 }
2414         }
2415
2416         return status;
2417 }
2418
2419 /**
2420  * vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process
2421  * the same.
2422  * @fifo: Handle to the fifo object used for non offload send
2423  *
2424  * The function polls the Tx for the completed descriptors and calls
2425  * the driver via supplied completion callback.
2426  *
2427  * Returns: VXGE_HW_OK, if the polling is completed successful.
2428  * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
2429  * descriptors available which are yet to be processed.
2430  */
2431 enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo,
2432                                         struct sk_buff ***skb_ptr, int nr_skb,
2433                                         int *more)
2434 {
2435         enum vxge_hw_fifo_tcode t_code;
2436         void *first_txdlh;
2437         enum vxge_hw_status status = VXGE_HW_OK;
2438         struct __vxge_hw_channel *channel;
2439
2440         channel = &fifo->channel;
2441
2442         status = vxge_hw_fifo_txdl_next_completed(fifo,
2443                                 &first_txdlh, &t_code);
2444         if (status == VXGE_HW_OK)
2445                 if (fifo->callback(fifo, first_txdlh, t_code,
2446                         channel->userdata, skb_ptr, nr_skb, more) != VXGE_HW_OK)
2447                         status = VXGE_HW_COMPLETIONS_REMAIN;
2448
2449         return status;
2450 }