1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */
2 /* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */
9 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */
10 #define IONIC_DEV_INFO_VERSION 1
11 #define IONIC_IFNAMSIZ 16
16 enum ionic_cmd_opcode {
20 IONIC_CMD_IDENTIFY = 1,
23 IONIC_CMD_GETATTR = 4,
24 IONIC_CMD_SETATTR = 5,
27 IONIC_CMD_PORT_IDENTIFY = 10,
28 IONIC_CMD_PORT_INIT = 11,
29 IONIC_CMD_PORT_RESET = 12,
30 IONIC_CMD_PORT_GETATTR = 13,
31 IONIC_CMD_PORT_SETATTR = 14,
34 IONIC_CMD_LIF_IDENTIFY = 20,
35 IONIC_CMD_LIF_INIT = 21,
36 IONIC_CMD_LIF_RESET = 22,
37 IONIC_CMD_LIF_GETATTR = 23,
38 IONIC_CMD_LIF_SETATTR = 24,
40 IONIC_CMD_RX_MODE_SET = 30,
41 IONIC_CMD_RX_FILTER_ADD = 31,
42 IONIC_CMD_RX_FILTER_DEL = 32,
45 IONIC_CMD_Q_INIT = 40,
46 IONIC_CMD_Q_CONTROL = 41,
49 IONIC_CMD_RDMA_RESET_LIF = 50,
50 IONIC_CMD_RDMA_CREATE_EQ = 51,
51 IONIC_CMD_RDMA_CREATE_CQ = 52,
52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
55 IONIC_CMD_VF_GETATTR = 60,
56 IONIC_CMD_VF_SETATTR = 61,
59 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
60 IONIC_CMD_QOS_CLASS_INIT = 241,
61 IONIC_CMD_QOS_CLASS_RESET = 242,
63 /* Firmware commands */
64 IONIC_CMD_FW_DOWNLOAD = 254,
65 IONIC_CMD_FW_CONTROL = 255,
69 * Command Return codes
71 enum ionic_status_code {
72 IONIC_RC_SUCCESS = 0, /* Success */
73 IONIC_RC_EVERSION = 1, /* Incorrect version for request */
74 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */
75 IONIC_RC_EIO = 3, /* I/O error */
76 IONIC_RC_EPERM = 4, /* Permission denied */
77 IONIC_RC_EQID = 5, /* Bad qid */
78 IONIC_RC_EQTYPE = 6, /* Bad qtype */
79 IONIC_RC_ENOENT = 7, /* No such element */
80 IONIC_RC_EINTR = 8, /* operation interrupted */
81 IONIC_RC_EAGAIN = 9, /* Try again */
82 IONIC_RC_ENOMEM = 10, /* Out of memory */
83 IONIC_RC_EFAULT = 11, /* Bad address */
84 IONIC_RC_EBUSY = 12, /* Device or resource busy */
85 IONIC_RC_EEXIST = 13, /* object already exists */
86 IONIC_RC_EINVAL = 14, /* Invalid argument */
87 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */
88 IONIC_RC_ERANGE = 16, /* Parameter out of range */
89 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */
90 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
91 IONIC_RC_ENOSUPP = 19, /* Operation not supported */
92 IONIC_RC_ERROR = 29, /* Generic error */
94 IONIC_RC_ERDMA = 30, /* Generic RDMA error */
97 enum ionic_notifyq_opcode {
98 IONIC_EVENT_LINK_CHANGE = 1,
99 IONIC_EVENT_RESET = 2,
100 IONIC_EVENT_HEARTBEAT = 3,
105 * struct cmd - General admin command format
106 * @opcode: Opcode for the command
107 * @lif_index: LIF index
108 * @cmd_data: Opcode-specific command bytes
110 struct ionic_admin_cmd {
118 * struct ionic_admin_comp - General admin command completion format
119 * @status: The status of the command (enum status_code)
120 * @comp_index: The index in the descriptor ring for which this
122 * @cmd_data: Command-specific bytes.
123 * @color: Color bit. (Always 0 for commands issued to the
124 * Device Cmd Registers.)
126 struct ionic_admin_comp {
132 #define IONIC_COMP_COLOR_MASK 0x80
135 static inline u8 color_match(u8 color, u8 done_color)
137 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
141 * struct ionic_nop_cmd - NOP command
144 struct ionic_nop_cmd {
150 * struct ionic_nop_comp - NOP command completion
151 * @status: The status of the command (enum status_code)
153 struct ionic_nop_comp {
159 * struct ionic_dev_init_cmd - Device init command
163 struct ionic_dev_init_cmd {
170 * struct init_comp - Device init command completion
171 * @status: The status of the command (enum status_code)
173 struct ionic_dev_init_comp {
179 * struct ionic_dev_reset_cmd - Device reset command
182 struct ionic_dev_reset_cmd {
188 * struct reset_comp - Reset command completion
189 * @status: The status of the command (enum status_code)
191 struct ionic_dev_reset_comp {
196 #define IONIC_IDENTITY_VERSION_1 1
199 * struct ionic_dev_identify_cmd - Driver/device identify command
201 * @ver: Highest version of identify supported by driver
203 struct ionic_dev_identify_cmd {
210 * struct dev_identify_comp - Driver/device identify command completion
211 * @status: The status of the command (enum status_code)
212 * @ver: Version of identify returned by device
214 struct ionic_dev_identify_comp {
221 IONIC_OS_TYPE_LINUX = 1,
222 IONIC_OS_TYPE_WIN = 2,
223 IONIC_OS_TYPE_DPDK = 3,
224 IONIC_OS_TYPE_FREEBSD = 4,
225 IONIC_OS_TYPE_IPXE = 5,
226 IONIC_OS_TYPE_ESXI = 6,
230 * union drv_identity - driver identity information
231 * @os_type: OS type (see enum os_type)
232 * @os_dist: OS distribution, numeric format
233 * @os_dist_str: OS distribution, string format
234 * @kernel_ver: Kernel version, numeric format
235 * @kernel_ver_str: Kernel version, string format
236 * @driver_ver_str: Driver version, string format
238 union ionic_drv_identity {
242 char os_dist_str[128];
244 char kernel_ver_str[32];
245 char driver_ver_str[32];
251 * union dev_identity - device identity information
252 * @version: Version of device identify
253 * @type: Identify type (0 for now)
254 * @nports: Number of ports provisioned
255 * @nlifs: Number of LIFs provisioned
256 * @nintrs: Number of interrupts provisioned
257 * @ndbpgs_per_lif: Number of doorbell pages per LIF
258 * @intr_coal_mult: Interrupt coalescing multiplication factor.
259 * Scale user-supplied interrupt coalescing
260 * value in usecs to device units using:
261 * device units = usecs * mult / div
262 * @intr_coal_div: Interrupt coalescing division factor.
263 * Scale user-supplied interrupt coalescing
264 * value in usecs to device units using:
265 * device units = usecs * mult / div
268 union ionic_dev_identity {
277 __le32 ndbpgs_per_lif;
278 __le32 intr_coal_mult;
279 __le32 intr_coal_div;
284 enum ionic_lif_type {
285 IONIC_LIF_TYPE_CLASSIC = 0,
286 IONIC_LIF_TYPE_MACVLAN = 1,
287 IONIC_LIF_TYPE_NETQUEUE = 2,
291 * struct ionic_lif_identify_cmd - lif identify command
293 * @type: lif type (enum lif_type)
294 * @ver: version of identify returned by device
296 struct ionic_lif_identify_cmd {
304 * struct ionic_lif_identify_comp - lif identify command completion
305 * @status: status of the command (enum status_code)
306 * @ver: version of identify returned by device
308 struct ionic_lif_identify_comp {
314 enum ionic_lif_capability {
315 IONIC_LIF_CAP_ETH = BIT(0),
316 IONIC_LIF_CAP_RDMA = BIT(1),
320 * Logical Queue Types
322 enum ionic_logical_qtype {
323 IONIC_QTYPE_ADMINQ = 0,
324 IONIC_QTYPE_NOTIFYQ = 1,
328 IONIC_QTYPE_MAX = 16,
332 * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue type.
333 * @qtype: Hardware Queue Type.
334 * @qid_count: Number of Queue IDs of the logical type.
335 * @qid_base: Minimum Queue ID of the logical type.
337 struct ionic_lif_logical_qtype {
344 enum ionic_lif_state {
345 IONIC_LIF_DISABLE = 0,
346 IONIC_LIF_ENABLE = 1,
347 IONIC_LIF_HANG_RESET = 2,
352 * @state: lif state (enum lif_state)
355 * @mac: station mac address
356 * @features: features (enum ionic_eth_hw_features)
357 * @queue_count: queue counts per queue-type
359 union ionic_lif_config {
363 char name[IONIC_IFNAMSIZ];
368 __le32 queue_count[IONIC_QTYPE_MAX];
374 * struct ionic_lif_identity - lif identity information (type-specific)
376 * @capabilities LIF capabilities
379 * @version: Ethernet identify structure version.
380 * @features: Ethernet features supported on this lif type.
381 * @max_ucast_filters: Number of perfect unicast addresses supported.
382 * @max_mcast_filters: Number of perfect multicast addresses supported.
383 * @min_frame_size: Minimum size of frames to be sent
384 * @max_frame_size: Maximim size of frames to be sent
385 * @config: LIF config struct with features, mtu, mac, q counts
388 * @version: RDMA version of opcodes and queue descriptors.
389 * @qp_opcodes: Number of rdma queue pair opcodes supported.
390 * @admin_opcodes: Number of rdma admin opcodes supported.
391 * @npts_per_lif: Page table size per lif
392 * @nmrs_per_lif: Number of memory regions per lif
393 * @nahs_per_lif: Number of address handles per lif
394 * @max_stride: Max work request stride.
395 * @cl_stride: Cache line stride.
396 * @pte_stride: Page table entry stride.
397 * @rrq_stride: Remote RQ work request stride.
398 * @rsq_stride: Remote SQ work request stride.
399 * @dcqcn_profiles: Number of DCQCN profiles
400 * @aq_qtype: RDMA Admin Qtype.
401 * @sq_qtype: RDMA Send Qtype.
402 * @rq_qtype: RDMA Receive Qtype.
403 * @cq_qtype: RDMA Completion Qtype.
404 * @eq_qtype: RDMA Event Qtype.
406 union ionic_lif_identity {
413 __le32 max_ucast_filters;
414 __le32 max_mcast_filters;
415 __le16 rss_ind_tbl_sz;
416 __le32 min_frame_size;
417 __le32 max_frame_size;
419 union ionic_lif_config config;
436 u8 rsvd_dimensions[10];
437 struct ionic_lif_logical_qtype aq_qtype;
438 struct ionic_lif_logical_qtype sq_qtype;
439 struct ionic_lif_logical_qtype rq_qtype;
440 struct ionic_lif_logical_qtype cq_qtype;
441 struct ionic_lif_logical_qtype eq_qtype;
448 * struct ionic_lif_init_cmd - LIF init command
450 * @type: LIF type (enum lif_type)
452 * @info_pa: destination address for lif info (struct ionic_lif_info)
454 struct ionic_lif_init_cmd {
464 * struct ionic_lif_init_comp - LIF init command completion
465 * @status: The status of the command (enum status_code)
467 struct ionic_lif_init_comp {
475 * struct ionic_q_init_cmd - Queue init command
477 * @type: Logical queue type
478 * @ver: Queue version (defines opcode/descriptor scope)
479 * @lif_index: LIF index
480 * @index: (lif, qtype) relative admin queue index
481 * @intr_index: Interrupt control register index
484 * IRQ: Interrupt requested on completion
485 * ENA: Enable the queue. If ENA=0 the queue is initialized
486 * but remains disabled, to be later enabled with the
487 * Queue Enable command. If ENA=1, then queue is
488 * initialized and then enabled.
489 * SG: Enable Scatter-Gather on the queue.
490 * in number of descs. The actual ring size is
491 * (1 << ring_size). For example, to
492 * select a ring size of 64 descriptors write
493 * ring_size = 6. The minimum ring_size value is 2
494 * for a ring size of 4 descriptors. The maximum
495 * ring_size value is 16 for a ring size of 64k
496 * descriptors. Values of ring_size <2 and >16 are
498 * EQ: Enable the Event Queue
499 * @cos: Class of service for this queue.
500 * @ring_size: Queue ring size, encoded as a log2(size)
501 * @ring_base: Queue ring base address
502 * @cq_ring_base: Completion queue ring base address
503 * @sg_ring_base: Scatter/Gather ring base address
504 * @eq_index: Event queue index
506 struct ionic_q_init_cmd {
517 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */
518 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */
519 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */
520 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */
521 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
532 * struct ionic_q_init_comp - Queue init command completion
533 * @status: The status of the command (enum status_code)
534 * @ver: Queue version (defines opcode/descriptor scope)
535 * @comp_index: The index in the descriptor ring for which this
537 * @hw_index: Hardware Queue ID
538 * @hw_type: Hardware Queue type
541 struct ionic_q_init_comp {
551 /* the device's internal addressing uses up to 52 bits */
552 #define IONIC_ADDR_LEN 52
553 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
555 enum ionic_txq_desc_opcode {
556 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
557 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
558 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
559 IONIC_TXQ_DESC_OPCODE_TSO = 3,
563 * struct ionic_txq_desc - Ethernet Tx queue descriptor format
564 * @opcode: Tx operation, see TXQ_DESC_OPCODE_*:
566 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
568 * Non-offload send. No segmentation,
569 * fragmentation or checksum calc/insertion is
570 * performed by device; packet is prepared
571 * to send by software stack and requires
572 * no further manipulation from device.
574 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
576 * Offload 16-bit L4 checksum
577 * calculation/insertion. The device will
578 * calculate the L4 checksum value and
579 * insert the result in the packet's L4
580 * header checksum field. The L4 checksum
581 * is calculated starting at @csum_start bytes
582 * into the packet to the end of the packet.
583 * The checksum insertion position is given
584 * in @csum_offset. This feature is only
585 * applicable to protocols such as TCP, UDP
586 * and ICMP where a standard (i.e. the
587 * 'IP-style' checksum) one's complement
588 * 16-bit checksum is used, using an IP
589 * pseudo-header to seed the calculation.
590 * Software will preload the L4 checksum
591 * field with the IP pseudo-header checksum.
593 * For tunnel encapsulation, @csum_start and
594 * @csum_offset refer to the inner L4
595 * header. Supported tunnels encapsulations
596 * are: IPIP, GRE, and UDP. If the @encap
597 * is clear, no further processing by the
598 * device is required; software will
599 * calculate the outer header checksums. If
600 * the @encap is set, the device will
601 * offload the outer header checksums using
602 * LCO (local checksum offload) (see
603 * Documentation/networking/checksum-offloads.rst
606 * IONIC_TXQ_DESC_OPCODE_CSUM_HW:
608 * Offload 16-bit checksum computation to hardware.
609 * If @csum_l3 is set then the packet's L3 checksum is
610 * updated. Similarly, if @csum_l4 is set the the L4
611 * checksum is updated. If @encap is set then encap header
612 * checksums are also updated.
614 * IONIC_TXQ_DESC_OPCODE_TSO:
616 * Device preforms TCP segmentation offload
617 * (TSO). @hdr_len is the number of bytes
618 * to the end of TCP header (the offset to
619 * the TCP payload). @mss is the desired
620 * MSS, the TCP payload length for each
621 * segment. The device will calculate/
622 * insert IP (IPv4 only) and TCP checksums
623 * for each segment. In the first data
624 * buffer containing the header template,
625 * the driver will set IPv4 checksum to 0
626 * and preload TCP checksum with the IP
627 * pseudo header calculated with IP length = 0.
629 * Supported tunnel encapsulations are IPIP,
630 * layer-3 GRE, and UDP. @hdr_len includes
631 * both outer and inner headers. The driver
632 * will set IPv4 checksum to zero and
633 * preload TCP checksum with IP pseudo
634 * header on the inner header.
636 * TCP ECN offload is supported. The device
637 * will set CWR flag in the first segment if
638 * CWR is set in the template header, and
639 * clear CWR in remaining segments.
642 * Insert an L2 VLAN header using @vlan_tci.
644 * Calculate encap header checksum.
646 * Compute L3 header checksum.
648 * Compute L4 header checksum.
653 * @num_sg_elems: Number of scatter-gather elements in SG
655 * @addr: First data buffer's DMA address.
656 * (Subsequent data buffers are on txq_sg_desc).
657 * @len: First data buffer's length, in bytes
658 * @vlan_tci: VLAN tag to insert in the packet (if requested
659 * by @V-bit). Includes .1p and .1q tags
660 * @hdr_len: Length of packet headers, including
661 * encapsulating outer header, if applicable.
662 * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and
663 * TXQ_DESC_OPCODE_TSO. Should be set to zero for
664 * all other modes. For
665 * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
666 * of headers up to inner-most L4 header. For
667 * TXQ_DESC_OPCODE_TSO, @hdr_len is up to
668 * inner-most L4 payload, so inclusive of
669 * inner-most L4 header.
670 * @mss: Desired MSS value for TSO. Only applicable for
671 * TXQ_DESC_OPCODE_TSO.
672 * @csum_start: Offset into inner-most L3 header of checksum
673 * @csum_offset: Offset into inner-most L4 header of checksum
676 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf
677 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4
678 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf
679 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0
680 #define IONIC_TXQ_DESC_NSGE_MASK 0xf
681 #define IONIC_TXQ_DESC_NSGE_SHIFT 8
682 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
683 #define IONIC_TXQ_DESC_ADDR_SHIFT 12
686 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1
687 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
689 /* flags for csum_hw opcode */
690 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
691 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
693 /* flags for tso opcode */
694 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
695 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
697 struct ionic_txq_desc {
716 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
721 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
722 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
723 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
724 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
729 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
732 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
733 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
734 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
735 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
738 #define IONIC_TX_MAX_SG_ELEMS 8
739 #define IONIC_RX_MAX_SG_ELEMS 8
742 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list
743 * @addr: DMA address of SG element data buffer
744 * @len: Length of SG element data buffer, in bytes
746 struct ionic_txq_sg_desc {
747 struct ionic_txq_sg_elem {
751 } elems[IONIC_TX_MAX_SG_ELEMS];
755 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor
756 * @status: The status of the command (enum status_code)
757 * @comp_index: The index in the descriptor ring for which this
761 struct ionic_txq_comp {
769 enum ionic_rxq_desc_opcode {
770 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
771 IONIC_RXQ_DESC_OPCODE_SG = 1,
775 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format
776 * @opcode: Rx operation, see RXQ_DESC_OPCODE_*:
778 * RXQ_DESC_OPCODE_SIMPLE:
780 * Receive full packet into data buffer
781 * starting at @addr. Results of
782 * receive, including actual bytes received,
783 * are recorded in Rx completion descriptor.
785 * @len: Data buffer's length, in bytes.
786 * @addr: Data buffer's DMA address
788 struct ionic_rxq_desc {
796 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list
797 * @addr: DMA address of SG element data buffer
798 * @len: Length of SG element data buffer, in bytes
800 struct ionic_rxq_sg_desc {
801 struct ionic_rxq_sg_elem {
805 } elems[IONIC_RX_MAX_SG_ELEMS];
809 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor
810 * @status: The status of the command (enum status_code)
811 * @num_sg_elems: Number of SG elements used by this descriptor
812 * @comp_index: The index in the descriptor ring for which this
814 * @rss_hash: 32-bit RSS hash
815 * @csum: 16-bit sum of the packet's L2 payload.
816 * If the packet's L2 payload is odd length, an extra
817 * zero-value byte is included in the @csum calculation but
818 * not included in @len.
819 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is
820 * set. Includes .1p and .1q tags.
821 * @len: Received packet length, in bytes. Excludes FCS.
822 * @csum_calc L2 payload checksum is computed or not
823 * @csum_tcp_ok: The TCP checksum calculated by the device
824 * matched the checksum in the receive packet's
826 * @csum_tcp_bad: The TCP checksum calculated by the device did
827 * not match the checksum in the receive packet's
829 * @csum_udp_ok: The UDP checksum calculated by the device
830 * matched the checksum in the receive packet's
832 * @csum_udp_bad: The UDP checksum calculated by the device did
833 * not match the checksum in the receive packet's
835 * @csum_ip_ok: The IPv4 checksum calculated by the device
836 * matched the checksum in the receive packet's
837 * first IPv4 header. If the receive packet
838 * contains both a tunnel IPv4 header and a
839 * transport IPv4 header, the device validates the
840 * checksum for the both IPv4 headers.
841 * @csum_ip_bad: The IPv4 checksum calculated by the device did
842 * not match the checksum in the receive packet's
843 * first IPv4 header. If the receive packet
844 * contains both a tunnel IPv4 header and a
845 * transport IPv4 header, the device validates the
846 * checksum for both IP headers.
847 * @VLAN: VLAN header was stripped and placed in @vlan_tci.
848 * @pkt_type: Packet type
851 struct ionic_rxq_comp {
860 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
861 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
862 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
863 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
864 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
865 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
866 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
867 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
869 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
872 enum ionic_pkt_type {
873 IONIC_PKT_TYPE_NON_IP = 0x000,
874 IONIC_PKT_TYPE_IPV4 = 0x001,
875 IONIC_PKT_TYPE_IPV4_TCP = 0x003,
876 IONIC_PKT_TYPE_IPV4_UDP = 0x005,
877 IONIC_PKT_TYPE_IPV6 = 0x008,
878 IONIC_PKT_TYPE_IPV6_TCP = 0x018,
879 IONIC_PKT_TYPE_IPV6_UDP = 0x028,
882 enum ionic_eth_hw_features {
883 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
884 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
885 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
886 IONIC_ETH_HW_RX_HASH = BIT(3),
887 IONIC_ETH_HW_RX_CSUM = BIT(4),
888 IONIC_ETH_HW_TX_SG = BIT(5),
889 IONIC_ETH_HW_RX_SG = BIT(6),
890 IONIC_ETH_HW_TX_CSUM = BIT(7),
891 IONIC_ETH_HW_TSO = BIT(8),
892 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
893 IONIC_ETH_HW_TSO_ECN = BIT(10),
894 IONIC_ETH_HW_TSO_GRE = BIT(11),
895 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
896 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
897 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
898 IONIC_ETH_HW_TSO_UDP = BIT(15),
899 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
903 * struct ionic_q_control_cmd - Queue control command
906 * @lif_index: LIF index
907 * @index: Queue index
908 * @oper: Operation (enum q_control_oper)
910 struct ionic_q_control_cmd {
919 typedef struct ionic_admin_comp ionic_q_control_comp;
921 enum q_control_oper {
924 IONIC_Q_HANG_RESET = 2,
928 * Physical connection type
930 enum ionic_phy_type {
931 IONIC_PHY_TYPE_NONE = 0,
932 IONIC_PHY_TYPE_COPPER = 1,
933 IONIC_PHY_TYPE_FIBER = 2,
939 enum ionic_xcvr_state {
940 IONIC_XCVR_STATE_REMOVED = 0,
941 IONIC_XCVR_STATE_INSERTED = 1,
942 IONIC_XCVR_STATE_PENDING = 2,
943 IONIC_XCVR_STATE_SPROM_READ = 3,
944 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
948 * Supported link modes
950 enum ionic_xcvr_pid {
951 IONIC_XCVR_PID_UNKNOWN = 0,
954 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
955 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
956 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
957 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
958 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
961 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
962 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
963 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
964 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
965 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
966 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
967 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
968 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
969 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
970 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
971 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
972 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
973 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
974 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
975 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
976 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
977 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
978 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
979 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
980 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
981 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
987 enum ionic_port_type {
988 IONIC_PORT_TYPE_NONE = 0, /* port type not configured */
989 IONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */
990 IONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */
996 enum ionic_port_admin_state {
997 IONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */
998 IONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */
999 IONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */
1003 * Port operational status
1005 enum ionic_port_oper_status {
1006 IONIC_PORT_OPER_STATUS_NONE = 0, /* port is disabled */
1007 IONIC_PORT_OPER_STATUS_UP = 1, /* port is linked up */
1008 IONIC_PORT_OPER_STATUS_DOWN = 2, /* port link status is down */
1012 * Ethernet Forward error correction (fec) modes
1014 enum ionic_port_fec_type {
1015 IONIC_PORT_FEC_TYPE_NONE = 0, /* Disabled */
1016 IONIC_PORT_FEC_TYPE_FC = 1, /* FireCode */
1017 IONIC_PORT_FEC_TYPE_RS = 2, /* ReedSolomon */
1021 * Ethernet pause (flow control) modes
1023 enum ionic_port_pause_type {
1024 IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */
1025 IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */
1026 IONIC_PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */
1032 enum ionic_port_loopback_mode {
1033 IONIC_PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */
1034 IONIC_PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */
1035 IONIC_PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */
1039 * Transceiver Status information
1040 * @state: Transceiver status (enum ionic_xcvr_state)
1041 * @phy: Physical connection type (enum ionic_phy_type)
1042 * @pid: Transceiver link mode (enum pid)
1043 * @sprom: Transceiver sprom contents
1045 struct ionic_xcvr_status {
1053 * Port configuration
1054 * @speed: port speed (in Mbps)
1056 * @state: port admin state (enum port_admin_state)
1057 * @an_enable: autoneg enable
1058 * @fec_type: fec type (enum ionic_port_fec_type)
1059 * @pause_type: pause type (enum ionic_port_pause_type)
1060 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode)
1062 union ionic_port_config {
1064 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */
1065 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */
1066 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */
1067 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */
1068 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */
1069 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */
1075 #define IONIC_PAUSE_TYPE_MASK 0x0f
1076 #define IONIC_PAUSE_FLAGS_MASK 0xf0
1077 #define IONIC_PAUSE_F_TX 0x10
1078 #define IONIC_PAUSE_F_RX 0x20
1086 * Port Status information
1087 * @status: link status (enum ionic_port_oper_status)
1089 * @speed: link speed (in Mbps)
1090 * @xcvr: tranceiver status
1092 struct ionic_port_status {
1097 struct ionic_xcvr_status xcvr;
1101 * struct ionic_port_identify_cmd - Port identify command
1103 * @index: port index
1104 * @ver: Highest version of identify supported by driver
1106 struct ionic_port_identify_cmd {
1114 * struct ionic_port_identify_comp - Port identify command completion
1115 * @status: The status of the command (enum status_code)
1116 * @ver: Version of identify returned by device
1118 struct ionic_port_identify_comp {
1125 * struct ionic_port_init_cmd - Port initialization command
1127 * @index: port index
1128 * @info_pa: destination address for port info (struct ionic_port_info)
1130 struct ionic_port_init_cmd {
1139 * struct ionic_port_init_comp - Port initialization command completion
1140 * @status: The status of the command (enum status_code)
1142 struct ionic_port_init_comp {
1148 * struct ionic_port_reset_cmd - Port reset command
1150 * @index: port index
1152 struct ionic_port_reset_cmd {
1159 * struct ionic_port_reset_comp - Port reset command completion
1160 * @status: The status of the command (enum status_code)
1162 struct ionic_port_reset_comp {
1168 * enum stats_ctl_cmd - List of commands for stats control
1170 enum ionic_stats_ctl_cmd {
1171 IONIC_STATS_CTL_RESET = 0,
1176 * enum ionic_port_attr - List of device attributes
1178 enum ionic_port_attr {
1179 IONIC_PORT_ATTR_STATE = 0,
1180 IONIC_PORT_ATTR_SPEED = 1,
1181 IONIC_PORT_ATTR_MTU = 2,
1182 IONIC_PORT_ATTR_AUTONEG = 3,
1183 IONIC_PORT_ATTR_FEC = 4,
1184 IONIC_PORT_ATTR_PAUSE = 5,
1185 IONIC_PORT_ATTR_LOOPBACK = 6,
1186 IONIC_PORT_ATTR_STATS_CTRL = 7,
1190 * struct ionic_port_setattr_cmd - Set port attributes on the NIC
1192 * @index: port index
1193 * @attr: Attribute type (enum ionic_port_attr)
1195 struct ionic_port_setattr_cmd {
1214 * struct ionic_port_setattr_comp - Port set attr command completion
1215 * @status: The status of the command (enum status_code)
1218 struct ionic_port_setattr_comp {
1225 * struct ionic_port_getattr_cmd - Get port attributes from the NIC
1227 * @index: port index
1228 * @attr: Attribute type (enum ionic_port_attr)
1230 struct ionic_port_getattr_cmd {
1238 * struct ionic_port_getattr_comp - Port get attr command completion
1239 * @status: The status of the command (enum status_code)
1242 struct ionic_port_getattr_comp {
1259 * struct ionic_lif_status - Lif status register
1260 * @eid: most recent NotifyQ event id
1261 * @port_num: port the lif is connected to
1262 * @link_status: port status (enum ionic_port_oper_status)
1263 * @link_speed: speed of link in Mbps
1264 * @link_down_count: number of times link status changes
1266 struct ionic_lif_status {
1271 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */
1272 __le16 link_down_count;
1277 * struct ionic_lif_reset_cmd - LIF reset command
1281 struct ionic_lif_reset_cmd {
1288 typedef struct ionic_admin_comp ionic_lif_reset_comp;
1290 enum ionic_dev_state {
1291 IONIC_DEV_DISABLE = 0,
1292 IONIC_DEV_ENABLE = 1,
1293 IONIC_DEV_HANG_RESET = 2,
1297 * enum ionic_dev_attr - List of device attributes
1299 enum ionic_dev_attr {
1300 IONIC_DEV_ATTR_STATE = 0,
1301 IONIC_DEV_ATTR_NAME = 1,
1302 IONIC_DEV_ATTR_FEATURES = 2,
1306 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC
1308 * @attr: Attribute type (enum ionic_dev_attr)
1309 * @state: Device state (enum ionic_dev_state)
1310 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated
1311 * @features: Device features
1313 struct ionic_dev_setattr_cmd {
1319 char name[IONIC_IFNAMSIZ];
1326 * struct ionic_dev_setattr_comp - Device set attr command completion
1327 * @status: The status of the command (enum status_code)
1328 * @features: Device features
1331 struct ionic_dev_setattr_comp {
1342 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC
1344 * @attr: Attribute type (enum ionic_dev_attr)
1346 struct ionic_dev_getattr_cmd {
1353 * struct ionic_dev_setattr_comp - Device set attr command completion
1354 * @status: The status of the command (enum status_code)
1355 * @features: Device features
1358 struct ionic_dev_getattr_comp {
1371 #define IONIC_RSS_HASH_KEY_SIZE 40
1373 enum ionic_rss_hash_types {
1374 IONIC_RSS_TYPE_IPV4 = BIT(0),
1375 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1376 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1377 IONIC_RSS_TYPE_IPV6 = BIT(3),
1378 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1379 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1383 * enum ionic_lif_attr - List of LIF attributes
1385 enum ionic_lif_attr {
1386 IONIC_LIF_ATTR_STATE = 0,
1387 IONIC_LIF_ATTR_NAME = 1,
1388 IONIC_LIF_ATTR_MTU = 2,
1389 IONIC_LIF_ATTR_MAC = 3,
1390 IONIC_LIF_ATTR_FEATURES = 4,
1391 IONIC_LIF_ATTR_RSS = 5,
1392 IONIC_LIF_ATTR_STATS_CTRL = 6,
1396 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
1398 * @type: Attribute type (enum ionic_lif_attr)
1400 * @state: lif state (enum lif_state)
1401 * @name: The netdev name string, 0 terminated
1404 * @features: Features (enum ionic_eth_hw_features)
1405 * @rss: RSS properties
1406 * @types: The hash types to enable (see rss_hash_types).
1407 * @key: The hash secret key.
1408 * @addr: Address for the indirection table shared memory.
1409 * @stats_ctl: stats control commands (enum stats_ctl_cmd)
1411 struct ionic_lif_setattr_cmd {
1417 char name[IONIC_IFNAMSIZ];
1423 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1433 * struct ionic_lif_setattr_comp - LIF set attr command completion
1434 * @status: The status of the command (enum status_code)
1435 * @comp_index: The index in the descriptor ring for which this
1436 * is the completion.
1437 * @features: features (enum ionic_eth_hw_features)
1440 struct ionic_lif_setattr_comp {
1452 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC
1454 * @attr: Attribute type (enum ionic_lif_attr)
1457 struct ionic_lif_getattr_cmd {
1465 * struct ionic_lif_getattr_comp - LIF get attr command completion
1466 * @status: The status of the command (enum status_code)
1467 * @comp_index: The index in the descriptor ring for which this
1468 * is the completion.
1469 * @state: lif state (enum lif_state)
1470 * @name: The netdev name string, 0 terminated
1473 * @features: Features (enum ionic_eth_hw_features)
1476 struct ionic_lif_getattr_comp {
1490 enum ionic_rx_mode {
1491 IONIC_RX_MODE_F_UNICAST = BIT(0),
1492 IONIC_RX_MODE_F_MULTICAST = BIT(1),
1493 IONIC_RX_MODE_F_BROADCAST = BIT(2),
1494 IONIC_RX_MODE_F_PROMISC = BIT(3),
1495 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
1499 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command
1501 * @lif_index: LIF index
1502 * @rx_mode: Rx mode flags:
1503 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets.
1504 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets.
1505 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets.
1506 * IONIC_RX_MODE_F_PROMISC: Accept any packets.
1507 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets.
1509 struct ionic_rx_mode_set_cmd {
1517 typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1519 enum ionic_rx_filter_match_type {
1520 IONIC_RX_FILTER_MATCH_VLAN = 0,
1521 IONIC_RX_FILTER_MATCH_MAC,
1522 IONIC_RX_FILTER_MATCH_MAC_VLAN,
1526 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command
1528 * @qtype: Queue type
1529 * @lif_index: LIF index
1531 * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx)
1533 * @addr: MAC address (network-byte order)
1535 struct ionic_rx_filter_add_cmd {
1557 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
1558 * @status: The status of the command (enum status_code)
1559 * @comp_index: The index in the descriptor ring for which this
1560 * is the completion.
1561 * @filter_id: Filter ID
1562 * @color: Color bit.
1564 struct ionic_rx_filter_add_comp {
1574 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command
1576 * @lif_index: LIF index
1577 * @filter_id: Filter ID
1579 struct ionic_rx_filter_del_cmd {
1587 typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1590 * struct ionic_qos_identify_cmd - QoS identify command
1592 * @ver: Highest version of identify supported by driver
1595 struct ionic_qos_identify_cmd {
1602 * struct ionic_qos_identify_comp - QoS identify command completion
1603 * @status: The status of the command (enum status_code)
1604 * @ver: Version of identify returned by device
1606 struct ionic_qos_identify_comp {
1612 #define IONIC_QOS_CLASS_MAX 7
1613 #define IONIC_QOS_CLASS_NAME_SZ 32
1614 #define IONIC_QOS_DSCP_MAX_VALUES 64
1617 * enum ionic_qos_class
1619 enum ionic_qos_class {
1620 IONIC_QOS_CLASS_DEFAULT = 0,
1621 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
1622 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
1623 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
1624 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
1625 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
1626 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
1630 * enum ionic_qos_class_type - Traffic classification criteria
1632 enum ionic_qos_class_type {
1633 IONIC_QOS_CLASS_TYPE_NONE = 0,
1634 IONIC_QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */
1635 IONIC_QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */
1639 * enum ionic_qos_sched_type - Qos class scheduling type
1641 enum ionic_qos_sched_type {
1642 IONIC_QOS_SCHED_TYPE_STRICT = 0, /* Strict priority */
1643 IONIC_QOS_SCHED_TYPE_DWRR = 1, /* Deficit weighted round-robin */
1646 enum ionic_vf_attr {
1647 IONIC_VF_ATTR_SPOOFCHK = 1,
1648 IONIC_VF_ATTR_TRUST = 2,
1649 IONIC_VF_ATTR_MAC = 3,
1650 IONIC_VF_ATTR_LINKSTATE = 4,
1651 IONIC_VF_ATTR_VLAN = 5,
1652 IONIC_VF_ATTR_RATE = 6,
1653 IONIC_VF_ATTR_STATSADDR = 7,
1659 enum ionic_vf_link_status {
1660 IONIC_VF_LINK_STATUS_AUTO = 0, /* link state of the uplink */
1661 IONIC_VF_LINK_STATUS_UP = 1, /* link is always up */
1662 IONIC_VF_LINK_STATUS_DOWN = 2, /* link is always down */
1666 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
1669 * @attr: Attribute type (enum ionic_vf_attr)
1670 * macaddr mac address
1672 * maxrate max Tx rate in Mbps
1673 * spoofchk enable address spoof checking
1674 * trust enable VF trust
1675 * linkstate set link up or down
1676 * stats_pa set DMA address for VF stats
1678 struct ionic_vf_setattr_cmd {
1694 struct ionic_vf_setattr_comp {
1704 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
1707 * @attr: Attribute type (enum ionic_vf_attr)
1709 struct ionic_vf_getattr_cmd {
1716 struct ionic_vf_getattr_comp {
1734 * union ionic_qos_config - Qos configuration structure
1735 * @flags: Configuration flags
1736 * IONIC_QOS_CONFIG_F_ENABLE enable
1737 * IONIC_QOS_CONFIG_F_DROP drop/nodrop
1738 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite
1739 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite
1740 * @sched_type: Qos class scheduling type (enum ionic_qos_sched_type)
1741 * @class_type: Qos class type (enum ionic_qos_class_type)
1742 * @pause_type: Qos pause type (enum ionic_qos_pause_type)
1743 * @name: Qos class name
1744 * @mtu: MTU of the class
1745 * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP)
1746 * @dwrr_weight: Qos class scheduling weight
1747 * @strict_rlmt: Rate limit for strict priority scheduling
1748 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP)
1749 * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP)
1750 * @dot1q_pcp: Dot1q pcp value
1751 * @ndscp: Number of valid dscp values in the ip_dscp field
1752 * @ip_dscp: IP dscp values
1754 union ionic_qos_config {
1756 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
1757 #define IONIC_QOS_CONFIG_F_DROP BIT(1)
1758 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
1759 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
1764 char name[IONIC_QOS_CLASS_NAME_SZ];
1778 /* classification */
1783 u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES];
1791 * union ionic_qos_identity - QoS identity structure
1792 * @version: Version of the identify structure
1793 * @type: QoS system type
1794 * @nclasses: Number of usable QoS classes
1795 * @config: Current configuration of classes
1797 union ionic_qos_identity {
1802 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
1808 * struct qos_init_cmd - QoS config init command
1810 * @group: Qos class id
1811 * @info_pa: destination address for qos info
1813 struct ionic_qos_init_cmd {
1821 typedef struct ionic_admin_comp ionic_qos_init_comp;
1824 * struct ionic_qos_reset_cmd - Qos config reset command
1827 struct ionic_qos_reset_cmd {
1833 typedef struct ionic_admin_comp ionic_qos_reset_comp;
1836 * struct ionic_fw_download_cmd - Firmware download command
1838 * @addr: dma address of the firmware buffer
1839 * @offset: offset of the firmware buffer within the full image
1840 * @length: number of valid bytes in the firmware buffer
1842 struct ionic_fw_download_cmd {
1850 typedef struct ionic_admin_comp ionic_fw_download_comp;
1852 enum ionic_fw_control_oper {
1853 IONIC_FW_RESET = 0, /* Reset firmware */
1854 IONIC_FW_INSTALL = 1, /* Install firmware */
1855 IONIC_FW_ACTIVATE = 2, /* Activate firmware */
1859 * struct ionic_fw_control_cmd - Firmware control command
1861 * @oper: firmware control operation (enum ionic_fw_control_oper)
1862 * @slot: slot to activate
1864 struct ionic_fw_control_cmd {
1873 * struct ionic_fw_control_comp - Firmware control copletion
1875 * @slot: slot where the firmware was installed
1877 struct ionic_fw_control_comp {
1886 /******************************************************************
1887 ******************* RDMA Commands ********************************
1888 ******************************************************************/
1891 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
1893 * @lif_index: lif index
1895 * There is no rdma specific dev command completion struct. Completion uses
1896 * the common struct ionic_admin_comp. Only the status is indicated.
1897 * Nonzero status means the LIF does not support rdma.
1899 struct ionic_rdma_reset_cmd {
1907 * struct ionic_rdma_queue_cmd - Create RDMA Queue command
1908 * @opcode: opcode, 52, 53
1909 * @lif_index lif index
1910 * @qid_ver: (qid | (rdma version << 24))
1911 * @cid: intr, eq_id, or cq_id
1912 * @dbid: doorbell page id
1913 * @depth_log2: log base two of queue depth
1914 * @stride_log2: log base two of queue stride
1915 * @dma_addr: address of the queue memory
1916 * @xxx_table_index: temporary, but should not need pgtbl for contig. queues.
1918 * The same command struct is used to create an rdma event queue, completion
1919 * queue, or rdma admin queue. The cid is an interrupt number for an event
1920 * queue, an event queue id for a completion queue, or a completion queue id
1921 * for an rdma admin queue.
1923 * The queue created via a dev command must be contiguous in dma space.
1925 * The dev commands are intended only to be used during driver initialization,
1926 * to create queues supporting the rdma admin queue. Other queues, and other
1927 * types of rdma resources like memory regions, will be created and registered
1928 * via the rdma admin queue, and will support a more complete interface
1929 * providing scatter gather lists for larger, scattered queue buffers and
1930 * memory registration.
1932 * There is no rdma specific dev command completion struct. Completion uses
1933 * the common struct ionic_admin_comp. Only the status is indicated.
1935 struct ionic_rdma_queue_cmd {
1946 __le32 xxx_table_index;
1949 /******************************************************************
1950 ******************* Notify Events ********************************
1951 ******************************************************************/
1954 * struct ionic_notifyq_event
1955 * @eid: event number
1956 * @ecode: event code
1957 * @data: unspecified data about the event
1959 * This is the generic event report struct from which the other
1960 * actual events will be formed.
1962 struct ionic_notifyq_event {
1969 * struct ionic_link_change_event
1970 * @eid: event number
1971 * @ecode: event code = EVENT_OPCODE_LINK_CHANGE
1972 * @link_status: link up or down, with error bits (enum port_status)
1973 * @link_speed: speed of the network link
1975 * Sent when the network link state changes between UP and DOWN
1977 struct ionic_link_change_event {
1981 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */
1986 * struct ionic_reset_event
1987 * @eid: event number
1988 * @ecode: event code = EVENT_OPCODE_RESET
1989 * @reset_code: reset type
1990 * @state: 0=pending, 1=complete, 2=error
1992 * Sent when the NIC or some subsystem is going to be or
1995 struct ionic_reset_event {
2004 * struct ionic_heartbeat_event
2005 * @eid: event number
2006 * @ecode: event code = EVENT_OPCODE_HEARTBEAT
2008 * Sent periodically by the NIC to indicate continued health
2010 struct ionic_heartbeat_event {
2017 * struct ionic_log_event
2018 * @eid: event number
2019 * @ecode: event code = EVENT_OPCODE_LOG
2022 * Sent to notify the driver of an internal error.
2024 struct ionic_log_event {
2031 * struct ionic_port_stats
2033 struct ionic_port_stats {
2034 __le64 frames_rx_ok;
2035 __le64 frames_rx_all;
2036 __le64 frames_rx_bad_fcs;
2037 __le64 frames_rx_bad_all;
2038 __le64 octets_rx_ok;
2039 __le64 octets_rx_all;
2040 __le64 frames_rx_unicast;
2041 __le64 frames_rx_multicast;
2042 __le64 frames_rx_broadcast;
2043 __le64 frames_rx_pause;
2044 __le64 frames_rx_bad_length;
2045 __le64 frames_rx_undersized;
2046 __le64 frames_rx_oversized;
2047 __le64 frames_rx_fragments;
2048 __le64 frames_rx_jabber;
2049 __le64 frames_rx_pripause;
2050 __le64 frames_rx_stomped_crc;
2051 __le64 frames_rx_too_long;
2052 __le64 frames_rx_vlan_good;
2053 __le64 frames_rx_dropped;
2054 __le64 frames_rx_less_than_64b;
2055 __le64 frames_rx_64b;
2056 __le64 frames_rx_65b_127b;
2057 __le64 frames_rx_128b_255b;
2058 __le64 frames_rx_256b_511b;
2059 __le64 frames_rx_512b_1023b;
2060 __le64 frames_rx_1024b_1518b;
2061 __le64 frames_rx_1519b_2047b;
2062 __le64 frames_rx_2048b_4095b;
2063 __le64 frames_rx_4096b_8191b;
2064 __le64 frames_rx_8192b_9215b;
2065 __le64 frames_rx_other;
2066 __le64 frames_tx_ok;
2067 __le64 frames_tx_all;
2068 __le64 frames_tx_bad;
2069 __le64 octets_tx_ok;
2070 __le64 octets_tx_total;
2071 __le64 frames_tx_unicast;
2072 __le64 frames_tx_multicast;
2073 __le64 frames_tx_broadcast;
2074 __le64 frames_tx_pause;
2075 __le64 frames_tx_pripause;
2076 __le64 frames_tx_vlan;
2077 __le64 frames_tx_less_than_64b;
2078 __le64 frames_tx_64b;
2079 __le64 frames_tx_65b_127b;
2080 __le64 frames_tx_128b_255b;
2081 __le64 frames_tx_256b_511b;
2082 __le64 frames_tx_512b_1023b;
2083 __le64 frames_tx_1024b_1518b;
2084 __le64 frames_tx_1519b_2047b;
2085 __le64 frames_tx_2048b_4095b;
2086 __le64 frames_tx_4096b_8191b;
2087 __le64 frames_tx_8192b_9215b;
2088 __le64 frames_tx_other;
2089 __le64 frames_tx_pri_0;
2090 __le64 frames_tx_pri_1;
2091 __le64 frames_tx_pri_2;
2092 __le64 frames_tx_pri_3;
2093 __le64 frames_tx_pri_4;
2094 __le64 frames_tx_pri_5;
2095 __le64 frames_tx_pri_6;
2096 __le64 frames_tx_pri_7;
2097 __le64 frames_rx_pri_0;
2098 __le64 frames_rx_pri_1;
2099 __le64 frames_rx_pri_2;
2100 __le64 frames_rx_pri_3;
2101 __le64 frames_rx_pri_4;
2102 __le64 frames_rx_pri_5;
2103 __le64 frames_rx_pri_6;
2104 __le64 frames_rx_pri_7;
2105 __le64 tx_pripause_0_1us_count;
2106 __le64 tx_pripause_1_1us_count;
2107 __le64 tx_pripause_2_1us_count;
2108 __le64 tx_pripause_3_1us_count;
2109 __le64 tx_pripause_4_1us_count;
2110 __le64 tx_pripause_5_1us_count;
2111 __le64 tx_pripause_6_1us_count;
2112 __le64 tx_pripause_7_1us_count;
2113 __le64 rx_pripause_0_1us_count;
2114 __le64 rx_pripause_1_1us_count;
2115 __le64 rx_pripause_2_1us_count;
2116 __le64 rx_pripause_3_1us_count;
2117 __le64 rx_pripause_4_1us_count;
2118 __le64 rx_pripause_5_1us_count;
2119 __le64 rx_pripause_6_1us_count;
2120 __le64 rx_pripause_7_1us_count;
2121 __le64 rx_pause_1us_count;
2122 __le64 frames_tx_truncated;
2125 struct ionic_mgmt_port_stats {
2126 __le64 frames_rx_ok;
2127 __le64 frames_rx_all;
2128 __le64 frames_rx_bad_fcs;
2129 __le64 frames_rx_bad_all;
2130 __le64 octets_rx_ok;
2131 __le64 octets_rx_all;
2132 __le64 frames_rx_unicast;
2133 __le64 frames_rx_multicast;
2134 __le64 frames_rx_broadcast;
2135 __le64 frames_rx_pause;
2136 __le64 frames_rx_bad_length0;
2137 __le64 frames_rx_undersized1;
2138 __le64 frames_rx_oversized2;
2139 __le64 frames_rx_fragments3;
2140 __le64 frames_rx_jabber4;
2141 __le64 frames_rx_64b5;
2142 __le64 frames_rx_65b_127b6;
2143 __le64 frames_rx_128b_255b7;
2144 __le64 frames_rx_256b_511b8;
2145 __le64 frames_rx_512b_1023b9;
2146 __le64 frames_rx_1024b_1518b0;
2147 __le64 frames_rx_gt_1518b1;
2148 __le64 frames_rx_fifo_full2;
2149 __le64 frames_tx_ok3;
2150 __le64 frames_tx_all4;
2151 __le64 frames_tx_bad5;
2152 __le64 octets_tx_ok6;
2153 __le64 octets_tx_total7;
2154 __le64 frames_tx_unicast8;
2155 __le64 frames_tx_multicast9;
2156 __le64 frames_tx_broadcast0;
2157 __le64 frames_tx_pause1;
2161 * struct ionic_port_identity - port identity structure
2162 * @version: identity structure version
2163 * @type: type of port (enum port_type)
2164 * @num_lanes: number of lanes for the port
2165 * @autoneg: autoneg supported
2166 * @min_frame_size: minimum frame size supported
2167 * @max_frame_size: maximum frame size supported
2168 * @fec_type: supported fec types
2169 * @pause_type: supported pause types
2170 * @loopback_mode: supported loopback mode
2171 * @speeds: supported speeds
2172 * @config: current port configuration
2174 union ionic_port_identity {
2180 __le32 min_frame_size;
2181 __le32 max_frame_size;
2184 u8 loopback_mode[2];
2187 union ionic_port_config config;
2193 * struct ionic_port_info - port info structure
2194 * @port_status: port status
2195 * @port_stats: port stats
2197 struct ionic_port_info {
2198 union ionic_port_config config;
2199 struct ionic_port_status status;
2200 struct ionic_port_stats stats;
2204 * struct ionic_lif_stats
2206 struct ionic_lif_stats {
2208 __le64 rx_ucast_bytes;
2209 __le64 rx_ucast_packets;
2210 __le64 rx_mcast_bytes;
2211 __le64 rx_mcast_packets;
2212 __le64 rx_bcast_bytes;
2213 __le64 rx_bcast_packets;
2217 __le64 rx_ucast_drop_bytes;
2218 __le64 rx_ucast_drop_packets;
2219 __le64 rx_mcast_drop_bytes;
2220 __le64 rx_mcast_drop_packets;
2221 __le64 rx_bcast_drop_bytes;
2222 __le64 rx_bcast_drop_packets;
2223 __le64 rx_dma_error;
2226 __le64 tx_ucast_bytes;
2227 __le64 tx_ucast_packets;
2228 __le64 tx_mcast_bytes;
2229 __le64 tx_mcast_packets;
2230 __le64 tx_bcast_bytes;
2231 __le64 tx_bcast_packets;
2235 __le64 tx_ucast_drop_bytes;
2236 __le64 tx_ucast_drop_packets;
2237 __le64 tx_mcast_drop_bytes;
2238 __le64 tx_mcast_drop_packets;
2239 __le64 tx_bcast_drop_bytes;
2240 __le64 tx_bcast_drop_packets;
2241 __le64 tx_dma_error;
2243 /* Rx Queue/Ring drops */
2244 __le64 rx_queue_disabled;
2245 __le64 rx_queue_empty;
2246 __le64 rx_queue_error;
2247 __le64 rx_desc_fetch_error;
2248 __le64 rx_desc_data_error;
2252 /* Tx Queue/Ring drops */
2253 __le64 tx_queue_disabled;
2254 __le64 tx_queue_error;
2255 __le64 tx_desc_fetch_error;
2256 __le64 tx_desc_data_error;
2263 __le64 tx_rdma_ucast_bytes;
2264 __le64 tx_rdma_ucast_packets;
2265 __le64 tx_rdma_mcast_bytes;
2266 __le64 tx_rdma_mcast_packets;
2267 __le64 tx_rdma_cnp_packets;
2273 __le64 rx_rdma_ucast_bytes;
2274 __le64 rx_rdma_ucast_packets;
2275 __le64 rx_rdma_mcast_bytes;
2276 __le64 rx_rdma_mcast_packets;
2277 __le64 rx_rdma_cnp_packets;
2278 __le64 rx_rdma_ecn_packets;
2318 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */
2319 __le64 rdma_req_rx_pkt_seq_err;
2320 __le64 rdma_req_rx_rnr_retry_err;
2321 __le64 rdma_req_rx_remote_access_err;
2322 __le64 rdma_req_rx_remote_inv_req_err;
2323 __le64 rdma_req_rx_remote_oper_err;
2324 __le64 rdma_req_rx_implied_nak_seq_err;
2325 __le64 rdma_req_rx_cqe_err;
2326 __le64 rdma_req_rx_cqe_flush_err;
2328 __le64 rdma_req_rx_dup_responses;
2329 __le64 rdma_req_rx_invalid_packets;
2330 __le64 rdma_req_tx_local_access_err;
2331 __le64 rdma_req_tx_local_oper_err;
2332 __le64 rdma_req_tx_memory_mgmt_err;
2337 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
2338 __le64 rdma_resp_rx_dup_requests;
2339 __le64 rdma_resp_rx_out_of_buffer;
2340 __le64 rdma_resp_rx_out_of_seq_pkts;
2341 __le64 rdma_resp_rx_cqe_err;
2342 __le64 rdma_resp_rx_cqe_flush_err;
2343 __le64 rdma_resp_rx_local_len_err;
2344 __le64 rdma_resp_rx_inv_request_err;
2345 __le64 rdma_resp_rx_local_qp_oper_err;
2347 __le64 rdma_resp_rx_out_of_atomic_resource;
2348 __le64 rdma_resp_tx_pkt_seq_err;
2349 __le64 rdma_resp_tx_remote_inv_req_err;
2350 __le64 rdma_resp_tx_remote_access_err;
2351 __le64 rdma_resp_tx_remote_oper_err;
2352 __le64 rdma_resp_tx_rnr_retry_err;
2358 * struct ionic_lif_info - lif info structure
2360 struct ionic_lif_info {
2361 union ionic_lif_config config;
2362 struct ionic_lif_status status;
2363 struct ionic_lif_stats stats;
2366 union ionic_dev_cmd {
2368 struct ionic_admin_cmd cmd;
2369 struct ionic_nop_cmd nop;
2371 struct ionic_dev_identify_cmd identify;
2372 struct ionic_dev_init_cmd init;
2373 struct ionic_dev_reset_cmd reset;
2374 struct ionic_dev_getattr_cmd getattr;
2375 struct ionic_dev_setattr_cmd setattr;
2377 struct ionic_port_identify_cmd port_identify;
2378 struct ionic_port_init_cmd port_init;
2379 struct ionic_port_reset_cmd port_reset;
2380 struct ionic_port_getattr_cmd port_getattr;
2381 struct ionic_port_setattr_cmd port_setattr;
2383 struct ionic_vf_setattr_cmd vf_setattr;
2384 struct ionic_vf_getattr_cmd vf_getattr;
2386 struct ionic_lif_identify_cmd lif_identify;
2387 struct ionic_lif_init_cmd lif_init;
2388 struct ionic_lif_reset_cmd lif_reset;
2390 struct ionic_qos_identify_cmd qos_identify;
2391 struct ionic_qos_init_cmd qos_init;
2392 struct ionic_qos_reset_cmd qos_reset;
2394 struct ionic_q_init_cmd q_init;
2397 union ionic_dev_cmd_comp {
2400 struct ionic_admin_comp comp;
2401 struct ionic_nop_comp nop;
2403 struct ionic_dev_identify_comp identify;
2404 struct ionic_dev_init_comp init;
2405 struct ionic_dev_reset_comp reset;
2406 struct ionic_dev_getattr_comp getattr;
2407 struct ionic_dev_setattr_comp setattr;
2409 struct ionic_port_identify_comp port_identify;
2410 struct ionic_port_init_comp port_init;
2411 struct ionic_port_reset_comp port_reset;
2412 struct ionic_port_getattr_comp port_getattr;
2413 struct ionic_port_setattr_comp port_setattr;
2415 struct ionic_vf_setattr_comp vf_setattr;
2416 struct ionic_vf_getattr_comp vf_getattr;
2418 struct ionic_lif_identify_comp lif_identify;
2419 struct ionic_lif_init_comp lif_init;
2420 ionic_lif_reset_comp lif_reset;
2422 struct ionic_qos_identify_comp qos_identify;
2423 ionic_qos_init_comp qos_init;
2424 ionic_qos_reset_comp qos_reset;
2426 struct ionic_q_init_comp q_init;
2430 * union dev_info - Device info register format (read-only)
2431 * @signature: Signature value of 0x44455649 ('DEVI').
2432 * @version: Current version of info.
2433 * @asic_type: Asic type.
2434 * @asic_rev: Asic revision.
2435 * @fw_status: Firmware status.
2436 * @fw_heartbeat: Firmware heartbeat counter.
2437 * @serial_num: Serial number.
2438 * @fw_version: Firmware version.
2440 union ionic_dev_info_regs {
2441 #define IONIC_DEVINFO_FWVERS_BUFLEN 32
2442 #define IONIC_DEVINFO_SERIAL_BUFLEN 32
2450 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
2451 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
2457 * union ionic_dev_cmd_regs - Device command register format (read-write)
2458 * @doorbell: Device Cmd Doorbell, write-only.
2459 * Write a 1 to signal device to process cmd,
2460 * poll done for completion.
2461 * @done: Done indicator, bit 0 == 1 when command is complete.
2462 * @cmd: Opcode-specific command bytes
2463 * @comp: Opcode-specific response bytes
2464 * @data: Opcode-specific side-data
2466 union ionic_dev_cmd_regs {
2470 union ionic_dev_cmd cmd;
2471 union ionic_dev_cmd_comp comp;
2479 * union ionic_dev_regs - Device register format in for bar 0 page 0
2480 * @info: Device info registers
2481 * @devcmd: Device command registers
2483 union ionic_dev_regs {
2485 union ionic_dev_info_regs info;
2486 union ionic_dev_cmd_regs devcmd;
2491 union ionic_adminq_cmd {
2492 struct ionic_admin_cmd cmd;
2493 struct ionic_nop_cmd nop;
2494 struct ionic_q_init_cmd q_init;
2495 struct ionic_q_control_cmd q_control;
2496 struct ionic_lif_setattr_cmd lif_setattr;
2497 struct ionic_lif_getattr_cmd lif_getattr;
2498 struct ionic_rx_mode_set_cmd rx_mode_set;
2499 struct ionic_rx_filter_add_cmd rx_filter_add;
2500 struct ionic_rx_filter_del_cmd rx_filter_del;
2501 struct ionic_rdma_reset_cmd rdma_reset;
2502 struct ionic_rdma_queue_cmd rdma_queue;
2503 struct ionic_fw_download_cmd fw_download;
2504 struct ionic_fw_control_cmd fw_control;
2507 union ionic_adminq_comp {
2508 struct ionic_admin_comp comp;
2509 struct ionic_nop_comp nop;
2510 struct ionic_q_init_comp q_init;
2511 struct ionic_lif_setattr_comp lif_setattr;
2512 struct ionic_lif_getattr_comp lif_getattr;
2513 struct ionic_rx_filter_add_comp rx_filter_add;
2514 struct ionic_fw_control_comp fw_control;
2517 #define IONIC_BARS_MAX 6
2518 #define IONIC_PCI_BAR_DBELL 1
2521 #define IONIC_BAR0_SIZE 0x8000
2523 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
2524 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
2525 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
2526 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
2527 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
2528 #define IONIC_DEV_CMD_DONE 0x00000001
2530 #define IONIC_ASIC_TYPE_CAPRI 0
2533 * struct ionic_doorbell - Doorbell register layout
2534 * @p_index: Producer index
2535 * @ring: Selects the specific ring of the queue to update.
2536 * Type-specific meaning:
2537 * ring=0: Default producer/consumer queue.
2538 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs
2539 * send events to EQs when armed. EQs send
2540 * interrupts when armed.
2541 * @qid: The queue id selects the queue destination for the
2542 * producer index and flags.
2544 struct ionic_doorbell {
2552 struct ionic_intr_status {
2556 struct ionic_notifyq_cmd {
2557 __le32 data; /* Not used but needed for qcq structure */
2560 union ionic_notifyq_comp {
2561 struct ionic_notifyq_event event;
2562 struct ionic_link_change_event link_change;
2563 struct ionic_reset_event reset;
2564 struct ionic_heartbeat_event heartbeat;
2565 struct ionic_log_event log;
2569 struct ionic_identity {
2570 union ionic_drv_identity drv;
2571 union ionic_dev_identity dev;
2572 union ionic_lif_identity lif;
2573 union ionic_port_identity port;
2574 union ionic_qos_identity qos;
2579 #endif /* _IONIC_IF_H_ */