drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_H
  34 #define _QED_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/firmware.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/list.h>
  42 #include <linux/mutex.h>
  43 #include <linux/pci.h>
  44 #include <linux/slab.h>
  45 #include <linux/string.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/zlib.h>
  48 #include <linux/hashtable.h>
  49 #include <linux/qed/qed_if.h>
  50 #include "qed_debug.h"
  51 #include "qed_hsi.h"
  52
  53 extern const struct qed_common_ops qed_common_ops_pass;
  54
  55 #define QED_MAJOR_VERSION               8
  56 #define QED_MINOR_VERSION               37
  57 #define QED_REVISION_VERSION            0
  58 #define QED_ENGINEERING_VERSION         20
  59
  60 #define QED_VERSION                                              \
  61         ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
  62          (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
  63
  64 #define STORM_FW_VERSION                                       \
  65         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
  66          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  67
  68 #define MAX_HWFNS_PER_DEVICE    (4)
  69 #define NAME_SIZE 16
  70 #define VER_SIZE 16
  71
  72 #define QED_WFQ_UNIT    100
  73
  74 #define QED_WID_SIZE            (1024)
  75 #define QED_MIN_WIDS            (4)
  76 #define QED_PF_DEMS_SIZE        (4)
  77
  78 /* cau states */
  79 enum qed_coalescing_mode {
  80         QED_COAL_MODE_DISABLE,
  81         QED_COAL_MODE_ENABLE
  82 };
  83
  84 enum qed_nvm_cmd {
  85         QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  86         QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  87         QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  88         QED_GET_MCP_NVM_RESP = 0xFFFFFF00
  89 };
  90
  91 struct qed_eth_cb_ops;
  92 struct qed_dev_info;
  93 union qed_mcp_protocol_stats;
  94 enum qed_mcp_protocol_type;
  95 enum qed_mfw_tlv_type;
  96 union qed_mfw_tlv_data;
  97
  98 /* helpers */
  99 #define QED_MFW_GET_FIELD(name, field) \
 100         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
 101
 102 #define QED_MFW_SET_FIELD(name, field, value)                                  \
 103         do {                                                                   \
 104                 (name)  &= ~(field ## _MASK);          \
 105                 (name)  |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
 106         } while (0)
 107
 108 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
 109 {
 110         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 111                       (cid * QED_PF_DEMS_SIZE);
 112
 113         return db_addr;
 114 }
 115
 116 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
 117 {
 118         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 119                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 120
 121         return db_addr;
 122 }
 123
 124 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
 125         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
 126          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
 127
 128 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
 129
 130 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 131         (val == (cond1) ? true1 :                     \
 132          (val == (cond2) ? true2 : def))
 133
 134 /* forward */
 135 struct qed_ptt_pool;
 136 struct qed_spq;
 137 struct qed_sb_info;
 138 struct qed_sb_attn_info;
 139 struct qed_cxt_mngr;
 140 struct qed_sb_sp_info;
 141 struct qed_ll2_info;
 142 struct qed_mcp_info;
 143
 144 struct qed_rt_data {
 145         u32     *init_val;
 146         bool    *b_valid;
 147 };
 148
 149 enum qed_tunn_mode {
 150         QED_MODE_L2GENEVE_TUNN,
 151         QED_MODE_IPGENEVE_TUNN,
 152         QED_MODE_L2GRE_TUNN,
 153         QED_MODE_IPGRE_TUNN,
 154         QED_MODE_VXLAN_TUNN,
 155 };
 156
 157 enum qed_tunn_clss {
 158         QED_TUNN_CLSS_MAC_VLAN,
 159         QED_TUNN_CLSS_MAC_VNI,
 160         QED_TUNN_CLSS_INNER_MAC_VLAN,
 161         QED_TUNN_CLSS_INNER_MAC_VNI,
 162         QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 163         MAX_QED_TUNN_CLSS,
 164 };
 165
 166 struct qed_tunn_update_type {
 167         bool b_update_mode;
 168         bool b_mode_enabled;
 169         enum qed_tunn_clss tun_cls;
 170 };
 171
 172 struct qed_tunn_update_udp_port {
 173         bool b_update_port;
 174         u16 port;
 175 };
 176
 177 struct qed_tunnel_info {
 178         struct qed_tunn_update_type vxlan;
 179         struct qed_tunn_update_type l2_geneve;
 180         struct qed_tunn_update_type ip_geneve;
 181         struct qed_tunn_update_type l2_gre;
 182         struct qed_tunn_update_type ip_gre;
 183
 184         struct qed_tunn_update_udp_port vxlan_port;
 185         struct qed_tunn_update_udp_port geneve_port;
 186
 187         bool b_update_rx_cls;
 188         bool b_update_tx_cls;
 189 };
 190
 191 struct qed_tunn_start_params {
 192         unsigned long   tunn_mode;
 193         u16             vxlan_udp_port;
 194         u16             geneve_udp_port;
 195         u8              update_vxlan_udp_port;
 196         u8              update_geneve_udp_port;
 197         u8              tunn_clss_vxlan;
 198         u8              tunn_clss_l2geneve;
 199         u8              tunn_clss_ipgeneve;
 200         u8              tunn_clss_l2gre;
 201         u8              tunn_clss_ipgre;
 202 };
 203
 204 struct qed_tunn_update_params {
 205         unsigned long   tunn_mode_update_mask;
 206         unsigned long   tunn_mode;
 207         u16             vxlan_udp_port;
 208         u16             geneve_udp_port;
 209         u8              update_rx_pf_clss;
 210         u8              update_tx_pf_clss;
 211         u8              update_vxlan_udp_port;
 212         u8              update_geneve_udp_port;
 213         u8              tunn_clss_vxlan;
 214         u8              tunn_clss_l2geneve;
 215         u8              tunn_clss_ipgeneve;
 216         u8              tunn_clss_l2gre;
 217         u8              tunn_clss_ipgre;
 218 };
 219
 220 /* The PCI personality is not quite synonymous to protocol ID:
 221  * 1. All personalities need CORE connections
 222  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 223  */
 224 enum qed_pci_personality {
 225         QED_PCI_ETH,
 226         QED_PCI_FCOE,
 227         QED_PCI_ISCSI,
 228         QED_PCI_ETH_ROCE,
 229         QED_PCI_ETH_IWARP,
 230         QED_PCI_ETH_RDMA,
 231         QED_PCI_DEFAULT, /* default in shmem */
 232 };
 233
 234 /* All VFs are symmetric, all counters are PF + all VFs */
 235 struct qed_qm_iids {
 236         u32 cids;
 237         u32 vf_cids;
 238         u32 tids;
 239 };
 240
 241 /* HW / FW resources, output of features supported below, most information
 242  * is received from MFW.
 243  */
 244 enum qed_resources {
 245         QED_SB,
 246         QED_L2_QUEUE,
 247         QED_VPORT,
 248         QED_RSS_ENG,
 249         QED_PQ,
 250         QED_RL,
 251         QED_MAC,
 252         QED_VLAN,
 253         QED_RDMA_CNQ_RAM,
 254         QED_ILT,
 255         QED_LL2_QUEUE,
 256         QED_CMDQS_CQS,
 257         QED_RDMA_STATS_QUEUE,
 258         QED_BDQ,
 259         QED_MAX_RESC,
 260 };
 261
 262 enum QED_FEATURE {
 263         QED_PF_L2_QUE,
 264         QED_VF,
 265         QED_RDMA_CNQ,
 266         QED_ISCSI_CQ,
 267         QED_FCOE_CQ,
 268         QED_VF_L2_QUE,
 269         QED_MAX_FEATURES,
 270 };
 271
 272 enum QED_PORT_MODE {
 273         QED_PORT_MODE_DE_2X40G,
 274         QED_PORT_MODE_DE_2X50G,
 275         QED_PORT_MODE_DE_1X100G,
 276         QED_PORT_MODE_DE_4X10G_F,
 277         QED_PORT_MODE_DE_4X10G_E,
 278         QED_PORT_MODE_DE_4X20G,
 279         QED_PORT_MODE_DE_1X40G,
 280         QED_PORT_MODE_DE_2X25G,
 281         QED_PORT_MODE_DE_1X25G,
 282         QED_PORT_MODE_DE_4X25G,
 283         QED_PORT_MODE_DE_2X10G,
 284 };
 285
 286 enum qed_dev_cap {
 287         QED_DEV_CAP_ETH,
 288         QED_DEV_CAP_FCOE,
 289         QED_DEV_CAP_ISCSI,
 290         QED_DEV_CAP_ROCE,
 291         QED_DEV_CAP_IWARP,
 292 };
 293
 294 enum qed_wol_support {
 295         QED_WOL_SUPPORT_NONE,
 296         QED_WOL_SUPPORT_PME,
 297 };
 298
 299 enum qed_db_rec_exec {
 300         DB_REC_DRY_RUN,
 301         DB_REC_REAL_DEAL,
 302         DB_REC_ONCE,
 303 };
 304
 305 struct qed_hw_info {
 306         /* PCI personality */
 307         enum qed_pci_personality personality;
 308 #define QED_IS_RDMA_PERSONALITY(dev)                        \
 309         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE ||  \
 310          (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 311          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 312 #define QED_IS_ROCE_PERSONALITY(dev)                       \
 313         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
 314          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 315 #define QED_IS_IWARP_PERSONALITY(dev)                       \
 316         ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 317          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 318 #define QED_IS_L2_PERSONALITY(dev)                    \
 319         ((dev)->hw_info.personality == QED_PCI_ETH || \
 320          QED_IS_RDMA_PERSONALITY(dev))
 321 #define QED_IS_FCOE_PERSONALITY(dev) \
 322         ((dev)->hw_info.personality == QED_PCI_FCOE)
 323 #define QED_IS_ISCSI_PERSONALITY(dev) \
 324         ((dev)->hw_info.personality == QED_PCI_ISCSI)
 325
 326         /* Resource Allocation scheme results */
 327         u32                             resc_start[QED_MAX_RESC];
 328         u32                             resc_num[QED_MAX_RESC];
 329         u32                             feat_num[QED_MAX_FEATURES];
 330
 331 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 332 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 333 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 334                                  RESC_NUM(_p_hwfn, resc))
 335 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 336
 337         /* Amount of traffic classes HW supports */
 338         u8 num_hw_tc;
 339
 340         /* Amount of TCs which should be active according to DCBx or upper
 341          * layer driver configuration.
 342          */
 343         u8 num_active_tc;
 344         u8                              offload_tc;
 345         bool                            offload_tc_set;
 346
 347         bool                            multi_tc_roce_en;
 348 #define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))
 349
 350         u32                             concrete_fid;
 351         u16                             opaque_fid;
 352         u16                             ovlan;
 353         u32                             part_num[4];
 354
 355         unsigned char                   hw_mac_addr[ETH_ALEN];
 356         u64                             node_wwn;
 357         u64                             port_wwn;
 358
 359         u16                             num_fcoe_conns;
 360
 361         struct qed_igu_info             *p_igu_info;
 362
 363         u32                             port_mode;
 364         u32                             hw_mode;
 365         unsigned long           device_capabilities;
 366         u16                             mtu;
 367
 368         enum qed_wol_support b_wol_support;
 369 };
 370
 371 /* maximun size of read/write commands (HW limit) */
 372 #define DMAE_MAX_RW_SIZE        0x2000
 373
 374 struct qed_dmae_info {
 375         /* Mutex for synchronizing access to functions */
 376         struct mutex    mutex;
 377
 378         u8              channel;
 379
 380         dma_addr_t      completion_word_phys_addr;
 381
 382         /* The memory location where the DMAE writes the completion
 383          * value when an operation is finished on this context.
 384          */
 385         u32             *p_completion_word;
 386
 387         dma_addr_t      intermediate_buffer_phys_addr;
 388
 389         /* An intermediate buffer for DMAE operations that use virtual
 390          * addresses - data is DMA'd to/from this buffer and then
 391          * memcpy'd to/from the virtual address
 392          */
 393         u32             *p_intermediate_buffer;
 394
 395         dma_addr_t      dmae_cmd_phys_addr;
 396         struct dmae_cmd *p_dmae_cmd;
 397 };
 398
 399 struct qed_wfq_data {
 400         /* when feature is configured for at least 1 vport */
 401         u32     min_speed;
 402         bool    configured;
 403 };
 404
 405 struct qed_qm_info {
 406         struct init_qm_pq_params        *qm_pq_params;
 407         struct init_qm_vport_params     *qm_vport_params;
 408         struct init_qm_port_params      *qm_port_params;
 409         u16                             start_pq;
 410         u8                              start_vport;
 411         u16                              pure_lb_pq;
 412         u16                             first_ofld_pq;
 413         u16                             first_llt_pq;
 414         u16                             pure_ack_pq;
 415         u16                             ooo_pq;
 416         u16                             first_vf_pq;
 417         u16                             first_mcos_pq;
 418         u16                             first_rl_pq;
 419         u16                             num_pqs;
 420         u16                             num_vf_pqs;
 421         u8                              num_vports;
 422         u8                              max_phys_tcs_per_port;
 423         u8                              ooo_tc;
 424         bool                            pf_rl_en;
 425         bool                            pf_wfq_en;
 426         bool                            vport_rl_en;
 427         bool                            vport_wfq_en;
 428         u8                              pf_wfq;
 429         u32                             pf_rl;
 430         struct qed_wfq_data             *wfq_data;
 431         u8 num_pf_rls;
 432 };
 433
 434 #define QED_OVERFLOW_BIT        1
 435
 436 struct qed_db_recovery_info {
 437         struct list_head list;
 438
 439         /* Lock to protect the doorbell recovery mechanism list */
 440         spinlock_t lock;
 441         bool dorq_attn;
 442         u32 db_recovery_counter;
 443         unsigned long overflow;
 444 };
 445
 446 struct storm_stats {
 447         u32     address;
 448         u32     len;
 449 };
 450
 451 struct qed_storm_stats {
 452         struct storm_stats mstats;
 453         struct storm_stats pstats;
 454         struct storm_stats tstats;
 455         struct storm_stats ustats;
 456 };
 457
 458 struct qed_fw_data {
 459         struct fw_ver_info      *fw_ver_info;
 460         const u8                *modes_tree_buf;
 461         union init_op           *init_ops;
 462         const u32               *arr_data;
 463         u32                     init_ops_size;
 464 };
 465
 466 enum qed_mf_mode_bit {
 467         /* Supports PF-classification based on tag */
 468         QED_MF_OVLAN_CLSS,
 469
 470         /* Supports PF-classification based on MAC */
 471         QED_MF_LLH_MAC_CLSS,
 472
 473         /* Supports PF-classification based on protocol type */
 474         QED_MF_LLH_PROTO_CLSS,
 475
 476         /* Requires a default PF to be set */
 477         QED_MF_NEED_DEF_PF,
 478
 479         /* Allow LL2 to multicast/broadcast */
 480         QED_MF_LL2_NON_UNICAST,
 481
 482         /* Allow Cross-PF [& child VFs] Tx-switching */
 483         QED_MF_INTER_PF_SWITCH,
 484
 485         /* Unified Fabtic Port support enabled */
 486         QED_MF_UFP_SPECIFIC,
 487
 488         /* Disable Accelerated Receive Flow Steering (aRFS) */
 489         QED_MF_DISABLE_ARFS,
 490
 491         /* Use vlan for steering */
 492         QED_MF_8021Q_TAGGING,
 493
 494         /* Use stag for steering */
 495         QED_MF_8021AD_TAGGING,
 496
 497         /* Allow DSCP to TC mapping */
 498         QED_MF_DSCP_TO_TC_MAP,
 499 };
 500
 501 enum qed_ufp_mode {
 502         QED_UFP_MODE_ETS,
 503         QED_UFP_MODE_VNIC_BW,
 504         QED_UFP_MODE_UNKNOWN
 505 };
 506
 507 enum qed_ufp_pri_type {
 508         QED_UFP_PRI_OS,
 509         QED_UFP_PRI_VNIC,
 510         QED_UFP_PRI_UNKNOWN
 511 };
 512
 513 struct qed_ufp_info {
 514         enum qed_ufp_pri_type pri_type;
 515         enum qed_ufp_mode mode;
 516         u8 tc;
 517 };
 518
 519 enum BAR_ID {
 520         BAR_ID_0,               /* used for GRC */
 521         BAR_ID_1                /* Used for doorbells */
 522 };
 523
 524 struct qed_nvm_image_info {
 525         u32 num_images;
 526         struct bist_nvm_image_att *image_att;
 527         bool valid;
 528 };
 529
 530 #define DRV_MODULE_VERSION                    \
 531         __stringify(QED_MAJOR_VERSION) "."    \
 532         __stringify(QED_MINOR_VERSION) "."    \
 533         __stringify(QED_REVISION_VERSION) "." \
 534         __stringify(QED_ENGINEERING_VERSION)
 535
 536 struct qed_simd_fp_handler {
 537         void    *token;
 538         void    (*func)(void *);
 539 };
 540
 541 enum qed_slowpath_wq_flag {
 542         QED_SLOWPATH_MFW_TLV_REQ,
 543         QED_SLOWPATH_PERIODIC_DB_REC,
 544 };
 545
 546 struct qed_hwfn {
 547         struct qed_dev                  *cdev;
 548         u8                              my_id;          /* ID inside the PF */
 549 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 550         u8                              rel_pf_id;      /* Relative to engine*/
 551         u8                              abs_pf_id;
 552 #define QED_PATH_ID(_p_hwfn) \
 553         (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 554         u8                              port_id;
 555         bool                            b_active;
 556
 557         u32                             dp_module;
 558         u8                              dp_level;
 559         char                            name[NAME_SIZE];
 560
 561         bool                            hw_init_done;
 562
 563         u8                              num_funcs_on_engine;
 564         u8 enabled_func_idx;
 565
 566         /* BAR access */
 567         void __iomem                    *regview;
 568         void __iomem                    *doorbells;
 569         u64                             db_phys_addr;
 570         unsigned long                   db_size;
 571
 572         /* PTT pool */
 573         struct qed_ptt_pool             *p_ptt_pool;
 574
 575         /* HW info */
 576         struct qed_hw_info              hw_info;
 577
 578         /* rt_array (for init-tool) */
 579         struct qed_rt_data              rt_data;
 580
 581         /* SPQ */
 582         struct qed_spq                  *p_spq;
 583
 584         /* EQ */
 585         struct qed_eq                   *p_eq;
 586
 587         /* Consolidate Q*/
 588         struct qed_consq                *p_consq;
 589
 590         /* Slow-Path definitions */
 591         struct tasklet_struct           *sp_dpc;
 592         bool                            b_sp_dpc_enabled;
 593
 594         struct qed_ptt                  *p_main_ptt;
 595         struct qed_ptt                  *p_dpc_ptt;
 596
 597         /* PTP will be used only by the leading function.
 598          * Usage of all PTP-apis should be synchronized as result.
 599          */
 600         struct qed_ptt *p_ptp_ptt;
 601
 602         struct qed_sb_sp_info           *p_sp_sb;
 603         struct qed_sb_attn_info         *p_sb_attn;
 604
 605         /* Protocol related */
 606         bool                            using_ll2;
 607         struct qed_ll2_info             *p_ll2_info;
 608         struct qed_ooo_info             *p_ooo_info;
 609         struct qed_rdma_info            *p_rdma_info;
 610         struct qed_iscsi_info           *p_iscsi_info;
 611         struct qed_fcoe_info            *p_fcoe_info;
 612         struct qed_pf_params            pf_params;
 613
 614         bool b_rdma_enabled_in_prs;
 615         u32 rdma_prs_search_reg;
 616
 617         struct qed_cxt_mngr             *p_cxt_mngr;
 618
 619         /* Flag indicating whether interrupts are enabled or not*/
 620         bool                            b_int_enabled;
 621         bool                            b_int_requested;
 622
 623         /* True if the driver requests for the link */
 624         bool                            b_drv_link_init;
 625
 626         struct qed_vf_iov               *vf_iov_info;
 627         struct qed_pf_iov               *pf_iov_info;
 628         struct qed_mcp_info             *mcp_info;
 629
 630         struct qed_dcbx_info            *p_dcbx_info;
 631
 632         struct qed_ufp_info             ufp_info;
 633
 634         struct qed_dmae_info            dmae_info;
 635
 636         /* QM init */
 637         struct qed_qm_info              qm_info;
 638         struct qed_storm_stats          storm_stats;
 639
 640         /* Buffer for unzipping firmware data */
 641         void                            *unzip_buf;
 642
 643         struct dbg_tools_data           dbg_info;
 644         void                            *dbg_user_info;
 645
 646         /* PWM region specific data */
 647         u16                             wid_count;
 648         u32                             dpi_size;
 649         u32                             dpi_count;
 650
 651         /* This is used to calculate the doorbell address */
 652         u32 dpi_start_offset;
 653
 654         /* If one of the following is set then EDPM shouldn't be used */
 655         u8 dcbx_no_edpm;
 656         u8 db_bar_no_edpm;
 657
 658         /* L2-related */
 659         struct qed_l2_info *p_l2_info;
 660
 661         /* Mechanism for recovering from doorbell drop */
 662         struct qed_db_recovery_info db_recovery_info;
 663
 664         /* Nvm images number and attributes */
 665         struct qed_nvm_image_info nvm_info;
 666
 667         struct qed_ptt *p_arfs_ptt;
 668
 669         struct qed_simd_fp_handler      simd_proto_handler[64];
 670
 671 #ifdef CONFIG_QED_SRIOV
 672         struct workqueue_struct *iov_wq;
 673         struct delayed_work iov_task;
 674         unsigned long iov_task_flags;
 675 #endif
 676         struct z_stream_s *stream;
 677         bool slowpath_wq_active;
 678         struct workqueue_struct *slowpath_wq;
 679         struct delayed_work slowpath_task;
 680         unsigned long slowpath_task_flags;
 681         u32 periodic_db_rec_count;
 682 };
 683
 684 struct pci_params {
 685         int             pm_cap;
 686
 687         unsigned long   mem_start;
 688         unsigned long   mem_end;
 689         unsigned int    irq;
 690         u8              pf_num;
 691 };
 692
 693 struct qed_int_param {
 694         u32     int_mode;
 695         u8      num_vectors;
 696         u8      min_msix_cnt; /* for minimal functionality */
 697 };
 698
 699 struct qed_int_params {
 700         struct qed_int_param    in;
 701         struct qed_int_param    out;
 702         struct msix_entry       *msix_table;
 703         bool                    fp_initialized;
 704         u8                      fp_msix_base;
 705         u8                      fp_msix_cnt;
 706         u8                      rdma_msix_base;
 707         u8                      rdma_msix_cnt;
 708 };
 709
 710 struct qed_dbg_feature {
 711         struct dentry *dentry;
 712         u8 *dump_buf;
 713         u32 buf_size;
 714         u32 dumped_dwords;
 715 };
 716
 717 struct qed_dbg_params {
 718         struct qed_dbg_feature features[DBG_FEATURE_NUM];
 719         u8 engine_for_debug;
 720         bool print_data;
 721 };
 722
 723 struct qed_dev {
 724         u32     dp_module;
 725         u8      dp_level;
 726         char    name[NAME_SIZE];
 727
 728         enum    qed_dev_type type;
 729 /* Translate type/revision combo into the proper conditions */
 730 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 731 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 732                                  CHIP_REV_IS_B0(dev))
 733 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 734 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 735
 736         u16     vendor_id;
 737         u16     device_id;
 738 #define QED_DEV_ID_MASK         0xff00
 739 #define QED_DEV_ID_MASK_BB      0x1600
 740 #define QED_DEV_ID_MASK_AH      0x8000
 741
 742         u16     chip_num;
 743 #define CHIP_NUM_MASK                   0xffff
 744 #define CHIP_NUM_SHIFT                  16
 745
 746         u16     chip_rev;
 747 #define CHIP_REV_MASK                   0xf
 748 #define CHIP_REV_SHIFT                  12
 749 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 750
 751         u16                             chip_metal;
 752 #define CHIP_METAL_MASK                 0xff
 753 #define CHIP_METAL_SHIFT                4
 754
 755         u16                             chip_bond_id;
 756 #define CHIP_BOND_ID_MASK               0xf
 757 #define CHIP_BOND_ID_SHIFT              0
 758
 759         u8                              num_engines;
 760         u8                              num_ports;
 761         u8                              num_ports_in_engine;
 762         u8                              num_funcs_in_port;
 763
 764         u8                              path_id;
 765
 766         unsigned long                   mf_bits;
 767
 768         int                             pcie_width;
 769         int                             pcie_speed;
 770
 771         /* Add MF related configuration */
 772         u8                              mcp_rev;
 773         u8                              boot_mode;
 774
 775         /* WoL related configurations */
 776         u8 wol_config;
 777         u8 wol_mac[ETH_ALEN];
 778
 779         u32                             int_mode;
 780         enum qed_coalescing_mode        int_coalescing_mode;
 781         u16                             rx_coalesce_usecs;
 782         u16                             tx_coalesce_usecs;
 783
 784         /* Start Bar offset of first hwfn */
 785         void __iomem                    *regview;
 786         void __iomem                    *doorbells;
 787         u64                             db_phys_addr;
 788         unsigned long                   db_size;
 789
 790         /* PCI */
 791         u8                              cache_shift;
 792
 793         /* Init */
 794         const struct iro                *iro_arr;
 795 #define IRO (p_hwfn->cdev->iro_arr)
 796
 797         /* HW functions */
 798         u8                              num_hwfns;
 799         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 800
 801         /* SRIOV */
 802         struct qed_hw_sriov_info *p_iov_info;
 803 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 804         struct qed_tunnel_info          tunnel;
 805         bool                            b_is_vf;
 806         u32                             drv_type;
 807         struct qed_eth_stats            *reset_stats;
 808         struct qed_fw_data              *fw_data;
 809
 810         u32                             mcp_nvm_resp;
 811
 812         /* Recovery */
 813         bool recov_in_prog;
 814
 815         /* Linux specific here */
 816         struct  qede_dev                *edev;
 817         struct  pci_dev                 *pdev;
 818         u32 flags;
 819 #define QED_FLAG_STORAGE_STARTED        (BIT(0))
 820         int                             msg_enable;
 821
 822         struct pci_params               pci_params;
 823
 824         struct qed_int_params           int_params;
 825
 826         u8                              protocol;
 827 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 828 #define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)
 829
 830         /* Callbacks to protocol driver */
 831         union {
 832                 struct qed_common_cb_ops        *common;
 833                 struct qed_eth_cb_ops           *eth;
 834                 struct qed_fcoe_cb_ops          *fcoe;
 835                 struct qed_iscsi_cb_ops         *iscsi;
 836         } protocol_ops;
 837         void                            *ops_cookie;
 838
 839         struct qed_dbg_params           dbg_params;
 840
 841 #ifdef CONFIG_QED_LL2
 842         struct qed_cb_ll2_info          *ll2;
 843         u8                              ll2_mac_address[ETH_ALEN];
 844 #endif
 845         DECLARE_HASHTABLE(connections, 10);
 846         const struct firmware           *firmware;
 847
 848         u32 rdma_max_sge;
 849         u32 rdma_max_inline;
 850         u32 rdma_max_srq_sge;
 851         u16 tunn_feature_mask;
 852 };
 853
 854 #define NUM_OF_VFS(dev)         (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
 855                                                 : MAX_NUM_VFS_K2)
 856 #define NUM_OF_L2_QUEUES(dev)   (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 857                                                 : MAX_NUM_L2_QUEUES_K2)
 858 #define NUM_OF_PORTS(dev)       (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 859                                                 : MAX_NUM_PORTS_K2)
 860 #define NUM_OF_SBS(dev)         (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 861                                                 : MAX_SB_PER_PATH_K2)
 862 #define NUM_OF_ENG_PFS(dev)     (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
 863                                                 : MAX_NUM_PFS_K2)
 864
 865 /**
 866  * @brief qed_concrete_to_sw_fid - get the sw function id from
 867  *        the concrete value.
 868  *
 869  * @param concrete_fid
 870  *
 871  * @return inline u8
 872  */
 873 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 874                                         u32 concrete_fid)
 875 {
 876         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 877         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 878         u8 vf_valid = GET_FIELD(concrete_fid,
 879                                 PXP_CONCRETE_FID_VFVALID);
 880         u8 sw_fid;
 881
 882         if (vf_valid)
 883                 sw_fid = vfid + MAX_NUM_PFS;
 884         else
 885                 sw_fid = pfid;
 886
 887         return sw_fid;
 888 }
 889
 890 #define PKT_LB_TC       9
 891 #define MAX_NUM_VOQS_E4 20
 892
 893 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 894 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
 895                                          struct qed_ptt *p_ptt,
 896                                          u32 min_pf_rate);
 897
 898 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 899 int qed_device_num_engines(struct qed_dev *cdev);
 900 void qed_set_fw_mac_addr(__le16 *fw_msb,
 901                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
 902
 903 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 904
 905 /* Flags for indication of required queues */
 906 #define PQ_FLAGS_RLS    (BIT(0))
 907 #define PQ_FLAGS_MCOS   (BIT(1))
 908 #define PQ_FLAGS_LB     (BIT(2))
 909 #define PQ_FLAGS_OOO    (BIT(3))
 910 #define PQ_FLAGS_ACK    (BIT(4))
 911 #define PQ_FLAGS_OFLD   (BIT(5))
 912 #define PQ_FLAGS_VFS    (BIT(6))
 913 #define PQ_FLAGS_LLT    (BIT(7))
 914 #define PQ_FLAGS_MTC    (BIT(8))
 915
 916 /* physical queue index for cm context intialization */
 917 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
 918 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
 919 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
 920 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
 921 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
 922
 923 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 924
 925 /* doorbell recovery mechanism */
 926 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
 927 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
 928 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
 929
 930 /* Other Linux specific common definitions */
 931 #define DP_NAME(cdev) ((cdev)->name)
 932
 933 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 934                                                 (cdev->regview) + \
 935                                                          (offset))
 936
 937 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 938 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 939 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 940
 941 #define DOORBELL(cdev, db_addr, val)                     \
 942         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 943                                           (cdev->doorbells) + (db_addr)))
 944
 945 #define MFW_PORT(_p_hwfn)       ((_p_hwfn)->abs_pf_id %                   \
 946                                   qed_device_num_ports((_p_hwfn)->cdev))
 947 int qed_device_num_ports(struct qed_dev *cdev);
 948
 949 /* Prototypes */
 950 int qed_fill_dev_info(struct qed_dev *cdev,
 951                       struct qed_dev_info *dev_info);
 952 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
 953 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 954                    u32 input_len, u8 *input_buf,
 955                    u32 max_size, u8 *unzip_buf);
 956 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
 957 void qed_get_protocol_stats(struct qed_dev *cdev,
 958                             enum qed_mcp_protocol_type type,
 959                             union qed_mcp_protocol_stats *stats);
 960 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 961 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
 962 int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
 963
 964 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
 965                           enum qed_mfw_tlv_type type,
 966                           union qed_mfw_tlv_data *tlv_data);
 967
 968 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
 969
 970 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
 971 #endif /* _QED_H */