drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  73                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  74 {
  75         u32 bar_reg = (bar_id == BAR_ID_0 ?
  76                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  77         u32 val;
  78
  79         if (IS_VF(p_hwfn->cdev))
  80                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
  81
  82         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  83         if (val)
  84                 return 1 << (val + 15);
  85
  86         /* Old MFW initialized above registered only conditionally */
  87         if (p_hwfn->cdev->num_hwfns > 1) {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  90                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  91         } else {
  92                 DP_INFO(p_hwfn,
  93                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  94                         return 512 * 1024;
  95         }
  96 }
  97
  98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  99 {
 100         u32 i;
 101
 102         cdev->dp_level = dp_level;
 103         cdev->dp_module = dp_module;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109         }
 110 }
 111
 112 void qed_init_struct(struct qed_dev *cdev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 118
 119                 p_hwfn->cdev = cdev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 mutex_init(&p_hwfn->dmae_info.mutex);
 124         }
 125
 126         /* hwfn 0 is always active */
 127         cdev->hwfns[0].b_active = true;
 128
 129         /* set the default cache alignment to 128 */
 130         cdev->cache_shift = 7;
 131 }
 132
 133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 134 {
 135         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 136
 137         kfree(qm_info->qm_pq_params);
 138         qm_info->qm_pq_params = NULL;
 139         kfree(qm_info->qm_vport_params);
 140         qm_info->qm_vport_params = NULL;
 141         kfree(qm_info->qm_port_params);
 142         qm_info->qm_port_params = NULL;
 143         kfree(qm_info->wfq_data);
 144         qm_info->wfq_data = NULL;
 145 }
 146
 147 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
 148 {
 149         kfree(p_hwfn->dbg_user_info);
 150         p_hwfn->dbg_user_info = NULL;
 151 }
 152
 153 void qed_resc_free(struct qed_dev *cdev)
 154 {
 155         int i;
 156
 157         if (IS_VF(cdev)) {
 158                 for_each_hwfn(cdev, i)
 159                         qed_l2_free(&cdev->hwfns[i]);
 160                 return;
 161         }
 162
 163         kfree(cdev->fw_data);
 164         cdev->fw_data = NULL;
 165
 166         kfree(cdev->reset_stats);
 167         cdev->reset_stats = NULL;
 168
 169         for_each_hwfn(cdev, i) {
 170                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 171
 172                 qed_cxt_mngr_free(p_hwfn);
 173                 qed_qm_info_free(p_hwfn);
 174                 qed_spq_free(p_hwfn);
 175                 qed_eq_free(p_hwfn);
 176                 qed_consq_free(p_hwfn);
 177                 qed_int_free(p_hwfn);
 178 #ifdef CONFIG_QED_LL2
 179                 qed_ll2_free(p_hwfn);
 180 #endif
 181                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 182                         qed_fcoe_free(p_hwfn);
 183
 184                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 185                         qed_iscsi_free(p_hwfn);
 186                         qed_ooo_free(p_hwfn);
 187                 }
 188
 189                 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
 190                         qed_rdma_info_free(p_hwfn);
 191
 192                 qed_iov_free(p_hwfn);
 193                 qed_l2_free(p_hwfn);
 194                 qed_dmae_info_free(p_hwfn);
 195                 qed_dcbx_info_free(p_hwfn);
 196                 qed_dbg_user_data_free(p_hwfn);
 197         }
 198 }
 199
 200 /******************** QM initialization *******************/
 201 #define ACTIVE_TCS_BMAP 0x9f
 202 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 203
 204 /* determines the physical queue flags for a given PF. */
 205 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 206 {
 207         u32 flags;
 208
 209         /* common flags */
 210         flags = PQ_FLAGS_LB;
 211
 212         /* feature flags */
 213         if (IS_QED_SRIOV(p_hwfn->cdev))
 214                 flags |= PQ_FLAGS_VFS;
 215
 216         /* protocol flags */
 217         switch (p_hwfn->hw_info.personality) {
 218         case QED_PCI_ETH:
 219                 flags |= PQ_FLAGS_MCOS;
 220                 break;
 221         case QED_PCI_FCOE:
 222                 flags |= PQ_FLAGS_OFLD;
 223                 break;
 224         case QED_PCI_ISCSI:
 225                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 226                 break;
 227         case QED_PCI_ETH_ROCE:
 228                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 229                 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
 230                         flags |= PQ_FLAGS_MTC;
 231                 break;
 232         case QED_PCI_ETH_IWARP:
 233                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 234                     PQ_FLAGS_OFLD;
 235                 break;
 236         default:
 237                 DP_ERR(p_hwfn,
 238                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 239                 return 0;
 240         }
 241
 242         return flags;
 243 }
 244
 245 /* Getters for resource amounts necessary for qm initialization */
 246 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 247 {
 248         return p_hwfn->hw_info.num_hw_tc;
 249 }
 250
 251 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 252 {
 253         return IS_QED_SRIOV(p_hwfn->cdev) ?
 254                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 255 }
 256
 257 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
 258 {
 259         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 260
 261         if (!(PQ_FLAGS_MTC & pq_flags))
 262                 return 1;
 263
 264         return qed_init_qm_get_num_tcs(p_hwfn);
 265 }
 266
 267 #define NUM_DEFAULT_RLS 1
 268
 269 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 270 {
 271         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 272
 273         /* num RLs can't exceed resource amount of rls or vports */
 274         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 275                                  RESC_NUM(p_hwfn, QED_VPORT));
 276
 277         /* Make sure after we reserve there's something left */
 278         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 279                 return 0;
 280
 281         /* subtract rls necessary for VFs and one default one for the PF */
 282         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 283
 284         return num_pf_rls;
 285 }
 286
 287 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 288 {
 289         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 290
 291         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 292         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 293                qed_init_qm_get_num_pf_rls(p_hwfn) +
 294                (!!(PQ_FLAGS_VFS & pq_flags)) *
 295                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 296 }
 297
 298 /* calc amount of PQs according to the requested flags */
 299 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 300 {
 301         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 302
 303         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 304                qed_init_qm_get_num_pf_rls(p_hwfn) +
 305                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 306                qed_init_qm_get_num_tcs(p_hwfn) +
 307                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 308                (!!(PQ_FLAGS_ACK & pq_flags)) +
 309                (!!(PQ_FLAGS_OFLD & pq_flags)) *
 310                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 311                (!!(PQ_FLAGS_LLT & pq_flags)) *
 312                qed_init_qm_get_num_mtc_tcs(p_hwfn) +
 313                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 314 }
 315
 316 /* initialize the top level QM params */
 317 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 318 {
 319         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 320         bool four_port;
 321
 322         /* pq and vport bases for this PF */
 323         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 324         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 325
 326         /* rate limiting and weighted fair queueing are always enabled */
 327         qm_info->vport_rl_en = true;
 328         qm_info->vport_wfq_en = true;
 329
 330         /* TC config is different for AH 4 port */
 331         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 332
 333         /* in AH 4 port we have fewer TCs per port */
 334         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 335                                                      NUM_OF_PHYS_TCS;
 336
 337         /* unless MFW indicated otherwise, ooo_tc == 3 for
 338          * AH 4-port and 4 otherwise.
 339          */
 340         if (!qm_info->ooo_tc)
 341                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 342                                               DCBX_TCP_OOO_TC;
 343 }
 344
 345 /* initialize qm vport params */
 346 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 347 {
 348         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 349         u8 i;
 350
 351         /* all vports participate in weighted fair queueing */
 352         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 353                 qm_info->qm_vport_params[i].vport_wfq = 1;
 354 }
 355
 356 /* initialize qm port params */
 357 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 358 {
 359         /* Initialize qm port parameters */
 360         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 361
 362         /* indicate how ooo and high pri traffic is dealt with */
 363         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 364                           ACTIVE_TCS_BMAP_4PORT_K2 :
 365                           ACTIVE_TCS_BMAP;
 366
 367         for (i = 0; i < num_ports; i++) {
 368                 struct init_qm_port_params *p_qm_port =
 369                     &p_hwfn->qm_info.qm_port_params[i];
 370
 371                 p_qm_port->active = 1;
 372                 p_qm_port->active_phys_tcs = active_phys_tcs;
 373                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 374                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 375         }
 376 }
 377
 378 /* Reset the params which must be reset for qm init. QM init may be called as
 379  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 380  * params may be affected by the init but would simply recalculate to the same
 381  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 382  * affected as these amounts stay the same.
 383  */
 384 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 385 {
 386         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 387
 388         qm_info->num_pqs = 0;
 389         qm_info->num_vports = 0;
 390         qm_info->num_pf_rls = 0;
 391         qm_info->num_vf_pqs = 0;
 392         qm_info->first_vf_pq = 0;
 393         qm_info->first_mcos_pq = 0;
 394         qm_info->first_rl_pq = 0;
 395 }
 396
 397 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 398 {
 399         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 400
 401         qm_info->num_vports++;
 402
 403         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 404                 DP_ERR(p_hwfn,
 405                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 406                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 407 }
 408
 409 /* initialize a single pq and manage qm_info resources accounting.
 410  * The pq_init_flags param determines whether the PQ is rate limited
 411  * (for VF or PF) and whether a new vport is allocated to the pq or not
 412  * (i.e. vport will be shared).
 413  */
 414
 415 /* flags for pq init */
 416 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 417 #define PQ_INIT_PF_RL           (1 << 1)
 418 #define PQ_INIT_VF_RL           (1 << 2)
 419
 420 /* defines for pq init */
 421 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 422 #define PQ_INIT_DEFAULT_TC              0
 423
 424 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
 425 {
 426         p_info->offload_tc = tc;
 427         p_info->offload_tc_set = true;
 428 }
 429
 430 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
 431 {
 432         return p_hwfn->hw_info.offload_tc_set;
 433 }
 434
 435 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
 436 {
 437         if (qed_is_offload_tc_set(p_hwfn))
 438                 return p_hwfn->hw_info.offload_tc;
 439
 440         return PQ_INIT_DEFAULT_TC;
 441 }
 442
 443 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 444                            struct qed_qm_info *qm_info,
 445                            u8 tc, u32 pq_init_flags)
 446 {
 447         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 448
 449         if (pq_idx > max_pq)
 450                 DP_ERR(p_hwfn,
 451                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 452
 453         /* init pq params */
 454         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 455         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 456             qm_info->num_vports;
 457         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 458         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 459         qm_info->qm_pq_params[pq_idx].rl_valid =
 460             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 461
 462         /* qm params accounting */
 463         qm_info->num_pqs++;
 464         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 465                 qm_info->num_vports++;
 466
 467         if (pq_init_flags & PQ_INIT_PF_RL)
 468                 qm_info->num_pf_rls++;
 469
 470         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 471                 DP_ERR(p_hwfn,
 472                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 473                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 474
 475         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 476                 DP_ERR(p_hwfn,
 477                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 478                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 479 }
 480
 481 /* get pq index according to PQ_FLAGS */
 482 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 483                                            u32 pq_flags)
 484 {
 485         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 486
 487         /* Can't have multiple flags set here */
 488         if (bitmap_weight((unsigned long *)&pq_flags,
 489                           sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
 490                 DP_ERR(p_hwfn, "requested multiple pq flags 0x%x\n", pq_flags);
 491                 goto err;
 492         }
 493
 494         if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
 495                 DP_ERR(p_hwfn, "pq flag 0x%x is not set\n", pq_flags);
 496                 goto err;
 497         }
 498
 499         switch (pq_flags) {
 500         case PQ_FLAGS_RLS:
 501                 return &qm_info->first_rl_pq;
 502         case PQ_FLAGS_MCOS:
 503                 return &qm_info->first_mcos_pq;
 504         case PQ_FLAGS_LB:
 505                 return &qm_info->pure_lb_pq;
 506         case PQ_FLAGS_OOO:
 507                 return &qm_info->ooo_pq;
 508         case PQ_FLAGS_ACK:
 509                 return &qm_info->pure_ack_pq;
 510         case PQ_FLAGS_OFLD:
 511                 return &qm_info->first_ofld_pq;
 512         case PQ_FLAGS_LLT:
 513                 return &qm_info->first_llt_pq;
 514         case PQ_FLAGS_VFS:
 515                 return &qm_info->first_vf_pq;
 516         default:
 517                 goto err;
 518         }
 519
 520 err:
 521         return &qm_info->start_pq;
 522 }
 523
 524 /* save pq index in qm info */
 525 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 526                                 u32 pq_flags, u16 pq_val)
 527 {
 528         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 529
 530         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 531 }
 532
 533 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 534 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 535 {
 536         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 537
 538         return *base_pq_idx + CM_TX_PQ_BASE;
 539 }
 540
 541 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 542 {
 543         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 544
 545         if (max_tc == 0) {
 546                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 547                        PQ_FLAGS_MCOS);
 548                 return p_hwfn->qm_info.start_pq;
 549         }
 550
 551         if (tc > max_tc)
 552                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 553
 554         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
 555 }
 556
 557 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 558 {
 559         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 560
 561         if (max_vf == 0) {
 562                 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
 563                        PQ_FLAGS_VFS);
 564                 return p_hwfn->qm_info.start_pq;
 565         }
 566
 567         if (vf > max_vf)
 568                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 569
 570         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
 571 }
 572
 573 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 574 {
 575         u16 first_ofld_pq, pq_offset;
 576
 577         first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
 578         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 579                     tc : PQ_INIT_DEFAULT_TC;
 580
 581         return first_ofld_pq + pq_offset;
 582 }
 583
 584 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
 585 {
 586         u16 first_llt_pq, pq_offset;
 587
 588         first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
 589         pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
 590                     tc : PQ_INIT_DEFAULT_TC;
 591
 592         return first_llt_pq + pq_offset;
 593 }
 594
 595 /* Functions for creating specific types of pqs */
 596 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 597 {
 598         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 599
 600         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 601                 return;
 602
 603         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 604         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 605 }
 606
 607 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 608 {
 609         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 610
 611         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 612                 return;
 613
 614         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 615         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 616 }
 617
 618 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 619 {
 620         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 621
 622         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 623                 return;
 624
 625         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 626         qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 627                        PQ_INIT_SHARE_VPORT);
 628 }
 629
 630 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
 631 {
 632         u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
 633         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 634         u8 tc;
 635
 636         /* override pq's TC if offload TC is set */
 637         for (tc = 0; tc < num_tcs; tc++)
 638                 qed_init_qm_pq(p_hwfn, qm_info,
 639                                qed_is_offload_tc_set(p_hwfn) ?
 640                                p_hwfn->hw_info.offload_tc : tc,
 641                                PQ_INIT_SHARE_VPORT);
 642 }
 643
 644 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 645 {
 646         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 647
 648         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 649                 return;
 650
 651         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 652         qed_init_qm_mtc_pqs(p_hwfn);
 653 }
 654
 655 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 656 {
 657         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 658
 659         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 660                 return;
 661
 662         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 663         qed_init_qm_mtc_pqs(p_hwfn);
 664 }
 665
 666 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 667 {
 668         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 669         u8 tc_idx;
 670
 671         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 672                 return;
 673
 674         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 675         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 676                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 677 }
 678
 679 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 680 {
 681         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 682         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 683
 684         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 685                 return;
 686
 687         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 688         qm_info->num_vf_pqs = num_vfs;
 689         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 690                 qed_init_qm_pq(p_hwfn,
 691                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 692 }
 693
 694 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 695 {
 696         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 697         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 698
 699         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 700                 return;
 701
 702         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 703         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 704                 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
 705                                PQ_INIT_PF_RL);
 706 }
 707
 708 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 709 {
 710         /* rate limited pqs, must come first (FW assumption) */
 711         qed_init_qm_rl_pqs(p_hwfn);
 712
 713         /* pqs for multi cos */
 714         qed_init_qm_mcos_pqs(p_hwfn);
 715
 716         /* pure loopback pq */
 717         qed_init_qm_lb_pq(p_hwfn);
 718
 719         /* out of order pq */
 720         qed_init_qm_ooo_pq(p_hwfn);
 721
 722         /* pure ack pq */
 723         qed_init_qm_pure_ack_pq(p_hwfn);
 724
 725         /* pq for offloaded protocol */
 726         qed_init_qm_offload_pq(p_hwfn);
 727
 728         /* low latency pq */
 729         qed_init_qm_low_latency_pq(p_hwfn);
 730
 731         /* done sharing vports */
 732         qed_init_qm_advance_vport(p_hwfn);
 733
 734         /* pqs for vfs */
 735         qed_init_qm_vf_pqs(p_hwfn);
 736 }
 737
 738 /* compare values of getters against resources amounts */
 739 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 740 {
 741         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 742                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 743                 return -EINVAL;
 744         }
 745
 746         if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
 747                 return 0;
 748
 749         if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
 750                 p_hwfn->hw_info.multi_tc_roce_en = 0;
 751                 DP_NOTICE(p_hwfn,
 752                           "multi-tc roce was disabled to reduce requested amount of pqs\n");
 753                 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
 754                         return 0;
 755         }
 756
 757         DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 758         return -EINVAL;
 759 }
 760
 761 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 762 {
 763         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 764         struct init_qm_vport_params *vport;
 765         struct init_qm_port_params *port;
 766         struct init_qm_pq_params *pq;
 767         int i, tc;
 768
 769         /* top level params */
 770         DP_VERBOSE(p_hwfn,
 771                    NETIF_MSG_HW,
 772                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
 773                    qm_info->start_pq,
 774                    qm_info->start_vport,
 775                    qm_info->pure_lb_pq,
 776                    qm_info->first_ofld_pq,
 777                    qm_info->first_llt_pq,
 778                    qm_info->pure_ack_pq);
 779         DP_VERBOSE(p_hwfn,
 780                    NETIF_MSG_HW,
 781                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 782                    qm_info->ooo_pq,
 783                    qm_info->first_vf_pq,
 784                    qm_info->num_pqs,
 785                    qm_info->num_vf_pqs,
 786                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 787         DP_VERBOSE(p_hwfn,
 788                    NETIF_MSG_HW,
 789                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 790                    qm_info->pf_rl_en,
 791                    qm_info->pf_wfq_en,
 792                    qm_info->vport_rl_en,
 793                    qm_info->vport_wfq_en,
 794                    qm_info->pf_wfq,
 795                    qm_info->pf_rl,
 796                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 797
 798         /* port table */
 799         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 800                 port = &(qm_info->qm_port_params[i]);
 801                 DP_VERBOSE(p_hwfn,
 802                            NETIF_MSG_HW,
 803                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 804                            i,
 805                            port->active,
 806                            port->active_phys_tcs,
 807                            port->num_pbf_cmd_lines,
 808                            port->num_btb_blocks, port->reserved);
 809         }
 810
 811         /* vport table */
 812         for (i = 0; i < qm_info->num_vports; i++) {
 813                 vport = &(qm_info->qm_vport_params[i]);
 814                 DP_VERBOSE(p_hwfn,
 815                            NETIF_MSG_HW,
 816                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 817                            qm_info->start_vport + i,
 818                            vport->vport_rl, vport->vport_wfq);
 819                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 820                         DP_VERBOSE(p_hwfn,
 821                                    NETIF_MSG_HW,
 822                                    "%d ", vport->first_tx_pq_id[tc]);
 823                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 824         }
 825
 826         /* pq table */
 827         for (i = 0; i < qm_info->num_pqs; i++) {
 828                 pq = &(qm_info->qm_pq_params[i]);
 829                 DP_VERBOSE(p_hwfn,
 830                            NETIF_MSG_HW,
 831                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 832                            qm_info->start_pq + i,
 833                            pq->port_id,
 834                            pq->vport_id,
 835                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 836         }
 837 }
 838
 839 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 840 {
 841         /* reset params required for init run */
 842         qed_init_qm_reset_params(p_hwfn);
 843
 844         /* init QM top level params */
 845         qed_init_qm_params(p_hwfn);
 846
 847         /* init QM port params */
 848         qed_init_qm_port_params(p_hwfn);
 849
 850         /* init QM vport params */
 851         qed_init_qm_vport_params(p_hwfn);
 852
 853         /* init QM physical queue params */
 854         qed_init_qm_pq_params(p_hwfn);
 855
 856         /* display all that init */
 857         qed_dp_init_qm_params(p_hwfn);
 858 }
 859
 860 /* This function reconfigures the QM pf on the fly.
 861  * For this purpose we:
 862  * 1. reconfigure the QM database
 863  * 2. set new values to runtime array
 864  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 865  * 4. activate init tool in QM_PF stage
 866  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 867  */
 868 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 869 {
 870         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 871         bool b_rc;
 872         int rc;
 873
 874         /* initialize qed's qm data structure */
 875         qed_init_qm_info(p_hwfn);
 876
 877         /* stop PF's qm queues */
 878         spin_lock_bh(&qm_lock);
 879         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 880                                     qm_info->start_pq, qm_info->num_pqs);
 881         spin_unlock_bh(&qm_lock);
 882         if (!b_rc)
 883                 return -EINVAL;
 884
 885         /* clear the QM_PF runtime phase leftovers from previous init */
 886         qed_init_clear_rt_data(p_hwfn);
 887
 888         /* prepare QM portion of runtime array */
 889         qed_qm_init_pf(p_hwfn, p_ptt, false);
 890
 891         /* activate init tool on runtime array */
 892         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 893                           p_hwfn->hw_info.hw_mode);
 894         if (rc)
 895                 return rc;
 896
 897         /* start PF's qm queues */
 898         spin_lock_bh(&qm_lock);
 899         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 900                                     qm_info->start_pq, qm_info->num_pqs);
 901         spin_unlock_bh(&qm_lock);
 902         if (!b_rc)
 903                 return -EINVAL;
 904
 905         return 0;
 906 }
 907
 908 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 909 {
 910         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 911         int rc;
 912
 913         rc = qed_init_qm_sanity(p_hwfn);
 914         if (rc)
 915                 goto alloc_err;
 916
 917         qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
 918                                         sizeof(*qm_info->qm_pq_params),
 919                                         GFP_KERNEL);
 920         if (!qm_info->qm_pq_params)
 921                 goto alloc_err;
 922
 923         qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
 924                                            sizeof(*qm_info->qm_vport_params),
 925                                            GFP_KERNEL);
 926         if (!qm_info->qm_vport_params)
 927                 goto alloc_err;
 928
 929         qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
 930                                           sizeof(*qm_info->qm_port_params),
 931                                           GFP_KERNEL);
 932         if (!qm_info->qm_port_params)
 933                 goto alloc_err;
 934
 935         qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
 936                                     sizeof(*qm_info->wfq_data),
 937                                     GFP_KERNEL);
 938         if (!qm_info->wfq_data)
 939                 goto alloc_err;
 940
 941         return 0;
 942
 943 alloc_err:
 944         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 945         qed_qm_info_free(p_hwfn);
 946         return -ENOMEM;
 947 }
 948
 949 int qed_resc_alloc(struct qed_dev *cdev)
 950 {
 951         u32 rdma_tasks, excess_tasks;
 952         u32 line_count;
 953         int i, rc = 0;
 954
 955         if (IS_VF(cdev)) {
 956                 for_each_hwfn(cdev, i) {
 957                         rc = qed_l2_alloc(&cdev->hwfns[i]);
 958                         if (rc)
 959                                 return rc;
 960                 }
 961                 return rc;
 962         }
 963
 964         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 965         if (!cdev->fw_data)
 966                 return -ENOMEM;
 967
 968         for_each_hwfn(cdev, i) {
 969                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 970                 u32 n_eqes, num_cons;
 971
 972                 /* First allocate the context manager structure */
 973                 rc = qed_cxt_mngr_alloc(p_hwfn);
 974                 if (rc)
 975                         goto alloc_err;
 976
 977                 /* Set the HW cid/tid numbers (in the contest manager)
 978                  * Must be done prior to any further computations.
 979                  */
 980                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 981                 if (rc)
 982                         goto alloc_err;
 983
 984                 rc = qed_alloc_qm_data(p_hwfn);
 985                 if (rc)
 986                         goto alloc_err;
 987
 988                 /* init qm info */
 989                 qed_init_qm_info(p_hwfn);
 990
 991                 /* Compute the ILT client partition */
 992                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 993                 if (rc) {
 994                         DP_NOTICE(p_hwfn,
 995                                   "too many ILT lines; re-computing with less lines\n");
 996                         /* In case there are not enough ILT lines we reduce the
 997                          * number of RDMA tasks and re-compute.
 998                          */
 999                         excess_tasks =
1000                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
1001                         if (!excess_tasks)
1002                                 goto alloc_err;
1003
1004                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
1005                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
1006                         if (rc)
1007                                 goto alloc_err;
1008
1009                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
1010                         if (rc) {
1011                                 DP_ERR(p_hwfn,
1012                                        "failed ILT compute. Requested too many lines: %u\n",
1013                                        line_count);
1014
1015                                 goto alloc_err;
1016                         }
1017                 }
1018
1019                 /* CID map / ILT shadow table / T2
1020                  * The talbes sizes are determined by the computations above
1021                  */
1022                 rc = qed_cxt_tables_alloc(p_hwfn);
1023                 if (rc)
1024                         goto alloc_err;
1025
1026                 /* SPQ, must follow ILT because initializes SPQ context */
1027                 rc = qed_spq_alloc(p_hwfn);
1028                 if (rc)
1029                         goto alloc_err;
1030
1031                 /* SP status block allocation */
1032                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
1033                                                          RESERVED_PTT_DPC);
1034
1035                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
1036                 if (rc)
1037                         goto alloc_err;
1038
1039                 rc = qed_iov_alloc(p_hwfn);
1040                 if (rc)
1041                         goto alloc_err;
1042
1043                 /* EQ */
1044                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
1045                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1046                         enum protocol_type rdma_proto;
1047
1048                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
1049                                 rdma_proto = PROTOCOLID_ROCE;
1050                         else
1051                                 rdma_proto = PROTOCOLID_IWARP;
1052
1053                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
1054                                                                rdma_proto,
1055                                                                NULL) * 2;
1056                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
1057                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1058                         num_cons =
1059                             qed_cxt_get_proto_cid_count(p_hwfn,
1060                                                         PROTOCOLID_ISCSI,
1061                                                         NULL);
1062                         n_eqes += 2 * num_cons;
1063                 }
1064
1065                 if (n_eqes > 0xFFFF) {
1066                         DP_ERR(p_hwfn,
1067                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
1068                                n_eqes, 0xFFFF);
1069                         goto alloc_no_mem;
1070                 }
1071
1072                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
1073                 if (rc)
1074                         goto alloc_err;
1075
1076                 rc = qed_consq_alloc(p_hwfn);
1077                 if (rc)
1078                         goto alloc_err;
1079
1080                 rc = qed_l2_alloc(p_hwfn);
1081                 if (rc)
1082                         goto alloc_err;
1083
1084 #ifdef CONFIG_QED_LL2
1085                 if (p_hwfn->using_ll2) {
1086                         rc = qed_ll2_alloc(p_hwfn);
1087                         if (rc)
1088                                 goto alloc_err;
1089                 }
1090 #endif
1091
1092                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1093                         rc = qed_fcoe_alloc(p_hwfn);
1094                         if (rc)
1095                                 goto alloc_err;
1096                 }
1097
1098                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1099                         rc = qed_iscsi_alloc(p_hwfn);
1100                         if (rc)
1101                                 goto alloc_err;
1102                         rc = qed_ooo_alloc(p_hwfn);
1103                         if (rc)
1104                                 goto alloc_err;
1105                 }
1106
1107                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
1108                         rc = qed_rdma_info_alloc(p_hwfn);
1109                         if (rc)
1110                                 goto alloc_err;
1111                 }
1112
1113                 /* DMA info initialization */
1114                 rc = qed_dmae_info_alloc(p_hwfn);
1115                 if (rc)
1116                         goto alloc_err;
1117
1118                 /* DCBX initialization */
1119                 rc = qed_dcbx_info_alloc(p_hwfn);
1120                 if (rc)
1121                         goto alloc_err;
1122
1123                 rc = qed_dbg_alloc_user_data(p_hwfn);
1124                 if (rc)
1125                         goto alloc_err;
1126         }
1127
1128         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1129         if (!cdev->reset_stats)
1130                 goto alloc_no_mem;
1131
1132         return 0;
1133
1134 alloc_no_mem:
1135         rc = -ENOMEM;
1136 alloc_err:
1137         qed_resc_free(cdev);
1138         return rc;
1139 }
1140
1141 void qed_resc_setup(struct qed_dev *cdev)
1142 {
1143         int i;
1144
1145         if (IS_VF(cdev)) {
1146                 for_each_hwfn(cdev, i)
1147                         qed_l2_setup(&cdev->hwfns[i]);
1148                 return;
1149         }
1150
1151         for_each_hwfn(cdev, i) {
1152                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1153
1154                 qed_cxt_mngr_setup(p_hwfn);
1155                 qed_spq_setup(p_hwfn);
1156                 qed_eq_setup(p_hwfn);
1157                 qed_consq_setup(p_hwfn);
1158
1159                 /* Read shadow of current MFW mailbox */
1160                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1161                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1162                        p_hwfn->mcp_info->mfw_mb_cur,
1163                        p_hwfn->mcp_info->mfw_mb_length);
1164
1165                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1166
1167                 qed_l2_setup(p_hwfn);
1168                 qed_iov_setup(p_hwfn);
1169 #ifdef CONFIG_QED_LL2
1170                 if (p_hwfn->using_ll2)
1171                         qed_ll2_setup(p_hwfn);
1172 #endif
1173                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1174                         qed_fcoe_setup(p_hwfn);
1175
1176                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1177                         qed_iscsi_setup(p_hwfn);
1178                         qed_ooo_setup(p_hwfn);
1179                 }
1180         }
1181 }
1182
1183 #define FINAL_CLEANUP_POLL_CNT          (100)
1184 #define FINAL_CLEANUP_POLL_TIME         (10)
1185 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1186                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1187 {
1188         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1189         int rc = -EBUSY;
1190
1191         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1192                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1193
1194         if (is_vf)
1195                 id += 0x10;
1196
1197         command |= X_FINAL_CLEANUP_AGG_INT <<
1198                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1199         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1200         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1201         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1202
1203         /* Make sure notification is not set before initiating final cleanup */
1204         if (REG_RD(p_hwfn, addr)) {
1205                 DP_NOTICE(p_hwfn,
1206                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1207                 REG_WR(p_hwfn, addr, 0);
1208         }
1209
1210         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1211                    "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1212                    id, command);
1213
1214         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1215
1216         /* Poll until completion */
1217         while (!REG_RD(p_hwfn, addr) && count--)
1218                 msleep(FINAL_CLEANUP_POLL_TIME);
1219
1220         if (REG_RD(p_hwfn, addr))
1221                 rc = 0;
1222         else
1223                 DP_NOTICE(p_hwfn,
1224                           "Failed to receive FW final cleanup notification\n");
1225
1226         /* Cleanup afterwards */
1227         REG_WR(p_hwfn, addr, 0);
1228
1229         return rc;
1230 }
1231
1232 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1233 {
1234         int hw_mode = 0;
1235
1236         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1237                 hw_mode |= 1 << MODE_BB;
1238         } else if (QED_IS_AH(p_hwfn->cdev)) {
1239                 hw_mode |= 1 << MODE_K2;
1240         } else {
1241                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1242                           p_hwfn->cdev->type);
1243                 return -EINVAL;
1244         }
1245
1246         switch (p_hwfn->cdev->num_ports_in_engine) {
1247         case 1:
1248                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1249                 break;
1250         case 2:
1251                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1252                 break;
1253         case 4:
1254                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1255                 break;
1256         default:
1257                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1258                           p_hwfn->cdev->num_ports_in_engine);
1259                 return -EINVAL;
1260         }
1261
1262         if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1263                 hw_mode |= 1 << MODE_MF_SD;
1264         else
1265                 hw_mode |= 1 << MODE_MF_SI;
1266
1267         hw_mode |= 1 << MODE_ASIC;
1268
1269         if (p_hwfn->cdev->num_hwfns > 1)
1270                 hw_mode |= 1 << MODE_100G;
1271
1272         p_hwfn->hw_info.hw_mode = hw_mode;
1273
1274         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1275                    "Configuring function for hw_mode: 0x%08x\n",
1276                    p_hwfn->hw_info.hw_mode);
1277
1278         return 0;
1279 }
1280
1281 /* Init run time data for all PFs on an engine. */
1282 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1283 {
1284         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1285         int i, igu_sb_id;
1286
1287         for_each_hwfn(cdev, i) {
1288                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1289                 struct qed_igu_info *p_igu_info;
1290                 struct qed_igu_block *p_block;
1291                 struct cau_sb_entry sb_entry;
1292
1293                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1294
1295                 for (igu_sb_id = 0;
1296                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1297                         p_block = &p_igu_info->entry[igu_sb_id];
1298
1299                         if (!p_block->is_pf)
1300                                 continue;
1301
1302                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1303                                               p_block->function_id, 0, 0);
1304                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1305                                          sb_entry);
1306                 }
1307         }
1308 }
1309
1310 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1311                                      struct qed_ptt *p_ptt)
1312 {
1313         u32 val, wr_mbs, cache_line_size;
1314
1315         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1316         switch (val) {
1317         case 0:
1318                 wr_mbs = 128;
1319                 break;
1320         case 1:
1321                 wr_mbs = 256;
1322                 break;
1323         case 2:
1324                 wr_mbs = 512;
1325                 break;
1326         default:
1327                 DP_INFO(p_hwfn,
1328                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1329                         val);
1330                 return;
1331         }
1332
1333         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1334         switch (cache_line_size) {
1335         case 32:
1336                 val = 0;
1337                 break;
1338         case 64:
1339                 val = 1;
1340                 break;
1341         case 128:
1342                 val = 2;
1343                 break;
1344         case 256:
1345                 val = 3;
1346                 break;
1347         default:
1348                 DP_INFO(p_hwfn,
1349                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1350                         cache_line_size);
1351         }
1352
1353         if (L1_CACHE_BYTES > wr_mbs)
1354                 DP_INFO(p_hwfn,
1355                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1356                         L1_CACHE_BYTES, wr_mbs);
1357
1358         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1359         if (val > 0) {
1360                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1361                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1362         }
1363 }
1364
1365 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1366                               struct qed_ptt *p_ptt, int hw_mode)
1367 {
1368         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1369         struct qed_qm_common_rt_init_params params;
1370         struct qed_dev *cdev = p_hwfn->cdev;
1371         u8 vf_id, max_num_vfs;
1372         u16 num_pfs, pf_id;
1373         u32 concrete_fid;
1374         int rc = 0;
1375
1376         qed_init_cau_rt_data(cdev);
1377
1378         /* Program GTT windows */
1379         qed_gtt_init(p_hwfn);
1380
1381         if (p_hwfn->mcp_info) {
1382                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1383                         qm_info->pf_rl_en = true;
1384                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1385                         qm_info->pf_wfq_en = true;
1386         }
1387
1388         memset(&params, 0, sizeof(params));
1389         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1390         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1391         params.pf_rl_en = qm_info->pf_rl_en;
1392         params.pf_wfq_en = qm_info->pf_wfq_en;
1393         params.vport_rl_en = qm_info->vport_rl_en;
1394         params.vport_wfq_en = qm_info->vport_wfq_en;
1395         params.port_params = qm_info->qm_port_params;
1396
1397         qed_qm_common_rt_init(p_hwfn, &params);
1398
1399         qed_cxt_hw_init_common(p_hwfn);
1400
1401         qed_init_cache_line_size(p_hwfn, p_ptt);
1402
1403         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1404         if (rc)
1405                 return rc;
1406
1407         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1408         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1409
1410         if (QED_IS_BB(p_hwfn->cdev)) {
1411                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1412                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1413                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1414                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1415                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1416                 }
1417                 /* pretend to original PF */
1418                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1419         }
1420
1421         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1422         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1423                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1424                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1425                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1426                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1427                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1428                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1429         }
1430         /* pretend to original PF */
1431         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1432
1433         return rc;
1434 }
1435
1436 static int
1437 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1438                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1439 {
1440         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1441         u32 min_dpis;
1442         u32 n_wids;
1443
1444         /* Calculate DPI size */
1445         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1446         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1447         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1448         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1449         dpi_count = pwm_region_size / dpi_page_size;
1450
1451         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1452         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1453
1454         p_hwfn->dpi_size = dpi_page_size;
1455         p_hwfn->dpi_count = dpi_count;
1456
1457         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1458
1459         if (dpi_count < min_dpis)
1460                 return -EINVAL;
1461
1462         return 0;
1463 }
1464
1465 enum QED_ROCE_EDPM_MODE {
1466         QED_ROCE_EDPM_MODE_ENABLE = 0,
1467         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1468         QED_ROCE_EDPM_MODE_DISABLE = 2,
1469 };
1470
1471 static int
1472 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1473 {
1474         u32 pwm_regsize, norm_regsize;
1475         u32 non_pwm_conn, min_addr_reg1;
1476         u32 db_bar_size, n_cpus = 1;
1477         u32 roce_edpm_mode;
1478         u32 pf_dems_shift;
1479         int rc = 0;
1480         u8 cond;
1481
1482         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1483         if (p_hwfn->cdev->num_hwfns > 1)
1484                 db_bar_size /= 2;
1485
1486         /* Calculate doorbell regions */
1487         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1488                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1489                                                    NULL) +
1490                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1491                                                    NULL);
1492         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1493         min_addr_reg1 = norm_regsize / 4096;
1494         pwm_regsize = db_bar_size - norm_regsize;
1495
1496         /* Check that the normal and PWM sizes are valid */
1497         if (db_bar_size < norm_regsize) {
1498                 DP_ERR(p_hwfn->cdev,
1499                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1500                        db_bar_size, norm_regsize);
1501                 return -EINVAL;
1502         }
1503
1504         if (pwm_regsize < QED_MIN_PWM_REGION) {
1505                 DP_ERR(p_hwfn->cdev,
1506                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1507                        pwm_regsize,
1508                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1509                 return -EINVAL;
1510         }
1511
1512         /* Calculate number of DPIs */
1513         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1514         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1515             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1516                 /* Either EDPM is mandatory, or we are attempting to allocate a
1517                  * WID per CPU.
1518                  */
1519                 n_cpus = num_present_cpus();
1520                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1521         }
1522
1523         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1524                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1525         if (cond || p_hwfn->dcbx_no_edpm) {
1526                 /* Either EDPM is disabled from user configuration, or it is
1527                  * disabled via DCBx, or it is not mandatory and we failed to
1528                  * allocated a WID per CPU.
1529                  */
1530                 n_cpus = 1;
1531                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1532
1533                 if (cond)
1534                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1535         }
1536
1537         p_hwfn->wid_count = (u16) n_cpus;
1538
1539         DP_INFO(p_hwfn,
1540                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1541                 norm_regsize,
1542                 pwm_regsize,
1543                 p_hwfn->dpi_size,
1544                 p_hwfn->dpi_count,
1545                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1546                 "disabled" : "enabled");
1547
1548         if (rc) {
1549                 DP_ERR(p_hwfn,
1550                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1551                        p_hwfn->dpi_count,
1552                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1553                 return -EINVAL;
1554         }
1555
1556         p_hwfn->dpi_start_offset = norm_regsize;
1557
1558         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1559         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1560         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1561         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1562
1563         return 0;
1564 }
1565
1566 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1567                             struct qed_ptt *p_ptt, int hw_mode)
1568 {
1569         int rc = 0;
1570
1571         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1572         if (rc)
1573                 return rc;
1574
1575         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1576
1577         return 0;
1578 }
1579
1580 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1581                           struct qed_ptt *p_ptt,
1582                           struct qed_tunnel_info *p_tunn,
1583                           int hw_mode,
1584                           bool b_hw_start,
1585                           enum qed_int_mode int_mode,
1586                           bool allow_npar_tx_switch)
1587 {
1588         u8 rel_pf_id = p_hwfn->rel_pf_id;
1589         int rc = 0;
1590
1591         if (p_hwfn->mcp_info) {
1592                 struct qed_mcp_function_info *p_info;
1593
1594                 p_info = &p_hwfn->mcp_info->func_info;
1595                 if (p_info->bandwidth_min)
1596                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1597
1598                 /* Update rate limit once we'll actually have a link */
1599                 p_hwfn->qm_info.pf_rl = 100000;
1600         }
1601
1602         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1603
1604         qed_int_igu_init_rt(p_hwfn);
1605
1606         /* Set VLAN in NIG if needed */
1607         if (hw_mode & BIT(MODE_MF_SD)) {
1608                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1609                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1610                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1611                              p_hwfn->hw_info.ovlan);
1612
1613                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1614                            "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1615                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1616                              1);
1617         }
1618
1619         /* Enable classification by MAC if needed */
1620         if (hw_mode & BIT(MODE_MF_SI)) {
1621                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1622                            "Configuring TAGMAC_CLS_TYPE\n");
1623                 STORE_RT_REG(p_hwfn,
1624                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1625         }
1626
1627         /* Protocol Configuration */
1628         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1629                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1630         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1631                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1632         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1633
1634         /* Cleanup chip from previous driver if such remains exist */
1635         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1636         if (rc)
1637                 return rc;
1638
1639         /* Sanity check before the PF init sequence that uses DMAE */
1640         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1641         if (rc)
1642                 return rc;
1643
1644         /* PF Init sequence */
1645         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1646         if (rc)
1647                 return rc;
1648
1649         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1650         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1651         if (rc)
1652                 return rc;
1653
1654         /* Pure runtime initializations - directly to the HW  */
1655         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1656
1657         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1658         if (rc)
1659                 return rc;
1660
1661         if (b_hw_start) {
1662                 /* enable interrupts */
1663                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1664
1665                 /* send function start command */
1666                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1667                                      allow_npar_tx_switch);
1668                 if (rc) {
1669                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1670                         return rc;
1671                 }
1672                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1673                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1674                         qed_wr(p_hwfn, p_ptt,
1675                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1676                                0x100);
1677                 }
1678         }
1679         return rc;
1680 }
1681
1682 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1683                                struct qed_ptt *p_ptt,
1684                                u8 enable)
1685 {
1686         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1687
1688         /* Change PF in PXP */
1689         qed_wr(p_hwfn, p_ptt,
1690                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1691
1692         /* wait until value is set - try for 1 second every 50us */
1693         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1694                 val = qed_rd(p_hwfn, p_ptt,
1695                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1696                 if (val == set_val)
1697                         break;
1698
1699                 usleep_range(50, 60);
1700         }
1701
1702         if (val != set_val) {
1703                 DP_NOTICE(p_hwfn,
1704                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1705                 return -EAGAIN;
1706         }
1707
1708         return 0;
1709 }
1710
1711 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1712                                 struct qed_ptt *p_main_ptt)
1713 {
1714         /* Read shadow of current MFW mailbox */
1715         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1716         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1717                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1718 }
1719
1720 static void
1721 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1722                          struct qed_drv_load_params *p_drv_load)
1723 {
1724         memset(p_load_req, 0, sizeof(*p_load_req));
1725
1726         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1727                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1728         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1729         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1730         p_load_req->override_force_load = p_drv_load->override_force_load;
1731 }
1732
1733 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1734                         struct qed_hw_init_params *p_params)
1735 {
1736         if (p_params->p_tunn) {
1737                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1738                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1739         }
1740
1741         p_hwfn->b_int_enabled = true;
1742
1743         return 0;
1744 }
1745
1746 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1747 {
1748         struct qed_load_req_params load_req_params;
1749         u32 load_code, resp, param, drv_mb_param;
1750         bool b_default_mtu = true;
1751         struct qed_hwfn *p_hwfn;
1752         int rc = 0, mfw_rc, i;
1753         u16 ether_type;
1754
1755         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1756                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1757                 return -EINVAL;
1758         }
1759
1760         if (IS_PF(cdev)) {
1761                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1762                 if (rc)
1763                         return rc;
1764         }
1765
1766         for_each_hwfn(cdev, i) {
1767                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1768
1769                 /* If management didn't provide a default, set one of our own */
1770                 if (!p_hwfn->hw_info.mtu) {
1771                         p_hwfn->hw_info.mtu = 1500;
1772                         b_default_mtu = false;
1773                 }
1774
1775                 if (IS_VF(cdev)) {
1776                         qed_vf_start(p_hwfn, p_params);
1777                         continue;
1778                 }
1779
1780                 /* Enable DMAE in PXP */
1781                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1782
1783                 rc = qed_calc_hw_mode(p_hwfn);
1784                 if (rc)
1785                         return rc;
1786
1787                 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
1788                                              &cdev->mf_bits) ||
1789                                     test_bit(QED_MF_8021AD_TAGGING,
1790                                              &cdev->mf_bits))) {
1791                         if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
1792                                 ether_type = ETH_P_8021Q;
1793                         else
1794                                 ether_type = ETH_P_8021AD;
1795                         STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1796                                      ether_type);
1797                         STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1798                                      ether_type);
1799                         STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1800                                      ether_type);
1801                         STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
1802                                      ether_type);
1803                 }
1804
1805                 qed_fill_load_req_params(&load_req_params,
1806                                          p_params->p_drv_load_params);
1807                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1808                                       &load_req_params);
1809                 if (rc) {
1810                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1811                         return rc;
1812                 }
1813
1814                 load_code = load_req_params.load_code;
1815                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1816                            "Load request was sent. Load code: 0x%x\n",
1817                            load_code);
1818
1819                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1820
1821                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1822
1823                 p_hwfn->first_on_engine = (load_code ==
1824                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1825
1826                 switch (load_code) {
1827                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1828                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1829                                                 p_hwfn->hw_info.hw_mode);
1830                         if (rc)
1831                                 break;
1832                 /* Fall through */
1833                 case FW_MSG_CODE_DRV_LOAD_PORT:
1834                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1835                                               p_hwfn->hw_info.hw_mode);
1836                         if (rc)
1837                                 break;
1838
1839                 /* Fall through */
1840                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1841                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1842                                             p_params->p_tunn,
1843                                             p_hwfn->hw_info.hw_mode,
1844                                             p_params->b_hw_start,
1845                                             p_params->int_mode,
1846                                             p_params->allow_npar_tx_switch);
1847                         break;
1848                 default:
1849                         DP_NOTICE(p_hwfn,
1850                                   "Unexpected load code [0x%08x]", load_code);
1851                         rc = -EINVAL;
1852                         break;
1853                 }
1854
1855                 if (rc)
1856                         DP_NOTICE(p_hwfn,
1857                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1858                                    load_code, rc);
1859
1860                 /* ACK mfw regardless of success or failure of initialization */
1861                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1862                                      DRV_MSG_CODE_LOAD_DONE,
1863                                      0, &load_code, &param);
1864                 if (rc)
1865                         return rc;
1866                 if (mfw_rc) {
1867                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1868                         return mfw_rc;
1869                 }
1870
1871                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1872                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1873                         DP_NOTICE(p_hwfn,
1874                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1875
1876                 /* send DCBX attention request command */
1877                 DP_VERBOSE(p_hwfn,
1878                            QED_MSG_DCB,
1879                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1880                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1881                                      DRV_MSG_CODE_SET_DCBX,
1882                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1883                                      &load_code, &param);
1884                 if (mfw_rc) {
1885                         DP_NOTICE(p_hwfn,
1886                                   "Failed to send DCBX attention request\n");
1887                         return mfw_rc;
1888                 }
1889
1890                 p_hwfn->hw_init_done = true;
1891         }
1892
1893         if (IS_PF(cdev)) {
1894                 p_hwfn = QED_LEADING_HWFN(cdev);
1895
1896                 /* Get pre-negotiated values for stag, bandwidth etc. */
1897                 DP_VERBOSE(p_hwfn,
1898                            QED_MSG_SPQ,
1899                            "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
1900                 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
1901                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1902                                  DRV_MSG_CODE_GET_OEM_UPDATES,
1903                                  drv_mb_param, &resp, &param);
1904                 if (rc)
1905                         DP_NOTICE(p_hwfn,
1906                                   "Failed to send GET_OEM_UPDATES attention request\n");
1907
1908                 drv_mb_param = STORM_FW_VERSION;
1909                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1910                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1911                                  drv_mb_param, &load_code, &param);
1912                 if (rc)
1913                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1914
1915                 if (!b_default_mtu) {
1916                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1917                                                    p_hwfn->hw_info.mtu);
1918                         if (rc)
1919                                 DP_INFO(p_hwfn,
1920                                         "Failed to update default mtu\n");
1921                 }
1922
1923                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1924                                                     p_hwfn->p_main_ptt,
1925                                                   QED_OV_DRIVER_STATE_DISABLED);
1926                 if (rc)
1927                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1928
1929                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1930                                                QED_OV_ESWITCH_NONE);
1931                 if (rc)
1932                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1933         }
1934
1935         return 0;
1936 }
1937
1938 #define QED_HW_STOP_RETRY_LIMIT (10)
1939 static void qed_hw_timers_stop(struct qed_dev *cdev,
1940                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1941 {
1942         int i;
1943
1944         /* close timers */
1945         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1946         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1947
1948         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1949                 if ((!qed_rd(p_hwfn, p_ptt,
1950                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1951                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1952                         break;
1953
1954                 /* Dependent on number of connection/tasks, possibly
1955                  * 1ms sleep is required between polls
1956                  */
1957                 usleep_range(1000, 2000);
1958         }
1959
1960         if (i < QED_HW_STOP_RETRY_LIMIT)
1961                 return;
1962
1963         DP_NOTICE(p_hwfn,
1964                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1965                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1966                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1967 }
1968
1969 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1970 {
1971         int j;
1972
1973         for_each_hwfn(cdev, j) {
1974                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1975                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1976
1977                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1978         }
1979 }
1980
1981 int qed_hw_stop(struct qed_dev *cdev)
1982 {
1983         struct qed_hwfn *p_hwfn;
1984         struct qed_ptt *p_ptt;
1985         int rc, rc2 = 0;
1986         int j;
1987
1988         for_each_hwfn(cdev, j) {
1989                 p_hwfn = &cdev->hwfns[j];
1990                 p_ptt = p_hwfn->p_main_ptt;
1991
1992                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1993
1994                 if (IS_VF(cdev)) {
1995                         qed_vf_pf_int_cleanup(p_hwfn);
1996                         rc = qed_vf_pf_reset(p_hwfn);
1997                         if (rc) {
1998                                 DP_NOTICE(p_hwfn,
1999                                           "qed_vf_pf_reset failed. rc = %d.\n",
2000                                           rc);
2001                                 rc2 = -EINVAL;
2002                         }
2003                         continue;
2004                 }
2005
2006                 /* mark the hw as uninitialized... */
2007                 p_hwfn->hw_init_done = false;
2008
2009                 /* Send unload command to MCP */
2010                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
2011                 if (rc) {
2012                         DP_NOTICE(p_hwfn,
2013                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
2014                                   rc);
2015                         rc2 = -EINVAL;
2016                 }
2017
2018                 qed_slowpath_irq_sync(p_hwfn);
2019
2020                 /* After this point no MFW attentions are expected, e.g. prevent
2021                  * race between pf stop and dcbx pf update.
2022                  */
2023                 rc = qed_sp_pf_stop(p_hwfn);
2024                 if (rc) {
2025                         DP_NOTICE(p_hwfn,
2026                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
2027                                   rc);
2028                         rc2 = -EINVAL;
2029                 }
2030
2031                 qed_wr(p_hwfn, p_ptt,
2032                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2033
2034                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2035                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2036                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2037                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2038                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2039
2040                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
2041
2042                 /* Disable Attention Generation */
2043                 qed_int_igu_disable_int(p_hwfn, p_ptt);
2044
2045                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
2046                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
2047
2048                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
2049
2050                 /* Need to wait 1ms to guarantee SBs are cleared */
2051                 usleep_range(1000, 2000);
2052
2053                 /* Disable PF in HW blocks */
2054                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
2055                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
2056
2057                 qed_mcp_unload_done(p_hwfn, p_ptt);
2058                 if (rc) {
2059                         DP_NOTICE(p_hwfn,
2060                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
2061                                   rc);
2062                         rc2 = -EINVAL;
2063                 }
2064         }
2065
2066         if (IS_PF(cdev)) {
2067                 p_hwfn = QED_LEADING_HWFN(cdev);
2068                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
2069
2070                 /* Disable DMAE in PXP - in CMT, this should only be done for
2071                  * first hw-function, and only after all transactions have
2072                  * stopped for all active hw-functions.
2073                  */
2074                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
2075                 if (rc) {
2076                         DP_NOTICE(p_hwfn,
2077                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
2078                         rc2 = -EINVAL;
2079                 }
2080         }
2081
2082         return rc2;
2083 }
2084
2085 int qed_hw_stop_fastpath(struct qed_dev *cdev)
2086 {
2087         int j;
2088
2089         for_each_hwfn(cdev, j) {
2090                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
2091                 struct qed_ptt *p_ptt;
2092
2093                 if (IS_VF(cdev)) {
2094                         qed_vf_pf_int_cleanup(p_hwfn);
2095                         continue;
2096                 }
2097                 p_ptt = qed_ptt_acquire(p_hwfn);
2098                 if (!p_ptt)
2099                         return -EAGAIN;
2100
2101                 DP_VERBOSE(p_hwfn,
2102                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
2103
2104                 qed_wr(p_hwfn, p_ptt,
2105                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
2106
2107                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2108                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
2109                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
2110                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2111                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
2112
2113                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
2114
2115                 /* Need to wait 1ms to guarantee SBs are cleared */
2116                 usleep_range(1000, 2000);
2117                 qed_ptt_release(p_hwfn, p_ptt);
2118         }
2119
2120         return 0;
2121 }
2122
2123 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2124 {
2125         struct qed_ptt *p_ptt;
2126
2127         if (IS_VF(p_hwfn->cdev))
2128                 return 0;
2129
2130         p_ptt = qed_ptt_acquire(p_hwfn);
2131         if (!p_ptt)
2132                 return -EAGAIN;
2133
2134         if (p_hwfn->p_rdma_info &&
2135             p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
2136                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2137
2138         /* Re-open incoming traffic */
2139         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2140         qed_ptt_release(p_hwfn, p_ptt);
2141
2142         return 0;
2143 }
2144
2145 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2146 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2147 {
2148         qed_ptt_pool_free(p_hwfn);
2149         kfree(p_hwfn->hw_info.p_igu_info);
2150         p_hwfn->hw_info.p_igu_info = NULL;
2151 }
2152
2153 /* Setup bar access */
2154 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2155 {
2156         /* clear indirect access */
2157         if (QED_IS_AH(p_hwfn->cdev)) {
2158                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2159                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2160                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2161                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2162                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2163                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2164                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2165                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2166         } else {
2167                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2168                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2169                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2170                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2171                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2172                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2173                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2174                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2175         }
2176
2177         /* Clean Previous errors if such exist */
2178         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2179                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2180
2181         /* enable internal target-read */
2182         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2183                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2184 }
2185
2186 static void get_function_id(struct qed_hwfn *p_hwfn)
2187 {
2188         /* ME Register */
2189         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2190                                                   PXP_PF_ME_OPAQUE_ADDR);
2191
2192         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2193
2194         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2195         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2196                                       PXP_CONCRETE_FID_PFID);
2197         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2198                                     PXP_CONCRETE_FID_PORT);
2199
2200         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2201                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2202                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2203 }
2204
2205 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2206 {
2207         u32 *feat_num = p_hwfn->hw_info.feat_num;
2208         struct qed_sb_cnt_info sb_cnt;
2209         u32 non_l2_sbs = 0;
2210
2211         memset(&sb_cnt, 0, sizeof(sb_cnt));
2212         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2213
2214         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2215             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2216                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2217                  * the status blocks equally between L2 / RoCE but with
2218                  * consideration as to how many l2 queues / cnqs we have.
2219                  */
2220                 feat_num[QED_RDMA_CNQ] =
2221                         min_t(u32, sb_cnt.cnt / 2,
2222                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2223
2224                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2225         }
2226         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2227                 /* Start by allocating VF queues, then PF's */
2228                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2229                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2230                                                 sb_cnt.iov_cnt);
2231                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2232                                                 sb_cnt.cnt - non_l2_sbs,
2233                                                 RESC_NUM(p_hwfn,
2234                                                          QED_L2_QUEUE) -
2235                                                 FEAT_NUM(p_hwfn,
2236                                                          QED_VF_L2_QUE));
2237         }
2238
2239         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2240                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2241                                                RESC_NUM(p_hwfn,
2242                                                         QED_CMDQS_CQS));
2243
2244         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2245                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2246                                                RESC_NUM(p_hwfn,
2247                                                         QED_CMDQS_CQS));
2248         DP_VERBOSE(p_hwfn,
2249                    NETIF_MSG_PROBE,
2250                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2251                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2252                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2253                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2254                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2255                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2256                    (int)sb_cnt.cnt);
2257 }
2258
2259 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2260 {
2261         switch (res_id) {
2262         case QED_L2_QUEUE:
2263                 return "L2_QUEUE";
2264         case QED_VPORT:
2265                 return "VPORT";
2266         case QED_RSS_ENG:
2267                 return "RSS_ENG";
2268         case QED_PQ:
2269                 return "PQ";
2270         case QED_RL:
2271                 return "RL";
2272         case QED_MAC:
2273                 return "MAC";
2274         case QED_VLAN:
2275                 return "VLAN";
2276         case QED_RDMA_CNQ_RAM:
2277                 return "RDMA_CNQ_RAM";
2278         case QED_ILT:
2279                 return "ILT";
2280         case QED_LL2_QUEUE:
2281                 return "LL2_QUEUE";
2282         case QED_CMDQS_CQS:
2283                 return "CMDQS_CQS";
2284         case QED_RDMA_STATS_QUEUE:
2285                 return "RDMA_STATS_QUEUE";
2286         case QED_BDQ:
2287                 return "BDQ";
2288         case QED_SB:
2289                 return "SB";
2290         default:
2291                 return "UNKNOWN_RESOURCE";
2292         }
2293 }
2294
2295 static int
2296 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2297                             struct qed_ptt *p_ptt,
2298                             enum qed_resources res_id,
2299                             u32 resc_max_val, u32 *p_mcp_resp)
2300 {
2301         int rc;
2302
2303         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2304                                       resc_max_val, p_mcp_resp);
2305         if (rc) {
2306                 DP_NOTICE(p_hwfn,
2307                           "MFW response failure for a max value setting of resource %d [%s]\n",
2308                           res_id, qed_hw_get_resc_name(res_id));
2309                 return rc;
2310         }
2311
2312         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2313                 DP_INFO(p_hwfn,
2314                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2315                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2316
2317         return 0;
2318 }
2319
2320 static int
2321 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2322 {
2323         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2324         u32 resc_max_val, mcp_resp;
2325         u8 res_id;
2326         int rc;
2327
2328         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2329                 switch (res_id) {
2330                 case QED_LL2_QUEUE:
2331                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2332                         break;
2333                 case QED_RDMA_CNQ_RAM:
2334                         /* No need for a case for QED_CMDQS_CQS since
2335                          * CNQ/CMDQS are the same resource.
2336                          */
2337                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
2338                         break;
2339                 case QED_RDMA_STATS_QUEUE:
2340                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2341                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2342                         break;
2343                 case QED_BDQ:
2344                         resc_max_val = BDQ_NUM_RESOURCES;
2345                         break;
2346                 default:
2347                         continue;
2348                 }
2349
2350                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2351                                                  resc_max_val, &mcp_resp);
2352                 if (rc)
2353                         return rc;
2354
2355                 /* There's no point to continue to the next resource if the
2356                  * command is not supported by the MFW.
2357                  * We do continue if the command is supported but the resource
2358                  * is unknown to the MFW. Such a resource will be later
2359                  * configured with the default allocation values.
2360                  */
2361                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2362                         return -EINVAL;
2363         }
2364
2365         return 0;
2366 }
2367
2368 static
2369 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2370                          enum qed_resources res_id,
2371                          u32 *p_resc_num, u32 *p_resc_start)
2372 {
2373         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2374         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2375
2376         switch (res_id) {
2377         case QED_L2_QUEUE:
2378                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2379                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2380                 break;
2381         case QED_VPORT:
2382                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2383                                MAX_NUM_VPORTS_BB) / num_funcs;
2384                 break;
2385         case QED_RSS_ENG:
2386                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2387                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2388                 break;
2389         case QED_PQ:
2390                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2391                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2392                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2393                 break;
2394         case QED_RL:
2395                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2396                 break;
2397         case QED_MAC:
2398         case QED_VLAN:
2399                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2400                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2401                 break;
2402         case QED_ILT:
2403                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2404                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2405                 break;
2406         case QED_LL2_QUEUE:
2407                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2408                 break;
2409         case QED_RDMA_CNQ_RAM:
2410         case QED_CMDQS_CQS:
2411                 /* CNQ/CMDQS are the same resource */
2412                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2413                 break;
2414         case QED_RDMA_STATS_QUEUE:
2415                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2416                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2417                 break;
2418         case QED_BDQ:
2419                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2420                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2421                         *p_resc_num = 0;
2422                 else
2423                         *p_resc_num = 1;
2424                 break;
2425         case QED_SB:
2426                 /* Since we want its value to reflect whether MFW supports
2427                  * the new scheme, have a default of 0.
2428                  */
2429                 *p_resc_num = 0;
2430                 break;
2431         default:
2432                 return -EINVAL;
2433         }
2434
2435         switch (res_id) {
2436         case QED_BDQ:
2437                 if (!*p_resc_num)
2438                         *p_resc_start = 0;
2439                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2440                         *p_resc_start = p_hwfn->port_id;
2441                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2442                         *p_resc_start = p_hwfn->port_id;
2443                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2444                         *p_resc_start = p_hwfn->port_id + 2;
2445                 break;
2446         default:
2447                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2448                 break;
2449         }
2450
2451         return 0;
2452 }
2453
2454 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2455                                   enum qed_resources res_id)
2456 {
2457         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2458         u32 mcp_resp, *p_resc_num, *p_resc_start;
2459         int rc;
2460
2461         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2462         p_resc_start = &RESC_START(p_hwfn, res_id);
2463
2464         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2465                                   &dflt_resc_start);
2466         if (rc) {
2467                 DP_ERR(p_hwfn,
2468                        "Failed to get default amount for resource %d [%s]\n",
2469                        res_id, qed_hw_get_resc_name(res_id));
2470                 return rc;
2471         }
2472
2473         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2474                                    &mcp_resp, p_resc_num, p_resc_start);
2475         if (rc) {
2476                 DP_NOTICE(p_hwfn,
2477                           "MFW response failure for an allocation request for resource %d [%s]\n",
2478                           res_id, qed_hw_get_resc_name(res_id));
2479                 return rc;
2480         }
2481
2482         /* Default driver values are applied in the following cases:
2483          * - The resource allocation MB command is not supported by the MFW
2484          * - There is an internal error in the MFW while processing the request
2485          * - The resource ID is unknown to the MFW
2486          */
2487         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2488                 DP_INFO(p_hwfn,
2489                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2490                         res_id,
2491                         qed_hw_get_resc_name(res_id),
2492                         mcp_resp, dflt_resc_num, dflt_resc_start);
2493                 *p_resc_num = dflt_resc_num;
2494                 *p_resc_start = dflt_resc_start;
2495                 goto out;
2496         }
2497
2498 out:
2499         /* PQs have to divide by 8 [that's the HW granularity].
2500          * Reduce number so it would fit.
2501          */
2502         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2503                 DP_INFO(p_hwfn,
2504                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2505                         *p_resc_num,
2506                         (*p_resc_num) & ~0x7,
2507                         *p_resc_start, (*p_resc_start) & ~0x7);
2508                 *p_resc_num &= ~0x7;
2509                 *p_resc_start &= ~0x7;
2510         }
2511
2512         return 0;
2513 }
2514
2515 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2516 {
2517         int rc;
2518         u8 res_id;
2519
2520         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2521                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2522                 if (rc)
2523                         return rc;
2524         }
2525
2526         return 0;
2527 }
2528
2529 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2530 {
2531         struct qed_resc_unlock_params resc_unlock_params;
2532         struct qed_resc_lock_params resc_lock_params;
2533         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2534         u8 res_id;
2535         int rc;
2536
2537         /* Setting the max values of the soft resources and the following
2538          * resources allocation queries should be atomic. Since several PFs can
2539          * run in parallel - a resource lock is needed.
2540          * If either the resource lock or resource set value commands are not
2541          * supported - skip the the max values setting, release the lock if
2542          * needed, and proceed to the queries. Other failures, including a
2543          * failure to acquire the lock, will cause this function to fail.
2544          */
2545         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2546                                        QED_RESC_LOCK_RESC_ALLOC, false);
2547
2548         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2549         if (rc && rc != -EINVAL) {
2550                 return rc;
2551         } else if (rc == -EINVAL) {
2552                 DP_INFO(p_hwfn,
2553                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2554         } else if (!rc && !resc_lock_params.b_granted) {
2555                 DP_NOTICE(p_hwfn,
2556                           "Failed to acquire the resource lock for the resource allocation commands\n");
2557                 return -EBUSY;
2558         } else {
2559                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2560                 if (rc && rc != -EINVAL) {
2561                         DP_NOTICE(p_hwfn,
2562                                   "Failed to set the max values of the soft resources\n");
2563                         goto unlock_and_exit;
2564                 } else if (rc == -EINVAL) {
2565                         DP_INFO(p_hwfn,
2566                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2567                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2568                                                  &resc_unlock_params);
2569                         if (rc)
2570                                 DP_INFO(p_hwfn,
2571                                         "Failed to release the resource lock for the resource allocation commands\n");
2572                 }
2573         }
2574
2575         rc = qed_hw_set_resc_info(p_hwfn);
2576         if (rc)
2577                 goto unlock_and_exit;
2578
2579         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2580                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2581                 if (rc)
2582                         DP_INFO(p_hwfn,
2583                                 "Failed to release the resource lock for the resource allocation commands\n");
2584         }
2585
2586         /* Sanity for ILT */
2587         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2588             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2589                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2590                           RESC_START(p_hwfn, QED_ILT),
2591                           RESC_END(p_hwfn, QED_ILT) - 1);
2592                 return -EINVAL;
2593         }
2594
2595         /* This will also learn the number of SBs from MFW */
2596         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2597                 return -EINVAL;
2598
2599         qed_hw_set_feat(p_hwfn);
2600
2601         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2602                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2603                            qed_hw_get_resc_name(res_id),
2604                            RESC_NUM(p_hwfn, res_id),
2605                            RESC_START(p_hwfn, res_id));
2606
2607         return 0;
2608
2609 unlock_and_exit:
2610         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2611                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2612         return rc;
2613 }
2614
2615 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2616 {
2617         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2618         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2619         struct qed_mcp_link_capabilities *p_caps;
2620         struct qed_mcp_link_params *link;
2621
2622         /* Read global nvm_cfg address */
2623         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2624
2625         /* Verify MCP has initialized it */
2626         if (!nvm_cfg_addr) {
2627                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2628                 return -EINVAL;
2629         }
2630
2631         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2632         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2633
2634         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2635                offsetof(struct nvm_cfg1, glob) +
2636                offsetof(struct nvm_cfg1_glob, core_cfg);
2637
2638         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2639
2640         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2641                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2642         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2643                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2644                 break;
2645         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2646                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2647                 break;
2648         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2649                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2650                 break;
2651         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2652                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2653                 break;
2654         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2655                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2656                 break;
2657         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2658                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2659                 break;
2660         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2661                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2662                 break;
2663         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2664                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2665                 break;
2666         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2667                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2668                 break;
2669         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2670                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2671                 break;
2672         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2673                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2674                 break;
2675         default:
2676                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2677                 break;
2678         }
2679
2680         /* Read default link configuration */
2681         link = &p_hwfn->mcp_info->link_input;
2682         p_caps = &p_hwfn->mcp_info->link_capabilities;
2683         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2684                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2685         link_temp = qed_rd(p_hwfn, p_ptt,
2686                            port_cfg_addr +
2687                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2688         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2689         link->speed.advertised_speeds = link_temp;
2690
2691         link_temp = link->speed.advertised_speeds;
2692         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2693
2694         link_temp = qed_rd(p_hwfn, p_ptt,
2695                            port_cfg_addr +
2696                            offsetof(struct nvm_cfg1_port, link_settings));
2697         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2698                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2699         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2700                 link->speed.autoneg = true;
2701                 break;
2702         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2703                 link->speed.forced_speed = 1000;
2704                 break;
2705         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2706                 link->speed.forced_speed = 10000;
2707                 break;
2708         case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
2709                 link->speed.forced_speed = 20000;
2710                 break;
2711         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2712                 link->speed.forced_speed = 25000;
2713                 break;
2714         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2715                 link->speed.forced_speed = 40000;
2716                 break;
2717         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2718                 link->speed.forced_speed = 50000;
2719                 break;
2720         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2721                 link->speed.forced_speed = 100000;
2722                 break;
2723         default:
2724                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2725         }
2726
2727         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2728                 link->speed.autoneg;
2729
2730         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2731         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2732         link->pause.autoneg = !!(link_temp &
2733                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2734         link->pause.forced_rx = !!(link_temp &
2735                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2736         link->pause.forced_tx = !!(link_temp &
2737                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2738         link->loopback_mode = 0;
2739
2740         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2741                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2742                                    offsetof(struct nvm_cfg1_port, ext_phy));
2743                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2744                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2745                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2746                 link->eee.enable = true;
2747                 switch (link_temp) {
2748                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2749                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
2750                         link->eee.enable = false;
2751                         break;
2752                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2753                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2754                         break;
2755                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2756                         p_caps->eee_lpi_timer =
2757                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2758                         break;
2759                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2760                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2761                         break;
2762                 }
2763
2764                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2765                 link->eee.tx_lpi_enable = link->eee.enable;
2766                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2767         } else {
2768                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2769         }
2770
2771         DP_VERBOSE(p_hwfn,
2772                    NETIF_MSG_LINK,
2773                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2774                    link->speed.forced_speed,
2775                    link->speed.advertised_speeds,
2776                    link->speed.autoneg,
2777                    link->pause.autoneg,
2778                    p_caps->default_eee, p_caps->eee_lpi_timer);
2779
2780         if (IS_LEAD_HWFN(p_hwfn)) {
2781                 struct qed_dev *cdev = p_hwfn->cdev;
2782
2783                 /* Read Multi-function information from shmem */
2784                 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2785                        offsetof(struct nvm_cfg1, glob) +
2786                        offsetof(struct nvm_cfg1_glob, generic_cont0);
2787
2788                 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2789
2790                 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2791                           NVM_CFG1_GLOB_MF_MODE_OFFSET;
2792
2793                 switch (mf_mode) {
2794                 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2795                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
2796                         break;
2797                 case NVM_CFG1_GLOB_MF_MODE_UFP:
2798                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2799                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2800                                         BIT(QED_MF_UFP_SPECIFIC) |
2801                                         BIT(QED_MF_8021Q_TAGGING);
2802                         break;
2803                 case NVM_CFG1_GLOB_MF_MODE_BD:
2804                         cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2805                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2806                                         BIT(QED_MF_8021AD_TAGGING);
2807                         break;
2808                 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2809                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2810                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2811                                         BIT(QED_MF_LL2_NON_UNICAST) |
2812                                         BIT(QED_MF_INTER_PF_SWITCH);
2813                         break;
2814                 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2815                         cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2816                                         BIT(QED_MF_LLH_PROTO_CLSS) |
2817                                         BIT(QED_MF_LL2_NON_UNICAST);
2818                         if (QED_IS_BB(p_hwfn->cdev))
2819                                 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
2820                         break;
2821                 }
2822
2823                 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2824                         cdev->mf_bits);
2825         }
2826
2827         DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2828                 p_hwfn->cdev->mf_bits);
2829
2830         /* Read device capabilities information from shmem */
2831         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2832                 offsetof(struct nvm_cfg1, glob) +
2833                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2834
2835         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2836         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2837                 __set_bit(QED_DEV_CAP_ETH,
2838                           &p_hwfn->hw_info.device_capabilities);
2839         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2840                 __set_bit(QED_DEV_CAP_FCOE,
2841                           &p_hwfn->hw_info.device_capabilities);
2842         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2843                 __set_bit(QED_DEV_CAP_ISCSI,
2844                           &p_hwfn->hw_info.device_capabilities);
2845         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2846                 __set_bit(QED_DEV_CAP_ROCE,
2847                           &p_hwfn->hw_info.device_capabilities);
2848
2849         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2850 }
2851
2852 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2853 {
2854         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2855         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2856         struct qed_dev *cdev = p_hwfn->cdev;
2857
2858         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2859
2860         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2861          * in the other bits are selected.
2862          * Bits 1-15 are for functions 1-15, respectively, and their value is
2863          * '0' only for enabled functions (function 0 always exists and
2864          * enabled).
2865          * In case of CMT, only the "even" functions are enabled, and thus the
2866          * number of functions for both hwfns is learnt from the same bits.
2867          */
2868         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2869
2870         if (reg_function_hide & 0x1) {
2871                 if (QED_IS_BB(cdev)) {
2872                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2873                                 num_funcs = 0;
2874                                 eng_mask = 0xaaaa;
2875                         } else {
2876                                 num_funcs = 1;
2877                                 eng_mask = 0x5554;
2878                         }
2879                 } else {
2880                         num_funcs = 1;
2881                         eng_mask = 0xfffe;
2882                 }
2883
2884                 /* Get the number of the enabled functions on the engine */
2885                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2886                 while (tmp) {
2887                         if (tmp & 0x1)
2888                                 num_funcs++;
2889                         tmp >>= 0x1;
2890                 }
2891
2892                 /* Get the PF index within the enabled functions */
2893                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2894                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2895                 while (tmp) {
2896                         if (tmp & 0x1)
2897                                 enabled_func_idx--;
2898                         tmp >>= 0x1;
2899                 }
2900         }
2901
2902         p_hwfn->num_funcs_on_engine = num_funcs;
2903         p_hwfn->enabled_func_idx = enabled_func_idx;
2904
2905         DP_VERBOSE(p_hwfn,
2906                    NETIF_MSG_PROBE,
2907                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2908                    p_hwfn->rel_pf_id,
2909                    p_hwfn->abs_pf_id,
2910                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2911 }
2912
2913 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2914                                     struct qed_ptt *p_ptt)
2915 {
2916         u32 port_mode;
2917
2918         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2919
2920         if (port_mode < 3) {
2921                 p_hwfn->cdev->num_ports_in_engine = 1;
2922         } else if (port_mode <= 5) {
2923                 p_hwfn->cdev->num_ports_in_engine = 2;
2924         } else {
2925                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2926                           p_hwfn->cdev->num_ports_in_engine);
2927
2928                 /* Default num_ports_in_engine to something */
2929                 p_hwfn->cdev->num_ports_in_engine = 1;
2930         }
2931 }
2932
2933 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2934                                     struct qed_ptt *p_ptt)
2935 {
2936         u32 port;
2937         int i;
2938
2939         p_hwfn->cdev->num_ports_in_engine = 0;
2940
2941         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2942                 port = qed_rd(p_hwfn, p_ptt,
2943                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2944                 if (port & 1)
2945                         p_hwfn->cdev->num_ports_in_engine++;
2946         }
2947
2948         if (!p_hwfn->cdev->num_ports_in_engine) {
2949                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2950
2951                 /* Default num_ports_in_engine to something */
2952                 p_hwfn->cdev->num_ports_in_engine = 1;
2953         }
2954 }
2955
2956 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2957 {
2958         if (QED_IS_BB(p_hwfn->cdev))
2959                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2960         else
2961                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2962 }
2963
2964 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2965 {
2966         struct qed_mcp_link_capabilities *p_caps;
2967         u32 eee_status;
2968
2969         p_caps = &p_hwfn->mcp_info->link_capabilities;
2970         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2971                 return;
2972
2973         p_caps->eee_speed_caps = 0;
2974         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2975                             offsetof(struct public_port, eee_status));
2976         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2977                         EEE_SUPPORTED_SPEED_OFFSET;
2978
2979         if (eee_status & EEE_1G_SUPPORTED)
2980                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2981         if (eee_status & EEE_10G_ADV)
2982                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2983 }
2984
2985 static int
2986 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2987                 struct qed_ptt *p_ptt,
2988                 enum qed_pci_personality personality)
2989 {
2990         int rc;
2991
2992         /* Since all information is common, only first hwfns should do this */
2993         if (IS_LEAD_HWFN(p_hwfn)) {
2994                 rc = qed_iov_hw_info(p_hwfn);
2995                 if (rc)
2996                         return rc;
2997         }
2998
2999         qed_hw_info_port_num(p_hwfn, p_ptt);
3000
3001         qed_mcp_get_capabilities(p_hwfn, p_ptt);
3002
3003         qed_hw_get_nvm_info(p_hwfn, p_ptt);
3004
3005         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
3006         if (rc)
3007                 return rc;
3008
3009         if (qed_mcp_is_init(p_hwfn))
3010                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
3011                                 p_hwfn->mcp_info->func_info.mac);
3012         else
3013                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
3014
3015         if (qed_mcp_is_init(p_hwfn)) {
3016                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
3017                         p_hwfn->hw_info.ovlan =
3018                                 p_hwfn->mcp_info->func_info.ovlan;
3019
3020                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
3021
3022                 qed_get_eee_caps(p_hwfn, p_ptt);
3023
3024                 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
3025         }
3026
3027         if (qed_mcp_is_init(p_hwfn)) {
3028                 enum qed_pci_personality protocol;
3029
3030                 protocol = p_hwfn->mcp_info->func_info.protocol;
3031                 p_hwfn->hw_info.personality = protocol;
3032         }
3033
3034         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
3035                 p_hwfn->hw_info.multi_tc_roce_en = 1;
3036
3037         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
3038         p_hwfn->hw_info.num_active_tc = 1;
3039
3040         qed_get_num_funcs(p_hwfn, p_ptt);
3041
3042         if (qed_mcp_is_init(p_hwfn))
3043                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
3044
3045         return qed_hw_get_resc(p_hwfn, p_ptt);
3046 }
3047
3048 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3049 {
3050         struct qed_dev *cdev = p_hwfn->cdev;
3051         u16 device_id_mask;
3052         u32 tmp;
3053
3054         /* Read Vendor Id / Device Id */
3055         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
3056         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
3057
3058         /* Determine type */
3059         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
3060         switch (device_id_mask) {
3061         case QED_DEV_ID_MASK_BB:
3062                 cdev->type = QED_DEV_TYPE_BB;
3063                 break;
3064         case QED_DEV_ID_MASK_AH:
3065                 cdev->type = QED_DEV_TYPE_AH;
3066                 break;
3067         default:
3068                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
3069                 return -EBUSY;
3070         }
3071
3072         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
3073         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
3074
3075         MASK_FIELD(CHIP_REV, cdev->chip_rev);
3076
3077         /* Learn number of HW-functions */
3078         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
3079
3080         if (tmp & (1 << p_hwfn->rel_pf_id)) {
3081                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
3082                 cdev->num_hwfns = 2;
3083         } else {
3084                 cdev->num_hwfns = 1;
3085         }
3086
3087         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
3088                                     MISCS_REG_CHIP_TEST_REG) >> 4;
3089         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
3090         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
3091         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
3092
3093         DP_INFO(cdev->hwfns,
3094                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
3095                 QED_IS_BB(cdev) ? "BB" : "AH",
3096                 'A' + cdev->chip_rev,
3097                 (int)cdev->chip_metal,
3098                 cdev->chip_num, cdev->chip_rev,
3099                 cdev->chip_bond_id, cdev->chip_metal);
3100
3101         return 0;
3102 }
3103
3104 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
3105 {
3106         kfree(p_hwfn->nvm_info.image_att);
3107         p_hwfn->nvm_info.image_att = NULL;
3108 }
3109
3110 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
3111                                  void __iomem *p_regview,
3112                                  void __iomem *p_doorbells,
3113                                  enum qed_pci_personality personality)
3114 {
3115         int rc = 0;
3116
3117         /* Split PCI bars evenly between hwfns */
3118         p_hwfn->regview = p_regview;
3119         p_hwfn->doorbells = p_doorbells;
3120
3121         if (IS_VF(p_hwfn->cdev))
3122                 return qed_vf_hw_prepare(p_hwfn);
3123
3124         /* Validate that chip access is feasible */
3125         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3126                 DP_ERR(p_hwfn,
3127                        "Reading the ME register returns all Fs; Preventing further chip access\n");
3128                 return -EINVAL;
3129         }
3130
3131         get_function_id(p_hwfn);
3132
3133         /* Allocate PTT pool */
3134         rc = qed_ptt_pool_alloc(p_hwfn);
3135         if (rc)
3136                 goto err0;
3137
3138         /* Allocate the main PTT */
3139         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3140
3141         /* First hwfn learns basic information, e.g., number of hwfns */
3142         if (!p_hwfn->my_id) {
3143                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3144                 if (rc)
3145                         goto err1;
3146         }
3147
3148         qed_hw_hwfn_prepare(p_hwfn);
3149
3150         /* Initialize MCP structure */
3151         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3152         if (rc) {
3153                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3154                 goto err1;
3155         }
3156
3157         /* Read the device configuration information from the HW and SHMEM */
3158         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3159         if (rc) {
3160                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3161                 goto err2;
3162         }
3163
3164         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3165          * is called as it sets the ports number in an engine.
3166          */
3167         if (IS_LEAD_HWFN(p_hwfn)) {
3168                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3169                 if (rc)
3170                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3171         }
3172
3173         /* NVRAM info initialization and population */
3174         if (IS_LEAD_HWFN(p_hwfn)) {
3175                 rc = qed_mcp_nvm_info_populate(p_hwfn);
3176                 if (rc) {
3177                         DP_NOTICE(p_hwfn,
3178                                   "Failed to populate nvm info shadow\n");
3179                         goto err2;
3180                 }
3181         }
3182
3183         /* Allocate the init RT array and initialize the init-ops engine */
3184         rc = qed_init_alloc(p_hwfn);
3185         if (rc)
3186                 goto err3;
3187
3188         return rc;
3189 err3:
3190         if (IS_LEAD_HWFN(p_hwfn))
3191                 qed_nvm_info_free(p_hwfn);
3192 err2:
3193         if (IS_LEAD_HWFN(p_hwfn))
3194                 qed_iov_free_hw_info(p_hwfn->cdev);
3195         qed_mcp_free(p_hwfn);
3196 err1:
3197         qed_hw_hwfn_free(p_hwfn);
3198 err0:
3199         return rc;
3200 }
3201
3202 int qed_hw_prepare(struct qed_dev *cdev,
3203                    int personality)
3204 {
3205         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3206         int rc;
3207
3208         /* Store the precompiled init data ptrs */
3209         if (IS_PF(cdev))
3210                 qed_init_iro_array(cdev);
3211
3212         /* Initialize the first hwfn - will learn number of hwfns */
3213         rc = qed_hw_prepare_single(p_hwfn,
3214                                    cdev->regview,
3215                                    cdev->doorbells, personality);
3216         if (rc)
3217                 return rc;
3218
3219         personality = p_hwfn->hw_info.personality;
3220
3221         /* Initialize the rest of the hwfns */
3222         if (cdev->num_hwfns > 1) {
3223                 void __iomem *p_regview, *p_doorbell;
3224                 u8 __iomem *addr;
3225
3226                 /* adjust bar offset for second engine */
3227                 addr = cdev->regview +
3228                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3229                                        BAR_ID_0) / 2;
3230                 p_regview = addr;
3231
3232                 addr = cdev->doorbells +
3233                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3234                                        BAR_ID_1) / 2;
3235                 p_doorbell = addr;
3236
3237                 /* prepare second hw function */
3238                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3239                                            p_doorbell, personality);
3240
3241                 /* in case of error, need to free the previously
3242                  * initiliazed hwfn 0.
3243                  */
3244                 if (rc) {
3245                         if (IS_PF(cdev)) {
3246                                 qed_init_free(p_hwfn);
3247                                 qed_nvm_info_free(p_hwfn);
3248                                 qed_mcp_free(p_hwfn);
3249                                 qed_hw_hwfn_free(p_hwfn);
3250                         }
3251                 }
3252         }
3253
3254         return rc;
3255 }
3256
3257 void qed_hw_remove(struct qed_dev *cdev)
3258 {
3259         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3260         int i;
3261
3262         if (IS_PF(cdev))
3263                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3264                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3265
3266         for_each_hwfn(cdev, i) {
3267                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3268
3269                 if (IS_VF(cdev)) {
3270                         qed_vf_pf_release(p_hwfn);
3271                         continue;
3272                 }
3273
3274                 qed_init_free(p_hwfn);
3275                 qed_hw_hwfn_free(p_hwfn);
3276                 qed_mcp_free(p_hwfn);
3277         }
3278
3279         qed_iov_free_hw_info(cdev);
3280
3281         qed_nvm_info_free(p_hwfn);
3282 }
3283
3284 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3285                                     struct qed_chain *p_chain)
3286 {
3287         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3288         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3289         struct qed_chain_next *p_next;
3290         u32 size, i;
3291
3292         if (!p_virt)
3293                 return;
3294
3295         size = p_chain->elem_size * p_chain->usable_per_page;
3296
3297         for (i = 0; i < p_chain->page_cnt; i++) {
3298                 if (!p_virt)
3299                         break;
3300
3301                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3302                 p_virt_next = p_next->next_virt;
3303                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3304
3305                 dma_free_coherent(&cdev->pdev->dev,
3306                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3307
3308                 p_virt = p_virt_next;
3309                 p_phys = p_phys_next;
3310         }
3311 }
3312
3313 static void qed_chain_free_single(struct qed_dev *cdev,
3314                                   struct qed_chain *p_chain)
3315 {
3316         if (!p_chain->p_virt_addr)
3317                 return;
3318
3319         dma_free_coherent(&cdev->pdev->dev,
3320                           QED_CHAIN_PAGE_SIZE,
3321                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3322 }
3323
3324 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3325 {
3326         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3327         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3328         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3329
3330         if (!pp_virt_addr_tbl)
3331                 return;
3332
3333         if (!p_pbl_virt)
3334                 goto out;
3335
3336         for (i = 0; i < page_cnt; i++) {
3337                 if (!pp_virt_addr_tbl[i])
3338                         break;
3339
3340                 dma_free_coherent(&cdev->pdev->dev,
3341                                   QED_CHAIN_PAGE_SIZE,
3342                                   pp_virt_addr_tbl[i],
3343                                   *(dma_addr_t *)p_pbl_virt);
3344
3345                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3346         }
3347
3348         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3349
3350         if (!p_chain->b_external_pbl)
3351                 dma_free_coherent(&cdev->pdev->dev,
3352                                   pbl_size,
3353                                   p_chain->pbl_sp.p_virt_table,
3354                                   p_chain->pbl_sp.p_phys_table);
3355 out:
3356         vfree(p_chain->pbl.pp_virt_addr_tbl);
3357         p_chain->pbl.pp_virt_addr_tbl = NULL;
3358 }
3359
3360 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3361 {
3362         switch (p_chain->mode) {
3363         case QED_CHAIN_MODE_NEXT_PTR:
3364                 qed_chain_free_next_ptr(cdev, p_chain);
3365                 break;
3366         case QED_CHAIN_MODE_SINGLE:
3367                 qed_chain_free_single(cdev, p_chain);
3368                 break;
3369         case QED_CHAIN_MODE_PBL:
3370                 qed_chain_free_pbl(cdev, p_chain);
3371                 break;
3372         }
3373 }
3374
3375 static int
3376 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3377                              enum qed_chain_cnt_type cnt_type,
3378                              size_t elem_size, u32 page_cnt)
3379 {
3380         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3381
3382         /* The actual chain size can be larger than the maximal possible value
3383          * after rounding up the requested elements number to pages, and after
3384          * taking into acount the unusuable elements (next-ptr elements).
3385          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3386          * size/capacity fields are of a u32 type.
3387          */
3388         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3389              chain_size > ((u32)U16_MAX + 1)) ||
3390             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3391                 DP_NOTICE(cdev,
3392                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3393                           chain_size);
3394                 return -EINVAL;
3395         }
3396
3397         return 0;
3398 }
3399
3400 static int
3401 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3402 {
3403         void *p_virt = NULL, *p_virt_prev = NULL;
3404         dma_addr_t p_phys = 0;
3405         u32 i;
3406
3407         for (i = 0; i < p_chain->page_cnt; i++) {
3408                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3409                                             QED_CHAIN_PAGE_SIZE,
3410                                             &p_phys, GFP_KERNEL);
3411                 if (!p_virt)
3412                         return -ENOMEM;
3413
3414                 if (i == 0) {
3415                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3416                         qed_chain_reset(p_chain);
3417                 } else {
3418                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3419                                                      p_virt, p_phys);
3420                 }
3421
3422                 p_virt_prev = p_virt;
3423         }
3424         /* Last page's next element should point to the beginning of the
3425          * chain.
3426          */
3427         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3428                                      p_chain->p_virt_addr,
3429                                      p_chain->p_phys_addr);
3430
3431         return 0;
3432 }
3433
3434 static int
3435 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3436 {
3437         dma_addr_t p_phys = 0;
3438         void *p_virt = NULL;
3439
3440         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3441                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3442         if (!p_virt)
3443                 return -ENOMEM;
3444
3445         qed_chain_init_mem(p_chain, p_virt, p_phys);
3446         qed_chain_reset(p_chain);
3447
3448         return 0;
3449 }
3450
3451 static int
3452 qed_chain_alloc_pbl(struct qed_dev *cdev,
3453                     struct qed_chain *p_chain,
3454                     struct qed_chain_ext_pbl *ext_pbl)
3455 {
3456         u32 page_cnt = p_chain->page_cnt, size, i;
3457         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3458         void **pp_virt_addr_tbl = NULL;
3459         u8 *p_pbl_virt = NULL;
3460         void *p_virt = NULL;
3461
3462         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3463         pp_virt_addr_tbl = vzalloc(size);
3464         if (!pp_virt_addr_tbl)
3465                 return -ENOMEM;
3466
3467         /* The allocation of the PBL table is done with its full size, since it
3468          * is expected to be successive.
3469          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3470          * failure, since pp_virt_addr_tbl was previously allocated, and it
3471          * should be saved to allow its freeing during the error flow.
3472          */
3473         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3474
3475         if (!ext_pbl) {
3476                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3477                                                 size, &p_pbl_phys, GFP_KERNEL);
3478         } else {
3479                 p_pbl_virt = ext_pbl->p_pbl_virt;
3480                 p_pbl_phys = ext_pbl->p_pbl_phys;
3481                 p_chain->b_external_pbl = true;
3482         }
3483
3484         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3485                                pp_virt_addr_tbl);
3486         if (!p_pbl_virt)
3487                 return -ENOMEM;
3488
3489         for (i = 0; i < page_cnt; i++) {
3490                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3491                                             QED_CHAIN_PAGE_SIZE,
3492                                             &p_phys, GFP_KERNEL);
3493                 if (!p_virt)
3494                         return -ENOMEM;
3495
3496                 if (i == 0) {
3497                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3498                         qed_chain_reset(p_chain);
3499                 }
3500
3501                 /* Fill the PBL table with the physical address of the page */
3502                 *(dma_addr_t *)p_pbl_virt = p_phys;
3503                 /* Keep the virtual address of the page */
3504                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3505
3506                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3507         }
3508
3509         return 0;
3510 }
3511
3512 int qed_chain_alloc(struct qed_dev *cdev,
3513                     enum qed_chain_use_mode intended_use,
3514                     enum qed_chain_mode mode,
3515                     enum qed_chain_cnt_type cnt_type,
3516                     u32 num_elems,
3517                     size_t elem_size,
3518                     struct qed_chain *p_chain,
3519                     struct qed_chain_ext_pbl *ext_pbl)
3520 {
3521         u32 page_cnt;
3522         int rc = 0;
3523
3524         if (mode == QED_CHAIN_MODE_SINGLE)
3525                 page_cnt = 1;
3526         else
3527                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3528
3529         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3530         if (rc) {
3531                 DP_NOTICE(cdev,
3532                           "Cannot allocate a chain with the given arguments:\n");
3533                 DP_NOTICE(cdev,
3534                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3535                           intended_use, mode, cnt_type, num_elems, elem_size);
3536                 return rc;
3537         }
3538
3539         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3540                               mode, cnt_type);
3541
3542         switch (mode) {
3543         case QED_CHAIN_MODE_NEXT_PTR:
3544                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3545                 break;
3546         case QED_CHAIN_MODE_SINGLE:
3547                 rc = qed_chain_alloc_single(cdev, p_chain);
3548                 break;
3549         case QED_CHAIN_MODE_PBL:
3550                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3551                 break;
3552         }
3553         if (rc)
3554                 goto nomem;
3555
3556         return 0;
3557
3558 nomem:
3559         qed_chain_free(cdev, p_chain);
3560         return rc;
3561 }
3562
3563 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3564 {
3565         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3566                 u16 min, max;
3567
3568                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3569                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3570                 DP_NOTICE(p_hwfn,
3571                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3572                           src_id, min, max);
3573
3574                 return -EINVAL;
3575         }
3576
3577         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3578
3579         return 0;
3580 }
3581
3582 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3583 {
3584         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3585                 u8 min, max;
3586
3587                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3588                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3589                 DP_NOTICE(p_hwfn,
3590                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3591                           src_id, min, max);
3592
3593                 return -EINVAL;
3594         }
3595
3596         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3597
3598         return 0;
3599 }
3600
3601 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3602 {
3603         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3604                 u8 min, max;
3605
3606                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3607                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3608                 DP_NOTICE(p_hwfn,
3609                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3610                           src_id, min, max);
3611
3612                 return -EINVAL;
3613         }
3614
3615         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3616
3617         return 0;
3618 }
3619
3620 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3621                                   u8 *p_filter)
3622 {
3623         *p_high = p_filter[1] | (p_filter[0] << 8);
3624         *p_low = p_filter[5] | (p_filter[4] << 8) |
3625                  (p_filter[3] << 16) | (p_filter[2] << 24);
3626 }
3627
3628 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3629                            struct qed_ptt *p_ptt, u8 *p_filter)
3630 {
3631         u32 high = 0, low = 0, en;
3632         int i;
3633
3634         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3635                 return 0;
3636
3637         qed_llh_mac_to_filter(&high, &low, p_filter);
3638
3639         /* Find a free entry and utilize it */
3640         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3641                 en = qed_rd(p_hwfn, p_ptt,
3642                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3643                 if (en)
3644                         continue;
3645                 qed_wr(p_hwfn, p_ptt,
3646                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3647                        2 * i * sizeof(u32), low);
3648                 qed_wr(p_hwfn, p_ptt,
3649                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3650                        (2 * i + 1) * sizeof(u32), high);
3651                 qed_wr(p_hwfn, p_ptt,
3652                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3653                 qed_wr(p_hwfn, p_ptt,
3654                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3655                        i * sizeof(u32), 0);
3656                 qed_wr(p_hwfn, p_ptt,
3657                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3658                 break;
3659         }
3660         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3661                 DP_NOTICE(p_hwfn,
3662                           "Failed to find an empty LLH filter to utilize\n");
3663                 return -EINVAL;
3664         }
3665
3666         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3667                    "mac: %pM is added at %d\n",
3668                    p_filter, i);
3669
3670         return 0;
3671 }
3672
3673 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3674                                struct qed_ptt *p_ptt, u8 *p_filter)
3675 {
3676         u32 high = 0, low = 0;
3677         int i;
3678
3679         if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3680                 return;
3681
3682         qed_llh_mac_to_filter(&high, &low, p_filter);
3683
3684         /* Find the entry and clean it */
3685         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3686                 if (qed_rd(p_hwfn, p_ptt,
3687                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3688                            2 * i * sizeof(u32)) != low)
3689                         continue;
3690                 if (qed_rd(p_hwfn, p_ptt,
3691                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3692                            (2 * i + 1) * sizeof(u32)) != high)
3693                         continue;
3694
3695                 qed_wr(p_hwfn, p_ptt,
3696                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3697                 qed_wr(p_hwfn, p_ptt,
3698                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3699                 qed_wr(p_hwfn, p_ptt,
3700                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3701                        (2 * i + 1) * sizeof(u32), 0);
3702
3703                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3704                            "mac: %pM is removed from %d\n",
3705                            p_filter, i);
3706                 break;
3707         }
3708         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3709                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3710 }
3711
3712 int
3713 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3714                             struct qed_ptt *p_ptt,
3715                             u16 source_port_or_eth_type,
3716                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3717 {
3718         u32 high = 0, low = 0, en;
3719         int i;
3720
3721         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3722                 return 0;
3723
3724         switch (type) {
3725         case QED_LLH_FILTER_ETHERTYPE:
3726                 high = source_port_or_eth_type;
3727                 break;
3728         case QED_LLH_FILTER_TCP_SRC_PORT:
3729         case QED_LLH_FILTER_UDP_SRC_PORT:
3730                 low = source_port_or_eth_type << 16;
3731                 break;
3732         case QED_LLH_FILTER_TCP_DEST_PORT:
3733         case QED_LLH_FILTER_UDP_DEST_PORT:
3734                 low = dest_port;
3735                 break;
3736         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3737         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3738                 low = (source_port_or_eth_type << 16) | dest_port;
3739                 break;
3740         default:
3741                 DP_NOTICE(p_hwfn,
3742                           "Non valid LLH protocol filter type %d\n", type);
3743                 return -EINVAL;
3744         }
3745         /* Find a free entry and utilize it */
3746         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3747                 en = qed_rd(p_hwfn, p_ptt,
3748                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3749                 if (en)
3750                         continue;
3751                 qed_wr(p_hwfn, p_ptt,
3752                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3753                        2 * i * sizeof(u32), low);
3754                 qed_wr(p_hwfn, p_ptt,
3755                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3756                        (2 * i + 1) * sizeof(u32), high);
3757                 qed_wr(p_hwfn, p_ptt,
3758                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3759                 qed_wr(p_hwfn, p_ptt,
3760                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3761                        i * sizeof(u32), 1 << type);
3762                 qed_wr(p_hwfn, p_ptt,
3763                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3764                 break;
3765         }
3766         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3767                 DP_NOTICE(p_hwfn,
3768                           "Failed to find an empty LLH filter to utilize\n");
3769                 return -EINVAL;
3770         }
3771         switch (type) {
3772         case QED_LLH_FILTER_ETHERTYPE:
3773                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3774                            "ETH type %x is added at %d\n",
3775                            source_port_or_eth_type, i);
3776                 break;
3777         case QED_LLH_FILTER_TCP_SRC_PORT:
3778                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3779                            "TCP src port %x is added at %d\n",
3780                            source_port_or_eth_type, i);
3781                 break;
3782         case QED_LLH_FILTER_UDP_SRC_PORT:
3783                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3784                            "UDP src port %x is added at %d\n",
3785                            source_port_or_eth_type, i);
3786                 break;
3787         case QED_LLH_FILTER_TCP_DEST_PORT:
3788                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3789                            "TCP dst port %x is added at %d\n", dest_port, i);
3790                 break;
3791         case QED_LLH_FILTER_UDP_DEST_PORT:
3792                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3793                            "UDP dst port %x is added at %d\n", dest_port, i);
3794                 break;
3795         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3796                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3797                            "TCP src/dst ports %x/%x are added at %d\n",
3798                            source_port_or_eth_type, dest_port, i);
3799                 break;
3800         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3801                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3802                            "UDP src/dst ports %x/%x are added at %d\n",
3803                            source_port_or_eth_type, dest_port, i);
3804                 break;
3805         }
3806         return 0;
3807 }
3808
3809 void
3810 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3811                                struct qed_ptt *p_ptt,
3812                                u16 source_port_or_eth_type,
3813                                u16 dest_port,
3814                                enum qed_llh_port_filter_type_t type)
3815 {
3816         u32 high = 0, low = 0;
3817         int i;
3818
3819         if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3820                 return;
3821
3822         switch (type) {
3823         case QED_LLH_FILTER_ETHERTYPE:
3824                 high = source_port_or_eth_type;
3825                 break;
3826         case QED_LLH_FILTER_TCP_SRC_PORT:
3827         case QED_LLH_FILTER_UDP_SRC_PORT:
3828                 low = source_port_or_eth_type << 16;
3829                 break;
3830         case QED_LLH_FILTER_TCP_DEST_PORT:
3831         case QED_LLH_FILTER_UDP_DEST_PORT:
3832                 low = dest_port;
3833                 break;
3834         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3835         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3836                 low = (source_port_or_eth_type << 16) | dest_port;
3837                 break;
3838         default:
3839                 DP_NOTICE(p_hwfn,
3840                           "Non valid LLH protocol filter type %d\n", type);
3841                 return;
3842         }
3843
3844         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3845                 if (!qed_rd(p_hwfn, p_ptt,
3846                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3847                         continue;
3848                 if (!qed_rd(p_hwfn, p_ptt,
3849                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3850                         continue;
3851                 if (!(qed_rd(p_hwfn, p_ptt,
3852                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3853                              i * sizeof(u32)) & BIT(type)))
3854                         continue;
3855                 if (qed_rd(p_hwfn, p_ptt,
3856                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3857                            2 * i * sizeof(u32)) != low)
3858                         continue;
3859                 if (qed_rd(p_hwfn, p_ptt,
3860                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3861                            (2 * i + 1) * sizeof(u32)) != high)
3862                         continue;
3863
3864                 qed_wr(p_hwfn, p_ptt,
3865                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3866                 qed_wr(p_hwfn, p_ptt,
3867                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3868                 qed_wr(p_hwfn, p_ptt,
3869                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3870                        i * sizeof(u32), 0);
3871                 qed_wr(p_hwfn, p_ptt,
3872                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3873                 qed_wr(p_hwfn, p_ptt,
3874                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3875                        (2 * i + 1) * sizeof(u32), 0);
3876                 break;
3877         }
3878
3879         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3880                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3881 }
3882
3883 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3884                             u32 hw_addr, void *p_eth_qzone,
3885                             size_t eth_qzone_size, u8 timeset)
3886 {
3887         struct coalescing_timeset *p_coal_timeset;
3888
3889         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3890                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3891                 return -EINVAL;
3892         }
3893
3894         p_coal_timeset = p_eth_qzone;
3895         memset(p_eth_qzone, 0, eth_qzone_size);
3896         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3897         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3898         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3899
3900         return 0;
3901 }
3902
3903 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3904 {
3905         struct qed_queue_cid *p_cid = p_handle;
3906         struct qed_hwfn *p_hwfn;
3907         struct qed_ptt *p_ptt;
3908         int rc = 0;
3909
3910         p_hwfn = p_cid->p_owner;
3911
3912         if (IS_VF(p_hwfn->cdev))
3913                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3914
3915         p_ptt = qed_ptt_acquire(p_hwfn);
3916         if (!p_ptt)
3917                 return -EAGAIN;
3918
3919         if (rx_coal) {
3920                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3921                 if (rc)
3922                         goto out;
3923                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3924         }
3925
3926         if (tx_coal) {
3927                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3928                 if (rc)
3929                         goto out;
3930                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3931         }
3932 out:
3933         qed_ptt_release(p_hwfn, p_ptt);
3934         return rc;
3935 }
3936
3937 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3938                          struct qed_ptt *p_ptt,
3939                          u16 coalesce, struct qed_queue_cid *p_cid)
3940 {
3941         struct ustorm_eth_queue_zone eth_qzone;
3942         u8 timeset, timer_res;
3943         u32 address;
3944         int rc;
3945
3946         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3947         if (coalesce <= 0x7F) {
3948                 timer_res = 0;
3949         } else if (coalesce <= 0xFF) {
3950                 timer_res = 1;
3951         } else if (coalesce <= 0x1FF) {
3952                 timer_res = 2;
3953         } else {
3954                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3955                 return -EINVAL;
3956         }
3957         timeset = (u8)(coalesce >> timer_res);
3958
3959         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3960                                    p_cid->sb_igu_id, false);
3961         if (rc)
3962                 goto out;
3963
3964         address = BAR0_MAP_REG_USDM_RAM +
3965                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3966
3967         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3968                               sizeof(struct ustorm_eth_queue_zone), timeset);
3969         if (rc)
3970                 goto out;
3971
3972 out:
3973         return rc;
3974 }
3975
3976 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3977                          struct qed_ptt *p_ptt,
3978                          u16 coalesce, struct qed_queue_cid *p_cid)
3979 {
3980         struct xstorm_eth_queue_zone eth_qzone;
3981         u8 timeset, timer_res;
3982         u32 address;
3983         int rc;
3984
3985         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3986         if (coalesce <= 0x7F) {
3987                 timer_res = 0;
3988         } else if (coalesce <= 0xFF) {
3989                 timer_res = 1;
3990         } else if (coalesce <= 0x1FF) {
3991                 timer_res = 2;
3992         } else {
3993                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3994                 return -EINVAL;
3995         }
3996         timeset = (u8)(coalesce >> timer_res);
3997
3998         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3999                                    p_cid->sb_igu_id, true);
4000         if (rc)
4001                 goto out;
4002
4003         address = BAR0_MAP_REG_XSDM_RAM +
4004                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4005
4006         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
4007                               sizeof(struct xstorm_eth_queue_zone), timeset);
4008 out:
4009         return rc;
4010 }
4011
4012 /* Calculate final WFQ values for all vports and configure them.
4013  * After this configuration each vport will have
4014  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
4015  */
4016 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4017                                              struct qed_ptt *p_ptt,
4018                                              u32 min_pf_rate)
4019 {
4020         struct init_qm_vport_params *vport_params;
4021         int i;
4022
4023         vport_params = p_hwfn->qm_info.qm_vport_params;
4024
4025         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4026                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4027
4028                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
4029                                                 min_pf_rate;
4030                 qed_init_vport_wfq(p_hwfn, p_ptt,
4031                                    vport_params[i].first_tx_pq_id,
4032                                    vport_params[i].vport_wfq);
4033         }
4034 }
4035
4036 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4037                                        u32 min_pf_rate)
4038
4039 {
4040         int i;
4041
4042         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4043                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
4044 }
4045
4046 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4047                                            struct qed_ptt *p_ptt,
4048                                            u32 min_pf_rate)
4049 {
4050         struct init_qm_vport_params *vport_params;
4051         int i;
4052
4053         vport_params = p_hwfn->qm_info.qm_vport_params;
4054
4055         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4056                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
4057                 qed_init_vport_wfq(p_hwfn, p_ptt,
4058                                    vport_params[i].first_tx_pq_id,
4059                                    vport_params[i].vport_wfq);
4060         }
4061 }
4062
4063 /* This function performs several validations for WFQ
4064  * configuration and required min rate for a given vport
4065  * 1. req_rate must be greater than one percent of min_pf_rate.
4066  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
4067  *    rates to get less than one percent of min_pf_rate.
4068  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
4069  */
4070 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
4071                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
4072 {
4073         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
4074         int non_requested_count = 0, req_count = 0, i, num_vports;
4075
4076         num_vports = p_hwfn->qm_info.num_vports;
4077
4078         /* Accounting for the vports which are configured for WFQ explicitly */
4079         for (i = 0; i < num_vports; i++) {
4080                 u32 tmp_speed;
4081
4082                 if ((i != vport_id) &&
4083                     p_hwfn->qm_info.wfq_data[i].configured) {
4084                         req_count++;
4085                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4086                         total_req_min_rate += tmp_speed;
4087                 }
4088         }
4089
4090         /* Include current vport data as well */
4091         req_count++;
4092         total_req_min_rate += req_rate;
4093         non_requested_count = num_vports - req_count;
4094
4095         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
4096                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4097                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4098                            vport_id, req_rate, min_pf_rate);
4099                 return -EINVAL;
4100         }
4101
4102         if (num_vports > QED_WFQ_UNIT) {
4103                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4104                            "Number of vports is greater than %d\n",
4105                            QED_WFQ_UNIT);
4106                 return -EINVAL;
4107         }
4108
4109         if (total_req_min_rate > min_pf_rate) {
4110                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4111                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
4112                            total_req_min_rate, min_pf_rate);
4113                 return -EINVAL;
4114         }
4115
4116         total_left_rate = min_pf_rate - total_req_min_rate;
4117
4118         left_rate_per_vp = total_left_rate / non_requested_count;
4119         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
4120                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4121                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
4122                            left_rate_per_vp, min_pf_rate);
4123                 return -EINVAL;
4124         }
4125
4126         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4127         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4128
4129         for (i = 0; i < num_vports; i++) {
4130                 if (p_hwfn->qm_info.wfq_data[i].configured)
4131                         continue;
4132
4133                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4134         }
4135
4136         return 0;
4137 }
4138
4139 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4140                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4141 {
4142         struct qed_mcp_link_state *p_link;
4143         int rc = 0;
4144
4145         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4146
4147         if (!p_link->min_pf_rate) {
4148                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4149                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4150                 return rc;
4151         }
4152
4153         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4154
4155         if (!rc)
4156                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4157                                                  p_link->min_pf_rate);
4158         else
4159                 DP_NOTICE(p_hwfn,
4160                           "Validation failed while configuring min rate\n");
4161
4162         return rc;
4163 }
4164
4165 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4166                                                  struct qed_ptt *p_ptt,
4167                                                  u32 min_pf_rate)
4168 {
4169         bool use_wfq = false;
4170         int rc = 0;
4171         u16 i;
4172
4173         /* Validate all pre configured vports for wfq */
4174         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4175                 u32 rate;
4176
4177                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4178                         continue;
4179
4180                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4181                 use_wfq = true;
4182
4183                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4184                 if (rc) {
4185                         DP_NOTICE(p_hwfn,
4186                                   "WFQ validation failed while configuring min rate\n");
4187                         break;
4188                 }
4189         }
4190
4191         if (!rc && use_wfq)
4192                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4193         else
4194                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4195
4196         return rc;
4197 }
4198
4199 /* Main API for qed clients to configure vport min rate.
4200  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4201  * rate - Speed in Mbps needs to be assigned to a given vport.
4202  */
4203 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4204 {
4205         int i, rc = -EINVAL;
4206
4207         /* Currently not supported; Might change in future */
4208         if (cdev->num_hwfns > 1) {
4209                 DP_NOTICE(cdev,
4210                           "WFQ configuration is not supported for this device\n");
4211                 return rc;
4212         }
4213
4214         for_each_hwfn(cdev, i) {
4215                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4216                 struct qed_ptt *p_ptt;
4217
4218                 p_ptt = qed_ptt_acquire(p_hwfn);
4219                 if (!p_ptt)
4220                         return -EBUSY;
4221
4222                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4223
4224                 if (rc) {
4225                         qed_ptt_release(p_hwfn, p_ptt);
4226                         return rc;
4227                 }
4228
4229                 qed_ptt_release(p_hwfn, p_ptt);
4230         }
4231
4232         return rc;
4233 }
4234
4235 /* API to configure WFQ from mcp link change */
4236 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4237                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
4238 {
4239         int i;
4240
4241         if (cdev->num_hwfns > 1) {
4242                 DP_VERBOSE(cdev,
4243                            NETIF_MSG_LINK,
4244                            "WFQ configuration is not supported for this device\n");
4245                 return;
4246         }
4247
4248         for_each_hwfn(cdev, i) {
4249                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4250
4251                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4252                                                       min_pf_rate);
4253         }
4254 }
4255
4256 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4257                                      struct qed_ptt *p_ptt,
4258                                      struct qed_mcp_link_state *p_link,
4259                                      u8 max_bw)
4260 {
4261         int rc = 0;
4262
4263         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4264
4265         if (!p_link->line_speed && (max_bw != 100))
4266                 return rc;
4267
4268         p_link->speed = (p_link->line_speed * max_bw) / 100;
4269         p_hwfn->qm_info.pf_rl = p_link->speed;
4270
4271         /* Since the limiter also affects Tx-switched traffic, we don't want it
4272          * to limit such traffic in case there's no actual limit.
4273          * In that case, set limit to imaginary high boundary.
4274          */
4275         if (max_bw == 100)
4276                 p_hwfn->qm_info.pf_rl = 100000;
4277
4278         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4279                             p_hwfn->qm_info.pf_rl);
4280
4281         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4282                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4283                    p_link->speed);
4284
4285         return rc;
4286 }
4287
4288 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4289 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4290 {
4291         int i, rc = -EINVAL;
4292
4293         if (max_bw < 1 || max_bw > 100) {
4294                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4295                 return rc;
4296         }
4297
4298         for_each_hwfn(cdev, i) {
4299                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4300                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4301                 struct qed_mcp_link_state *p_link;
4302                 struct qed_ptt *p_ptt;
4303
4304                 p_link = &p_lead->mcp_info->link_output;
4305
4306                 p_ptt = qed_ptt_acquire(p_hwfn);
4307                 if (!p_ptt)
4308                         return -EBUSY;
4309
4310                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4311                                                       p_link, max_bw);
4312
4313                 qed_ptt_release(p_hwfn, p_ptt);
4314
4315                 if (rc)
4316                         break;
4317         }
4318
4319         return rc;
4320 }
4321
4322 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4323                                      struct qed_ptt *p_ptt,
4324                                      struct qed_mcp_link_state *p_link,
4325                                      u8 min_bw)
4326 {
4327         int rc = 0;
4328
4329         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4330         p_hwfn->qm_info.pf_wfq = min_bw;
4331
4332         if (!p_link->line_speed)
4333                 return rc;
4334
4335         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4336
4337         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4338
4339         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4340                    "Configured MIN bandwidth to be %d Mb/sec\n",
4341                    p_link->min_pf_rate);
4342
4343         return rc;
4344 }
4345
4346 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4347 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4348 {
4349         int i, rc = -EINVAL;
4350
4351         if (min_bw < 1 || min_bw > 100) {
4352                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4353                 return rc;
4354         }
4355
4356         for_each_hwfn(cdev, i) {
4357                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4358                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4359                 struct qed_mcp_link_state *p_link;
4360                 struct qed_ptt *p_ptt;
4361
4362                 p_link = &p_lead->mcp_info->link_output;
4363
4364                 p_ptt = qed_ptt_acquire(p_hwfn);
4365                 if (!p_ptt)
4366                         return -EBUSY;
4367
4368                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4369                                                       p_link, min_bw);
4370                 if (rc) {
4371                         qed_ptt_release(p_hwfn, p_ptt);
4372                         return rc;
4373                 }
4374
4375                 if (p_link->min_pf_rate) {
4376                         u32 min_rate = p_link->min_pf_rate;
4377
4378                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4379                                                                    p_ptt,
4380                                                                    min_rate);
4381                 }
4382
4383                 qed_ptt_release(p_hwfn, p_ptt);
4384         }
4385
4386         return rc;
4387 }
4388
4389 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4390 {
4391         struct qed_mcp_link_state *p_link;
4392
4393         p_link = &p_hwfn->mcp_info->link_output;
4394
4395         if (p_link->min_pf_rate)
4396                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4397                                                p_link->min_pf_rate);
4398
4399         memset(p_hwfn->qm_info.wfq_data, 0,
4400                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4401 }
4402
4403 int qed_device_num_engines(struct qed_dev *cdev)
4404 {
4405         return QED_IS_BB(cdev) ? 2 : 1;
4406 }
4407
4408 static int qed_device_num_ports(struct qed_dev *cdev)
4409 {
4410         /* in CMT always only one port */
4411         if (cdev->num_hwfns > 1)
4412                 return 1;
4413
4414         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4415 }
4416
4417 int qed_device_get_port_id(struct qed_dev *cdev)
4418 {
4419         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4420 }
4421
4422 void qed_set_fw_mac_addr(__le16 *fw_msb,
4423                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4424 {
4425         ((u8 *)fw_msb)[0] = mac[1];
4426         ((u8 *)fw_msb)[1] = mac[0];
4427         ((u8 *)fw_mid)[0] = mac[3];
4428         ((u8 *)fw_mid)[1] = mac[2];
4429         ((u8 *)fw_lsb)[0] = mac[5];
4430         ((u8 *)fw_lsb)[1] = mac[4];
4431 }