1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
40 #include <linux/mutex.h>
41 #include <linux/pci.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/vmalloc.h>
45 #include <linux/etherdevice.h>
46 #include <linux/qed/qed_chain.h>
47 #include <linux/qed/qed_if.h>
51 #include "qed_dev_api.h"
55 #include "qed_init_ops.h"
57 #include "qed_iscsi.h"
61 #include "qed_reg_addr.h"
63 #include "qed_sriov.h"
67 static DEFINE_SPINLOCK(qm_lock);
69 /******************** Doorbell Recovery *******************/
70 /* The doorbell recovery mechanism consists of a list of entries which represent
71 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
72 * entity needs to register with the mechanism and provide the parameters
73 * describing it's doorbell, including a location where last used doorbell data
74 * can be found. The doorbell execute function will traverse the list and
75 * doorbell all of the registered entries.
77 struct qed_db_recovery_entry {
78 struct list_head list_entry;
79 void __iomem *db_addr;
81 enum qed_db_rec_width db_width;
82 enum qed_db_rec_space db_space;
86 /* Display a single doorbell recovery entry */
87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
88 struct qed_db_recovery_entry *db_entry,
93 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
98 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
99 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
103 /* Doorbell address sanity (address within doorbell bar range) */
104 static bool qed_db_rec_sanity(struct qed_dev *cdev,
105 void __iomem *db_addr,
106 enum qed_db_rec_width db_width,
109 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
111 /* Make sure doorbell address is within the doorbell bar */
112 if (db_addr < cdev->doorbells ||
113 (u8 __iomem *)db_addr + width >
114 (u8 __iomem *)cdev->doorbells + cdev->db_size) {
116 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
119 (u8 __iomem *)cdev->doorbells + cdev->db_size);
123 /* ake sure doorbell data pointer is not null */
125 WARN(true, "Illegal doorbell data pointer: %p", db_data);
132 /* Find hwfn according to the doorbell address */
133 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
134 void __iomem *db_addr)
136 struct qed_hwfn *p_hwfn;
138 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
139 if (cdev->num_hwfns > 1)
140 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
141 &cdev->hwfns[0] : &cdev->hwfns[1];
143 p_hwfn = QED_LEADING_HWFN(cdev);
148 /* Add a new entry to the doorbell recovery mechanism */
149 int qed_db_recovery_add(struct qed_dev *cdev,
150 void __iomem *db_addr,
152 enum qed_db_rec_width db_width,
153 enum qed_db_rec_space db_space)
155 struct qed_db_recovery_entry *db_entry;
156 struct qed_hwfn *p_hwfn;
158 /* Shortcircuit VFs, for now */
161 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
165 /* Sanitize doorbell address */
166 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
169 /* Obtain hwfn from doorbell address */
170 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
173 db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
175 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
180 db_entry->db_addr = db_addr;
181 db_entry->db_data = db_data;
182 db_entry->db_width = db_width;
183 db_entry->db_space = db_space;
184 db_entry->hwfn_idx = p_hwfn->my_id;
187 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
189 /* Protect the list */
190 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
191 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
192 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
197 /* Remove an entry from the doorbell recovery mechanism */
198 int qed_db_recovery_del(struct qed_dev *cdev,
199 void __iomem *db_addr, void *db_data)
201 struct qed_db_recovery_entry *db_entry = NULL;
202 struct qed_hwfn *p_hwfn;
205 /* Shortcircuit VFs, for now */
208 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
212 /* Obtain hwfn from doorbell address */
213 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
215 /* Protect the list */
216 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
217 list_for_each_entry(db_entry,
218 &p_hwfn->db_recovery_info.list, list_entry) {
219 /* search according to db_data addr since db_addr is not unique (roce) */
220 if (db_entry->db_data == db_data) {
221 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
222 list_del(&db_entry->list_entry);
228 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
233 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
241 /* Initialize the doorbell recovery mechanism */
242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
244 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
246 /* Make sure db_size was set in cdev */
247 if (!p_hwfn->cdev->db_size) {
248 DP_ERR(p_hwfn->cdev, "db_size not set\n");
252 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
253 spin_lock_init(&p_hwfn->db_recovery_info.lock);
254 p_hwfn->db_recovery_info.db_recovery_counter = 0;
259 /* Destroy the doorbell recovery mechanism */
260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
262 struct qed_db_recovery_entry *db_entry = NULL;
264 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
265 if (!list_empty(&p_hwfn->db_recovery_info.list)) {
268 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
269 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
271 list_first_entry(&p_hwfn->db_recovery_info.list,
272 struct qed_db_recovery_entry,
274 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
275 list_del(&db_entry->list_entry);
279 p_hwfn->db_recovery_info.db_recovery_counter = 0;
282 /* Print the content of the doorbell recovery mechanism */
283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
285 struct qed_db_recovery_entry *db_entry = NULL;
288 "Displaying doorbell recovery database. Counter was %d\n",
289 p_hwfn->db_recovery_info.db_recovery_counter);
291 /* Protect the list */
292 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
293 list_for_each_entry(db_entry,
294 &p_hwfn->db_recovery_info.list, list_entry) {
295 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
298 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
301 /* Ring the doorbell of a single doorbell recovery entry */
302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
303 struct qed_db_recovery_entry *db_entry)
305 /* Print according to width */
306 if (db_entry->db_width == DB_REC_WIDTH_32B) {
307 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
308 "ringing doorbell address %p data %x\n",
310 *(u32 *)db_entry->db_data);
312 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
313 "ringing doorbell address %p data %llx\n",
315 *(u64 *)(db_entry->db_data));
319 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
320 db_entry->db_width, db_entry->db_data))
323 /* Flush the write combined buffer. Since there are multiple doorbelling
324 * entities using the same address, if we don't flush, a transaction
329 /* Ring the doorbell */
330 if (db_entry->db_width == DB_REC_WIDTH_32B)
331 DIRECT_REG_WR(db_entry->db_addr,
332 *(u32 *)(db_entry->db_data));
334 DIRECT_REG_WR64(db_entry->db_addr,
335 *(u64 *)(db_entry->db_data));
337 /* Flush the write combined buffer. Next doorbell may come from a
338 * different entity to the same address...
343 /* Traverse the doorbell recovery entry list and ring all the doorbells */
344 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
346 struct qed_db_recovery_entry *db_entry = NULL;
348 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
349 p_hwfn->db_recovery_info.db_recovery_counter);
351 /* Track amount of times recovery was executed */
352 p_hwfn->db_recovery_info.db_recovery_counter++;
354 /* Protect the list */
355 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
356 list_for_each_entry(db_entry,
357 &p_hwfn->db_recovery_info.list, list_entry)
358 qed_db_recovery_ring(p_hwfn, db_entry);
359 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
362 /******************** Doorbell Recovery end ****************/
364 /********************************** NIG LLH ***********************************/
366 enum qed_llh_filter_type {
367 QED_LLH_FILTER_TYPE_MAC,
368 QED_LLH_FILTER_TYPE_PROTOCOL,
371 struct qed_llh_mac_filter {
375 struct qed_llh_protocol_filter {
376 enum qed_llh_prot_filter_type_t type;
377 u16 source_port_or_eth_type;
381 union qed_llh_filter {
382 struct qed_llh_mac_filter mac;
383 struct qed_llh_protocol_filter protocol;
386 struct qed_llh_filter_info {
389 enum qed_llh_filter_type type;
390 union qed_llh_filter filter;
393 struct qed_llh_info {
394 /* Number of LLH filters banks */
397 #define MAX_NUM_PPFID 8
398 u8 ppfid_array[MAX_NUM_PPFID];
400 /* Array of filters arrays:
401 * "num_ppfid" elements of filters banks, where each is an array of
402 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
404 struct qed_llh_filter_info **pp_filters;
407 static void qed_llh_free(struct qed_dev *cdev)
409 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
413 if (p_llh_info->pp_filters)
414 for (i = 0; i < p_llh_info->num_ppfid; i++)
415 kfree(p_llh_info->pp_filters[i]);
417 kfree(p_llh_info->pp_filters);
421 cdev->p_llh_info = NULL;
424 static int qed_llh_alloc(struct qed_dev *cdev)
426 struct qed_llh_info *p_llh_info;
429 p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL);
432 cdev->p_llh_info = p_llh_info;
434 for (i = 0; i < MAX_NUM_PPFID; i++) {
435 if (!(cdev->ppfid_bitmap & (0x1 << i)))
438 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
439 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n",
440 p_llh_info->num_ppfid, i);
441 p_llh_info->num_ppfid++;
444 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
445 p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL);
446 if (!p_llh_info->pp_filters)
449 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
450 sizeof(**p_llh_info->pp_filters);
451 for (i = 0; i < p_llh_info->num_ppfid; i++) {
452 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL);
453 if (!p_llh_info->pp_filters[i])
460 static int qed_llh_shadow_sanity(struct qed_dev *cdev,
461 u8 ppfid, u8 filter_idx, const char *action)
463 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
465 if (ppfid >= p_llh_info->num_ppfid) {
467 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
468 action, ppfid, p_llh_info->num_ppfid);
472 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
474 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
475 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
482 #define QED_LLH_INVALID_FILTER_IDX 0xff
485 qed_llh_shadow_search_filter(struct qed_dev *cdev,
487 union qed_llh_filter *p_filter, u8 *p_filter_idx)
489 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
490 struct qed_llh_filter_info *p_filters;
494 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search");
498 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
500 p_filters = p_llh_info->pp_filters[ppfid];
501 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
502 if (!memcmp(p_filter, &p_filters[i].filter,
503 sizeof(*p_filter))) {
513 qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx)
515 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
516 struct qed_llh_filter_info *p_filters;
520 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx");
524 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
526 p_filters = p_llh_info->pp_filters[ppfid];
527 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
528 if (!p_filters[i].b_enabled) {
538 __qed_llh_shadow_add_filter(struct qed_dev *cdev,
541 enum qed_llh_filter_type type,
542 union qed_llh_filter *p_filter, u32 *p_ref_cnt)
544 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
545 struct qed_llh_filter_info *p_filters;
548 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add");
552 p_filters = p_llh_info->pp_filters[ppfid];
553 if (!p_filters[filter_idx].ref_cnt) {
554 p_filters[filter_idx].b_enabled = true;
555 p_filters[filter_idx].type = type;
556 memcpy(&p_filters[filter_idx].filter, p_filter,
557 sizeof(p_filters[filter_idx].filter));
560 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
566 qed_llh_shadow_add_filter(struct qed_dev *cdev,
568 enum qed_llh_filter_type type,
569 union qed_llh_filter *p_filter,
570 u8 *p_filter_idx, u32 *p_ref_cnt)
574 /* Check if the same filter already exist */
575 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
579 /* Find a new entry in case of a new filter */
580 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
581 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx);
586 /* No free entry was found */
587 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
589 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
594 return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type,
595 p_filter, p_ref_cnt);
599 __qed_llh_shadow_remove_filter(struct qed_dev *cdev,
600 u8 ppfid, u8 filter_idx, u32 *p_ref_cnt)
602 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
603 struct qed_llh_filter_info *p_filters;
606 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove");
610 p_filters = p_llh_info->pp_filters[ppfid];
611 if (!p_filters[filter_idx].ref_cnt) {
613 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
617 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
618 if (!p_filters[filter_idx].ref_cnt)
619 memset(&p_filters[filter_idx],
620 0, sizeof(p_filters[filter_idx]));
626 qed_llh_shadow_remove_filter(struct qed_dev *cdev,
628 union qed_llh_filter *p_filter,
629 u8 *p_filter_idx, u32 *p_ref_cnt)
633 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
637 /* No matching filter was found */
638 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
639 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n");
643 return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx,
647 static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid)
649 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
651 if (ppfid >= p_llh_info->num_ppfid) {
653 "ppfid %d is not valid, available indices are 0..%hhd\n",
654 ppfid, p_llh_info->num_ppfid - 1);
659 *p_abs_ppfid = p_llh_info->ppfid_array[ppfid];
665 qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
667 struct qed_dev *cdev = p_hwfn->cdev;
672 rc = qed_mcp_get_engine_config(p_hwfn, p_ptt);
673 if (rc != 0 && rc != -EOPNOTSUPP) {
675 "Failed to get the engine affinity configuration\n");
679 /* RoCE PF is bound to a single engine */
680 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
681 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
682 rc = qed_llh_set_roce_affinity(cdev, eng);
685 "Failed to set the RoCE engine affinity\n");
691 "LLH: Set the engine affinity of RoCE packets as %d\n",
695 /* Storage PF is bound to a single engine while L2 PF uses both */
696 if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn))
697 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
698 else /* L2_PERSONALITY */
701 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
702 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
705 "Failed to set the engine affinity of ppfid %d\n",
711 DP_VERBOSE(cdev, QED_MSG_SP,
712 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
718 static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn,
719 struct qed_ptt *p_ptt)
721 struct qed_dev *cdev = p_hwfn->cdev;
725 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
728 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
732 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
733 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
736 if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
737 !QED_IS_FCOE_PERSONALITY(p_hwfn)) {
738 rc = qed_llh_add_mac_filter(cdev, 0,
739 p_hwfn->hw_info.hw_mac_addr);
742 "Failed to add an LLH filter with the primary MAC\n");
745 if (QED_IS_CMT(cdev)) {
746 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt);
754 u8 qed_llh_get_num_ppfid(struct qed_dev *cdev)
756 return cdev->p_llh_info->num_ppfid;
759 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
760 #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
761 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
762 #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
764 int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng)
766 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
767 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
768 u32 addr, val, eng_sel;
775 if (!QED_IS_CMT(cdev))
778 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
793 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng);
798 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
799 val = qed_rd(p_hwfn, p_ptt, addr);
800 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
801 qed_wr(p_hwfn, p_ptt, addr, val);
803 /* The iWARP affinity is set as the affinity of ppfid 0 */
804 if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn))
805 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0;
807 qed_ptt_release(p_hwfn, p_ptt);
812 int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng)
814 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
815 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
816 u32 addr, val, eng_sel;
823 if (!QED_IS_CMT(cdev))
835 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
836 0xf); /* QP bit 15 */
839 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng);
844 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
845 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
849 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
850 val = qed_rd(p_hwfn, p_ptt, addr);
851 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
852 qed_wr(p_hwfn, p_ptt, addr, val);
855 qed_ptt_release(p_hwfn, p_ptt);
860 struct qed_llh_filter_details {
869 qed_llh_access_filter(struct qed_hwfn *p_hwfn,
870 struct qed_ptt *p_ptt,
873 struct qed_llh_filter_details *p_details)
875 struct qed_dmae_params params = {0};
880 /* The NIG/LLH registers that are accessed in this function have only 16
881 * rows which are exposed to a PF. I.e. only the 16 filters of its
882 * default ppfid. Accessing filters of other ppfids requires pretending
884 * The calculation of PPFID->PFID in AH is based on the relative index
885 * of a PF on its port.
886 * For BB the pfid is actually the abs_ppfid.
888 if (QED_IS_BB(p_hwfn->cdev))
891 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine +
894 /* Filter enable - should be done first when removing a filter */
895 if (!p_details->enable) {
896 qed_fid_pretend(p_hwfn, p_ptt,
897 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
899 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
900 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
902 qed_fid_pretend(p_hwfn, p_ptt,
904 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
908 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
910 SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1);
911 params.dst_pfid = pfid;
912 rc = qed_dmae_host2grc(p_hwfn,
914 (u64)(uintptr_t)&p_details->value,
915 addr, 2 /* size_in_dwords */,
920 qed_fid_pretend(p_hwfn, p_ptt,
921 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
924 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
925 qed_wr(p_hwfn, p_ptt, addr, p_details->mode);
927 /* Filter protocol type */
928 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
929 qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type);
931 /* Filter header select */
932 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
933 qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel);
935 /* Filter enable - should be done last when adding a filter */
936 if (p_details->enable) {
937 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
938 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
941 qed_fid_pretend(p_hwfn, p_ptt,
943 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
949 qed_llh_add_filter(struct qed_hwfn *p_hwfn,
950 struct qed_ptt *p_ptt,
952 u8 filter_idx, u8 filter_prot_type, u32 high, u32 low)
954 struct qed_llh_filter_details filter_details;
956 filter_details.enable = 1;
957 filter_details.value = ((u64)high << 32) | low;
958 filter_details.hdr_sel = 0;
959 filter_details.protocol_type = filter_prot_type;
960 /* Mode: 0: MAC-address classification 1: protocol classification */
961 filter_details.mode = filter_prot_type ? 1 : 0;
963 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
968 qed_llh_remove_filter(struct qed_hwfn *p_hwfn,
969 struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
971 struct qed_llh_filter_details filter_details = {0};
973 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
977 int qed_llh_add_mac_filter(struct qed_dev *cdev,
978 u8 ppfid, u8 mac_addr[ETH_ALEN])
980 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
981 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
982 union qed_llh_filter filter = {};
983 u8 filter_idx, abs_ppfid;
984 u32 high, low, ref_cnt;
990 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
993 memcpy(filter.mac.addr, mac_addr, ETH_ALEN);
994 rc = qed_llh_shadow_add_filter(cdev, ppfid,
995 QED_LLH_FILTER_TYPE_MAC,
996 &filter, &filter_idx, &ref_cnt);
1000 /* Configure the LLH only in case of a new the filter */
1002 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1006 high = mac_addr[1] | (mac_addr[0] << 8);
1007 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
1008 (mac_addr[2] << 24);
1009 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
1017 "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1018 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1022 err: DP_NOTICE(cdev,
1023 "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n",
1026 qed_ptt_release(p_hwfn, p_ptt);
1032 qed_llh_protocol_filter_stringify(struct qed_dev *cdev,
1033 enum qed_llh_prot_filter_type_t type,
1034 u16 source_port_or_eth_type,
1035 u16 dest_port, u8 *str, size_t str_len)
1038 case QED_LLH_FILTER_ETHERTYPE:
1039 snprintf(str, str_len, "Ethertype 0x%04x",
1040 source_port_or_eth_type);
1042 case QED_LLH_FILTER_TCP_SRC_PORT:
1043 snprintf(str, str_len, "TCP src port 0x%04x",
1044 source_port_or_eth_type);
1046 case QED_LLH_FILTER_UDP_SRC_PORT:
1047 snprintf(str, str_len, "UDP src port 0x%04x",
1048 source_port_or_eth_type);
1050 case QED_LLH_FILTER_TCP_DEST_PORT:
1051 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port);
1053 case QED_LLH_FILTER_UDP_DEST_PORT:
1054 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port);
1056 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1057 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1058 source_port_or_eth_type, dest_port);
1060 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1061 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1062 source_port_or_eth_type, dest_port);
1066 "Non valid LLH protocol filter type %d\n", type);
1074 qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev,
1075 enum qed_llh_prot_filter_type_t type,
1076 u16 source_port_or_eth_type,
1077 u16 dest_port, u32 *p_high, u32 *p_low)
1083 case QED_LLH_FILTER_ETHERTYPE:
1084 *p_high = source_port_or_eth_type;
1086 case QED_LLH_FILTER_TCP_SRC_PORT:
1087 case QED_LLH_FILTER_UDP_SRC_PORT:
1088 *p_low = source_port_or_eth_type << 16;
1090 case QED_LLH_FILTER_TCP_DEST_PORT:
1091 case QED_LLH_FILTER_UDP_DEST_PORT:
1094 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1095 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1096 *p_low = (source_port_or_eth_type << 16) | dest_port;
1100 "Non valid LLH protocol filter type %d\n", type);
1108 qed_llh_add_protocol_filter(struct qed_dev *cdev,
1110 enum qed_llh_prot_filter_type_t type,
1111 u16 source_port_or_eth_type, u16 dest_port)
1113 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1114 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1115 u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1116 union qed_llh_filter filter = {};
1117 u32 high, low, ref_cnt;
1123 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1126 rc = qed_llh_protocol_filter_stringify(cdev, type,
1127 source_port_or_eth_type,
1128 dest_port, str, sizeof(str));
1132 filter.protocol.type = type;
1133 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1134 filter.protocol.dest_port = dest_port;
1135 rc = qed_llh_shadow_add_filter(cdev,
1137 QED_LLH_FILTER_TYPE_PROTOCOL,
1138 &filter, &filter_idx, &ref_cnt);
1142 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1146 /* Configure the LLH only in case of a new the filter */
1148 rc = qed_llh_protocol_filter_to_hilo(cdev, type,
1149 source_port_or_eth_type,
1150 dest_port, &high, &low);
1154 type_bitmap = 0x1 << type;
1155 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid,
1156 filter_idx, type_bitmap, high, low);
1163 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1164 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1168 err: DP_NOTICE(p_hwfn,
1169 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1172 qed_ptt_release(p_hwfn, p_ptt);
1177 void qed_llh_remove_mac_filter(struct qed_dev *cdev,
1178 u8 ppfid, u8 mac_addr[ETH_ALEN])
1180 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1181 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1182 union qed_llh_filter filter = {};
1183 u8 filter_idx, abs_ppfid;
1190 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
1193 ether_addr_copy(filter.mac.addr, mac_addr);
1194 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1199 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1203 /* Remove from the LLH in case the filter is not in use */
1205 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1213 "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1214 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1218 err: DP_NOTICE(cdev,
1219 "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n",
1222 qed_ptt_release(p_hwfn, p_ptt);
1225 void qed_llh_remove_protocol_filter(struct qed_dev *cdev,
1227 enum qed_llh_prot_filter_type_t type,
1228 u16 source_port_or_eth_type, u16 dest_port)
1230 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1231 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1232 u8 filter_idx, abs_ppfid, str[32];
1233 union qed_llh_filter filter = {};
1240 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1243 rc = qed_llh_protocol_filter_stringify(cdev, type,
1244 source_port_or_eth_type,
1245 dest_port, str, sizeof(str));
1249 filter.protocol.type = type;
1250 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1251 filter.protocol.dest_port = dest_port;
1252 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1257 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1261 /* Remove from the LLH in case the filter is not in use */
1263 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1271 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1272 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1276 err: DP_NOTICE(cdev,
1277 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1280 qed_ptt_release(p_hwfn, p_ptt);
1283 /******************************* NIG LLH - End ********************************/
1285 #define QED_MIN_DPIS (4)
1286 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
1288 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
1289 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
1291 u32 bar_reg = (bar_id == BAR_ID_0 ?
1292 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1295 if (IS_VF(p_hwfn->cdev))
1296 return qed_vf_hw_bar_size(p_hwfn, bar_id);
1298 val = qed_rd(p_hwfn, p_ptt, bar_reg);
1300 return 1 << (val + 15);
1302 /* Old MFW initialized above registered only conditionally */
1303 if (p_hwfn->cdev->num_hwfns > 1) {
1305 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1306 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1309 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1314 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
1318 cdev->dp_level = dp_level;
1319 cdev->dp_module = dp_module;
1320 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1321 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1323 p_hwfn->dp_level = dp_level;
1324 p_hwfn->dp_module = dp_module;
1328 void qed_init_struct(struct qed_dev *cdev)
1332 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1333 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1335 p_hwfn->cdev = cdev;
1337 p_hwfn->b_active = false;
1339 mutex_init(&p_hwfn->dmae_info.mutex);
1342 /* hwfn 0 is always active */
1343 cdev->hwfns[0].b_active = true;
1345 /* set the default cache alignment to 128 */
1346 cdev->cache_shift = 7;
1349 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
1351 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1353 kfree(qm_info->qm_pq_params);
1354 qm_info->qm_pq_params = NULL;
1355 kfree(qm_info->qm_vport_params);
1356 qm_info->qm_vport_params = NULL;
1357 kfree(qm_info->qm_port_params);
1358 qm_info->qm_port_params = NULL;
1359 kfree(qm_info->wfq_data);
1360 qm_info->wfq_data = NULL;
1363 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
1365 kfree(p_hwfn->dbg_user_info);
1366 p_hwfn->dbg_user_info = NULL;
1369 void qed_resc_free(struct qed_dev *cdev)
1374 for_each_hwfn(cdev, i)
1375 qed_l2_free(&cdev->hwfns[i]);
1379 kfree(cdev->fw_data);
1380 cdev->fw_data = NULL;
1382 kfree(cdev->reset_stats);
1383 cdev->reset_stats = NULL;
1387 for_each_hwfn(cdev, i) {
1388 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1390 qed_cxt_mngr_free(p_hwfn);
1391 qed_qm_info_free(p_hwfn);
1392 qed_spq_free(p_hwfn);
1393 qed_eq_free(p_hwfn);
1394 qed_consq_free(p_hwfn);
1395 qed_int_free(p_hwfn);
1396 #ifdef CONFIG_QED_LL2
1397 qed_ll2_free(p_hwfn);
1399 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1400 qed_fcoe_free(p_hwfn);
1402 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1403 qed_iscsi_free(p_hwfn);
1404 qed_ooo_free(p_hwfn);
1407 if (QED_IS_RDMA_PERSONALITY(p_hwfn))
1408 qed_rdma_info_free(p_hwfn);
1410 qed_iov_free(p_hwfn);
1411 qed_l2_free(p_hwfn);
1412 qed_dmae_info_free(p_hwfn);
1413 qed_dcbx_info_free(p_hwfn);
1414 qed_dbg_user_data_free(p_hwfn);
1415 qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1417 /* Destroy doorbell recovery mechanism */
1418 qed_db_recovery_teardown(p_hwfn);
1422 /******************** QM initialization *******************/
1423 #define ACTIVE_TCS_BMAP 0x9f
1424 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1426 /* determines the physical queue flags for a given PF. */
1427 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
1432 flags = PQ_FLAGS_LB;
1435 if (IS_QED_SRIOV(p_hwfn->cdev))
1436 flags |= PQ_FLAGS_VFS;
1438 /* protocol flags */
1439 switch (p_hwfn->hw_info.personality) {
1441 flags |= PQ_FLAGS_MCOS;
1444 flags |= PQ_FLAGS_OFLD;
1447 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1449 case QED_PCI_ETH_ROCE:
1450 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1451 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
1452 flags |= PQ_FLAGS_MTC;
1454 case QED_PCI_ETH_IWARP:
1455 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
1460 "unknown personality %d\n", p_hwfn->hw_info.personality);
1467 /* Getters for resource amounts necessary for qm initialization */
1468 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
1470 return p_hwfn->hw_info.num_hw_tc;
1473 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
1475 return IS_QED_SRIOV(p_hwfn->cdev) ?
1476 p_hwfn->cdev->p_iov_info->total_vfs : 0;
1479 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
1481 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1483 if (!(PQ_FLAGS_MTC & pq_flags))
1486 return qed_init_qm_get_num_tcs(p_hwfn);
1489 #define NUM_DEFAULT_RLS 1
1491 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
1493 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1495 /* num RLs can't exceed resource amount of rls or vports */
1496 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
1497 RESC_NUM(p_hwfn, QED_VPORT));
1499 /* Make sure after we reserve there's something left */
1500 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
1503 /* subtract rls necessary for VFs and one default one for the PF */
1504 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1509 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
1511 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1513 /* all pqs share the same vport, except for vfs and pf_rl pqs */
1514 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1515 qed_init_qm_get_num_pf_rls(p_hwfn) +
1516 (!!(PQ_FLAGS_VFS & pq_flags)) *
1517 qed_init_qm_get_num_vfs(p_hwfn) + 1;
1520 /* calc amount of PQs according to the requested flags */
1521 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
1523 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1525 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1526 qed_init_qm_get_num_pf_rls(p_hwfn) +
1527 (!!(PQ_FLAGS_MCOS & pq_flags)) *
1528 qed_init_qm_get_num_tcs(p_hwfn) +
1529 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
1530 (!!(PQ_FLAGS_ACK & pq_flags)) +
1531 (!!(PQ_FLAGS_OFLD & pq_flags)) *
1532 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1533 (!!(PQ_FLAGS_LLT & pq_flags)) *
1534 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1535 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
1538 /* initialize the top level QM params */
1539 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
1541 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1544 /* pq and vport bases for this PF */
1545 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
1546 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
1548 /* rate limiting and weighted fair queueing are always enabled */
1549 qm_info->vport_rl_en = true;
1550 qm_info->vport_wfq_en = true;
1552 /* TC config is different for AH 4 port */
1553 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1555 /* in AH 4 port we have fewer TCs per port */
1556 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1559 /* unless MFW indicated otherwise, ooo_tc == 3 for
1560 * AH 4-port and 4 otherwise.
1562 if (!qm_info->ooo_tc)
1563 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1567 /* initialize qm vport params */
1568 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
1570 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1573 /* all vports participate in weighted fair queueing */
1574 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
1575 qm_info->qm_vport_params[i].wfq = 1;
1578 /* initialize qm port params */
1579 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
1581 /* Initialize qm port parameters */
1582 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
1583 struct qed_dev *cdev = p_hwfn->cdev;
1585 /* indicate how ooo and high pri traffic is dealt with */
1586 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1587 ACTIVE_TCS_BMAP_4PORT_K2 :
1590 for (i = 0; i < num_ports; i++) {
1591 struct init_qm_port_params *p_qm_port =
1592 &p_hwfn->qm_info.qm_port_params[i];
1593 u16 pbf_max_cmd_lines;
1595 p_qm_port->active = 1;
1596 p_qm_port->active_phys_tcs = active_phys_tcs;
1597 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev);
1598 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1599 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports;
1603 /* Reset the params which must be reset for qm init. QM init may be called as
1604 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1605 * params may be affected by the init but would simply recalculate to the same
1606 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1607 * affected as these amounts stay the same.
1609 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
1611 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1613 qm_info->num_pqs = 0;
1614 qm_info->num_vports = 0;
1615 qm_info->num_pf_rls = 0;
1616 qm_info->num_vf_pqs = 0;
1617 qm_info->first_vf_pq = 0;
1618 qm_info->first_mcos_pq = 0;
1619 qm_info->first_rl_pq = 0;
1622 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
1624 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1626 qm_info->num_vports++;
1628 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1630 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1631 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1634 /* initialize a single pq and manage qm_info resources accounting.
1635 * The pq_init_flags param determines whether the PQ is rate limited
1636 * (for VF or PF) and whether a new vport is allocated to the pq or not
1637 * (i.e. vport will be shared).
1640 /* flags for pq init */
1641 #define PQ_INIT_SHARE_VPORT (1 << 0)
1642 #define PQ_INIT_PF_RL (1 << 1)
1643 #define PQ_INIT_VF_RL (1 << 2)
1645 /* defines for pq init */
1646 #define PQ_INIT_DEFAULT_WRR_GROUP 1
1647 #define PQ_INIT_DEFAULT_TC 0
1649 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
1651 p_info->offload_tc = tc;
1652 p_info->offload_tc_set = true;
1655 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
1657 return p_hwfn->hw_info.offload_tc_set;
1660 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
1662 if (qed_is_offload_tc_set(p_hwfn))
1663 return p_hwfn->hw_info.offload_tc;
1665 return PQ_INIT_DEFAULT_TC;
1668 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
1669 struct qed_qm_info *qm_info,
1670 u8 tc, u32 pq_init_flags)
1672 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
1674 if (pq_idx > max_pq)
1676 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1678 /* init pq params */
1679 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1680 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1681 qm_info->num_vports;
1682 qm_info->qm_pq_params[pq_idx].tc_id = tc;
1683 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1684 qm_info->qm_pq_params[pq_idx].rl_valid =
1685 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
1687 /* qm params accounting */
1689 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1690 qm_info->num_vports++;
1692 if (pq_init_flags & PQ_INIT_PF_RL)
1693 qm_info->num_pf_rls++;
1695 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1697 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1698 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1700 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
1702 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
1703 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
1706 /* get pq index according to PQ_FLAGS */
1707 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
1708 unsigned long pq_flags)
1710 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1712 /* Can't have multiple flags set here */
1713 if (bitmap_weight(&pq_flags,
1714 sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
1715 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
1719 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
1720 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
1726 return &qm_info->first_rl_pq;
1728 return &qm_info->first_mcos_pq;
1730 return &qm_info->pure_lb_pq;
1732 return &qm_info->ooo_pq;
1734 return &qm_info->pure_ack_pq;
1736 return &qm_info->first_ofld_pq;
1738 return &qm_info->first_llt_pq;
1740 return &qm_info->first_vf_pq;
1746 return &qm_info->start_pq;
1749 /* save pq index in qm info */
1750 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
1751 u32 pq_flags, u16 pq_val)
1753 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1755 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1758 /* get tx pq index, with the PQ TX base already set (ready for context init) */
1759 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
1761 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1763 return *base_pq_idx + CM_TX_PQ_BASE;
1766 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
1768 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
1771 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1773 return p_hwfn->qm_info.start_pq;
1777 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
1779 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
1782 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
1784 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
1787 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1789 return p_hwfn->qm_info.start_pq;
1793 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
1795 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
1798 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1800 u16 first_ofld_pq, pq_offset;
1802 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1803 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1804 tc : PQ_INIT_DEFAULT_TC;
1806 return first_ofld_pq + pq_offset;
1809 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1811 u16 first_llt_pq, pq_offset;
1813 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
1814 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1815 tc : PQ_INIT_DEFAULT_TC;
1817 return first_llt_pq + pq_offset;
1820 /* Functions for creating specific types of pqs */
1821 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
1823 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1825 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
1828 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
1829 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
1832 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
1834 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1836 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
1839 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
1840 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
1843 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
1845 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1847 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
1850 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
1851 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1852 PQ_INIT_SHARE_VPORT);
1855 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
1857 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
1858 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1861 /* override pq's TC if offload TC is set */
1862 for (tc = 0; tc < num_tcs; tc++)
1863 qed_init_qm_pq(p_hwfn, qm_info,
1864 qed_is_offload_tc_set(p_hwfn) ?
1865 p_hwfn->hw_info.offload_tc : tc,
1866 PQ_INIT_SHARE_VPORT);
1869 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
1871 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1873 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
1876 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
1877 qed_init_qm_mtc_pqs(p_hwfn);
1880 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
1882 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1884 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
1887 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
1888 qed_init_qm_mtc_pqs(p_hwfn);
1891 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
1893 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1896 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
1899 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
1900 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
1901 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
1904 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
1906 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1907 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1909 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1912 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1913 qm_info->num_vf_pqs = num_vfs;
1914 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1915 qed_init_qm_pq(p_hwfn,
1916 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1919 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1921 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1922 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1924 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1927 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1928 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1929 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1933 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1935 /* rate limited pqs, must come first (FW assumption) */
1936 qed_init_qm_rl_pqs(p_hwfn);
1938 /* pqs for multi cos */
1939 qed_init_qm_mcos_pqs(p_hwfn);
1941 /* pure loopback pq */
1942 qed_init_qm_lb_pq(p_hwfn);
1944 /* out of order pq */
1945 qed_init_qm_ooo_pq(p_hwfn);
1948 qed_init_qm_pure_ack_pq(p_hwfn);
1950 /* pq for offloaded protocol */
1951 qed_init_qm_offload_pq(p_hwfn);
1953 /* low latency pq */
1954 qed_init_qm_low_latency_pq(p_hwfn);
1956 /* done sharing vports */
1957 qed_init_qm_advance_vport(p_hwfn);
1960 qed_init_qm_vf_pqs(p_hwfn);
1963 /* compare values of getters against resources amounts */
1964 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1966 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1967 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1971 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1974 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1975 p_hwfn->hw_info.multi_tc_roce_en = 0;
1977 "multi-tc roce was disabled to reduce requested amount of pqs\n");
1978 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1982 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1986 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1988 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1989 struct init_qm_vport_params *vport;
1990 struct init_qm_port_params *port;
1991 struct init_qm_pq_params *pq;
1994 /* top level params */
1997 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1999 qm_info->start_vport,
2000 qm_info->pure_lb_pq,
2001 qm_info->first_ofld_pq,
2002 qm_info->first_llt_pq,
2003 qm_info->pure_ack_pq);
2006 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
2008 qm_info->first_vf_pq,
2010 qm_info->num_vf_pqs,
2011 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
2014 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2017 qm_info->vport_rl_en,
2018 qm_info->vport_wfq_en,
2021 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
2024 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
2025 port = &(qm_info->qm_port_params[i]);
2028 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2031 port->active_phys_tcs,
2032 port->num_pbf_cmd_lines,
2033 port->num_btb_blocks, port->reserved);
2037 for (i = 0; i < qm_info->num_vports; i++) {
2038 vport = &(qm_info->qm_vport_params[i]);
2041 "vport idx %d, wfq %d, first_tx_pq_id [ ",
2042 qm_info->start_vport + i, vport->wfq);
2043 for (tc = 0; tc < NUM_OF_TCS; tc++)
2046 "%d ", vport->first_tx_pq_id[tc]);
2047 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
2051 for (i = 0; i < qm_info->num_pqs; i++) {
2052 pq = &(qm_info->qm_pq_params[i]);
2055 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n",
2056 qm_info->start_pq + i,
2059 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2063 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
2065 /* reset params required for init run */
2066 qed_init_qm_reset_params(p_hwfn);
2068 /* init QM top level params */
2069 qed_init_qm_params(p_hwfn);
2071 /* init QM port params */
2072 qed_init_qm_port_params(p_hwfn);
2074 /* init QM vport params */
2075 qed_init_qm_vport_params(p_hwfn);
2077 /* init QM physical queue params */
2078 qed_init_qm_pq_params(p_hwfn);
2080 /* display all that init */
2081 qed_dp_init_qm_params(p_hwfn);
2084 /* This function reconfigures the QM pf on the fly.
2085 * For this purpose we:
2086 * 1. reconfigure the QM database
2087 * 2. set new values to runtime array
2088 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2089 * 4. activate init tool in QM_PF stage
2090 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2092 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2094 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2098 /* initialize qed's qm data structure */
2099 qed_init_qm_info(p_hwfn);
2101 /* stop PF's qm queues */
2102 spin_lock_bh(&qm_lock);
2103 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2104 qm_info->start_pq, qm_info->num_pqs);
2105 spin_unlock_bh(&qm_lock);
2109 /* prepare QM portion of runtime array */
2110 qed_qm_init_pf(p_hwfn, p_ptt, false);
2112 /* activate init tool on runtime array */
2113 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2114 p_hwfn->hw_info.hw_mode);
2118 /* start PF's qm queues */
2119 spin_lock_bh(&qm_lock);
2120 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2121 qm_info->start_pq, qm_info->num_pqs);
2122 spin_unlock_bh(&qm_lock);
2129 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
2131 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2134 rc = qed_init_qm_sanity(p_hwfn);
2138 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
2139 sizeof(*qm_info->qm_pq_params),
2141 if (!qm_info->qm_pq_params)
2144 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2145 sizeof(*qm_info->qm_vport_params),
2147 if (!qm_info->qm_vport_params)
2150 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
2151 sizeof(*qm_info->qm_port_params),
2153 if (!qm_info->qm_port_params)
2156 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2157 sizeof(*qm_info->wfq_data),
2159 if (!qm_info->wfq_data)
2165 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
2166 qed_qm_info_free(p_hwfn);
2170 int qed_resc_alloc(struct qed_dev *cdev)
2172 u32 rdma_tasks, excess_tasks;
2177 for_each_hwfn(cdev, i) {
2178 rc = qed_l2_alloc(&cdev->hwfns[i]);
2185 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
2189 for_each_hwfn(cdev, i) {
2190 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2191 u32 n_eqes, num_cons;
2193 /* Initialize the doorbell recovery mechanism */
2194 rc = qed_db_recovery_setup(p_hwfn);
2198 /* First allocate the context manager structure */
2199 rc = qed_cxt_mngr_alloc(p_hwfn);
2203 /* Set the HW cid/tid numbers (in the contest manager)
2204 * Must be done prior to any further computations.
2206 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2210 rc = qed_alloc_qm_data(p_hwfn);
2215 qed_init_qm_info(p_hwfn);
2217 /* Compute the ILT client partition */
2218 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2221 "too many ILT lines; re-computing with less lines\n");
2222 /* In case there are not enough ILT lines we reduce the
2223 * number of RDMA tasks and re-compute.
2226 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
2230 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2231 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
2235 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2238 "failed ILT compute. Requested too many lines: %u\n",
2245 /* CID map / ILT shadow table / T2
2246 * The talbes sizes are determined by the computations above
2248 rc = qed_cxt_tables_alloc(p_hwfn);
2252 /* SPQ, must follow ILT because initializes SPQ context */
2253 rc = qed_spq_alloc(p_hwfn);
2257 /* SP status block allocation */
2258 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
2261 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2265 rc = qed_iov_alloc(p_hwfn);
2270 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
2271 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2272 enum protocol_type rdma_proto;
2274 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2275 rdma_proto = PROTOCOLID_ROCE;
2277 rdma_proto = PROTOCOLID_IWARP;
2279 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
2282 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
2283 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2285 qed_cxt_get_proto_cid_count(p_hwfn,
2288 n_eqes += 2 * num_cons;
2291 if (n_eqes > 0xFFFF) {
2293 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
2298 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
2302 rc = qed_consq_alloc(p_hwfn);
2306 rc = qed_l2_alloc(p_hwfn);
2310 #ifdef CONFIG_QED_LL2
2311 if (p_hwfn->using_ll2) {
2312 rc = qed_ll2_alloc(p_hwfn);
2318 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2319 rc = qed_fcoe_alloc(p_hwfn);
2324 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2325 rc = qed_iscsi_alloc(p_hwfn);
2328 rc = qed_ooo_alloc(p_hwfn);
2333 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2334 rc = qed_rdma_info_alloc(p_hwfn);
2339 /* DMA info initialization */
2340 rc = qed_dmae_info_alloc(p_hwfn);
2344 /* DCBX initialization */
2345 rc = qed_dcbx_info_alloc(p_hwfn);
2349 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info);
2354 rc = qed_llh_alloc(cdev);
2357 "Failed to allocate memory for the llh_info structure\n");
2361 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2362 if (!cdev->reset_stats)
2370 qed_resc_free(cdev);
2374 void qed_resc_setup(struct qed_dev *cdev)
2379 for_each_hwfn(cdev, i)
2380 qed_l2_setup(&cdev->hwfns[i]);
2384 for_each_hwfn(cdev, i) {
2385 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2387 qed_cxt_mngr_setup(p_hwfn);
2388 qed_spq_setup(p_hwfn);
2389 qed_eq_setup(p_hwfn);
2390 qed_consq_setup(p_hwfn);
2392 /* Read shadow of current MFW mailbox */
2393 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2394 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2395 p_hwfn->mcp_info->mfw_mb_cur,
2396 p_hwfn->mcp_info->mfw_mb_length);
2398 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2400 qed_l2_setup(p_hwfn);
2401 qed_iov_setup(p_hwfn);
2402 #ifdef CONFIG_QED_LL2
2403 if (p_hwfn->using_ll2)
2404 qed_ll2_setup(p_hwfn);
2406 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2407 qed_fcoe_setup(p_hwfn);
2409 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2410 qed_iscsi_setup(p_hwfn);
2411 qed_ooo_setup(p_hwfn);
2416 #define FINAL_CLEANUP_POLL_CNT (100)
2417 #define FINAL_CLEANUP_POLL_TIME (10)
2418 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
2419 struct qed_ptt *p_ptt, u16 id, bool is_vf)
2421 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2424 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2425 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2430 command |= X_FINAL_CLEANUP_AGG_INT <<
2431 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2432 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2433 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2434 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2436 /* Make sure notification is not set before initiating final cleanup */
2437 if (REG_RD(p_hwfn, addr)) {
2439 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2440 REG_WR(p_hwfn, addr, 0);
2443 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2444 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2447 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2449 /* Poll until completion */
2450 while (!REG_RD(p_hwfn, addr) && count--)
2451 msleep(FINAL_CLEANUP_POLL_TIME);
2453 if (REG_RD(p_hwfn, addr))
2457 "Failed to receive FW final cleanup notification\n");
2459 /* Cleanup afterwards */
2460 REG_WR(p_hwfn, addr, 0);
2465 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
2469 if (QED_IS_BB_B0(p_hwfn->cdev)) {
2470 hw_mode |= 1 << MODE_BB;
2471 } else if (QED_IS_AH(p_hwfn->cdev)) {
2472 hw_mode |= 1 << MODE_K2;
2474 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
2475 p_hwfn->cdev->type);
2479 switch (p_hwfn->cdev->num_ports_in_engine) {
2481 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2484 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2487 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2490 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
2491 p_hwfn->cdev->num_ports_in_engine);
2495 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
2496 hw_mode |= 1 << MODE_MF_SD;
2498 hw_mode |= 1 << MODE_MF_SI;
2500 hw_mode |= 1 << MODE_ASIC;
2502 if (p_hwfn->cdev->num_hwfns > 1)
2503 hw_mode |= 1 << MODE_100G;
2505 p_hwfn->hw_info.hw_mode = hw_mode;
2507 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
2508 "Configuring function for hw_mode: 0x%08x\n",
2509 p_hwfn->hw_info.hw_mode);
2514 /* Init run time data for all PFs on an engine. */
2515 static void qed_init_cau_rt_data(struct qed_dev *cdev)
2517 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2520 for_each_hwfn(cdev, i) {
2521 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2522 struct qed_igu_info *p_igu_info;
2523 struct qed_igu_block *p_block;
2524 struct cau_sb_entry sb_entry;
2526 p_igu_info = p_hwfn->hw_info.p_igu_info;
2529 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
2530 p_block = &p_igu_info->entry[igu_sb_id];
2532 if (!p_block->is_pf)
2535 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
2536 p_block->function_id, 0, 0);
2537 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2543 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
2544 struct qed_ptt *p_ptt)
2546 u32 val, wr_mbs, cache_line_size;
2548 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2561 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2566 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2567 switch (cache_line_size) {
2582 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2586 if (L1_CACHE_BYTES > wr_mbs)
2588 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2589 L1_CACHE_BYTES, wr_mbs);
2591 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2593 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2594 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2598 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
2599 struct qed_ptt *p_ptt, int hw_mode)
2601 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2602 struct qed_qm_common_rt_init_params params;
2603 struct qed_dev *cdev = p_hwfn->cdev;
2604 u8 vf_id, max_num_vfs;
2609 qed_init_cau_rt_data(cdev);
2611 /* Program GTT windows */
2612 qed_gtt_init(p_hwfn);
2614 if (p_hwfn->mcp_info) {
2615 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2616 qm_info->pf_rl_en = true;
2617 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2618 qm_info->pf_wfq_en = true;
2621 memset(¶ms, 0, sizeof(params));
2622 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
2623 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
2624 params.pf_rl_en = qm_info->pf_rl_en;
2625 params.pf_wfq_en = qm_info->pf_wfq_en;
2626 params.global_rl_en = qm_info->vport_rl_en;
2627 params.vport_wfq_en = qm_info->vport_wfq_en;
2628 params.port_params = qm_info->qm_port_params;
2630 qed_qm_common_rt_init(p_hwfn, ¶ms);
2632 qed_cxt_hw_init_common(p_hwfn);
2634 qed_init_cache_line_size(p_hwfn, p_ptt);
2636 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
2640 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2641 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2643 if (QED_IS_BB(p_hwfn->cdev)) {
2644 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
2645 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2646 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
2647 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2648 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2650 /* pretend to original PF */
2651 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2654 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2655 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2656 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
2657 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
2658 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2659 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2660 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2661 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2663 /* pretend to original PF */
2664 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2670 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
2671 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
2673 u32 dpi_bit_shift, dpi_count, dpi_page_size;
2677 /* Calculate DPI size */
2678 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
2679 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
2680 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
2681 dpi_bit_shift = ilog2(dpi_page_size / 4096);
2682 dpi_count = pwm_region_size / dpi_page_size;
2684 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
2685 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
2687 p_hwfn->dpi_size = dpi_page_size;
2688 p_hwfn->dpi_count = dpi_count;
2690 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
2692 if (dpi_count < min_dpis)
2698 enum QED_ROCE_EDPM_MODE {
2699 QED_ROCE_EDPM_MODE_ENABLE = 0,
2700 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
2701 QED_ROCE_EDPM_MODE_DISABLE = 2,
2704 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
2706 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
2713 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2715 u32 pwm_regsize, norm_regsize;
2716 u32 non_pwm_conn, min_addr_reg1;
2717 u32 db_bar_size, n_cpus = 1;
2723 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
2724 if (p_hwfn->cdev->num_hwfns > 1)
2727 /* Calculate doorbell regions */
2728 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2729 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2731 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2733 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
2734 min_addr_reg1 = norm_regsize / 4096;
2735 pwm_regsize = db_bar_size - norm_regsize;
2737 /* Check that the normal and PWM sizes are valid */
2738 if (db_bar_size < norm_regsize) {
2739 DP_ERR(p_hwfn->cdev,
2740 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2741 db_bar_size, norm_regsize);
2745 if (pwm_regsize < QED_MIN_PWM_REGION) {
2746 DP_ERR(p_hwfn->cdev,
2747 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2749 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
2753 /* Calculate number of DPIs */
2754 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2755 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
2756 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
2757 /* Either EDPM is mandatory, or we are attempting to allocate a
2760 n_cpus = num_present_cpus();
2761 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2764 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
2765 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
2766 if (cond || p_hwfn->dcbx_no_edpm) {
2767 /* Either EDPM is disabled from user configuration, or it is
2768 * disabled via DCBx, or it is not mandatory and we failed to
2769 * allocated a WID per CPU.
2772 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2775 qed_rdma_dpm_bar(p_hwfn, p_ptt);
2778 p_hwfn->wid_count = (u16) n_cpus;
2781 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
2786 (!qed_edpm_enabled(p_hwfn)) ?
2787 "disabled" : "enabled", PAGE_SIZE);
2791 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
2793 p_hwfn->pf_params.rdma_pf_params.min_dpis);
2797 p_hwfn->dpi_start_offset = norm_regsize;
2799 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2800 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
2801 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2802 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2807 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
2808 struct qed_ptt *p_ptt, int hw_mode)
2812 /* In CMT the gate should be cleared by the 2nd hwfn */
2813 if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn))
2814 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2816 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
2820 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2825 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
2826 struct qed_ptt *p_ptt,
2827 struct qed_tunnel_info *p_tunn,
2830 enum qed_int_mode int_mode,
2831 bool allow_npar_tx_switch)
2833 u8 rel_pf_id = p_hwfn->rel_pf_id;
2836 if (p_hwfn->mcp_info) {
2837 struct qed_mcp_function_info *p_info;
2839 p_info = &p_hwfn->mcp_info->func_info;
2840 if (p_info->bandwidth_min)
2841 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2843 /* Update rate limit once we'll actually have a link */
2844 p_hwfn->qm_info.pf_rl = 100000;
2847 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
2849 qed_int_igu_init_rt(p_hwfn);
2851 /* Set VLAN in NIG if needed */
2852 if (hw_mode & BIT(MODE_MF_SD)) {
2853 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2854 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2855 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2856 p_hwfn->hw_info.ovlan);
2858 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2859 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2860 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2864 /* Enable classification by MAC if needed */
2865 if (hw_mode & BIT(MODE_MF_SI)) {
2866 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2867 "Configuring TAGMAC_CLS_TYPE\n");
2868 STORE_RT_REG(p_hwfn,
2869 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
2872 /* Protocol Configuration */
2873 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2874 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
2875 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2876 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
2877 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2879 /* Sanity check before the PF init sequence that uses DMAE */
2880 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2884 /* PF Init sequence */
2885 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2889 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2890 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2894 qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
2896 /* Pure runtime initializations - directly to the HW */
2897 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2899 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2903 /* Use the leading hwfn since in CMT only NIG #0 is operational */
2904 if (IS_LEAD_HWFN(p_hwfn)) {
2905 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt);
2911 /* enable interrupts */
2912 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
2914 /* send function start command */
2915 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2916 allow_npar_tx_switch);
2918 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
2921 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2922 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2923 qed_wr(p_hwfn, p_ptt,
2924 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2931 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2932 struct qed_ptt *p_ptt, bool b_enable)
2934 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2936 /* Configure the PF's internal FID_enable for master transactions */
2937 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2939 /* Wait until value is set - try for 1 second every 50us */
2940 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2941 val = qed_rd(p_hwfn, p_ptt,
2942 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2946 usleep_range(50, 60);
2949 if (val != set_val) {
2951 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2958 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2959 struct qed_ptt *p_main_ptt)
2961 /* Read shadow of current MFW mailbox */
2962 qed_mcp_read_mb(p_hwfn, p_main_ptt);
2963 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2964 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2968 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2969 struct qed_drv_load_params *p_drv_load)
2971 memset(p_load_req, 0, sizeof(*p_load_req));
2973 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2974 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2975 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2976 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2977 p_load_req->override_force_load = p_drv_load->override_force_load;
2980 static int qed_vf_start(struct qed_hwfn *p_hwfn,
2981 struct qed_hw_init_params *p_params)
2983 if (p_params->p_tunn) {
2984 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2985 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2988 p_hwfn->b_int_enabled = true;
2993 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2995 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
2996 BIT(p_hwfn->abs_pf_id));
2999 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
3001 struct qed_load_req_params load_req_params;
3002 u32 load_code, resp, param, drv_mb_param;
3003 bool b_default_mtu = true;
3004 struct qed_hwfn *p_hwfn;
3005 const u32 *fw_overlays;
3006 u32 fw_overlays_len;
3010 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
3011 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
3016 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
3021 for_each_hwfn(cdev, i) {
3022 p_hwfn = &cdev->hwfns[i];
3024 /* If management didn't provide a default, set one of our own */
3025 if (!p_hwfn->hw_info.mtu) {
3026 p_hwfn->hw_info.mtu = 1500;
3027 b_default_mtu = false;
3031 qed_vf_start(p_hwfn, p_params);
3035 rc = qed_calc_hw_mode(p_hwfn);
3039 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
3041 test_bit(QED_MF_8021AD_TAGGING,
3043 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
3044 ether_type = ETH_P_8021Q;
3046 ether_type = ETH_P_8021AD;
3047 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3049 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3051 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3053 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3057 qed_fill_load_req_params(&load_req_params,
3058 p_params->p_drv_load_params);
3059 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3062 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
3066 load_code = load_req_params.load_code;
3067 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3068 "Load request was sent. Load code: 0x%x\n",
3071 /* Only relevant for recovery:
3072 * Clear the indication after LOAD_REQ is responded by the MFW.
3074 cdev->recov_in_prog = false;
3076 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3078 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3080 /* Clean up chip from previous driver if such remains exist.
3081 * This is not needed when the PF is the first one on the
3082 * engine, since afterwards we are going to init the FW.
3084 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3085 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3086 p_hwfn->rel_pf_id, false);
3088 DP_NOTICE(p_hwfn, "Final cleanup failed\n");
3093 /* Log and clear previous pglue_b errors if such exist */
3094 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt);
3096 /* Enable the PF's internal FID_enable in the PXP */
3097 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3102 /* Clear the pglue_b was_error indication.
3103 * In E4 it must be done after the BME and the internal
3104 * FID_enable for the PF are set, since VDMs may cause the
3105 * indication to be set again.
3107 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3109 fw_overlays = cdev->fw_data->fw_overlays;
3110 fw_overlays_len = cdev->fw_data->fw_overlays_len;
3111 p_hwfn->fw_overlay_mem =
3112 qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3114 if (!p_hwfn->fw_overlay_mem) {
3116 "Failed to allocate fw overlay memory\n");
3121 switch (load_code) {
3122 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3123 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3124 p_hwfn->hw_info.hw_mode);
3128 case FW_MSG_CODE_DRV_LOAD_PORT:
3129 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3130 p_hwfn->hw_info.hw_mode);
3135 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3136 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3138 p_hwfn->hw_info.hw_mode,
3139 p_params->b_hw_start,
3141 p_params->allow_npar_tx_switch);
3145 "Unexpected load code [0x%08x]", load_code);
3152 "init phase failed for loadcode 0x%x (rc %d)\n",
3157 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3161 /* send DCBX attention request command */
3164 "sending phony dcbx set command to trigger DCBx attention handling\n");
3165 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3166 DRV_MSG_CODE_SET_DCBX,
3167 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
3171 "Failed to send DCBX attention request\n");
3175 p_hwfn->hw_init_done = true;
3179 p_hwfn = QED_LEADING_HWFN(cdev);
3181 /* Get pre-negotiated values for stag, bandwidth etc. */
3184 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3185 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
3186 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3187 DRV_MSG_CODE_GET_OEM_UPDATES,
3188 drv_mb_param, &resp, ¶m);
3191 "Failed to send GET_OEM_UPDATES attention request\n");
3193 drv_mb_param = STORM_FW_VERSION;
3194 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3195 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3196 drv_mb_param, &load_code, ¶m);
3198 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3200 if (!b_default_mtu) {
3201 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3202 p_hwfn->hw_info.mtu);
3205 "Failed to update default mtu\n");
3208 rc = qed_mcp_ov_update_driver_state(p_hwfn,
3210 QED_OV_DRIVER_STATE_DISABLED);
3212 DP_INFO(p_hwfn, "Failed to update driver state\n");
3214 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3215 QED_OV_ESWITCH_NONE);
3217 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3223 /* The MFW load lock should be released also when initialization fails.
3225 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3229 #define QED_HW_STOP_RETRY_LIMIT (10)
3230 static void qed_hw_timers_stop(struct qed_dev *cdev,
3231 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3236 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3237 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3239 if (cdev->recov_in_prog)
3242 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
3243 if ((!qed_rd(p_hwfn, p_ptt,
3244 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3245 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3248 /* Dependent on number of connection/tasks, possibly
3249 * 1ms sleep is required between polls
3251 usleep_range(1000, 2000);
3254 if (i < QED_HW_STOP_RETRY_LIMIT)
3258 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3259 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3260 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3263 void qed_hw_timers_stop_all(struct qed_dev *cdev)
3267 for_each_hwfn(cdev, j) {
3268 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3269 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
3271 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3275 int qed_hw_stop(struct qed_dev *cdev)
3277 struct qed_hwfn *p_hwfn;
3278 struct qed_ptt *p_ptt;
3282 for_each_hwfn(cdev, j) {
3283 p_hwfn = &cdev->hwfns[j];
3284 p_ptt = p_hwfn->p_main_ptt;
3286 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
3289 qed_vf_pf_int_cleanup(p_hwfn);
3290 rc = qed_vf_pf_reset(p_hwfn);
3293 "qed_vf_pf_reset failed. rc = %d.\n",
3300 /* mark the hw as uninitialized... */
3301 p_hwfn->hw_init_done = false;
3303 /* Send unload command to MCP */
3304 if (!cdev->recov_in_prog) {
3305 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
3308 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3314 qed_slowpath_irq_sync(p_hwfn);
3316 /* After this point no MFW attentions are expected, e.g. prevent
3317 * race between pf stop and dcbx pf update.
3319 rc = qed_sp_pf_stop(p_hwfn);
3322 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3327 qed_wr(p_hwfn, p_ptt,
3328 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3330 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3331 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3332 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3333 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3334 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3336 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3338 /* Disable Attention Generation */
3339 qed_int_igu_disable_int(p_hwfn, p_ptt);
3341 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
3342 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
3344 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
3346 /* Need to wait 1ms to guarantee SBs are cleared */
3347 usleep_range(1000, 2000);
3349 /* Disable PF in HW blocks */
3350 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
3351 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
3353 if (IS_LEAD_HWFN(p_hwfn) &&
3354 test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
3355 !QED_IS_FCOE_PERSONALITY(p_hwfn))
3356 qed_llh_remove_mac_filter(cdev, 0,
3357 p_hwfn->hw_info.hw_mac_addr);
3359 if (!cdev->recov_in_prog) {
3360 rc = qed_mcp_unload_done(p_hwfn, p_ptt);
3363 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
3370 if (IS_PF(cdev) && !cdev->recov_in_prog) {
3371 p_hwfn = QED_LEADING_HWFN(cdev);
3372 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
3374 /* Clear the PF's internal FID_enable in the PXP.
3375 * In CMT this should only be done for first hw-function, and
3376 * only after all transactions have stopped for all active
3379 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3382 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
3391 int qed_hw_stop_fastpath(struct qed_dev *cdev)
3395 for_each_hwfn(cdev, j) {
3396 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3397 struct qed_ptt *p_ptt;
3400 qed_vf_pf_int_cleanup(p_hwfn);
3403 p_ptt = qed_ptt_acquire(p_hwfn);
3408 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
3410 qed_wr(p_hwfn, p_ptt,
3411 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3413 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3414 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3415 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3416 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3417 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3419 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
3421 /* Need to wait 1ms to guarantee SBs are cleared */
3422 usleep_range(1000, 2000);
3423 qed_ptt_release(p_hwfn, p_ptt);
3429 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
3431 struct qed_ptt *p_ptt;
3433 if (IS_VF(p_hwfn->cdev))
3436 p_ptt = qed_ptt_acquire(p_hwfn);
3440 if (p_hwfn->p_rdma_info &&
3441 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
3442 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
3444 /* Re-open incoming traffic */
3445 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
3446 qed_ptt_release(p_hwfn, p_ptt);
3451 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3452 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
3454 qed_ptt_pool_free(p_hwfn);
3455 kfree(p_hwfn->hw_info.p_igu_info);
3456 p_hwfn->hw_info.p_igu_info = NULL;
3459 /* Setup bar access */
3460 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
3462 /* clear indirect access */
3463 if (QED_IS_AH(p_hwfn->cdev)) {
3464 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3465 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
3466 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3467 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
3468 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3469 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
3470 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3471 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
3473 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3474 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3475 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3476 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3477 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3478 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3479 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3480 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3483 /* Clean previous pglue_b errors if such exist */
3484 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3486 /* enable internal target-read */
3487 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3488 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3491 static void get_function_id(struct qed_hwfn *p_hwfn)
3494 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
3495 PXP_PF_ME_OPAQUE_ADDR);
3497 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3499 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3500 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3501 PXP_CONCRETE_FID_PFID);
3502 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3503 PXP_CONCRETE_FID_PORT);
3505 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
3506 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3507 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3510 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
3512 u32 *feat_num = p_hwfn->hw_info.feat_num;
3513 struct qed_sb_cnt_info sb_cnt;
3516 memset(&sb_cnt, 0, sizeof(sb_cnt));
3517 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
3519 if (IS_ENABLED(CONFIG_QED_RDMA) &&
3520 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
3521 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
3522 * the status blocks equally between L2 / RoCE but with
3523 * consideration as to how many l2 queues / cnqs we have.
3525 feat_num[QED_RDMA_CNQ] =
3526 min_t(u32, sb_cnt.cnt / 2,
3527 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
3529 non_l2_sbs = feat_num[QED_RDMA_CNQ];
3531 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
3532 /* Start by allocating VF queues, then PF's */
3533 feat_num[QED_VF_L2_QUE] = min_t(u32,
3534 RESC_NUM(p_hwfn, QED_L2_QUEUE),
3536 feat_num[QED_PF_L2_QUE] = min_t(u32,
3537 sb_cnt.cnt - non_l2_sbs,
3544 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
3545 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
3549 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
3550 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
3555 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
3556 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
3557 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
3558 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
3559 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
3560 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
3564 const char *qed_hw_get_resc_name(enum qed_resources res_id)
3581 case QED_RDMA_CNQ_RAM:
3582 return "RDMA_CNQ_RAM";
3585 case QED_LL2_RAM_QUEUE:
3586 return "LL2_RAM_QUEUE";
3587 case QED_LL2_CTX_QUEUE:
3588 return "LL2_CTX_QUEUE";
3591 case QED_RDMA_STATS_QUEUE:
3592 return "RDMA_STATS_QUEUE";
3598 return "UNKNOWN_RESOURCE";
3603 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
3604 struct qed_ptt *p_ptt,
3605 enum qed_resources res_id,
3606 u32 resc_max_val, u32 *p_mcp_resp)
3610 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3611 resc_max_val, p_mcp_resp);
3614 "MFW response failure for a max value setting of resource %d [%s]\n",
3615 res_id, qed_hw_get_resc_name(res_id));
3619 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3621 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3622 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
3627 static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
3628 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
3629 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
3630 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
3631 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,},
3632 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
3633 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
3634 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
3635 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
3636 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
3637 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
3638 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
3639 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
3640 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
3643 u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
3645 enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2;
3647 if (type >= QED_NUM_HSI_DEFS) {
3648 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type);
3652 return qed_hsi_def_val[type][chip_id];
3655 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3657 u32 resc_max_val, mcp_resp;
3660 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3662 case QED_LL2_RAM_QUEUE:
3663 resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES;
3665 case QED_LL2_CTX_QUEUE:
3666 resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES;
3668 case QED_RDMA_CNQ_RAM:
3669 /* No need for a case for QED_CMDQS_CQS since
3670 * CNQ/CMDQS are the same resource.
3672 resc_max_val = NUM_OF_GLOBAL_QUEUES;
3674 case QED_RDMA_STATS_QUEUE:
3676 NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev);
3679 resc_max_val = BDQ_NUM_RESOURCES;
3685 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3686 resc_max_val, &mcp_resp);
3690 /* There's no point to continue to the next resource if the
3691 * command is not supported by the MFW.
3692 * We do continue if the command is supported but the resource
3693 * is unknown to the MFW. Such a resource will be later
3694 * configured with the default allocation values.
3696 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3704 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
3705 enum qed_resources res_id,
3706 u32 *p_resc_num, u32 *p_resc_start)
3708 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3709 struct qed_dev *cdev = p_hwfn->cdev;
3713 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs;
3716 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs;
3719 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs;
3722 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs;
3723 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
3726 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs;
3730 /* Each VFC resource can accommodate both a MAC and a VLAN */
3731 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3734 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs;
3736 case QED_LL2_RAM_QUEUE:
3737 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
3739 case QED_LL2_CTX_QUEUE:
3740 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs;
3742 case QED_RDMA_CNQ_RAM:
3744 /* CNQ/CMDQS are the same resource */
3745 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3747 case QED_RDMA_STATS_QUEUE:
3748 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs;
3751 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
3752 p_hwfn->hw_info.personality != QED_PCI_FCOE)
3758 /* Since we want its value to reflect whether MFW supports
3759 * the new scheme, have a default of 0.
3771 else if (p_hwfn->cdev->num_ports_in_engine == 4)
3772 *p_resc_start = p_hwfn->port_id;
3773 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
3774 *p_resc_start = p_hwfn->port_id;
3775 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
3776 *p_resc_start = p_hwfn->port_id + 2;
3779 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3786 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
3787 enum qed_resources res_id)
3789 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3790 u32 mcp_resp, *p_resc_num, *p_resc_start;
3793 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3794 p_resc_start = &RESC_START(p_hwfn, res_id);
3796 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3800 "Failed to get default amount for resource %d [%s]\n",
3801 res_id, qed_hw_get_resc_name(res_id));
3805 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3806 &mcp_resp, p_resc_num, p_resc_start);
3809 "MFW response failure for an allocation request for resource %d [%s]\n",
3810 res_id, qed_hw_get_resc_name(res_id));
3814 /* Default driver values are applied in the following cases:
3815 * - The resource allocation MB command is not supported by the MFW
3816 * - There is an internal error in the MFW while processing the request
3817 * - The resource ID is unknown to the MFW
3819 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3821 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
3823 qed_hw_get_resc_name(res_id),
3824 mcp_resp, dflt_resc_num, dflt_resc_start);
3825 *p_resc_num = dflt_resc_num;
3826 *p_resc_start = dflt_resc_start;
3831 /* PQs have to divide by 8 [that's the HW granularity].
3832 * Reduce number so it would fit.
3834 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
3836 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
3838 (*p_resc_num) & ~0x7,
3839 *p_resc_start, (*p_resc_start) & ~0x7);
3840 *p_resc_num &= ~0x7;
3841 *p_resc_start &= ~0x7;
3847 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
3852 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3853 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
3861 static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn,
3862 struct qed_ptt *p_ptt)
3864 struct qed_dev *cdev = p_hwfn->cdev;
3865 u8 native_ppfid_idx;
3868 /* Calculation of BB/AH is different for native_ppfid_idx */
3869 if (QED_IS_BB(cdev))
3870 native_ppfid_idx = p_hwfn->rel_pf_id;
3872 native_ppfid_idx = p_hwfn->rel_pf_id /
3873 cdev->num_ports_in_engine;
3875 rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
3876 if (rc != 0 && rc != -EOPNOTSUPP)
3878 else if (rc == -EOPNOTSUPP)
3879 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3881 if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
3883 "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
3884 native_ppfid_idx, cdev->ppfid_bitmap);
3885 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3891 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3893 struct qed_resc_unlock_params resc_unlock_params;
3894 struct qed_resc_lock_params resc_lock_params;
3895 bool b_ah = QED_IS_AH(p_hwfn->cdev);
3899 /* Setting the max values of the soft resources and the following
3900 * resources allocation queries should be atomic. Since several PFs can
3901 * run in parallel - a resource lock is needed.
3902 * If either the resource lock or resource set value commands are not
3903 * supported - skip the the max values setting, release the lock if
3904 * needed, and proceed to the queries. Other failures, including a
3905 * failure to acquire the lock, will cause this function to fail.
3907 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3908 QED_RESC_LOCK_RESC_ALLOC, false);
3910 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3911 if (rc && rc != -EINVAL) {
3913 } else if (rc == -EINVAL) {
3915 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3916 } else if (!rc && !resc_lock_params.b_granted) {
3918 "Failed to acquire the resource lock for the resource allocation commands\n");
3921 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
3922 if (rc && rc != -EINVAL) {
3924 "Failed to set the max values of the soft resources\n");
3925 goto unlock_and_exit;
3926 } else if (rc == -EINVAL) {
3928 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3929 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
3930 &resc_unlock_params);
3933 "Failed to release the resource lock for the resource allocation commands\n");
3937 rc = qed_hw_set_resc_info(p_hwfn);
3939 goto unlock_and_exit;
3941 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3942 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3945 "Failed to release the resource lock for the resource allocation commands\n");
3949 if (IS_LEAD_HWFN(p_hwfn)) {
3950 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
3955 /* Sanity for ILT */
3956 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3957 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3958 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
3959 RESC_START(p_hwfn, QED_ILT),
3960 RESC_END(p_hwfn, QED_ILT) - 1);
3964 /* This will also learn the number of SBs from MFW */
3965 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
3968 qed_hw_set_feat(p_hwfn);
3970 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
3971 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
3972 qed_hw_get_resc_name(res_id),
3973 RESC_NUM(p_hwfn, res_id),
3974 RESC_START(p_hwfn, res_id));
3979 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
3980 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3984 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3986 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
3987 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
3988 struct qed_mcp_link_capabilities *p_caps;
3989 struct qed_mcp_link_params *link;
3991 /* Read global nvm_cfg address */
3992 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
3994 /* Verify MCP has initialized it */
3995 if (!nvm_cfg_addr) {
3996 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
4000 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
4001 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4003 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4004 offsetof(struct nvm_cfg1, glob) +
4005 offsetof(struct nvm_cfg1_glob, core_cfg);
4007 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
4009 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4010 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4011 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4012 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
4014 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4015 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
4017 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4018 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
4020 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4021 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
4023 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4024 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
4026 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4027 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
4029 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4030 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
4032 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4033 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
4035 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4036 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
4038 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4039 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
4041 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4042 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
4045 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
4049 /* Read default link configuration */
4050 link = &p_hwfn->mcp_info->link_input;
4051 p_caps = &p_hwfn->mcp_info->link_capabilities;
4052 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4053 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4054 link_temp = qed_rd(p_hwfn, p_ptt,
4056 offsetof(struct nvm_cfg1_port, speed_cap_mask));
4057 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4058 link->speed.advertised_speeds = link_temp;
4060 link_temp = link->speed.advertised_speeds;
4061 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
4063 link_temp = qed_rd(p_hwfn, p_ptt,
4065 offsetof(struct nvm_cfg1_port, link_settings));
4066 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4067 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4068 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4069 link->speed.autoneg = true;
4071 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4072 link->speed.forced_speed = 1000;
4074 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4075 link->speed.forced_speed = 10000;
4077 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
4078 link->speed.forced_speed = 20000;
4080 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4081 link->speed.forced_speed = 25000;
4083 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4084 link->speed.forced_speed = 40000;
4086 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4087 link->speed.forced_speed = 50000;
4089 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4090 link->speed.forced_speed = 100000;
4093 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
4096 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
4097 link->speed.autoneg;
4099 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
4100 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
4101 link->pause.autoneg = !!(link_temp &
4102 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4103 link->pause.forced_rx = !!(link_temp &
4104 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4105 link->pause.forced_tx = !!(link_temp &
4106 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4107 link->loopback_mode = 0;
4109 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4110 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
4111 offsetof(struct nvm_cfg1_port, ext_phy));
4112 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4113 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4114 p_caps->default_eee = QED_MCP_EEE_ENABLED;
4115 link->eee.enable = true;
4116 switch (link_temp) {
4117 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4118 p_caps->default_eee = QED_MCP_EEE_DISABLED;
4119 link->eee.enable = false;
4121 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4122 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4124 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4125 p_caps->eee_lpi_timer =
4126 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4128 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4129 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4133 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4134 link->eee.tx_lpi_enable = link->eee.enable;
4135 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
4137 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
4142 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
4143 link->speed.forced_speed,
4144 link->speed.advertised_speeds,
4145 link->speed.autoneg,
4146 link->pause.autoneg,
4147 p_caps->default_eee, p_caps->eee_lpi_timer);
4149 if (IS_LEAD_HWFN(p_hwfn)) {
4150 struct qed_dev *cdev = p_hwfn->cdev;
4152 /* Read Multi-function information from shmem */
4153 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4154 offsetof(struct nvm_cfg1, glob) +
4155 offsetof(struct nvm_cfg1_glob, generic_cont0);
4157 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
4159 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4160 NVM_CFG1_GLOB_MF_MODE_OFFSET;
4163 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4164 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
4166 case NVM_CFG1_GLOB_MF_MODE_UFP:
4167 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4168 BIT(QED_MF_LLH_PROTO_CLSS) |
4169 BIT(QED_MF_UFP_SPECIFIC) |
4170 BIT(QED_MF_8021Q_TAGGING) |
4171 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4173 case NVM_CFG1_GLOB_MF_MODE_BD:
4174 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4175 BIT(QED_MF_LLH_PROTO_CLSS) |
4176 BIT(QED_MF_8021AD_TAGGING) |
4177 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4179 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4180 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4181 BIT(QED_MF_LLH_PROTO_CLSS) |
4182 BIT(QED_MF_LL2_NON_UNICAST) |
4183 BIT(QED_MF_INTER_PF_SWITCH);
4185 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4186 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4187 BIT(QED_MF_LLH_PROTO_CLSS) |
4188 BIT(QED_MF_LL2_NON_UNICAST);
4189 if (QED_IS_BB(p_hwfn->cdev))
4190 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
4194 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4198 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4199 p_hwfn->cdev->mf_bits);
4201 /* Read device capabilities information from shmem */
4202 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4203 offsetof(struct nvm_cfg1, glob) +
4204 offsetof(struct nvm_cfg1_glob, device_capabilities);
4206 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
4207 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
4208 __set_bit(QED_DEV_CAP_ETH,
4209 &p_hwfn->hw_info.device_capabilities);
4210 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
4211 __set_bit(QED_DEV_CAP_FCOE,
4212 &p_hwfn->hw_info.device_capabilities);
4213 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
4214 __set_bit(QED_DEV_CAP_ISCSI,
4215 &p_hwfn->hw_info.device_capabilities);
4216 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
4217 __set_bit(QED_DEV_CAP_ROCE,
4218 &p_hwfn->hw_info.device_capabilities);
4220 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
4223 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4225 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
4226 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
4227 struct qed_dev *cdev = p_hwfn->cdev;
4229 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
4231 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
4232 * in the other bits are selected.
4233 * Bits 1-15 are for functions 1-15, respectively, and their value is
4234 * '0' only for enabled functions (function 0 always exists and
4236 * In case of CMT, only the "even" functions are enabled, and thus the
4237 * number of functions for both hwfns is learnt from the same bits.
4239 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
4241 if (reg_function_hide & 0x1) {
4242 if (QED_IS_BB(cdev)) {
4243 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
4255 /* Get the number of the enabled functions on the engine */
4256 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
4263 /* Get the PF index within the enabled functions */
4264 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
4265 tmp = reg_function_hide & eng_mask & low_pfs_mask;
4273 p_hwfn->num_funcs_on_engine = num_funcs;
4274 p_hwfn->enabled_func_idx = enabled_func_idx;
4278 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
4281 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
4284 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4286 u32 addr, global_offsize, global_addr, port_mode;
4287 struct qed_dev *cdev = p_hwfn->cdev;
4289 /* In CMT there is always only one port */
4290 if (cdev->num_hwfns > 1) {
4291 cdev->num_ports_in_engine = 1;
4292 cdev->num_ports = 1;
4296 /* Determine the number of ports per engine */
4297 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
4298 switch (port_mode) {
4300 cdev->num_ports_in_engine = 1;
4303 cdev->num_ports_in_engine = 2;
4306 cdev->num_ports_in_engine = 4;
4309 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
4310 cdev->num_ports_in_engine = 1; /* Default to something */
4314 /* Get the total number of ports of the device */
4315 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
4317 global_offsize = qed_rd(p_hwfn, p_ptt, addr);
4318 global_addr = SECTION_ADDR(global_offsize, 0);
4319 addr = global_addr + offsetof(struct public_global, max_ports);
4320 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
4323 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4325 struct qed_mcp_link_capabilities *p_caps;
4328 p_caps = &p_hwfn->mcp_info->link_capabilities;
4329 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
4332 p_caps->eee_speed_caps = 0;
4333 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
4334 offsetof(struct public_port, eee_status));
4335 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
4336 EEE_SUPPORTED_SPEED_OFFSET;
4338 if (eee_status & EEE_1G_SUPPORTED)
4339 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
4340 if (eee_status & EEE_10G_ADV)
4341 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
4345 qed_get_hw_info(struct qed_hwfn *p_hwfn,
4346 struct qed_ptt *p_ptt,
4347 enum qed_pci_personality personality)
4351 /* Since all information is common, only first hwfns should do this */
4352 if (IS_LEAD_HWFN(p_hwfn)) {
4353 rc = qed_iov_hw_info(p_hwfn);
4358 if (IS_LEAD_HWFN(p_hwfn))
4359 qed_hw_info_port_num(p_hwfn, p_ptt);
4361 qed_mcp_get_capabilities(p_hwfn, p_ptt);
4363 qed_hw_get_nvm_info(p_hwfn, p_ptt);
4365 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
4369 if (qed_mcp_is_init(p_hwfn))
4370 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
4371 p_hwfn->mcp_info->func_info.mac);
4373 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
4375 if (qed_mcp_is_init(p_hwfn)) {
4376 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
4377 p_hwfn->hw_info.ovlan =
4378 p_hwfn->mcp_info->func_info.ovlan;
4380 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
4382 qed_get_eee_caps(p_hwfn, p_ptt);
4384 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
4387 if (qed_mcp_is_init(p_hwfn)) {
4388 enum qed_pci_personality protocol;
4390 protocol = p_hwfn->mcp_info->func_info.protocol;
4391 p_hwfn->hw_info.personality = protocol;
4394 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
4395 p_hwfn->hw_info.multi_tc_roce_en = 1;
4397 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4398 p_hwfn->hw_info.num_active_tc = 1;
4400 qed_get_num_funcs(p_hwfn, p_ptt);
4402 if (qed_mcp_is_init(p_hwfn))
4403 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4405 return qed_hw_get_resc(p_hwfn, p_ptt);
4408 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4410 struct qed_dev *cdev = p_hwfn->cdev;
4414 /* Read Vendor Id / Device Id */
4415 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
4416 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
4418 /* Determine type */
4419 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
4420 switch (device_id_mask) {
4421 case QED_DEV_ID_MASK_BB:
4422 cdev->type = QED_DEV_TYPE_BB;
4424 case QED_DEV_ID_MASK_AH:
4425 cdev->type = QED_DEV_TYPE_AH;
4428 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
4432 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4433 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4435 MASK_FIELD(CHIP_REV, cdev->chip_rev);
4437 /* Learn number of HW-functions */
4438 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4440 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4441 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
4442 cdev->num_hwfns = 2;
4444 cdev->num_hwfns = 1;
4447 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
4448 MISCS_REG_CHIP_TEST_REG) >> 4;
4449 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
4450 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4451 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
4453 DP_INFO(cdev->hwfns,
4454 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4455 QED_IS_BB(cdev) ? "BB" : "AH",
4456 'A' + cdev->chip_rev,
4457 (int)cdev->chip_metal,
4458 cdev->chip_num, cdev->chip_rev,
4459 cdev->chip_bond_id, cdev->chip_metal);
4464 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
4466 kfree(p_hwfn->nvm_info.image_att);
4467 p_hwfn->nvm_info.image_att = NULL;
4470 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
4471 void __iomem *p_regview,
4472 void __iomem *p_doorbells,
4474 enum qed_pci_personality personality)
4476 struct qed_dev *cdev = p_hwfn->cdev;
4479 /* Split PCI bars evenly between hwfns */
4480 p_hwfn->regview = p_regview;
4481 p_hwfn->doorbells = p_doorbells;
4482 p_hwfn->db_phys_addr = db_phys_addr;
4484 if (IS_VF(p_hwfn->cdev))
4485 return qed_vf_hw_prepare(p_hwfn);
4487 /* Validate that chip access is feasible */
4488 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4490 "Reading the ME register returns all Fs; Preventing further chip access\n");
4494 get_function_id(p_hwfn);
4496 /* Allocate PTT pool */
4497 rc = qed_ptt_pool_alloc(p_hwfn);
4501 /* Allocate the main PTT */
4502 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4504 /* First hwfn learns basic information, e.g., number of hwfns */
4505 if (!p_hwfn->my_id) {
4506 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4511 qed_hw_hwfn_prepare(p_hwfn);
4513 /* Initialize MCP structure */
4514 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4516 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
4520 /* Read the device configuration information from the HW and SHMEM */
4521 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
4523 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
4527 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
4528 * is called as it sets the ports number in an engine.
4530 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
4531 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4533 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
4536 /* NVRAM info initialization and population */
4537 if (IS_LEAD_HWFN(p_hwfn)) {
4538 rc = qed_mcp_nvm_info_populate(p_hwfn);
4541 "Failed to populate nvm info shadow\n");
4546 /* Allocate the init RT array and initialize the init-ops engine */
4547 rc = qed_init_alloc(p_hwfn);
4553 if (IS_LEAD_HWFN(p_hwfn))
4554 qed_nvm_info_free(p_hwfn);
4556 if (IS_LEAD_HWFN(p_hwfn))
4557 qed_iov_free_hw_info(p_hwfn->cdev);
4558 qed_mcp_free(p_hwfn);
4560 qed_hw_hwfn_free(p_hwfn);
4565 int qed_hw_prepare(struct qed_dev *cdev,
4568 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4571 /* Store the precompiled init data ptrs */
4573 qed_init_iro_array(cdev);
4575 /* Initialize the first hwfn - will learn number of hwfns */
4576 rc = qed_hw_prepare_single(p_hwfn,
4584 personality = p_hwfn->hw_info.personality;
4586 /* Initialize the rest of the hwfns */
4587 if (cdev->num_hwfns > 1) {
4588 void __iomem *p_regview, *p_doorbell;
4592 /* adjust bar offset for second engine */
4593 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4595 p_regview = cdev->regview + offset;
4597 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4600 p_doorbell = cdev->doorbells + offset;
4602 db_phys_addr = cdev->db_phys_addr + offset;
4604 /* prepare second hw function */
4605 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
4606 p_doorbell, db_phys_addr,
4609 /* in case of error, need to free the previously
4610 * initiliazed hwfn 0.
4614 qed_init_free(p_hwfn);
4615 qed_nvm_info_free(p_hwfn);
4616 qed_mcp_free(p_hwfn);
4617 qed_hw_hwfn_free(p_hwfn);
4625 void qed_hw_remove(struct qed_dev *cdev)
4627 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4631 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4632 QED_OV_DRIVER_STATE_NOT_LOADED);
4634 for_each_hwfn(cdev, i) {
4635 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4638 qed_vf_pf_release(p_hwfn);
4642 qed_init_free(p_hwfn);
4643 qed_hw_hwfn_free(p_hwfn);
4644 qed_mcp_free(p_hwfn);
4647 qed_iov_free_hw_info(cdev);
4649 qed_nvm_info_free(p_hwfn);
4652 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
4653 struct qed_chain *p_chain)
4655 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
4656 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
4657 struct qed_chain_next *p_next;
4663 size = p_chain->elem_size * p_chain->usable_per_page;
4665 for (i = 0; i < p_chain->page_cnt; i++) {
4669 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
4670 p_virt_next = p_next->next_virt;
4671 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
4673 dma_free_coherent(&cdev->pdev->dev,
4674 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
4676 p_virt = p_virt_next;
4677 p_phys = p_phys_next;
4681 static void qed_chain_free_single(struct qed_dev *cdev,
4682 struct qed_chain *p_chain)
4684 if (!p_chain->p_virt_addr)
4687 dma_free_coherent(&cdev->pdev->dev,
4688 QED_CHAIN_PAGE_SIZE,
4689 p_chain->p_virt_addr, p_chain->p_phys_addr);
4692 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
4694 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
4695 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
4696 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
4698 if (!pp_virt_addr_tbl)
4704 for (i = 0; i < page_cnt; i++) {
4705 if (!pp_virt_addr_tbl[i])
4708 dma_free_coherent(&cdev->pdev->dev,
4709 QED_CHAIN_PAGE_SIZE,
4710 pp_virt_addr_tbl[i],
4711 *(dma_addr_t *)p_pbl_virt);
4713 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
4716 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4718 if (!p_chain->b_external_pbl)
4719 dma_free_coherent(&cdev->pdev->dev,
4721 p_chain->pbl_sp.p_virt_table,
4722 p_chain->pbl_sp.p_phys_table);
4724 vfree(p_chain->pbl.pp_virt_addr_tbl);
4725 p_chain->pbl.pp_virt_addr_tbl = NULL;
4728 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
4730 switch (p_chain->mode) {
4731 case QED_CHAIN_MODE_NEXT_PTR:
4732 qed_chain_free_next_ptr(cdev, p_chain);
4734 case QED_CHAIN_MODE_SINGLE:
4735 qed_chain_free_single(cdev, p_chain);
4737 case QED_CHAIN_MODE_PBL:
4738 qed_chain_free_pbl(cdev, p_chain);
4744 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
4745 enum qed_chain_cnt_type cnt_type,
4746 size_t elem_size, u32 page_cnt)
4748 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
4750 /* The actual chain size can be larger than the maximal possible value
4751 * after rounding up the requested elements number to pages, and after
4752 * taking into acount the unusuable elements (next-ptr elements).
4753 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
4754 * size/capacity fields are of a u32 type.
4756 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
4757 chain_size > ((u32)U16_MAX + 1)) ||
4758 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
4760 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
4769 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
4771 void *p_virt = NULL, *p_virt_prev = NULL;
4772 dma_addr_t p_phys = 0;
4775 for (i = 0; i < p_chain->page_cnt; i++) {
4776 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4777 QED_CHAIN_PAGE_SIZE,
4778 &p_phys, GFP_KERNEL);
4783 qed_chain_init_mem(p_chain, p_virt, p_phys);
4784 qed_chain_reset(p_chain);
4786 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4790 p_virt_prev = p_virt;
4792 /* Last page's next element should point to the beginning of the
4795 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
4796 p_chain->p_virt_addr,
4797 p_chain->p_phys_addr);
4803 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
4805 dma_addr_t p_phys = 0;
4806 void *p_virt = NULL;
4808 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4809 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
4813 qed_chain_init_mem(p_chain, p_virt, p_phys);
4814 qed_chain_reset(p_chain);
4820 qed_chain_alloc_pbl(struct qed_dev *cdev,
4821 struct qed_chain *p_chain,
4822 struct qed_chain_ext_pbl *ext_pbl)
4824 u32 page_cnt = p_chain->page_cnt, size, i;
4825 dma_addr_t p_phys = 0, p_pbl_phys = 0;
4826 void **pp_virt_addr_tbl = NULL;
4827 u8 *p_pbl_virt = NULL;
4828 void *p_virt = NULL;
4830 size = page_cnt * sizeof(*pp_virt_addr_tbl);
4831 pp_virt_addr_tbl = vzalloc(size);
4832 if (!pp_virt_addr_tbl)
4835 /* The allocation of the PBL table is done with its full size, since it
4836 * is expected to be successive.
4837 * qed_chain_init_pbl_mem() is called even in a case of an allocation
4838 * failure, since pp_virt_addr_tbl was previously allocated, and it
4839 * should be saved to allow its freeing during the error flow.
4841 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
4844 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
4845 size, &p_pbl_phys, GFP_KERNEL);
4847 p_pbl_virt = ext_pbl->p_pbl_virt;
4848 p_pbl_phys = ext_pbl->p_pbl_phys;
4849 p_chain->b_external_pbl = true;
4852 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
4857 for (i = 0; i < page_cnt; i++) {
4858 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
4859 QED_CHAIN_PAGE_SIZE,
4860 &p_phys, GFP_KERNEL);
4865 qed_chain_init_mem(p_chain, p_virt, p_phys);
4866 qed_chain_reset(p_chain);
4869 /* Fill the PBL table with the physical address of the page */
4870 *(dma_addr_t *)p_pbl_virt = p_phys;
4871 /* Keep the virtual address of the page */
4872 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
4874 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
4880 int qed_chain_alloc(struct qed_dev *cdev,
4881 enum qed_chain_use_mode intended_use,
4882 enum qed_chain_mode mode,
4883 enum qed_chain_cnt_type cnt_type,
4886 struct qed_chain *p_chain,
4887 struct qed_chain_ext_pbl *ext_pbl)
4892 if (mode == QED_CHAIN_MODE_SINGLE)
4895 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
4897 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
4900 "Cannot allocate a chain with the given arguments:\n");
4902 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
4903 intended_use, mode, cnt_type, num_elems, elem_size);
4907 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
4911 case QED_CHAIN_MODE_NEXT_PTR:
4912 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
4914 case QED_CHAIN_MODE_SINGLE:
4915 rc = qed_chain_alloc_single(cdev, p_chain);
4917 case QED_CHAIN_MODE_PBL:
4918 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
4927 qed_chain_free(cdev, p_chain);
4931 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
4933 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
4936 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
4937 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
4939 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4945 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
4950 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4952 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
4955 min = (u8)RESC_START(p_hwfn, QED_VPORT);
4956 max = min + RESC_NUM(p_hwfn, QED_VPORT);
4958 "vport id [%d] is not valid, available indices [%d - %d]\n",
4964 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
4969 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4971 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
4974 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
4975 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
4977 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4983 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
4988 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4989 u32 hw_addr, void *p_eth_qzone,
4990 size_t eth_qzone_size, u8 timeset)
4992 struct coalescing_timeset *p_coal_timeset;
4994 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4995 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4999 p_coal_timeset = p_eth_qzone;
5000 memset(p_eth_qzone, 0, eth_qzone_size);
5001 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
5002 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
5003 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
5008 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
5010 struct qed_queue_cid *p_cid = p_handle;
5011 struct qed_hwfn *p_hwfn;
5012 struct qed_ptt *p_ptt;
5015 p_hwfn = p_cid->p_owner;
5017 if (IS_VF(p_hwfn->cdev))
5018 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
5020 p_ptt = qed_ptt_acquire(p_hwfn);
5025 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
5028 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
5032 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
5035 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
5038 qed_ptt_release(p_hwfn, p_ptt);
5042 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
5043 struct qed_ptt *p_ptt,
5044 u16 coalesce, struct qed_queue_cid *p_cid)
5046 struct ustorm_eth_queue_zone eth_qzone;
5047 u8 timeset, timer_res;
5051 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5052 if (coalesce <= 0x7F) {
5054 } else if (coalesce <= 0xFF) {
5056 } else if (coalesce <= 0x1FF) {
5059 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5062 timeset = (u8)(coalesce >> timer_res);
5064 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5065 p_cid->sb_igu_id, false);
5069 address = BAR0_MAP_REG_USDM_RAM +
5070 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5072 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5073 sizeof(struct ustorm_eth_queue_zone), timeset);
5081 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
5082 struct qed_ptt *p_ptt,
5083 u16 coalesce, struct qed_queue_cid *p_cid)
5085 struct xstorm_eth_queue_zone eth_qzone;
5086 u8 timeset, timer_res;
5090 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
5091 if (coalesce <= 0x7F) {
5093 } else if (coalesce <= 0xFF) {
5095 } else if (coalesce <= 0x1FF) {
5098 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
5101 timeset = (u8)(coalesce >> timer_res);
5103 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
5104 p_cid->sb_igu_id, true);
5108 address = BAR0_MAP_REG_XSDM_RAM +
5109 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
5111 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
5112 sizeof(struct xstorm_eth_queue_zone), timeset);
5117 /* Calculate final WFQ values for all vports and configure them.
5118 * After this configuration each vport will have
5119 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
5121 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5122 struct qed_ptt *p_ptt,
5125 struct init_qm_vport_params *vport_params;
5128 vport_params = p_hwfn->qm_info.qm_vport_params;
5130 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5131 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5133 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) /
5135 qed_init_vport_wfq(p_hwfn, p_ptt,
5136 vport_params[i].first_tx_pq_id,
5137 vport_params[i].wfq);
5141 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
5147 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
5148 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
5151 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
5152 struct qed_ptt *p_ptt,
5155 struct init_qm_vport_params *vport_params;
5158 vport_params = p_hwfn->qm_info.qm_vport_params;
5160 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5161 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
5162 qed_init_vport_wfq(p_hwfn, p_ptt,
5163 vport_params[i].first_tx_pq_id,
5164 vport_params[i].wfq);
5168 /* This function performs several validations for WFQ
5169 * configuration and required min rate for a given vport
5170 * 1. req_rate must be greater than one percent of min_pf_rate.
5171 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5172 * rates to get less than one percent of min_pf_rate.
5173 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5175 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
5176 u16 vport_id, u32 req_rate, u32 min_pf_rate)
5178 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5179 int non_requested_count = 0, req_count = 0, i, num_vports;
5181 num_vports = p_hwfn->qm_info.num_vports;
5183 /* Accounting for the vports which are configured for WFQ explicitly */
5184 for (i = 0; i < num_vports; i++) {
5187 if ((i != vport_id) &&
5188 p_hwfn->qm_info.wfq_data[i].configured) {
5190 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5191 total_req_min_rate += tmp_speed;
5195 /* Include current vport data as well */
5197 total_req_min_rate += req_rate;
5198 non_requested_count = num_vports - req_count;
5200 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
5201 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5202 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5203 vport_id, req_rate, min_pf_rate);
5207 if (num_vports > QED_WFQ_UNIT) {
5208 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5209 "Number of vports is greater than %d\n",
5214 if (total_req_min_rate > min_pf_rate) {
5215 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5216 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5217 total_req_min_rate, min_pf_rate);
5221 total_left_rate = min_pf_rate - total_req_min_rate;
5223 left_rate_per_vp = total_left_rate / non_requested_count;
5224 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
5225 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5226 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5227 left_rate_per_vp, min_pf_rate);
5231 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5232 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5234 for (i = 0; i < num_vports; i++) {
5235 if (p_hwfn->qm_info.wfq_data[i].configured)
5238 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5244 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
5245 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
5247 struct qed_mcp_link_state *p_link;
5250 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
5252 if (!p_link->min_pf_rate) {
5253 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5254 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5258 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5261 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5262 p_link->min_pf_rate);
5265 "Validation failed while configuring min rate\n");
5270 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
5271 struct qed_ptt *p_ptt,
5274 bool use_wfq = false;
5278 /* Validate all pre configured vports for wfq */
5279 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5282 if (!p_hwfn->qm_info.wfq_data[i].configured)
5285 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5288 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5291 "WFQ validation failed while configuring min rate\n");
5297 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5299 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5304 /* Main API for qed clients to configure vport min rate.
5305 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5306 * rate - Speed in Mbps needs to be assigned to a given vport.
5308 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
5310 int i, rc = -EINVAL;
5312 /* Currently not supported; Might change in future */
5313 if (cdev->num_hwfns > 1) {
5315 "WFQ configuration is not supported for this device\n");
5319 for_each_hwfn(cdev, i) {
5320 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5321 struct qed_ptt *p_ptt;
5323 p_ptt = qed_ptt_acquire(p_hwfn);
5327 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5330 qed_ptt_release(p_hwfn, p_ptt);
5334 qed_ptt_release(p_hwfn, p_ptt);
5340 /* API to configure WFQ from mcp link change */
5341 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
5342 struct qed_ptt *p_ptt, u32 min_pf_rate)
5346 if (cdev->num_hwfns > 1) {
5349 "WFQ configuration is not supported for this device\n");
5353 for_each_hwfn(cdev, i) {
5354 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5356 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5361 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
5362 struct qed_ptt *p_ptt,
5363 struct qed_mcp_link_state *p_link,
5368 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5370 if (!p_link->line_speed && (max_bw != 100))
5373 p_link->speed = (p_link->line_speed * max_bw) / 100;
5374 p_hwfn->qm_info.pf_rl = p_link->speed;
5376 /* Since the limiter also affects Tx-switched traffic, we don't want it
5377 * to limit such traffic in case there's no actual limit.
5378 * In that case, set limit to imaginary high boundary.
5381 p_hwfn->qm_info.pf_rl = 100000;
5383 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5384 p_hwfn->qm_info.pf_rl);
5386 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5387 "Configured MAX bandwidth to be %08x Mb/sec\n",
5393 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5394 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
5396 int i, rc = -EINVAL;
5398 if (max_bw < 1 || max_bw > 100) {
5399 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
5403 for_each_hwfn(cdev, i) {
5404 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5405 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5406 struct qed_mcp_link_state *p_link;
5407 struct qed_ptt *p_ptt;
5409 p_link = &p_lead->mcp_info->link_output;
5411 p_ptt = qed_ptt_acquire(p_hwfn);
5415 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5418 qed_ptt_release(p_hwfn, p_ptt);
5427 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
5428 struct qed_ptt *p_ptt,
5429 struct qed_mcp_link_state *p_link,
5434 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5435 p_hwfn->qm_info.pf_wfq = min_bw;
5437 if (!p_link->line_speed)
5440 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5442 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5444 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5445 "Configured MIN bandwidth to be %d Mb/sec\n",
5446 p_link->min_pf_rate);
5451 /* Main API to configure PF min bandwidth where bw range is [1-100] */
5452 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
5454 int i, rc = -EINVAL;
5456 if (min_bw < 1 || min_bw > 100) {
5457 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
5461 for_each_hwfn(cdev, i) {
5462 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5463 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5464 struct qed_mcp_link_state *p_link;
5465 struct qed_ptt *p_ptt;
5467 p_link = &p_lead->mcp_info->link_output;
5469 p_ptt = qed_ptt_acquire(p_hwfn);
5473 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5476 qed_ptt_release(p_hwfn, p_ptt);
5480 if (p_link->min_pf_rate) {
5481 u32 min_rate = p_link->min_pf_rate;
5483 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
5488 qed_ptt_release(p_hwfn, p_ptt);
5494 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
5496 struct qed_mcp_link_state *p_link;
5498 p_link = &p_hwfn->mcp_info->link_output;
5500 if (p_link->min_pf_rate)
5501 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5502 p_link->min_pf_rate);
5504 memset(p_hwfn->qm_info.wfq_data, 0,
5505 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
5508 int qed_device_num_ports(struct qed_dev *cdev)
5510 return cdev->num_ports;
5513 void qed_set_fw_mac_addr(__le16 *fw_msb,
5514 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
5516 ((u8 *)fw_msb)[0] = mac[1];
5517 ((u8 *)fw_msb)[1] = mac[0];
5518 ((u8 *)fw_mid)[0] = mac[3];
5519 ((u8 *)fw_mid)[1] = mac[2];
5520 ((u8 *)fw_lsb)[0] = mac[5];
5521 ((u8 *)fw_lsb)[1] = mac[4];