1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
40 #include <linux/mutex.h>
41 #include <linux/pci.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/vmalloc.h>
45 #include <linux/etherdevice.h>
46 #include <linux/qed/qed_chain.h>
47 #include <linux/qed/qed_if.h>
51 #include "qed_dev_api.h"
55 #include "qed_init_ops.h"
57 #include "qed_iscsi.h"
61 #include "qed_reg_addr.h"
63 #include "qed_sriov.h"
67 static DEFINE_SPINLOCK(qm_lock);
69 #define QED_MIN_DPIS (4)
70 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
73 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
75 u32 bar_reg = (bar_id == BAR_ID_0 ?
76 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
79 if (IS_VF(p_hwfn->cdev))
80 return qed_vf_hw_bar_size(p_hwfn, bar_id);
82 val = qed_rd(p_hwfn, p_ptt, bar_reg);
84 return 1 << (val + 15);
86 /* Old MFW initialized above registered only conditionally */
87 if (p_hwfn->cdev->num_hwfns > 1) {
89 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
90 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
93 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
102 cdev->dp_level = dp_level;
103 cdev->dp_module = dp_module;
104 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
105 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
107 p_hwfn->dp_level = dp_level;
108 p_hwfn->dp_module = dp_module;
112 void qed_init_struct(struct qed_dev *cdev)
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
121 p_hwfn->b_active = false;
123 mutex_init(&p_hwfn->dmae_info.mutex);
126 /* hwfn 0 is always active */
127 cdev->hwfns[0].b_active = true;
129 /* set the default cache alignment to 128 */
130 cdev->cache_shift = 7;
133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
135 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
137 kfree(qm_info->qm_pq_params);
138 qm_info->qm_pq_params = NULL;
139 kfree(qm_info->qm_vport_params);
140 qm_info->qm_vport_params = NULL;
141 kfree(qm_info->qm_port_params);
142 qm_info->qm_port_params = NULL;
143 kfree(qm_info->wfq_data);
144 qm_info->wfq_data = NULL;
147 void qed_resc_free(struct qed_dev *cdev)
152 for_each_hwfn(cdev, i)
153 qed_l2_free(&cdev->hwfns[i]);
157 kfree(cdev->fw_data);
158 cdev->fw_data = NULL;
160 kfree(cdev->reset_stats);
161 cdev->reset_stats = NULL;
163 for_each_hwfn(cdev, i) {
164 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
166 qed_cxt_mngr_free(p_hwfn);
167 qed_qm_info_free(p_hwfn);
168 qed_spq_free(p_hwfn);
170 qed_consq_free(p_hwfn);
171 qed_int_free(p_hwfn);
172 #ifdef CONFIG_QED_LL2
173 qed_ll2_free(p_hwfn);
175 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
176 qed_fcoe_free(p_hwfn);
178 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
179 qed_iscsi_free(p_hwfn);
180 qed_ooo_free(p_hwfn);
182 qed_iov_free(p_hwfn);
184 qed_dmae_info_free(p_hwfn);
185 qed_dcbx_info_free(p_hwfn);
189 /******************** QM initialization *******************/
190 #define ACTIVE_TCS_BMAP 0x9f
191 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
193 /* determines the physical queue flags for a given PF. */
194 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
202 if (IS_QED_SRIOV(p_hwfn->cdev))
203 flags |= PQ_FLAGS_VFS;
206 switch (p_hwfn->hw_info.personality) {
208 flags |= PQ_FLAGS_MCOS;
211 flags |= PQ_FLAGS_OFLD;
214 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
216 case QED_PCI_ETH_ROCE:
217 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
219 case QED_PCI_ETH_IWARP:
220 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
225 "unknown personality %d\n", p_hwfn->hw_info.personality);
232 /* Getters for resource amounts necessary for qm initialization */
233 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
235 return p_hwfn->hw_info.num_hw_tc;
238 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
240 return IS_QED_SRIOV(p_hwfn->cdev) ?
241 p_hwfn->cdev->p_iov_info->total_vfs : 0;
244 #define NUM_DEFAULT_RLS 1
246 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
248 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
250 /* num RLs can't exceed resource amount of rls or vports */
251 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
252 RESC_NUM(p_hwfn, QED_VPORT));
254 /* Make sure after we reserve there's something left */
255 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
258 /* subtract rls necessary for VFs and one default one for the PF */
259 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
264 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
266 u32 pq_flags = qed_get_pq_flags(p_hwfn);
268 /* all pqs share the same vport, except for vfs and pf_rl pqs */
269 return (!!(PQ_FLAGS_RLS & pq_flags)) *
270 qed_init_qm_get_num_pf_rls(p_hwfn) +
271 (!!(PQ_FLAGS_VFS & pq_flags)) *
272 qed_init_qm_get_num_vfs(p_hwfn) + 1;
275 /* calc amount of PQs according to the requested flags */
276 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
278 u32 pq_flags = qed_get_pq_flags(p_hwfn);
280 return (!!(PQ_FLAGS_RLS & pq_flags)) *
281 qed_init_qm_get_num_pf_rls(p_hwfn) +
282 (!!(PQ_FLAGS_MCOS & pq_flags)) *
283 qed_init_qm_get_num_tcs(p_hwfn) +
284 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
285 (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
286 (!!(PQ_FLAGS_LLT & pq_flags)) +
287 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
290 /* initialize the top level QM params */
291 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
293 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
296 /* pq and vport bases for this PF */
297 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
298 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
300 /* rate limiting and weighted fair queueing are always enabled */
301 qm_info->vport_rl_en = true;
302 qm_info->vport_wfq_en = true;
304 /* TC config is different for AH 4 port */
305 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
307 /* in AH 4 port we have fewer TCs per port */
308 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
311 /* unless MFW indicated otherwise, ooo_tc == 3 for
312 * AH 4-port and 4 otherwise.
314 if (!qm_info->ooo_tc)
315 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
319 /* initialize qm vport params */
320 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
322 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
325 /* all vports participate in weighted fair queueing */
326 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
327 qm_info->qm_vport_params[i].vport_wfq = 1;
330 /* initialize qm port params */
331 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
333 /* Initialize qm port parameters */
334 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
336 /* indicate how ooo and high pri traffic is dealt with */
337 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
338 ACTIVE_TCS_BMAP_4PORT_K2 :
341 for (i = 0; i < num_ports; i++) {
342 struct init_qm_port_params *p_qm_port =
343 &p_hwfn->qm_info.qm_port_params[i];
345 p_qm_port->active = 1;
346 p_qm_port->active_phys_tcs = active_phys_tcs;
347 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
348 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
352 /* Reset the params which must be reset for qm init. QM init may be called as
353 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
354 * params may be affected by the init but would simply recalculate to the same
355 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
356 * affected as these amounts stay the same.
358 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
360 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
362 qm_info->num_pqs = 0;
363 qm_info->num_vports = 0;
364 qm_info->num_pf_rls = 0;
365 qm_info->num_vf_pqs = 0;
366 qm_info->first_vf_pq = 0;
367 qm_info->first_mcos_pq = 0;
368 qm_info->first_rl_pq = 0;
371 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
373 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
375 qm_info->num_vports++;
377 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
379 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
380 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
383 /* initialize a single pq and manage qm_info resources accounting.
384 * The pq_init_flags param determines whether the PQ is rate limited
385 * (for VF or PF) and whether a new vport is allocated to the pq or not
386 * (i.e. vport will be shared).
389 /* flags for pq init */
390 #define PQ_INIT_SHARE_VPORT (1 << 0)
391 #define PQ_INIT_PF_RL (1 << 1)
392 #define PQ_INIT_VF_RL (1 << 2)
394 /* defines for pq init */
395 #define PQ_INIT_DEFAULT_WRR_GROUP 1
396 #define PQ_INIT_DEFAULT_TC 0
397 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
399 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
400 struct qed_qm_info *qm_info,
401 u8 tc, u32 pq_init_flags)
403 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
407 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
410 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
411 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
413 qm_info->qm_pq_params[pq_idx].tc_id = tc;
414 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
415 qm_info->qm_pq_params[pq_idx].rl_valid =
416 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
418 /* qm params accounting */
420 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
421 qm_info->num_vports++;
423 if (pq_init_flags & PQ_INIT_PF_RL)
424 qm_info->num_pf_rls++;
426 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
428 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
429 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
431 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
433 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
434 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
437 /* get pq index according to PQ_FLAGS */
438 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
441 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
443 /* Can't have multiple flags set here */
444 if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
449 return &qm_info->first_rl_pq;
451 return &qm_info->first_mcos_pq;
453 return &qm_info->pure_lb_pq;
455 return &qm_info->ooo_pq;
457 return &qm_info->pure_ack_pq;
459 return &qm_info->offload_pq;
461 return &qm_info->low_latency_pq;
463 return &qm_info->first_vf_pq;
469 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
473 /* save pq index in qm info */
474 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
475 u32 pq_flags, u16 pq_val)
477 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
479 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
482 /* get tx pq index, with the PQ TX base already set (ready for context init) */
483 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
485 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
487 return *base_pq_idx + CM_TX_PQ_BASE;
490 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
492 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
495 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
497 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
500 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
502 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
505 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
507 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
510 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
512 u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
515 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
517 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
520 /* Functions for creating specific types of pqs */
521 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
523 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
525 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
528 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
529 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
532 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
534 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
536 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
539 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
540 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
543 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
545 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
547 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
550 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
551 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
554 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
556 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
558 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
561 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
562 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
565 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
567 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
569 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
572 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
573 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
576 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
578 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
581 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
584 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
585 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
586 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
589 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
591 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
592 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
594 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
597 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
598 qm_info->num_vf_pqs = num_vfs;
599 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
600 qed_init_qm_pq(p_hwfn,
601 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
604 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
606 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
607 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
609 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
612 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
613 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
614 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
617 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
619 /* rate limited pqs, must come first (FW assumption) */
620 qed_init_qm_rl_pqs(p_hwfn);
622 /* pqs for multi cos */
623 qed_init_qm_mcos_pqs(p_hwfn);
625 /* pure loopback pq */
626 qed_init_qm_lb_pq(p_hwfn);
628 /* out of order pq */
629 qed_init_qm_ooo_pq(p_hwfn);
632 qed_init_qm_pure_ack_pq(p_hwfn);
634 /* pq for offloaded protocol */
635 qed_init_qm_offload_pq(p_hwfn);
638 qed_init_qm_low_latency_pq(p_hwfn);
640 /* done sharing vports */
641 qed_init_qm_advance_vport(p_hwfn);
644 qed_init_qm_vf_pqs(p_hwfn);
647 /* compare values of getters against resources amounts */
648 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
650 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
651 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
655 if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
656 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
663 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
665 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
666 struct init_qm_vport_params *vport;
667 struct init_qm_port_params *port;
668 struct init_qm_pq_params *pq;
671 /* top level params */
674 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
676 qm_info->start_vport,
678 qm_info->offload_pq, qm_info->pure_ack_pq);
681 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
683 qm_info->first_vf_pq,
686 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
689 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
692 qm_info->vport_rl_en,
693 qm_info->vport_wfq_en,
696 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
699 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
700 port = &(qm_info->qm_port_params[i]);
703 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
706 port->active_phys_tcs,
707 port->num_pbf_cmd_lines,
708 port->num_btb_blocks, port->reserved);
712 for (i = 0; i < qm_info->num_vports; i++) {
713 vport = &(qm_info->qm_vport_params[i]);
716 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
717 qm_info->start_vport + i,
718 vport->vport_rl, vport->vport_wfq);
719 for (tc = 0; tc < NUM_OF_TCS; tc++)
722 "%d ", vport->first_tx_pq_id[tc]);
723 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
727 for (i = 0; i < qm_info->num_pqs; i++) {
728 pq = &(qm_info->qm_pq_params[i]);
731 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
732 qm_info->start_pq + i,
735 pq->tc_id, pq->wrr_group, pq->rl_valid);
739 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
741 /* reset params required for init run */
742 qed_init_qm_reset_params(p_hwfn);
744 /* init QM top level params */
745 qed_init_qm_params(p_hwfn);
747 /* init QM port params */
748 qed_init_qm_port_params(p_hwfn);
750 /* init QM vport params */
751 qed_init_qm_vport_params(p_hwfn);
753 /* init QM physical queue params */
754 qed_init_qm_pq_params(p_hwfn);
756 /* display all that init */
757 qed_dp_init_qm_params(p_hwfn);
760 /* This function reconfigures the QM pf on the fly.
761 * For this purpose we:
762 * 1. reconfigure the QM database
763 * 2. set new values to runtime array
764 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
765 * 4. activate init tool in QM_PF stage
766 * 5. send an sdm_qm_cmd through rbc interface to release the QM
768 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
770 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
774 /* initialize qed's qm data structure */
775 qed_init_qm_info(p_hwfn);
777 /* stop PF's qm queues */
778 spin_lock_bh(&qm_lock);
779 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
780 qm_info->start_pq, qm_info->num_pqs);
781 spin_unlock_bh(&qm_lock);
785 /* clear the QM_PF runtime phase leftovers from previous init */
786 qed_init_clear_rt_data(p_hwfn);
788 /* prepare QM portion of runtime array */
789 qed_qm_init_pf(p_hwfn, p_ptt, false);
791 /* activate init tool on runtime array */
792 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
793 p_hwfn->hw_info.hw_mode);
797 /* start PF's qm queues */
798 spin_lock_bh(&qm_lock);
799 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
800 qm_info->start_pq, qm_info->num_pqs);
801 spin_unlock_bh(&qm_lock);
808 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
810 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
813 rc = qed_init_qm_sanity(p_hwfn);
817 qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
818 qed_init_qm_get_num_pqs(p_hwfn),
820 if (!qm_info->qm_pq_params)
823 qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
824 qed_init_qm_get_num_vports(p_hwfn),
826 if (!qm_info->qm_vport_params)
829 qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
830 p_hwfn->cdev->num_ports_in_engine,
832 if (!qm_info->qm_port_params)
835 qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
836 qed_init_qm_get_num_vports(p_hwfn),
838 if (!qm_info->wfq_data)
844 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
845 qed_qm_info_free(p_hwfn);
849 int qed_resc_alloc(struct qed_dev *cdev)
851 u32 rdma_tasks, excess_tasks;
856 for_each_hwfn(cdev, i) {
857 rc = qed_l2_alloc(&cdev->hwfns[i]);
864 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
868 for_each_hwfn(cdev, i) {
869 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
870 u32 n_eqes, num_cons;
872 /* First allocate the context manager structure */
873 rc = qed_cxt_mngr_alloc(p_hwfn);
877 /* Set the HW cid/tid numbers (in the contest manager)
878 * Must be done prior to any further computations.
880 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
884 rc = qed_alloc_qm_data(p_hwfn);
889 qed_init_qm_info(p_hwfn);
891 /* Compute the ILT client partition */
892 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
895 "too many ILT lines; re-computing with less lines\n");
896 /* In case there are not enough ILT lines we reduce the
897 * number of RDMA tasks and re-compute.
900 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
904 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
905 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
909 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
912 "failed ILT compute. Requested too many lines: %u\n",
919 /* CID map / ILT shadow table / T2
920 * The talbes sizes are determined by the computations above
922 rc = qed_cxt_tables_alloc(p_hwfn);
926 /* SPQ, must follow ILT because initializes SPQ context */
927 rc = qed_spq_alloc(p_hwfn);
931 /* SP status block allocation */
932 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
935 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
939 rc = qed_iov_alloc(p_hwfn);
944 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
945 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
946 enum protocol_type rdma_proto;
948 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
949 rdma_proto = PROTOCOLID_ROCE;
951 rdma_proto = PROTOCOLID_IWARP;
953 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
956 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
957 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
959 qed_cxt_get_proto_cid_count(p_hwfn,
962 n_eqes += 2 * num_cons;
965 if (n_eqes > 0xFFFF) {
967 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
972 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
976 rc = qed_consq_alloc(p_hwfn);
980 rc = qed_l2_alloc(p_hwfn);
984 #ifdef CONFIG_QED_LL2
985 if (p_hwfn->using_ll2) {
986 rc = qed_ll2_alloc(p_hwfn);
992 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
993 rc = qed_fcoe_alloc(p_hwfn);
998 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
999 rc = qed_iscsi_alloc(p_hwfn);
1002 rc = qed_ooo_alloc(p_hwfn);
1007 /* DMA info initialization */
1008 rc = qed_dmae_info_alloc(p_hwfn);
1012 /* DCBX initialization */
1013 rc = qed_dcbx_info_alloc(p_hwfn);
1018 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1019 if (!cdev->reset_stats)
1027 qed_resc_free(cdev);
1031 void qed_resc_setup(struct qed_dev *cdev)
1036 for_each_hwfn(cdev, i)
1037 qed_l2_setup(&cdev->hwfns[i]);
1041 for_each_hwfn(cdev, i) {
1042 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1044 qed_cxt_mngr_setup(p_hwfn);
1045 qed_spq_setup(p_hwfn);
1046 qed_eq_setup(p_hwfn);
1047 qed_consq_setup(p_hwfn);
1049 /* Read shadow of current MFW mailbox */
1050 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1051 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1052 p_hwfn->mcp_info->mfw_mb_cur,
1053 p_hwfn->mcp_info->mfw_mb_length);
1055 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1057 qed_l2_setup(p_hwfn);
1058 qed_iov_setup(p_hwfn);
1059 #ifdef CONFIG_QED_LL2
1060 if (p_hwfn->using_ll2)
1061 qed_ll2_setup(p_hwfn);
1063 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1064 qed_fcoe_setup(p_hwfn);
1066 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1067 qed_iscsi_setup(p_hwfn);
1068 qed_ooo_setup(p_hwfn);
1073 #define FINAL_CLEANUP_POLL_CNT (100)
1074 #define FINAL_CLEANUP_POLL_TIME (10)
1075 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1076 struct qed_ptt *p_ptt, u16 id, bool is_vf)
1078 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1081 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1082 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1087 command |= X_FINAL_CLEANUP_AGG_INT <<
1088 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1089 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1090 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1091 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1093 /* Make sure notification is not set before initiating final cleanup */
1094 if (REG_RD(p_hwfn, addr)) {
1096 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1097 REG_WR(p_hwfn, addr, 0);
1100 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1101 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
1104 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1106 /* Poll until completion */
1107 while (!REG_RD(p_hwfn, addr) && count--)
1108 msleep(FINAL_CLEANUP_POLL_TIME);
1110 if (REG_RD(p_hwfn, addr))
1114 "Failed to receive FW final cleanup notification\n");
1116 /* Cleanup afterwards */
1117 REG_WR(p_hwfn, addr, 0);
1122 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1126 if (QED_IS_BB_B0(p_hwfn->cdev)) {
1127 hw_mode |= 1 << MODE_BB;
1128 } else if (QED_IS_AH(p_hwfn->cdev)) {
1129 hw_mode |= 1 << MODE_K2;
1131 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1132 p_hwfn->cdev->type);
1136 switch (p_hwfn->cdev->num_ports_in_engine) {
1138 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1141 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1144 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1147 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1148 p_hwfn->cdev->num_ports_in_engine);
1152 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
1153 hw_mode |= 1 << MODE_MF_SD;
1155 hw_mode |= 1 << MODE_MF_SI;
1157 hw_mode |= 1 << MODE_ASIC;
1159 if (p_hwfn->cdev->num_hwfns > 1)
1160 hw_mode |= 1 << MODE_100G;
1162 p_hwfn->hw_info.hw_mode = hw_mode;
1164 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1165 "Configuring function for hw_mode: 0x%08x\n",
1166 p_hwfn->hw_info.hw_mode);
1171 /* Init run time data for all PFs on an engine. */
1172 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1174 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1177 for_each_hwfn(cdev, i) {
1178 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1179 struct qed_igu_info *p_igu_info;
1180 struct qed_igu_block *p_block;
1181 struct cau_sb_entry sb_entry;
1183 p_igu_info = p_hwfn->hw_info.p_igu_info;
1186 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1187 p_block = &p_igu_info->entry[igu_sb_id];
1189 if (!p_block->is_pf)
1192 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1193 p_block->function_id, 0, 0);
1194 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1200 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1201 struct qed_ptt *p_ptt)
1203 u32 val, wr_mbs, cache_line_size;
1205 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1218 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1223 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1224 switch (cache_line_size) {
1239 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1243 if (L1_CACHE_BYTES > wr_mbs)
1245 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1246 L1_CACHE_BYTES, wr_mbs);
1248 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1250 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1251 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1255 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1256 struct qed_ptt *p_ptt, int hw_mode)
1258 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1259 struct qed_qm_common_rt_init_params params;
1260 struct qed_dev *cdev = p_hwfn->cdev;
1261 u8 vf_id, max_num_vfs;
1266 qed_init_cau_rt_data(cdev);
1268 /* Program GTT windows */
1269 qed_gtt_init(p_hwfn);
1271 if (p_hwfn->mcp_info) {
1272 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1273 qm_info->pf_rl_en = true;
1274 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1275 qm_info->pf_wfq_en = true;
1278 memset(¶ms, 0, sizeof(params));
1279 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1280 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1281 params.pf_rl_en = qm_info->pf_rl_en;
1282 params.pf_wfq_en = qm_info->pf_wfq_en;
1283 params.vport_rl_en = qm_info->vport_rl_en;
1284 params.vport_wfq_en = qm_info->vport_wfq_en;
1285 params.port_params = qm_info->qm_port_params;
1287 qed_qm_common_rt_init(p_hwfn, ¶ms);
1289 qed_cxt_hw_init_common(p_hwfn);
1291 qed_init_cache_line_size(p_hwfn, p_ptt);
1293 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1297 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1298 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1300 if (QED_IS_BB(p_hwfn->cdev)) {
1301 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1302 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1303 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1304 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1305 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1307 /* pretend to original PF */
1308 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1311 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1312 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1313 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1314 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1315 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1316 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1317 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1318 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1320 /* pretend to original PF */
1321 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1327 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1328 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1330 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1334 /* Calculate DPI size */
1335 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1336 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1337 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1338 dpi_bit_shift = ilog2(dpi_page_size / 4096);
1339 dpi_count = pwm_region_size / dpi_page_size;
1341 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1342 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1344 p_hwfn->dpi_size = dpi_page_size;
1345 p_hwfn->dpi_count = dpi_count;
1347 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1349 if (dpi_count < min_dpis)
1355 enum QED_ROCE_EDPM_MODE {
1356 QED_ROCE_EDPM_MODE_ENABLE = 0,
1357 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1358 QED_ROCE_EDPM_MODE_DISABLE = 2,
1362 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1364 u32 pwm_regsize, norm_regsize;
1365 u32 non_pwm_conn, min_addr_reg1;
1366 u32 db_bar_size, n_cpus = 1;
1372 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1373 if (p_hwfn->cdev->num_hwfns > 1)
1376 /* Calculate doorbell regions */
1377 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1378 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1380 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1382 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1383 min_addr_reg1 = norm_regsize / 4096;
1384 pwm_regsize = db_bar_size - norm_regsize;
1386 /* Check that the normal and PWM sizes are valid */
1387 if (db_bar_size < norm_regsize) {
1388 DP_ERR(p_hwfn->cdev,
1389 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1390 db_bar_size, norm_regsize);
1394 if (pwm_regsize < QED_MIN_PWM_REGION) {
1395 DP_ERR(p_hwfn->cdev,
1396 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1398 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1402 /* Calculate number of DPIs */
1403 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1404 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1405 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1406 /* Either EDPM is mandatory, or we are attempting to allocate a
1409 n_cpus = num_present_cpus();
1410 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1413 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1414 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1415 if (cond || p_hwfn->dcbx_no_edpm) {
1416 /* Either EDPM is disabled from user configuration, or it is
1417 * disabled via DCBx, or it is not mandatory and we failed to
1418 * allocated a WID per CPU.
1421 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1424 qed_rdma_dpm_bar(p_hwfn, p_ptt);
1427 p_hwfn->wid_count = (u16) n_cpus;
1430 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1435 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1436 "disabled" : "enabled");
1440 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1442 p_hwfn->pf_params.rdma_pf_params.min_dpis);
1446 p_hwfn->dpi_start_offset = norm_regsize;
1448 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1449 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1450 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1451 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1456 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1457 struct qed_ptt *p_ptt, int hw_mode)
1461 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1465 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1470 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1471 struct qed_ptt *p_ptt,
1472 struct qed_tunnel_info *p_tunn,
1475 enum qed_int_mode int_mode,
1476 bool allow_npar_tx_switch)
1478 u8 rel_pf_id = p_hwfn->rel_pf_id;
1481 if (p_hwfn->mcp_info) {
1482 struct qed_mcp_function_info *p_info;
1484 p_info = &p_hwfn->mcp_info->func_info;
1485 if (p_info->bandwidth_min)
1486 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1488 /* Update rate limit once we'll actually have a link */
1489 p_hwfn->qm_info.pf_rl = 100000;
1492 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1494 qed_int_igu_init_rt(p_hwfn);
1496 /* Set VLAN in NIG if needed */
1497 if (hw_mode & BIT(MODE_MF_SD)) {
1498 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1499 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1500 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1501 p_hwfn->hw_info.ovlan);
1503 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1504 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1505 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1509 /* Enable classification by MAC if needed */
1510 if (hw_mode & BIT(MODE_MF_SI)) {
1511 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1512 "Configuring TAGMAC_CLS_TYPE\n");
1513 STORE_RT_REG(p_hwfn,
1514 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1517 /* Protocol Configuration */
1518 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1519 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1520 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1521 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1522 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1524 /* Cleanup chip from previous driver if such remains exist */
1525 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1529 /* Sanity check before the PF init sequence that uses DMAE */
1530 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1534 /* PF Init sequence */
1535 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1539 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1540 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1544 /* Pure runtime initializations - directly to the HW */
1545 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1547 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1552 /* enable interrupts */
1553 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1555 /* send function start command */
1556 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1557 allow_npar_tx_switch);
1559 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1562 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1563 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1564 qed_wr(p_hwfn, p_ptt,
1565 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1572 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1573 struct qed_ptt *p_ptt,
1576 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1578 /* Change PF in PXP */
1579 qed_wr(p_hwfn, p_ptt,
1580 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1582 /* wait until value is set - try for 1 second every 50us */
1583 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1584 val = qed_rd(p_hwfn, p_ptt,
1585 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1589 usleep_range(50, 60);
1592 if (val != set_val) {
1594 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1601 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1602 struct qed_ptt *p_main_ptt)
1604 /* Read shadow of current MFW mailbox */
1605 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1606 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1607 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1611 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1612 struct qed_drv_load_params *p_drv_load)
1614 memset(p_load_req, 0, sizeof(*p_load_req));
1616 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1617 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1618 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1619 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1620 p_load_req->override_force_load = p_drv_load->override_force_load;
1623 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1624 struct qed_hw_init_params *p_params)
1626 if (p_params->p_tunn) {
1627 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1628 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1631 p_hwfn->b_int_enabled = true;
1636 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1638 struct qed_load_req_params load_req_params;
1639 u32 load_code, param, drv_mb_param;
1640 bool b_default_mtu = true;
1641 struct qed_hwfn *p_hwfn;
1642 int rc = 0, mfw_rc, i;
1645 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1646 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1651 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1656 for_each_hwfn(cdev, i) {
1657 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1659 /* If management didn't provide a default, set one of our own */
1660 if (!p_hwfn->hw_info.mtu) {
1661 p_hwfn->hw_info.mtu = 1500;
1662 b_default_mtu = false;
1666 qed_vf_start(p_hwfn, p_params);
1670 /* Enable DMAE in PXP */
1671 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1673 rc = qed_calc_hw_mode(p_hwfn);
1677 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
1679 test_bit(QED_MF_8021AD_TAGGING,
1681 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
1682 ether_type = ETH_P_8021Q;
1684 ether_type = ETH_P_8021AD;
1685 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1687 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1689 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1691 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
1695 qed_fill_load_req_params(&load_req_params,
1696 p_params->p_drv_load_params);
1697 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1700 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1704 load_code = load_req_params.load_code;
1705 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1706 "Load request was sent. Load code: 0x%x\n",
1709 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1711 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1713 p_hwfn->first_on_engine = (load_code ==
1714 FW_MSG_CODE_DRV_LOAD_ENGINE);
1716 switch (load_code) {
1717 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1718 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1719 p_hwfn->hw_info.hw_mode);
1723 case FW_MSG_CODE_DRV_LOAD_PORT:
1724 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1725 p_hwfn->hw_info.hw_mode);
1730 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1731 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1733 p_hwfn->hw_info.hw_mode,
1734 p_params->b_hw_start,
1736 p_params->allow_npar_tx_switch);
1740 "Unexpected load code [0x%08x]", load_code);
1747 "init phase failed for loadcode 0x%x (rc %d)\n",
1750 /* ACK mfw regardless of success or failure of initialization */
1751 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1752 DRV_MSG_CODE_LOAD_DONE,
1753 0, &load_code, ¶m);
1757 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1761 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1762 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1764 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1766 /* send DCBX attention request command */
1769 "sending phony dcbx set command to trigger DCBx attention handling\n");
1770 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1771 DRV_MSG_CODE_SET_DCBX,
1772 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1773 &load_code, ¶m);
1776 "Failed to send DCBX attention request\n");
1780 p_hwfn->hw_init_done = true;
1784 p_hwfn = QED_LEADING_HWFN(cdev);
1785 drv_mb_param = STORM_FW_VERSION;
1786 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1787 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1788 drv_mb_param, &load_code, ¶m);
1790 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1792 if (!b_default_mtu) {
1793 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1794 p_hwfn->hw_info.mtu);
1797 "Failed to update default mtu\n");
1800 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1802 QED_OV_DRIVER_STATE_DISABLED);
1804 DP_INFO(p_hwfn, "Failed to update driver state\n");
1806 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1807 QED_OV_ESWITCH_VEB);
1809 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1815 #define QED_HW_STOP_RETRY_LIMIT (10)
1816 static void qed_hw_timers_stop(struct qed_dev *cdev,
1817 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1822 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1823 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1825 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1826 if ((!qed_rd(p_hwfn, p_ptt,
1827 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1828 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1831 /* Dependent on number of connection/tasks, possibly
1832 * 1ms sleep is required between polls
1834 usleep_range(1000, 2000);
1837 if (i < QED_HW_STOP_RETRY_LIMIT)
1841 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1842 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1843 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1846 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1850 for_each_hwfn(cdev, j) {
1851 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1852 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1854 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1858 int qed_hw_stop(struct qed_dev *cdev)
1860 struct qed_hwfn *p_hwfn;
1861 struct qed_ptt *p_ptt;
1865 for_each_hwfn(cdev, j) {
1866 p_hwfn = &cdev->hwfns[j];
1867 p_ptt = p_hwfn->p_main_ptt;
1869 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1872 qed_vf_pf_int_cleanup(p_hwfn);
1873 rc = qed_vf_pf_reset(p_hwfn);
1876 "qed_vf_pf_reset failed. rc = %d.\n",
1883 /* mark the hw as uninitialized... */
1884 p_hwfn->hw_init_done = false;
1886 /* Send unload command to MCP */
1887 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1890 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1895 qed_slowpath_irq_sync(p_hwfn);
1897 /* After this point no MFW attentions are expected, e.g. prevent
1898 * race between pf stop and dcbx pf update.
1900 rc = qed_sp_pf_stop(p_hwfn);
1903 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1908 qed_wr(p_hwfn, p_ptt,
1909 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1911 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1912 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1913 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1914 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1915 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1917 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1919 /* Disable Attention Generation */
1920 qed_int_igu_disable_int(p_hwfn, p_ptt);
1922 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1923 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1925 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1927 /* Need to wait 1ms to guarantee SBs are cleared */
1928 usleep_range(1000, 2000);
1930 /* Disable PF in HW blocks */
1931 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1932 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1934 qed_mcp_unload_done(p_hwfn, p_ptt);
1937 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1944 p_hwfn = QED_LEADING_HWFN(cdev);
1945 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1947 /* Disable DMAE in PXP - in CMT, this should only be done for
1948 * first hw-function, and only after all transactions have
1949 * stopped for all active hw-functions.
1951 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1954 "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1962 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1966 for_each_hwfn(cdev, j) {
1967 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1968 struct qed_ptt *p_ptt;
1971 qed_vf_pf_int_cleanup(p_hwfn);
1974 p_ptt = qed_ptt_acquire(p_hwfn);
1979 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1981 qed_wr(p_hwfn, p_ptt,
1982 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1984 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1985 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1986 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1987 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1988 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1990 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1992 /* Need to wait 1ms to guarantee SBs are cleared */
1993 usleep_range(1000, 2000);
1994 qed_ptt_release(p_hwfn, p_ptt);
2000 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
2002 struct qed_ptt *p_ptt;
2004 if (IS_VF(p_hwfn->cdev))
2007 p_ptt = qed_ptt_acquire(p_hwfn);
2011 /* If roce info is allocated it means roce is initialized and should
2012 * be enabled in searcher.
2014 if (p_hwfn->p_rdma_info &&
2015 p_hwfn->b_rdma_enabled_in_prs)
2016 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2018 /* Re-open incoming traffic */
2019 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2020 qed_ptt_release(p_hwfn, p_ptt);
2025 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2026 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2028 qed_ptt_pool_free(p_hwfn);
2029 kfree(p_hwfn->hw_info.p_igu_info);
2030 p_hwfn->hw_info.p_igu_info = NULL;
2033 /* Setup bar access */
2034 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2036 /* clear indirect access */
2037 if (QED_IS_AH(p_hwfn->cdev)) {
2038 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2039 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2040 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2041 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2042 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2043 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2044 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2045 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2047 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2048 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2049 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2050 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2051 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2052 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2053 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2054 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2057 /* Clean Previous errors if such exist */
2058 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2059 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2061 /* enable internal target-read */
2062 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2063 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2066 static void get_function_id(struct qed_hwfn *p_hwfn)
2069 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2070 PXP_PF_ME_OPAQUE_ADDR);
2072 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2074 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2075 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2076 PXP_CONCRETE_FID_PFID);
2077 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2078 PXP_CONCRETE_FID_PORT);
2080 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2081 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2082 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2085 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2087 u32 *feat_num = p_hwfn->hw_info.feat_num;
2088 struct qed_sb_cnt_info sb_cnt;
2091 memset(&sb_cnt, 0, sizeof(sb_cnt));
2092 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2094 if (IS_ENABLED(CONFIG_QED_RDMA) &&
2095 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2096 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2097 * the status blocks equally between L2 / RoCE but with
2098 * consideration as to how many l2 queues / cnqs we have.
2100 feat_num[QED_RDMA_CNQ] =
2101 min_t(u32, sb_cnt.cnt / 2,
2102 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2104 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2106 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2107 /* Start by allocating VF queues, then PF's */
2108 feat_num[QED_VF_L2_QUE] = min_t(u32,
2109 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2111 feat_num[QED_PF_L2_QUE] = min_t(u32,
2112 sb_cnt.cnt - non_l2_sbs,
2119 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2120 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
2124 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2125 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2130 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2131 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2132 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2133 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2134 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2135 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2139 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2156 case QED_RDMA_CNQ_RAM:
2157 return "RDMA_CNQ_RAM";
2164 case QED_RDMA_STATS_QUEUE:
2165 return "RDMA_STATS_QUEUE";
2171 return "UNKNOWN_RESOURCE";
2176 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2177 struct qed_ptt *p_ptt,
2178 enum qed_resources res_id,
2179 u32 resc_max_val, u32 *p_mcp_resp)
2183 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2184 resc_max_val, p_mcp_resp);
2187 "MFW response failure for a max value setting of resource %d [%s]\n",
2188 res_id, qed_hw_get_resc_name(res_id));
2192 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2194 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2195 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2201 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2203 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2204 u32 resc_max_val, mcp_resp;
2208 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2211 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2213 case QED_RDMA_CNQ_RAM:
2214 /* No need for a case for QED_CMDQS_CQS since
2215 * CNQ/CMDQS are the same resource.
2217 resc_max_val = NUM_OF_GLOBAL_QUEUES;
2219 case QED_RDMA_STATS_QUEUE:
2220 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2221 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2224 resc_max_val = BDQ_NUM_RESOURCES;
2230 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2231 resc_max_val, &mcp_resp);
2235 /* There's no point to continue to the next resource if the
2236 * command is not supported by the MFW.
2237 * We do continue if the command is supported but the resource
2238 * is unknown to the MFW. Such a resource will be later
2239 * configured with the default allocation values.
2241 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2249 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2250 enum qed_resources res_id,
2251 u32 *p_resc_num, u32 *p_resc_start)
2253 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2254 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2258 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2259 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2262 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2263 MAX_NUM_VPORTS_BB) / num_funcs;
2266 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2267 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2270 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2271 MAX_QM_TX_QUEUES_BB) / num_funcs;
2272 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
2275 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2279 /* Each VFC resource can accommodate both a MAC and a VLAN */
2280 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2283 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2284 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2287 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2289 case QED_RDMA_CNQ_RAM:
2291 /* CNQ/CMDQS are the same resource */
2292 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2294 case QED_RDMA_STATS_QUEUE:
2295 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2296 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2299 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2300 p_hwfn->hw_info.personality != QED_PCI_FCOE)
2306 /* Since we want its value to reflect whether MFW supports
2307 * the new scheme, have a default of 0.
2319 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2320 *p_resc_start = p_hwfn->port_id;
2321 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2322 *p_resc_start = p_hwfn->port_id;
2323 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2324 *p_resc_start = p_hwfn->port_id + 2;
2327 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2334 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2335 enum qed_resources res_id)
2337 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2338 u32 mcp_resp, *p_resc_num, *p_resc_start;
2341 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2342 p_resc_start = &RESC_START(p_hwfn, res_id);
2344 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2348 "Failed to get default amount for resource %d [%s]\n",
2349 res_id, qed_hw_get_resc_name(res_id));
2353 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2354 &mcp_resp, p_resc_num, p_resc_start);
2357 "MFW response failure for an allocation request for resource %d [%s]\n",
2358 res_id, qed_hw_get_resc_name(res_id));
2362 /* Default driver values are applied in the following cases:
2363 * - The resource allocation MB command is not supported by the MFW
2364 * - There is an internal error in the MFW while processing the request
2365 * - The resource ID is unknown to the MFW
2367 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2369 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2371 qed_hw_get_resc_name(res_id),
2372 mcp_resp, dflt_resc_num, dflt_resc_start);
2373 *p_resc_num = dflt_resc_num;
2374 *p_resc_start = dflt_resc_start;
2379 /* PQs have to divide by 8 [that's the HW granularity].
2380 * Reduce number so it would fit.
2382 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2384 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2386 (*p_resc_num) & ~0x7,
2387 *p_resc_start, (*p_resc_start) & ~0x7);
2388 *p_resc_num &= ~0x7;
2389 *p_resc_start &= ~0x7;
2395 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2400 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2401 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2409 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2411 struct qed_resc_unlock_params resc_unlock_params;
2412 struct qed_resc_lock_params resc_lock_params;
2413 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2417 /* Setting the max values of the soft resources and the following
2418 * resources allocation queries should be atomic. Since several PFs can
2419 * run in parallel - a resource lock is needed.
2420 * If either the resource lock or resource set value commands are not
2421 * supported - skip the the max values setting, release the lock if
2422 * needed, and proceed to the queries. Other failures, including a
2423 * failure to acquire the lock, will cause this function to fail.
2425 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2426 QED_RESC_LOCK_RESC_ALLOC, false);
2428 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2429 if (rc && rc != -EINVAL) {
2431 } else if (rc == -EINVAL) {
2433 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2434 } else if (!rc && !resc_lock_params.b_granted) {
2436 "Failed to acquire the resource lock for the resource allocation commands\n");
2439 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2440 if (rc && rc != -EINVAL) {
2442 "Failed to set the max values of the soft resources\n");
2443 goto unlock_and_exit;
2444 } else if (rc == -EINVAL) {
2446 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2447 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2448 &resc_unlock_params);
2451 "Failed to release the resource lock for the resource allocation commands\n");
2455 rc = qed_hw_set_resc_info(p_hwfn);
2457 goto unlock_and_exit;
2459 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2460 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2463 "Failed to release the resource lock for the resource allocation commands\n");
2466 /* Sanity for ILT */
2467 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2468 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2469 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2470 RESC_START(p_hwfn, QED_ILT),
2471 RESC_END(p_hwfn, QED_ILT) - 1);
2475 /* This will also learn the number of SBs from MFW */
2476 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2479 qed_hw_set_feat(p_hwfn);
2481 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2482 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2483 qed_hw_get_resc_name(res_id),
2484 RESC_NUM(p_hwfn, res_id),
2485 RESC_START(p_hwfn, res_id));
2490 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2491 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2495 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2497 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2498 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2499 struct qed_mcp_link_capabilities *p_caps;
2500 struct qed_mcp_link_params *link;
2502 /* Read global nvm_cfg address */
2503 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2505 /* Verify MCP has initialized it */
2506 if (!nvm_cfg_addr) {
2507 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2511 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2512 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2514 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2515 offsetof(struct nvm_cfg1, glob) +
2516 offsetof(struct nvm_cfg1_glob, core_cfg);
2518 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2520 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2521 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2522 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2523 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2525 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2526 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2528 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2529 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2531 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2532 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2534 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2535 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2537 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2538 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2540 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2541 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2543 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2544 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2546 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2547 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2549 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2550 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2552 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2553 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2556 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2560 /* Read default link configuration */
2561 link = &p_hwfn->mcp_info->link_input;
2562 p_caps = &p_hwfn->mcp_info->link_capabilities;
2563 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2564 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2565 link_temp = qed_rd(p_hwfn, p_ptt,
2567 offsetof(struct nvm_cfg1_port, speed_cap_mask));
2568 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2569 link->speed.advertised_speeds = link_temp;
2571 link_temp = link->speed.advertised_speeds;
2572 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2574 link_temp = qed_rd(p_hwfn, p_ptt,
2576 offsetof(struct nvm_cfg1_port, link_settings));
2577 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2578 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2579 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2580 link->speed.autoneg = true;
2582 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2583 link->speed.forced_speed = 1000;
2585 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2586 link->speed.forced_speed = 10000;
2588 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2589 link->speed.forced_speed = 25000;
2591 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2592 link->speed.forced_speed = 40000;
2594 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2595 link->speed.forced_speed = 50000;
2597 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2598 link->speed.forced_speed = 100000;
2601 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2604 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2605 link->speed.autoneg;
2607 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2608 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2609 link->pause.autoneg = !!(link_temp &
2610 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2611 link->pause.forced_rx = !!(link_temp &
2612 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2613 link->pause.forced_tx = !!(link_temp &
2614 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2615 link->loopback_mode = 0;
2617 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2618 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2619 offsetof(struct nvm_cfg1_port, ext_phy));
2620 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2621 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2622 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2623 link->eee.enable = true;
2624 switch (link_temp) {
2625 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2626 p_caps->default_eee = QED_MCP_EEE_DISABLED;
2627 link->eee.enable = false;
2629 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2630 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2632 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2633 p_caps->eee_lpi_timer =
2634 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2636 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2637 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2641 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2642 link->eee.tx_lpi_enable = link->eee.enable;
2643 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2645 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2650 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2651 link->speed.forced_speed,
2652 link->speed.advertised_speeds,
2653 link->speed.autoneg,
2654 link->pause.autoneg,
2655 p_caps->default_eee, p_caps->eee_lpi_timer);
2657 if (IS_LEAD_HWFN(p_hwfn)) {
2658 struct qed_dev *cdev = p_hwfn->cdev;
2660 /* Read Multi-function information from shmem */
2661 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2662 offsetof(struct nvm_cfg1, glob) +
2663 offsetof(struct nvm_cfg1_glob, generic_cont0);
2665 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2667 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2668 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2671 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2672 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
2674 case NVM_CFG1_GLOB_MF_MODE_UFP:
2675 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2676 BIT(QED_MF_LLH_PROTO_CLSS) |
2677 BIT(QED_MF_UFP_SPECIFIC) |
2678 BIT(QED_MF_8021Q_TAGGING);
2680 case NVM_CFG1_GLOB_MF_MODE_BD:
2681 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2682 BIT(QED_MF_LLH_PROTO_CLSS) |
2683 BIT(QED_MF_8021AD_TAGGING);
2685 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2686 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2687 BIT(QED_MF_LLH_PROTO_CLSS) |
2688 BIT(QED_MF_LL2_NON_UNICAST) |
2689 BIT(QED_MF_INTER_PF_SWITCH);
2691 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2692 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2693 BIT(QED_MF_LLH_PROTO_CLSS) |
2694 BIT(QED_MF_LL2_NON_UNICAST);
2695 if (QED_IS_BB(p_hwfn->cdev))
2696 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
2700 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2704 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2705 p_hwfn->cdev->mf_bits);
2707 /* Read device capabilities information from shmem */
2708 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2709 offsetof(struct nvm_cfg1, glob) +
2710 offsetof(struct nvm_cfg1_glob, device_capabilities);
2712 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2713 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2714 __set_bit(QED_DEV_CAP_ETH,
2715 &p_hwfn->hw_info.device_capabilities);
2716 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2717 __set_bit(QED_DEV_CAP_FCOE,
2718 &p_hwfn->hw_info.device_capabilities);
2719 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2720 __set_bit(QED_DEV_CAP_ISCSI,
2721 &p_hwfn->hw_info.device_capabilities);
2722 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2723 __set_bit(QED_DEV_CAP_ROCE,
2724 &p_hwfn->hw_info.device_capabilities);
2726 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2729 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2731 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2732 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2733 struct qed_dev *cdev = p_hwfn->cdev;
2735 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2737 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2738 * in the other bits are selected.
2739 * Bits 1-15 are for functions 1-15, respectively, and their value is
2740 * '0' only for enabled functions (function 0 always exists and
2742 * In case of CMT, only the "even" functions are enabled, and thus the
2743 * number of functions for both hwfns is learnt from the same bits.
2745 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2747 if (reg_function_hide & 0x1) {
2748 if (QED_IS_BB(cdev)) {
2749 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2761 /* Get the number of the enabled functions on the engine */
2762 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2769 /* Get the PF index within the enabled functions */
2770 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2771 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2779 p_hwfn->num_funcs_on_engine = num_funcs;
2780 p_hwfn->enabled_func_idx = enabled_func_idx;
2784 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2787 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2790 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2791 struct qed_ptt *p_ptt)
2795 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB);
2797 if (port_mode < 3) {
2798 p_hwfn->cdev->num_ports_in_engine = 1;
2799 } else if (port_mode <= 5) {
2800 p_hwfn->cdev->num_ports_in_engine = 2;
2802 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2803 p_hwfn->cdev->num_ports_in_engine);
2805 /* Default num_ports_in_engine to something */
2806 p_hwfn->cdev->num_ports_in_engine = 1;
2810 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2811 struct qed_ptt *p_ptt)
2816 p_hwfn->cdev->num_ports_in_engine = 0;
2818 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2819 port = qed_rd(p_hwfn, p_ptt,
2820 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2822 p_hwfn->cdev->num_ports_in_engine++;
2825 if (!p_hwfn->cdev->num_ports_in_engine) {
2826 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2828 /* Default num_ports_in_engine to something */
2829 p_hwfn->cdev->num_ports_in_engine = 1;
2833 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2835 if (QED_IS_BB(p_hwfn->cdev))
2836 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2838 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2841 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2843 struct qed_mcp_link_capabilities *p_caps;
2846 p_caps = &p_hwfn->mcp_info->link_capabilities;
2847 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2850 p_caps->eee_speed_caps = 0;
2851 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2852 offsetof(struct public_port, eee_status));
2853 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2854 EEE_SUPPORTED_SPEED_OFFSET;
2856 if (eee_status & EEE_1G_SUPPORTED)
2857 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2858 if (eee_status & EEE_10G_ADV)
2859 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2863 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2864 struct qed_ptt *p_ptt,
2865 enum qed_pci_personality personality)
2869 /* Since all information is common, only first hwfns should do this */
2870 if (IS_LEAD_HWFN(p_hwfn)) {
2871 rc = qed_iov_hw_info(p_hwfn);
2876 qed_hw_info_port_num(p_hwfn, p_ptt);
2878 qed_mcp_get_capabilities(p_hwfn, p_ptt);
2880 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2882 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2886 if (qed_mcp_is_init(p_hwfn))
2887 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2888 p_hwfn->mcp_info->func_info.mac);
2890 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2892 if (qed_mcp_is_init(p_hwfn)) {
2893 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2894 p_hwfn->hw_info.ovlan =
2895 p_hwfn->mcp_info->func_info.ovlan;
2897 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2899 qed_get_eee_caps(p_hwfn, p_ptt);
2901 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
2904 if (qed_mcp_is_init(p_hwfn)) {
2905 enum qed_pci_personality protocol;
2907 protocol = p_hwfn->mcp_info->func_info.protocol;
2908 p_hwfn->hw_info.personality = protocol;
2911 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2912 p_hwfn->hw_info.num_active_tc = 1;
2914 qed_get_num_funcs(p_hwfn, p_ptt);
2916 if (qed_mcp_is_init(p_hwfn))
2917 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2919 return qed_hw_get_resc(p_hwfn, p_ptt);
2922 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2924 struct qed_dev *cdev = p_hwfn->cdev;
2928 /* Read Vendor Id / Device Id */
2929 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2930 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2932 /* Determine type */
2933 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2934 switch (device_id_mask) {
2935 case QED_DEV_ID_MASK_BB:
2936 cdev->type = QED_DEV_TYPE_BB;
2938 case QED_DEV_ID_MASK_AH:
2939 cdev->type = QED_DEV_TYPE_AH;
2942 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2946 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2947 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2949 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2951 /* Learn number of HW-functions */
2952 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2954 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2955 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2956 cdev->num_hwfns = 2;
2958 cdev->num_hwfns = 1;
2961 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2962 MISCS_REG_CHIP_TEST_REG) >> 4;
2963 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2964 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2965 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2967 DP_INFO(cdev->hwfns,
2968 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2969 QED_IS_BB(cdev) ? "BB" : "AH",
2970 'A' + cdev->chip_rev,
2971 (int)cdev->chip_metal,
2972 cdev->chip_num, cdev->chip_rev,
2973 cdev->chip_bond_id, cdev->chip_metal);
2978 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
2980 kfree(p_hwfn->nvm_info.image_att);
2981 p_hwfn->nvm_info.image_att = NULL;
2984 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2985 void __iomem *p_regview,
2986 void __iomem *p_doorbells,
2987 enum qed_pci_personality personality)
2991 /* Split PCI bars evenly between hwfns */
2992 p_hwfn->regview = p_regview;
2993 p_hwfn->doorbells = p_doorbells;
2995 if (IS_VF(p_hwfn->cdev))
2996 return qed_vf_hw_prepare(p_hwfn);
2998 /* Validate that chip access is feasible */
2999 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
3001 "Reading the ME register returns all Fs; Preventing further chip access\n");
3005 get_function_id(p_hwfn);
3007 /* Allocate PTT pool */
3008 rc = qed_ptt_pool_alloc(p_hwfn);
3012 /* Allocate the main PTT */
3013 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
3015 /* First hwfn learns basic information, e.g., number of hwfns */
3016 if (!p_hwfn->my_id) {
3017 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
3022 qed_hw_hwfn_prepare(p_hwfn);
3024 /* Initialize MCP structure */
3025 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
3027 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
3031 /* Read the device configuration information from the HW and SHMEM */
3032 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
3034 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
3038 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
3039 * is called as it sets the ports number in an engine.
3041 if (IS_LEAD_HWFN(p_hwfn)) {
3042 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3044 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3047 /* NVRAM info initialization and population */
3048 if (IS_LEAD_HWFN(p_hwfn)) {
3049 rc = qed_mcp_nvm_info_populate(p_hwfn);
3052 "Failed to populate nvm info shadow\n");
3057 /* Allocate the init RT array and initialize the init-ops engine */
3058 rc = qed_init_alloc(p_hwfn);
3064 if (IS_LEAD_HWFN(p_hwfn))
3065 qed_nvm_info_free(p_hwfn);
3067 if (IS_LEAD_HWFN(p_hwfn))
3068 qed_iov_free_hw_info(p_hwfn->cdev);
3069 qed_mcp_free(p_hwfn);
3071 qed_hw_hwfn_free(p_hwfn);
3076 int qed_hw_prepare(struct qed_dev *cdev,
3079 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3082 /* Store the precompiled init data ptrs */
3084 qed_init_iro_array(cdev);
3086 /* Initialize the first hwfn - will learn number of hwfns */
3087 rc = qed_hw_prepare_single(p_hwfn,
3089 cdev->doorbells, personality);
3093 personality = p_hwfn->hw_info.personality;
3095 /* Initialize the rest of the hwfns */
3096 if (cdev->num_hwfns > 1) {
3097 void __iomem *p_regview, *p_doorbell;
3100 /* adjust bar offset for second engine */
3101 addr = cdev->regview +
3102 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3106 addr = cdev->doorbells +
3107 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3111 /* prepare second hw function */
3112 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3113 p_doorbell, personality);
3115 /* in case of error, need to free the previously
3116 * initiliazed hwfn 0.
3120 qed_init_free(p_hwfn);
3121 qed_nvm_info_free(p_hwfn);
3122 qed_mcp_free(p_hwfn);
3123 qed_hw_hwfn_free(p_hwfn);
3131 void qed_hw_remove(struct qed_dev *cdev)
3133 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3137 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3138 QED_OV_DRIVER_STATE_NOT_LOADED);
3140 for_each_hwfn(cdev, i) {
3141 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3144 qed_vf_pf_release(p_hwfn);
3148 qed_init_free(p_hwfn);
3149 qed_hw_hwfn_free(p_hwfn);
3150 qed_mcp_free(p_hwfn);
3153 qed_iov_free_hw_info(cdev);
3155 qed_nvm_info_free(p_hwfn);
3158 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3159 struct qed_chain *p_chain)
3161 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3162 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3163 struct qed_chain_next *p_next;
3169 size = p_chain->elem_size * p_chain->usable_per_page;
3171 for (i = 0; i < p_chain->page_cnt; i++) {
3175 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3176 p_virt_next = p_next->next_virt;
3177 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3179 dma_free_coherent(&cdev->pdev->dev,
3180 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3182 p_virt = p_virt_next;
3183 p_phys = p_phys_next;
3187 static void qed_chain_free_single(struct qed_dev *cdev,
3188 struct qed_chain *p_chain)
3190 if (!p_chain->p_virt_addr)
3193 dma_free_coherent(&cdev->pdev->dev,
3194 QED_CHAIN_PAGE_SIZE,
3195 p_chain->p_virt_addr, p_chain->p_phys_addr);
3198 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3200 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3201 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3202 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3204 if (!pp_virt_addr_tbl)
3210 for (i = 0; i < page_cnt; i++) {
3211 if (!pp_virt_addr_tbl[i])
3214 dma_free_coherent(&cdev->pdev->dev,
3215 QED_CHAIN_PAGE_SIZE,
3216 pp_virt_addr_tbl[i],
3217 *(dma_addr_t *)p_pbl_virt);
3219 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3222 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3224 if (!p_chain->b_external_pbl)
3225 dma_free_coherent(&cdev->pdev->dev,
3227 p_chain->pbl_sp.p_virt_table,
3228 p_chain->pbl_sp.p_phys_table);
3230 vfree(p_chain->pbl.pp_virt_addr_tbl);
3231 p_chain->pbl.pp_virt_addr_tbl = NULL;
3234 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3236 switch (p_chain->mode) {
3237 case QED_CHAIN_MODE_NEXT_PTR:
3238 qed_chain_free_next_ptr(cdev, p_chain);
3240 case QED_CHAIN_MODE_SINGLE:
3241 qed_chain_free_single(cdev, p_chain);
3243 case QED_CHAIN_MODE_PBL:
3244 qed_chain_free_pbl(cdev, p_chain);
3250 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3251 enum qed_chain_cnt_type cnt_type,
3252 size_t elem_size, u32 page_cnt)
3254 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3256 /* The actual chain size can be larger than the maximal possible value
3257 * after rounding up the requested elements number to pages, and after
3258 * taking into acount the unusuable elements (next-ptr elements).
3259 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3260 * size/capacity fields are of a u32 type.
3262 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3263 chain_size > ((u32)U16_MAX + 1)) ||
3264 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3266 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3275 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3277 void *p_virt = NULL, *p_virt_prev = NULL;
3278 dma_addr_t p_phys = 0;
3281 for (i = 0; i < p_chain->page_cnt; i++) {
3282 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3283 QED_CHAIN_PAGE_SIZE,
3284 &p_phys, GFP_KERNEL);
3289 qed_chain_init_mem(p_chain, p_virt, p_phys);
3290 qed_chain_reset(p_chain);
3292 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3296 p_virt_prev = p_virt;
3298 /* Last page's next element should point to the beginning of the
3301 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3302 p_chain->p_virt_addr,
3303 p_chain->p_phys_addr);
3309 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3311 dma_addr_t p_phys = 0;
3312 void *p_virt = NULL;
3314 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3315 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3319 qed_chain_init_mem(p_chain, p_virt, p_phys);
3320 qed_chain_reset(p_chain);
3326 qed_chain_alloc_pbl(struct qed_dev *cdev,
3327 struct qed_chain *p_chain,
3328 struct qed_chain_ext_pbl *ext_pbl)
3330 u32 page_cnt = p_chain->page_cnt, size, i;
3331 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3332 void **pp_virt_addr_tbl = NULL;
3333 u8 *p_pbl_virt = NULL;
3334 void *p_virt = NULL;
3336 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3337 pp_virt_addr_tbl = vzalloc(size);
3338 if (!pp_virt_addr_tbl)
3341 /* The allocation of the PBL table is done with its full size, since it
3342 * is expected to be successive.
3343 * qed_chain_init_pbl_mem() is called even in a case of an allocation
3344 * failure, since pp_virt_addr_tbl was previously allocated, and it
3345 * should be saved to allow its freeing during the error flow.
3347 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3350 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3351 size, &p_pbl_phys, GFP_KERNEL);
3353 p_pbl_virt = ext_pbl->p_pbl_virt;
3354 p_pbl_phys = ext_pbl->p_pbl_phys;
3355 p_chain->b_external_pbl = true;
3358 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3363 for (i = 0; i < page_cnt; i++) {
3364 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3365 QED_CHAIN_PAGE_SIZE,
3366 &p_phys, GFP_KERNEL);
3371 qed_chain_init_mem(p_chain, p_virt, p_phys);
3372 qed_chain_reset(p_chain);
3375 /* Fill the PBL table with the physical address of the page */
3376 *(dma_addr_t *)p_pbl_virt = p_phys;
3377 /* Keep the virtual address of the page */
3378 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3380 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3386 int qed_chain_alloc(struct qed_dev *cdev,
3387 enum qed_chain_use_mode intended_use,
3388 enum qed_chain_mode mode,
3389 enum qed_chain_cnt_type cnt_type,
3392 struct qed_chain *p_chain,
3393 struct qed_chain_ext_pbl *ext_pbl)
3398 if (mode == QED_CHAIN_MODE_SINGLE)
3401 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3403 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3406 "Cannot allocate a chain with the given arguments:\n");
3408 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3409 intended_use, mode, cnt_type, num_elems, elem_size);
3413 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3417 case QED_CHAIN_MODE_NEXT_PTR:
3418 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3420 case QED_CHAIN_MODE_SINGLE:
3421 rc = qed_chain_alloc_single(cdev, p_chain);
3423 case QED_CHAIN_MODE_PBL:
3424 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3433 qed_chain_free(cdev, p_chain);
3437 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3439 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3442 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3443 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3445 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3451 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3456 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3458 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3461 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3462 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3464 "vport id [%d] is not valid, available indices [%d - %d]\n",
3470 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3475 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3477 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3480 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3481 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3483 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3489 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3494 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3497 *p_high = p_filter[1] | (p_filter[0] << 8);
3498 *p_low = p_filter[5] | (p_filter[4] << 8) |
3499 (p_filter[3] << 16) | (p_filter[2] << 24);
3502 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3503 struct qed_ptt *p_ptt, u8 *p_filter)
3505 u32 high = 0, low = 0, en;
3508 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3511 qed_llh_mac_to_filter(&high, &low, p_filter);
3513 /* Find a free entry and utilize it */
3514 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3515 en = qed_rd(p_hwfn, p_ptt,
3516 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3519 qed_wr(p_hwfn, p_ptt,
3520 NIG_REG_LLH_FUNC_FILTER_VALUE +
3521 2 * i * sizeof(u32), low);
3522 qed_wr(p_hwfn, p_ptt,
3523 NIG_REG_LLH_FUNC_FILTER_VALUE +
3524 (2 * i + 1) * sizeof(u32), high);
3525 qed_wr(p_hwfn, p_ptt,
3526 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3527 qed_wr(p_hwfn, p_ptt,
3528 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3529 i * sizeof(u32), 0);
3530 qed_wr(p_hwfn, p_ptt,
3531 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3534 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3536 "Failed to find an empty LLH filter to utilize\n");
3540 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3541 "mac: %pM is added at %d\n",
3547 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3548 struct qed_ptt *p_ptt, u8 *p_filter)
3550 u32 high = 0, low = 0;
3553 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
3556 qed_llh_mac_to_filter(&high, &low, p_filter);
3558 /* Find the entry and clean it */
3559 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3560 if (qed_rd(p_hwfn, p_ptt,
3561 NIG_REG_LLH_FUNC_FILTER_VALUE +
3562 2 * i * sizeof(u32)) != low)
3564 if (qed_rd(p_hwfn, p_ptt,
3565 NIG_REG_LLH_FUNC_FILTER_VALUE +
3566 (2 * i + 1) * sizeof(u32)) != high)
3569 qed_wr(p_hwfn, p_ptt,
3570 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3571 qed_wr(p_hwfn, p_ptt,
3572 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3573 qed_wr(p_hwfn, p_ptt,
3574 NIG_REG_LLH_FUNC_FILTER_VALUE +
3575 (2 * i + 1) * sizeof(u32), 0);
3577 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3578 "mac: %pM is removed from %d\n",
3582 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3583 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3587 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3588 struct qed_ptt *p_ptt,
3589 u16 source_port_or_eth_type,
3590 u16 dest_port, enum qed_llh_port_filter_type_t type)
3592 u32 high = 0, low = 0, en;
3595 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3599 case QED_LLH_FILTER_ETHERTYPE:
3600 high = source_port_or_eth_type;
3602 case QED_LLH_FILTER_TCP_SRC_PORT:
3603 case QED_LLH_FILTER_UDP_SRC_PORT:
3604 low = source_port_or_eth_type << 16;
3606 case QED_LLH_FILTER_TCP_DEST_PORT:
3607 case QED_LLH_FILTER_UDP_DEST_PORT:
3610 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3611 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3612 low = (source_port_or_eth_type << 16) | dest_port;
3616 "Non valid LLH protocol filter type %d\n", type);
3619 /* Find a free entry and utilize it */
3620 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3621 en = qed_rd(p_hwfn, p_ptt,
3622 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3625 qed_wr(p_hwfn, p_ptt,
3626 NIG_REG_LLH_FUNC_FILTER_VALUE +
3627 2 * i * sizeof(u32), low);
3628 qed_wr(p_hwfn, p_ptt,
3629 NIG_REG_LLH_FUNC_FILTER_VALUE +
3630 (2 * i + 1) * sizeof(u32), high);
3631 qed_wr(p_hwfn, p_ptt,
3632 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3633 qed_wr(p_hwfn, p_ptt,
3634 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3635 i * sizeof(u32), 1 << type);
3636 qed_wr(p_hwfn, p_ptt,
3637 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3640 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3642 "Failed to find an empty LLH filter to utilize\n");
3646 case QED_LLH_FILTER_ETHERTYPE:
3647 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3648 "ETH type %x is added at %d\n",
3649 source_port_or_eth_type, i);
3651 case QED_LLH_FILTER_TCP_SRC_PORT:
3652 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3653 "TCP src port %x is added at %d\n",
3654 source_port_or_eth_type, i);
3656 case QED_LLH_FILTER_UDP_SRC_PORT:
3657 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3658 "UDP src port %x is added at %d\n",
3659 source_port_or_eth_type, i);
3661 case QED_LLH_FILTER_TCP_DEST_PORT:
3662 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3663 "TCP dst port %x is added at %d\n", dest_port, i);
3665 case QED_LLH_FILTER_UDP_DEST_PORT:
3666 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3667 "UDP dst port %x is added at %d\n", dest_port, i);
3669 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3670 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3671 "TCP src/dst ports %x/%x are added at %d\n",
3672 source_port_or_eth_type, dest_port, i);
3674 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3675 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3676 "UDP src/dst ports %x/%x are added at %d\n",
3677 source_port_or_eth_type, dest_port, i);
3684 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3685 struct qed_ptt *p_ptt,
3686 u16 source_port_or_eth_type,
3688 enum qed_llh_port_filter_type_t type)
3690 u32 high = 0, low = 0;
3693 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
3697 case QED_LLH_FILTER_ETHERTYPE:
3698 high = source_port_or_eth_type;
3700 case QED_LLH_FILTER_TCP_SRC_PORT:
3701 case QED_LLH_FILTER_UDP_SRC_PORT:
3702 low = source_port_or_eth_type << 16;
3704 case QED_LLH_FILTER_TCP_DEST_PORT:
3705 case QED_LLH_FILTER_UDP_DEST_PORT:
3708 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3709 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3710 low = (source_port_or_eth_type << 16) | dest_port;
3714 "Non valid LLH protocol filter type %d\n", type);
3718 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3719 if (!qed_rd(p_hwfn, p_ptt,
3720 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3722 if (!qed_rd(p_hwfn, p_ptt,
3723 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3725 if (!(qed_rd(p_hwfn, p_ptt,
3726 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3727 i * sizeof(u32)) & BIT(type)))
3729 if (qed_rd(p_hwfn, p_ptt,
3730 NIG_REG_LLH_FUNC_FILTER_VALUE +
3731 2 * i * sizeof(u32)) != low)
3733 if (qed_rd(p_hwfn, p_ptt,
3734 NIG_REG_LLH_FUNC_FILTER_VALUE +
3735 (2 * i + 1) * sizeof(u32)) != high)
3738 qed_wr(p_hwfn, p_ptt,
3739 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3740 qed_wr(p_hwfn, p_ptt,
3741 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3742 qed_wr(p_hwfn, p_ptt,
3743 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3744 i * sizeof(u32), 0);
3745 qed_wr(p_hwfn, p_ptt,
3746 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3747 qed_wr(p_hwfn, p_ptt,
3748 NIG_REG_LLH_FUNC_FILTER_VALUE +
3749 (2 * i + 1) * sizeof(u32), 0);
3753 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3754 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3757 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3758 u32 hw_addr, void *p_eth_qzone,
3759 size_t eth_qzone_size, u8 timeset)
3761 struct coalescing_timeset *p_coal_timeset;
3763 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3764 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3768 p_coal_timeset = p_eth_qzone;
3769 memset(p_eth_qzone, 0, eth_qzone_size);
3770 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3771 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3772 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3777 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3779 struct qed_queue_cid *p_cid = p_handle;
3780 struct qed_hwfn *p_hwfn;
3781 struct qed_ptt *p_ptt;
3784 p_hwfn = p_cid->p_owner;
3786 if (IS_VF(p_hwfn->cdev))
3787 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3789 p_ptt = qed_ptt_acquire(p_hwfn);
3794 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3797 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3801 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3804 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3807 qed_ptt_release(p_hwfn, p_ptt);
3811 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3812 struct qed_ptt *p_ptt,
3813 u16 coalesce, struct qed_queue_cid *p_cid)
3815 struct ustorm_eth_queue_zone eth_qzone;
3816 u8 timeset, timer_res;
3820 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3821 if (coalesce <= 0x7F) {
3823 } else if (coalesce <= 0xFF) {
3825 } else if (coalesce <= 0x1FF) {
3828 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3831 timeset = (u8)(coalesce >> timer_res);
3833 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3834 p_cid->sb_igu_id, false);
3838 address = BAR0_MAP_REG_USDM_RAM +
3839 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3841 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3842 sizeof(struct ustorm_eth_queue_zone), timeset);
3850 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3851 struct qed_ptt *p_ptt,
3852 u16 coalesce, struct qed_queue_cid *p_cid)
3854 struct xstorm_eth_queue_zone eth_qzone;
3855 u8 timeset, timer_res;
3859 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3860 if (coalesce <= 0x7F) {
3862 } else if (coalesce <= 0xFF) {
3864 } else if (coalesce <= 0x1FF) {
3867 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3870 timeset = (u8)(coalesce >> timer_res);
3872 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3873 p_cid->sb_igu_id, true);
3877 address = BAR0_MAP_REG_XSDM_RAM +
3878 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3880 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
3881 sizeof(struct xstorm_eth_queue_zone), timeset);
3886 /* Calculate final WFQ values for all vports and configure them.
3887 * After this configuration each vport will have
3888 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3890 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3891 struct qed_ptt *p_ptt,
3894 struct init_qm_vport_params *vport_params;
3897 vport_params = p_hwfn->qm_info.qm_vport_params;
3899 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3900 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3902 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3904 qed_init_vport_wfq(p_hwfn, p_ptt,
3905 vport_params[i].first_tx_pq_id,
3906 vport_params[i].vport_wfq);
3910 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3916 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3917 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3920 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3921 struct qed_ptt *p_ptt,
3924 struct init_qm_vport_params *vport_params;
3927 vport_params = p_hwfn->qm_info.qm_vport_params;
3929 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3930 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3931 qed_init_vport_wfq(p_hwfn, p_ptt,
3932 vport_params[i].first_tx_pq_id,
3933 vport_params[i].vport_wfq);
3937 /* This function performs several validations for WFQ
3938 * configuration and required min rate for a given vport
3939 * 1. req_rate must be greater than one percent of min_pf_rate.
3940 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3941 * rates to get less than one percent of min_pf_rate.
3942 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3944 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3945 u16 vport_id, u32 req_rate, u32 min_pf_rate)
3947 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3948 int non_requested_count = 0, req_count = 0, i, num_vports;
3950 num_vports = p_hwfn->qm_info.num_vports;
3952 /* Accounting for the vports which are configured for WFQ explicitly */
3953 for (i = 0; i < num_vports; i++) {
3956 if ((i != vport_id) &&
3957 p_hwfn->qm_info.wfq_data[i].configured) {
3959 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3960 total_req_min_rate += tmp_speed;
3964 /* Include current vport data as well */
3966 total_req_min_rate += req_rate;
3967 non_requested_count = num_vports - req_count;
3969 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3970 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3971 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3972 vport_id, req_rate, min_pf_rate);
3976 if (num_vports > QED_WFQ_UNIT) {
3977 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3978 "Number of vports is greater than %d\n",
3983 if (total_req_min_rate > min_pf_rate) {
3984 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3985 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3986 total_req_min_rate, min_pf_rate);
3990 total_left_rate = min_pf_rate - total_req_min_rate;
3992 left_rate_per_vp = total_left_rate / non_requested_count;
3993 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
3994 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3995 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3996 left_rate_per_vp, min_pf_rate);
4000 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
4001 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
4003 for (i = 0; i < num_vports; i++) {
4004 if (p_hwfn->qm_info.wfq_data[i].configured)
4007 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
4013 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
4014 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
4016 struct qed_mcp_link_state *p_link;
4019 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
4021 if (!p_link->min_pf_rate) {
4022 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
4023 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
4027 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
4030 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
4031 p_link->min_pf_rate);
4034 "Validation failed while configuring min rate\n");
4039 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
4040 struct qed_ptt *p_ptt,
4043 bool use_wfq = false;
4047 /* Validate all pre configured vports for wfq */
4048 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4051 if (!p_hwfn->qm_info.wfq_data[i].configured)
4054 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4057 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4060 "WFQ validation failed while configuring min rate\n");
4066 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4068 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4073 /* Main API for qed clients to configure vport min rate.
4074 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4075 * rate - Speed in Mbps needs to be assigned to a given vport.
4077 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4079 int i, rc = -EINVAL;
4081 /* Currently not supported; Might change in future */
4082 if (cdev->num_hwfns > 1) {
4084 "WFQ configuration is not supported for this device\n");
4088 for_each_hwfn(cdev, i) {
4089 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4090 struct qed_ptt *p_ptt;
4092 p_ptt = qed_ptt_acquire(p_hwfn);
4096 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4099 qed_ptt_release(p_hwfn, p_ptt);
4103 qed_ptt_release(p_hwfn, p_ptt);
4109 /* API to configure WFQ from mcp link change */
4110 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4111 struct qed_ptt *p_ptt, u32 min_pf_rate)
4115 if (cdev->num_hwfns > 1) {
4118 "WFQ configuration is not supported for this device\n");
4122 for_each_hwfn(cdev, i) {
4123 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4125 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4130 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4131 struct qed_ptt *p_ptt,
4132 struct qed_mcp_link_state *p_link,
4137 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4139 if (!p_link->line_speed && (max_bw != 100))
4142 p_link->speed = (p_link->line_speed * max_bw) / 100;
4143 p_hwfn->qm_info.pf_rl = p_link->speed;
4145 /* Since the limiter also affects Tx-switched traffic, we don't want it
4146 * to limit such traffic in case there's no actual limit.
4147 * In that case, set limit to imaginary high boundary.
4150 p_hwfn->qm_info.pf_rl = 100000;
4152 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4153 p_hwfn->qm_info.pf_rl);
4155 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4156 "Configured MAX bandwidth to be %08x Mb/sec\n",
4162 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4163 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4165 int i, rc = -EINVAL;
4167 if (max_bw < 1 || max_bw > 100) {
4168 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4172 for_each_hwfn(cdev, i) {
4173 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4174 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4175 struct qed_mcp_link_state *p_link;
4176 struct qed_ptt *p_ptt;
4178 p_link = &p_lead->mcp_info->link_output;
4180 p_ptt = qed_ptt_acquire(p_hwfn);
4184 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4187 qed_ptt_release(p_hwfn, p_ptt);
4196 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4197 struct qed_ptt *p_ptt,
4198 struct qed_mcp_link_state *p_link,
4203 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4204 p_hwfn->qm_info.pf_wfq = min_bw;
4206 if (!p_link->line_speed)
4209 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4211 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4213 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4214 "Configured MIN bandwidth to be %d Mb/sec\n",
4215 p_link->min_pf_rate);
4220 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4221 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4223 int i, rc = -EINVAL;
4225 if (min_bw < 1 || min_bw > 100) {
4226 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4230 for_each_hwfn(cdev, i) {
4231 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4232 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4233 struct qed_mcp_link_state *p_link;
4234 struct qed_ptt *p_ptt;
4236 p_link = &p_lead->mcp_info->link_output;
4238 p_ptt = qed_ptt_acquire(p_hwfn);
4242 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4245 qed_ptt_release(p_hwfn, p_ptt);
4249 if (p_link->min_pf_rate) {
4250 u32 min_rate = p_link->min_pf_rate;
4252 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4257 qed_ptt_release(p_hwfn, p_ptt);
4263 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4265 struct qed_mcp_link_state *p_link;
4267 p_link = &p_hwfn->mcp_info->link_output;
4269 if (p_link->min_pf_rate)
4270 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4271 p_link->min_pf_rate);
4273 memset(p_hwfn->qm_info.wfq_data, 0,
4274 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4277 int qed_device_num_engines(struct qed_dev *cdev)
4279 return QED_IS_BB(cdev) ? 2 : 1;
4282 static int qed_device_num_ports(struct qed_dev *cdev)
4284 /* in CMT always only one port */
4285 if (cdev->num_hwfns > 1)
4288 return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4291 int qed_device_get_port_id(struct qed_dev *cdev)
4293 return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4296 void qed_set_fw_mac_addr(__le16 *fw_msb,
4297 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4299 ((u8 *)fw_msb)[0] = mac[1];
4300 ((u8 *)fw_msb)[1] = mac[0];
4301 ((u8 *)fw_mid)[0] = mac[3];
4302 ((u8 *)fw_mid)[1] = mac[2];
4303 ((u8 *)fw_lsb)[0] = mac[5];
4304 ((u8 *)fw_lsb)[1] = mac[4];