1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
38 #include <linux/bitops.h>
39 #include <linux/delay.h>
40 #include <linux/kernel.h>
41 #include <linux/list.h>
42 #include <linux/slab.h>
43 #include <linux/qed/common_hsi.h>
44 #include <linux/qed/storage_common.h>
45 #include <linux/qed/tcp_common.h>
46 #include <linux/qed/fcoe_common.h>
47 #include <linux/qed/eth_common.h>
48 #include <linux/qed/iscsi_common.h>
49 #include <linux/qed/iwarp_common.h>
50 #include <linux/qed/rdma_common.h>
51 #include <linux/qed/roce_common.h>
52 #include <linux/qed/qed_fcoe_if.h>
57 /* Opcodes for the event ring */
58 enum common_event_opcode {
59 COMMON_EVENT_PF_START,
61 COMMON_EVENT_VF_START,
63 COMMON_EVENT_VF_PF_CHANNEL,
65 COMMON_EVENT_PF_UPDATE,
66 COMMON_EVENT_MALICIOUS_VF,
67 COMMON_EVENT_RL_UPDATE,
69 MAX_COMMON_EVENT_OPCODE
72 /* Common Ramrod Command IDs */
73 enum common_ramrod_cmd_id {
75 COMMON_RAMROD_PF_START,
76 COMMON_RAMROD_PF_STOP,
77 COMMON_RAMROD_VF_START,
78 COMMON_RAMROD_VF_STOP,
79 COMMON_RAMROD_PF_UPDATE,
80 COMMON_RAMROD_RL_UPDATE,
82 MAX_COMMON_RAMROD_CMD_ID
85 /* How ll2 should deal with packet upon errors */
86 enum core_error_handle {
93 /* Opcodes for the event ring */
94 enum core_event_opcode {
95 CORE_EVENT_TX_QUEUE_START,
96 CORE_EVENT_TX_QUEUE_STOP,
97 CORE_EVENT_RX_QUEUE_START,
98 CORE_EVENT_RX_QUEUE_STOP,
99 CORE_EVENT_RX_QUEUE_FLUSH,
100 CORE_EVENT_TX_QUEUE_UPDATE,
101 CORE_EVENT_QUEUE_STATS_QUERY,
102 MAX_CORE_EVENT_OPCODE
105 /* The L4 pseudo checksum mode for Core */
106 enum core_l4_pseudo_checksum_mode {
107 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
108 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
109 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
112 /* Light-L2 RX Producers in Tstorm RAM */
113 struct core_ll2_port_stats {
114 struct regpair gsi_invalid_hdr;
115 struct regpair gsi_invalid_pkt_length;
116 struct regpair gsi_unsupported_pkt_typ;
117 struct regpair gsi_crcchksm_error;
120 /* LL2 TX Per Queue Stats */
121 struct core_ll2_pstorm_per_queue_stat {
122 struct regpair sent_ucast_bytes;
123 struct regpair sent_mcast_bytes;
124 struct regpair sent_bcast_bytes;
125 struct regpair sent_ucast_pkts;
126 struct regpair sent_mcast_pkts;
127 struct regpair sent_bcast_pkts;
128 struct regpair error_drop_pkts;
131 /* Light-L2 RX Producers in Tstorm RAM */
132 struct core_ll2_rx_prod {
137 struct core_ll2_tstorm_per_queue_stat {
138 struct regpair packet_too_big_discard;
139 struct regpair no_buff_discard;
142 struct core_ll2_ustorm_per_queue_stat {
143 struct regpair rcv_ucast_bytes;
144 struct regpair rcv_mcast_bytes;
145 struct regpair rcv_bcast_bytes;
146 struct regpair rcv_ucast_pkts;
147 struct regpair rcv_mcast_pkts;
148 struct regpair rcv_bcast_pkts;
151 /* Structure for doorbell data, in PWM mode, for RX producers update. */
152 struct core_pwm_prod_update_data {
153 __le16 icid; /* internal CID */
156 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
157 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
158 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
159 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
160 struct core_ll2_rx_prod prod; /* Producers */
163 /* Core Ramrod Command IDs (light L2) */
164 enum core_ramrod_cmd_id {
166 CORE_RAMROD_RX_QUEUE_START,
167 CORE_RAMROD_TX_QUEUE_START,
168 CORE_RAMROD_RX_QUEUE_STOP,
169 CORE_RAMROD_TX_QUEUE_STOP,
170 CORE_RAMROD_RX_QUEUE_FLUSH,
171 CORE_RAMROD_TX_QUEUE_UPDATE,
172 CORE_RAMROD_QUEUE_STATS_QUERY,
173 MAX_CORE_RAMROD_CMD_ID
176 /* Core RX CQE Type for Light L2 */
177 enum core_roce_flavor_type {
180 MAX_CORE_ROCE_FLAVOR_TYPE
183 /* Specifies how ll2 should deal with packets errors: packet_too_big and
186 struct core_rx_action_on_error {
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
191 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
193 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
196 /* Core RX BD for Light L2 */
202 /* Core RX CM offload BD for Light L2 */
203 struct core_rx_bd_with_buff_len {
209 /* Core RX CM offload BD for Light L2 */
210 union core_rx_bd_union {
211 struct core_rx_bd rx_bd;
212 struct core_rx_bd_with_buff_len rx_bd_with_len;
215 /* Opaque Data for Light L2 RX CQE */
216 struct core_rx_cqe_opaque_data {
220 /* Core RX CQE Type for Light L2 */
221 enum core_rx_cqe_type {
222 CORE_RX_CQE_ILLEGAL_TYPE,
223 CORE_RX_CQE_TYPE_REGULAR,
224 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
225 CORE_RX_CQE_TYPE_SLOW_PATH,
229 /* Core RX CQE for Light L2 */
230 struct core_rx_fast_path_cqe {
233 struct parsing_and_err_flags parse_flags;
234 __le16 packet_length;
236 struct core_rx_cqe_opaque_data opaque_data;
237 struct parsing_err_flags err_flags;
242 /* Core Rx CM offload CQE */
243 struct core_rx_gsi_offload_cqe {
245 u8 data_length_error;
246 struct parsing_and_err_flags parse_flags;
249 __le32 src_mac_addrhi;
250 __le16 src_mac_addrlo;
253 struct core_rx_cqe_opaque_data opaque_data;
257 /* Core RX CQE for Light L2 */
258 struct core_rx_slow_path_cqe {
262 struct core_rx_cqe_opaque_data opaque_data;
266 /* Core RX CM offload BD for Light L2 */
267 union core_rx_cqe_union {
268 struct core_rx_fast_path_cqe rx_cqe_fp;
269 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
270 struct core_rx_slow_path_cqe rx_cqe_sp;
273 /* Ramrod data for rx queue start ramrod */
274 struct core_rx_start_ramrod_data {
275 struct regpair bd_base;
276 struct regpair cqe_pbl_addr;
281 u8 complete_event_flg;
283 __le16 num_of_pbl_pages;
284 u8 inner_vlan_stripping_en;
285 u8 report_outer_vlan;
288 u8 mf_si_bcast_accept_all;
289 u8 mf_si_mcast_accept_all;
290 struct core_rx_action_on_error action_on_error;
295 u8 wipe_inner_vlan_pri_en;
299 /* Ramrod data for rx queue stop ramrod */
300 struct core_rx_stop_ramrod_data {
302 u8 complete_event_flg;
308 /* Flags for Core TX BD */
309 struct core_tx_bd_data {
311 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
312 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
313 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
314 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
315 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
316 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
317 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
318 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
319 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
320 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
321 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
322 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
323 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
324 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
325 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
326 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
327 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
328 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
329 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
330 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
331 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
332 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
333 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
334 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
335 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
336 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
339 /* Core TX BD for Light L2 */
343 __le16 nw_vlan_or_lb_echo;
344 struct core_tx_bd_data bd_data;
346 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
347 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
348 #define CORE_TX_BD_TX_DST_MASK 0x3
349 #define CORE_TX_BD_TX_DST_SHIFT 14
352 /* Light L2 TX Destination */
356 CORE_TX_DEST_RESERVED,
361 /* Ramrod data for tx queue start ramrod */
362 struct core_tx_start_ramrod_data {
363 struct regpair pbl_base_addr;
376 u8 enforce_security_flag;
380 /* Ramrod data for tx queue stop ramrod */
381 struct core_tx_stop_ramrod_data {
385 /* Ramrod data for tx queue update ramrod */
386 struct core_tx_update_ramrod_data {
387 u8 update_qm_pq_id_flg;
393 /* Enum flag for what type of dcb data to update */
394 enum dcb_dscp_update_mode {
395 DONT_UPDATE_DCB_DSCP,
399 MAX_DCB_DSCP_UPDATE_MODE
402 /* The core storm context for the Ystorm */
403 struct ystorm_core_conn_st_ctx {
407 /* The core storm context for the Pstorm */
408 struct pstorm_core_conn_st_ctx {
412 /* Core Slowpath Connection storm context of Xstorm */
413 struct xstorm_core_conn_st_ctx {
416 struct regpair consolid_base_addr;
418 __le16 consolid_cons;
419 __le32 reserved0[55];
422 struct e4_xstorm_core_conn_ag_ctx {
426 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
427 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
428 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
429 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
430 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
431 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
432 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
433 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
434 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
435 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
436 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
437 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
438 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
439 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
440 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
441 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
443 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
444 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
445 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
446 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
447 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
448 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
449 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
450 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
451 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
452 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
453 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
454 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
455 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
456 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
457 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
458 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
460 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
463 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
465 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
469 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
470 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
471 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
472 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
473 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
474 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
475 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
476 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
478 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
479 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
480 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
481 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
482 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
483 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
484 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
485 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
487 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
488 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
489 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
492 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
494 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
496 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
497 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
500 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
501 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
502 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
503 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
505 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
506 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
507 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
508 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
509 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
510 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
511 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
519 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
520 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
522 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
523 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
524 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
525 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
526 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
527 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
528 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
529 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
530 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
531 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
533 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
534 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
535 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
536 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
537 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
538 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
539 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
540 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
541 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
542 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
543 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
544 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
545 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
546 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
547 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
548 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
550 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
551 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
552 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
553 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
554 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
555 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
556 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
557 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
558 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
559 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
560 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
561 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
562 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
563 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
564 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
565 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
567 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
568 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
569 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
570 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
571 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
572 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
574 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
577 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
579 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
580 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
581 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
582 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
584 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
585 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
586 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
587 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
591 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
592 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
593 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
594 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
595 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
596 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
597 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
598 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
599 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
601 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
602 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
603 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
604 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
605 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
606 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
607 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
608 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
609 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
610 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
611 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
612 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
613 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
614 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
615 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
616 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
618 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
619 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
620 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
621 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
622 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
623 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
624 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
625 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
626 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
627 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
628 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
629 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
630 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
631 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
634 __le16 consolid_prod;
637 __le16 tx_bd_or_spq_prod;
638 __le16 updated_qm_pq_id;
685 struct e4_tstorm_core_conn_ag_ctx {
689 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
690 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
691 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
692 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
693 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
694 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
695 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
696 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
697 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
698 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
699 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
700 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
708 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
711 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
713 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
723 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
724 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
725 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
726 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
727 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
728 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
729 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
730 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
731 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
732 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
733 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
735 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
736 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
737 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
738 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
739 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
740 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
741 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
742 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
743 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
744 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
745 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
746 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
747 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
748 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
749 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
750 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
752 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
753 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
754 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
755 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
756 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
757 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
758 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
759 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
760 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
761 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
762 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
763 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
764 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
765 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
766 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
767 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
789 struct e4_ustorm_core_conn_ag_ctx {
793 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
794 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
795 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
796 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
797 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
798 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
799 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
800 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
801 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
802 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
804 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
805 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
806 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
807 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
808 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
809 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
810 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
811 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
813 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
814 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
815 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
816 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
817 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
818 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
819 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
820 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
821 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
822 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
823 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
824 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
825 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
826 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
827 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
828 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
830 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
831 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
832 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
833 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
834 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
835 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
836 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
837 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
838 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
839 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
840 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
841 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
842 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
843 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
844 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
845 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
858 /* The core storm context for the Mstorm */
859 struct mstorm_core_conn_st_ctx {
863 /* The core storm context for the Ustorm */
864 struct ustorm_core_conn_st_ctx {
868 /* The core storm context for the Tstorm */
869 struct tstorm_core_conn_st_ctx {
873 /* core connection context */
874 struct e4_core_conn_context {
875 struct ystorm_core_conn_st_ctx ystorm_st_context;
876 struct regpair ystorm_st_padding[2];
877 struct pstorm_core_conn_st_ctx pstorm_st_context;
878 struct regpair pstorm_st_padding[2];
879 struct xstorm_core_conn_st_ctx xstorm_st_context;
880 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
881 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
882 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
883 struct mstorm_core_conn_st_ctx mstorm_st_context;
884 struct ustorm_core_conn_st_ctx ustorm_st_context;
885 struct regpair ustorm_st_padding[2];
886 struct tstorm_core_conn_st_ctx tstorm_st_context;
887 struct regpair tstorm_st_padding[2];
890 struct eth_mstorm_per_pf_stat {
891 struct regpair gre_discard_pkts;
892 struct regpair vxlan_discard_pkts;
893 struct regpair geneve_discard_pkts;
894 struct regpair lb_discard_pkts;
897 struct eth_mstorm_per_queue_stat {
898 struct regpair ttl0_discard;
899 struct regpair packet_too_big_discard;
900 struct regpair no_buff_discard;
901 struct regpair not_active_discard;
902 struct regpair tpa_coalesced_pkts;
903 struct regpair tpa_coalesced_events;
904 struct regpair tpa_aborts_num;
905 struct regpair tpa_coalesced_bytes;
908 /* Ethernet TX Per PF */
909 struct eth_pstorm_per_pf_stat {
910 struct regpair sent_lb_ucast_bytes;
911 struct regpair sent_lb_mcast_bytes;
912 struct regpair sent_lb_bcast_bytes;
913 struct regpair sent_lb_ucast_pkts;
914 struct regpair sent_lb_mcast_pkts;
915 struct regpair sent_lb_bcast_pkts;
916 struct regpair sent_gre_bytes;
917 struct regpair sent_vxlan_bytes;
918 struct regpair sent_geneve_bytes;
919 struct regpair sent_mpls_bytes;
920 struct regpair sent_gre_mpls_bytes;
921 struct regpair sent_udp_mpls_bytes;
922 struct regpair sent_gre_pkts;
923 struct regpair sent_vxlan_pkts;
924 struct regpair sent_geneve_pkts;
925 struct regpair sent_mpls_pkts;
926 struct regpair sent_gre_mpls_pkts;
927 struct regpair sent_udp_mpls_pkts;
928 struct regpair gre_drop_pkts;
929 struct regpair vxlan_drop_pkts;
930 struct regpair geneve_drop_pkts;
931 struct regpair mpls_drop_pkts;
932 struct regpair gre_mpls_drop_pkts;
933 struct regpair udp_mpls_drop_pkts;
936 /* Ethernet TX Per Queue Stats */
937 struct eth_pstorm_per_queue_stat {
938 struct regpair sent_ucast_bytes;
939 struct regpair sent_mcast_bytes;
940 struct regpair sent_bcast_bytes;
941 struct regpair sent_ucast_pkts;
942 struct regpair sent_mcast_pkts;
943 struct regpair sent_bcast_pkts;
944 struct regpair error_drop_pkts;
947 /* ETH Rx producers data */
948 struct eth_rx_rate_limit {
956 /* Update RSS indirection table entry command */
957 struct eth_tstorm_rss_update_data {
962 __le16 ind_table_value;
966 struct eth_ustorm_per_pf_stat {
967 struct regpair rcv_lb_ucast_bytes;
968 struct regpair rcv_lb_mcast_bytes;
969 struct regpair rcv_lb_bcast_bytes;
970 struct regpair rcv_lb_ucast_pkts;
971 struct regpair rcv_lb_mcast_pkts;
972 struct regpair rcv_lb_bcast_pkts;
973 struct regpair rcv_gre_bytes;
974 struct regpair rcv_vxlan_bytes;
975 struct regpair rcv_geneve_bytes;
976 struct regpair rcv_gre_pkts;
977 struct regpair rcv_vxlan_pkts;
978 struct regpair rcv_geneve_pkts;
981 struct eth_ustorm_per_queue_stat {
982 struct regpair rcv_ucast_bytes;
983 struct regpair rcv_mcast_bytes;
984 struct regpair rcv_bcast_bytes;
985 struct regpair rcv_ucast_pkts;
986 struct regpair rcv_mcast_pkts;
987 struct regpair rcv_bcast_pkts;
990 /* Event Ring VF-PF Channel data */
991 struct vf_pf_channel_eqe_data {
992 struct regpair msg_addr;
995 /* Event Ring malicious VF data */
996 struct malicious_vf_eqe_data {
1002 /* Event Ring initial cleanup data */
1003 struct initial_cleanup_eqe_data {
1008 /* Event Data Union */
1009 union event_ring_data {
1011 struct vf_pf_channel_eqe_data vf_pf_channel;
1012 struct iscsi_eqe_data iscsi_info;
1013 struct iscsi_connect_done_results iscsi_conn_done_info;
1014 union rdma_eqe_data rdma_data;
1015 struct malicious_vf_eqe_data malicious_vf;
1016 struct initial_cleanup_eqe_data vf_init_cleanup;
1019 /* Event Ring Entry */
1020 struct event_ring_entry {
1028 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1029 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1030 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1031 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
1032 union event_ring_data data;
1035 /* Event Ring Next Page Address */
1036 struct event_ring_next_addr {
1037 struct regpair addr;
1041 /* Event Ring Element */
1042 union event_ring_element {
1043 struct event_ring_entry entry;
1044 struct event_ring_next_addr next_addr;
1048 enum fw_flow_ctrl_mode {
1051 MAX_FW_FLOW_CTRL_MODE
1054 /* GFT profile type */
1055 enum gft_profile_type {
1056 GFT_PROFILE_TYPE_4_TUPLE,
1057 GFT_PROFILE_TYPE_L4_DST_PORT,
1058 GFT_PROFILE_TYPE_IP_DST_ADDR,
1059 GFT_PROFILE_TYPE_IP_SRC_ADDR,
1060 GFT_PROFILE_TYPE_TUNNEL_TYPE,
1061 MAX_GFT_PROFILE_TYPE
1064 /* Major and Minor hsi Versions */
1065 struct hsi_fp_ver_struct {
1066 u8 minor_ver_arr[2];
1067 u8 major_ver_arr[2];
1070 enum iwarp_ll2_tx_queues {
1071 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1072 IWARP_LL2_ALIGNED_TX_QUEUE,
1073 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1075 MAX_IWARP_LL2_TX_QUEUES
1078 /* Malicious VF error ID */
1079 enum malicious_vf_error_id {
1080 MALICIOUS_VF_NO_ERROR,
1081 VF_PF_CHANNEL_NOT_READY,
1082 VF_ZONE_MSG_NOT_VALID,
1083 VF_ZONE_FUNC_NOT_ENABLED,
1084 ETH_PACKET_TOO_SMALL,
1085 ETH_ILLEGAL_VLAN_MODE,
1087 ETH_ILLEGAL_INBAND_TAGS,
1088 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1090 ETH_FIRST_BD_WO_SOP,
1091 ETH_INSUFFICIENT_BDS,
1092 ETH_ILLEGAL_LSO_HDR_NBDS,
1093 ETH_ILLEGAL_LSO_MSS,
1095 ETH_ILLEGAL_LSO_HDR_LEN,
1096 ETH_INSUFFICIENT_PAYLOAD,
1097 ETH_EDPM_OUT_OF_SYNC,
1098 ETH_TUNN_IPV6_EXT_NBD_ERR,
1099 ETH_CONTROL_PACKET_VIOLATION,
1100 ETH_ANTI_SPOOFING_ERR,
1101 ETH_PACKET_SIZE_TOO_LARGE,
1102 CORE_ILLEGAL_VLAN_MODE,
1104 CORE_FIRST_BD_WO_SOP,
1105 CORE_INSUFFICIENT_BDS,
1106 CORE_PACKET_TOO_SMALL,
1107 CORE_ILLEGAL_INBAND_TAGS,
1108 CORE_VLAN_INSERT_AND_INBAND_VLAN,
1110 CORE_CONTROL_PACKET_VIOLATION,
1111 CORE_ANTI_SPOOFING_ERR,
1112 CORE_PACKET_SIZE_TOO_LARGE,
1113 CORE_ILLEGAL_BD_FLAGS,
1114 CORE_GSI_PACKET_VIOLATION,
1115 MAX_MALICIOUS_VF_ERROR_ID,
1118 /* Mstorm non-triggering VF zone */
1119 struct mstorm_non_trigger_vf_zone {
1120 struct eth_mstorm_per_queue_stat eth_queue_stat;
1121 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1124 /* Mstorm VF zone */
1125 struct mstorm_vf_zone {
1126 struct mstorm_non_trigger_vf_zone non_trigger;
1129 /* vlan header including TPID and TCI fields */
1130 struct vlan_header {
1135 /* outer tag configurations */
1136 struct outer_tag_config_struct {
1137 u8 enable_stag_pri_change;
1140 struct vlan_header outer_tag;
1141 u8 inner_to_outer_pri_map[8];
1144 /* personality per PF */
1145 enum personality_type {
1146 BAD_PERSONALITY_TYP,
1149 PERSONALITY_RDMA_AND_ETH,
1153 PERSONALITY_RESERVED,
1154 MAX_PERSONALITY_TYPE
1157 /* tunnel configuration */
1158 struct pf_start_tunnel_config {
1159 u8 set_vxlan_udp_port_flg;
1160 u8 set_geneve_udp_port_flg;
1161 u8 set_no_inner_l2_vxlan_udp_port_flg;
1162 u8 tunnel_clss_vxlan;
1163 u8 tunnel_clss_l2geneve;
1164 u8 tunnel_clss_ipgeneve;
1165 u8 tunnel_clss_l2gre;
1166 u8 tunnel_clss_ipgre;
1167 __le16 vxlan_udp_port;
1168 __le16 geneve_udp_port;
1169 __le16 no_inner_l2_vxlan_udp_port;
1173 /* Ramrod data for PF start ramrod */
1174 struct pf_start_ramrod_data {
1175 struct regpair event_ring_pbl_addr;
1176 struct regpair consolid_q_pbl_addr;
1177 struct pf_start_tunnel_config tunnel_config;
1178 __le16 event_ring_sb_id;
1181 u8 event_ring_num_pages;
1182 u8 event_ring_sb_index;
1184 u8 warning_as_error;
1185 u8 dont_log_ramrods;
1187 __le16 log_type_mask;
1190 u8 allow_npar_tx_switching;
1192 struct hsi_fp_ver_struct hsi_fp_ver;
1193 struct outer_tag_config_struct outer_tag_config;
1196 /* Data for port update ramrod */
1197 struct protocol_dcb_data {
1199 u8 dscp_enable_flag;
1203 u8 dcb_dont_add_vlan0;
1206 /* Update tunnel configuration */
1207 struct pf_update_tunnel_config {
1208 u8 update_rx_pf_clss;
1209 u8 update_rx_def_ucast_clss;
1210 u8 update_rx_def_non_ucast_clss;
1211 u8 set_vxlan_udp_port_flg;
1212 u8 set_geneve_udp_port_flg;
1213 u8 set_no_inner_l2_vxlan_udp_port_flg;
1214 u8 tunnel_clss_vxlan;
1215 u8 tunnel_clss_l2geneve;
1216 u8 tunnel_clss_ipgeneve;
1217 u8 tunnel_clss_l2gre;
1218 u8 tunnel_clss_ipgre;
1220 __le16 vxlan_udp_port;
1221 __le16 geneve_udp_port;
1222 __le16 no_inner_l2_vxlan_udp_port;
1223 __le16 reserved1[3];
1226 /* Data for port update ramrod */
1227 struct pf_update_ramrod_data {
1228 u8 update_eth_dcb_data_mode;
1229 u8 update_fcoe_dcb_data_mode;
1230 u8 update_iscsi_dcb_data_mode;
1231 u8 update_roce_dcb_data_mode;
1232 u8 update_rroce_dcb_data_mode;
1233 u8 update_iwarp_dcb_data_mode;
1234 u8 update_mf_vlan_flag;
1235 u8 update_enable_stag_pri_change;
1236 struct protocol_dcb_data eth_dcb_data;
1237 struct protocol_dcb_data fcoe_dcb_data;
1238 struct protocol_dcb_data iscsi_dcb_data;
1239 struct protocol_dcb_data roce_dcb_data;
1240 struct protocol_dcb_data rroce_dcb_data;
1241 struct protocol_dcb_data iwarp_dcb_data;
1243 u8 enable_stag_pri_change;
1245 struct pf_update_tunnel_config tunnel_config;
1258 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1259 enum protocol_version_array_key {
1262 MAX_PROTOCOL_VERSION_ARRAY_KEY
1266 struct rdma_sent_stats {
1267 struct regpair sent_bytes;
1268 struct regpair sent_pkts;
1271 /* Pstorm non-triggering VF zone */
1272 struct pstorm_non_trigger_vf_zone {
1273 struct eth_pstorm_per_queue_stat eth_queue_stat;
1274 struct rdma_sent_stats rdma_stats;
1277 /* Pstorm VF zone */
1278 struct pstorm_vf_zone {
1279 struct pstorm_non_trigger_vf_zone non_trigger;
1280 struct regpair reserved[7];
1283 /* Ramrod Header of SPQE */
1284 struct ramrod_header {
1292 struct rdma_rcv_stats {
1293 struct regpair rcv_bytes;
1294 struct regpair rcv_pkts;
1297 /* Data for update QCN/DCQCN RL ramrod */
1298 struct rl_update_ramrod_data {
1299 u8 qcn_update_param_flg;
1300 u8 dcqcn_update_param_flg;
1307 u8 dcqcn_reset_alpha_on_idle;
1309 u8 rl_timer_stage_th;
1317 __le32 dcqcn_timeuot_us;
1318 __le32 qcn_timeuot_us;
1322 /* Slowpath Element (SPQE) */
1323 struct slow_path_element {
1324 struct ramrod_header hdr;
1325 struct regpair data_ptr;
1328 /* Tstorm non-triggering VF zone */
1329 struct tstorm_non_trigger_vf_zone {
1330 struct rdma_rcv_stats rdma_stats;
1333 struct tstorm_per_port_stat {
1334 struct regpair trunc_error_discard;
1335 struct regpair mac_error_discard;
1336 struct regpair mftag_filter_discard;
1337 struct regpair eth_mac_filter_discard;
1338 struct regpair ll2_mac_filter_discard;
1339 struct regpair ll2_conn_disabled_discard;
1340 struct regpair iscsi_irregular_pkt;
1341 struct regpair fcoe_irregular_pkt;
1342 struct regpair roce_irregular_pkt;
1343 struct regpair iwarp_irregular_pkt;
1344 struct regpair eth_irregular_pkt;
1345 struct regpair toe_irregular_pkt;
1346 struct regpair preroce_irregular_pkt;
1347 struct regpair eth_gre_tunn_filter_discard;
1348 struct regpair eth_vxlan_tunn_filter_discard;
1349 struct regpair eth_geneve_tunn_filter_discard;
1350 struct regpair eth_gft_drop_pkt;
1353 /* Tstorm VF zone */
1354 struct tstorm_vf_zone {
1355 struct tstorm_non_trigger_vf_zone non_trigger;
1358 /* Tunnel classification scheme */
1360 TUNNEL_CLSS_MAC_VLAN = 0,
1361 TUNNEL_CLSS_MAC_VNI,
1362 TUNNEL_CLSS_INNER_MAC_VLAN,
1363 TUNNEL_CLSS_INNER_MAC_VNI,
1364 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1368 /* Ustorm non-triggering VF zone */
1369 struct ustorm_non_trigger_vf_zone {
1370 struct eth_ustorm_per_queue_stat eth_queue_stat;
1371 struct regpair vf_pf_msg_addr;
1374 /* Ustorm triggering VF zone */
1375 struct ustorm_trigger_vf_zone {
1380 /* Ustorm VF zone */
1381 struct ustorm_vf_zone {
1382 struct ustorm_non_trigger_vf_zone non_trigger;
1383 struct ustorm_trigger_vf_zone trigger;
1386 /* VF-PF channel data */
1387 struct vf_pf_channel_data {
1394 /* Ramrod data for VF start ramrod */
1395 struct vf_start_ramrod_data {
1401 struct hsi_fp_ver_struct hsi_fp_ver;
1405 /* Ramrod data for VF start ramrod */
1406 struct vf_stop_ramrod_data {
1413 /* VF zone size mode */
1414 enum vf_zone_size_mode {
1415 VF_ZONE_SIZE_MODE_DEFAULT,
1416 VF_ZONE_SIZE_MODE_DOUBLE,
1417 VF_ZONE_SIZE_MODE_QUAD,
1418 MAX_VF_ZONE_SIZE_MODE
1421 /* Xstorm non-triggering VF zone */
1422 struct xstorm_non_trigger_vf_zone {
1423 struct regpair non_edpm_ack_pkts;
1426 /* Tstorm VF zone */
1427 struct xstorm_vf_zone {
1428 struct xstorm_non_trigger_vf_zone non_trigger;
1431 /* Attentions status block */
1432 struct atten_status_block {
1443 #define DMAE_CMD_SRC_MASK 0x1
1444 #define DMAE_CMD_SRC_SHIFT 0
1445 #define DMAE_CMD_DST_MASK 0x3
1446 #define DMAE_CMD_DST_SHIFT 1
1447 #define DMAE_CMD_C_DST_MASK 0x1
1448 #define DMAE_CMD_C_DST_SHIFT 3
1449 #define DMAE_CMD_CRC_RESET_MASK 0x1
1450 #define DMAE_CMD_CRC_RESET_SHIFT 4
1451 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1452 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1453 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1454 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1455 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1456 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1457 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1458 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1459 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1460 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1461 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1462 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1463 #define DMAE_CMD_RESERVED1_MASK 0x1
1464 #define DMAE_CMD_RESERVED1_SHIFT 13
1465 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1466 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1467 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1468 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1469 #define DMAE_CMD_PORT_ID_MASK 0x3
1470 #define DMAE_CMD_PORT_ID_SHIFT 18
1471 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1472 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
1473 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1474 #define DMAE_CMD_DST_PF_ID_SHIFT 24
1475 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1476 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1477 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1478 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1479 #define DMAE_CMD_RESERVED2_MASK 0x3
1480 #define DMAE_CMD_RESERVED2_SHIFT 30
1487 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1488 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1489 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1490 #define DMAE_CMD_DST_VF_ID_SHIFT 8
1491 __le32 comp_addr_lo;
1492 __le32 comp_addr_hi;
1499 __le16 error_bit_reserved;
1500 #define DMAE_CMD_ERROR_BIT_MASK 0x1
1501 #define DMAE_CMD_ERROR_BIT_SHIFT 0
1502 #define DMAE_CMD_RESERVED_MASK 0x7FFF
1503 #define DMAE_CMD_RESERVED_SHIFT 1
1508 enum dmae_cmd_comp_crc_en_enum {
1509 dmae_cmd_comp_crc_disabled,
1510 dmae_cmd_comp_crc_enabled,
1511 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1514 enum dmae_cmd_comp_func_enum {
1515 dmae_cmd_comp_func_to_src,
1516 dmae_cmd_comp_func_to_dst,
1517 MAX_DMAE_CMD_COMP_FUNC_ENUM
1520 enum dmae_cmd_comp_word_en_enum {
1521 dmae_cmd_comp_word_disabled,
1522 dmae_cmd_comp_word_enabled,
1523 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1526 enum dmae_cmd_c_dst_enum {
1527 dmae_cmd_c_dst_pcie,
1529 MAX_DMAE_CMD_C_DST_ENUM
1532 enum dmae_cmd_dst_enum {
1533 dmae_cmd_dst_none_0,
1536 dmae_cmd_dst_none_3,
1537 MAX_DMAE_CMD_DST_ENUM
1540 enum dmae_cmd_error_handling_enum {
1541 dmae_cmd_error_handling_send_regular_comp,
1542 dmae_cmd_error_handling_send_comp_with_err,
1543 dmae_cmd_error_handling_dont_send_comp,
1544 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1547 enum dmae_cmd_src_enum {
1550 MAX_DMAE_CMD_SRC_ENUM
1553 struct e4_mstorm_core_conn_ag_ctx {
1557 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1558 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1559 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1560 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1561 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1562 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1563 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1564 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1565 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1566 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1568 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1569 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1570 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1571 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1572 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1573 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1574 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1575 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1576 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1577 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1578 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1579 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1580 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1581 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1582 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1583 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1590 struct e4_ystorm_core_conn_ag_ctx {
1594 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1595 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1596 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1597 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1598 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1599 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1600 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1601 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1602 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1603 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1605 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1606 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1607 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1608 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1609 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1610 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1611 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1612 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1613 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1614 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1615 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1616 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1617 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1618 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1619 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1620 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1634 /* DMAE parameters */
1635 struct qed_dmae_params {
1637 /* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
1638 * source is a block of length DMAE_MAX_RW_SIZE and the
1639 * destination is larger, the source block will be duplicated as
1640 * many times as required to fill the destination block. This is
1641 * used mostly to write a zeroed buffer to destination address
1644 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
1645 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
1646 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
1647 #define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1
1648 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
1649 #define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT 2
1650 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
1651 #define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT 3
1652 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
1653 #define QED_DMAE_PARAMS_PORT_VALID_SHIFT 4
1654 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
1655 #define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5
1656 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
1657 #define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT 6
1658 #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
1659 #define QED_DMAE_PARAMS_RESERVED_SHIFT 7
1669 /* IGU cleanup command */
1670 struct igu_cleanup {
1671 __le32 sb_id_and_flags;
1672 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1673 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1674 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1675 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1676 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1677 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1678 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1679 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1683 /* IGU firmware driver command */
1685 struct igu_prod_cons_update prod_cons_update;
1686 struct igu_cleanup cleanup;
1689 /* IGU firmware driver command */
1690 struct igu_command_reg_ctrl {
1692 __le16 igu_command_reg_ctrl_fields;
1693 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1694 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1695 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1696 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1697 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1698 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1701 /* IGU mapping line structure */
1702 struct igu_mapping_line {
1703 __le32 igu_mapping_line_fields;
1704 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1705 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1706 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1707 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1708 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1709 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1710 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1711 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1712 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1713 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1714 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1715 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1718 /* IGU MSIX line structure */
1719 struct igu_msix_vector {
1720 struct regpair address;
1722 __le32 msix_vector_fields;
1723 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1724 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1725 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1726 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1727 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1728 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1729 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1730 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1732 /* per encapsulation type enabling flags */
1733 struct prs_reg_encapsulation_type_en {
1735 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1736 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1737 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1738 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1739 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1740 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1741 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1742 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1743 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1744 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1745 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1746 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1747 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1748 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1751 enum pxp_tph_st_hint {
1753 TPH_ST_HINT_REQUESTER,
1755 TPH_ST_HINT_TARGET_PRIO,
1759 /* QM hardware structure of enable bypass credit mask */
1760 struct qm_rf_bypass_mask {
1762 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1763 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1764 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1765 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1766 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1767 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1768 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1769 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1770 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1771 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1772 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1773 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1774 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1775 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1776 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1777 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1780 /* QM hardware structure of opportunistic credit mask */
1781 struct qm_rf_opportunistic_mask {
1783 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1784 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1785 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1786 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1787 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1788 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1789 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1790 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1791 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1792 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1793 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1794 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1795 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1796 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1797 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1798 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1799 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1800 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1801 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1802 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1805 /* QM hardware structure of QM map memory */
1806 struct qm_rf_pq_map_e4 {
1808 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1
1809 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
1810 #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF
1811 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
1812 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
1813 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
1814 #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F
1815 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
1816 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3
1817 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
1818 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1
1819 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
1820 #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
1821 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
1824 /* Completion params for aggregated interrupt completion */
1825 struct sdm_agg_int_comp_params {
1827 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1828 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1829 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1830 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1831 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1832 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1835 /* SDM operation gen command (generate aggregative interrupt) */
1838 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1839 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1840 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1841 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1842 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
1843 #define SDM_OP_GEN_RESERVED_SHIFT 20
1846 /* Physical memory descriptor */
1847 struct phys_mem_desc {
1848 dma_addr_t phys_addr;
1850 u32 size; /* In bytes */
1853 /* Virtual memory descriptor */
1854 struct virt_mem_desc {
1856 u32 size; /* In bytes */
1859 /****************************************/
1860 /* Debug Tools HSI constants and macros */
1861 /****************************************/
1864 GRCBASE_GRC = 0x50000,
1865 GRCBASE_MISCS = 0x9000,
1866 GRCBASE_MISC = 0x8000,
1867 GRCBASE_DBU = 0xa000,
1868 GRCBASE_PGLUE_B = 0x2a8000,
1869 GRCBASE_CNIG = 0x218000,
1870 GRCBASE_CPMU = 0x30000,
1871 GRCBASE_NCSI = 0x40000,
1872 GRCBASE_OPTE = 0x53000,
1873 GRCBASE_BMB = 0x540000,
1874 GRCBASE_PCIE = 0x54000,
1875 GRCBASE_MCP = 0xe00000,
1876 GRCBASE_MCP2 = 0x52000,
1877 GRCBASE_PSWHST = 0x2a0000,
1878 GRCBASE_PSWHST2 = 0x29e000,
1879 GRCBASE_PSWRD = 0x29c000,
1880 GRCBASE_PSWRD2 = 0x29d000,
1881 GRCBASE_PSWWR = 0x29a000,
1882 GRCBASE_PSWWR2 = 0x29b000,
1883 GRCBASE_PSWRQ = 0x280000,
1884 GRCBASE_PSWRQ2 = 0x240000,
1885 GRCBASE_PGLCS = 0x0,
1886 GRCBASE_DMAE = 0xc000,
1887 GRCBASE_PTU = 0x560000,
1888 GRCBASE_TCM = 0x1180000,
1889 GRCBASE_MCM = 0x1200000,
1890 GRCBASE_UCM = 0x1280000,
1891 GRCBASE_XCM = 0x1000000,
1892 GRCBASE_YCM = 0x1080000,
1893 GRCBASE_PCM = 0x1100000,
1894 GRCBASE_QM = 0x2f0000,
1895 GRCBASE_TM = 0x2c0000,
1896 GRCBASE_DORQ = 0x100000,
1897 GRCBASE_BRB = 0x340000,
1898 GRCBASE_SRC = 0x238000,
1899 GRCBASE_PRS = 0x1f0000,
1900 GRCBASE_TSDM = 0xfb0000,
1901 GRCBASE_MSDM = 0xfc0000,
1902 GRCBASE_USDM = 0xfd0000,
1903 GRCBASE_XSDM = 0xf80000,
1904 GRCBASE_YSDM = 0xf90000,
1905 GRCBASE_PSDM = 0xfa0000,
1906 GRCBASE_TSEM = 0x1700000,
1907 GRCBASE_MSEM = 0x1800000,
1908 GRCBASE_USEM = 0x1900000,
1909 GRCBASE_XSEM = 0x1400000,
1910 GRCBASE_YSEM = 0x1500000,
1911 GRCBASE_PSEM = 0x1600000,
1912 GRCBASE_RSS = 0x238800,
1913 GRCBASE_TMLD = 0x4d0000,
1914 GRCBASE_MULD = 0x4e0000,
1915 GRCBASE_YULD = 0x4c8000,
1916 GRCBASE_XYLD = 0x4c0000,
1917 GRCBASE_PTLD = 0x5a0000,
1918 GRCBASE_YPLD = 0x5c0000,
1919 GRCBASE_PRM = 0x230000,
1920 GRCBASE_PBF_PB1 = 0xda0000,
1921 GRCBASE_PBF_PB2 = 0xda4000,
1922 GRCBASE_RPB = 0x23c000,
1923 GRCBASE_BTB = 0xdb0000,
1924 GRCBASE_PBF = 0xd80000,
1925 GRCBASE_RDIF = 0x300000,
1926 GRCBASE_TDIF = 0x310000,
1927 GRCBASE_CDU = 0x580000,
1928 GRCBASE_CCFC = 0x2e0000,
1929 GRCBASE_TCFC = 0x2d0000,
1930 GRCBASE_IGU = 0x180000,
1931 GRCBASE_CAU = 0x1c0000,
1932 GRCBASE_RGFS = 0xf00000,
1933 GRCBASE_RGSRC = 0x320000,
1934 GRCBASE_TGFS = 0xd00000,
1935 GRCBASE_TGSRC = 0x322000,
1936 GRCBASE_UMAC = 0x51000,
1937 GRCBASE_XMAC = 0x210000,
1938 GRCBASE_DBG = 0x10000,
1939 GRCBASE_NIG = 0x500000,
1940 GRCBASE_WOL = 0x600000,
1941 GRCBASE_BMBN = 0x610000,
1942 GRCBASE_IPC = 0x20000,
1943 GRCBASE_NWM = 0x800000,
1944 GRCBASE_NWS = 0x700000,
1945 GRCBASE_MS = 0x6a0000,
1946 GRCBASE_PHY_PCIE = 0x620000,
1947 GRCBASE_LED = 0x6b8000,
1948 GRCBASE_AVS_WRAP = 0x6b0000,
1949 GRCBASE_PXPREQBUS = 0x56000,
1950 GRCBASE_MISC_AEU = 0x8000,
1951 GRCBASE_BAR0_MAP = 0x1c00000,
2047 /* binary debug buffer types */
2048 enum bin_dbg_buffer_type {
2049 BIN_BUF_DBG_MODE_TREE,
2050 BIN_BUF_DBG_DUMP_REG,
2051 BIN_BUF_DBG_DUMP_MEM,
2052 BIN_BUF_DBG_IDLE_CHK_REGS,
2053 BIN_BUF_DBG_IDLE_CHK_IMMS,
2054 BIN_BUF_DBG_IDLE_CHK_RULES,
2055 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
2056 BIN_BUF_DBG_ATTN_BLOCKS,
2057 BIN_BUF_DBG_ATTN_REGS,
2058 BIN_BUF_DBG_ATTN_INDEXES,
2059 BIN_BUF_DBG_ATTN_NAME_OFFSETS,
2060 BIN_BUF_DBG_BUS_BLOCKS,
2061 BIN_BUF_DBG_BUS_LINES,
2062 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
2063 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
2064 BIN_BUF_DBG_PARSING_STRINGS,
2065 MAX_BIN_DBG_BUFFER_TYPE
2069 /* Attention bit mapping */
2070 struct dbg_attn_bit_mapping {
2072 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
2073 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
2074 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
2075 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
2078 /* Attention block per-type data */
2079 struct dbg_attn_block_type_data {
2088 /* Block attentions */
2089 struct dbg_attn_block {
2090 struct dbg_attn_block_type_data per_type_data[2];
2093 /* Attention register result */
2094 struct dbg_attn_reg_result {
2096 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
2097 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
2098 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
2099 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24
2100 u16 block_attn_offset;
2106 /* Attention block result */
2107 struct dbg_attn_block_result {
2110 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
2111 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
2112 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
2113 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
2115 struct dbg_attn_reg_result reg_results[15];
2119 struct dbg_mode_hdr {
2121 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
2122 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
2123 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
2124 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
2127 /* Attention register */
2128 struct dbg_attn_reg {
2129 struct dbg_mode_hdr mode;
2130 u16 block_attn_offset;
2132 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
2133 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
2134 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
2135 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
2136 u32 sts_clr_address;
2140 /* Attention types */
2141 enum dbg_attn_type {
2142 ATTN_TYPE_INTERRUPT,
2147 /* Debug Bus block data */
2148 struct dbg_bus_block {
2150 u8 has_latency_events;
2154 /* Debug Bus block user data */
2155 struct dbg_bus_block_user_data {
2157 u8 has_latency_events;
2161 /* Block Debug line data */
2162 struct dbg_bus_line {
2164 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
2165 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
2166 #define DBG_BUS_LINE_IS_256B_MASK 0x1
2167 #define DBG_BUS_LINE_IS_256B_SHIFT 4
2168 #define DBG_BUS_LINE_RESERVED_MASK 0x7
2169 #define DBG_BUS_LINE_RESERVED_SHIFT 5
2173 /* Condition header for registers dump */
2174 struct dbg_dump_cond_hdr {
2175 struct dbg_mode_hdr mode; /* Mode header */
2176 u8 block_id; /* block ID */
2177 u8 data_size; /* size in dwords of the data following this header */
2180 /* Memory data for registers dump */
2181 struct dbg_dump_mem {
2183 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
2184 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
2185 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
2186 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
2188 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
2189 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
2190 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
2191 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
2192 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F
2193 #define DBG_DUMP_MEM_RESERVED_SHIFT 25
2196 /* Register data for registers dump */
2197 struct dbg_dump_reg {
2199 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF
2200 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
2201 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1
2202 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
2203 #define DBG_DUMP_REG_LENGTH_MASK 0xFF
2204 #define DBG_DUMP_REG_LENGTH_SHIFT 24
2207 /* Split header for registers dump */
2208 struct dbg_dump_split_hdr {
2210 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
2211 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
2212 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
2213 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
2216 /* Condition header for idle check */
2217 struct dbg_idle_chk_cond_hdr {
2218 struct dbg_mode_hdr mode; /* Mode header */
2219 u16 data_size; /* size in dwords of the data following this header */
2222 /* Idle Check condition register */
2223 struct dbg_idle_chk_cond_reg {
2225 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
2226 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
2227 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
2228 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
2229 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
2230 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
2236 /* Idle Check info register */
2237 struct dbg_idle_chk_info_reg {
2239 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
2240 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
2241 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
2242 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
2243 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
2244 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
2245 u16 size; /* register size in dwords */
2246 struct dbg_mode_hdr mode; /* Mode header */
2249 /* Idle Check register */
2250 union dbg_idle_chk_reg {
2251 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2252 struct dbg_idle_chk_info_reg info_reg; /* info register */
2255 /* Idle Check result header */
2256 struct dbg_idle_chk_result_hdr {
2257 u16 rule_id; /* Failing rule index */
2258 u16 mem_entry_id; /* Failing memory entry index */
2259 u8 num_dumped_cond_regs; /* number of dumped condition registers */
2260 u8 num_dumped_info_regs; /* number of dumped condition registers */
2261 u8 severity; /* from dbg_idle_chk_severity_types enum */
2265 /* Idle Check result register header */
2266 struct dbg_idle_chk_result_reg_hdr {
2268 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
2269 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2270 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
2271 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2272 u8 start_entry; /* index of the first checked entry */
2273 u16 size; /* register size in dwords */
2276 /* Idle Check rule */
2277 struct dbg_idle_chk_rule {
2278 u16 rule_id; /* Idle Check rule ID */
2279 u8 severity; /* value from dbg_idle_chk_severity_types enum */
2280 u8 cond_id; /* Condition ID */
2281 u8 num_cond_regs; /* number of condition registers */
2282 u8 num_info_regs; /* number of info registers */
2283 u8 num_imms; /* number of immediates in the condition */
2285 u16 reg_offset; /* offset of this rules registers in the idle check
2286 * register array (in dbg_idle_chk_reg units).
2288 u16 imm_offset; /* offset of this rules immediate values in the
2289 * immediate values array (in dwords).
2293 /* Idle Check rule parsing data */
2294 struct dbg_idle_chk_rule_parsing_data {
2296 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
2297 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2298 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
2299 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
2302 /* Idle check severity types */
2303 enum dbg_idle_chk_severity_types {
2304 /* idle check failure should cause an error */
2305 IDLE_CHK_SEVERITY_ERROR,
2306 /* idle check failure should cause an error only if theres no traffic */
2307 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2308 /* idle check failure should cause a warning */
2309 IDLE_CHK_SEVERITY_WARNING,
2310 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2313 /* Debug Bus block data */
2314 struct dbg_bus_block_data {
2316 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF
2317 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0
2318 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF
2319 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4
2320 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF
2321 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8
2322 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF
2323 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12
2328 /* Debug Bus Clients */
2329 enum dbg_bus_clients {
2330 DBG_BUS_CLIENT_RBCN,
2331 DBG_BUS_CLIENT_RBCP,
2332 DBG_BUS_CLIENT_RBCR,
2333 DBG_BUS_CLIENT_RBCT,
2334 DBG_BUS_CLIENT_RBCU,
2335 DBG_BUS_CLIENT_RBCF,
2336 DBG_BUS_CLIENT_RBCX,
2337 DBG_BUS_CLIENT_RBCS,
2338 DBG_BUS_CLIENT_RBCH,
2339 DBG_BUS_CLIENT_RBCZ,
2340 DBG_BUS_CLIENT_OTHER_ENGINE,
2341 DBG_BUS_CLIENT_TIMESTAMP,
2343 DBG_BUS_CLIENT_RBCY,
2344 DBG_BUS_CLIENT_RBCQ,
2345 DBG_BUS_CLIENT_RBCM,
2346 DBG_BUS_CLIENT_RBCB,
2347 DBG_BUS_CLIENT_RBCW,
2348 DBG_BUS_CLIENT_RBCV,
2352 /* Debug Bus constraint operation types */
2353 enum dbg_bus_constraint_ops {
2354 DBG_BUS_CONSTRAINT_OP_EQ,
2355 DBG_BUS_CONSTRAINT_OP_NE,
2356 DBG_BUS_CONSTRAINT_OP_LT,
2357 DBG_BUS_CONSTRAINT_OP_LTC,
2358 DBG_BUS_CONSTRAINT_OP_LE,
2359 DBG_BUS_CONSTRAINT_OP_LEC,
2360 DBG_BUS_CONSTRAINT_OP_GT,
2361 DBG_BUS_CONSTRAINT_OP_GTC,
2362 DBG_BUS_CONSTRAINT_OP_GE,
2363 DBG_BUS_CONSTRAINT_OP_GEC,
2364 MAX_DBG_BUS_CONSTRAINT_OPS
2367 /* Debug Bus trigger state data */
2368 struct dbg_bus_trigger_state_data {
2370 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF
2371 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0
2372 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF
2373 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4
2376 /* Debug Bus memory address */
2377 struct dbg_bus_mem_addr {
2382 /* Debug Bus PCI buffer data */
2383 struct dbg_bus_pci_buf_data {
2384 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2385 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2386 u32 size; /* PCI buffer size in bytes */
2389 /* Debug Bus Storm EID range filter params */
2390 struct dbg_bus_storm_eid_range_params {
2391 u8 min; /* Minimal event ID to filter on */
2392 u8 max; /* Maximal event ID to filter on */
2395 /* Debug Bus Storm EID mask filter params */
2396 struct dbg_bus_storm_eid_mask_params {
2397 u8 val; /* Event ID value */
2398 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2401 /* Debug Bus Storm EID filter params */
2402 union dbg_bus_storm_eid_params {
2403 struct dbg_bus_storm_eid_range_params range;
2404 struct dbg_bus_storm_eid_mask_params mask;
2407 /* Debug Bus Storm data */
2408 struct dbg_bus_storm_data {
2413 u8 eid_range_not_mask;
2415 union dbg_bus_storm_eid_params eid_filter_params;
2419 /* Debug Bus data */
2420 struct dbg_bus_data {
2425 u8 num_enabled_blocks;
2426 u8 num_enabled_storms;
2430 u8 timestamp_input_en;
2433 u8 filter_pre_trigger;
2434 u8 filter_post_trigger;
2437 struct dbg_bus_trigger_state_data trigger_states[3];
2438 u8 next_trigger_state;
2439 u8 next_constraint_id;
2441 u8 rcv_from_other_engine;
2442 struct dbg_bus_pci_buf_data pci_buf;
2443 struct dbg_bus_block_data blocks[88];
2444 struct dbg_bus_storm_data storms[6];
2447 /* Debug bus filter types */
2448 enum dbg_bus_filter_types {
2449 DBG_BUS_FILTER_TYPE_OFF,
2450 DBG_BUS_FILTER_TYPE_PRE,
2451 DBG_BUS_FILTER_TYPE_POST,
2452 DBG_BUS_FILTER_TYPE_ON,
2453 MAX_DBG_BUS_FILTER_TYPES
2456 /* Debug bus frame modes */
2457 enum dbg_bus_frame_modes {
2458 DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2459 DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2460 DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2461 MAX_DBG_BUS_FRAME_MODES
2464 /* Debug bus other engine mode */
2465 enum dbg_bus_other_engine_modes {
2466 DBG_BUS_OTHER_ENGINE_MODE_NONE,
2467 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2468 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2469 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2470 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2471 MAX_DBG_BUS_OTHER_ENGINE_MODES
2474 /* Debug bus post-trigger recording types */
2475 enum dbg_bus_post_trigger_types {
2476 DBG_BUS_POST_TRIGGER_RECORD,
2477 DBG_BUS_POST_TRIGGER_DROP,
2478 MAX_DBG_BUS_POST_TRIGGER_TYPES
2481 /* Debug bus pre-trigger recording types */
2482 enum dbg_bus_pre_trigger_types {
2483 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2484 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2485 DBG_BUS_PRE_TRIGGER_DROP,
2486 MAX_DBG_BUS_PRE_TRIGGER_TYPES
2489 /* Debug bus SEMI frame modes */
2490 enum dbg_bus_semi_frame_modes {
2491 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2492 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2493 MAX_DBG_BUS_SEMI_FRAME_MODES
2496 /* Debug bus states */
2497 enum dbg_bus_states {
2499 DBG_BUS_STATE_READY,
2500 DBG_BUS_STATE_RECORDING,
2501 DBG_BUS_STATE_STOPPED,
2505 /* Debug Bus Storm modes */
2506 enum dbg_bus_storm_modes {
2507 DBG_BUS_STORM_MODE_PRINTF,
2508 DBG_BUS_STORM_MODE_PRAM_ADDR,
2509 DBG_BUS_STORM_MODE_DRA_RW,
2510 DBG_BUS_STORM_MODE_DRA_W,
2511 DBG_BUS_STORM_MODE_LD_ST_ADDR,
2512 DBG_BUS_STORM_MODE_DRA_FSM,
2513 DBG_BUS_STORM_MODE_RH,
2514 DBG_BUS_STORM_MODE_FOC,
2515 DBG_BUS_STORM_MODE_EXT_STORE,
2516 MAX_DBG_BUS_STORM_MODES
2519 /* Debug bus target IDs */
2520 enum dbg_bus_targets {
2521 DBG_BUS_TARGET_ID_INT_BUF,
2522 DBG_BUS_TARGET_ID_NIG,
2523 DBG_BUS_TARGET_ID_PCI,
2528 struct dbg_grc_data {
2529 u8 params_initialized;
2535 /* Debug GRC params */
2536 enum dbg_grc_params {
2537 DBG_GRC_PARAM_DUMP_TSTORM,
2538 DBG_GRC_PARAM_DUMP_MSTORM,
2539 DBG_GRC_PARAM_DUMP_USTORM,
2540 DBG_GRC_PARAM_DUMP_XSTORM,
2541 DBG_GRC_PARAM_DUMP_YSTORM,
2542 DBG_GRC_PARAM_DUMP_PSTORM,
2543 DBG_GRC_PARAM_DUMP_REGS,
2544 DBG_GRC_PARAM_DUMP_RAM,
2545 DBG_GRC_PARAM_DUMP_PBUF,
2546 DBG_GRC_PARAM_DUMP_IOR,
2547 DBG_GRC_PARAM_DUMP_VFC,
2548 DBG_GRC_PARAM_DUMP_CM_CTX,
2549 DBG_GRC_PARAM_DUMP_PXP,
2550 DBG_GRC_PARAM_DUMP_RSS,
2551 DBG_GRC_PARAM_DUMP_CAU,
2552 DBG_GRC_PARAM_DUMP_QM,
2553 DBG_GRC_PARAM_DUMP_MCP,
2554 DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2555 DBG_GRC_PARAM_DUMP_CFC,
2556 DBG_GRC_PARAM_DUMP_IGU,
2557 DBG_GRC_PARAM_DUMP_BRB,
2558 DBG_GRC_PARAM_DUMP_BTB,
2559 DBG_GRC_PARAM_DUMP_BMB,
2560 DBG_GRC_PARAM_DUMP_NIG,
2561 DBG_GRC_PARAM_DUMP_MULD,
2562 DBG_GRC_PARAM_DUMP_PRS,
2563 DBG_GRC_PARAM_DUMP_DMAE,
2564 DBG_GRC_PARAM_DUMP_TM,
2565 DBG_GRC_PARAM_DUMP_SDM,
2566 DBG_GRC_PARAM_DUMP_DIF,
2567 DBG_GRC_PARAM_DUMP_STATIC,
2568 DBG_GRC_PARAM_UNSTALL,
2569 DBG_GRC_PARAM_NUM_LCIDS,
2570 DBG_GRC_PARAM_NUM_LTIDS,
2571 DBG_GRC_PARAM_EXCLUDE_ALL,
2572 DBG_GRC_PARAM_CRASH,
2573 DBG_GRC_PARAM_PARITY_SAFE,
2574 DBG_GRC_PARAM_DUMP_CM,
2575 DBG_GRC_PARAM_DUMP_PHY,
2576 DBG_GRC_PARAM_NO_MCP,
2577 DBG_GRC_PARAM_NO_FW_VER,
2581 /* Debug reset registers */
2582 enum dbg_reset_regs {
2583 DBG_RESET_REG_MISCS_PL_UA,
2584 DBG_RESET_REG_MISCS_PL_HV,
2585 DBG_RESET_REG_MISCS_PL_HV_2,
2586 DBG_RESET_REG_MISC_PL_UA,
2587 DBG_RESET_REG_MISC_PL_HV,
2588 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2589 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2590 DBG_RESET_REG_MISC_PL_PDA_VAUX,
2594 /* Debug status codes */
2597 DBG_STATUS_APP_VERSION_NOT_SET,
2598 DBG_STATUS_UNSUPPORTED_APP_VERSION,
2599 DBG_STATUS_DBG_BLOCK_NOT_RESET,
2600 DBG_STATUS_INVALID_ARGS,
2601 DBG_STATUS_OUTPUT_ALREADY_SET,
2602 DBG_STATUS_INVALID_PCI_BUF_SIZE,
2603 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2604 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2605 DBG_STATUS_TOO_MANY_INPUTS,
2606 DBG_STATUS_INPUT_OVERLAP,
2607 DBG_STATUS_HW_ONLY_RECORDING,
2608 DBG_STATUS_STORM_ALREADY_ENABLED,
2609 DBG_STATUS_STORM_NOT_ENABLED,
2610 DBG_STATUS_BLOCK_ALREADY_ENABLED,
2611 DBG_STATUS_BLOCK_NOT_ENABLED,
2612 DBG_STATUS_NO_INPUT_ENABLED,
2613 DBG_STATUS_NO_FILTER_TRIGGER_64B,
2614 DBG_STATUS_FILTER_ALREADY_ENABLED,
2615 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2616 DBG_STATUS_TRIGGER_NOT_ENABLED,
2617 DBG_STATUS_CANT_ADD_CONSTRAINT,
2618 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2619 DBG_STATUS_TOO_MANY_CONSTRAINTS,
2620 DBG_STATUS_RECORDING_NOT_STARTED,
2621 DBG_STATUS_DATA_DIDNT_TRIGGER,
2622 DBG_STATUS_NO_DATA_RECORDED,
2623 DBG_STATUS_DUMP_BUF_TOO_SMALL,
2624 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2625 DBG_STATUS_UNKNOWN_CHIP,
2626 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2627 DBG_STATUS_BLOCK_IN_RESET,
2628 DBG_STATUS_INVALID_TRACE_SIGNATURE,
2629 DBG_STATUS_INVALID_NVRAM_BUNDLE,
2630 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2631 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2632 DBG_STATUS_NVRAM_READ_FAILED,
2633 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2634 DBG_STATUS_MCP_TRACE_BAD_DATA,
2635 DBG_STATUS_MCP_TRACE_NO_META,
2636 DBG_STATUS_MCP_COULD_NOT_HALT,
2637 DBG_STATUS_MCP_COULD_NOT_RESUME,
2638 DBG_STATUS_RESERVED2,
2639 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2640 DBG_STATUS_IGU_FIFO_BAD_DATA,
2641 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2642 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2643 DBG_STATUS_REG_FIFO_BAD_DATA,
2644 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2645 DBG_STATUS_DBG_ARRAY_NOT_SET,
2646 DBG_STATUS_FILTER_BUG,
2647 DBG_STATUS_NON_MATCHING_LINES,
2648 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
2649 DBG_STATUS_DBG_BUS_IN_USE,
2653 /* Debug Storms IDs */
2664 /* Idle Check data */
2665 struct idle_chk_data {
2672 struct pretend_params {
2678 /* Debug Tools data (per HW function)
2680 struct dbg_tools_data {
2681 struct dbg_grc_data grc;
2682 struct dbg_bus_data bus;
2683 struct idle_chk_data idle_chk;
2685 u8 block_in_reset[88];
2689 u8 num_pfs_per_port;
2694 struct pretend_params pretend;
2698 /********************************/
2699 /* HSI Init Functions constants */
2700 /********************************/
2702 /* Number of VLAN priorities */
2703 #define NUM_OF_VLAN_PRIORITIES 8
2705 /* BRB RAM init requirements */
2706 struct init_brb_ram_req {
2707 u32 guranteed_per_tc;
2708 u32 headroom_per_tc;
2710 u32 max_ports_per_engine;
2711 u8 num_active_tcs[MAX_NUM_PORTS];
2714 /* ETS per-TC init requirements */
2715 struct init_ets_tc_req {
2721 /* ETS init requirements */
2722 struct init_ets_req {
2724 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2727 /* NIG LB RL init requirements */
2728 struct init_nig_lb_rl_req {
2732 u16 tc_rate[NUM_OF_PHYS_TCS];
2735 /* NIG TC mapping for each priority */
2736 struct init_nig_pri_tc_map_entry {
2741 /* NIG priority to TC map init requirements */
2742 struct init_nig_pri_tc_map_req {
2743 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2746 /* QM per global RL init parameters */
2747 struct init_qm_global_rl_params {
2751 /* QM per-port init parameters */
2752 struct init_qm_port_params {
2753 u16 active_phys_tcs;
2754 u16 num_pbf_cmd_lines;
2760 /* QM per-PQ init parameters */
2761 struct init_qm_pq_params {
2771 /* QM per-vport init parameters */
2772 struct init_qm_vport_params {
2774 u16 first_tx_pq_id[NUM_OF_TCS];
2777 /**************************************/
2778 /* Init Tool HSI constants and macros */
2779 /**************************************/
2781 /* Width of GRC address in bits (addresses are specified in dwords) */
2782 #define GRC_ADDR_BITS 23
2783 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
2785 /* indicates an init that should be applied to any phase ID */
2786 #define ANY_PHASE_ID 0xffff
2788 /* Max size in dwords of a zipped array */
2789 #define MAX_ZIPPED_SIZE 8192
2797 struct fw_asserts_ram_section {
2798 __le16 section_ram_line_offset;
2799 __le16 section_ram_line_size;
2800 u8 list_dword_offset;
2801 u8 list_element_dword_size;
2802 u8 list_num_elements;
2803 u8 list_next_index_dword_offset;
2813 struct fw_ver_info {
2817 struct fw_ver_num num;
2823 struct fw_ver_info ver;
2824 struct fw_asserts_ram_section fw_asserts_section;
2827 struct fw_info_location {
2844 MODE_PORTS_PER_ENG_1,
2845 MODE_PORTS_PER_ENG_2,
2846 MODE_PORTS_PER_ENG_4,
2862 enum init_split_types {
2868 MAX_INIT_SPLIT_TYPES
2871 /* Binary buffer header */
2872 struct bin_buffer_hdr {
2877 /* Binary init buffer types */
2878 enum bin_init_buffer_type {
2879 BIN_BUF_INIT_FW_VER_INFO,
2882 BIN_BUF_INIT_MODE_TREE,
2884 BIN_BUF_INIT_OVERLAYS,
2885 MAX_BIN_INIT_BUFFER_TYPE
2888 /* FW overlay buffer header */
2889 struct fw_overlay_buf_hdr {
2891 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
2892 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2893 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
2894 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
2897 /* init array header: raw */
2898 struct init_array_raw_hdr {
2900 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2901 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2902 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2903 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2906 /* init array header: standard */
2907 struct init_array_standard_hdr {
2909 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2910 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2911 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2912 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
2915 /* init array header: zipped */
2916 struct init_array_zipped_hdr {
2918 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2919 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2920 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2921 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2924 /* init array header: pattern */
2925 struct init_array_pattern_hdr {
2927 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2928 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2929 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2930 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2931 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2932 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
2935 /* init array header union */
2936 union init_array_hdr {
2937 struct init_array_raw_hdr raw;
2938 struct init_array_standard_hdr standard;
2939 struct init_array_zipped_hdr zipped;
2940 struct init_array_pattern_hdr pattern;
2943 /* init array types */
2944 enum init_array_types {
2948 MAX_INIT_ARRAY_TYPES
2951 /* init operation: callback */
2952 struct init_callback_op {
2954 #define INIT_CALLBACK_OP_OP_MASK 0xF
2955 #define INIT_CALLBACK_OP_OP_SHIFT 0
2956 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2957 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2962 /* init operation: delay */
2963 struct init_delay_op {
2965 #define INIT_DELAY_OP_OP_MASK 0xF
2966 #define INIT_DELAY_OP_OP_SHIFT 0
2967 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2968 #define INIT_DELAY_OP_RESERVED_SHIFT 4
2972 /* init operation: if_mode */
2973 struct init_if_mode_op {
2975 #define INIT_IF_MODE_OP_OP_MASK 0xF
2976 #define INIT_IF_MODE_OP_OP_SHIFT 0
2977 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2978 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2979 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2980 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2982 u16 modes_buf_offset;
2985 /* init operation: if_phase */
2986 struct init_if_phase_op {
2988 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2989 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2990 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
2991 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4
2992 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2993 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
2995 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2996 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2997 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2998 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2999 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
3000 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
3003 /* init mode operators */
3004 enum init_mode_ops {
3011 /* init operation: raw */
3012 struct init_raw_op {
3014 #define INIT_RAW_OP_OP_MASK 0xF
3015 #define INIT_RAW_OP_OP_SHIFT 0
3016 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
3017 #define INIT_RAW_OP_PARAM1_SHIFT 4
3021 /* init array params */
3022 struct init_op_array_params {
3027 /* Write init operation arguments */
3028 union init_write_args {
3032 struct init_op_array_params runtime;
3035 /* init operation: write */
3036 struct init_write_op {
3038 #define INIT_WRITE_OP_OP_MASK 0xF
3039 #define INIT_WRITE_OP_OP_SHIFT 0
3040 #define INIT_WRITE_OP_SOURCE_MASK 0x7
3041 #define INIT_WRITE_OP_SOURCE_SHIFT 4
3042 #define INIT_WRITE_OP_RESERVED_MASK 0x1
3043 #define INIT_WRITE_OP_RESERVED_SHIFT 7
3044 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
3045 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
3046 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
3047 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
3048 union init_write_args args;
3051 /* init operation: read */
3052 struct init_read_op {
3054 #define INIT_READ_OP_OP_MASK 0xF
3055 #define INIT_READ_OP_OP_SHIFT 0
3056 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
3057 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
3058 #define INIT_READ_OP_RESERVED_MASK 0x1
3059 #define INIT_READ_OP_RESERVED_SHIFT 8
3060 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
3061 #define INIT_READ_OP_ADDRESS_SHIFT 9
3065 /* Init operations union */
3067 struct init_raw_op raw;
3068 struct init_write_op write;
3069 struct init_read_op read;
3070 struct init_if_mode_op if_mode;
3071 struct init_if_phase_op if_phase;
3072 struct init_callback_op callback;
3073 struct init_delay_op delay;
3076 /* Init command operation types */
3077 enum init_op_types {
3087 /* init polling types */
3088 enum init_poll_types {
3096 /* init source types */
3097 enum init_source_types {
3102 MAX_INIT_SOURCE_TYPES
3105 /* Internal RAM Offsets macro data */
3114 /***************************** Public Functions *******************************/
3117 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
3120 * @param bin_ptr - a pointer to the binary data with debug arrays.
3122 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
3125 * @brief qed_read_regs - Reads registers into a buffer (using GRC).
3127 * @param p_hwfn - HW device data
3128 * @param p_ptt - Ptt window used for writing the registers.
3129 * @param buf - Destination buffer.
3130 * @param addr - Source GRC address in dwords.
3131 * @param len - Number of registers to read.
3133 void qed_read_regs(struct qed_hwfn *p_hwfn,
3134 struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
3137 * @brief qed_read_fw_info - Reads FW info from the chip.
3139 * The FW info contains FW-related information, such as the FW version,
3140 * FW image (main/L2B/kuku), FW timestamp, etc.
3141 * The FW info is read from the internal RAM of the first Storm that is not in
3144 * @param p_hwfn - HW device data
3145 * @param p_ptt - Ptt window used for writing the registers.
3146 * @param fw_info - Out: a pointer to write the FW info into.
3148 * @return true if the FW info was read successfully from one of the Storms,
3149 * or false if all Storms are in reset.
3151 bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
3152 struct qed_ptt *p_ptt, struct fw_info *fw_info);
3154 * @brief qed_dbg_grc_config - Sets the value of a GRC parameter.
3156 * @param p_hwfn - HW device data
3157 * @param grc_param - GRC parameter
3158 * @param val - Value to set.
3160 * @return error if one of the following holds:
3161 * - the version wasn't set
3162 * - grc_param is invalid
3163 * - val is outside the allowed boundaries
3165 enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
3166 struct qed_ptt *p_ptt,
3167 enum dbg_grc_params grc_param, u32 val);
3170 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
3173 * @param p_hwfn - HW device data
3175 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
3177 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
3180 * @param p_hwfn - HW device data
3181 * @param p_ptt - Ptt window used for writing the registers.
3182 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
3185 * @return error if one of the following holds:
3186 * - the version wasn't set
3187 * Otherwise, returns ok.
3189 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3190 struct qed_ptt *p_ptt,
3194 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
3196 * @param p_hwfn - HW device data
3197 * @param p_ptt - Ptt window used for writing the registers.
3198 * @param dump_buf - Pointer to write the collected GRC data into.
3199 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3200 * @param num_dumped_dwords - OUT: number of dumped dwords.
3202 * @return error if one of the following holds:
3203 * - the version wasn't set
3204 * - the specified dump buffer is too small
3205 * Otherwise, returns ok.
3207 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
3208 struct qed_ptt *p_ptt,
3210 u32 buf_size_in_dwords,
3211 u32 *num_dumped_dwords);
3214 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
3215 * for idle check results.
3217 * @param p_hwfn - HW device data
3218 * @param p_ptt - Ptt window used for writing the registers.
3219 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
3222 * @return error if one of the following holds:
3223 * - the version wasn't set
3224 * Otherwise, returns ok.
3226 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3227 struct qed_ptt *p_ptt,
3231 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
3232 * into the specified buffer.
3234 * @param p_hwfn - HW device data
3235 * @param p_ptt - Ptt window used for writing the registers.
3236 * @param dump_buf - Pointer to write the idle check data into.
3237 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3238 * @param num_dumped_dwords - OUT: number of dumped dwords.
3240 * @return error if one of the following holds:
3241 * - the version wasn't set
3242 * - the specified buffer is too small
3243 * Otherwise, returns ok.
3245 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
3246 struct qed_ptt *p_ptt,
3248 u32 buf_size_in_dwords,
3249 u32 *num_dumped_dwords);
3252 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
3253 * for mcp trace results.
3255 * @param p_hwfn - HW device data
3256 * @param p_ptt - Ptt window used for writing the registers.
3257 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
3259 * @return error if one of the following holds:
3260 * - the version wasn't set
3261 * - the trace data in MCP scratchpad contain an invalid signature
3262 * - the bundle ID in NVRAM is invalid
3263 * - the trace meta data cannot be found (in NVRAM or image file)
3264 * Otherwise, returns ok.
3266 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3267 struct qed_ptt *p_ptt,
3271 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
3272 * into the specified buffer.
3274 * @param p_hwfn - HW device data
3275 * @param p_ptt - Ptt window used for writing the registers.
3276 * @param dump_buf - Pointer to write the mcp trace data into.
3277 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3278 * @param num_dumped_dwords - OUT: number of dumped dwords.
3280 * @return error if one of the following holds:
3281 * - the version wasn't set
3282 * - the specified buffer is too small
3283 * - the trace data in MCP scratchpad contain an invalid signature
3284 * - the bundle ID in NVRAM is invalid
3285 * - the trace meta data cannot be found (in NVRAM or image file)
3286 * - the trace meta data cannot be read (from NVRAM or image file)
3287 * Otherwise, returns ok.
3289 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3290 struct qed_ptt *p_ptt,
3292 u32 buf_size_in_dwords,
3293 u32 *num_dumped_dwords);
3296 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3297 * for grc trace fifo results.
3299 * @param p_hwfn - HW device data
3300 * @param p_ptt - Ptt window used for writing the registers.
3301 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3303 * @return error if one of the following holds:
3304 * - the version wasn't set
3305 * Otherwise, returns ok.
3307 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3308 struct qed_ptt *p_ptt,
3312 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3313 * the specified buffer.
3315 * @param p_hwfn - HW device data
3316 * @param p_ptt - Ptt window used for writing the registers.
3317 * @param dump_buf - Pointer to write the reg fifo data into.
3318 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3319 * @param num_dumped_dwords - OUT: number of dumped dwords.
3321 * @return error if one of the following holds:
3322 * - the version wasn't set
3323 * - the specified buffer is too small
3324 * - DMAE transaction failed
3325 * Otherwise, returns ok.
3327 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3328 struct qed_ptt *p_ptt,
3330 u32 buf_size_in_dwords,
3331 u32 *num_dumped_dwords);
3334 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3335 * for the IGU fifo results.
3337 * @param p_hwfn - HW device data
3338 * @param p_ptt - Ptt window used for writing the registers.
3339 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3342 * @return error if one of the following holds:
3343 * - the version wasn't set
3344 * Otherwise, returns ok.
3346 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3347 struct qed_ptt *p_ptt,
3351 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3352 * the specified buffer.
3354 * @param p_hwfn - HW device data
3355 * @param p_ptt - Ptt window used for writing the registers.
3356 * @param dump_buf - Pointer to write the IGU fifo data into.
3357 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3358 * @param num_dumped_dwords - OUT: number of dumped dwords.
3360 * @return error if one of the following holds:
3361 * - the version wasn't set
3362 * - the specified buffer is too small
3363 * - DMAE transaction failed
3364 * Otherwise, returns ok.
3366 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3367 struct qed_ptt *p_ptt,
3369 u32 buf_size_in_dwords,
3370 u32 *num_dumped_dwords);
3373 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3374 * buffer size for protection override window results.
3376 * @param p_hwfn - HW device data
3377 * @param p_ptt - Ptt window used for writing the registers.
3378 * @param buf_size - OUT: required buffer size (in dwords) for protection
3381 * @return error if one of the following holds:
3382 * - the version wasn't set
3383 * Otherwise, returns ok.
3386 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3387 struct qed_ptt *p_ptt,
3390 * @brief qed_dbg_protection_override_dump - Reads protection override window
3391 * entries and writes the results into the specified buffer.
3393 * @param p_hwfn - HW device data
3394 * @param p_ptt - Ptt window used for writing the registers.
3395 * @param dump_buf - Pointer to write the protection override data into.
3396 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3397 * @param num_dumped_dwords - OUT: number of dumped dwords.
3399 * @return error if one of the following holds:
3400 * - the version wasn't set
3401 * - the specified buffer is too small
3402 * - DMAE transaction failed
3403 * Otherwise, returns ok.
3405 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3406 struct qed_ptt *p_ptt,
3408 u32 buf_size_in_dwords,
3409 u32 *num_dumped_dwords);
3411 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3412 * size for FW Asserts results.
3414 * @param p_hwfn - HW device data
3415 * @param p_ptt - Ptt window used for writing the registers.
3416 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3418 * @return error if one of the following holds:
3419 * - the version wasn't set
3420 * Otherwise, returns ok.
3422 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3423 struct qed_ptt *p_ptt,
3426 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3427 * into the specified buffer.
3429 * @param p_hwfn - HW device data
3430 * @param p_ptt - Ptt window used for writing the registers.
3431 * @param dump_buf - Pointer to write the FW Asserts data into.
3432 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3433 * @param num_dumped_dwords - OUT: number of dumped dwords.
3435 * @return error if one of the following holds:
3436 * - the version wasn't set
3437 * - the specified buffer is too small
3438 * Otherwise, returns ok.
3440 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3441 struct qed_ptt *p_ptt,
3443 u32 buf_size_in_dwords,
3444 u32 *num_dumped_dwords);
3447 * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3448 * block and type, and writes the results into the specified buffer.
3450 * @param p_hwfn - HW device data
3451 * @param p_ptt - Ptt window used for writing the registers.
3452 * @param block - Block ID.
3453 * @param attn_type - Attention type.
3454 * @param clear_status - Indicates if the attention status should be cleared.
3455 * @param results - OUT: Pointer to write the read results into
3457 * @return error if one of the following holds:
3458 * - the version wasn't set
3459 * Otherwise, returns ok.
3461 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3462 struct qed_ptt *p_ptt,
3463 enum block_id block,
3464 enum dbg_attn_type attn_type,
3466 struct dbg_attn_block_result *results);
3469 * @brief qed_dbg_print_attn - Prints attention registers values in the
3470 * specified results struct.
3473 * @param results - Pointer to the attention read results
3475 * @return error if one of the following holds:
3476 * - the version wasn't set
3477 * Otherwise, returns ok.
3479 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3480 struct dbg_attn_block_result *results);
3482 /******************************* Data Types **********************************/
3484 struct mcp_trace_format {
3486 #define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff
3487 #define MCP_TRACE_FORMAT_MODULE_SHIFT 0
3488 #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000
3489 #define MCP_TRACE_FORMAT_LEVEL_SHIFT 16
3490 #define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000
3491 #define MCP_TRACE_FORMAT_P1_SIZE_SHIFT 18
3492 #define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000
3493 #define MCP_TRACE_FORMAT_P2_SIZE_SHIFT 20
3494 #define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000
3495 #define MCP_TRACE_FORMAT_P3_SIZE_SHIFT 22
3496 #define MCP_TRACE_FORMAT_LEN_MASK 0xff000000
3497 #define MCP_TRACE_FORMAT_LEN_SHIFT 24
3501 /******************************** Constants **********************************/
3503 #define MAX_NAME_LEN 16
3505 /***************************** Public Functions *******************************/
3508 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3511 * @param bin_ptr - a pointer to the binary data with debug arrays.
3513 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
3516 * @brief qed_dbg_alloc_user_data - Allocates user debug data.
3518 * @param p_hwfn - HW device data
3520 enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn);
3523 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3525 * @param status - a debug status code.
3527 * @return a string for the specified status
3529 const char *qed_dbg_get_status_str(enum dbg_status status);
3532 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3533 * for idle check results (in bytes).
3535 * @param p_hwfn - HW device data
3536 * @param dump_buf - idle check dump buffer.
3537 * @param num_dumped_dwords - number of dwords that were dumped.
3538 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3541 * @return error if the parsing fails, ok otherwise.
3543 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3545 u32 num_dumped_dwords,
3546 u32 *results_buf_size);
3548 * @brief qed_print_idle_chk_results - Prints idle check results
3550 * @param p_hwfn - HW device data
3551 * @param dump_buf - idle check dump buffer.
3552 * @param num_dumped_dwords - number of dwords that were dumped.
3553 * @param results_buf - buffer for printing the idle check results.
3554 * @param num_errors - OUT: number of errors found in idle check.
3555 * @param num_warnings - OUT: number of warnings found in idle check.
3557 * @return error if the parsing fails, ok otherwise.
3559 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3561 u32 num_dumped_dwords,
3567 * @brief qed_dbg_mcp_trace_set_meta_data - Sets the MCP Trace meta data.
3569 * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3572 * @param data - pointer to MCP Trace meta data
3573 * @param size - size of MCP Trace meta data in dwords
3575 void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
3576 const u32 *meta_buf);
3579 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3580 * for MCP Trace results (in bytes).
3582 * @param p_hwfn - HW device data
3583 * @param dump_buf - MCP Trace dump buffer.
3584 * @param num_dumped_dwords - number of dwords that were dumped.
3585 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3588 * @return error if the parsing fails, ok otherwise.
3590 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3592 u32 num_dumped_dwords,
3593 u32 *results_buf_size);
3596 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3598 * @param p_hwfn - HW device data
3599 * @param dump_buf - mcp trace dump buffer, starting from the header.
3600 * @param num_dumped_dwords - number of dwords that were dumped.
3601 * @param results_buf - buffer for printing the mcp trace results.
3603 * @return error if the parsing fails, ok otherwise.
3605 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3607 u32 num_dumped_dwords,
3611 * @brief qed_print_mcp_trace_results_cont - Prints MCP Trace results, and
3612 * keeps the MCP trace meta data allocated, to support continuous MCP Trace
3613 * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should
3614 * be called to free the meta data.
3616 * @param p_hwfn - HW device data
3617 * @param dump_buf - mcp trace dump buffer, starting from the header.
3618 * @param results_buf - buffer for printing the mcp trace results.
3620 * @return error if the parsing fails, ok otherwise.
3622 enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
3627 * @brief print_mcp_trace_line - Prints MCP Trace results for a single line
3629 * @param p_hwfn - HW device data
3630 * @param dump_buf - mcp trace dump buffer, starting from the header.
3631 * @param num_dumped_bytes - number of bytes that were dumped.
3632 * @param results_buf - buffer for printing the mcp trace results.
3634 * @return error if the parsing fails, ok otherwise.
3636 enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
3638 u32 num_dumped_bytes,
3642 * @brief mcp_trace_free_meta_data - Frees the MCP Trace meta data.
3643 * Should be called after continuous MCP Trace parsing.
3645 * @param p_hwfn - HW device data
3647 void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn);
3650 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3651 * for reg_fifo results (in bytes).
3653 * @param p_hwfn - HW device data
3654 * @param dump_buf - reg fifo dump buffer.
3655 * @param num_dumped_dwords - number of dwords that were dumped.
3656 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3659 * @return error if the parsing fails, ok otherwise.
3661 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3663 u32 num_dumped_dwords,
3664 u32 *results_buf_size);
3667 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3669 * @param p_hwfn - HW device data
3670 * @param dump_buf - reg fifo dump buffer, starting from the header.
3671 * @param num_dumped_dwords - number of dwords that were dumped.
3672 * @param results_buf - buffer for printing the reg fifo results.
3674 * @return error if the parsing fails, ok otherwise.
3676 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3678 u32 num_dumped_dwords,
3682 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3683 * for igu_fifo results (in bytes).
3685 * @param p_hwfn - HW device data
3686 * @param dump_buf - IGU fifo dump buffer.
3687 * @param num_dumped_dwords - number of dwords that were dumped.
3688 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3691 * @return error if the parsing fails, ok otherwise.
3693 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3695 u32 num_dumped_dwords,
3696 u32 *results_buf_size);
3699 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3701 * @param p_hwfn - HW device data
3702 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3703 * @param num_dumped_dwords - number of dwords that were dumped.
3704 * @param results_buf - buffer for printing the IGU fifo results.
3706 * @return error if the parsing fails, ok otherwise.
3708 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3710 u32 num_dumped_dwords,
3714 * @brief qed_get_protection_override_results_buf_size - Returns the required
3715 * buffer size for protection override results (in bytes).
3717 * @param p_hwfn - HW device data
3718 * @param dump_buf - protection override dump buffer.
3719 * @param num_dumped_dwords - number of dwords that were dumped.
3720 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3723 * @return error if the parsing fails, ok otherwise.
3726 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3728 u32 num_dumped_dwords,
3729 u32 *results_buf_size);
3732 * @brief qed_print_protection_override_results - Prints protection override
3735 * @param p_hwfn - HW device data
3736 * @param dump_buf - protection override dump buffer, starting from the header.
3737 * @param num_dumped_dwords - number of dwords that were dumped.
3738 * @param results_buf - buffer for printing the reg fifo results.
3740 * @return error if the parsing fails, ok otherwise.
3742 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3744 u32 num_dumped_dwords,
3748 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3749 * for FW Asserts results (in bytes).
3751 * @param p_hwfn - HW device data
3752 * @param dump_buf - FW Asserts dump buffer.
3753 * @param num_dumped_dwords - number of dwords that were dumped.
3754 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3757 * @return error if the parsing fails, ok otherwise.
3759 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3761 u32 num_dumped_dwords,
3762 u32 *results_buf_size);
3765 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3767 * @param p_hwfn - HW device data
3768 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3769 * @param num_dumped_dwords - number of dwords that were dumped.
3770 * @param results_buf - buffer for printing the FW Asserts results.
3772 * @return error if the parsing fails, ok otherwise.
3774 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3776 u32 num_dumped_dwords,
3780 * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3781 * the specified results struct.
3783 * @param p_hwfn - HW device data
3784 * @param results - Pointer to the attention read results
3786 * @return error if one of the following holds:
3787 * - the version wasn't set
3788 * Otherwise, returns ok.
3790 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3791 struct dbg_attn_block_result *results);
3793 /* Debug Bus blocks */
3794 static const u32 dbg_bus_blocks[] = {
3795 0x0000000f, /* grc, bb, 15 lines */
3796 0x0000000f, /* grc, k2, 15 lines */
3798 0x00000000, /* miscs, bb, 0 lines */
3799 0x00000000, /* miscs, k2, 0 lines */
3801 0x00000000, /* misc, bb, 0 lines */
3802 0x00000000, /* misc, k2, 0 lines */
3804 0x00000000, /* dbu, bb, 0 lines */
3805 0x00000000, /* dbu, k2, 0 lines */
3807 0x000f0127, /* pglue_b, bb, 39 lines */
3808 0x0036012a, /* pglue_b, k2, 42 lines */
3810 0x00000000, /* cnig, bb, 0 lines */
3811 0x00120102, /* cnig, k2, 2 lines */
3813 0x00000000, /* cpmu, bb, 0 lines */
3814 0x00000000, /* cpmu, k2, 0 lines */
3816 0x00000001, /* ncsi, bb, 1 lines */
3817 0x00000001, /* ncsi, k2, 1 lines */
3819 0x00000000, /* opte, bb, 0 lines */
3820 0x00000000, /* opte, k2, 0 lines */
3822 0x00600085, /* bmb, bb, 133 lines */
3823 0x00600085, /* bmb, k2, 133 lines */
3825 0x00000000, /* pcie, bb, 0 lines */
3826 0x00e50033, /* pcie, k2, 51 lines */
3828 0x00000000, /* mcp, bb, 0 lines */
3829 0x00000000, /* mcp, k2, 0 lines */
3831 0x01180009, /* mcp2, bb, 9 lines */
3832 0x01180009, /* mcp2, k2, 9 lines */
3834 0x01210104, /* pswhst, bb, 4 lines */
3835 0x01210104, /* pswhst, k2, 4 lines */
3837 0x01250103, /* pswhst2, bb, 3 lines */
3838 0x01250103, /* pswhst2, k2, 3 lines */
3840 0x00340101, /* pswrd, bb, 1 lines */
3841 0x00340101, /* pswrd, k2, 1 lines */
3843 0x01280119, /* pswrd2, bb, 25 lines */
3844 0x01280119, /* pswrd2, k2, 25 lines */
3846 0x01410109, /* pswwr, bb, 9 lines */
3847 0x01410109, /* pswwr, k2, 9 lines */
3849 0x00000000, /* pswwr2, bb, 0 lines */
3850 0x00000000, /* pswwr2, k2, 0 lines */
3852 0x001c0001, /* pswrq, bb, 1 lines */
3853 0x001c0001, /* pswrq, k2, 1 lines */
3855 0x014a0015, /* pswrq2, bb, 21 lines */
3856 0x014a0015, /* pswrq2, k2, 21 lines */
3858 0x00000000, /* pglcs, bb, 0 lines */
3859 0x00120006, /* pglcs, k2, 6 lines */
3861 0x00100001, /* dmae, bb, 1 lines */
3862 0x00100001, /* dmae, k2, 1 lines */
3864 0x015f0105, /* ptu, bb, 5 lines */
3865 0x015f0105, /* ptu, k2, 5 lines */
3867 0x01640120, /* tcm, bb, 32 lines */
3868 0x01640120, /* tcm, k2, 32 lines */
3870 0x01640120, /* mcm, bb, 32 lines */
3871 0x01640120, /* mcm, k2, 32 lines */
3873 0x01640120, /* ucm, bb, 32 lines */
3874 0x01640120, /* ucm, k2, 32 lines */
3876 0x01640120, /* xcm, bb, 32 lines */
3877 0x01640120, /* xcm, k2, 32 lines */
3879 0x01640120, /* ycm, bb, 32 lines */
3880 0x01640120, /* ycm, k2, 32 lines */
3882 0x01640120, /* pcm, bb, 32 lines */
3883 0x01640120, /* pcm, k2, 32 lines */
3885 0x01840062, /* qm, bb, 98 lines */
3886 0x01840062, /* qm, k2, 98 lines */
3888 0x01e60021, /* tm, bb, 33 lines */
3889 0x01e60021, /* tm, k2, 33 lines */
3891 0x02070107, /* dorq, bb, 7 lines */
3892 0x02070107, /* dorq, k2, 7 lines */
3894 0x00600185, /* brb, bb, 133 lines */
3895 0x00600185, /* brb, k2, 133 lines */
3897 0x020e0019, /* src, bb, 25 lines */
3898 0x020c001a, /* src, k2, 26 lines */
3900 0x02270104, /* prs, bb, 4 lines */
3901 0x02270104, /* prs, k2, 4 lines */
3903 0x022b0133, /* tsdm, bb, 51 lines */
3904 0x022b0133, /* tsdm, k2, 51 lines */
3906 0x022b0133, /* msdm, bb, 51 lines */
3907 0x022b0133, /* msdm, k2, 51 lines */
3909 0x022b0133, /* usdm, bb, 51 lines */
3910 0x022b0133, /* usdm, k2, 51 lines */
3912 0x022b0133, /* xsdm, bb, 51 lines */
3913 0x022b0133, /* xsdm, k2, 51 lines */
3915 0x022b0133, /* ysdm, bb, 51 lines */
3916 0x022b0133, /* ysdm, k2, 51 lines */
3918 0x022b0133, /* psdm, bb, 51 lines */
3919 0x022b0133, /* psdm, k2, 51 lines */
3921 0x025e010c, /* tsem, bb, 12 lines */
3922 0x025e010c, /* tsem, k2, 12 lines */
3924 0x025e010c, /* msem, bb, 12 lines */
3925 0x025e010c, /* msem, k2, 12 lines */
3927 0x025e010c, /* usem, bb, 12 lines */
3928 0x025e010c, /* usem, k2, 12 lines */
3930 0x025e010c, /* xsem, bb, 12 lines */
3931 0x025e010c, /* xsem, k2, 12 lines */
3933 0x025e010c, /* ysem, bb, 12 lines */
3934 0x025e010c, /* ysem, k2, 12 lines */
3936 0x025e010c, /* psem, bb, 12 lines */
3937 0x025e010c, /* psem, k2, 12 lines */
3939 0x026a000d, /* rss, bb, 13 lines */
3940 0x026a000d, /* rss, k2, 13 lines */
3942 0x02770106, /* tmld, bb, 6 lines */
3943 0x02770106, /* tmld, k2, 6 lines */
3945 0x027d0106, /* muld, bb, 6 lines */
3946 0x027d0106, /* muld, k2, 6 lines */
3948 0x02770005, /* yuld, bb, 5 lines */
3949 0x02770005, /* yuld, k2, 5 lines */
3951 0x02830107, /* xyld, bb, 7 lines */
3952 0x027d0107, /* xyld, k2, 7 lines */
3954 0x00000000, /* ptld, bb, 0 lines */
3955 0x00000000, /* ptld, k2, 0 lines */
3957 0x00000000, /* ypld, bb, 0 lines */
3958 0x00000000, /* ypld, k2, 0 lines */
3960 0x028a010e, /* prm, bb, 14 lines */
3961 0x02980110, /* prm, k2, 16 lines */
3963 0x02a8000d, /* pbf_pb1, bb, 13 lines */
3964 0x02a8000d, /* pbf_pb1, k2, 13 lines */
3966 0x02a8000d, /* pbf_pb2, bb, 13 lines */
3967 0x02a8000d, /* pbf_pb2, k2, 13 lines */
3969 0x02a8000d, /* rpb, bb, 13 lines */
3970 0x02a8000d, /* rpb, k2, 13 lines */
3972 0x00600185, /* btb, bb, 133 lines */
3973 0x00600185, /* btb, k2, 133 lines */
3975 0x02b50117, /* pbf, bb, 23 lines */
3976 0x02b50117, /* pbf, k2, 23 lines */
3978 0x02cc0006, /* rdif, bb, 6 lines */
3979 0x02cc0006, /* rdif, k2, 6 lines */
3981 0x02d20006, /* tdif, bb, 6 lines */
3982 0x02d20006, /* tdif, k2, 6 lines */
3984 0x02d80003, /* cdu, bb, 3 lines */
3985 0x02db000e, /* cdu, k2, 14 lines */
3987 0x02e9010d, /* ccfc, bb, 13 lines */
3988 0x02f60117, /* ccfc, k2, 23 lines */
3990 0x02e9010d, /* tcfc, bb, 13 lines */
3991 0x02f60117, /* tcfc, k2, 23 lines */
3993 0x030d0133, /* igu, bb, 51 lines */
3994 0x030d0133, /* igu, k2, 51 lines */
3996 0x03400106, /* cau, bb, 6 lines */
3997 0x03400106, /* cau, k2, 6 lines */
3999 0x00000000, /* rgfs, bb, 0 lines */
4000 0x00000000, /* rgfs, k2, 0 lines */
4002 0x00000000, /* rgsrc, bb, 0 lines */
4003 0x00000000, /* rgsrc, k2, 0 lines */
4005 0x00000000, /* tgfs, bb, 0 lines */
4006 0x00000000, /* tgfs, k2, 0 lines */
4008 0x00000000, /* tgsrc, bb, 0 lines */
4009 0x00000000, /* tgsrc, k2, 0 lines */
4011 0x00000000, /* umac, bb, 0 lines */
4012 0x00120006, /* umac, k2, 6 lines */
4014 0x00000000, /* xmac, bb, 0 lines */
4015 0x00000000, /* xmac, k2, 0 lines */
4017 0x00000000, /* dbg, bb, 0 lines */
4018 0x00000000, /* dbg, k2, 0 lines */
4020 0x0346012b, /* nig, bb, 43 lines */
4021 0x0346011d, /* nig, k2, 29 lines */
4023 0x00000000, /* wol, bb, 0 lines */
4024 0x001c0002, /* wol, k2, 2 lines */
4026 0x00000000, /* bmbn, bb, 0 lines */
4027 0x00210008, /* bmbn, k2, 8 lines */
4029 0x00000000, /* ipc, bb, 0 lines */
4030 0x00000000, /* ipc, k2, 0 lines */
4032 0x00000000, /* nwm, bb, 0 lines */
4033 0x0371000b, /* nwm, k2, 11 lines */
4035 0x00000000, /* nws, bb, 0 lines */
4036 0x037c0009, /* nws, k2, 9 lines */
4038 0x00000000, /* ms, bb, 0 lines */
4039 0x00120004, /* ms, k2, 4 lines */
4041 0x00000000, /* phy_pcie, bb, 0 lines */
4042 0x00e5001a, /* phy_pcie, k2, 26 lines */
4044 0x00000000, /* led, bb, 0 lines */
4045 0x00000000, /* led, k2, 0 lines */
4047 0x00000000, /* avs_wrap, bb, 0 lines */
4048 0x00000000, /* avs_wrap, k2, 0 lines */
4050 0x00000000, /* bar0_map, bb, 0 lines */
4051 0x00000000, /* bar0_map, k2, 0 lines */
4053 0x00000000, /* bar0_map, bb, 0 lines */
4054 0x00000000, /* bar0_map, k2, 0 lines */
4059 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
4062 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
4065 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
4068 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
4071 #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
4074 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
4077 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
4080 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
4083 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
4086 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
4089 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
4091 * Returns the required host memory size in 4KB units.
4092 * Must be called before all QM init HSI functions.
4094 * @param num_pf_cids - number of connections used by this PF
4095 * @param num_vf_cids - number of connections used by VFs of this PF
4096 * @param num_tids - number of tasks used by this PF
4097 * @param num_pf_pqs - number of PQs used by this PF
4098 * @param num_vf_pqs - number of PQs used by VFs of this PF
4100 * @return The required host memory size in 4KB units.
4102 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
4104 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
4106 struct qed_qm_common_rt_init_params {
4107 u8 max_ports_per_engine;
4108 u8 max_phys_tcs_per_port;
4113 struct init_qm_port_params *port_params;
4116 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
4117 struct qed_qm_common_rt_init_params *p_params);
4119 struct qed_qm_pf_rt_init_params {
4122 u8 max_phys_tcs_per_port;
4134 struct init_qm_pq_params *pq_params;
4135 struct init_qm_vport_params *vport_params;
4138 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
4139 struct qed_ptt *p_ptt,
4140 struct qed_qm_pf_rt_init_params *p_params);
4143 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
4146 * @param p_ptt - ptt window used for writing the registers
4147 * @param pf_id - PF ID
4148 * @param pf_wfq - WFQ weight. Must be non-zero.
4150 * @return 0 on success, -1 on error.
4152 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
4153 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
4156 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
4159 * @param p_ptt - ptt window used for writing the registers
4160 * @param pf_id - PF ID
4161 * @param pf_rl - rate limit in Mb/sec units
4163 * @return 0 on success, -1 on error.
4165 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
4166 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
4169 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
4172 * @param p_ptt - ptt window used for writing the registers
4173 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
4174 * with the VPORT for each TC. This array is filled by
4176 * @param vport_wfq - WFQ weight. Must be non-zero.
4178 * @return 0 on success, -1 on error.
4180 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
4181 struct qed_ptt *p_ptt,
4182 u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq);
4185 * @brief qed_init_global_rl - Initializes the rate limit of the specified
4189 * @param p_ptt - ptt window used for writing the registers
4190 * @param rl_id - RL ID
4191 * @param rate_limit - rate limit in Mb/sec units
4193 * @return 0 on success, -1 on error.
4195 int qed_init_global_rl(struct qed_hwfn *p_hwfn,
4196 struct qed_ptt *p_ptt,
4197 u16 rl_id, u32 rate_limit);
4200 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
4204 * @param is_release_cmd - true for release, false for stop.
4205 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
4206 * @param start_pq - first PQ ID to stop
4207 * @param num_pqs - Number of PQs to stop, starting from start_pq.
4209 * @return bool, true if successful, false if timeout occurred while waiting for
4212 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
4213 struct qed_ptt *p_ptt,
4214 bool is_release_cmd,
4215 bool is_tx_pq, u16 start_pq, u16 num_pqs);
4218 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
4221 * @param p_ptt - ptt window used for writing the registers.
4222 * @param dest_port - vxlan destination udp port.
4224 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
4225 struct qed_ptt *p_ptt, u16 dest_port);
4228 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
4231 * @param p_ptt - ptt window used for writing the registers.
4232 * @param vxlan_enable - vxlan enable flag.
4234 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
4235 struct qed_ptt *p_ptt, bool vxlan_enable);
4238 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
4241 * @param p_ptt - ptt window used for writing the registers.
4242 * @param eth_gre_enable - eth GRE enable enable flag.
4243 * @param ip_gre_enable - IP GRE enable enable flag.
4245 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
4246 struct qed_ptt *p_ptt,
4247 bool eth_gre_enable, bool ip_gre_enable);
4250 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
4253 * @param p_ptt - ptt window used for writing the registers.
4254 * @param dest_port - geneve destination udp port.
4256 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
4257 struct qed_ptt *p_ptt, u16 dest_port);
4260 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
4262 * @param p_ptt - ptt window used for writing the registers.
4263 * @param eth_geneve_enable - eth GENEVE enable enable flag.
4264 * @param ip_geneve_enable - IP GENEVE enable enable flag.
4266 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
4267 struct qed_ptt *p_ptt,
4268 bool eth_geneve_enable, bool ip_geneve_enable);
4270 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
4271 struct qed_ptt *p_ptt, bool enable);
4274 * @brief qed_gft_disable - Disable GFT
4277 * @param p_ptt - ptt window used for writing the registers.
4278 * @param pf_id - pf on which to disable GFT.
4280 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
4283 * @brief qed_gft_config - Enable and configure HW for GFT
4285 * @param p_hwfn - HW device data
4286 * @param p_ptt - ptt window used for writing the registers.
4287 * @param pf_id - pf on which to enable GFT.
4288 * @param tcp - set profile tcp packets.
4289 * @param udp - set profile udp packet.
4290 * @param ipv4 - set profile ipv4 packet.
4291 * @param ipv6 - set profile ipv6 packet.
4292 * @param profile_type - define packet same fields. Use enum gft_profile_type.
4294 void qed_gft_config(struct qed_hwfn *p_hwfn,
4295 struct qed_ptt *p_ptt,
4299 bool ipv4, bool ipv6, enum gft_profile_type profile_type);
4302 * @brief qed_enable_context_validation - Enable and configure context
4306 * @param p_ptt - ptt window used for writing the registers.
4308 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
4309 struct qed_ptt *p_ptt);
4312 * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
4315 * @param p_ctx_mem - pointer to context memory.
4316 * @param ctx_size - context size.
4317 * @param ctx_type - context type.
4318 * @param cid - context cid.
4320 void qed_calc_session_ctx_validation(void *p_ctx_mem,
4321 u16 ctx_size, u8 ctx_type, u32 cid);
4324 * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
4327 * @param p_ctx_mem - pointer to context memory.
4328 * @param ctx_size - context size.
4329 * @param ctx_type - context type.
4330 * @param tid - context tid.
4332 void qed_calc_task_ctx_validation(void *p_ctx_mem,
4333 u16 ctx_size, u8 ctx_type, u32 tid);
4336 * @brief qed_memset_session_ctx - Memset session context to 0 while
4337 * preserving validation bytes.
4340 * @param p_ctx_mem - pointer to context memory.
4341 * @param ctx_size - size to initialzie.
4342 * @param ctx_type - context type.
4344 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4347 * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4350 * @param p_ctx_mem - pointer to context memory.
4351 * @param ctx_size - size to initialzie.
4352 * @param ctx_type - context type.
4354 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4356 #define NUM_STORMS 6
4359 * @brief qed_set_rdma_error_level - Sets the RDMA assert level.
4360 * If the severity of the error will be
4361 * above the level, the FW will assert.
4362 * @param p_hwfn - HW device data
4363 * @param p_ptt - ptt window used for writing the registers
4364 * @param assert_level - An array of assert levels for each storm.
4367 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
4368 struct qed_ptt *p_ptt,
4369 u8 assert_level[NUM_STORMS]);
4371 * @brief qed_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory.
4373 * @param p_hwfn - HW device data
4374 * @param fw_overlay_in_buf - the input FW overlay buffer.
4375 * @param buf_size - the size of the input FW overlay buffer in bytes.
4376 * must be aligned to dwords.
4377 * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory.
4379 * @return a pointer to the allocated overlays memory,
4380 * or NULL in case of failures.
4382 struct phys_mem_desc *
4383 qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
4384 const u32 * const fw_overlay_in_buf,
4385 u32 buf_size_in_bytes);
4388 * @brief qed_fw_overlay_init_ram - Initializes the FW overlay RAM.
4390 * @param p_hwfn - HW device data.
4391 * @param p_ptt - ptt window used for writing the registers.
4392 * @param fw_overlay_mem - the allocated FW overlay memory.
4394 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
4395 struct qed_ptt *p_ptt,
4396 struct phys_mem_desc *fw_overlay_mem);
4399 * @brief qed_fw_overlay_mem_free - Frees the FW overlay memory.
4401 * @param p_hwfn - HW device data.
4402 * @param fw_overlay_mem - the allocated FW overlay memory to free.
4404 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
4405 struct phys_mem_desc *fw_overlay_mem);
4407 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4408 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
4409 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
4411 /* Tstorm port statistics */
4412 #define TSTORM_PORT_STAT_OFFSET(port_id) \
4413 (IRO[1].base + ((port_id) * IRO[1].m1))
4414 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
4416 /* Tstorm ll2 port statistics */
4417 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
4418 (IRO[2].base + ((port_id) * IRO[2].m1))
4419 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
4421 /* Ustorm VF-PF Channel ready flag */
4422 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
4423 (IRO[3].base + ((vf_id) * IRO[3].m1))
4424 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
4426 /* Ustorm Final flr cleanup ack */
4427 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
4428 (IRO[4].base + ((pf_id) * IRO[4].m1))
4429 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
4431 /* Ustorm Event ring consumer */
4432 #define USTORM_EQE_CONS_OFFSET(pf_id) \
4433 (IRO[5].base + ((pf_id) * IRO[5].m1))
4434 #define USTORM_EQE_CONS_SIZE (IRO[5].size)
4436 /* Ustorm eth queue zone */
4437 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
4438 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4439 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
4441 /* Ustorm Common Queue ring consumer */
4442 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
4443 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4444 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
4446 /* Xstorm common PQ info */
4447 #define XSTORM_PQ_INFO_OFFSET(pq_id) \
4448 (IRO[8].base + ((pq_id) * IRO[8].m1))
4449 #define XSTORM_PQ_INFO_SIZE (IRO[8].size)
4451 /* Xstorm Integration Test Data */
4452 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
4453 #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
4455 /* Ystorm Integration Test Data */
4456 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
4457 #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
4459 /* Pstorm Integration Test Data */
4460 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
4461 #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
4463 /* Tstorm Integration Test Data */
4464 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
4465 #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
4467 /* Mstorm Integration Test Data */
4468 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
4469 #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
4471 /* Ustorm Integration Test Data */
4472 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base)
4473 #define USTORM_INTEG_TEST_DATA_SIZE (IRO[14].size)
4475 /* Xstorm overlay buffer host address */
4476 #define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[15].base)
4477 #define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[15].size)
4479 /* Ystorm overlay buffer host address */
4480 #define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[16].base)
4481 #define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[16].size)
4483 /* Pstorm overlay buffer host address */
4484 #define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[17].base)
4485 #define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[17].size)
4487 /* Tstorm overlay buffer host address */
4488 #define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[18].base)
4489 #define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[18].size)
4491 /* Mstorm overlay buffer host address */
4492 #define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[19].base)
4493 #define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[19].size)
4495 /* Ustorm overlay buffer host address */
4496 #define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[20].base)
4497 #define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[20].size)
4499 /* Tstorm producers */
4500 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4501 (IRO[21].base + ((core_rx_queue_id) * IRO[21].m1))
4502 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[21].size)
4504 /* Tstorm LightL2 queue statistics */
4505 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4506 (IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
4507 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[22].size)
4509 /* Ustorm LiteL2 queue statistics */
4510 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4511 (IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
4512 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[23].size)
4514 /* Pstorm LiteL2 queue statistics */
4515 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4516 (IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
4517 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[24].size)
4519 /* Mstorm queue statistics */
4520 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4521 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4522 #define MSTORM_QUEUE_STAT_SIZE (IRO[25].size)
4524 /* TPA agregation timeout in us resolution (on ASIC) */
4525 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[26].base)
4526 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[26].size)
4528 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4531 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4532 (IRO[27].base + ((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
4533 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[27].size)
4535 /* Mstorm ETH PF queues producers */
4536 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4537 (IRO[28].base + ((queue_id) * IRO[28].m1))
4538 #define MSTORM_ETH_PF_PRODS_SIZE (IRO[28].size)
4540 /* Mstorm pf statistics */
4541 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4542 (IRO[29].base + ((pf_id) * IRO[29].m1))
4543 #define MSTORM_ETH_PF_STAT_SIZE (IRO[29].size)
4545 /* Ustorm queue statistics */
4546 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4547 (IRO[30].base + ((stat_counter_id) * IRO[30].m1))
4548 #define USTORM_QUEUE_STAT_SIZE (IRO[30].size)
4550 /* Ustorm pf statistics */
4551 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
4552 (IRO[31].base + ((pf_id) * IRO[31].m1))
4553 #define USTORM_ETH_PF_STAT_SIZE (IRO[31].size)
4555 /* Pstorm queue statistics */
4556 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4557 (IRO[32].base + ((stat_counter_id) * IRO[32].m1))
4558 #define PSTORM_QUEUE_STAT_SIZE (IRO[32].size)
4560 /* Pstorm pf statistics */
4561 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4562 (IRO[33].base + ((pf_id) * IRO[33].m1))
4563 #define PSTORM_ETH_PF_STAT_SIZE (IRO[33].size)
4565 /* Control frame's EthType configuration for TX control frame security */
4566 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
4567 (IRO[34].base + ((eth_type_id) * IRO[34].m1))
4568 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[34].size)
4570 /* Tstorm last parser message */
4571 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[35].base)
4572 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[35].size)
4574 /* Tstorm Eth limit Rx rate */
4575 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
4576 (IRO[36].base + ((pf_id) * IRO[36].m1))
4577 #define ETH_RX_RATE_LIMIT_SIZE (IRO[36].size)
4579 /* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
4580 * Use eth_tstorm_rss_update_data for update
4582 #define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \
4583 (IRO[37].base + ((pf_id) * IRO[37].m1))
4584 #define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[37].size)
4586 /* Xstorm queue zone */
4587 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
4588 (IRO[38].base + ((queue_id) * IRO[38].m1))
4589 #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[38].size)
4591 /* Ystorm cqe producer */
4592 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4593 (IRO[39].base + ((rss_id) * IRO[39].m1))
4594 #define YSTORM_TOE_CQ_PROD_SIZE (IRO[39].size)
4596 /* Ustorm cqe producer */
4597 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4598 (IRO[40].base + ((rss_id) * IRO[40].m1))
4599 #define USTORM_TOE_CQ_PROD_SIZE (IRO[40].size)
4601 /* Ustorm grq producer */
4602 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
4603 (IRO[41].base + ((pf_id) * IRO[41].m1))
4604 #define USTORM_TOE_GRQ_PROD_SIZE (IRO[41].size)
4606 /* Tstorm cmdq-cons of given command queue-id */
4607 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
4608 (IRO[42].base + ((cmdq_queue_id) * IRO[42].m1))
4609 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[42].size)
4611 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4614 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
4615 (IRO[43].base + ((storage_func_id) * IRO[43].m1) + \
4616 ((bdq_id) * IRO[43].m2))
4617 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[43].size)
4619 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
4620 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
4621 (IRO[44].base + ((storage_func_id) * IRO[44].m1) + \
4622 ((bdq_id) * IRO[44].m2))
4623 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[44].size)
4625 /* Tstorm iSCSI RX stats */
4626 #define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4627 (IRO[45].base + ((storage_func_id) * IRO[45].m1))
4628 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[45].size)
4630 /* Mstorm iSCSI RX stats */
4631 #define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4632 (IRO[46].base + ((storage_func_id) * IRO[46].m1))
4633 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[46].size)
4635 /* Ustorm iSCSI RX stats */
4636 #define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4637 (IRO[47].base + ((storage_func_id) * IRO[47].m1))
4638 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[47].size)
4640 /* Xstorm iSCSI TX stats */
4641 #define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4642 (IRO[48].base + ((storage_func_id) * IRO[48].m1))
4643 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[48].size)
4645 /* Ystorm iSCSI TX stats */
4646 #define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4647 (IRO[49].base + ((storage_func_id) * IRO[49].m1))
4648 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[49].size)
4650 /* Pstorm iSCSI TX stats */
4651 #define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4652 (IRO[50].base + ((storage_func_id) * IRO[50].m1))
4653 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[50].size)
4655 /* Tstorm FCoE RX stats */
4656 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
4657 (IRO[51].base + ((pf_id) * IRO[51].m1))
4658 #define TSTORM_FCOE_RX_STATS_SIZE (IRO[51].size)
4660 /* Pstorm FCoE TX stats */
4661 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4662 (IRO[52].base + ((pf_id) * IRO[52].m1))
4663 #define PSTORM_FCOE_TX_STATS_SIZE (IRO[52].size)
4665 /* Pstorm RDMA queue statistics */
4666 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4667 (IRO[53].base + ((rdma_stat_counter_id) * IRO[53].m1))
4668 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[53].size)
4670 /* Tstorm RDMA queue statistics */
4671 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4672 (IRO[54].base + ((rdma_stat_counter_id) * IRO[54].m1))
4673 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[54].size)
4675 /* Xstorm error level for assert */
4676 #define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4677 (IRO[55].base + ((pf_id) * IRO[55].m1))
4678 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[55].size)
4680 /* Ystorm error level for assert */
4681 #define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4682 (IRO[56].base + ((pf_id) * IRO[56].m1))
4683 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[56].size)
4685 /* Pstorm error level for assert */
4686 #define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4687 (IRO[57].base + ((pf_id) * IRO[57].m1))
4688 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[57].size)
4690 /* Tstorm error level for assert */
4691 #define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4692 (IRO[58].base + ((pf_id) * IRO[58].m1))
4693 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[58].size)
4695 /* Mstorm error level for assert */
4696 #define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4697 (IRO[59].base + ((pf_id) * IRO[59].m1))
4698 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[59].size)
4700 /* Ustorm error level for assert */
4701 #define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4702 (IRO[60].base + ((pf_id) * IRO[60].m1))
4703 #define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[60].size)
4705 /* Xstorm iWARP rxmit stats */
4706 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
4707 (IRO[61].base + ((pf_id) * IRO[61].m1))
4708 #define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[61].size)
4710 /* Tstorm RoCE Event Statistics */
4711 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
4712 (IRO[62].base + ((roce_pf_id) * IRO[62].m1))
4713 #define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[62].size)
4715 /* DCQCN Received Statistics */
4716 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id)\
4717 (IRO[63].base + ((roce_pf_id) * IRO[63].m1))
4718 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[63].size)
4720 /* RoCE Error Statistics */
4721 #define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
4722 (IRO[64].base + ((roce_pf_id) * IRO[64].m1))
4723 #define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[64].size)
4725 /* DCQCN Sent Statistics */
4726 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
4727 (IRO[65].base + ((roce_pf_id) * IRO[65].m1))
4728 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[65].size)
4730 /* RoCE CQEs Statistics */
4731 #define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
4732 (IRO[66].base + ((roce_pf_id) * IRO[66].m1))
4733 #define USTORM_ROCE_CQE_STATS_SIZE (IRO[66].size)
4736 static const u32 iro_arr[] = {
4737 0x00000000, 0x00000000, 0x00080000,
4738 0x00003288, 0x00000088, 0x00880000,
4739 0x000058e8, 0x00000020, 0x00200000,
4740 0x00000b00, 0x00000008, 0x00040000,
4741 0x00000a80, 0x00000008, 0x00040000,
4742 0x00000000, 0x00000008, 0x00020000,
4743 0x00000080, 0x00000008, 0x00040000,
4744 0x00000084, 0x00000008, 0x00020000,
4745 0x00005718, 0x00000004, 0x00040000,
4746 0x00004dd0, 0x00000000, 0x00780000,
4747 0x00003e40, 0x00000000, 0x00780000,
4748 0x00004480, 0x00000000, 0x00780000,
4749 0x00003210, 0x00000000, 0x00780000,
4750 0x00003b50, 0x00000000, 0x00780000,
4751 0x00007f58, 0x00000000, 0x00780000,
4752 0x00005f58, 0x00000000, 0x00080000,
4753 0x00007100, 0x00000000, 0x00080000,
4754 0x0000aea0, 0x00000000, 0x00080000,
4755 0x00004398, 0x00000000, 0x00080000,
4756 0x0000a5a0, 0x00000000, 0x00080000,
4757 0x0000bde8, 0x00000000, 0x00080000,
4758 0x00000020, 0x00000004, 0x00040000,
4759 0x000056c8, 0x00000010, 0x00100000,
4760 0x0000c210, 0x00000030, 0x00300000,
4761 0x0000b088, 0x00000038, 0x00380000,
4762 0x00003d20, 0x00000080, 0x00400000,
4763 0x0000bf60, 0x00000000, 0x00040000,
4764 0x00004560, 0x00040080, 0x00040000,
4765 0x000001f8, 0x00000004, 0x00040000,
4766 0x00003d60, 0x00000080, 0x00200000,
4767 0x00008960, 0x00000040, 0x00300000,
4768 0x0000e840, 0x00000060, 0x00600000,
4769 0x00004618, 0x00000080, 0x00380000,
4770 0x00010738, 0x000000c0, 0x00c00000,
4771 0x000001f8, 0x00000002, 0x00020000,
4772 0x0000a2a0, 0x00000000, 0x01080000,
4773 0x0000a3a8, 0x00000008, 0x00080000,
4774 0x000001c0, 0x00000008, 0x00080000,
4775 0x000001f8, 0x00000008, 0x00080000,
4776 0x00000ac0, 0x00000008, 0x00080000,
4777 0x00002578, 0x00000008, 0x00080000,
4778 0x000024f8, 0x00000008, 0x00080000,
4779 0x00000280, 0x00000008, 0x00080000,
4780 0x00000680, 0x00080018, 0x00080000,
4781 0x00000b78, 0x00080018, 0x00020000,
4782 0x0000c640, 0x00000050, 0x003c0000,
4783 0x00012038, 0x00000018, 0x00100000,
4784 0x00011b00, 0x00000040, 0x00180000,
4785 0x000095d0, 0x00000050, 0x00200000,
4786 0x00008b10, 0x00000040, 0x00280000,
4787 0x00011640, 0x00000018, 0x00100000,
4788 0x0000c828, 0x00000048, 0x00380000,
4789 0x00011710, 0x00000020, 0x00200000,
4790 0x00004650, 0x00000080, 0x00100000,
4791 0x00003618, 0x00000010, 0x00100000,
4792 0x0000a968, 0x00000008, 0x00010000,
4793 0x000097a0, 0x00000008, 0x00010000,
4794 0x00011990, 0x00000008, 0x00010000,
4795 0x0000f018, 0x00000008, 0x00010000,
4796 0x00012628, 0x00000008, 0x00010000,
4797 0x00011da8, 0x00000008, 0x00010000,
4798 0x0000aa78, 0x00000030, 0x00100000,
4799 0x0000d768, 0x00000028, 0x00280000,
4800 0x00009a58, 0x00000018, 0x00180000,
4801 0x00009bd8, 0x00000008, 0x00080000,
4802 0x00013a18, 0x00000008, 0x00080000,
4803 0x000126e8, 0x00000018, 0x00180000,
4804 0x0000e608, 0x00500288, 0x00100000,
4805 0x00012970, 0x00000138, 0x00280000,
4808 /* Runtime array offsets */
4809 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
4810 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
4811 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
4812 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
4813 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
4814 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
4815 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
4816 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
4817 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
4818 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
4819 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
4820 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
4821 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
4822 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
4823 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
4824 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
4825 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16
4826 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17
4827 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18
4828 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19
4829 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20
4830 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21
4831 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22
4832 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23
4833 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24
4834 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25
4835 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26
4836 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
4837 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762
4838 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
4839 #define CAU_REG_PI_MEMORY_RT_OFFSET 1498
4840 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
4841 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914
4842 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915
4843 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916
4844 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917
4845 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918
4846 #define PRS_REG_SEARCH_TCP_RT_OFFSET 5919
4847 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920
4848 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921
4849 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922
4850 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923
4851 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924
4852 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925
4853 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926
4854 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927
4855 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928
4856 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929
4857 #define SRC_REG_FIRSTFREE_RT_OFFSET 5930
4858 #define SRC_REG_FIRSTFREE_RT_SIZE 2
4859 #define SRC_REG_LASTFREE_RT_OFFSET 5932
4860 #define SRC_REG_LASTFREE_RT_SIZE 2
4861 #define SRC_REG_COUNTFREE_RT_OFFSET 5934
4862 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935
4863 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936
4864 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937
4865 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938
4866 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939
4867 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940
4868 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941
4869 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942
4870 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943
4871 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944
4872 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945
4873 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946
4874 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947
4875 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948
4876 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949
4877 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950
4878 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951
4879 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952
4880 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953
4881 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954
4882 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955
4883 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956
4884 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957
4885 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958
4886 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959
4887 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960
4888 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961
4889 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962
4890 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963
4891 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964
4892 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965
4893 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966
4894 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967
4895 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
4896 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967
4897 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968
4898 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969
4899 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970
4900 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971
4901 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972
4902 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973
4903 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974
4904 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975
4905 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976
4906 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977
4907 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978
4908 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979
4909 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
4910 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395
4911 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
4912 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907
4913 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908
4914 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909
4915 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910
4916 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911
4917 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912
4918 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913
4919 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914
4920 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915
4921 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916
4922 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917
4923 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918
4924 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919
4925 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920
4926 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921
4927 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922
4928 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923
4929 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924
4930 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925
4931 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926
4932 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927
4933 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928
4934 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929
4935 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930
4936 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931
4937 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932
4938 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933
4939 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934
4940 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935
4941 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936
4942 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937
4943 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938
4944 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939
4945 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940
4946 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941
4947 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942
4948 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943
4949 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944
4950 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945
4951 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946
4952 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947
4953 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948
4954 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949
4955 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950
4956 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951
4957 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952
4958 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953
4959 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954
4960 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955
4961 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956
4962 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957
4963 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958
4964 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959
4965 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960
4966 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961
4967 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962
4968 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963
4969 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964
4970 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965
4971 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966
4972 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967
4973 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968
4974 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969
4975 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970
4976 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971
4977 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972
4978 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973
4979 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974
4980 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
4981 #define QM_REG_PTRTBLOTHER_RT_OFFSET 29102
4982 #define QM_REG_PTRTBLOTHER_RT_SIZE 256
4983 #define QM_REG_VOQCRDLINE_RT_OFFSET 29358
4984 #define QM_REG_VOQCRDLINE_RT_SIZE 20
4985 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378
4986 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
4987 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398
4988 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399
4989 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400
4990 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401
4991 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402
4992 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403
4993 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404
4994 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405
4995 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406
4996 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407
4997 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408
4998 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409
4999 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410
5000 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411
5001 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412
5002 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413
5003 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414
5004 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415
5005 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416
5006 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417
5007 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418
5008 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419
5009 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420
5010 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421
5011 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422
5012 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423
5013 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424
5014 #define QM_REG_PQTX2PF_0_RT_OFFSET 29425
5015 #define QM_REG_PQTX2PF_1_RT_OFFSET 29426
5016 #define QM_REG_PQTX2PF_2_RT_OFFSET 29427
5017 #define QM_REG_PQTX2PF_3_RT_OFFSET 29428
5018 #define QM_REG_PQTX2PF_4_RT_OFFSET 29429
5019 #define QM_REG_PQTX2PF_5_RT_OFFSET 29430
5020 #define QM_REG_PQTX2PF_6_RT_OFFSET 29431
5021 #define QM_REG_PQTX2PF_7_RT_OFFSET 29432
5022 #define QM_REG_PQTX2PF_8_RT_OFFSET 29433
5023 #define QM_REG_PQTX2PF_9_RT_OFFSET 29434
5024 #define QM_REG_PQTX2PF_10_RT_OFFSET 29435
5025 #define QM_REG_PQTX2PF_11_RT_OFFSET 29436
5026 #define QM_REG_PQTX2PF_12_RT_OFFSET 29437
5027 #define QM_REG_PQTX2PF_13_RT_OFFSET 29438
5028 #define QM_REG_PQTX2PF_14_RT_OFFSET 29439
5029 #define QM_REG_PQTX2PF_15_RT_OFFSET 29440
5030 #define QM_REG_PQTX2PF_16_RT_OFFSET 29441
5031 #define QM_REG_PQTX2PF_17_RT_OFFSET 29442
5032 #define QM_REG_PQTX2PF_18_RT_OFFSET 29443
5033 #define QM_REG_PQTX2PF_19_RT_OFFSET 29444
5034 #define QM_REG_PQTX2PF_20_RT_OFFSET 29445
5035 #define QM_REG_PQTX2PF_21_RT_OFFSET 29446
5036 #define QM_REG_PQTX2PF_22_RT_OFFSET 29447
5037 #define QM_REG_PQTX2PF_23_RT_OFFSET 29448
5038 #define QM_REG_PQTX2PF_24_RT_OFFSET 29449
5039 #define QM_REG_PQTX2PF_25_RT_OFFSET 29450
5040 #define QM_REG_PQTX2PF_26_RT_OFFSET 29451
5041 #define QM_REG_PQTX2PF_27_RT_OFFSET 29452
5042 #define QM_REG_PQTX2PF_28_RT_OFFSET 29453
5043 #define QM_REG_PQTX2PF_29_RT_OFFSET 29454
5044 #define QM_REG_PQTX2PF_30_RT_OFFSET 29455
5045 #define QM_REG_PQTX2PF_31_RT_OFFSET 29456
5046 #define QM_REG_PQTX2PF_32_RT_OFFSET 29457
5047 #define QM_REG_PQTX2PF_33_RT_OFFSET 29458
5048 #define QM_REG_PQTX2PF_34_RT_OFFSET 29459
5049 #define QM_REG_PQTX2PF_35_RT_OFFSET 29460
5050 #define QM_REG_PQTX2PF_36_RT_OFFSET 29461
5051 #define QM_REG_PQTX2PF_37_RT_OFFSET 29462
5052 #define QM_REG_PQTX2PF_38_RT_OFFSET 29463
5053 #define QM_REG_PQTX2PF_39_RT_OFFSET 29464
5054 #define QM_REG_PQTX2PF_40_RT_OFFSET 29465
5055 #define QM_REG_PQTX2PF_41_RT_OFFSET 29466
5056 #define QM_REG_PQTX2PF_42_RT_OFFSET 29467
5057 #define QM_REG_PQTX2PF_43_RT_OFFSET 29468
5058 #define QM_REG_PQTX2PF_44_RT_OFFSET 29469
5059 #define QM_REG_PQTX2PF_45_RT_OFFSET 29470
5060 #define QM_REG_PQTX2PF_46_RT_OFFSET 29471
5061 #define QM_REG_PQTX2PF_47_RT_OFFSET 29472
5062 #define QM_REG_PQTX2PF_48_RT_OFFSET 29473
5063 #define QM_REG_PQTX2PF_49_RT_OFFSET 29474
5064 #define QM_REG_PQTX2PF_50_RT_OFFSET 29475
5065 #define QM_REG_PQTX2PF_51_RT_OFFSET 29476
5066 #define QM_REG_PQTX2PF_52_RT_OFFSET 29477
5067 #define QM_REG_PQTX2PF_53_RT_OFFSET 29478
5068 #define QM_REG_PQTX2PF_54_RT_OFFSET 29479
5069 #define QM_REG_PQTX2PF_55_RT_OFFSET 29480
5070 #define QM_REG_PQTX2PF_56_RT_OFFSET 29481
5071 #define QM_REG_PQTX2PF_57_RT_OFFSET 29482
5072 #define QM_REG_PQTX2PF_58_RT_OFFSET 29483
5073 #define QM_REG_PQTX2PF_59_RT_OFFSET 29484
5074 #define QM_REG_PQTX2PF_60_RT_OFFSET 29485
5075 #define QM_REG_PQTX2PF_61_RT_OFFSET 29486
5076 #define QM_REG_PQTX2PF_62_RT_OFFSET 29487
5077 #define QM_REG_PQTX2PF_63_RT_OFFSET 29488
5078 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489
5079 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490
5080 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491
5081 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492
5082 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493
5083 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494
5084 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495
5085 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496
5086 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497
5087 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498
5088 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499
5089 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500
5090 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501
5091 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502
5092 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503
5093 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504
5094 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505
5095 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506
5096 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507
5097 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508
5098 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509
5099 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510
5100 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511
5101 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512
5102 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513
5103 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514
5104 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515
5105 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516
5106 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517
5107 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
5108 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773
5109 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
5110 #define QM_REG_RLGLBLCRD_RT_OFFSET 30029
5111 #define QM_REG_RLGLBLCRD_RT_SIZE 256
5112 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30285
5113 #define QM_REG_RLPFPERIOD_RT_OFFSET 30286
5114 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287
5115 #define QM_REG_RLPFINCVAL_RT_OFFSET 30288
5116 #define QM_REG_RLPFINCVAL_RT_SIZE 16
5117 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304
5118 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
5119 #define QM_REG_RLPFCRD_RT_OFFSET 30320
5120 #define QM_REG_RLPFCRD_RT_SIZE 16
5121 #define QM_REG_RLPFENABLE_RT_OFFSET 30336
5122 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337
5123 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338
5124 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
5125 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354
5126 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
5127 #define QM_REG_WFQPFCRD_RT_OFFSET 30370
5128 #define QM_REG_WFQPFCRD_RT_SIZE 160
5129 #define QM_REG_WFQPFENABLE_RT_OFFSET 30530
5130 #define QM_REG_WFQVPENABLE_RT_OFFSET 30531
5131 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532
5132 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
5133 #define QM_REG_TXPQMAP_RT_OFFSET 31044
5134 #define QM_REG_TXPQMAP_RT_SIZE 512
5135 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556
5136 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
5137 #define QM_REG_WFQVPCRD_RT_OFFSET 32068
5138 #define QM_REG_WFQVPCRD_RT_SIZE 512
5139 #define QM_REG_WFQVPMAP_RT_OFFSET 32580
5140 #define QM_REG_WFQVPMAP_RT_SIZE 512
5141 #define QM_REG_PTRTBLTX_RT_OFFSET 33092
5142 #define QM_REG_PTRTBLTX_RT_SIZE 1024
5143 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34116
5144 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
5145 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34276
5146 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34277
5147 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34278
5148 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34279
5149 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34280
5150 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34281
5151 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34282
5152 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34283
5153 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
5154 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34287
5155 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
5156 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34291
5157 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
5158 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34323
5159 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
5160 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34339
5161 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
5162 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34355
5163 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
5164 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34371
5165 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
5166 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34387
5167 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34388
5168 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
5169 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34396
5170 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34397
5171 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34398
5172 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34399
5173 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34400
5174 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34401
5175 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34402
5176 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34403
5177 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34404
5178 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34405
5179 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34406
5180 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34407
5181 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34408
5182 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34409
5183 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34410
5184 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34411
5185 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34412
5186 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34413
5187 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34414
5188 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34415
5189 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34416
5190 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34417
5191 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34418
5192 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34419
5193 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34420
5194 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34421
5195 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34422
5196 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34423
5197 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34424
5198 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34425
5199 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34426
5200 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34427
5201 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34428
5202 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34429
5203 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34430
5204 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34431
5205 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34432
5206 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34433
5207 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34434
5208 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34435
5209 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34436
5210 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34437
5211 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34438
5212 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34439
5213 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34440
5214 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34441
5215 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34442
5216 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34443
5217 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34444
5218 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34445
5219 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34446
5220 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34447
5221 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34448
5222 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34449
5223 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34450
5224 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34451
5225 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34452
5226 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34453
5227 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34454
5228 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34455
5229 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34456
5230 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34457
5231 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34458
5232 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34459
5233 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34460
5234 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34461
5235 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34462
5236 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34463
5237 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34464
5238 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34465
5239 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34466
5240 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34467
5241 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34468
5242 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34469
5243 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34470
5244 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34471
5246 #define RUNTIME_ARRAY_SIZE 34472
5248 /* Init Callbacks */
5249 #define DMAE_READY_CB 0
5251 /* The eth storm context for the Tstorm */
5252 struct tstorm_eth_conn_st_ctx {
5256 /* The eth storm context for the Pstorm */
5257 struct pstorm_eth_conn_st_ctx {
5261 /* The eth storm context for the Xstorm */
5262 struct xstorm_eth_conn_st_ctx {
5263 __le32 reserved[60];
5266 struct e4_xstorm_eth_conn_ag_ctx {
5270 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5271 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5272 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
5273 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
5274 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
5275 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
5276 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5277 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
5278 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
5279 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
5280 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
5281 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
5282 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
5283 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
5284 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
5285 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
5287 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
5288 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
5289 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
5290 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
5291 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
5292 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
5293 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
5294 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
5295 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
5296 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
5297 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
5298 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
5299 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
5300 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
5301 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
5302 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
5304 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5305 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
5306 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5307 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
5308 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5309 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
5310 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5311 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
5313 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
5314 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
5315 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
5316 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
5317 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
5318 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
5319 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
5320 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
5322 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
5323 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
5324 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
5325 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
5326 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
5327 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
5328 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
5329 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
5331 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
5332 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
5333 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
5334 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
5335 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
5336 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
5337 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
5338 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
5340 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
5341 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
5342 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
5343 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
5344 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
5345 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
5346 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
5347 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
5349 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5350 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5351 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
5352 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
5353 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5354 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
5355 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5356 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
5357 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5358 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
5360 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5361 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
5362 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5363 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
5364 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
5365 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
5366 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
5367 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
5368 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
5369 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
5370 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
5371 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
5372 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
5373 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
5374 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
5375 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
5377 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
5378 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
5379 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
5380 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
5381 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
5382 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
5383 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
5384 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
5385 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
5386 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
5387 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
5388 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
5389 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
5390 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
5391 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
5392 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
5394 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5395 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
5396 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
5397 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
5398 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5399 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
5400 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
5401 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
5402 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5403 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
5404 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
5405 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
5406 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
5407 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
5408 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
5409 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
5411 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
5412 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
5413 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
5414 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
5415 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
5416 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
5417 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5418 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
5419 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
5420 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
5421 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5422 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
5423 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5424 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
5425 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
5426 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
5428 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
5429 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
5430 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
5431 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
5432 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5433 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
5434 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5435 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
5436 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
5437 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
5438 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
5439 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
5440 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
5441 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
5442 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
5443 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
5445 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
5446 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
5447 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
5448 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
5449 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5450 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
5451 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5452 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
5453 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5454 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
5455 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5456 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
5457 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5458 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
5459 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5460 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
5462 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
5463 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
5464 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
5465 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
5466 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
5467 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
5468 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5469 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5470 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
5471 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
5472 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
5473 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
5474 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
5475 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
5478 __le16 e5_reserved1;
5479 __le16 edpm_num_bds;
5482 __le16 updated_qm_pq_id;
5529 /* The eth storm context for the Ystorm */
5530 struct ystorm_eth_conn_st_ctx {
5534 struct e4_ystorm_eth_conn_ag_ctx {
5538 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5539 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5540 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5541 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5542 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
5543 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
5544 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
5545 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
5546 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5547 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5549 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
5550 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
5551 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
5552 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
5553 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5554 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5555 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5556 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
5557 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5558 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
5559 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5560 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
5561 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5562 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
5563 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5564 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
5565 u8 tx_q0_int_coallecing_timeset;
5568 __le32 terminate_spqe;
5570 __le16 tx_bd_cons_upd;
5578 struct e4_tstorm_eth_conn_ag_ctx {
5582 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5583 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5584 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5585 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5586 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
5587 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
5588 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
5589 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
5590 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
5591 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
5592 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
5593 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
5594 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5595 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
5597 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5598 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
5599 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5600 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
5601 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5602 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
5603 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
5604 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
5606 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
5607 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
5608 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
5609 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
5610 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
5611 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
5612 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
5613 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
5615 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
5616 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
5617 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
5618 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
5619 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5620 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
5621 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5622 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
5623 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5624 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
5625 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5626 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
5628 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
5629 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
5630 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
5631 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
5632 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
5633 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
5634 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
5635 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
5636 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
5637 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
5638 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
5639 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
5640 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
5641 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
5642 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5643 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
5645 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5646 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5647 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5648 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
5649 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5650 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
5651 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5652 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
5653 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5654 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5655 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
5656 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
5657 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5658 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5659 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5660 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
5682 struct e4_ustorm_eth_conn_ag_ctx {
5686 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5687 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5688 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5689 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5690 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
5691 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
5692 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
5693 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
5694 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5695 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5697 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5698 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
5699 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
5700 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
5701 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
5702 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
5703 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
5704 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
5706 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
5707 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
5708 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
5709 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
5710 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5711 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5712 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5713 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
5714 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
5715 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
5716 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
5717 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
5718 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
5719 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
5720 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5721 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
5723 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5724 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5725 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5726 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
5727 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5728 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
5729 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5730 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
5731 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5732 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5733 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
5734 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
5735 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5736 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5737 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5738 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
5746 __le32 tx_int_coallecing_timeset;
5747 __le16 tx_drv_bd_cons;
5748 __le16 rx_drv_cqe_cons;
5751 /* The eth storm context for the Ustorm */
5752 struct ustorm_eth_conn_st_ctx {
5753 __le32 reserved[40];
5756 /* The eth storm context for the Mstorm */
5757 struct mstorm_eth_conn_st_ctx {
5761 /* eth connection context */
5762 struct e4_eth_conn_context {
5763 struct tstorm_eth_conn_st_ctx tstorm_st_context;
5764 struct regpair tstorm_st_padding[2];
5765 struct pstorm_eth_conn_st_ctx pstorm_st_context;
5766 struct xstorm_eth_conn_st_ctx xstorm_st_context;
5767 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
5768 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5769 struct ystorm_eth_conn_st_ctx ystorm_st_context;
5770 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5771 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
5772 struct ustorm_eth_conn_st_ctx ustorm_st_context;
5773 struct mstorm_eth_conn_st_ctx mstorm_st_context;
5776 /* Ethernet filter types: mac/vlan/pair */
5777 enum eth_error_code {
5779 ETH_FILTERS_MAC_ADD_FAIL_FULL,
5780 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
5781 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
5782 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
5783 ETH_FILTERS_MAC_DEL_FAIL_NOF,
5784 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
5785 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
5786 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
5787 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
5788 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
5789 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
5790 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
5791 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
5792 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
5793 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
5794 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
5795 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
5796 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
5797 ETH_FILTERS_VNI_ADD_FAIL_FULL,
5798 ETH_FILTERS_VNI_ADD_FAIL_DUP,
5799 ETH_FILTERS_GFT_UPDATE_FAIL,
5800 ETH_RX_QUEUE_FAIL_LOAD_VF_DATA,
5801 ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS,
5802 ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY,
5803 ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS,
5804 ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR,
5805 ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR,
5806 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS,
5807 ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY,
5808 ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR,
5809 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR,
5813 /* Opcodes for the event ring */
5814 enum eth_event_opcode {
5816 ETH_EVENT_VPORT_START,
5817 ETH_EVENT_VPORT_UPDATE,
5818 ETH_EVENT_VPORT_STOP,
5819 ETH_EVENT_TX_QUEUE_START,
5820 ETH_EVENT_TX_QUEUE_STOP,
5821 ETH_EVENT_RX_QUEUE_START,
5822 ETH_EVENT_RX_QUEUE_UPDATE,
5823 ETH_EVENT_RX_QUEUE_STOP,
5824 ETH_EVENT_FILTERS_UPDATE,
5825 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
5826 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
5827 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
5828 ETH_EVENT_RX_ADD_UDP_FILTER,
5829 ETH_EVENT_RX_DELETE_UDP_FILTER,
5830 ETH_EVENT_RX_CREATE_GFT_ACTION,
5831 ETH_EVENT_RX_GFT_UPDATE_FILTER,
5832 ETH_EVENT_TX_QUEUE_UPDATE,
5833 ETH_EVENT_RGFS_ADD_FILTER,
5834 ETH_EVENT_RGFS_DEL_FILTER,
5835 ETH_EVENT_TGFS_ADD_FILTER,
5836 ETH_EVENT_TGFS_DEL_FILTER,
5837 ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST,
5838 MAX_ETH_EVENT_OPCODE
5841 /* Classify rule types in E2/E3 */
5842 enum eth_filter_action {
5843 ETH_FILTER_ACTION_UNUSED,
5844 ETH_FILTER_ACTION_REMOVE,
5845 ETH_FILTER_ACTION_ADD,
5846 ETH_FILTER_ACTION_REMOVE_ALL,
5847 MAX_ETH_FILTER_ACTION
5850 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
5851 struct eth_filter_cmd {
5863 /* $$KEEP_ENDIANNESS$$ */
5864 struct eth_filter_cmd_header {
5872 /* Ethernet filter types: mac/vlan/pair */
5873 enum eth_filter_type {
5874 ETH_FILTER_TYPE_UNUSED,
5875 ETH_FILTER_TYPE_MAC,
5876 ETH_FILTER_TYPE_VLAN,
5877 ETH_FILTER_TYPE_PAIR,
5878 ETH_FILTER_TYPE_INNER_MAC,
5879 ETH_FILTER_TYPE_INNER_VLAN,
5880 ETH_FILTER_TYPE_INNER_PAIR,
5881 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5882 ETH_FILTER_TYPE_MAC_VNI_PAIR,
5883 ETH_FILTER_TYPE_VNI,
5887 /* inner to inner vlan priority translation configurations */
5888 struct eth_in_to_in_pri_map_cfg {
5889 u8 inner_vlan_pri_remap_en;
5891 u8 non_rdma_in_to_in_pri_map[8];
5892 u8 rdma_in_to_in_pri_map[8];
5895 /* Eth IPv4 Fragment Type */
5896 enum eth_ipv4_frag_type {
5898 ETH_IPV4_FIRST_FRAG,
5899 ETH_IPV4_NON_FIRST_FRAG,
5900 MAX_ETH_IPV4_FRAG_TYPE
5903 /* eth IPv4 Fragment Type */
5910 /* Ethernet Ramrod Command IDs */
5911 enum eth_ramrod_cmd_id {
5913 ETH_RAMROD_VPORT_START,
5914 ETH_RAMROD_VPORT_UPDATE,
5915 ETH_RAMROD_VPORT_STOP,
5916 ETH_RAMROD_RX_QUEUE_START,
5917 ETH_RAMROD_RX_QUEUE_STOP,
5918 ETH_RAMROD_TX_QUEUE_START,
5919 ETH_RAMROD_TX_QUEUE_STOP,
5920 ETH_RAMROD_FILTERS_UPDATE,
5921 ETH_RAMROD_RX_QUEUE_UPDATE,
5922 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5923 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5924 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5925 ETH_RAMROD_RX_ADD_UDP_FILTER,
5926 ETH_RAMROD_RX_DELETE_UDP_FILTER,
5927 ETH_RAMROD_RX_CREATE_GFT_ACTION,
5928 ETH_RAMROD_GFT_UPDATE_FILTER,
5929 ETH_RAMROD_TX_QUEUE_UPDATE,
5930 ETH_RAMROD_RGFS_FILTER_ADD,
5931 ETH_RAMROD_RGFS_FILTER_DEL,
5932 ETH_RAMROD_TGFS_FILTER_ADD,
5933 ETH_RAMROD_TGFS_FILTER_DEL,
5934 ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST,
5935 MAX_ETH_RAMROD_CMD_ID
5938 /* Return code from eth sp ramrods */
5939 struct eth_return_code {
5941 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
5942 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5943 #define ETH_RETURN_CODE_RESERVED_MASK 0x1
5944 #define ETH_RETURN_CODE_RESERVED_SHIFT 6
5945 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
5946 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
5949 /* tx destination enum */
5950 enum eth_tx_dst_mode_config_enum {
5951 ETH_TX_DST_MODE_CONFIG_DISABLE,
5952 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD,
5953 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT,
5954 MAX_ETH_TX_DST_MODE_CONFIG_ENUM
5957 /* What to do in case an error occurs */
5960 ETH_TX_ERR_ASSERT_MALICIOUS,
5964 /* Array of the different error type behaviors */
5965 struct eth_tx_err_vals {
5967 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
5968 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
5969 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
5970 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
5971 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
5972 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
5973 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
5974 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
5975 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
5976 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
5977 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
5978 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
5979 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
5980 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
5981 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
5982 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7
5983 #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
5984 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 8
5987 /* vport rss configuration data */
5988 struct eth_vport_rss_config {
5989 __le16 capabilities;
5990 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
5991 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
5992 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
5993 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
5994 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
5995 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
5996 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
5997 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
5998 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
5999 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
6000 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
6001 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
6002 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
6003 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
6004 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
6005 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
6009 u8 update_rss_ind_table;
6010 u8 update_rss_capabilities;
6012 __le32 reserved2[2];
6013 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
6014 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
6015 __le32 reserved3[2];
6018 /* eth vport RSS mode */
6019 enum eth_vport_rss_mode {
6020 ETH_VPORT_RSS_MODE_DISABLED,
6021 ETH_VPORT_RSS_MODE_REGULAR,
6022 MAX_ETH_VPORT_RSS_MODE
6025 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
6026 struct eth_vport_rx_mode {
6028 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
6029 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
6030 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
6031 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
6032 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
6033 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
6034 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
6035 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
6036 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
6037 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
6038 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
6039 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
6040 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
6041 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6
6042 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF
6043 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7
6046 /* Command for setting tpa parameters */
6047 struct eth_vport_tpa_param {
6050 u8 tpa_ipv4_tunn_en_flg;
6051 u8 tpa_ipv6_tunn_en_flg;
6052 u8 tpa_pkt_split_flg;
6053 u8 tpa_hdr_data_split_flg;
6054 u8 tpa_gro_consistent_flg;
6056 u8 tpa_max_aggs_num;
6058 __le16 tpa_max_size;
6059 __le16 tpa_min_size_to_start;
6061 __le16 tpa_min_size_to_cont;
6066 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
6067 struct eth_vport_tx_mode {
6069 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
6070 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
6071 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
6072 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
6073 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
6074 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
6075 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
6076 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
6077 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
6078 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
6079 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
6080 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
6083 /* GFT filter update action type */
6084 enum gft_filter_update_action {
6087 MAX_GFT_FILTER_UPDATE_ACTION
6090 /* Ramrod data for rx add openflow filter */
6091 struct rx_add_openflow_filter_data {
6107 u8 tenant_id_exists;
6108 __le32 ipv4_dst_addr;
6109 __le32 ipv4_src_addr;
6114 /* Ramrod data for rx create gft action */
6115 struct rx_create_gft_action_data {
6120 /* Ramrod data for rx create openflow action */
6121 struct rx_create_openflow_action_data {
6126 /* Ramrod data for rx queue start ramrod */
6127 struct rx_queue_start_ramrod_data {
6129 __le16 num_of_pbl_pages;
6130 __le16 bd_max_bytes;
6134 u8 default_rss_queue_flg;
6135 u8 complete_cqe_flg;
6136 u8 complete_event_flg;
6137 u8 stats_counter_id;
6139 u8 pxp_tph_valid_bd;
6140 u8 pxp_tph_valid_pkt;
6143 __le16 pxp_st_index;
6149 u8 vf_rx_prod_index;
6150 u8 vf_rx_prod_use_zone_a;
6153 struct regpair cqe_pbl_addr;
6154 struct regpair bd_base;
6155 struct regpair reserved2;
6158 /* Ramrod data for rx queue stop ramrod */
6159 struct rx_queue_stop_ramrod_data {
6161 u8 complete_cqe_flg;
6162 u8 complete_event_flg;
6167 /* Ramrod data for rx queue update ramrod */
6168 struct rx_queue_update_ramrod_data {
6170 u8 complete_cqe_flg;
6171 u8 complete_event_flg;
6173 u8 set_default_rss_queue;
6180 struct regpair reserved6;
6183 /* Ramrod data for rx Add UDP Filter */
6184 struct rx_udp_filter_data {
6188 u8 tenant_id_exists;
6190 __le32 ip_dst_addr[4];
6191 __le32 ip_src_addr[4];
6192 __le16 udp_dst_port;
6193 __le16 udp_src_port;
6197 /* Add or delete GFT filter - filter is packet header of type of packet wished
6198 * to pass certain FW flow.
6200 struct rx_update_gft_filter_data {
6201 struct regpair pkt_hdr_addr;
6202 __le16 pkt_hdr_length;
6207 u8 action_icid_valid;
6212 u8 inner_vlan_removal_en;
6215 /* Ramrod data for tx queue start ramrod */
6216 struct tx_queue_start_ramrod_data {
6221 u8 stats_counter_id;
6224 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
6225 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
6226 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
6227 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
6228 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
6229 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2
6230 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
6231 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3
6232 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
6233 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4
6234 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
6235 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5
6237 u8 pxp_tph_valid_bd;
6238 u8 pxp_tph_valid_pkt;
6239 __le16 pxp_st_index;
6240 __le16 comp_agg_size;
6241 __le16 queue_zone_id;
6245 __le16 same_as_last_id;
6247 struct regpair pbl_base_addr;
6248 struct regpair bd_cons_address;
6251 /* Ramrod data for tx queue stop ramrod */
6252 struct tx_queue_stop_ramrod_data {
6256 /* Ramrod data for tx queue update ramrod */
6257 struct tx_queue_update_ramrod_data {
6258 __le16 update_qm_pq_id_flg;
6261 struct regpair reserved1[5];
6264 /* Inner to Inner VLAN priority map update mode */
6265 enum update_in_to_in_pri_map_mode_enum {
6266 ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
6267 ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
6268 ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
6269 MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
6272 /* Ramrod data for vport update ramrod */
6273 struct vport_filter_update_ramrod_data {
6274 struct eth_filter_cmd_header filter_cmd_hdr;
6275 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
6278 /* Ramrod data for vport start ramrod */
6279 struct vport_start_ramrod_data {
6284 u8 inner_vlan_removal_en;
6285 struct eth_vport_rx_mode rx_mode;
6286 struct eth_vport_tx_mode tx_mode;
6287 struct eth_vport_tpa_param tpa_param;
6288 __le16 default_vlan;
6290 u8 anti_spoofing_en;
6293 u8 silent_vlan_removal_en;
6295 struct eth_tx_err_vals tx_err_behav;
6296 u8 zero_placement_offset;
6297 u8 ctl_frame_mac_check_en;
6298 u8 ctl_frame_ethtype_check_en;
6301 u8 tx_dst_port_mode_config;
6303 u8 tx_dst_port_mode;
6304 u8 dst_vport_id_valid;
6305 u8 wipe_inner_vlan_pri_en;
6307 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
6310 /* Ramrod data for vport stop ramrod */
6311 struct vport_stop_ramrod_data {
6316 /* Ramrod data for vport update ramrod */
6317 struct vport_update_ramrod_data_cmn {
6319 u8 update_rx_active_flg;
6321 u8 update_tx_active_flg;
6323 u8 update_rx_mode_flg;
6324 u8 update_tx_mode_flg;
6325 u8 update_approx_mcast_flg;
6328 u8 update_inner_vlan_removal_en_flg;
6330 u8 inner_vlan_removal_en;
6331 u8 update_tpa_param_flg;
6332 u8 update_tpa_en_flg;
6333 u8 update_tx_switching_en_flg;
6336 u8 update_anti_spoofing_en_flg;
6338 u8 anti_spoofing_en;
6339 u8 update_handle_ptp_pkts;
6342 u8 update_default_vlan_en_flg;
6346 u8 update_default_vlan_flg;
6348 __le16 default_vlan;
6349 u8 update_accept_any_vlan_flg;
6352 u8 silent_vlan_removal_en;
6356 u8 update_ctl_frame_checks_en_flg;
6357 u8 ctl_frame_mac_check_en;
6358 u8 ctl_frame_ethtype_check_en;
6359 u8 update_in_to_in_pri_map_mode;
6360 u8 in_to_in_pri_map[8];
6364 struct vport_update_ramrod_mcast {
6365 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
6368 /* Ramrod data for vport update ramrod */
6369 struct vport_update_ramrod_data {
6370 struct vport_update_ramrod_data_cmn common;
6372 struct eth_vport_rx_mode rx_mode;
6373 struct eth_vport_tx_mode tx_mode;
6375 struct eth_vport_tpa_param tpa_param;
6376 struct vport_update_ramrod_mcast approx_mcast;
6377 struct eth_vport_rss_config rss_config;
6380 struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
6384 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
6385 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
6386 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
6387 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
6388 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
6389 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
6390 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
6391 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
6392 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
6393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
6394 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
6395 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
6396 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
6397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
6398 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
6399 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
6401 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
6402 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
6403 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
6404 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
6405 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
6406 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
6407 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
6408 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
6409 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
6410 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4
6411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
6412 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5
6413 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
6414 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
6415 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
6416 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
6418 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6419 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6420 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6421 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
6422 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6423 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
6424 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6425 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
6427 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6428 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6429 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6430 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
6431 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6432 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
6433 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
6434 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
6436 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6437 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6438 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6439 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
6440 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6441 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
6442 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6443 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
6445 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6446 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6447 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6448 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
6449 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6450 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
6451 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6452 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
6454 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
6455 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
6456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
6457 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
6458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
6459 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
6460 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
6461 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
6463 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
6464 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
6465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
6466 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
6467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6468 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
6469 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6470 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
6471 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6472 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
6474 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6475 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6476 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6477 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
6478 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6479 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
6480 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6481 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
6482 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6483 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
6484 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
6485 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
6486 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6487 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
6488 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6489 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
6491 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6492 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6493 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6494 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
6495 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6496 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
6497 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6498 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
6499 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6500 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
6501 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6502 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
6503 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
6504 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
6505 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
6506 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
6508 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
6509 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
6510 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
6511 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
6512 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
6513 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
6514 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
6515 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
6516 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6517 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
6518 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
6519 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
6520 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
6521 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
6522 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
6523 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
6525 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
6526 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
6527 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
6528 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
6529 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
6530 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
6531 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6532 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
6533 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6534 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
6535 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6536 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
6537 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6538 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
6539 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6540 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
6542 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6543 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6544 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6545 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
6546 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6547 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
6548 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6549 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
6550 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6551 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
6552 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6553 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
6554 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6555 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
6556 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6557 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
6559 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6560 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6561 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6562 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
6563 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6564 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
6565 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6566 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
6567 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6568 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
6569 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6570 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
6571 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6572 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
6573 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6574 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
6576 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
6577 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
6578 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
6579 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
6580 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
6581 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
6582 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
6583 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
6584 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
6585 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
6586 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6587 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
6588 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
6589 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
6592 __le16 e5_reserved1;
6593 __le16 edpm_num_bds;
6596 __le16 updated_qm_pq_id;
6609 struct e4_mstorm_eth_conn_ag_ctx {
6613 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6614 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6615 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
6616 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
6617 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
6618 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
6619 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
6620 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
6621 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
6622 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
6624 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
6625 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
6626 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
6627 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
6628 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
6629 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
6630 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
6631 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
6632 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
6633 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
6634 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
6635 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
6636 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
6637 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
6638 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
6639 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
6646 struct e4_xstorm_eth_hw_conn_ag_ctx {
6650 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6651 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6652 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
6653 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
6654 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
6655 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
6656 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6657 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6658 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
6659 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
6660 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
6661 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
6662 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
6663 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
6664 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
6665 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
6667 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
6668 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
6669 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
6670 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
6671 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
6672 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
6673 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
6674 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
6675 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
6676 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
6677 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
6678 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
6679 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
6680 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
6681 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
6682 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
6684 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
6685 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
6686 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
6687 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
6688 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
6689 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
6690 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
6691 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
6693 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
6694 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
6695 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
6696 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
6697 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
6698 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
6699 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
6700 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
6702 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
6703 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
6704 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
6705 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
6706 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
6707 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
6708 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
6709 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
6711 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
6712 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
6713 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
6714 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
6715 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
6716 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
6717 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
6718 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
6720 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
6721 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
6722 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
6723 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
6724 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
6725 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
6726 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
6727 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
6729 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
6730 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
6731 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
6732 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
6733 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6734 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
6735 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
6736 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
6737 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
6738 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
6740 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
6741 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
6742 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
6743 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
6744 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
6745 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
6746 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
6747 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
6748 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
6749 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
6750 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
6751 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
6752 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
6753 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
6754 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
6755 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
6757 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
6758 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
6759 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
6760 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
6761 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
6762 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
6763 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
6764 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
6765 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
6766 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
6767 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
6768 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
6769 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
6770 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
6771 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
6772 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
6774 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
6775 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
6776 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
6777 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
6778 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
6779 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
6780 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
6781 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
6782 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6783 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
6784 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
6785 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
6786 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
6787 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
6788 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
6789 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
6791 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
6792 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
6793 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
6794 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
6795 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
6796 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
6797 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
6798 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
6799 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
6800 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
6801 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
6802 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
6803 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6804 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6805 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
6806 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
6808 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
6809 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
6810 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
6811 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
6812 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6813 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6814 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6815 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6816 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
6817 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
6818 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
6819 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
6820 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
6821 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
6822 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
6823 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
6825 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
6826 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
6827 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
6828 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
6829 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6830 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6831 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6832 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6833 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6834 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6835 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6836 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6837 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6838 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6839 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6840 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6842 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
6843 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
6844 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
6845 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
6846 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
6847 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
6848 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
6849 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
6850 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
6851 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
6852 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6853 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6854 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
6855 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
6858 __le16 e5_reserved1;
6859 __le16 edpm_num_bds;
6862 __le16 updated_qm_pq_id;
6866 /* GFT CAM line struct with fields breakout */
6867 struct gft_cam_line_mapped {
6869 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
6870 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
6871 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
6872 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
6873 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
6874 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
6875 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
6876 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
6877 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
6878 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
6879 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
6880 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
6881 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
6882 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
6883 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
6884 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
6885 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
6886 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
6887 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
6888 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
6889 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
6890 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
6891 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
6892 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
6896 /* Used in gft_profile_key: Indication for ip version */
6897 enum gft_profile_ip_version {
6898 GFT_PROFILE_IPV4 = 0,
6899 GFT_PROFILE_IPV6 = 1,
6900 MAX_GFT_PROFILE_IP_VERSION
6903 /* Profile key stucr fot GFT logic in Prs */
6904 struct gft_profile_key {
6906 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
6907 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
6908 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
6909 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
6910 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
6911 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
6912 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
6913 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
6914 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
6915 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
6916 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
6917 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
6920 /* Used in gft_profile_key: Indication for tunnel type */
6921 enum gft_profile_tunnel_type {
6922 GFT_PROFILE_NO_TUNNEL = 0,
6923 GFT_PROFILE_VXLAN_TUNNEL = 1,
6924 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6925 GFT_PROFILE_GRE_IP_TUNNEL = 3,
6926 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6927 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6928 MAX_GFT_PROFILE_TUNNEL_TYPE
6931 /* Used in gft_profile_key: Indication for protocol type */
6932 enum gft_profile_upper_protocol_type {
6933 GFT_PROFILE_ROCE_PROTOCOL = 0,
6934 GFT_PROFILE_RROCE_PROTOCOL = 1,
6935 GFT_PROFILE_FCOE_PROTOCOL = 2,
6936 GFT_PROFILE_ICMP_PROTOCOL = 3,
6937 GFT_PROFILE_ARP_PROTOCOL = 4,
6938 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6939 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6940 GFT_PROFILE_TCP_PROTOCOL = 7,
6941 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6942 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6943 GFT_PROFILE_UDP_PROTOCOL = 10,
6944 GFT_PROFILE_USER_IP_1_INNER = 11,
6945 GFT_PROFILE_USER_IP_2_OUTER = 12,
6946 GFT_PROFILE_USER_ETH_1_INNER = 13,
6947 GFT_PROFILE_USER_ETH_2_OUTER = 14,
6948 GFT_PROFILE_RAW = 15,
6949 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6952 /* GFT RAM line struct */
6953 struct gft_ram_line {
6955 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
6956 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
6957 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
6958 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
6959 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
6960 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
6961 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
6962 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
6963 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
6964 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
6965 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
6966 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
6967 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
6968 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
6969 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
6970 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
6971 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
6972 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
6973 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
6974 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
6975 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
6976 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
6977 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
6978 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
6979 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
6980 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
6981 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
6982 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
6983 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
6984 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
6985 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
6986 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
6987 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
6988 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
6989 #define GFT_RAM_LINE_TTL_MASK 0x1
6990 #define GFT_RAM_LINE_TTL_SHIFT 18
6991 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
6992 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
6993 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
6994 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
6995 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
6996 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
6997 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
6998 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
6999 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
7000 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
7001 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
7002 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
7003 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
7004 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
7005 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
7006 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
7007 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
7008 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
7009 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
7010 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
7011 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
7012 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
7013 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
7014 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
7015 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
7016 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
7018 #define GFT_RAM_LINE_DSCP_MASK 0x1
7019 #define GFT_RAM_LINE_DSCP_SHIFT 0
7020 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
7021 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
7022 #define GFT_RAM_LINE_DST_IP_MASK 0x1
7023 #define GFT_RAM_LINE_DST_IP_SHIFT 2
7024 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
7025 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
7026 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
7027 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
7028 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
7029 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
7030 #define GFT_RAM_LINE_VLAN_MASK 0x1
7031 #define GFT_RAM_LINE_VLAN_SHIFT 6
7032 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
7033 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
7034 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
7035 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
7036 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
7037 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
7038 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
7039 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
7042 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
7043 enum gft_vlan_select {
7044 INNER_PROVIDER_VLAN = 0,
7046 OUTER_PROVIDER_VLAN = 2,
7051 /* The rdma task context of Mstorm */
7052 struct ystorm_rdma_task_st_ctx {
7053 struct regpair temp[4];
7056 struct e4_ystorm_rdma_task_ag_ctx {
7059 __le16 msem_ctx_upd_seq;
7061 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
7062 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
7063 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
7064 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
7065 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7066 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
7067 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
7068 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
7069 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
7070 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
7072 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
7073 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
7074 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
7075 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
7076 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
7077 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
7078 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
7079 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
7080 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
7081 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
7083 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
7084 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
7085 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
7086 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
7087 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
7088 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
7089 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
7090 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
7091 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
7092 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
7093 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7094 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
7095 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
7096 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
7097 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
7098 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
7100 __le32 mw_cnt_or_qp_id;
7104 __le16 tx_ref_count;
7105 __le16 last_used_ltid;
7106 __le16 parent_mr_lo;
7107 __le16 parent_mr_hi;
7112 struct e4_mstorm_rdma_task_ag_ctx {
7117 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
7118 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
7119 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
7120 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
7121 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7122 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
7123 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
7124 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
7125 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
7126 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
7128 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
7129 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
7130 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
7131 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
7132 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
7133 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
7134 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
7135 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
7136 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
7137 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
7139 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
7140 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
7141 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
7142 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
7143 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
7144 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
7145 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
7146 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
7147 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
7148 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
7149 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7150 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
7151 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
7152 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
7153 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
7154 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
7156 __le32 mw_cnt_or_qp_id;
7160 __le16 tx_ref_count;
7161 __le16 last_used_ltid;
7162 __le16 parent_mr_lo;
7163 __le16 parent_mr_hi;
7168 /* The roce task context of Mstorm */
7169 struct mstorm_rdma_task_st_ctx {
7170 struct regpair temp[4];
7173 /* The roce task context of Ustorm */
7174 struct ustorm_rdma_task_st_ctx {
7175 struct regpair temp[6];
7178 struct e4_ustorm_rdma_task_ag_ctx {
7183 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
7184 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
7185 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
7186 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
7187 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7188 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
7189 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
7190 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
7192 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
7193 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
7194 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
7195 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
7196 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
7197 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4
7198 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
7199 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
7201 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
7202 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
7203 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
7204 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
7205 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
7206 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
7207 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1
7208 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3
7209 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
7210 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
7211 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
7212 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
7213 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
7214 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
7215 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
7216 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
7218 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
7219 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
7220 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7221 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
7222 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
7223 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2
7224 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
7225 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
7226 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
7227 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
7228 __le32 dif_err_intervals;
7229 __le32 dif_error_1st_interval;
7230 __le32 dif_rxmit_cons;
7231 __le32 dif_rxmit_prod;
7236 __le16 dif_write_cons;
7237 __le16 dif_write_prod;
7239 __le32 dif_error_buffer_address_lo;
7240 __le32 dif_error_buffer_address_hi;
7243 /* RDMA task context */
7244 struct e4_rdma_task_context {
7245 struct ystorm_rdma_task_st_ctx ystorm_st_context;
7246 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
7247 struct tdif_task_context tdif_context;
7248 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
7249 struct mstorm_rdma_task_st_ctx mstorm_st_context;
7250 struct rdif_task_context rdif_context;
7251 struct ustorm_rdma_task_st_ctx ustorm_st_context;
7252 struct regpair ustorm_st_padding[2];
7253 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
7256 /* rdma function init ramrod data */
7257 struct rdma_close_func_ramrod_data {
7258 u8 cnq_start_offset;
7265 /* rdma function init CNQ parameters */
7266 struct rdma_cnq_params {
7271 struct regpair pbl_base_addr;
7272 __le16 queue_zone_num;
7276 /* rdma create cq ramrod data */
7277 struct rdma_create_cq_ramrod_data {
7278 struct regpair cq_handle;
7279 struct regpair pbl_addr;
7281 __le16 pbl_num_pages;
7283 u8 is_two_level_pbl;
7285 u8 pbl_log_page_size;
7290 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7291 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
7292 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
7293 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1
7296 /* rdma deregister tid ramrod data */
7297 struct rdma_deregister_tid_ramrod_data {
7302 /* rdma destroy cq output params */
7303 struct rdma_destroy_cq_output_params {
7309 /* rdma destroy cq ramrod data */
7310 struct rdma_destroy_cq_ramrod_data {
7311 struct regpair output_params_addr;
7314 /* RDMA slow path EQ cmd IDs */
7315 enum rdma_event_opcode {
7317 RDMA_EVENT_FUNC_INIT,
7318 RDMA_EVENT_FUNC_CLOSE,
7319 RDMA_EVENT_REGISTER_MR,
7320 RDMA_EVENT_DEREGISTER_MR,
7321 RDMA_EVENT_CREATE_CQ,
7322 RDMA_EVENT_RESIZE_CQ,
7323 RDMA_EVENT_DESTROY_CQ,
7324 RDMA_EVENT_CREATE_SRQ,
7325 RDMA_EVENT_MODIFY_SRQ,
7326 RDMA_EVENT_DESTROY_SRQ,
7327 MAX_RDMA_EVENT_OPCODE
7330 /* RDMA FW return code for slow path ramrods */
7331 enum rdma_fw_return_code {
7333 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
7334 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
7335 RDMA_RETURN_RESIZE_CQ_ERR,
7336 RDMA_RETURN_NIG_DRAIN_REQ,
7337 RDMA_RETURN_GENERAL_ERR,
7338 MAX_RDMA_FW_RETURN_CODE
7341 /* rdma function init header */
7342 struct rdma_init_func_hdr {
7343 u8 cnq_start_offset;
7348 u8 relaxed_ordering;
7349 __le16 first_reg_srq_id;
7350 __le32 reg_srq_base_addr;
7357 /* rdma function init ramrod data */
7358 struct rdma_init_func_ramrod_data {
7359 struct rdma_init_func_hdr params_header;
7360 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
7363 /* RDMA ramrod command IDs */
7364 enum rdma_ramrod_cmd_id {
7366 RDMA_RAMROD_FUNC_INIT,
7367 RDMA_RAMROD_FUNC_CLOSE,
7368 RDMA_RAMROD_REGISTER_MR,
7369 RDMA_RAMROD_DEREGISTER_MR,
7370 RDMA_RAMROD_CREATE_CQ,
7371 RDMA_RAMROD_RESIZE_CQ,
7372 RDMA_RAMROD_DESTROY_CQ,
7373 RDMA_RAMROD_CREATE_SRQ,
7374 RDMA_RAMROD_MODIFY_SRQ,
7375 RDMA_RAMROD_DESTROY_SRQ,
7376 MAX_RDMA_RAMROD_CMD_ID
7379 /* rdma register tid ramrod data */
7380 struct rdma_register_tid_ramrod_data {
7382 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
7383 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
7384 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
7385 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
7386 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
7387 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
7388 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
7389 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
7390 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
7391 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
7392 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
7393 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
7394 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
7395 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
7396 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
7397 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
7398 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
7399 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
7400 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
7401 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
7402 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
7403 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
7405 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
7406 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
7407 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
7408 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
7410 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
7411 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
7412 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
7413 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
7414 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
7415 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
7426 struct regpair pbl_base;
7427 struct regpair dif_error_addr;
7428 __le32 reserved4[4];
7431 /* rdma resize cq output params */
7432 struct rdma_resize_cq_output_params {
7437 /* rdma resize cq ramrod data */
7438 struct rdma_resize_cq_ramrod_data {
7440 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
7441 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
7442 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
7443 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
7444 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7445 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2
7446 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
7447 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3
7448 u8 pbl_log_page_size;
7449 __le16 pbl_num_pages;
7451 struct regpair pbl_addr;
7452 struct regpair output_params_addr;
7457 /* The rdma SRQ context */
7458 struct rdma_srq_context {
7459 struct regpair temp[8];
7462 /* rdma create qp requester ramrod data */
7463 struct rdma_srq_create_ramrod_data {
7465 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
7466 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0
7467 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7468 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
7469 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F
7470 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2
7473 __le32 xrc_srq_cq_cid;
7474 struct regpair pbl_base_addr;
7475 __le16 pages_in_srq_pbl;
7477 struct rdma_srq_id srq_id;
7481 struct regpair producers_addr;
7484 /* rdma create qp requester ramrod data */
7485 struct rdma_srq_destroy_ramrod_data {
7486 struct rdma_srq_id srq_id;
7490 /* rdma create qp requester ramrod data */
7491 struct rdma_srq_modify_ramrod_data {
7492 struct rdma_srq_id srq_id;
7496 /* RDMA Tid type enumeration (for register_tid ramrod) */
7497 enum rdma_tid_type {
7498 RDMA_TID_REGISTERED_MR,
7504 /* The rdma XRC SRQ context */
7505 struct rdma_xrc_srq_context {
7506 struct regpair temp[9];
7509 struct e4_tstorm_rdma_task_ag_ctx {
7514 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
7515 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
7516 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
7517 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
7518 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7519 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
7520 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
7521 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
7522 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
7523 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
7525 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
7526 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
7527 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
7528 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
7529 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
7530 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
7531 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
7532 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
7533 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
7534 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
7536 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
7537 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
7538 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
7539 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
7540 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
7541 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
7542 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
7543 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
7545 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
7546 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
7547 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
7548 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
7549 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
7550 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
7551 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
7552 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
7553 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
7554 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
7555 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
7556 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
7557 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
7558 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
7560 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
7561 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
7562 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
7563 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
7564 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
7565 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
7566 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
7567 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
7568 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
7569 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
7570 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
7571 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
7572 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7573 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
7574 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
7575 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
7588 struct e4_ustorm_rdma_conn_ag_ctx {
7592 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7593 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7594 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1
7595 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1
7596 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7597 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
7598 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7599 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7600 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7601 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
7603 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7604 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
7605 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
7606 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
7607 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
7608 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
7609 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7610 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
7612 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7613 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7614 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7615 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7616 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7617 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7618 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7619 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
7620 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
7621 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
7622 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
7623 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
7624 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7625 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
7626 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
7627 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
7629 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
7630 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
7631 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7632 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
7633 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7634 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
7635 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7636 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
7637 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7638 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
7639 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7640 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
7641 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7642 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
7643 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7644 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
7657 struct e4_xstorm_roce_conn_ag_ctx {
7661 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7662 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7663 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7664 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
7665 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
7666 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2
7667 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7668 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7669 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
7670 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4
7671 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
7672 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5
7673 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1
7674 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6
7675 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1
7676 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7
7678 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1
7679 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0
7680 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1
7681 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1
7682 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1
7683 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2
7684 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
7685 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3
7686 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
7687 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
7688 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
7689 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
7690 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
7691 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6
7692 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7693 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7695 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7696 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0
7697 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7698 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2
7699 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7700 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4
7701 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
7702 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6
7704 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
7705 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0
7706 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
7707 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2
7708 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
7709 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4
7710 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7711 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7713 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
7714 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0
7715 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
7716 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2
7717 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
7718 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4
7719 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
7720 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6
7722 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
7723 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0
7724 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
7725 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2
7726 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
7727 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4
7728 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
7729 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6
7731 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
7732 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0
7733 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
7734 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2
7735 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
7736 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4
7737 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
7738 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6
7740 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
7741 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0
7742 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
7743 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2
7744 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7745 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7746 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7747 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6
7748 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
7749 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7
7751 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7752 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0
7753 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1
7754 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1
7755 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1
7756 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2
7757 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
7758 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3
7759 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
7760 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4
7761 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7762 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7763 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
7764 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6
7765 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
7766 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7
7768 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
7769 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0
7770 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1
7771 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1
7772 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1
7773 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2
7774 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1
7775 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3
7776 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1
7777 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4
7778 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1
7779 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5
7780 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1
7781 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6
7782 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1
7783 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7
7785 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1
7786 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0
7787 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1
7788 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1
7789 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1
7790 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2
7791 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1
7792 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3
7793 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7794 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7795 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1
7796 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5
7797 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7798 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6
7799 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7800 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7
7802 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7803 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0
7804 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7805 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1
7806 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7807 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2
7808 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
7809 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3
7810 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
7811 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4
7812 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
7813 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5
7814 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7815 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7816 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1
7817 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7
7819 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1
7820 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0
7821 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1
7822 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1
7823 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7824 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7825 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7826 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7827 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1
7828 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4
7829 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1
7830 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5
7831 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1
7832 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6
7833 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1
7834 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7
7836 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1
7837 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0
7838 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1
7839 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1
7840 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7841 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7842 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7843 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7844 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7845 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7846 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7847 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7848 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7849 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7850 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7851 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7853 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1
7854 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0
7855 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1
7856 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1
7857 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7858 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7859 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1
7860 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4
7861 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7862 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7863 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
7864 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6
7886 struct e4_tstorm_roce_conn_ag_ctx {
7890 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7891 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7892 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7893 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
7894 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
7895 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2
7896 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1
7897 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3
7898 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
7899 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4
7900 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
7901 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5
7902 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7903 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6
7905 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7906 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7907 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7908 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2
7909 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7910 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7911 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7912 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7914 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
7915 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0
7916 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
7917 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2
7918 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
7919 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4
7920 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
7921 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6
7923 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
7924 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0
7925 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
7926 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2
7927 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7928 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4
7929 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7930 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
7931 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7932 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6
7933 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7934 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7936 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7937 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7938 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
7939 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1
7940 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
7941 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2
7942 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1
7943 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3
7944 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
7945 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4
7946 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
7947 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5
7948 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
7949 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6
7950 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7951 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7
7953 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7954 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0
7955 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7956 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1
7957 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7958 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2
7959 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7960 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3
7961 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
7962 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4
7963 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
7964 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5
7965 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
7966 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6
7967 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1
7968 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7
7990 /* The roce storm context of Ystorm */
7991 struct ystorm_roce_conn_st_ctx {
7992 struct regpair temp[2];
7995 /* The roce storm context of Mstorm */
7996 struct pstorm_roce_conn_st_ctx {
7997 struct regpair temp[16];
8000 /* The roce storm context of Xstorm */
8001 struct xstorm_roce_conn_st_ctx {
8002 struct regpair temp[24];
8005 /* The roce storm context of Tstorm */
8006 struct tstorm_roce_conn_st_ctx {
8007 struct regpair temp[30];
8010 /* The roce storm context of Mstorm */
8011 struct mstorm_roce_conn_st_ctx {
8012 struct regpair temp[6];
8015 /* The roce storm context of Ustorm */
8016 struct ustorm_roce_conn_st_ctx {
8017 struct regpair temp[14];
8020 /* roce connection context */
8021 struct e4_roce_conn_context {
8022 struct ystorm_roce_conn_st_ctx ystorm_st_context;
8023 struct regpair ystorm_st_padding[2];
8024 struct pstorm_roce_conn_st_ctx pstorm_st_context;
8025 struct xstorm_roce_conn_st_ctx xstorm_st_context;
8026 struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context;
8027 struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context;
8028 struct timers_context timer_context;
8029 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
8030 struct tstorm_roce_conn_st_ctx tstorm_st_context;
8031 struct regpair tstorm_st_padding[2];
8032 struct mstorm_roce_conn_st_ctx mstorm_st_context;
8033 struct regpair mstorm_st_padding[2];
8034 struct ustorm_roce_conn_st_ctx ustorm_st_context;
8035 struct regpair ustorm_st_padding[2];
8038 /* roce cqes statistics */
8039 struct roce_cqe_stats {
8040 __le32 req_cqe_error;
8041 __le32 req_remote_access_errors;
8042 __le32 req_remote_invalid_request;
8043 __le32 resp_cqe_error;
8044 __le32 resp_local_length_error;
8048 /* roce create qp requester ramrod data */
8049 struct roce_create_qp_req_ramrod_data {
8051 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
8052 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
8053 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
8054 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
8055 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
8056 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
8057 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
8058 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
8059 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
8060 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7
8061 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
8062 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
8063 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
8064 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
8072 __le32 ack_timeout_val;
8076 __le16 sq_num_pages;
8077 __le16 low_latency_phy_queue;
8078 struct regpair sq_pbl_addr;
8079 struct regpair orq_pbl_addr;
8080 __le16 local_mac_addr[3];
8081 __le16 remote_mac_addr[3];
8083 __le16 udp_src_port;
8087 struct regpair qp_handle_for_cqe;
8088 struct regpair qp_handle_for_async;
8089 u8 stats_counter_id;
8093 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
8094 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
8095 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
8096 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1
8097 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x3F
8098 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 2
8101 __le16 regular_latency_phy_queue;
8105 /* roce create qp responder ramrod data */
8106 struct roce_create_qp_resp_ramrod_data {
8108 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
8109 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
8110 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
8111 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
8112 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
8113 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
8114 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
8115 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
8116 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
8117 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
8118 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
8119 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
8120 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
8121 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
8122 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
8123 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
8124 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
8125 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
8126 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
8127 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16
8128 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
8129 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17
8130 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x3FFF
8131 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 18
8140 u8 stats_counter_id;
8145 __le16 rq_num_pages;
8146 struct rdma_srq_id srq_id;
8147 struct regpair rq_pbl_addr;
8148 struct regpair irq_pbl_addr;
8149 __le16 local_mac_addr[3];
8150 __le16 remote_mac_addr[3];
8152 __le16 udp_src_port;
8155 struct regpair qp_handle_for_cqe;
8156 struct regpair qp_handle_for_async;
8157 __le16 low_latency_phy_queue;
8161 __le16 regular_latency_phy_queue;
8168 /* roce DCQCN received statistics */
8169 struct roce_dcqcn_received_stats {
8170 struct regpair ecn_pkt_rcv;
8171 struct regpair cnp_pkt_rcv;
8174 /* roce DCQCN sent statistics */
8175 struct roce_dcqcn_sent_stats {
8176 struct regpair cnp_pkt_sent;
8179 /* RoCE destroy qp requester output params */
8180 struct roce_destroy_qp_req_output_params {
8185 /* RoCE destroy qp requester ramrod data */
8186 struct roce_destroy_qp_req_ramrod_data {
8187 struct regpair output_params_addr;
8190 /* RoCE destroy qp responder output params */
8191 struct roce_destroy_qp_resp_output_params {
8196 /* RoCE destroy qp responder ramrod data */
8197 struct roce_destroy_qp_resp_ramrod_data {
8198 struct regpair output_params_addr;
8203 /* roce error statistics */
8204 struct roce_error_stats {
8205 __le32 resp_remote_access_errors;
8209 /* roce special events statistics */
8210 struct roce_events_stats {
8211 __le32 silent_drops;
8212 __le32 rnr_naks_sent;
8213 __le32 retransmit_count;
8214 __le32 icrc_error_count;
8215 __le32 implied_nak_seq_err;
8216 __le32 duplicate_request;
8217 __le32 local_ack_timeout_err;
8218 __le32 out_of_sequence;
8219 __le32 packet_seq_err;
8220 __le32 rnr_nak_retry_err;
8223 /* roce slow path EQ cmd IDs */
8224 enum roce_event_opcode {
8225 ROCE_EVENT_CREATE_QP = 11,
8226 ROCE_EVENT_MODIFY_QP,
8227 ROCE_EVENT_QUERY_QP,
8228 ROCE_EVENT_DESTROY_QP,
8229 ROCE_EVENT_CREATE_UD_QP,
8230 ROCE_EVENT_DESTROY_UD_QP,
8231 ROCE_EVENT_FUNC_UPDATE,
8232 MAX_ROCE_EVENT_OPCODE
8235 /* roce func init ramrod data */
8236 struct roce_init_func_params {
8238 u8 cnp_vlan_priority;
8241 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
8242 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
8243 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
8244 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
8245 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F
8246 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT 2
8247 __le32 cnp_send_timeout;
8253 /* roce func init ramrod data */
8254 struct roce_init_func_ramrod_data {
8255 struct rdma_init_func_ramrod_data rdma;
8256 struct roce_init_func_params roce;
8259 /* roce modify qp requester ramrod data */
8260 struct roce_modify_qp_req_ramrod_data {
8262 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
8263 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
8264 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
8265 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
8266 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
8267 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
8268 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
8269 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
8270 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
8271 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
8272 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
8273 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
8274 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
8275 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
8276 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
8277 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
8278 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
8279 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
8280 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
8281 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
8282 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
8283 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
8284 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
8285 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13
8286 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
8287 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14
8289 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
8290 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
8291 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
8292 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
8298 __le32 ack_timeout_val;
8301 __le32 reserved3[2];
8302 __le16 low_latency_phy_queue;
8303 __le16 regular_latency_phy_queue;
8308 /* roce modify qp responder ramrod data */
8309 struct roce_modify_qp_resp_ramrod_data {
8311 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
8312 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
8313 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
8314 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
8315 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
8316 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
8317 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
8318 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
8319 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
8320 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
8321 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
8322 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
8323 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
8324 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
8325 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
8326 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
8327 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
8328 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
8329 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
8330 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
8331 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
8332 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10
8333 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F
8334 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11
8336 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
8337 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
8338 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
8339 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
8346 __le16 low_latency_phy_queue;
8347 __le16 regular_latency_phy_queue;
8353 /* RoCE query qp requester output params */
8354 struct roce_query_qp_req_output_params {
8357 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
8358 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
8359 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
8360 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
8361 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
8362 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
8365 /* RoCE query qp requester ramrod data */
8366 struct roce_query_qp_req_ramrod_data {
8367 struct regpair output_params_addr;
8370 /* RoCE query qp responder output params */
8371 struct roce_query_qp_resp_output_params {
8374 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
8375 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
8376 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
8377 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
8380 /* RoCE query qp responder ramrod data */
8381 struct roce_query_qp_resp_ramrod_data {
8382 struct regpair output_params_addr;
8385 /* ROCE ramrod command IDs */
8386 enum roce_ramrod_cmd_id {
8387 ROCE_RAMROD_CREATE_QP = 11,
8388 ROCE_RAMROD_MODIFY_QP,
8389 ROCE_RAMROD_QUERY_QP,
8390 ROCE_RAMROD_DESTROY_QP,
8391 ROCE_RAMROD_CREATE_UD_QP,
8392 ROCE_RAMROD_DESTROY_UD_QP,
8393 ROCE_RAMROD_FUNC_UPDATE,
8394 MAX_ROCE_RAMROD_CMD_ID
8397 /* RoCE func init ramrod data */
8398 struct roce_update_func_params {
8399 u8 cnp_vlan_priority;
8402 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
8403 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
8404 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
8405 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
8406 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF
8407 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT 2
8408 __le32 cnp_send_timeout;
8411 struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
8415 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
8416 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
8417 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
8418 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
8419 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
8420 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
8421 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
8422 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
8423 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
8424 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
8425 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
8426 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
8427 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
8428 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
8429 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
8430 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
8432 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
8433 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
8434 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
8435 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
8436 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
8437 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
8438 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
8439 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
8440 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
8441 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4
8442 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
8443 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5
8444 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
8445 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
8446 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
8447 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
8449 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
8450 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
8451 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
8452 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
8453 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
8454 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
8455 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
8456 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
8458 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
8459 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
8460 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
8461 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
8462 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
8463 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
8464 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
8465 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
8467 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
8468 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
8469 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
8470 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
8471 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
8472 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
8473 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
8474 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
8476 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
8477 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
8478 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
8479 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
8480 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
8481 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
8482 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
8483 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
8485 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
8486 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
8487 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
8488 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
8489 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
8490 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
8491 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
8492 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
8494 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
8495 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
8496 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
8497 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
8498 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
8499 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
8500 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
8501 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
8502 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
8503 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
8505 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
8506 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
8507 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
8508 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
8509 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
8510 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
8511 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
8512 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
8513 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
8514 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
8515 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
8516 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
8517 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
8518 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
8519 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
8520 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
8522 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
8523 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
8524 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
8525 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
8526 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
8527 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
8528 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
8529 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
8530 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
8531 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
8532 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
8533 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
8534 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
8535 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
8536 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
8537 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
8539 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
8540 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
8541 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
8542 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
8543 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
8544 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
8545 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
8546 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
8547 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
8548 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
8549 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
8550 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
8551 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
8552 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
8553 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
8554 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
8556 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
8557 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
8558 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
8559 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
8560 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
8561 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
8562 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
8563 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
8564 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
8565 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
8566 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
8567 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
8568 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
8569 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
8570 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
8571 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
8573 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
8574 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
8575 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
8576 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
8577 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
8578 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
8579 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
8580 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
8581 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
8582 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
8583 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
8584 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
8585 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
8586 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
8587 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
8588 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
8590 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
8591 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
8592 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
8593 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
8594 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
8595 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
8596 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
8597 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
8598 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
8599 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
8600 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
8601 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
8602 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
8603 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
8604 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
8605 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
8607 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
8608 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
8609 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
8610 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
8611 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
8612 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
8613 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
8614 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
8615 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
8616 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
8617 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
8618 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
8638 struct e4_mstorm_roce_conn_ag_ctx {
8642 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
8643 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
8644 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
8645 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
8646 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8647 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2
8648 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8649 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4
8650 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8651 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6
8653 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
8654 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
8655 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
8656 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1
8657 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
8658 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2
8659 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
8660 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
8661 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
8662 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
8663 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
8664 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
8665 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
8666 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
8667 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
8668 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
8675 struct e4_mstorm_roce_req_conn_ag_ctx {
8679 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8680 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8681 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8682 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8683 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8684 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8685 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8686 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8687 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8688 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8690 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8691 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8692 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8693 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8694 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8695 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8696 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8697 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
8698 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8699 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
8700 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8701 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
8702 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8703 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
8704 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8705 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
8712 struct e4_mstorm_roce_resp_conn_ag_ctx {
8716 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8717 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8718 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8719 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8720 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8721 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8722 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8723 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8724 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8725 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8727 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8728 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8729 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8730 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8731 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8732 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8733 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8734 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
8735 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8736 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
8737 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8738 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
8739 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8740 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8741 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8742 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
8749 struct e4_tstorm_roce_req_conn_ag_ctx {
8753 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8754 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8755 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
8756 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
8757 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
8758 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
8759 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
8760 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
8761 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8762 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
8763 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8764 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
8765 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
8766 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
8768 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
8769 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
8770 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
8771 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
8772 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
8773 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
8774 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8775 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8777 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
8778 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0
8779 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
8780 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
8781 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
8782 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
8783 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
8784 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
8786 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
8787 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
8788 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
8789 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
8790 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
8791 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
8792 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8793 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
8794 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
8795 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
8796 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
8797 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
8799 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8800 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8801 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1
8802 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1
8803 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
8804 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
8805 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
8806 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
8807 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
8808 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
8809 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
8810 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
8811 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
8812 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
8813 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8814 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
8816 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8817 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8818 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
8819 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1
8820 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8821 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
8822 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8823 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
8824 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8825 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
8826 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
8827 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
8828 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8829 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
8830 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8831 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
8832 __le32 dif_rxmit_cnt;
8837 __le32 dif_acked_cnt;
8841 u8 tx_cqe_error_type;
8843 __le16 snd_sq_cons_th;
8848 __le16 force_comp_cons;
8849 __le32 dif_rxmit_acked_cnt;
8853 struct e4_tstorm_roce_resp_conn_ag_ctx {
8857 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8858 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8859 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
8860 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
8861 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
8862 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
8863 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
8864 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
8865 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8866 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
8867 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
8868 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
8869 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8870 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
8872 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
8873 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
8874 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
8875 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
8876 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8877 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
8878 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8879 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8881 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8882 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
8883 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8884 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
8885 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
8886 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
8887 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8888 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
8890 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8891 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
8892 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8893 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
8894 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8895 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
8896 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8897 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
8898 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
8899 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
8900 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8901 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
8903 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8904 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8905 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8906 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1
8907 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8908 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
8909 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
8910 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
8911 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8912 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
8913 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8914 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
8915 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8916 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
8917 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8918 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
8920 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8921 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8922 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8923 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8924 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8925 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8926 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8927 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8928 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8929 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8930 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
8931 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
8932 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8933 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8934 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8935 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
8936 __le32 psn_and_rxmit_id_echo;
8945 u8 tx_async_error_type;
8957 struct e4_ustorm_roce_req_conn_ag_ctx {
8961 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8962 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8963 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8964 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8965 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8966 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8967 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8968 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8969 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8970 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8972 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8973 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
8974 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
8975 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
8976 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
8977 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
8978 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
8979 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
8981 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8982 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8983 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8984 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8985 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8986 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8987 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8988 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
8989 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
8990 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
8991 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
8992 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
8993 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
8994 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
8995 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8996 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
8998 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8999 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
9000 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
9001 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
9002 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
9003 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
9004 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
9005 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
9006 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
9007 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
9008 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
9009 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
9010 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
9011 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
9012 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
9013 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
9026 struct e4_ustorm_roce_resp_conn_ag_ctx {
9030 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
9031 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
9032 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
9033 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
9034 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
9035 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
9036 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
9037 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
9038 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
9039 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
9041 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
9042 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
9043 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
9044 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
9045 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
9046 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
9047 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
9048 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
9050 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
9051 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
9052 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
9053 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
9054 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
9055 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
9056 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
9057 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
9058 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
9059 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
9060 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
9061 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
9062 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
9063 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
9064 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
9065 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
9067 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
9068 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
9069 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
9070 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
9071 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
9072 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
9073 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
9074 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
9075 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
9076 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
9077 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
9078 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
9079 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
9080 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
9081 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
9082 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
9095 struct e4_xstorm_roce_req_conn_ag_ctx {
9099 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9100 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9101 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
9102 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
9103 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
9104 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
9105 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9106 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9107 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
9108 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
9109 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
9110 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
9111 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
9112 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
9113 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
9114 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
9116 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
9117 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
9118 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
9119 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
9120 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
9121 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
9122 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
9123 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
9124 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
9125 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
9126 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
9127 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
9128 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
9129 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
9130 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
9131 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
9133 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
9134 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
9135 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
9136 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
9137 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
9138 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
9139 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
9140 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
9142 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
9143 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
9144 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
9145 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
9146 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
9147 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
9148 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
9149 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
9151 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
9152 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0
9153 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
9154 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2
9155 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
9156 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
9157 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
9158 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
9160 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
9161 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
9162 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
9163 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
9164 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
9165 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
9166 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
9167 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
9169 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
9170 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
9171 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
9172 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
9173 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
9174 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
9175 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
9176 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
9178 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
9179 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
9180 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
9181 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
9182 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9183 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9184 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
9185 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
9186 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
9187 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
9189 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
9190 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
9191 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
9192 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
9193 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
9194 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
9195 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
9196 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
9197 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
9198 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
9199 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9200 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
9201 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
9202 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6
9203 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1
9204 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7
9206 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
9207 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
9208 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
9209 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
9210 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
9211 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
9212 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
9213 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
9214 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
9215 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
9216 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
9217 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
9218 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
9219 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
9220 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
9221 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
9223 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
9224 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
9225 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
9226 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
9227 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
9228 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
9229 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
9230 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
9231 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9232 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9233 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
9234 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
9235 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
9236 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
9237 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
9238 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
9240 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
9241 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
9242 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
9243 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
9244 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
9245 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
9246 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
9247 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
9248 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
9249 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
9250 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
9251 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
9252 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9253 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9254 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
9255 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
9257 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
9258 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
9259 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
9260 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
9261 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9262 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9263 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9264 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9265 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
9266 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
9267 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
9268 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
9269 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
9270 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
9271 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
9272 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
9274 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
9275 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
9276 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
9277 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
9278 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9279 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
9280 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9281 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
9282 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9283 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9284 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9285 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
9286 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9287 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9288 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9289 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9291 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
9292 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
9293 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
9294 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
9295 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
9296 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
9297 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
9298 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
9299 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
9300 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
9301 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
9302 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
9309 __le16 dif_error_first_sq_cons;
9311 u8 dif_error_sge_index;
9319 __le32 dif_error_offset;
9324 struct e4_xstorm_roce_resp_conn_ag_ctx {
9328 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9329 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9330 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
9331 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
9332 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
9333 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
9334 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9335 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9336 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
9337 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
9338 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
9339 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
9340 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
9341 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
9342 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
9343 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
9345 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
9346 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
9347 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
9348 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
9349 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
9350 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
9351 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
9352 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
9353 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
9354 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
9355 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
9356 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
9357 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
9358 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
9359 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
9360 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
9362 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
9363 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
9364 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
9365 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
9366 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
9367 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
9368 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
9369 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
9371 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
9372 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
9373 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
9374 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
9375 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
9376 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
9377 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
9378 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
9380 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
9381 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
9382 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
9383 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
9384 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
9385 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
9386 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
9387 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
9389 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
9390 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
9391 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
9392 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
9393 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
9394 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
9395 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
9396 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
9398 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
9399 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
9400 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
9401 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
9402 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
9403 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
9404 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
9405 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
9407 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
9408 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
9409 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
9410 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
9411 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9412 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9413 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
9414 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
9415 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
9416 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
9418 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
9419 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
9420 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
9421 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
9422 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
9423 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
9424 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
9425 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
9426 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
9427 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
9428 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9429 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
9430 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
9431 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
9432 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
9433 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
9435 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
9436 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
9437 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
9438 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
9439 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
9440 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
9441 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
9442 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
9443 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
9444 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
9445 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
9446 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
9447 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
9448 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
9449 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
9450 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
9452 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
9453 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
9454 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
9455 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
9456 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
9457 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
9458 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
9459 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
9460 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9461 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9462 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
9463 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
9464 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
9465 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
9466 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
9467 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
9469 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
9470 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
9471 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
9472 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
9473 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
9474 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
9475 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
9476 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
9477 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
9478 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
9479 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
9480 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
9481 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9482 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9483 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
9484 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
9486 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
9487 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
9488 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
9489 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
9490 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9491 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9492 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9493 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9494 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
9495 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
9496 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
9497 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
9498 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
9499 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
9500 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
9501 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
9503 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
9504 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
9505 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
9506 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
9507 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9508 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
9509 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9510 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
9511 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9512 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9513 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9514 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
9515 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9516 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9517 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9518 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9520 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
9521 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
9522 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
9523 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
9524 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
9525 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
9526 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
9527 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
9528 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
9529 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
9530 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
9531 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
9532 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
9533 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
9536 __le16 irq_prod_shadow;
9540 __le16 e5_reserved1;
9546 __le32 rxmit_psn_and_id;
9547 __le32 rxmit_bytes_length;
9552 __le32 msn_and_syndrome;
9555 struct e4_ystorm_roce_conn_ag_ctx {
9559 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
9560 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
9561 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
9562 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
9563 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
9564 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2
9565 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
9566 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4
9567 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
9568 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6
9570 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
9571 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
9572 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
9573 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1
9574 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
9575 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2
9576 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
9577 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
9578 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
9579 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
9580 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
9581 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
9582 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
9583 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
9584 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
9585 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
9599 struct e4_ystorm_roce_req_conn_ag_ctx {
9603 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
9604 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
9605 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
9606 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
9607 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
9608 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
9609 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
9610 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
9611 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
9612 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
9614 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
9615 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
9616 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
9617 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
9618 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
9619 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
9620 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
9621 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
9622 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
9623 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
9624 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
9625 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
9626 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
9627 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
9628 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
9629 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
9643 struct e4_ystorm_roce_resp_conn_ag_ctx {
9647 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
9648 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
9649 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
9650 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
9651 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
9652 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
9653 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
9654 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
9655 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
9656 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
9658 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
9659 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
9660 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
9661 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
9662 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
9663 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
9664 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
9665 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
9666 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
9667 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
9668 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
9669 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
9670 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
9671 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
9672 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
9673 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
9687 /* Roce doorbell data */
9695 /* The iwarp storm context of Ystorm */
9696 struct ystorm_iwarp_conn_st_ctx {
9700 /* The iwarp storm context of Pstorm */
9701 struct pstorm_iwarp_conn_st_ctx {
9702 __le32 reserved[36];
9705 /* The iwarp storm context of Xstorm */
9706 struct xstorm_iwarp_conn_st_ctx {
9707 __le32 reserved[48];
9710 struct e4_xstorm_iwarp_conn_ag_ctx {
9714 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9715 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9716 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
9717 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
9718 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
9719 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
9720 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9721 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9722 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9723 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
9724 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
9725 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
9726 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
9727 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
9728 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
9729 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
9731 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
9732 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
9733 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
9734 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
9735 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
9736 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
9737 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
9738 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
9739 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
9740 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
9741 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
9742 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
9743 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
9744 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
9745 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
9746 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
9748 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9749 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
9750 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9751 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
9752 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9753 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
9754 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9755 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
9757 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9758 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
9759 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9760 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
9761 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9762 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
9763 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9764 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
9766 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9767 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
9768 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
9769 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
9770 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
9771 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
9772 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
9773 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
9775 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
9776 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
9777 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
9778 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
9779 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
9780 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
9781 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
9782 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
9784 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
9785 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9786 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
9787 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
9788 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
9789 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
9790 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
9791 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
9793 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9794 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9795 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
9796 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
9797 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9798 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9799 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9800 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
9801 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9802 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
9804 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9805 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
9806 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9807 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
9808 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9809 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
9810 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9811 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
9812 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9813 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
9814 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9815 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
9816 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9817 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
9818 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
9819 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
9821 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
9822 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
9823 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
9824 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
9825 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
9826 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
9827 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
9828 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
9829 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
9830 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
9831 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
9832 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
9833 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9834 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
9835 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
9836 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
9838 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
9839 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
9840 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
9841 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
9842 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9843 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
9844 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
9845 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
9846 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9847 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9848 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1
9849 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5
9850 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9851 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
9852 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
9853 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
9855 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
9856 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
9857 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9858 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
9859 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
9860 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
9861 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9862 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
9863 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9864 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
9865 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9866 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
9867 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9868 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9869 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
9870 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
9872 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
9873 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
9874 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
9875 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
9876 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9877 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9878 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9879 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9880 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
9881 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
9882 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
9883 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
9884 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
9885 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
9886 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
9887 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
9889 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
9890 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
9891 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
9892 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
9893 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
9894 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
9895 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
9896 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
9897 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9898 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9899 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
9900 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
9901 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9902 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9903 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9904 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9906 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
9907 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
9908 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
9909 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
9910 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
9911 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
9912 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
9913 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
9914 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
9915 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
9916 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
9917 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
9918 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
9919 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6
9923 __le16 sq_comp_cons;
9935 __le32 more_to_send_seq;
9937 __le32 rewinded_snd_max_or_term_opcode;
9939 __le16 irq_prod_via_msdm;
9941 __le16 hq_cons_th_or_mpa_data;
9947 u8 wqe_data_pad_bytes;
9950 u8 irq_prod_via_msem;
9952 u8 max_pkt_pdu_size_lo;
9953 u8 max_pkt_pdu_size_hi;
9956 __le16 e5_reserved4;
9959 __le32 shared_queue_page_addr_lo;
9960 __le32 shared_queue_page_addr_hi;
9967 struct e4_tstorm_iwarp_conn_ag_ctx {
9971 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9972 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9973 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9974 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9975 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
9976 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
9977 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1
9978 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3
9979 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9980 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
9981 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
9982 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
9983 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9984 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
9986 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
9987 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
9988 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
9989 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
9990 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9991 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
9992 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9993 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
9995 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9996 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
9997 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9998 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
9999 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
10000 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
10001 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
10002 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
10004 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
10005 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
10006 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
10007 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
10008 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
10009 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
10010 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
10011 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
10012 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
10013 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
10014 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10015 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
10017 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
10018 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
10019 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
10020 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
10021 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
10022 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
10023 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
10024 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
10025 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
10026 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
10027 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
10028 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
10029 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
10030 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
10031 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
10032 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
10034 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
10035 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
10036 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10037 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
10038 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
10039 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
10040 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10041 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
10042 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
10043 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
10044 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
10045 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
10046 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
10047 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
10048 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
10049 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
10052 __le32 unaligned_nxt_seq;
10061 __le16 sq_tx_cons_th;
10068 __le32 last_hq_sequence;
10071 /* The iwarp storm context of Tstorm */
10072 struct tstorm_iwarp_conn_st_ctx {
10073 __le32 reserved[60];
10076 /* The iwarp storm context of Mstorm */
10077 struct mstorm_iwarp_conn_st_ctx {
10078 __le32 reserved[32];
10081 /* The iwarp storm context of Ustorm */
10082 struct ustorm_iwarp_conn_st_ctx {
10083 struct regpair reserved[14];
10086 /* iwarp connection context */
10087 struct e4_iwarp_conn_context {
10088 struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
10089 struct regpair ystorm_st_padding[2];
10090 struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
10091 struct regpair pstorm_st_padding[2];
10092 struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
10093 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
10094 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
10095 struct timers_context timer_context;
10096 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
10097 struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
10098 struct regpair tstorm_st_padding[2];
10099 struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
10100 struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
10101 struct regpair ustorm_st_padding[2];
10104 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
10105 struct iwarp_create_qp_ramrod_data {
10107 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
10108 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
10109 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
10110 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
10111 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
10112 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
10113 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
10114 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
10115 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
10116 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
10117 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
10118 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
10119 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1
10120 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6
10121 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1
10122 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7
10125 __le16 sq_num_pages;
10126 __le16 rq_num_pages;
10127 __le32 reserved3[2];
10128 struct regpair qp_handle_for_cqe;
10129 struct rdma_srq_id srq_id;
10130 __le32 cq_cid_for_sq;
10131 __le32 cq_cid_for_rq;
10133 __le16 physical_q0;
10134 __le16 physical_q1;
10138 /* iWARP completion queue types */
10139 enum iwarp_eqe_async_opcode {
10140 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
10141 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
10142 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
10143 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
10144 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
10145 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
10146 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
10147 IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY,
10148 IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT,
10149 MAX_IWARP_EQE_ASYNC_OPCODE
10152 struct iwarp_eqe_data_mpa_async_completion {
10153 __le16 ulp_data_len;
10158 struct iwarp_eqe_data_tcp_async_completion {
10159 __le16 ulp_data_len;
10160 u8 mpa_handshake_mode;
10164 /* iWARP completion queue types */
10165 enum iwarp_eqe_sync_opcode {
10166 IWARP_EVENT_TYPE_TCP_OFFLOAD =
10168 IWARP_EVENT_TYPE_MPA_OFFLOAD,
10169 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
10170 IWARP_EVENT_TYPE_CREATE_QP,
10171 IWARP_EVENT_TYPE_QUERY_QP,
10172 IWARP_EVENT_TYPE_MODIFY_QP,
10173 IWARP_EVENT_TYPE_DESTROY_QP,
10174 IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD,
10175 MAX_IWARP_EQE_SYNC_OPCODE
10178 /* iWARP EQE completion status */
10179 enum iwarp_fw_return_code {
10180 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6,
10181 IWARP_CONN_ERROR_TCP_CONNECTION_RST,
10182 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
10183 IWARP_CONN_ERROR_MPA_ERROR_REJECT,
10184 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
10185 IWARP_CONN_ERROR_MPA_RST,
10186 IWARP_CONN_ERROR_MPA_FIN,
10187 IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
10188 IWARP_CONN_ERROR_MPA_INSUF_IRD,
10189 IWARP_CONN_ERROR_MPA_INVALID_PACKET,
10190 IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
10191 IWARP_CONN_ERROR_MPA_TIMEOUT,
10192 IWARP_CONN_ERROR_MPA_TERMINATE,
10193 IWARP_QP_IN_ERROR_GOOD_CLOSE,
10194 IWARP_QP_IN_ERROR_BAD_CLOSE,
10195 IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
10196 IWARP_EXCEPTION_DETECTED_LLP_RESET,
10197 IWARP_EXCEPTION_DETECTED_IRQ_FULL,
10198 IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
10199 IWARP_EXCEPTION_DETECTED_SRQ_EMPTY,
10200 IWARP_EXCEPTION_DETECTED_SRQ_LIMIT,
10201 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
10202 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
10203 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
10204 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
10205 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
10206 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
10207 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
10208 MAX_IWARP_FW_RETURN_CODE
10211 /* unaligned opaque data received from LL2 */
10212 struct iwarp_init_func_params {
10213 u8 ll2_ooo_q_index;
10217 /* iwarp func init ramrod data */
10218 struct iwarp_init_func_ramrod_data {
10219 struct rdma_init_func_ramrod_data rdma;
10220 struct tcp_init_params tcp;
10221 struct iwarp_init_func_params iwarp;
10224 /* iWARP QP - possible states to transition to */
10225 enum iwarp_modify_qp_new_state_type {
10226 IWARP_MODIFY_QP_STATE_CLOSING = 1,
10227 IWARP_MODIFY_QP_STATE_ERROR = 2,
10228 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
10231 /* iwarp modify qp responder ramrod data */
10232 struct iwarp_modify_qp_ramrod_data {
10233 __le16 transition_to_state;
10235 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
10236 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
10237 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
10238 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
10239 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
10240 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
10241 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
10242 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
10243 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
10244 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
10245 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
10246 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5
10247 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF
10248 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6
10249 __le16 physical_q0;
10250 __le16 physical_q1;
10251 __le32 reserved1[10];
10254 /* MPA params for Enhanced mode */
10255 struct mpa_rq_params {
10260 /* MPA host Address-Len for private data */
10261 struct mpa_ulp_buffer {
10262 struct regpair addr;
10264 __le16 reserved[3];
10267 /* iWARP MPA offload params common to Basic and Enhanced modes */
10268 struct mpa_outgoing_params {
10272 struct mpa_rq_params out_rq;
10273 struct mpa_ulp_buffer outgoing_ulp_buffer;
10276 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request
10279 struct iwarp_mpa_offload_ramrod_data {
10280 struct mpa_outgoing_params common;
10283 u8 tcp_connect_side;
10285 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
10286 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
10287 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
10288 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
10290 struct mpa_ulp_buffer incoming_ulp_buffer;
10291 struct regpair async_eqe_output_buf;
10292 struct regpair handle_for_async;
10293 struct regpair shared_queue_addr;
10295 u8 stats_counter_id;
10299 /* iWARP TCP connection offload params passed by driver to FW */
10300 struct iwarp_offload_params {
10301 struct mpa_ulp_buffer incoming_ulp_buffer;
10302 struct regpair async_eqe_output_buf;
10303 struct regpair handle_for_async;
10304 __le16 physical_q0;
10305 __le16 physical_q1;
10306 u8 stats_counter_id;
10311 /* iWARP query QP output params */
10312 struct iwarp_query_qp_output_params {
10314 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
10315 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
10316 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
10317 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
10321 /* iWARP query QP ramrod data */
10322 struct iwarp_query_qp_ramrod_data {
10323 struct regpair output_params_addr;
10326 /* iWARP Ramrod Command IDs */
10327 enum iwarp_ramrod_cmd_id {
10328 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
10329 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
10330 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
10331 IWARP_RAMROD_CMD_ID_CREATE_QP,
10332 IWARP_RAMROD_CMD_ID_QUERY_QP,
10333 IWARP_RAMROD_CMD_ID_MODIFY_QP,
10334 IWARP_RAMROD_CMD_ID_DESTROY_QP,
10335 IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD,
10336 MAX_IWARP_RAMROD_CMD_ID
10339 /* Per PF iWARP retransmit path statistics */
10340 struct iwarp_rxmit_stats_drv {
10341 struct regpair tx_go_to_slow_start_event_cnt;
10342 struct regpair tx_fast_retransmit_event_cnt;
10345 /* iWARP and TCP connection offload params passed by driver to FW in iWARP
10348 struct iwarp_tcp_offload_ramrod_data {
10349 struct tcp_offload_params_opt2 tcp;
10350 struct iwarp_offload_params iwarp;
10353 /* iWARP MPA negotiation types */
10354 enum mpa_negotiation_mode {
10355 MPA_NEGOTIATION_TYPE_BASIC = 1,
10356 MPA_NEGOTIATION_TYPE_ENHANCED = 2,
10357 MAX_MPA_NEGOTIATION_MODE
10360 /* iWARP MPA Enhanced mode RTR types */
10361 enum mpa_rtr_type {
10362 MPA_RTR_TYPE_NONE = 0,
10363 MPA_RTR_TYPE_ZERO_SEND = 1,
10364 MPA_RTR_TYPE_ZERO_WRITE = 2,
10365 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
10366 MPA_RTR_TYPE_ZERO_READ = 4,
10367 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
10368 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
10369 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
10373 /* unaligned opaque data received from LL2 */
10374 struct unaligned_opaque_data {
10375 __le16 first_mpa_offset;
10376 u8 tcp_payload_offset;
10378 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
10379 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
10380 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
10381 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
10382 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
10383 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
10387 struct e4_mstorm_iwarp_conn_ag_ctx {
10391 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10392 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10393 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
10394 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
10395 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
10396 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
10397 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
10398 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
10399 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
10400 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
10402 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
10403 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
10404 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
10405 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
10406 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
10407 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
10408 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
10409 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
10410 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
10411 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
10412 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10413 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
10414 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
10415 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
10416 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10417 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
10419 __le16 rcq_cons_th;
10424 struct e4_ustorm_iwarp_conn_ag_ctx {
10428 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10429 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10430 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
10431 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
10432 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
10433 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
10434 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
10435 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
10436 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
10437 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
10439 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
10440 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
10441 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
10442 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
10443 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
10444 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
10445 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
10446 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
10448 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
10449 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
10450 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
10451 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
10452 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
10453 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
10454 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
10455 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
10456 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
10457 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
10458 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
10459 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
10460 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
10461 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
10462 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
10463 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
10465 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
10466 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
10467 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10468 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
10469 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
10470 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
10471 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10472 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
10473 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
10474 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
10475 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
10476 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
10477 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
10478 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
10479 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
10480 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
10493 struct e4_ystorm_iwarp_conn_ag_ctx {
10497 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
10498 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
10499 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
10500 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
10501 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
10502 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
10503 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
10504 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
10505 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
10506 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
10508 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
10509 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
10510 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
10511 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
10512 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
10513 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
10514 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
10515 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
10516 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
10517 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
10518 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10519 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
10520 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
10521 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
10522 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10523 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
10537 /* The fcoe storm context of Ystorm */
10538 struct ystorm_fcoe_conn_st_ctx {
10543 __le16 stat_ram_addr;
10545 __le16 max_fc_payload_len;
10546 __le16 tx_max_fc_pay_len;
10550 struct regpair reserved;
10551 __le16 min_frame_size;
10552 u8 protection_info_flags;
10553 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
10554 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
10555 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
10556 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
10557 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
10558 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
10559 u8 dst_protection_per_mss;
10560 u8 src_protection_per_mss;
10561 u8 ptu_log_page_size;
10563 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10564 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
10565 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
10566 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
10567 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
10568 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
10572 /* FCoE 16-bits vlan structure */
10573 struct fcoe_vlan_fields {
10575 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
10576 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
10577 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
10578 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
10579 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7
10580 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
10583 /* FCoE 16-bits vlan union */
10584 union fcoe_vlan_field_union {
10585 struct fcoe_vlan_fields fields;
10589 /* FCoE 16-bits vlan, vif union */
10590 union fcoe_vlan_vif_field_union {
10591 union fcoe_vlan_field_union vlan;
10595 /* Ethernet context section */
10596 struct pstorm_fcoe_eth_context_section {
10609 union fcoe_vlan_vif_field_union vif_outer_vlan;
10610 __le16 vif_outer_eth_type;
10611 union fcoe_vlan_vif_field_union inner_vlan;
10612 __le16 inner_eth_type;
10615 /* The fcoe storm context of Pstorm */
10616 struct pstorm_fcoe_conn_st_ctx {
10621 __le16 stat_ram_addr;
10623 struct regpair abts_cleanup_addr;
10624 struct pstorm_fcoe_eth_context_section eth;
10629 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
10630 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
10631 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
10632 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
10633 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10634 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
10635 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
10636 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
10637 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
10638 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4
10639 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7
10640 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5
10645 __le16 rec_rr_tov_val;
10646 u8 q_relative_offset;
10650 /* The fcoe storm context of Xstorm */
10651 struct xstorm_fcoe_conn_st_ctx {
10655 u8 cached_wqes_avail;
10656 __le16 stat_ram_addr;
10658 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
10659 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
10660 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10661 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
10662 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
10663 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
10664 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
10665 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
10666 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
10667 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
10668 u8 cached_wqes_offset;
10673 __le16 num_pages_in_pbl;
10675 struct regpair sq_pbl_addr;
10676 struct regpair sq_curr_page_addr;
10677 struct regpair sq_next_page_addr;
10678 struct regpair xferq_pbl_addr;
10679 struct regpair xferq_curr_page_addr;
10680 struct regpair xferq_next_page_addr;
10681 struct regpair respq_pbl_addr;
10682 struct regpair respq_curr_page_addr;
10683 struct regpair respq_next_page_addr;
10685 __le16 tx_max_fc_pay_len;
10686 __le16 max_fc_payload_len;
10687 __le16 min_frame_size;
10688 __le16 sq_pbl_next_index;
10689 __le16 respq_pbl_next_index;
10690 u8 fcp_cmd_byte_credit;
10691 u8 fcp_rsp_byte_credit;
10692 __le16 protection_info;
10693 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
10694 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
10695 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
10696 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
10697 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
10698 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
10699 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
10700 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
10701 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
10702 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
10703 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
10704 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
10705 __le16 xferq_pbl_next_index;
10708 u8 fcp_xfer_byte_credit;
10710 struct fcoe_wqe cached_wqes[16];
10713 struct e4_xstorm_fcoe_conn_ag_ctx {
10717 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10718 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10719 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
10720 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
10721 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
10722 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
10723 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10724 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
10725 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
10726 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
10727 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
10728 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
10729 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
10730 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
10731 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
10732 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
10734 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
10735 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
10736 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
10737 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
10738 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
10739 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
10740 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
10741 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
10742 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
10743 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
10744 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
10745 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
10746 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
10747 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
10748 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
10749 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
10751 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10752 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
10753 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10754 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
10755 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10756 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
10757 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10758 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
10760 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10761 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
10762 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10763 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
10764 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10765 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
10766 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10767 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
10769 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10770 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
10771 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10772 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
10773 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10774 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
10775 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
10776 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
10778 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
10779 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
10780 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
10781 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
10782 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
10783 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
10784 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
10785 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
10787 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
10788 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
10789 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
10790 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
10791 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
10792 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
10793 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
10794 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
10796 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10797 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10798 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
10799 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
10800 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10801 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
10802 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10803 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
10804 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10805 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
10807 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10808 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
10809 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10810 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
10811 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10812 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
10813 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10814 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
10815 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10816 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
10817 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10818 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
10819 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10820 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
10821 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10822 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
10824 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10825 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
10826 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
10827 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
10828 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
10829 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
10830 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
10831 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
10832 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
10833 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
10834 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
10835 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
10836 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
10837 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
10838 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
10839 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
10841 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
10842 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
10843 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
10844 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
10845 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10846 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
10847 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
10848 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
10849 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10850 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
10851 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
10852 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
10853 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
10854 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
10855 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
10856 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
10858 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
10859 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
10860 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
10861 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
10862 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
10863 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
10864 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10865 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
10866 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10867 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
10868 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10869 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
10870 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10871 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
10872 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
10873 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
10875 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
10876 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
10877 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
10878 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
10879 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10880 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
10881 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10882 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
10883 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
10884 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
10885 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
10886 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
10887 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
10888 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
10889 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
10890 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
10892 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
10893 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
10894 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
10895 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
10896 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10897 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
10898 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10899 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
10900 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10901 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
10902 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10903 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
10904 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10905 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
10906 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10907 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
10909 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
10910 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
10911 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
10912 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
10913 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
10914 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
10915 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
10916 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
10917 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
10918 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
10919 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
10920 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
10921 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
10922 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
10924 __le16 physical_q0;
10950 /* The fcoe storm context of Ustorm */
10951 struct ustorm_fcoe_conn_st_ctx {
10952 struct regpair respq_pbl_addr;
10953 __le16 num_pages_in_pbl;
10954 u8 ptu_log_page_size;
10960 struct e4_tstorm_fcoe_conn_ag_ctx {
10964 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10965 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10966 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10967 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10968 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
10969 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
10970 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
10971 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
10972 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
10973 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
10974 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
10975 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
10976 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
10977 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
10979 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
10980 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
10981 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10982 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
10983 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
10984 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
10985 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10986 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
10988 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10989 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
10990 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10991 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
10992 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10993 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
10994 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10995 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
10997 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10998 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
10999 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
11000 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
11001 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
11002 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
11003 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
11004 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
11005 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
11006 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
11007 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
11008 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
11010 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
11011 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
11012 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
11013 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
11014 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
11015 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
11016 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
11017 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
11018 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
11019 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
11020 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
11021 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
11022 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
11023 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
11024 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
11025 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
11027 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
11028 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
11029 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
11030 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
11031 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
11032 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
11033 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
11034 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
11035 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
11036 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
11037 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
11038 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
11039 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
11040 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
11041 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
11042 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
11047 struct e4_ustorm_fcoe_conn_ag_ctx {
11051 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
11052 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
11053 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
11054 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
11055 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
11056 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
11057 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
11058 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
11059 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
11060 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
11062 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
11063 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
11064 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
11065 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
11066 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
11067 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
11068 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
11069 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
11071 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
11072 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
11073 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
11074 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
11075 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
11076 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
11077 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
11078 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
11079 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
11080 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
11081 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
11082 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
11083 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
11084 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
11085 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
11086 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
11088 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
11089 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
11090 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
11091 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
11092 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
11093 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
11094 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
11095 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
11096 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
11097 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
11098 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
11099 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
11100 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
11101 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
11102 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
11103 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
11116 /* The fcoe storm context of Tstorm */
11117 struct tstorm_fcoe_conn_st_ctx {
11118 __le16 stat_ram_addr;
11119 __le16 rx_max_fc_payload_len;
11120 __le16 e_d_tov_val;
11122 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
11123 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
11124 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
11125 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
11126 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
11127 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
11128 u8 timers_cleanup_invocation_cnt;
11129 __le32 reserved1[2];
11130 __le32 dst_mac_address_bytes_0_to_3;
11131 __le16 dst_mac_address_bytes_4_to_5;
11132 __le16 ramrod_echo;
11134 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
11135 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
11136 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
11137 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
11138 u8 cq_relative_offset;
11139 u8 cmdq_relative_offset;
11140 u8 bdq_resource_id;
11144 struct e4_mstorm_fcoe_conn_ag_ctx {
11148 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
11149 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
11150 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
11151 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
11152 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
11153 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
11154 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
11155 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
11156 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
11157 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
11159 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
11160 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
11161 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
11162 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
11163 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
11164 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
11165 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
11166 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
11167 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
11168 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
11169 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
11170 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
11171 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
11172 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
11173 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
11174 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
11181 /* Fast path part of the fcoe storm context of Mstorm */
11182 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
11186 u8 protection_info;
11187 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
11188 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
11189 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
11190 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
11191 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
11192 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
11193 u8 q_relative_offset;
11197 /* Non fast path part of the fcoe storm context of Mstorm */
11198 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
11200 __le16 stat_ram_addr;
11201 __le16 num_pages_in_pbl;
11202 u8 ptu_log_page_size;
11204 __le16 unsolicited_cq_count;
11206 u8 bdq_resource_id;
11208 struct regpair xferq_pbl_addr;
11209 struct regpair reserved1;
11210 struct regpair reserved2[3];
11213 /* The fcoe storm context of Mstorm */
11214 struct mstorm_fcoe_conn_st_ctx {
11215 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
11216 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
11219 /* fcoe connection context */
11220 struct e4_fcoe_conn_context {
11221 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
11222 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
11223 struct regpair pstorm_st_padding[2];
11224 struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
11225 struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
11226 struct regpair xstorm_ag_padding[6];
11227 struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
11228 struct regpair ustorm_st_padding[2];
11229 struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
11230 struct regpair tstorm_ag_padding[2];
11231 struct timers_context timer_context;
11232 struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
11233 struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
11234 struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
11235 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
11238 /* FCoE connection offload params passed by driver to FW in FCoE offload
11241 struct fcoe_conn_offload_ramrod_params {
11242 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
11245 /* FCoE connection terminate params passed by driver to FW in FCoE terminate
11248 struct fcoe_conn_terminate_ramrod_params {
11249 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
11252 /* FCoE event type */
11253 enum fcoe_event_type {
11254 FCOE_EVENT_INIT_FUNC,
11255 FCOE_EVENT_DESTROY_FUNC,
11256 FCOE_EVENT_STAT_FUNC,
11257 FCOE_EVENT_OFFLOAD_CONN,
11258 FCOE_EVENT_TERMINATE_CONN,
11260 MAX_FCOE_EVENT_TYPE
11263 /* FCoE init params passed by driver to FW in FCoE init ramrod */
11264 struct fcoe_init_ramrod_params {
11265 struct fcoe_init_func_ramrod_data init_ramrod_data;
11268 /* FCoE ramrod Command IDs */
11269 enum fcoe_ramrod_cmd_id {
11270 FCOE_RAMROD_CMD_ID_INIT_FUNC,
11271 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
11272 FCOE_RAMROD_CMD_ID_STAT_FUNC,
11273 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
11274 FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
11275 MAX_FCOE_RAMROD_CMD_ID
11278 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics
11281 struct fcoe_stat_ramrod_params {
11282 struct fcoe_stat_ramrod_data stat_ramrod_data;
11285 struct e4_ystorm_fcoe_conn_ag_ctx {
11289 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
11290 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
11291 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
11292 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
11293 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
11294 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
11295 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
11296 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
11297 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
11298 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
11300 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
11301 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
11302 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
11303 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
11304 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
11305 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
11306 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
11307 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
11308 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
11309 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
11310 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
11311 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
11312 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
11313 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
11314 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
11315 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
11329 /* The iscsi storm connection context of Ystorm */
11330 struct ystorm_iscsi_conn_st_ctx {
11331 __le32 reserved[8];
11334 /* Combined iSCSI and TCP storm connection of Pstorm */
11335 struct pstorm_iscsi_tcp_conn_st_ctx {
11340 /* The combined tcp and iscsi storm context of Xstorm */
11341 struct xstorm_iscsi_tcp_conn_st_ctx {
11342 __le32 reserved_tcp[4];
11343 __le32 reserved_iscsi[44];
11346 struct e4_xstorm_iscsi_conn_ag_ctx {
11350 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
11351 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
11352 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
11353 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
11354 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
11355 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
11356 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
11357 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
11358 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
11359 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
11360 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
11361 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
11362 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
11363 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
11364 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
11365 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
11367 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
11368 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
11369 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
11370 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
11371 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
11372 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
11373 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
11374 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
11375 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
11376 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
11377 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
11378 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
11379 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
11380 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
11381 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
11382 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
11384 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11385 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
11386 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11387 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
11388 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11389 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
11390 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
11391 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
11393 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
11394 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
11395 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
11396 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
11397 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
11398 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
11399 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
11400 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
11402 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
11403 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
11404 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
11405 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
11406 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
11407 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
11408 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
11409 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
11411 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
11412 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
11413 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
11414 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
11415 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
11416 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
11417 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
11418 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
11420 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
11421 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
11422 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
11423 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
11424 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
11425 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
11426 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
11427 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
11429 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
11430 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
11431 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
11432 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
11433 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
11434 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
11435 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11436 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
11437 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11438 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
11440 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11441 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
11442 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
11443 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
11444 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11445 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
11446 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11447 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
11448 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11449 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
11450 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
11451 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
11452 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
11453 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
11454 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
11455 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
11457 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
11458 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
11459 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
11460 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
11461 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
11462 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
11463 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
11464 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
11465 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
11466 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
11467 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
11468 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
11469 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
11470 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
11471 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
11472 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
11474 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
11475 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
11476 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
11477 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
11478 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
11479 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
11480 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
11481 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
11482 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
11483 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
11484 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
11485 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
11486 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11487 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
11488 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
11489 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
11491 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
11492 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
11493 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11494 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
11495 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
11496 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
11497 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11498 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
11499 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11500 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
11501 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11502 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
11503 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
11504 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
11505 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
11506 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
11508 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
11509 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
11510 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
11511 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
11512 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
11513 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
11514 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
11515 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
11516 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
11517 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
11518 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
11519 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
11520 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
11521 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
11522 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
11523 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
11525 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
11526 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
11527 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
11528 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
11529 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
11530 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
11531 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
11532 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
11533 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
11534 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
11535 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
11536 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
11537 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
11538 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
11539 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
11540 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
11542 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
11543 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
11544 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
11545 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
11546 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
11547 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
11548 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
11549 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
11550 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
11551 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
11552 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
11553 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
11554 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
11555 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
11557 __le16 physical_q0;
11558 __le16 physical_q1;
11559 __le16 dummy_dorq_var;
11563 __le16 slow_io_total_data_tx_update;
11571 __le32 more_to_send_seq;
11574 __le32 hq_scan_next_relevant_ack;
11580 __le32 bytes_to_next_pdu;
11595 __le32 exp_stat_sn;
11596 __le32 ongoing_fast_rxmit_seq;
11603 struct e4_tstorm_iscsi_conn_ag_ctx {
11607 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
11608 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
11609 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11610 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11611 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
11612 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
11613 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
11614 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
11615 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
11616 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
11617 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
11618 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
11619 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11620 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
11622 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
11623 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
11624 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
11625 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
11626 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
11627 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
11628 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
11629 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
11631 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
11632 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
11633 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
11634 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
11635 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
11636 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
11637 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
11638 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
11640 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
11641 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
11642 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
11643 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT 2
11644 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11645 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
11646 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
11647 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
11648 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
11649 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
11650 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
11651 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
11653 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11654 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
11655 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11656 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
11657 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11658 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
11659 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
11660 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
11661 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
11662 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
11663 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
11664 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
11665 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
11666 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT 6
11667 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11668 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
11670 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11671 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
11672 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11673 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
11674 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11675 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
11676 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11677 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
11678 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11679 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
11680 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11681 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
11682 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11683 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
11684 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
11685 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
11688 __le32 rx_tcp_checksum_err_cnt;
11695 u8 cid_offload_cnt;
11700 struct e4_ustorm_iscsi_conn_ag_ctx {
11704 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11705 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11706 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11707 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11708 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11709 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
11710 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11711 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
11712 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11713 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
11715 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
11716 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
11717 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
11718 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
11719 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
11720 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
11721 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
11722 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
11724 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11725 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11726 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11727 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
11728 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11729 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
11730 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
11731 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
11732 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11733 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
11734 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11735 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
11736 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11737 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
11738 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11739 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
11741 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11742 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
11743 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11744 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
11745 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11746 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
11747 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11748 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
11749 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11750 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
11751 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11752 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
11753 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11754 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
11755 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
11756 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
11769 /* The iscsi storm connection context of Tstorm */
11770 struct tstorm_iscsi_conn_st_ctx {
11771 __le32 reserved[44];
11774 struct e4_mstorm_iscsi_conn_ag_ctx {
11778 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11779 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11780 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11781 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11782 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11783 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
11784 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11785 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
11786 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11787 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
11789 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11790 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11791 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11792 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
11793 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11794 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
11795 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11796 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
11797 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11798 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
11799 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11800 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
11801 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11802 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
11803 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11804 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
11811 /* Combined iSCSI and TCP storm connection of Mstorm */
11812 struct mstorm_iscsi_tcp_conn_st_ctx {
11813 __le32 reserved_tcp[20];
11814 __le32 reserved_iscsi[12];
11817 /* The iscsi storm context of Ustorm */
11818 struct ustorm_iscsi_conn_st_ctx {
11819 __le32 reserved[52];
11822 /* iscsi connection context */
11823 struct e4_iscsi_conn_context {
11824 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
11825 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
11826 struct regpair pstorm_st_padding[2];
11827 struct pb_context xpb2_context;
11828 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
11829 struct regpair xstorm_st_padding[2];
11830 struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
11831 struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
11832 struct regpair tstorm_ag_padding[2];
11833 struct timers_context timer_context;
11834 struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
11835 struct pb_context upb_context;
11836 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
11837 struct regpair tstorm_st_padding[2];
11838 struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
11839 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
11840 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
11843 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */
11844 struct iscsi_init_ramrod_params {
11845 struct iscsi_spe_func_init iscsi_init_spe;
11846 struct tcp_init_params tcp_init;
11849 struct e4_ystorm_iscsi_conn_ag_ctx {
11853 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11854 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11855 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11856 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11857 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11858 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
11859 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11860 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
11861 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11862 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
11864 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11865 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11866 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11867 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
11868 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11869 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
11870 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11871 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
11872 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11873 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
11874 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11875 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
11876 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11877 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
11878 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11879 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
11893 #define MFW_TRACE_SIGNATURE 0x25071946
11895 /* The trace in the buffer */
11896 #define MFW_TRACE_EVENTID_MASK 0x00ffff
11897 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
11898 #define MFW_TRACE_PRM_SIZE_SHIFT 16
11899 #define MFW_TRACE_ENTRY_SIZE 3
11902 u32 signature; /* Help to identify that the trace is valid */
11903 u32 size; /* the size of the trace buffer in bytes */
11904 u32 curr_level; /* 2 - all will be written to the buffer
11905 * 1 - debug trace will not be written
11906 * 0 - just errors will be written to the buffer
11908 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
11912 /* Warning: the following pointers are assumed to be 32bits as they are
11913 * used only in the MFW.
11915 u32 trace_prod; /* The next trace will be written to this offset */
11916 u32 trace_oldest; /* The oldest valid trace starts at this offset
11917 * (usually very close after the current producer).
11921 #define VF_MAX_STATIC 192
11923 #define MCP_GLOB_PATH_MAX 2
11924 #define MCP_PORT_MAX 2
11925 #define MCP_GLOB_PORT_MAX 4
11926 #define MCP_GLOB_FUNC_MAX 16
11928 typedef u32 offsize_t; /* In DWORDS !!! */
11929 /* Offset from the beginning of the MCP scratchpad */
11930 #define OFFSIZE_OFFSET_SHIFT 0
11931 #define OFFSIZE_OFFSET_MASK 0x0000ffff
11932 /* Size of specific element (not the whole array if any) */
11933 #define OFFSIZE_SIZE_SHIFT 16
11934 #define OFFSIZE_SIZE_MASK 0xffff0000
11936 #define SECTION_OFFSET(_offsize) ((((_offsize & \
11937 OFFSIZE_OFFSET_MASK) >> \
11938 OFFSIZE_OFFSET_SHIFT) << 2))
11940 #define QED_SECTION_SIZE(_offsize) (((_offsize & \
11941 OFFSIZE_SIZE_MASK) >> \
11942 OFFSIZE_SIZE_SHIFT) << 2)
11944 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
11945 SECTION_OFFSET(_offsize) + \
11946 (QED_SECTION_SIZE(_offsize) * idx))
11948 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
11949 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
11951 /* PHY configuration */
11952 struct eth_phy_cfg {
11954 #define ETH_SPEED_AUTONEG 0
11955 #define ETH_SPEED_SMARTLINQ 0x8
11958 #define ETH_PAUSE_NONE 0x0
11959 #define ETH_PAUSE_AUTONEG 0x1
11960 #define ETH_PAUSE_RX 0x2
11961 #define ETH_PAUSE_TX 0x4
11965 #define ETH_LOOPBACK_NONE (0)
11966 #define ETH_LOOPBACK_INT_PHY (1)
11967 #define ETH_LOOPBACK_EXT_PHY (2)
11968 #define ETH_LOOPBACK_EXT (3)
11969 #define ETH_LOOPBACK_MAC (4)
11972 #define EEE_CFG_EEE_ENABLED BIT(0)
11973 #define EEE_CFG_TX_LPI BIT(1)
11974 #define EEE_CFG_ADV_SPEED_1G BIT(2)
11975 #define EEE_CFG_ADV_SPEED_10G BIT(3)
11976 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0)
11977 #define EEE_TX_TIMER_USEC_OFFSET 4
11978 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00)
11979 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100)
11980 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000)
11982 u32 feature_config_flags;
11983 #define ETH_EEE_MODE_ADV_LPI (1 << 0)
11986 struct port_mf_cfg {
11988 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
11989 #define PORT_MF_CFG_OV_TAG_SHIFT 0
11990 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
12079 u64 brb_truncate[8];
12080 u64 brb_discard[8];
12083 struct port_stats {
12084 struct brb_stats brb;
12085 struct eth_stats eth;
12088 struct couple_mode_teaming {
12089 u8 port_cmt[MCP_GLOB_PORT_MAX];
12090 #define PORT_CMT_IN_TEAM (1 << 0)
12092 #define PORT_CMT_PORT_ROLE (1 << 1)
12093 #define PORT_CMT_PORT_INACTIVE (0 << 1)
12094 #define PORT_CMT_PORT_ACTIVE (1 << 1)
12096 #define PORT_CMT_TEAM_MASK (1 << 2)
12097 #define PORT_CMT_TEAM0 (0 << 2)
12098 #define PORT_CMT_TEAM1 (1 << 2)
12101 #define LLDP_CHASSIS_ID_STAT_LEN 4
12102 #define LLDP_PORT_ID_STAT_LEN 4
12103 #define DCBX_MAX_APP_PROTOCOL 32
12104 #define MAX_SYSTEM_LLDP_TLV_DATA 32
12107 LLDP_NEAREST_BRIDGE = 0,
12108 LLDP_NEAREST_NON_TPMR_BRIDGE,
12109 LLDP_NEAREST_CUSTOMER_BRIDGE,
12110 LLDP_MAX_LLDP_AGENTS
12113 struct lldp_config_params_s {
12115 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
12116 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
12117 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
12118 #define LLDP_CONFIG_HOLD_SHIFT 8
12119 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
12120 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
12121 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
12122 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
12123 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
12124 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
12125 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
12126 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
12129 struct lldp_status_params_s {
12130 u32 prefix_seq_num;
12132 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
12133 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
12134 u32 suffix_seq_num;
12137 struct dcbx_ets_feature {
12139 #define DCBX_ETS_ENABLED_MASK 0x00000001
12140 #define DCBX_ETS_ENABLED_SHIFT 0
12141 #define DCBX_ETS_WILLING_MASK 0x00000002
12142 #define DCBX_ETS_WILLING_SHIFT 1
12143 #define DCBX_ETS_ERROR_MASK 0x00000004
12144 #define DCBX_ETS_ERROR_SHIFT 2
12145 #define DCBX_ETS_CBS_MASK 0x00000008
12146 #define DCBX_ETS_CBS_SHIFT 3
12147 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
12148 #define DCBX_ETS_MAX_TCS_SHIFT 4
12149 #define DCBX_OOO_TC_MASK 0x00000f00
12150 #define DCBX_OOO_TC_SHIFT 8
12152 #define DCBX_TCP_OOO_TC (4)
12154 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
12155 #define DCBX_CEE_STRICT_PRIORITY 0xf
12158 #define DCBX_ETS_TSA_STRICT 0
12159 #define DCBX_ETS_TSA_CBS 1
12160 #define DCBX_ETS_TSA_ETS 2
12163 #define DCBX_TCP_OOO_TC (4)
12164 #define DCBX_TCP_OOO_K2_4PORT_TC (3)
12166 struct dcbx_app_priority_entry {
12168 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
12169 #define DCBX_APP_PRI_MAP_SHIFT 0
12170 #define DCBX_APP_PRI_0 0x01
12171 #define DCBX_APP_PRI_1 0x02
12172 #define DCBX_APP_PRI_2 0x04
12173 #define DCBX_APP_PRI_3 0x08
12174 #define DCBX_APP_PRI_4 0x10
12175 #define DCBX_APP_PRI_5 0x20
12176 #define DCBX_APP_PRI_6 0x40
12177 #define DCBX_APP_PRI_7 0x80
12178 #define DCBX_APP_SF_MASK 0x00000300
12179 #define DCBX_APP_SF_SHIFT 8
12180 #define DCBX_APP_SF_ETHTYPE 0
12181 #define DCBX_APP_SF_PORT 1
12182 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
12183 #define DCBX_APP_SF_IEEE_SHIFT 12
12184 #define DCBX_APP_SF_IEEE_RESERVED 0
12185 #define DCBX_APP_SF_IEEE_ETHTYPE 1
12186 #define DCBX_APP_SF_IEEE_TCP_PORT 2
12187 #define DCBX_APP_SF_IEEE_UDP_PORT 3
12188 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
12190 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
12191 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
12194 struct dcbx_app_priority_feature {
12196 #define DCBX_APP_ENABLED_MASK 0x00000001
12197 #define DCBX_APP_ENABLED_SHIFT 0
12198 #define DCBX_APP_WILLING_MASK 0x00000002
12199 #define DCBX_APP_WILLING_SHIFT 1
12200 #define DCBX_APP_ERROR_MASK 0x00000004
12201 #define DCBX_APP_ERROR_SHIFT 2
12202 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
12203 #define DCBX_APP_MAX_TCS_SHIFT 12
12204 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
12205 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
12206 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
12209 struct dcbx_features {
12210 struct dcbx_ets_feature ets;
12212 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
12213 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
12214 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
12215 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
12216 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
12217 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
12218 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
12219 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
12220 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
12221 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
12223 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
12224 #define DCBX_PFC_FLAGS_SHIFT 8
12225 #define DCBX_PFC_CAPS_MASK 0x00000f00
12226 #define DCBX_PFC_CAPS_SHIFT 8
12227 #define DCBX_PFC_MBC_MASK 0x00004000
12228 #define DCBX_PFC_MBC_SHIFT 14
12229 #define DCBX_PFC_WILLING_MASK 0x00008000
12230 #define DCBX_PFC_WILLING_SHIFT 15
12231 #define DCBX_PFC_ENABLED_MASK 0x00010000
12232 #define DCBX_PFC_ENABLED_SHIFT 16
12233 #define DCBX_PFC_ERROR_MASK 0x00020000
12234 #define DCBX_PFC_ERROR_SHIFT 17
12236 struct dcbx_app_priority_feature app;
12239 struct dcbx_local_params {
12241 #define DCBX_CONFIG_VERSION_MASK 0x00000007
12242 #define DCBX_CONFIG_VERSION_SHIFT 0
12243 #define DCBX_CONFIG_VERSION_DISABLED 0
12244 #define DCBX_CONFIG_VERSION_IEEE 1
12245 #define DCBX_CONFIG_VERSION_CEE 2
12246 #define DCBX_CONFIG_VERSION_STATIC 4
12249 struct dcbx_features features;
12253 u32 prefix_seq_num;
12255 struct dcbx_features features;
12256 u32 suffix_seq_num;
12259 struct lldp_system_tlvs_buffer_s {
12262 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
12265 struct dcb_dscp_map {
12267 #define DCB_DSCP_ENABLE_MASK 0x1
12268 #define DCB_DSCP_ENABLE_SHIFT 0
12269 #define DCB_DSCP_ENABLE 1
12270 u32 dscp_pri_map[8];
12273 struct public_global {
12280 u32 debug_mb_offset;
12281 u32 phymod_dbg_mb_offset;
12282 struct couple_mode_teaming cmt;
12283 s32 internal_temperature;
12285 u32 running_bundle_id;
12286 s32 external_temperature;
12299 struct public_path {
12300 struct fw_flr_mb flr_mb;
12301 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
12304 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
12305 #define PROCESS_KILL_COUNTER_SHIFT 0
12306 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
12307 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
12308 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
12311 struct public_port {
12315 #define LINK_STATUS_LINK_UP 0x00000001
12316 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
12317 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
12318 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
12319 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
12320 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
12321 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
12322 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
12323 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
12324 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
12326 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
12328 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
12329 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
12331 #define LINK_STATUS_PFC_ENABLED 0x00000100
12332 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
12333 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
12334 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
12335 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
12336 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
12337 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
12338 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
12339 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
12341 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
12342 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
12343 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
12344 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
12345 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
12347 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
12348 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
12349 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
12350 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
12351 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
12352 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
12353 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
12356 u32 ext_phy_fw_version;
12357 u32 drv_phy_cfg_addr;
12361 u32 stat_nig_timer;
12363 struct port_mf_cfg port_mf_config;
12364 struct port_stats stats;
12367 #define MEDIA_UNSPECIFIED 0x0
12368 #define MEDIA_SFPP_10G_FIBER 0x1
12369 #define MEDIA_XFP_FIBER 0x2
12370 #define MEDIA_DA_TWINAX 0x3
12371 #define MEDIA_BASE_T 0x4
12372 #define MEDIA_SFP_1G_FIBER 0x5
12373 #define MEDIA_MODULE_FIBER 0x6
12374 #define MEDIA_KR 0xf0
12375 #define MEDIA_NOT_PRESENT 0xff
12378 u32 link_change_count;
12380 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
12381 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
12382 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
12384 /* DCBX related MIB */
12385 struct dcbx_local_params local_admin_dcbx_mib;
12386 struct dcbx_mib remote_dcbx_mib;
12387 struct dcbx_mib operational_dcbx_mib;
12390 u32 transceiver_data;
12391 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
12392 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
12393 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
12394 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
12395 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
12396 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
12397 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
12398 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00
12399 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
12400 #define ETH_TRANSCEIVER_TYPE_NONE 0x00
12401 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF
12402 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
12403 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
12404 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
12405 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
12406 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
12407 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
12408 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
12409 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
12410 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
12411 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
12412 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
12413 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
12414 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
12415 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
12416 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
12417 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
12418 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
12419 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
12420 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
12421 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
12422 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
12423 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
12424 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
12425 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
12426 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
12427 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
12428 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
12429 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
12430 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
12431 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
12432 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
12433 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
12434 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
12435 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
12436 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
12437 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
12438 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
12439 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
12440 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
12441 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
12442 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
12445 u32 wol_pkt_details;
12446 struct dcb_dscp_map dcb_dscp_map;
12449 #define EEE_ACTIVE_BIT BIT(0)
12450 #define EEE_LD_ADV_STATUS_MASK 0x000000f0
12451 #define EEE_LD_ADV_STATUS_OFFSET 4
12452 #define EEE_1G_ADV BIT(1)
12453 #define EEE_10G_ADV BIT(2)
12454 #define EEE_LP_ADV_STATUS_MASK 0x00000f00
12455 #define EEE_LP_ADV_STATUS_OFFSET 8
12456 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000
12457 #define EEE_SUPPORTED_SPEED_OFFSET 12
12458 #define EEE_1G_SUPPORTED BIT(1)
12459 #define EEE_10G_SUPPORTED BIT(2)
12462 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
12463 #define EEE_REMOTE_TW_TX_OFFSET 0
12464 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
12465 #define EEE_REMOTE_TW_RX_OFFSET 16
12469 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
12470 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0
12471 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
12472 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
12473 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
12474 #define OEM_CFG_SCHED_TYPE_OFFSET 2
12475 #define OEM_CFG_SCHED_TYPE_ETS 0x1
12476 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
12479 struct public_func {
12487 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
12488 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
12489 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
12491 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
12492 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
12493 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
12494 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
12495 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
12496 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
12497 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
12499 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
12500 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
12501 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
12502 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
12503 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
12504 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
12507 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001
12510 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
12511 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
12512 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
12514 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
12516 u32 fcoe_wwn_port_name_upper;
12517 u32 fcoe_wwn_port_name_lower;
12519 u32 fcoe_wwn_node_name_upper;
12520 u32 fcoe_wwn_node_name_lower;
12523 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
12524 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
12525 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
12531 u32 driver_last_activity_ts;
12533 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
12536 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
12537 #define DRV_ID_PDA_COMP_VER_SHIFT 0
12539 #define LOAD_REQ_HSI_VERSION 2
12540 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
12541 #define DRV_ID_MCP_HSI_VER_SHIFT 16
12542 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \
12543 DRV_ID_MCP_HSI_VER_SHIFT)
12545 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
12546 #define DRV_ID_DRV_TYPE_SHIFT 24
12547 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
12548 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
12550 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
12551 #define DRV_ID_DRV_INIT_HW_SHIFT 31
12552 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
12555 #define OEM_CFG_FUNC_TC_MASK 0x0000000F
12556 #define OEM_CFG_FUNC_TC_OFFSET 0
12557 #define OEM_CFG_FUNC_TC_0 0x0
12558 #define OEM_CFG_FUNC_TC_1 0x1
12559 #define OEM_CFG_FUNC_TC_2 0x2
12560 #define OEM_CFG_FUNC_TC_3 0x3
12561 #define OEM_CFG_FUNC_TC_4 0x4
12562 #define OEM_CFG_FUNC_TC_5 0x5
12563 #define OEM_CFG_FUNC_TC_6 0x6
12564 #define OEM_CFG_FUNC_TC_7 0x7
12566 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
12567 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4
12568 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
12569 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
12582 struct mcp_file_att {
12583 u32 nvm_start_addr;
12587 struct bist_nvm_image_att {
12590 u32 nvm_start_addr;
12594 #define MCP_DRV_VER_STR_SIZE 16
12595 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
12596 #define MCP_DRV_NVM_BUF_LEN 32
12597 struct drv_version_stc {
12599 u8 name[MCP_DRV_VER_STR_SIZE - 4];
12602 struct lan_stats_stc {
12609 struct fcoe_stats_stc {
12616 struct ocbb_data_stc {
12617 u32 ocbb_host_addr;
12618 u32 ocsd_host_addr;
12619 u32 ocsd_req_update_interval;
12622 #define MAX_NUM_OF_SENSORS 7
12623 struct temperature_status_stc {
12624 u32 num_of_sensors;
12625 u32 sensor[MAX_NUM_OF_SENSORS];
12628 /* crash dump configuration header */
12629 struct mdump_config_stc {
12637 enum resource_id_enum {
12638 RESOURCE_NUM_SB_E = 0,
12639 RESOURCE_NUM_L2_QUEUE_E = 1,
12640 RESOURCE_NUM_VPORT_E = 2,
12641 RESOURCE_NUM_VMQ_E = 3,
12642 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
12643 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
12644 RESOURCE_NUM_RL_E = 6,
12645 RESOURCE_NUM_PQ_E = 7,
12646 RESOURCE_NUM_VF_E = 8,
12647 RESOURCE_VFC_FILTER_E = 9,
12648 RESOURCE_ILT_E = 10,
12649 RESOURCE_CQS_E = 11,
12650 RESOURCE_GFT_PROFILES_E = 12,
12651 RESOURCE_NUM_TC_E = 13,
12652 RESOURCE_NUM_RSS_ENGINES_E = 14,
12653 RESOURCE_LL2_QUEUE_E = 15,
12654 RESOURCE_RDMA_STATS_QUEUE_E = 16,
12655 RESOURCE_BDQ_E = 17,
12656 RESOURCE_QCN_E = 18,
12657 RESOURCE_LLH_FILTER_E = 19,
12658 RESOURCE_VF_MAC_ADDR = 20,
12659 RESOURCE_LL2_CQS_E = 21,
12660 RESOURCE_VF_CNQS = 22,
12662 RESOURCE_NUM_INVALID = 0xFFFFFFFF
12665 /* Resource ID is to be filled by the driver in the MB request
12666 * Size, offset & flags to be filled by the MFW in the MB response
12668 struct resource_info {
12669 enum resource_id_enum res_id;
12670 u32 size; /* number of allocated resources */
12671 u32 offset; /* Offset of the 1st resource */
12675 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12678 #define DRV_ROLE_NONE 0
12679 #define DRV_ROLE_PREBOOT 1
12680 #define DRV_ROLE_OS 2
12681 #define DRV_ROLE_KDUMP 3
12683 struct load_req_stc {
12688 #define LOAD_REQ_ROLE_MASK 0x000000FF
12689 #define LOAD_REQ_ROLE_SHIFT 0
12690 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
12691 #define LOAD_REQ_LOCK_TO_SHIFT 8
12692 #define LOAD_REQ_LOCK_TO_DEFAULT 0
12693 #define LOAD_REQ_LOCK_TO_NONE 255
12694 #define LOAD_REQ_FORCE_MASK 0x000F0000
12695 #define LOAD_REQ_FORCE_SHIFT 16
12696 #define LOAD_REQ_FORCE_NONE 0
12697 #define LOAD_REQ_FORCE_PF 1
12698 #define LOAD_REQ_FORCE_ALL 2
12699 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
12700 #define LOAD_REQ_FLAGS0_SHIFT 20
12701 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
12704 struct load_rsp_stc {
12709 #define LOAD_RSP_ROLE_MASK 0x000000FF
12710 #define LOAD_RSP_ROLE_SHIFT 0
12711 #define LOAD_RSP_HSI_MASK 0x0000FF00
12712 #define LOAD_RSP_HSI_SHIFT 8
12713 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
12714 #define LOAD_RSP_FLAGS0_SHIFT 16
12715 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
12718 union drv_union_data {
12719 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
12720 struct mcp_mac wol_mac;
12722 struct eth_phy_cfg drv_phy_cfg;
12724 struct mcp_val64 val64;
12726 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
12728 struct mcp_file_att file_att;
12730 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
12732 struct drv_version_stc drv_version;
12734 struct lan_stats_stc lan_stats;
12735 struct fcoe_stats_stc fcoe_stats;
12736 struct ocbb_data_stc ocbb_info;
12737 struct temperature_status_stc temp_info;
12738 struct resource_info resource;
12739 struct bist_nvm_image_att nvm_image_att;
12740 struct mdump_config_stc mdump_config;
12743 struct public_drv_mb {
12745 #define DRV_MSG_CODE_MASK 0xffff0000
12746 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
12747 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
12748 #define DRV_MSG_CODE_INIT_HW 0x12000000
12749 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
12750 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
12751 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
12752 #define DRV_MSG_CODE_INIT_PHY 0x22000000
12753 #define DRV_MSG_CODE_LINK_RESET 0x23000000
12754 #define DRV_MSG_CODE_SET_DCBX 0x25000000
12755 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
12756 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
12757 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
12758 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
12759 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
12760 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
12761 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
12762 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
12763 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
12764 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
12765 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
12766 #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000
12768 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
12769 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
12770 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
12771 #define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000
12772 #define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000
12773 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
12774 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
12775 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
12776 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
12777 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
12778 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
12779 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
12780 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
12781 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
12782 #define DRV_MSG_CODE_MCP_RESET 0x00090000
12783 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
12784 #define DRV_MSG_CODE_MCP_HALT 0x00100000
12785 #define DRV_MSG_CODE_SET_VMAC 0x00110000
12786 #define DRV_MSG_CODE_GET_VMAC 0x00120000
12787 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
12788 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
12789 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
12790 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
12791 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
12793 #define DRV_MSG_CODE_GET_STATS 0x00130000
12794 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
12795 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
12796 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
12797 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
12799 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
12801 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
12803 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
12804 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
12805 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
12806 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000
12807 #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000
12808 #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000
12810 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
12811 #define RESOURCE_CMD_REQ_RESC_SHIFT 0
12812 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
12813 #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5
12814 #define RESOURCE_OPCODE_REQ 1
12815 #define RESOURCE_OPCODE_REQ_WO_AGING 2
12816 #define RESOURCE_OPCODE_REQ_W_AGING 3
12817 #define RESOURCE_OPCODE_RELEASE 4
12818 #define RESOURCE_OPCODE_FORCE_RELEASE 5
12819 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
12820 #define RESOURCE_CMD_REQ_AGE_SHIFT 8
12822 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
12823 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0
12824 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
12825 #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8
12826 #define RESOURCE_OPCODE_GNT 1
12827 #define RESOURCE_OPCODE_BUSY 2
12828 #define RESOURCE_OPCODE_RELEASED 3
12829 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
12830 #define RESOURCE_OPCODE_WRONG_OWNER 5
12831 #define RESOURCE_OPCODE_UNKNOWN_CMD 255
12833 #define RESOURCE_DUMP 0
12835 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
12836 #define DRV_MSG_CODE_OS_WOL 0x002e0000
12838 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
12839 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
12840 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
12843 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
12844 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
12845 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
12846 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
12847 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
12848 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
12850 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3
12851 #define DRV_MB_PARAM_NVM_LEN_OFFSET 24
12853 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
12854 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
12855 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
12856 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
12857 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
12858 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
12860 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
12861 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
12862 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
12863 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
12864 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
12865 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
12867 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
12868 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
12869 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
12870 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
12871 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
12872 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
12874 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
12875 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
12876 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
12877 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
12878 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
12879 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
12880 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
12882 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
12883 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
12885 #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \
12886 DRV_MB_PARAM_WOL_DISABLED | \
12887 DRV_MB_PARAM_WOL_ENABLED)
12888 #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
12889 #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
12890 #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED
12892 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
12893 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
12894 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
12895 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
12896 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
12897 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
12899 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1
12900 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0
12902 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
12903 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
12904 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
12906 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
12907 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
12908 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
12909 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC
12910 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
12911 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00
12912 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
12913 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000
12915 /* Resource Allocation params - Driver version support */
12916 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
12917 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12918 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
12919 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12921 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
12922 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
12923 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
12924 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
12926 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
12927 #define DRV_MB_PARAM_BIST_RC_PASSED 1
12928 #define DRV_MB_PARAM_BIST_RC_FAILED 2
12929 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
12931 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
12932 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
12933 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
12934 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00
12936 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF
12937 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
12938 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
12939 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
12941 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
12942 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF
12943 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16
12944 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000
12945 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17
12946 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000
12947 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18
12948 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000
12949 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19
12950 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000
12951 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20
12952 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000
12953 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24
12954 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000
12957 #define FW_MSG_CODE_MASK 0xffff0000
12958 #define FW_MSG_CODE_UNSUPPORTED 0x00000000
12959 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
12960 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
12961 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
12962 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
12963 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
12964 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
12965 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
12966 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12967 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
12968 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
12969 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
12970 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
12971 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
12972 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
12973 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
12974 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
12975 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
12976 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000
12977 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
12979 #define FW_MSG_CODE_NVM_OK 0x00010000
12980 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
12981 #define FW_MSG_CODE_PHY_OK 0x00110000
12982 #define FW_MSG_CODE_OK 0x00160000
12983 #define FW_MSG_CODE_ERROR 0x00170000
12984 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
12985 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
12986 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
12988 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
12989 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
12990 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
12991 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
12994 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
12995 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12996 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
12997 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12999 /* get pf rdma protocol command responce */
13000 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
13001 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
13002 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
13003 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
13005 /* get MFW feature support response */
13006 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001
13007 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002
13008 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000
13010 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0)
13012 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
13013 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
13014 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
13015 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 1
13016 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
13017 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT 2
13018 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
13019 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 3
13021 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF
13022 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0
13025 #define DRV_PULSE_SEQ_MASK 0x00007fff
13026 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
13027 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
13030 #define MCP_PULSE_SEQ_MASK 0x00007fff
13031 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
13032 #define MCP_EVENT_MASK 0xffff0000
13033 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
13035 union drv_union_data union_data;
13038 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff
13039 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0
13040 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000
13041 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT 24
13043 enum MFW_DRV_MSG_TYPE {
13044 MFW_DRV_MSG_LINK_CHANGE,
13045 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
13046 MFW_DRV_MSG_VF_DISABLED,
13047 MFW_DRV_MSG_LLDP_DATA_UPDATED,
13048 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
13049 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
13050 MFW_DRV_MSG_ERROR_RECOVERY,
13051 MFW_DRV_MSG_BW_UPDATE,
13052 MFW_DRV_MSG_S_TAG_UPDATE,
13053 MFW_DRV_MSG_GET_LAN_STATS,
13054 MFW_DRV_MSG_GET_FCOE_STATS,
13055 MFW_DRV_MSG_GET_ISCSI_STATS,
13056 MFW_DRV_MSG_GET_RDMA_STATS,
13057 MFW_DRV_MSG_BW_UPDATE10,
13058 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
13059 MFW_DRV_MSG_BW_UPDATE11,
13060 MFW_DRV_MSG_RESERVED,
13061 MFW_DRV_MSG_GET_TLV_REQ,
13062 MFW_DRV_MSG_OEM_CFG_UPDATE,
13066 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
13067 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
13068 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
13069 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
13071 struct public_mfw_mb {
13073 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
13074 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
13077 enum public_sections {
13084 PUBLIC_MAX_SECTIONS
13087 struct mcp_public_data {
13089 u32 sections[PUBLIC_MAX_SECTIONS];
13090 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
13091 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
13092 struct public_global global;
13093 struct public_path path[MCP_GLOB_PATH_MAX];
13094 struct public_port port[MCP_GLOB_PORT_MAX];
13095 struct public_func func[MCP_GLOB_FUNC_MAX];
13098 #define MAX_I2C_TRANSACTION_SIZE 16
13100 /* OCBB definitions */
13102 /* Category 1: Device Properties */
13104 DRV_TLV_CLP_STR_CTD,
13105 /* Category 6: Device Configuration */
13112 /* Category 8: Port Configuration */
13113 DRV_TLV_NPIV_ENABLED,
13114 /* Category 10: Function Configuration */
13115 DRV_TLV_FEATURE_FLAGS,
13116 DRV_TLV_LOCAL_ADMIN_ADDR,
13117 DRV_TLV_ADDITIONAL_MAC_ADDR_1,
13118 DRV_TLV_ADDITIONAL_MAC_ADDR_2,
13119 DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
13120 DRV_TLV_LSO_MIN_SEGMENT_COUNT,
13121 DRV_TLV_PROMISCUOUS_MODE,
13122 DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
13123 DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
13124 DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
13125 DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
13126 DRV_TLV_OS_DRIVER_STATES,
13127 DRV_TLV_PXE_BOOT_PROGRESS,
13128 /* Category 12: FC/FCoE Configuration */
13129 DRV_TLV_NPIV_STATE,
13130 DRV_TLV_NUM_OF_NPIV_IDS,
13131 DRV_TLV_SWITCH_NAME,
13132 DRV_TLV_SWITCH_PORT_NUM,
13133 DRV_TLV_SWITCH_PORT_ID,
13134 DRV_TLV_VENDOR_NAME,
13135 DRV_TLV_SWITCH_MODEL,
13136 DRV_TLV_SWITCH_FW_VER,
13137 DRV_TLV_QOS_PRIORITY_PER_802_1P,
13138 DRV_TLV_PORT_ALIAS,
13139 DRV_TLV_PORT_STATE,
13140 DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
13141 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
13142 DRV_TLV_LINK_FAILURE_COUNT,
13143 DRV_TLV_FCOE_BOOT_PROGRESS,
13144 /* Category 13: iSCSI Configuration */
13145 DRV_TLV_TARGET_LLMNR_ENABLED,
13146 DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
13147 DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
13148 DRV_TLV_AUTHENTICATION_METHOD,
13149 DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
13150 DRV_TLV_MAX_FRAME_SIZE,
13151 DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
13152 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
13153 DRV_TLV_ISCSI_BOOT_PROGRESS,
13154 /* Category 20: Device Data */
13155 DRV_TLV_PCIE_BUS_RX_UTILIZATION,
13156 DRV_TLV_PCIE_BUS_TX_UTILIZATION,
13157 DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
13158 DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
13159 DRV_TLV_NCSI_RX_BYTES_RECEIVED,
13160 DRV_TLV_NCSI_TX_BYTES_SENT,
13161 /* Category 22: Base Port Data */
13162 DRV_TLV_RX_DISCARDS,
13165 DRV_TLV_TX_DISCARDS,
13166 DRV_TLV_RX_FRAMES_RECEIVED,
13167 DRV_TLV_TX_FRAMES_SENT,
13168 /* Category 23: FC/FCoE Port Data */
13169 DRV_TLV_RX_BROADCAST_PACKETS,
13170 DRV_TLV_TX_BROADCAST_PACKETS,
13171 /* Category 28: Base Function Data */
13172 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
13173 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
13174 DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
13175 DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
13176 DRV_TLV_PF_RX_FRAMES_RECEIVED,
13177 DRV_TLV_RX_BYTES_RECEIVED,
13178 DRV_TLV_PF_TX_FRAMES_SENT,
13179 DRV_TLV_TX_BYTES_SENT,
13180 DRV_TLV_IOV_OFFLOAD,
13181 DRV_TLV_PCI_ERRORS_CAP_ID,
13182 DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
13183 DRV_TLV_UNCORRECTABLE_ERROR_MASK,
13184 DRV_TLV_CORRECTABLE_ERROR_STATUS,
13185 DRV_TLV_CORRECTABLE_ERROR_MASK,
13186 DRV_TLV_PCI_ERRORS_AECC_REGISTER,
13187 DRV_TLV_TX_QUEUES_EMPTY,
13188 DRV_TLV_RX_QUEUES_EMPTY,
13189 DRV_TLV_TX_QUEUES_FULL,
13190 DRV_TLV_RX_QUEUES_FULL,
13191 /* Category 29: FC/FCoE Function Data */
13192 DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
13193 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
13194 DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
13195 DRV_TLV_FCOE_RX_BYTES_RECEIVED,
13196 DRV_TLV_FCOE_TX_FRAMES_SENT,
13197 DRV_TLV_FCOE_TX_BYTES_SENT,
13198 DRV_TLV_CRC_ERROR_COUNT,
13199 DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
13200 DRV_TLV_CRC_ERROR_1_TIMESTAMP,
13201 DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
13202 DRV_TLV_CRC_ERROR_2_TIMESTAMP,
13203 DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
13204 DRV_TLV_CRC_ERROR_3_TIMESTAMP,
13205 DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
13206 DRV_TLV_CRC_ERROR_4_TIMESTAMP,
13207 DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
13208 DRV_TLV_CRC_ERROR_5_TIMESTAMP,
13209 DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
13210 DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
13211 DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
13212 DRV_TLV_DISPARITY_ERROR_COUNT,
13213 DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
13214 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
13215 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
13216 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
13217 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
13218 DRV_TLV_LAST_FLOGI_TIMESTAMP,
13219 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
13220 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
13221 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
13222 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
13223 DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
13224 DRV_TLV_LAST_FLOGI_RJT,
13225 DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
13226 DRV_TLV_FDISCS_SENT_COUNT,
13227 DRV_TLV_FDISC_ACCS_RECEIVED,
13228 DRV_TLV_FDISC_RJTS_RECEIVED,
13229 DRV_TLV_PLOGI_SENT_COUNT,
13230 DRV_TLV_PLOGI_ACCS_RECEIVED,
13231 DRV_TLV_PLOGI_RJTS_RECEIVED,
13232 DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
13233 DRV_TLV_PLOGI_1_TIMESTAMP,
13234 DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
13235 DRV_TLV_PLOGI_2_TIMESTAMP,
13236 DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
13237 DRV_TLV_PLOGI_3_TIMESTAMP,
13238 DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
13239 DRV_TLV_PLOGI_4_TIMESTAMP,
13240 DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
13241 DRV_TLV_PLOGI_5_TIMESTAMP,
13242 DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
13243 DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
13244 DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
13245 DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
13246 DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
13247 DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
13248 DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
13249 DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
13250 DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
13251 DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
13252 DRV_TLV_LOGOS_ISSUED,
13253 DRV_TLV_LOGO_ACCS_RECEIVED,
13254 DRV_TLV_LOGO_RJTS_RECEIVED,
13255 DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
13256 DRV_TLV_LOGO_1_TIMESTAMP,
13257 DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
13258 DRV_TLV_LOGO_2_TIMESTAMP,
13259 DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
13260 DRV_TLV_LOGO_3_TIMESTAMP,
13261 DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
13262 DRV_TLV_LOGO_4_TIMESTAMP,
13263 DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
13264 DRV_TLV_LOGO_5_TIMESTAMP,
13265 DRV_TLV_LOGOS_RECEIVED,
13266 DRV_TLV_ACCS_ISSUED,
13267 DRV_TLV_PRLIS_ISSUED,
13268 DRV_TLV_ACCS_RECEIVED,
13269 DRV_TLV_ABTS_SENT_COUNT,
13270 DRV_TLV_ABTS_ACCS_RECEIVED,
13271 DRV_TLV_ABTS_RJTS_RECEIVED,
13272 DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
13273 DRV_TLV_ABTS_1_TIMESTAMP,
13274 DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
13275 DRV_TLV_ABTS_2_TIMESTAMP,
13276 DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
13277 DRV_TLV_ABTS_3_TIMESTAMP,
13278 DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
13279 DRV_TLV_ABTS_4_TIMESTAMP,
13280 DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
13281 DRV_TLV_ABTS_5_TIMESTAMP,
13282 DRV_TLV_RSCNS_RECEIVED,
13283 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
13284 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
13285 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
13286 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
13287 DRV_TLV_LUN_RESETS_ISSUED,
13288 DRV_TLV_ABORT_TASK_SETS_ISSUED,
13289 DRV_TLV_TPRLOS_SENT,
13290 DRV_TLV_NOS_SENT_COUNT,
13291 DRV_TLV_NOS_RECEIVED_COUNT,
13295 DRV_TLV_LIP_SENT_COUNT,
13296 DRV_TLV_LIP_RECEIVED_COUNT,
13297 DRV_TLV_EOFA_COUNT,
13298 DRV_TLV_EOFNI_COUNT,
13299 DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
13300 DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
13301 DRV_TLV_SCSI_STATUS_BUSY_COUNT,
13302 DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
13303 DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
13304 DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
13305 DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
13306 DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
13307 DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
13308 DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
13309 DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
13310 DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
13311 DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
13312 DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
13313 DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
13314 DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
13315 DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
13316 DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
13317 DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
13318 /* Category 30: iSCSI Function Data */
13319 DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
13320 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
13321 DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
13322 DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
13323 DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
13324 DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
13327 struct nvm_cfg_mac_address {
13329 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
13330 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
13334 struct nvm_cfg1_glob {
13336 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
13337 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
13338 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
13339 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
13340 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
13341 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
13342 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
13343 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
13344 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
13345 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
13346 u32 engineering_change[3];
13347 u32 manufacturing_id;
13348 u32 serial_number[4];
13352 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
13353 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
13354 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
13355 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
13356 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
13357 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
13358 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
13359 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
13360 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
13361 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
13362 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
13363 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
13364 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF
13370 u32 mps10_preemphasis;
13371 u32 mps10_driver_current;
13372 u32 mps25_preemphasis;
13373 u32 mps25_driver_current;
13377 u32 mps10_txfir_main;
13378 u32 mps10_txfir_post;
13379 u32 mps25_txfir_main;
13380 u32 mps25_txfir_post;
13381 u32 manufacture_ver;
13382 u32 manufacture_time;
13383 u32 led_global_settings;
13386 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
13387 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
13388 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
13389 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
13390 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
13391 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
13394 u32 device_capabilities;
13395 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
13396 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
13397 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
13398 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
13399 u32 power_dissipated;
13400 u32 power_consumed;
13402 u32 multi_network_modes_capability;
13406 struct nvm_cfg1_path {
13410 struct nvm_cfg1_port {
13411 u32 reserved__m_relocated_to_option_123;
13412 u32 reserved__m_relocated_to_option_124;
13414 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
13415 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
13416 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
13417 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
13418 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
13419 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
13420 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
13421 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
13422 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
13423 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
13424 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
13427 u32 speed_cap_mask;
13428 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
13429 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
13430 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
13431 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
13432 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
13433 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
13434 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
13435 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
13436 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
13438 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
13439 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
13440 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
13441 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
13442 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
13443 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
13444 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
13445 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
13446 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
13447 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
13448 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
13449 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
13450 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
13451 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
13452 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
13453 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
13458 /* EEE power saving mode */
13459 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000
13460 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
13461 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
13462 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
13463 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
13464 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
13469 struct nvm_cfg_mac_address lldp_mac_address;
13470 u32 led_port_settings;
13471 u32 transceiver_00;
13474 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF
13475 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
13476 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
13477 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
13478 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
13479 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
13480 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
13499 struct nvm_cfg1_func {
13500 struct nvm_cfg_mac_address mac_address;
13506 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
13507 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
13508 u32 preboot_generic_cfg;
13513 struct nvm_cfg1_glob glob;
13514 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
13515 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
13516 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
13519 enum spad_sections {
13520 SPAD_SECTION_TRACE,
13521 SPAD_SECTION_NVM_CFG,
13522 SPAD_SECTION_PUBLIC,
13523 SPAD_SECTION_PRIVATE,
13527 #define MCP_TRACE_SIZE 2048 /* 2kb */
13529 /* This section is located at a fixed location in the beginning of the
13530 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
13531 * All the rest of data has a floating location which differs from version to
13532 * version, and is pointed by the mcp_meta_data below.
13533 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
13534 * with it from nvram in order to clear this portion.
13536 struct static_init {
13538 offsize_t sections[SPAD_SECTION_MAX];
13539 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
13541 struct mcp_trace trace;
13542 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
13543 u8 trace_buffer[MCP_TRACE_SIZE];
13544 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
13545 /* running_mfw has the same definition as in nvm_map.h.
13546 * This bit indicate both the running dir, and the running bundle.
13547 * It is set once when the LIM is loaded.
13550 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
13552 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
13554 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
13555 u32 mfw_secure_mode;
13556 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
13557 u16 pme_status_pf_bitmap;
13558 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
13559 u16 pme_enable_pf_bitmap;
13560 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
13562 u32 mim_start_addr;
13563 u32 ah_pcie_link_params;
13564 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
13565 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
13566 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
13567 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
13568 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
13569 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
13570 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
13571 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
13572 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
13574 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
13577 #define NVM_MAGIC_VALUE 0x669955aa
13579 enum nvm_image_type {
13580 NVM_TYPE_TIM1 = 0x01,
13581 NVM_TYPE_TIM2 = 0x02,
13582 NVM_TYPE_MIM1 = 0x03,
13583 NVM_TYPE_MIM2 = 0x04,
13584 NVM_TYPE_MBA = 0x05,
13585 NVM_TYPE_MODULES_PN = 0x06,
13586 NVM_TYPE_VPD = 0x07,
13587 NVM_TYPE_MFW_TRACE1 = 0x08,
13588 NVM_TYPE_MFW_TRACE2 = 0x09,
13589 NVM_TYPE_NVM_CFG1 = 0x0a,
13590 NVM_TYPE_L2B = 0x0b,
13591 NVM_TYPE_DIR1 = 0x0c,
13592 NVM_TYPE_EAGLE_FW1 = 0x0d,
13593 NVM_TYPE_FALCON_FW1 = 0x0e,
13594 NVM_TYPE_PCIE_FW1 = 0x0f,
13595 NVM_TYPE_HW_SET = 0x10,
13596 NVM_TYPE_LIM = 0x11,
13597 NVM_TYPE_AVS_FW1 = 0x12,
13598 NVM_TYPE_DIR2 = 0x13,
13599 NVM_TYPE_CCM = 0x14,
13600 NVM_TYPE_EAGLE_FW2 = 0x15,
13601 NVM_TYPE_FALCON_FW2 = 0x16,
13602 NVM_TYPE_PCIE_FW2 = 0x17,
13603 NVM_TYPE_AVS_FW2 = 0x18,
13604 NVM_TYPE_INIT_HW = 0x19,
13605 NVM_TYPE_DEFAULT_CFG = 0x1a,
13606 NVM_TYPE_MDUMP = 0x1b,
13607 NVM_TYPE_META = 0x1c,
13608 NVM_TYPE_ISCSI_CFG = 0x1d,
13609 NVM_TYPE_FCOE_CFG = 0x1f,
13610 NVM_TYPE_ETH_PHY_FW1 = 0x20,
13611 NVM_TYPE_ETH_PHY_FW2 = 0x21,
13615 #define DIR_ID_1 (0)