1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/stddef.h>
10 #include <linux/pci.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/version.h>
14 #include <linux/delay.h>
15 #include <asm/byteorder.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/string.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/workqueue.h>
21 #include <linux/ethtool.h>
22 #include <linux/etherdevice.h>
23 #include <linux/vmalloc.h>
24 #include <linux/qed/qed_if.h>
28 #include "qed_dev_api.h"
32 static char version[] =
33 "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
35 MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Core Module");
36 MODULE_LICENSE("GPL");
37 MODULE_VERSION(DRV_MODULE_VERSION);
39 #define FW_FILE_VERSION \
40 __stringify(FW_MAJOR_VERSION) "." \
41 __stringify(FW_MINOR_VERSION) "." \
42 __stringify(FW_REVISION_VERSION) "." \
43 __stringify(FW_ENGINEERING_VERSION)
45 #define QED_FW_FILE_NAME \
46 "qed/qed_init_values_zipped-" FW_FILE_VERSION ".bin"
48 MODULE_FIRMWARE(QED_FW_FILE_NAME);
50 static int __init qed_init(void)
52 pr_notice("qed_init called\n");
54 pr_info("%s", version);
59 static void __exit qed_cleanup(void)
61 pr_notice("qed_cleanup called\n");
64 module_init(qed_init);
65 module_exit(qed_cleanup);
67 /* Check if the DMA controller on the machine can properly handle the DMA
68 * addressing required by the device.
70 static int qed_set_coherency_mask(struct qed_dev *cdev)
72 struct device *dev = &cdev->pdev->dev;
74 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
75 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
77 "Can't request 64-bit consistent allocations\n");
80 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
81 DP_NOTICE(cdev, "Can't request 64b/32b DMA addresses\n");
88 static void qed_free_pci(struct qed_dev *cdev)
90 struct pci_dev *pdev = cdev->pdev;
93 iounmap(cdev->doorbells);
95 iounmap(cdev->regview);
96 if (atomic_read(&pdev->enable_cnt) == 1)
97 pci_release_regions(pdev);
99 pci_disable_device(pdev);
102 #define PCI_REVISION_ID_ERROR_VAL 0xff
104 /* Performs PCI initializations as well as initializing PCI-related parameters
105 * in the device structrue. Returns 0 in case of success.
107 static int qed_init_pci(struct qed_dev *cdev,
108 struct pci_dev *pdev)
115 rc = pci_enable_device(pdev);
117 DP_NOTICE(cdev, "Cannot enable PCI device\n");
121 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
122 DP_NOTICE(cdev, "No memory region found in bar #0\n");
127 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
128 DP_NOTICE(cdev, "No memory region found in bar #2\n");
133 if (atomic_read(&pdev->enable_cnt) == 1) {
134 rc = pci_request_regions(pdev, "qed");
137 "Failed to request PCI memory resources\n");
140 pci_set_master(pdev);
141 pci_save_state(pdev);
144 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
145 if (rev_id == PCI_REVISION_ID_ERROR_VAL) {
147 "Detected PCI device error [rev_id 0x%x]. Probably due to prior indication. Aborting.\n",
152 if (!pci_is_pcie(pdev)) {
153 DP_NOTICE(cdev, "The bus is not PCI Express\n");
158 cdev->pci_params.pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
159 if (cdev->pci_params.pm_cap == 0)
160 DP_NOTICE(cdev, "Cannot find power management capability\n");
162 rc = qed_set_coherency_mask(cdev);
166 cdev->pci_params.mem_start = pci_resource_start(pdev, 0);
167 cdev->pci_params.mem_end = pci_resource_end(pdev, 0);
168 cdev->pci_params.irq = pdev->irq;
170 cdev->regview = pci_ioremap_bar(pdev, 0);
171 if (!cdev->regview) {
172 DP_NOTICE(cdev, "Cannot map register space, aborting\n");
177 cdev->db_phys_addr = pci_resource_start(cdev->pdev, 2);
178 cdev->db_size = pci_resource_len(cdev->pdev, 2);
179 cdev->doorbells = ioremap_wc(cdev->db_phys_addr, cdev->db_size);
180 if (!cdev->doorbells) {
181 DP_NOTICE(cdev, "Cannot map doorbell space\n");
188 pci_release_regions(pdev);
190 pci_disable_device(pdev);
195 int qed_fill_dev_info(struct qed_dev *cdev,
196 struct qed_dev_info *dev_info)
200 memset(dev_info, 0, sizeof(struct qed_dev_info));
202 dev_info->num_hwfns = cdev->num_hwfns;
203 dev_info->pci_mem_start = cdev->pci_params.mem_start;
204 dev_info->pci_mem_end = cdev->pci_params.mem_end;
205 dev_info->pci_irq = cdev->pci_params.irq;
206 dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
207 ether_addr_copy(dev_info->hw_mac, cdev->hwfns[0].hw_info.hw_mac_addr);
209 dev_info->fw_major = FW_MAJOR_VERSION;
210 dev_info->fw_minor = FW_MINOR_VERSION;
211 dev_info->fw_rev = FW_REVISION_VERSION;
212 dev_info->fw_eng = FW_ENGINEERING_VERSION;
213 dev_info->mf_mode = cdev->mf_mode;
215 qed_mcp_get_mfw_ver(cdev, &dev_info->mfw_rev);
217 ptt = qed_ptt_acquire(QED_LEADING_HWFN(cdev));
219 qed_mcp_get_flash_size(QED_LEADING_HWFN(cdev), ptt,
220 &dev_info->flash_size);
222 qed_ptt_release(QED_LEADING_HWFN(cdev), ptt);
228 static void qed_free_cdev(struct qed_dev *cdev)
233 static struct qed_dev *qed_alloc_cdev(struct pci_dev *pdev)
235 struct qed_dev *cdev;
237 cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
241 qed_init_struct(cdev);
246 /* Sets the requested power state */
247 static int qed_set_power_state(struct qed_dev *cdev,
253 DP_VERBOSE(cdev, NETIF_MSG_DRV, "Omitting Power state change\n");
258 static struct qed_dev *qed_probe(struct pci_dev *pdev,
259 enum qed_protocol protocol,
263 struct qed_dev *cdev;
266 cdev = qed_alloc_cdev(pdev);
270 cdev->protocol = protocol;
272 qed_init_dp(cdev, dp_module, dp_level);
274 rc = qed_init_pci(cdev, pdev);
276 DP_ERR(cdev, "init pci failed\n");
279 DP_INFO(cdev, "PCI init completed successfully\n");
281 rc = qed_hw_prepare(cdev, QED_PCI_DEFAULT);
283 DP_ERR(cdev, "hw prepare failed\n");
287 DP_INFO(cdev, "qed_probe completed successffuly\n");
299 static void qed_remove(struct qed_dev *cdev)
308 qed_set_power_state(cdev, PCI_D3hot);
313 static void qed_disable_msix(struct qed_dev *cdev)
315 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
316 pci_disable_msix(cdev->pdev);
317 kfree(cdev->int_params.msix_table);
318 } else if (cdev->int_params.out.int_mode == QED_INT_MODE_MSI) {
319 pci_disable_msi(cdev->pdev);
322 memset(&cdev->int_params.out, 0, sizeof(struct qed_int_param));
325 static int qed_enable_msix(struct qed_dev *cdev,
326 struct qed_int_params *int_params)
330 cnt = int_params->in.num_vectors;
332 for (i = 0; i < cnt; i++)
333 int_params->msix_table[i].entry = i;
335 rc = pci_enable_msix_range(cdev->pdev, int_params->msix_table,
336 int_params->in.min_msix_cnt, cnt);
337 if (rc < cnt && rc >= int_params->in.min_msix_cnt &&
338 (rc % cdev->num_hwfns)) {
339 pci_disable_msix(cdev->pdev);
341 /* If fastpath is initialized, we need at least one interrupt
342 * per hwfn [and the slow path interrupts]. New requested number
343 * should be a multiple of the number of hwfns.
345 cnt = (rc / cdev->num_hwfns) * cdev->num_hwfns;
347 "Trying to enable MSI-X with less vectors (%d out of %d)\n",
348 cnt, int_params->in.num_vectors);
349 rc = pci_enable_msix_exact(cdev->pdev,
350 int_params->msix_table, cnt);
356 /* MSI-x configuration was achieved */
357 int_params->out.int_mode = QED_INT_MODE_MSIX;
358 int_params->out.num_vectors = rc;
362 "Failed to enable MSI-X [Requested %d vectors][rc %d]\n",
369 /* This function outputs the int mode and the number of enabled msix vector */
370 static int qed_set_int_mode(struct qed_dev *cdev, bool force_mode)
372 struct qed_int_params *int_params = &cdev->int_params;
373 struct msix_entry *tbl;
376 switch (int_params->in.int_mode) {
377 case QED_INT_MODE_MSIX:
378 /* Allocate MSIX table */
379 cnt = int_params->in.num_vectors;
380 int_params->msix_table = kcalloc(cnt, sizeof(*tbl), GFP_KERNEL);
381 if (!int_params->msix_table) {
387 rc = qed_enable_msix(cdev, int_params);
391 DP_NOTICE(cdev, "Failed to enable MSI-X\n");
392 kfree(int_params->msix_table);
397 case QED_INT_MODE_MSI:
398 rc = pci_enable_msi(cdev->pdev);
400 int_params->out.int_mode = QED_INT_MODE_MSI;
404 DP_NOTICE(cdev, "Failed to enable MSI\n");
409 case QED_INT_MODE_INTA:
410 int_params->out.int_mode = QED_INT_MODE_INTA;
414 DP_NOTICE(cdev, "Unknown int_mode value %d\n",
415 int_params->in.int_mode);
420 cdev->int_coalescing_mode = QED_COAL_MODE_ENABLE;
425 static void qed_simd_handler_config(struct qed_dev *cdev, void *token,
426 int index, void(*handler)(void *))
428 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
429 int relative_idx = index / cdev->num_hwfns;
431 hwfn->simd_proto_handler[relative_idx].func = handler;
432 hwfn->simd_proto_handler[relative_idx].token = token;
435 static void qed_simd_handler_clean(struct qed_dev *cdev, int index)
437 struct qed_hwfn *hwfn = &cdev->hwfns[index % cdev->num_hwfns];
438 int relative_idx = index / cdev->num_hwfns;
440 memset(&hwfn->simd_proto_handler[relative_idx], 0,
441 sizeof(struct qed_simd_fp_handler));
444 static irqreturn_t qed_msix_sp_int(int irq, void *tasklet)
446 tasklet_schedule((struct tasklet_struct *)tasklet);
450 static irqreturn_t qed_single_int(int irq, void *dev_instance)
452 struct qed_dev *cdev = (struct qed_dev *)dev_instance;
453 struct qed_hwfn *hwfn;
454 irqreturn_t rc = IRQ_NONE;
458 for (i = 0; i < cdev->num_hwfns; i++) {
459 status = qed_int_igu_read_sisr_reg(&cdev->hwfns[i]);
464 hwfn = &cdev->hwfns[i];
466 /* Slowpath interrupt */
467 if (unlikely(status & 0x1)) {
468 tasklet_schedule(hwfn->sp_dpc);
473 /* Fastpath interrupts */
474 for (j = 0; j < 64; j++) {
475 if ((0x2ULL << j) & status) {
476 hwfn->simd_proto_handler[j].func(
477 hwfn->simd_proto_handler[j].token);
478 status &= ~(0x2ULL << j);
483 if (unlikely(status))
484 DP_VERBOSE(hwfn, NETIF_MSG_INTR,
485 "got an unknown interrupt status 0x%llx\n",
492 int qed_slowpath_irq_req(struct qed_hwfn *hwfn)
494 struct qed_dev *cdev = hwfn->cdev;
498 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
500 snprintf(hwfn->name, NAME_SIZE, "sp-%d-%02x:%02x.%02x",
501 id, cdev->pdev->bus->number,
502 PCI_SLOT(cdev->pdev->devfn), hwfn->abs_pf_id);
503 rc = request_irq(cdev->int_params.msix_table[id].vector,
504 qed_msix_sp_int, 0, hwfn->name, hwfn->sp_dpc);
506 DP_VERBOSE(hwfn, (NETIF_MSG_INTR | QED_MSG_SP),
507 "Requested slowpath MSI-X\n");
509 unsigned long flags = 0;
511 snprintf(cdev->name, NAME_SIZE, "%02x:%02x.%02x",
512 cdev->pdev->bus->number, PCI_SLOT(cdev->pdev->devfn),
513 PCI_FUNC(cdev->pdev->devfn));
515 if (cdev->int_params.out.int_mode == QED_INT_MODE_INTA)
516 flags |= IRQF_SHARED;
518 rc = request_irq(cdev->pdev->irq, qed_single_int,
519 flags, cdev->name, cdev);
525 static void qed_slowpath_irq_free(struct qed_dev *cdev)
529 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
530 for_each_hwfn(cdev, i) {
531 if (!cdev->hwfns[i].b_int_requested)
533 synchronize_irq(cdev->int_params.msix_table[i].vector);
534 free_irq(cdev->int_params.msix_table[i].vector,
535 cdev->hwfns[i].sp_dpc);
538 if (QED_LEADING_HWFN(cdev)->b_int_requested)
539 free_irq(cdev->pdev->irq, cdev);
541 qed_int_disable_post_isr_release(cdev);
544 static int qed_nic_stop(struct qed_dev *cdev)
548 rc = qed_hw_stop(cdev);
550 for (i = 0; i < cdev->num_hwfns; i++) {
551 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
553 if (p_hwfn->b_sp_dpc_enabled) {
554 tasklet_disable(p_hwfn->sp_dpc);
555 p_hwfn->b_sp_dpc_enabled = false;
556 DP_VERBOSE(cdev, NETIF_MSG_IFDOWN,
557 "Disabled sp taskelt [hwfn %d] at %p\n",
565 static int qed_nic_reset(struct qed_dev *cdev)
569 rc = qed_hw_reset(cdev);
578 static int qed_nic_setup(struct qed_dev *cdev)
582 rc = qed_resc_alloc(cdev);
586 DP_INFO(cdev, "Allocated qed resources\n");
588 qed_resc_setup(cdev);
593 static int qed_set_int_fp(struct qed_dev *cdev, u16 cnt)
597 /* Mark the fastpath as free/used */
598 cdev->int_params.fp_initialized = cnt ? true : false;
600 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX)
601 limit = cdev->num_hwfns * 63;
602 else if (cdev->int_params.fp_msix_cnt)
603 limit = cdev->int_params.fp_msix_cnt;
608 return min_t(int, cnt, limit);
611 static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info)
613 memset(info, 0, sizeof(struct qed_int_info));
615 if (!cdev->int_params.fp_initialized) {
617 "Protocol driver requested interrupt information, but its support is not yet configured\n");
621 /* Need to expose only MSI-X information; Single IRQ is handled solely
624 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
625 int msix_base = cdev->int_params.fp_msix_base;
627 info->msix_cnt = cdev->int_params.fp_msix_cnt;
628 info->msix = &cdev->int_params.msix_table[msix_base];
634 static int qed_slowpath_setup_int(struct qed_dev *cdev,
635 enum qed_int_mode int_mode)
640 memset(&cdev->int_params, 0, sizeof(struct qed_int_params));
642 cdev->int_params.in.int_mode = int_mode;
643 for_each_hwfn(cdev, i)
644 num_vectors += qed_int_get_num_sbs(&cdev->hwfns[i], NULL) + 1;
645 cdev->int_params.in.num_vectors = num_vectors;
647 /* We want a minimum of one slowpath and one fastpath vector per hwfn */
648 cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;
650 rc = qed_set_int_mode(cdev, false);
652 DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
656 cdev->int_params.fp_msix_base = cdev->num_hwfns;
657 cdev->int_params.fp_msix_cnt = cdev->int_params.out.num_vectors -
663 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, u32 input_len,
664 u8 *input_buf, u32 max_size, u8 *unzip_buf)
668 p_hwfn->stream->next_in = input_buf;
669 p_hwfn->stream->avail_in = input_len;
670 p_hwfn->stream->next_out = unzip_buf;
671 p_hwfn->stream->avail_out = max_size;
673 rc = zlib_inflateInit2(p_hwfn->stream, MAX_WBITS);
676 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "zlib init failed, rc = %d\n",
681 rc = zlib_inflate(p_hwfn->stream, Z_FINISH);
682 zlib_inflateEnd(p_hwfn->stream);
684 if (rc != Z_OK && rc != Z_STREAM_END) {
685 DP_VERBOSE(p_hwfn, NETIF_MSG_DRV, "FW unzip error: %s, rc=%d\n",
686 p_hwfn->stream->msg, rc);
690 return p_hwfn->stream->total_out / 4;
693 static int qed_alloc_stream_mem(struct qed_dev *cdev)
698 for_each_hwfn(cdev, i) {
699 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
701 p_hwfn->stream = kzalloc(sizeof(*p_hwfn->stream), GFP_KERNEL);
705 workspace = vzalloc(zlib_inflate_workspacesize());
708 p_hwfn->stream->workspace = workspace;
714 static void qed_free_stream_mem(struct qed_dev *cdev)
718 for_each_hwfn(cdev, i) {
719 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
724 vfree(p_hwfn->stream->workspace);
725 kfree(p_hwfn->stream);
729 static void qed_update_pf_params(struct qed_dev *cdev,
730 struct qed_pf_params *params)
734 for (i = 0; i < cdev->num_hwfns; i++) {
735 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
737 p_hwfn->pf_params = *params;
741 static int qed_slowpath_start(struct qed_dev *cdev,
742 struct qed_slowpath_params *params)
744 struct qed_mcp_drv_version drv_version;
745 const u8 *data = NULL;
746 struct qed_hwfn *hwfn;
749 rc = request_firmware(&cdev->firmware, QED_FW_FILE_NAME,
753 "Failed to find fw file - /lib/firmware/%s\n",
758 rc = qed_nic_setup(cdev);
762 rc = qed_slowpath_setup_int(cdev, params->int_mode);
766 /* Allocate stream for unzipping */
767 rc = qed_alloc_stream_mem(cdev);
769 DP_NOTICE(cdev, "Failed to allocate stream memory\n");
773 /* Start the slowpath */
774 data = cdev->firmware->data;
776 rc = qed_hw_init(cdev, true, cdev->int_params.out.int_mode,
782 "HW initialization and function start completed successfully\n");
784 hwfn = QED_LEADING_HWFN(cdev);
785 drv_version.version = (params->drv_major << 24) |
786 (params->drv_minor << 16) |
787 (params->drv_rev << 8) |
789 strlcpy(drv_version.name, params->name,
790 MCP_DRV_VER_STR_SIZE - 4);
791 rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
794 DP_NOTICE(cdev, "Failed sending drv version command\n");
801 qed_free_stream_mem(cdev);
802 qed_slowpath_irq_free(cdev);
804 qed_disable_msix(cdev);
808 release_firmware(cdev->firmware);
813 static int qed_slowpath_stop(struct qed_dev *cdev)
818 qed_free_stream_mem(cdev);
821 qed_slowpath_irq_free(cdev);
823 qed_disable_msix(cdev);
826 release_firmware(cdev->firmware);
831 static void qed_set_id(struct qed_dev *cdev, char name[NAME_SIZE],
832 char ver_str[VER_SIZE])
836 memcpy(cdev->name, name, NAME_SIZE);
837 for_each_hwfn(cdev, i)
838 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
840 memcpy(cdev->ver_str, ver_str, VER_SIZE);
841 cdev->drv_type = DRV_ID_DRV_TYPE_LINUX;
844 static u32 qed_sb_init(struct qed_dev *cdev,
845 struct qed_sb_info *sb_info,
847 dma_addr_t sb_phy_addr, u16 sb_id,
848 enum qed_sb_type type)
850 struct qed_hwfn *p_hwfn;
856 /* RoCE uses single engine and CMT uses two engines. When using both
857 * we force only a single engine. Storage uses only engine 0 too.
859 if (type == QED_SB_TYPE_L2_QUEUE)
860 n_hwfns = cdev->num_hwfns;
864 hwfn_index = sb_id % n_hwfns;
865 p_hwfn = &cdev->hwfns[hwfn_index];
866 rel_sb_id = sb_id / n_hwfns;
868 DP_VERBOSE(cdev, NETIF_MSG_INTR,
869 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
870 hwfn_index, rel_sb_id, sb_id);
872 rc = qed_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
873 sb_virt_addr, sb_phy_addr, rel_sb_id);
878 static u32 qed_sb_release(struct qed_dev *cdev,
879 struct qed_sb_info *sb_info,
882 struct qed_hwfn *p_hwfn;
887 hwfn_index = sb_id % cdev->num_hwfns;
888 p_hwfn = &cdev->hwfns[hwfn_index];
889 rel_sb_id = sb_id / cdev->num_hwfns;
891 DP_VERBOSE(cdev, NETIF_MSG_INTR,
892 "hwfn [%d] <--[init]-- SB %04x [0x%04x upper]\n",
893 hwfn_index, rel_sb_id, sb_id);
895 rc = qed_int_sb_release(p_hwfn, sb_info, rel_sb_id);
900 static int qed_set_link(struct qed_dev *cdev,
901 struct qed_link_params *params)
903 struct qed_hwfn *hwfn;
904 struct qed_mcp_link_params *link_params;
911 /* The link should be set only once per PF */
912 hwfn = &cdev->hwfns[0];
914 ptt = qed_ptt_acquire(hwfn);
918 link_params = qed_mcp_get_link_params(hwfn);
919 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
920 link_params->speed.autoneg = params->autoneg;
921 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
922 link_params->speed.advertised_speeds = 0;
923 if ((params->adv_speeds & SUPPORTED_1000baseT_Half) ||
924 (params->adv_speeds & SUPPORTED_1000baseT_Full))
925 link_params->speed.advertised_speeds |=
926 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
927 if (params->adv_speeds & SUPPORTED_10000baseKR_Full)
928 link_params->speed.advertised_speeds |=
929 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
930 if (params->adv_speeds & SUPPORTED_40000baseLR4_Full)
931 link_params->speed.advertised_speeds |=
932 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
933 if (params->adv_speeds & 0)
934 link_params->speed.advertised_speeds |=
935 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
936 if (params->adv_speeds & 0)
937 link_params->speed.advertised_speeds |=
938 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G;
940 if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
941 link_params->speed.forced_speed = params->forced_speed;
943 rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
945 qed_ptt_release(hwfn, ptt);
950 static int qed_get_port_type(u32 media_type)
954 switch (media_type) {
955 case MEDIA_SFPP_10G_FIBER:
956 case MEDIA_SFP_1G_FIBER:
957 case MEDIA_XFP_FIBER:
959 port_type = PORT_FIBRE;
961 case MEDIA_DA_TWINAX:
967 case MEDIA_NOT_PRESENT:
968 port_type = PORT_NONE;
970 case MEDIA_UNSPECIFIED:
972 port_type = PORT_OTHER;
978 static void qed_fill_link(struct qed_hwfn *hwfn,
979 struct qed_link_output *if_link)
981 struct qed_mcp_link_params params;
982 struct qed_mcp_link_state link;
983 struct qed_mcp_link_capabilities link_caps;
986 memset(if_link, 0, sizeof(*if_link));
988 /* Prepare source inputs */
989 memcpy(¶ms, qed_mcp_get_link_params(hwfn), sizeof(params));
990 memcpy(&link, qed_mcp_get_link_state(hwfn), sizeof(link));
991 memcpy(&link_caps, qed_mcp_get_link_capabilities(hwfn),
994 /* Set the link parameters to pass to protocol driver */
996 if_link->link_up = true;
998 /* TODO - at the moment assume supported and advertised speed equal */
999 if_link->supported_caps = SUPPORTED_FIBRE;
1000 if (params.speed.autoneg)
1001 if_link->supported_caps |= SUPPORTED_Autoneg;
1002 if (params.pause.autoneg ||
1003 (params.pause.forced_rx && params.pause.forced_tx))
1004 if_link->supported_caps |= SUPPORTED_Asym_Pause;
1005 if (params.pause.autoneg || params.pause.forced_rx ||
1006 params.pause.forced_tx)
1007 if_link->supported_caps |= SUPPORTED_Pause;
1009 if_link->advertised_caps = if_link->supported_caps;
1010 if (params.speed.advertised_speeds &
1011 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1012 if_link->advertised_caps |= SUPPORTED_1000baseT_Half |
1013 SUPPORTED_1000baseT_Full;
1014 if (params.speed.advertised_speeds &
1015 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1016 if_link->advertised_caps |= SUPPORTED_10000baseKR_Full;
1017 if (params.speed.advertised_speeds &
1018 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1019 if_link->advertised_caps |= SUPPORTED_40000baseLR4_Full;
1020 if (params.speed.advertised_speeds &
1021 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1022 if_link->advertised_caps |= 0;
1023 if (params.speed.advertised_speeds &
1024 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
1025 if_link->advertised_caps |= 0;
1027 if (link_caps.speed_capabilities &
1028 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1029 if_link->supported_caps |= SUPPORTED_1000baseT_Half |
1030 SUPPORTED_1000baseT_Full;
1031 if (link_caps.speed_capabilities &
1032 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1033 if_link->supported_caps |= SUPPORTED_10000baseKR_Full;
1034 if (link_caps.speed_capabilities &
1035 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1036 if_link->supported_caps |= SUPPORTED_40000baseLR4_Full;
1037 if (link_caps.speed_capabilities &
1038 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1039 if_link->supported_caps |= 0;
1040 if (link_caps.speed_capabilities &
1041 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G)
1042 if_link->supported_caps |= 0;
1045 if_link->speed = link.speed;
1047 /* TODO - fill duplex properly */
1048 if_link->duplex = DUPLEX_FULL;
1049 qed_mcp_get_media_type(hwfn->cdev, &media_type);
1050 if_link->port = qed_get_port_type(media_type);
1052 if_link->autoneg = params.speed.autoneg;
1054 if (params.pause.autoneg)
1055 if_link->pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1056 if (params.pause.forced_rx)
1057 if_link->pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1058 if (params.pause.forced_tx)
1059 if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1061 /* Link partner capabilities */
1062 if (link.partner_adv_speed &
1063 QED_LINK_PARTNER_SPEED_1G_HD)
1064 if_link->lp_caps |= SUPPORTED_1000baseT_Half;
1065 if (link.partner_adv_speed &
1066 QED_LINK_PARTNER_SPEED_1G_FD)
1067 if_link->lp_caps |= SUPPORTED_1000baseT_Full;
1068 if (link.partner_adv_speed &
1069 QED_LINK_PARTNER_SPEED_10G)
1070 if_link->lp_caps |= SUPPORTED_10000baseKR_Full;
1071 if (link.partner_adv_speed &
1072 QED_LINK_PARTNER_SPEED_40G)
1073 if_link->lp_caps |= SUPPORTED_40000baseLR4_Full;
1074 if (link.partner_adv_speed &
1075 QED_LINK_PARTNER_SPEED_50G)
1076 if_link->lp_caps |= 0;
1077 if (link.partner_adv_speed &
1078 QED_LINK_PARTNER_SPEED_100G)
1079 if_link->lp_caps |= 0;
1081 if (link.an_complete)
1082 if_link->lp_caps |= SUPPORTED_Autoneg;
1084 if (link.partner_adv_pause)
1085 if_link->lp_caps |= SUPPORTED_Pause;
1086 if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
1087 link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
1088 if_link->lp_caps |= SUPPORTED_Asym_Pause;
1091 static void qed_get_current_link(struct qed_dev *cdev,
1092 struct qed_link_output *if_link)
1094 qed_fill_link(&cdev->hwfns[0], if_link);
1097 void qed_link_update(struct qed_hwfn *hwfn)
1099 void *cookie = hwfn->cdev->ops_cookie;
1100 struct qed_common_cb_ops *op = hwfn->cdev->protocol_ops.common;
1101 struct qed_link_output if_link;
1103 qed_fill_link(hwfn, &if_link);
1105 if (IS_LEAD_HWFN(hwfn) && cookie)
1106 op->link_update(cookie, &if_link);
1109 static int qed_drain(struct qed_dev *cdev)
1111 struct qed_hwfn *hwfn;
1112 struct qed_ptt *ptt;
1115 for_each_hwfn(cdev, i) {
1116 hwfn = &cdev->hwfns[i];
1117 ptt = qed_ptt_acquire(hwfn);
1119 DP_NOTICE(hwfn, "Failed to drain NIG; No PTT\n");
1122 rc = qed_mcp_drain(hwfn, ptt);
1125 qed_ptt_release(hwfn, ptt);
1131 static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
1133 struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
1134 struct qed_ptt *ptt;
1137 ptt = qed_ptt_acquire(hwfn);
1141 status = qed_mcp_set_led(hwfn, ptt, mode);
1143 qed_ptt_release(hwfn, ptt);
1148 const struct qed_common_ops qed_common_ops_pass = {
1149 .probe = &qed_probe,
1150 .remove = &qed_remove,
1151 .set_power_state = &qed_set_power_state,
1152 .set_id = &qed_set_id,
1153 .update_pf_params = &qed_update_pf_params,
1154 .slowpath_start = &qed_slowpath_start,
1155 .slowpath_stop = &qed_slowpath_stop,
1156 .set_fp_int = &qed_set_int_fp,
1157 .get_fp_int = &qed_get_int_fp,
1158 .sb_init = &qed_sb_init,
1159 .sb_release = &qed_sb_release,
1160 .simd_handler_config = &qed_simd_handler_config,
1161 .simd_handler_clean = &qed_simd_handler_clean,
1162 .set_link = &qed_set_link,
1163 .get_link = &qed_get_current_link,
1164 .drain = &qed_drain,
1165 .update_msglvl = &qed_init_dp,
1166 .chain_alloc = &qed_chain_alloc,
1167 .chain_free = &qed_chain_free,
1168 .set_led = &qed_set_led,
1171 u32 qed_get_protocol_version(enum qed_protocol protocol)
1174 case QED_PROTOCOL_ETH:
1175 return QED_ETH_INTERFACE_VERSION;
1180 EXPORT_SYMBOL(qed_get_protocol_version);