drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * qlcnic_83xx_idc_detach_driver
 390  *
 391  * @adapter: adapter structure
 392  * Detach net interface, stop TX and cleanup resources before the HW reset.
 393  * Returns: None
 394  *
 395  **/
 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 397 {
 398         int i;
 399         struct net_device *netdev = adapter->netdev;
 400
 401         netif_device_detach(netdev);
 402         qlcnic_83xx_detach_mailbox_work(adapter);
 403
 404         /* Disable mailbox interrupt */
 405         qlcnic_83xx_disable_mbx_intr(adapter);
 406         qlcnic_down(adapter, netdev);
 407         for (i = 0; i < adapter->ahw->num_msix; i++) {
 408                 adapter->ahw->intr_tbl[i].id = i;
 409                 adapter->ahw->intr_tbl[i].enabled = 0;
 410                 adapter->ahw->intr_tbl[i].src = 0;
 411         }
 412
 413         if (qlcnic_sriov_pf_check(adapter))
 414                 qlcnic_sriov_pf_reset(adapter);
 415 }
 416
 417 /**
 418  * qlcnic_83xx_idc_attach_driver
 419  *
 420  * @adapter: adapter structure
 421  *
 422  * Re-attach and re-enable net interface
 423  * Returns: None
 424  *
 425  **/
 426 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 427 {
 428         struct net_device *netdev = adapter->netdev;
 429
 430         if (netif_running(netdev)) {
 431                 if (qlcnic_up(adapter, netdev))
 432                         goto done;
 433                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 434         }
 435 done:
 436         netif_device_attach(netdev);
 437 }
 438
 439 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 440                                               int lock)
 441 {
 442         if (lock) {
 443                 if (qlcnic_83xx_lock_driver(adapter))
 444                         return -EBUSY;
 445         }
 446
 447         qlcnic_83xx_idc_clear_registers(adapter, 0);
 448         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 449         if (lock)
 450                 qlcnic_83xx_unlock_driver(adapter);
 451
 452         qlcnic_83xx_idc_log_state_history(adapter);
 453         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 454
 455         return 0;
 456 }
 457
 458 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 459                                             int lock)
 460 {
 461         if (lock) {
 462                 if (qlcnic_83xx_lock_driver(adapter))
 463                         return -EBUSY;
 464         }
 465
 466         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 467
 468         if (lock)
 469                 qlcnic_83xx_unlock_driver(adapter);
 470
 471         return 0;
 472 }
 473
 474 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 475                                               int lock)
 476 {
 477         if (lock) {
 478                 if (qlcnic_83xx_lock_driver(adapter))
 479                         return -EBUSY;
 480         }
 481
 482         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 483                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 484
 485         if (lock)
 486                 qlcnic_83xx_unlock_driver(adapter);
 487
 488         return 0;
 489 }
 490
 491 static int
 492 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 493 {
 494         if (lock) {
 495                 if (qlcnic_83xx_lock_driver(adapter))
 496                         return -EBUSY;
 497         }
 498
 499         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 500                QLC_83XX_IDC_DEV_NEED_RESET);
 501
 502         if (lock)
 503                 qlcnic_83xx_unlock_driver(adapter);
 504
 505         return 0;
 506 }
 507
 508 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 509                                              int lock)
 510 {
 511         if (lock) {
 512                 if (qlcnic_83xx_lock_driver(adapter))
 513                         return -EBUSY;
 514         }
 515
 516         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 517         if (lock)
 518                 qlcnic_83xx_unlock_driver(adapter);
 519
 520         return 0;
 521 }
 522
 523 /**
 524  * qlcnic_83xx_idc_find_reset_owner_id
 525  *
 526  * @adapter: adapter structure
 527  *
 528  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 529  * Within the same class, function with lowest PCI ID assumes ownership
 530  *
 531  * Returns: reset owner id or failure indication (-EIO)
 532  *
 533  **/
 534 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 535 {
 536         u32 reg, reg1, reg2, i, j, owner, class;
 537
 538         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 539         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 540         owner = QLCNIC_TYPE_NIC;
 541         i = 0;
 542         j = 0;
 543         reg = reg1;
 544
 545         do {
 546                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 547                 if (class == owner)
 548                         break;
 549                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 550                         reg = reg2;
 551                         j = 0;
 552                 } else {
 553                         j++;
 554                 }
 555
 556                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 557                         if (owner == QLCNIC_TYPE_NIC)
 558                                 owner = QLCNIC_TYPE_ISCSI;
 559                         else if (owner == QLCNIC_TYPE_ISCSI)
 560                                 owner = QLCNIC_TYPE_FCOE;
 561                         else if (owner == QLCNIC_TYPE_FCOE)
 562                                 return -EIO;
 563                         reg = reg1;
 564                         j = 0;
 565                         i = 0;
 566                 }
 567         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 568
 569         return i;
 570 }
 571
 572 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 573 {
 574         int ret = 0;
 575
 576         ret = qlcnic_83xx_restart_hw(adapter);
 577
 578         if (ret) {
 579                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 580         } else {
 581                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 582                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 583         }
 584
 585         return ret;
 586 }
 587
 588 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 589 {
 590         u32 status;
 591
 592         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 593
 594         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 595                 dev_err(&adapter->pdev->dev,
 596                         "peg halt status1=0x%x\n", status);
 597                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 598                         dev_err(&adapter->pdev->dev,
 599                                 "On board active cooling fan failed. "
 600                                 "Device has been halted.\n");
 601                         dev_err(&adapter->pdev->dev,
 602                                 "Replace the adapter.\n");
 603                         return -EIO;
 604                 }
 605         }
 606
 607         return 0;
 608 }
 609
 610 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 611 {
 612         int err;
 613
 614         qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox);
 615         qlcnic_83xx_enable_mbx_interrupt(adapter);
 616
 617         /* register for NIC IDC AEN Events */
 618         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 619
 620         err = qlcnic_sriov_pf_reinit(adapter);
 621         if (err)
 622                 return err;
 623
 624         qlcnic_83xx_enable_mbx_interrupt(adapter);
 625
 626         if (qlcnic_83xx_configure_opmode(adapter)) {
 627                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 628                 return -EIO;
 629         }
 630
 631         if (adapter->nic_ops->init_driver(adapter)) {
 632                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 633                 return -EIO;
 634         }
 635
 636         qlcnic_set_drv_version(adapter);
 637         qlcnic_83xx_idc_attach_driver(adapter);
 638
 639         return 0;
 640 }
 641
 642 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 643 {
 644         struct qlcnic_hardware_context *ahw = adapter->ahw;
 645
 646         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 647         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 648         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 649
 650         ahw->idc.quiesce_req = 0;
 651         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 652         ahw->idc.err_code = 0;
 653         ahw->idc.collect_dump = 0;
 654         ahw->reset_context = 0;
 655         adapter->tx_timeo_cnt = 0;
 656         ahw->idc.delay_reset = 0;
 657
 658         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 659 }
 660
 661 /**
 662  * qlcnic_83xx_idc_ready_state_entry
 663  *
 664  * @adapter: adapter structure
 665  *
 666  * Perform ready state initialization, this routine will get invoked only
 667  * once from READY state.
 668  *
 669  * Returns: Error code or Success(0)
 670  *
 671  **/
 672 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 673 {
 674         struct qlcnic_hardware_context *ahw = adapter->ahw;
 675
 676         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 677                 qlcnic_83xx_idc_update_idc_params(adapter);
 678                 /* Re-attach the device if required */
 679                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 680                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 681                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 682                                 return -EIO;
 683                 }
 684         }
 685
 686         return 0;
 687 }
 688
 689 /**
 690  * qlcnic_83xx_idc_vnic_pf_entry
 691  *
 692  * @adapter: adapter structure
 693  *
 694  * Ensure vNIC mode privileged function starts only after vNIC mode is
 695  * enabled by management function.
 696  * If vNIC mode is ready, start initialization.
 697  *
 698  * Returns: -EIO or 0
 699  *
 700  **/
 701 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 702 {
 703         u32 state;
 704         struct qlcnic_hardware_context *ahw = adapter->ahw;
 705
 706         /* Privileged function waits till mgmt function enables VNIC mode */
 707         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 708         if (state != QLCNIC_DEV_NPAR_OPER) {
 709                 if (!ahw->idc.vnic_wait_limit--) {
 710                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 711                         return -EIO;
 712                 }
 713                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 714                 return -EIO;
 715
 716         } else {
 717                 /* Perform one time initialization from ready state */
 718                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 719                         qlcnic_83xx_idc_update_idc_params(adapter);
 720
 721                         /* If the previous state is UNKNOWN, device will be
 722                            already attached properly by Init routine*/
 723                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 724                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 725                                         return -EIO;
 726                         }
 727                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 728                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 729                 }
 730         }
 731
 732         return 0;
 733 }
 734
 735 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 736 {
 737         adapter->ahw->idc.err_code = -EIO;
 738         dev_err(&adapter->pdev->dev,
 739                 "%s: Device in unknown state\n", __func__);
 740         return 0;
 741 }
 742
 743 /**
 744  * qlcnic_83xx_idc_cold_state
 745  *
 746  * @adapter: adapter structure
 747  *
 748  * If HW is up and running device will enter READY state.
 749  * If firmware image from host needs to be loaded, device is
 750  * forced to start with the file firmware image.
 751  *
 752  * Returns: Error code or Success(0)
 753  *
 754  **/
 755 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 756 {
 757         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 758         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 759
 760         if (qlcnic_load_fw_file) {
 761                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 762         } else {
 763                 if (qlcnic_83xx_check_hw_status(adapter)) {
 764                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 765                         return -EIO;
 766                 } else {
 767                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 768                 }
 769         }
 770         return 0;
 771 }
 772
 773 /**
 774  * qlcnic_83xx_idc_init_state
 775  *
 776  * @adapter: adapter structure
 777  *
 778  * Reset owner will restart the device from this state.
 779  * Device will enter failed state if it remains
 780  * in this state for more than DEV_INIT time limit.
 781  *
 782  * Returns: Error code or Success(0)
 783  *
 784  **/
 785 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 786 {
 787         int timeout, ret = 0;
 788         u32 owner;
 789
 790         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 791         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 792                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 793                 if (adapter->ahw->pci_func == owner)
 794                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 795         } else {
 796                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 797                 return ret;
 798         }
 799
 800         return ret;
 801 }
 802
 803 /**
 804  * qlcnic_83xx_idc_ready_state
 805  *
 806  * @adapter: adapter structure
 807  *
 808  * Perform IDC protocol specicifed actions after monitoring device state and
 809  * events.
 810  *
 811  * Returns: Error code or Success(0)
 812  *
 813  **/
 814 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 815 {
 816         struct qlcnic_hardware_context *ahw = adapter->ahw;
 817         struct qlcnic_mailbox *mbx = ahw->mailbox;
 818         int ret = 0;
 819         u32 val;
 820
 821         /* Perform NIC configuration based ready state entry actions */
 822         if (ahw->idc.state_entry(adapter))
 823                 return -EIO;
 824
 825         if (qlcnic_check_temp(adapter)) {
 826                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 827                         qlcnic_83xx_idc_check_fan_failure(adapter);
 828                         dev_err(&adapter->pdev->dev,
 829                                 "Error: device temperature %d above limits\n",
 830                                 adapter->ahw->temp);
 831                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 832                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 833                         qlcnic_83xx_idc_detach_driver(adapter);
 834                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 835                         return -EIO;
 836                 }
 837         }
 838
 839         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 840         ret = qlcnic_83xx_check_heartbeat(adapter);
 841         if (ret) {
 842                 adapter->flags |= QLCNIC_FW_HANG;
 843                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 844                         clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 845                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 846                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 847                 }
 848                 return -EIO;
 849         }
 850
 851         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 852                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 853
 854                 /* Move to need reset state and prepare for reset */
 855                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 856                 return ret;
 857         }
 858
 859         /* Check for soft reset request */
 860         if (ahw->reset_context &&
 861             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 862                 adapter->ahw->reset_context = 0;
 863                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 864                 return ret;
 865         }
 866
 867         /* Move to need quiesce state if requested */
 868         if (adapter->ahw->idc.quiesce_req) {
 869                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 870                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 871                 return ret;
 872         }
 873
 874         return ret;
 875 }
 876
 877 /**
 878  * qlcnic_83xx_idc_need_reset_state
 879  *
 880  * @adapter: adapter structure
 881  *
 882  * Device will remain in this state until:
 883  *      Reset request ACK's are recieved from all the functions
 884  *      Wait time exceeds max time limit
 885  *
 886  * Returns: Error code or Success(0)
 887  *
 888  **/
 889 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 890 {
 891         struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
 892         int ret = 0;
 893
 894         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 895                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 896                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 897                 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
 898                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 899                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 900
 901                 if (qlcnic_check_diag_status(adapter)) {
 902                         dev_info(&adapter->pdev->dev,
 903                                  "%s: Wait for diag completion\n", __func__);
 904                         adapter->ahw->idc.delay_reset = 1;
 905                         return 0;
 906                 } else {
 907                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 908                         qlcnic_83xx_idc_detach_driver(adapter);
 909                 }
 910         }
 911
 912         if (qlcnic_check_diag_status(adapter)) {
 913                 dev_info(&adapter->pdev->dev,
 914                          "%s: Wait for diag completion\n", __func__);
 915                 return  -1;
 916         } else {
 917                 if (adapter->ahw->idc.delay_reset) {
 918                         qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 919                         qlcnic_83xx_idc_detach_driver(adapter);
 920                         adapter->ahw->idc.delay_reset = 0;
 921                 }
 922
 923                 /* Check for ACK from other functions */
 924                 ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 925                 if (ret) {
 926                         dev_info(&adapter->pdev->dev,
 927                                  "%s: Waiting for reset ACK\n", __func__);
 928                         return -1;
 929                 }
 930         }
 931
 932         /* Transit to INIT state and restart the HW */
 933         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 934
 935         return ret;
 936 }
 937
 938 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 939 {
 940         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 941         return 0;
 942 }
 943
 944 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 945 {
 946         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 947         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 948         adapter->ahw->idc.err_code = -EIO;
 949
 950         return 0;
 951 }
 952
 953 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 954 {
 955         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 956         return 0;
 957 }
 958
 959 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 960                                                 u32 state)
 961 {
 962         u32 cur, prev, next;
 963
 964         cur = adapter->ahw->idc.curr_state;
 965         prev = adapter->ahw->idc.prev_state;
 966         next = state;
 967
 968         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 969             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 970                 dev_err(&adapter->pdev->dev,
 971                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 972                         __func__, cur, prev, state);
 973                 return 1;
 974         }
 975
 976         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 977             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 978                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 979                     (next != QLC_83XX_IDC_DEV_READY)) {
 980                         dev_err(&adapter->pdev->dev,
 981                                 "%s: failed, cur %d prev %d next %d\n",
 982                                 __func__, cur, prev, next);
 983                         return 1;
 984                 }
 985         }
 986
 987         if (next == QLC_83XX_IDC_DEV_INIT) {
 988                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 989                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 990                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 991                         dev_err(&adapter->pdev->dev,
 992                                 "%s: failed, cur %d prev %d next %d\n",
 993                                 __func__, cur, prev, next);
 994                         return 1;
 995                 }
 996         }
 997
 998         return 0;
 999 }
1000
1001 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
1002 {
1003         if (adapter->fhash.fnum)
1004                 qlcnic_prune_lb_filters(adapter);
1005 }
1006
1007 /**
1008  * qlcnic_83xx_idc_poll_dev_state
1009  *
1010  * @work: kernel work queue structure used to schedule the function
1011  *
1012  * Poll device state periodically and perform state specific
1013  * actions defined by Inter Driver Communication (IDC) protocol.
1014  *
1015  * Returns: None
1016  *
1017  **/
1018 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
1019 {
1020         struct qlcnic_adapter *adapter;
1021         u32 state;
1022
1023         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
1024         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1025
1026         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1027                 qlcnic_83xx_idc_log_state_history(adapter);
1028                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1029         } else {
1030                 adapter->ahw->idc.curr_state = state;
1031         }
1032
1033         switch (adapter->ahw->idc.curr_state) {
1034         case QLC_83XX_IDC_DEV_READY:
1035                 qlcnic_83xx_idc_ready_state(adapter);
1036                 break;
1037         case QLC_83XX_IDC_DEV_NEED_RESET:
1038                 qlcnic_83xx_idc_need_reset_state(adapter);
1039                 break;
1040         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1041                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1042                 break;
1043         case QLC_83XX_IDC_DEV_FAILED:
1044                 qlcnic_83xx_idc_failed_state(adapter);
1045                 return;
1046         case QLC_83XX_IDC_DEV_INIT:
1047                 qlcnic_83xx_idc_init_state(adapter);
1048                 break;
1049         case QLC_83XX_IDC_DEV_QUISCENT:
1050                 qlcnic_83xx_idc_quiesce_state(adapter);
1051                 break;
1052         default:
1053                 qlcnic_83xx_idc_unknown_state(adapter);
1054                 return;
1055         }
1056         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1057         qlcnic_83xx_periodic_tasks(adapter);
1058
1059         /* Re-schedule the function */
1060         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1061                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1062                                      adapter->ahw->idc.delay);
1063 }
1064
1065 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1066 {
1067         u32 idc_params, val;
1068
1069         if (qlcnic_83xx_lockless_flash_read32(adapter,
1070                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1071                                               (u8 *)&idc_params, 1)) {
1072                 dev_info(&adapter->pdev->dev,
1073                          "%s:failed to get IDC params from flash\n", __func__);
1074                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1075                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1076         } else {
1077                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1078                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1079         }
1080
1081         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1082         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1083         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1084         adapter->ahw->idc.err_code = 0;
1085         adapter->ahw->idc.collect_dump = 0;
1086         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1087
1088         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1089         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1090
1091         /* Check if reset recovery is disabled */
1092         if (!qlcnic_auto_fw_reset) {
1093                 /* Propagate do not reset request to other functions */
1094                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1095                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1096                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1097         }
1098 }
1099
1100 static int
1101 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1102 {
1103         u32 state, val;
1104
1105         if (qlcnic_83xx_lock_driver(adapter))
1106                 return -EIO;
1107
1108         /* Clear driver lock register */
1109         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1110         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1111                 qlcnic_83xx_unlock_driver(adapter);
1112                 return -EIO;
1113         }
1114
1115         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1116         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1117                 qlcnic_83xx_unlock_driver(adapter);
1118                 return -EIO;
1119         }
1120
1121         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1122                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1123                        QLC_83XX_IDC_DEV_COLD);
1124                 state = QLC_83XX_IDC_DEV_COLD;
1125         }
1126
1127         adapter->ahw->idc.curr_state = state;
1128         /* First to load function should cold boot the device */
1129         if (state == QLC_83XX_IDC_DEV_COLD)
1130                 qlcnic_83xx_idc_cold_state_handler(adapter);
1131
1132         /* Check if reset recovery is enabled */
1133         if (qlcnic_auto_fw_reset) {
1134                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1135                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1136                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1137         }
1138
1139         qlcnic_83xx_unlock_driver(adapter);
1140
1141         return 0;
1142 }
1143
1144 int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1145 {
1146         int ret = -EIO;
1147
1148         qlcnic_83xx_setup_idc_parameters(adapter);
1149
1150         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1151                 return ret;
1152
1153         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1154                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1155                         return -EIO;
1156         } else {
1157                 if (qlcnic_83xx_idc_check_major_version(adapter))
1158                         return -EIO;
1159         }
1160
1161         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1162
1163         return 0;
1164 }
1165
1166 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1167 {
1168         int id;
1169         u32 val;
1170
1171         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1172                 usleep_range(10000, 11000);
1173
1174         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1175         id = id & 0xFF;
1176
1177         if (id == adapter->portnum) {
1178                 dev_err(&adapter->pdev->dev,
1179                         "%s: wait for lock recovery.. %d\n", __func__, id);
1180                 msleep(20);
1181                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1182                 id = id & 0xFF;
1183         }
1184
1185         /* Clear driver presence bit */
1186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1187         val = val & ~(1 << adapter->portnum);
1188         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1189         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1190         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1191
1192         cancel_delayed_work_sync(&adapter->fw_work);
1193 }
1194
1195 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1196 {
1197         u32 val;
1198
1199         if (qlcnic_sriov_vf_check(adapter))
1200                 return;
1201
1202         if (qlcnic_83xx_lock_driver(adapter)) {
1203                 dev_err(&adapter->pdev->dev,
1204                         "%s:failed, please retry\n", __func__);
1205                 return;
1206         }
1207
1208         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1209         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1210             !qlcnic_auto_fw_reset) {
1211                 dev_err(&adapter->pdev->dev,
1212                         "%s:failed, device in non reset mode\n", __func__);
1213                 qlcnic_83xx_unlock_driver(adapter);
1214                 return;
1215         }
1216
1217         if (key == QLCNIC_FORCE_FW_RESET) {
1218                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1219                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1220                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1221         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1222                 adapter->ahw->idc.collect_dump = 1;
1223         }
1224
1225         qlcnic_83xx_unlock_driver(adapter);
1226         return;
1227 }
1228
1229 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1230 {
1231         u8 *p_cache;
1232         u32 src, size;
1233         u64 dest;
1234         int ret = -EIO;
1235
1236         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1237         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1238         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1239
1240         /* alignment check */
1241         if (size & 0xF)
1242                 size = (size + 16) & ~0xF;
1243
1244         p_cache = kzalloc(size, GFP_KERNEL);
1245         if (p_cache == NULL)
1246                 return -ENOMEM;
1247
1248         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1249                                                 size / sizeof(u32));
1250         if (ret) {
1251                 kfree(p_cache);
1252                 return ret;
1253         }
1254         /* 16 byte write to MS memory */
1255         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1256                                           size / 16);
1257         if (ret) {
1258                 kfree(p_cache);
1259                 return ret;
1260         }
1261         kfree(p_cache);
1262
1263         return ret;
1264 }
1265
1266 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1267 {
1268         u32 dest, *p_cache;
1269         u64 addr;
1270         u8 data[16];
1271         size_t size;
1272         int i, ret = -EIO;
1273
1274         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1275         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1276         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1277         addr = (u64)dest;
1278
1279         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1280                                           (u32 *)p_cache, size / 16);
1281         if (ret) {
1282                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1283                 release_firmware(adapter->ahw->fw_info.fw);
1284                 adapter->ahw->fw_info.fw = NULL;
1285                 return -EIO;
1286         }
1287
1288         /* alignment check */
1289         if (adapter->ahw->fw_info.fw->size & 0xF) {
1290                 addr = dest + size;
1291                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1292                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1293                 for (; i < 16; i++)
1294                         data[i] = 0;
1295                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1296                                                   (u32 *)data, 1);
1297                 if (ret) {
1298                         dev_err(&adapter->pdev->dev,
1299                                 "MS memory write failed\n");
1300                         release_firmware(adapter->ahw->fw_info.fw);
1301                         adapter->ahw->fw_info.fw = NULL;
1302                         return -EIO;
1303                 }
1304         }
1305         release_firmware(adapter->ahw->fw_info.fw);
1306         adapter->ahw->fw_info.fw = NULL;
1307
1308         return 0;
1309 }
1310
1311 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1312 {
1313         int i, j;
1314         u32 val = 0, val1 = 0, reg = 0;
1315
1316         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1317         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1318
1319         for (j = 0; j < 2; j++) {
1320                 if (j == 0) {
1321                         dev_info(&adapter->pdev->dev,
1322                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1323                         reg = QLC_83XX_PORT0_THRESHOLD;
1324                 } else if (j == 1) {
1325                         dev_info(&adapter->pdev->dev,
1326                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1327                         reg = QLC_83XX_PORT1_THRESHOLD;
1328                 }
1329                 for (i = 0; i < 8; i++) {
1330                         val = QLCRD32(adapter, reg + (i * 0x4));
1331                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1332                 }
1333                 dev_info(&adapter->pdev->dev, "\n");
1334         }
1335
1336         for (j = 0; j < 2; j++) {
1337                 if (j == 0) {
1338                         dev_info(&adapter->pdev->dev,
1339                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1340                         reg = QLC_83XX_PORT0_TC_MC_REG;
1341                 } else if (j == 1) {
1342                         dev_info(&adapter->pdev->dev,
1343                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1344                         reg = QLC_83XX_PORT1_TC_MC_REG;
1345                 }
1346                 for (i = 0; i < 4; i++) {
1347                         val = QLCRD32(adapter, reg + (i * 0x4));
1348                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1349                 }
1350                 dev_info(&adapter->pdev->dev, "\n");
1351         }
1352
1353         for (j = 0; j < 2; j++) {
1354                 if (j == 0) {
1355                         dev_info(&adapter->pdev->dev,
1356                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1357                         reg = QLC_83XX_PORT0_TC_STATS;
1358                 } else if (j == 1) {
1359                         dev_info(&adapter->pdev->dev,
1360                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1361                         reg = QLC_83XX_PORT1_TC_STATS;
1362                 }
1363                 for (i = 7; i >= 0; i--) {
1364                         val = QLCRD32(adapter, reg);
1365                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1366                         QLCWR32(adapter, reg, (val | (i << 29)));
1367                         val = QLCRD32(adapter, reg);
1368                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1369                 }
1370                 dev_info(&adapter->pdev->dev, "\n");
1371         }
1372
1373         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1374         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1375         dev_info(&adapter->pdev->dev,
1376                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1377                  val, val1);
1378 }
1379
1380
1381 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1382 {
1383         u32 reg = 0, i, j;
1384
1385         if (qlcnic_83xx_lock_driver(adapter)) {
1386                 dev_err(&adapter->pdev->dev,
1387                         "%s:failed to acquire driver lock\n", __func__);
1388                 return;
1389         }
1390
1391         qlcnic_83xx_dump_pause_control_regs(adapter);
1392         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1393
1394         for (j = 0; j < 2; j++) {
1395                 if (j == 0)
1396                         reg = QLC_83XX_PORT0_THRESHOLD;
1397                 else if (j == 1)
1398                         reg = QLC_83XX_PORT1_THRESHOLD;
1399
1400                 for (i = 0; i < 8; i++)
1401                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1402         }
1403
1404         for (j = 0; j < 2; j++) {
1405                 if (j == 0)
1406                         reg = QLC_83XX_PORT0_TC_MC_REG;
1407                 else if (j == 1)
1408                         reg = QLC_83XX_PORT1_TC_MC_REG;
1409
1410                 for (i = 0; i < 4; i++)
1411                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1412         }
1413
1414         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1415         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1416         dev_info(&adapter->pdev->dev,
1417                  "Disabled pause frames successfully on all ports\n");
1418         qlcnic_83xx_unlock_driver(adapter);
1419 }
1420
1421 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1422 {
1423         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1424         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1425         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1426         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1427         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1428         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1429         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1430         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1431         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1432 }
1433
1434 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1435 {
1436         u32 heartbeat, peg_status;
1437         int retries, ret = -EIO;
1438
1439         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1440         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1441                                                QLCNIC_PEG_ALIVE_COUNTER);
1442
1443         do {
1444                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1445                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1446                                                 QLCNIC_PEG_ALIVE_COUNTER);
1447                 if (heartbeat != p_dev->heartbeat) {
1448                         ret = QLCNIC_RCODE_SUCCESS;
1449                         break;
1450                 }
1451         } while (--retries);
1452
1453         if (ret) {
1454                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1455                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1456                 qlcnic_83xx_disable_pause_frames(p_dev);
1457                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1458                                                  QLCNIC_PEG_HALT_STATUS1);
1459                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1460                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1461                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1462                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1463                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1464                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1465                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1466                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1467                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1468                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1469                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1470
1471                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1472                         dev_err(&p_dev->pdev->dev,
1473                                 "Device is being reset err code 0x00006700.\n");
1474         }
1475
1476         return ret;
1477 }
1478
1479 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1480 {
1481         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1482         u32 val;
1483
1484         do {
1485                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1486                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1487                         return 0;
1488                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1489         } while (--retries);
1490
1491         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1492         return -EIO;
1493 }
1494
1495 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1496 {
1497         int err;
1498
1499         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1500         if (err)
1501                 return err;
1502
1503         err = qlcnic_83xx_check_heartbeat(p_dev);
1504         if (err)
1505                 return err;
1506
1507         return err;
1508 }
1509
1510 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1511                                 int duration, u32 mask, u32 status)
1512 {
1513         u32 value;
1514         int timeout_error;
1515         u8 retries;
1516
1517         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1518         retries = duration / 10;
1519
1520         do {
1521                 if ((value & mask) != status) {
1522                         timeout_error = 1;
1523                         msleep(duration / 10);
1524                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1525                 } else {
1526                         timeout_error = 0;
1527                         break;
1528                 }
1529         } while (retries--);
1530
1531         if (timeout_error) {
1532                 p_dev->ahw->reset.seq_error++;
1533                 dev_err(&p_dev->pdev->dev,
1534                         "%s: Timeout Err, entry_num = %d\n",
1535                         __func__, p_dev->ahw->reset.seq_index);
1536                 dev_err(&p_dev->pdev->dev,
1537                         "0x%08x 0x%08x 0x%08x\n",
1538                         value, mask, status);
1539         }
1540
1541         return timeout_error;
1542 }
1543
1544 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1545 {
1546         u32 sum = 0;
1547         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1548         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1549
1550         while (count-- > 0)
1551                 sum += *buff++;
1552
1553         while (sum >> 16)
1554                 sum = (sum & 0xFFFF) + (sum >> 16);
1555
1556         if (~sum) {
1557                 return 0;
1558         } else {
1559                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1560                 return -1;
1561         }
1562 }
1563
1564 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1565 {
1566         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1567         u32 addr, count, prev_ver, curr_ver;
1568         u8 *p_buff;
1569
1570         if (ahw->reset.buff != NULL) {
1571                 prev_ver = p_dev->fw_version;
1572                 curr_ver = qlcnic_83xx_get_fw_version(p_dev);
1573                 if (curr_ver > prev_ver)
1574                         kfree(ahw->reset.buff);
1575                 else
1576                         return 0;
1577         }
1578
1579         ahw->reset.seq_error = 0;
1580         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1581         if (p_dev->ahw->reset.buff == NULL)
1582                 return -ENOMEM;
1583
1584         p_buff = p_dev->ahw->reset.buff;
1585         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1586         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1587
1588         /* Copy template header from flash */
1589         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1590                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1591                 return -EIO;
1592         }
1593         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1594         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1595         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1596         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1597
1598         /* Copy rest of the template */
1599         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1600                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1601                 return -EIO;
1602         }
1603
1604         if (qlcnic_83xx_reset_template_checksum(p_dev))
1605                 return -EIO;
1606         /* Get Stop, Start and Init command offsets */
1607         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1608         ahw->reset.start_offset = ahw->reset.buff +
1609                                   ahw->reset.hdr->start_offset;
1610         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1611         return 0;
1612 }
1613
1614 /* Read Write HW register command */
1615 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1616                                            u32 raddr, u32 waddr)
1617 {
1618         int value;
1619
1620         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1621         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1622 }
1623
1624 /* Read Modify Write HW register command */
1625 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1626                                     u32 raddr, u32 waddr,
1627                                     struct qlc_83xx_rmw *p_rmw_hdr)
1628 {
1629         int value;
1630
1631         if (p_rmw_hdr->index_a)
1632                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1633         else
1634                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1635
1636         value &= p_rmw_hdr->mask;
1637         value <<= p_rmw_hdr->shl;
1638         value >>= p_rmw_hdr->shr;
1639         value |= p_rmw_hdr->or_value;
1640         value ^= p_rmw_hdr->xor_value;
1641         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1642 }
1643
1644 /* Write HW register command */
1645 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1646                                    struct qlc_83xx_entry_hdr *p_hdr)
1647 {
1648         int i;
1649         struct qlc_83xx_entry *entry;
1650
1651         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1652                                           sizeof(struct qlc_83xx_entry_hdr));
1653
1654         for (i = 0; i < p_hdr->count; i++, entry++) {
1655                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1656                                              entry->arg2);
1657                 if (p_hdr->delay)
1658                         udelay((u32)(p_hdr->delay));
1659         }
1660 }
1661
1662 /* Read and Write instruction */
1663 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1664                                         struct qlc_83xx_entry_hdr *p_hdr)
1665 {
1666         int i;
1667         struct qlc_83xx_entry *entry;
1668
1669         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1670                                           sizeof(struct qlc_83xx_entry_hdr));
1671
1672         for (i = 0; i < p_hdr->count; i++, entry++) {
1673                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1674                                                entry->arg2);
1675                 if (p_hdr->delay)
1676                         udelay((u32)(p_hdr->delay));
1677         }
1678 }
1679
1680 /* Poll HW register command */
1681 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1682                                   struct qlc_83xx_entry_hdr *p_hdr)
1683 {
1684         long delay;
1685         struct qlc_83xx_entry *entry;
1686         struct qlc_83xx_poll *poll;
1687         int i;
1688         unsigned long arg1, arg2;
1689
1690         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1691                                         sizeof(struct qlc_83xx_entry_hdr));
1692
1693         entry = (struct qlc_83xx_entry *)((char *)poll +
1694                                           sizeof(struct qlc_83xx_poll));
1695         delay = (long)p_hdr->delay;
1696
1697         if (!delay) {
1698                 for (i = 0; i < p_hdr->count; i++, entry++)
1699                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1700                                              delay, poll->mask,
1701                                              poll->status);
1702         } else {
1703                 for (i = 0; i < p_hdr->count; i++, entry++) {
1704                         arg1 = entry->arg1;
1705                         arg2 = entry->arg2;
1706                         if (delay) {
1707                                 if (qlcnic_83xx_poll_reg(p_dev,
1708                                                          arg1, delay,
1709                                                          poll->mask,
1710                                                          poll->status)){
1711                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1712                                                                     arg1);
1713                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1714                                                                     arg2);
1715                                 }
1716                         }
1717                 }
1718         }
1719 }
1720
1721 /* Poll and write HW register command */
1722 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1723                                         struct qlc_83xx_entry_hdr *p_hdr)
1724 {
1725         int i;
1726         long delay;
1727         struct qlc_83xx_quad_entry *entry;
1728         struct qlc_83xx_poll *poll;
1729
1730         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1731                                         sizeof(struct qlc_83xx_entry_hdr));
1732         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1733                                                sizeof(struct qlc_83xx_poll));
1734         delay = (long)p_hdr->delay;
1735
1736         for (i = 0; i < p_hdr->count; i++, entry++) {
1737                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1738                                              entry->dr_value);
1739                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1740                                              entry->ar_value);
1741                 if (delay)
1742                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1743                                              poll->mask, poll->status);
1744         }
1745 }
1746
1747 /* Read Modify Write register command */
1748 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1749                                           struct qlc_83xx_entry_hdr *p_hdr)
1750 {
1751         int i;
1752         struct qlc_83xx_entry *entry;
1753         struct qlc_83xx_rmw *rmw_hdr;
1754
1755         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1756                                           sizeof(struct qlc_83xx_entry_hdr));
1757
1758         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1759                                           sizeof(struct qlc_83xx_rmw));
1760
1761         for (i = 0; i < p_hdr->count; i++, entry++) {
1762                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1763                                         entry->arg2, rmw_hdr);
1764                 if (p_hdr->delay)
1765                         udelay((u32)(p_hdr->delay));
1766         }
1767 }
1768
1769 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1770 {
1771         if (p_hdr->delay)
1772                 mdelay((u32)((long)p_hdr->delay));
1773 }
1774
1775 /* Read and poll register command */
1776 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1777                                        struct qlc_83xx_entry_hdr *p_hdr)
1778 {
1779         long delay;
1780         int index, i, j;
1781         struct qlc_83xx_quad_entry *entry;
1782         struct qlc_83xx_poll *poll;
1783         unsigned long addr;
1784
1785         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1786                                         sizeof(struct qlc_83xx_entry_hdr));
1787
1788         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1789                                                sizeof(struct qlc_83xx_poll));
1790         delay = (long)p_hdr->delay;
1791
1792         for (i = 0; i < p_hdr->count; i++, entry++) {
1793                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1794                                              entry->ar_value);
1795                 if (delay) {
1796                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1797                                                   poll->mask, poll->status)){
1798                                 index = p_dev->ahw->reset.array_index;
1799                                 addr = entry->dr_addr;
1800                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1801                                 p_dev->ahw->reset.array[index++] = j;
1802
1803                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1804                                         p_dev->ahw->reset.array_index = 1;
1805                         }
1806                 }
1807         }
1808 }
1809
1810 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1811 {
1812         p_dev->ahw->reset.seq_end = 1;
1813 }
1814
1815 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1816 {
1817         p_dev->ahw->reset.template_end = 1;
1818         if (p_dev->ahw->reset.seq_error == 0)
1819                 dev_err(&p_dev->pdev->dev,
1820                         "HW restart process completed successfully.\n");
1821         else
1822                 dev_err(&p_dev->pdev->dev,
1823                         "HW restart completed with timeout errors.\n");
1824 }
1825
1826 /**
1827 * qlcnic_83xx_exec_template_cmd
1828 *
1829 * @p_dev: adapter structure
1830 * @p_buff: Poiter to instruction template
1831 *
1832 * Template provides instructions to stop, restart and initalize firmware.
1833 * These instructions are abstracted as a series of read, write and
1834 * poll operations on hardware registers. Register information and operation
1835 * specifics are not exposed to the driver. Driver reads the template from
1836 * flash and executes the instructions located at pre-defined offsets.
1837 *
1838 * Returns: None
1839 * */
1840 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1841                                           char *p_buff)
1842 {
1843         int index, entries;
1844         struct qlc_83xx_entry_hdr *p_hdr;
1845         char *entry = p_buff;
1846
1847         p_dev->ahw->reset.seq_end = 0;
1848         p_dev->ahw->reset.template_end = 0;
1849         entries = p_dev->ahw->reset.hdr->entries;
1850         index = p_dev->ahw->reset.seq_index;
1851
1852         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1853                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1854
1855                 switch (p_hdr->cmd) {
1856                 case QLC_83XX_OPCODE_NOP:
1857                         break;
1858                 case QLC_83XX_OPCODE_WRITE_LIST:
1859                         qlcnic_83xx_write_list(p_dev, p_hdr);
1860                         break;
1861                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1862                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1863                         break;
1864                 case QLC_83XX_OPCODE_POLL_LIST:
1865                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1866                         break;
1867                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1868                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1869                         break;
1870                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1871                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1872                         break;
1873                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1874                         qlcnic_83xx_pause(p_hdr);
1875                         break;
1876                 case QLC_83XX_OPCODE_SEQ_END:
1877                         qlcnic_83xx_seq_end(p_dev);
1878                         break;
1879                 case QLC_83XX_OPCODE_TMPL_END:
1880                         qlcnic_83xx_template_end(p_dev);
1881                         break;
1882                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1883                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1884                         break;
1885                 default:
1886                         dev_err(&p_dev->pdev->dev,
1887                                 "%s: Unknown opcode 0x%04x in template %d\n",
1888                                 __func__, p_hdr->cmd, index);
1889                         break;
1890                 }
1891                 entry += p_hdr->size;
1892         }
1893         p_dev->ahw->reset.seq_index = index;
1894 }
1895
1896 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1897 {
1898         p_dev->ahw->reset.seq_index = 0;
1899
1900         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1901         if (p_dev->ahw->reset.seq_end != 1)
1902                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1903 }
1904
1905 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1906 {
1907         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1908         if (p_dev->ahw->reset.template_end != 1)
1909                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1910 }
1911
1912 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1913 {
1914         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1915         if (p_dev->ahw->reset.seq_end != 1)
1916                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1917 }
1918
1919 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1920 {
1921         int err = -EIO;
1922
1923         if (request_firmware(&adapter->ahw->fw_info.fw,
1924                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1925                 dev_err(&adapter->pdev->dev,
1926                         "No file FW image, loading flash FW image.\n");
1927                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1928                                     QLC_83XX_BOOT_FROM_FLASH);
1929         } else {
1930                 if (qlcnic_83xx_copy_fw_file(adapter))
1931                         return err;
1932                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1933                                     QLC_83XX_BOOT_FROM_FILE);
1934         }
1935
1936         return 0;
1937 }
1938
1939 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1940 {
1941         u32 val;
1942         int err = -EIO;
1943
1944         qlcnic_83xx_stop_hw(adapter);
1945
1946         /* Collect FW register dump if required */
1947         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1948         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1949                 qlcnic_dump_fw(adapter);
1950         qlcnic_83xx_init_hw(adapter);
1951
1952         if (qlcnic_83xx_copy_bootloader(adapter))
1953                 return err;
1954         /* Boot either flash image or firmware image from host file system */
1955         if (qlcnic_load_fw_file) {
1956                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1957                         return err;
1958         } else {
1959                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1960                                     QLC_83XX_BOOT_FROM_FLASH);
1961         }
1962
1963         qlcnic_83xx_start_hw(adapter);
1964         if (qlcnic_83xx_check_hw_status(adapter))
1965                 return -EIO;
1966
1967         return 0;
1968 }
1969
1970 /**
1971 * qlcnic_83xx_config_default_opmode
1972 *
1973 * @adapter: adapter structure
1974 *
1975 * Configure default driver operating mode
1976 *
1977 * Returns: Error code or Success(0)
1978 * */
1979 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1980 {
1981         u32 op_mode;
1982         struct qlcnic_hardware_context *ahw = adapter->ahw;
1983
1984         qlcnic_get_func_no(adapter);
1985         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1986
1987         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1988                 op_mode = QLC_83XX_DEFAULT_OPMODE;
1989
1990         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1991                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1992                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1993         } else {
1994                 return -EIO;
1995         }
1996
1997         return 0;
1998 }
1999
2000 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
2001 {
2002         int err;
2003         struct qlcnic_info nic_info;
2004         struct qlcnic_hardware_context *ahw = adapter->ahw;
2005
2006         memset(&nic_info, 0, sizeof(struct qlcnic_info));
2007         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
2008         if (err)
2009                 return -EIO;
2010
2011         ahw->physical_port = (u8) nic_info.phys_port;
2012         ahw->switch_mode = nic_info.switch_mode;
2013         ahw->max_tx_ques = nic_info.max_tx_ques;
2014         ahw->max_rx_ques = nic_info.max_rx_ques;
2015         ahw->capabilities = nic_info.capabilities;
2016         ahw->max_mac_filters = nic_info.max_mac_filters;
2017         ahw->max_mtu = nic_info.max_mtu;
2018
2019         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
2020          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
2021          * exclusive. So in case of sriov capable device load driver in
2022          * default mode
2023          */
2024         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
2025                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2026                 return ahw->nic_mode;
2027         }
2028
2029         if (ahw->capabilities & BIT_23)
2030                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
2031         else
2032                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
2033
2034         return ahw->nic_mode;
2035 }
2036
2037 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
2038 {
2039         int ret;
2040
2041         ret = qlcnic_83xx_get_nic_configuration(adapter);
2042         if (ret == -EIO)
2043                 return -EIO;
2044
2045         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2046                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2047                         return -EIO;
2048         } else if (ret == QLC_83XX_DEFAULT_MODE) {
2049                 if (qlcnic_83xx_config_default_opmode(adapter))
2050                         return -EIO;
2051         }
2052
2053         return 0;
2054 }
2055
2056 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2057 {
2058         struct qlcnic_hardware_context *ahw = adapter->ahw;
2059
2060         if (ahw->port_type == QLCNIC_XGBE) {
2061                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2062                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2063                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2064                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2065
2066         } else if (ahw->port_type == QLCNIC_GBE) {
2067                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2068                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2069                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2070                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2071         }
2072         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2073         adapter->max_rds_rings = MAX_RDS_RINGS;
2074 }
2075
2076 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2077 {
2078         int err = -EIO;
2079
2080         qlcnic_83xx_get_minidump_template(adapter);
2081         if (qlcnic_83xx_get_port_info(adapter))
2082                 return err;
2083
2084         qlcnic_83xx_config_buff_descriptors(adapter);
2085         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2086         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2087
2088         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2089                  adapter->ahw->fw_hal_version);
2090
2091         return 0;
2092 }
2093
2094 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2095 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2096 {
2097         struct qlcnic_cmd_args cmd;
2098         u32 presence_mask, audit_mask;
2099         int status;
2100
2101         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2102         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2103
2104         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2105                 status = qlcnic_alloc_mbx_args(&cmd, adapter,
2106                                                QLCNIC_CMD_STOP_NIC_FUNC);
2107                 if (status)
2108                         return;
2109
2110                 cmd.req.arg[1] = BIT_31;
2111                 status = qlcnic_issue_cmd(adapter, &cmd);
2112                 if (status)
2113                         dev_err(&adapter->pdev->dev,
2114                                 "Failed to clean up the function resources\n");
2115                 qlcnic_free_mbx_args(&cmd);
2116         }
2117 }
2118
2119 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2120 {
2121         struct qlcnic_hardware_context *ahw = adapter->ahw;
2122         int err = 0;
2123
2124         ahw->msix_supported = !!qlcnic_use_msi_x;
2125         err = qlcnic_83xx_init_mailbox_work(adapter);
2126         if (err)
2127                 goto exit;
2128
2129         if (qlcnic_sriov_vf_check(adapter)) {
2130                 err = qlcnic_sriov_vf_init(adapter, pci_using_dac);
2131                 if (err)
2132                         goto detach_mbx;
2133                 else
2134                         return err;
2135         }
2136
2137         err = qlcnic_83xx_check_hw_status(adapter);
2138         if (err)
2139                 goto detach_mbx;
2140
2141         err = qlcnic_setup_intr(adapter, 0);
2142         if (err) {
2143                 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n");
2144                 goto disable_intr;
2145         }
2146
2147         err = qlcnic_83xx_setup_mbx_intr(adapter);
2148         if (err)
2149                 goto disable_mbx_intr;
2150
2151         qlcnic_83xx_clear_function_resources(adapter);
2152
2153         /* register for NIC IDC AEN Events */
2154         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2155
2156         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2157                 qlcnic_83xx_read_flash_mfg_id(adapter);
2158
2159         err = qlcnic_83xx_idc_init(adapter);
2160         if (err)
2161                 goto disable_mbx_intr;
2162
2163         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2164         err = qlcnic_83xx_configure_opmode(adapter);
2165         if (err)
2166                 goto disable_mbx_intr;
2167
2168         /* Perform operating mode specific initialization */
2169         err = adapter->nic_ops->init_driver(adapter);
2170         if (err)
2171                 goto disable_mbx_intr;
2172
2173         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2174
2175         /* Periodically monitor device status */
2176         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2177         return 0;
2178
2179 disable_mbx_intr:
2180         qlcnic_83xx_free_mbx_intr(adapter);
2181
2182 disable_intr:
2183         qlcnic_teardown_intr(adapter);
2184
2185 detach_mbx:
2186         qlcnic_83xx_detach_mailbox_work(adapter);
2187         qlcnic_83xx_free_mailbox(ahw->mailbox);
2188 exit:
2189         return err;
2190 }