drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492
 493         /* rtl8169_PHYstatus */
 494         TBI_Enable      = 0x80,
 495         TxFlowCtrl      = 0x40,
 496         RxFlowCtrl      = 0x20,
 497         _1000bpsF       = 0x10,
 498         _100bps         = 0x08,
 499         _10bps          = 0x04,
 500         LinkStatus      = 0x02,
 501         FullDup         = 0x01,
 502
 503         /* ResetCounterCommand */
 504         CounterReset    = 0x1,
 505
 506         /* DumpCounterCommand */
 507         CounterDump     = 0x8,
 508
 509         /* magic enable v2 */
 510         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 511 };
 512
 513 enum rtl_desc_bit {
 514         /* First doubleword. */
 515         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 516         RingEnd         = (1 << 30), /* End of descriptor ring */
 517         FirstFrag       = (1 << 29), /* First segment of a packet */
 518         LastFrag        = (1 << 28), /* Final segment of a packet */
 519 };
 520
 521 /* Generic case. */
 522 enum rtl_tx_desc_bit {
 523         /* First doubleword. */
 524         TD_LSO          = (1 << 27),            /* Large Send Offload */
 525 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 526
 527         /* Second doubleword. */
 528         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 529 };
 530
 531 /* 8169, 8168b and 810x except 8102e. */
 532 enum rtl_tx_desc_bit_0 {
 533         /* First doubleword. */
 534 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 535         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 536         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 537         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 538 };
 539
 540 /* 8102e, 8168c and beyond. */
 541 enum rtl_tx_desc_bit_1 {
 542         /* First doubleword. */
 543         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 544         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 545 #define GTTCPHO_SHIFT                   18
 546 #define GTTCPHO_MAX                     0x7fU
 547
 548         /* Second doubleword. */
 549 #define TCPHO_SHIFT                     18
 550 #define TCPHO_MAX                       0x3ffU
 551 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 552         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 553         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 554         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 555         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 556 };
 557
 558 enum rtl_rx_desc_bit {
 559         /* Rx private */
 560         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 561         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 562
 563 #define RxProtoUDP      (PID1)
 564 #define RxProtoTCP      (PID0)
 565 #define RxProtoIP       (PID1 | PID0)
 566 #define RxProtoMask     RxProtoIP
 567
 568         IPFail          = (1 << 16), /* IP checksum failed */
 569         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 570         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 571         RxVlanTag       = (1 << 16), /* VLAN tag available */
 572 };
 573
 574 #define RsvdMask        0x3fffc000
 575 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 576
 577 struct TxDesc {
 578         __le32 opts1;
 579         __le32 opts2;
 580         __le64 addr;
 581 };
 582
 583 struct RxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct ring_info {
 590         struct sk_buff  *skb;
 591         u32             len;
 592 };
 593
 594 struct rtl8169_counters {
 595         __le64  tx_packets;
 596         __le64  rx_packets;
 597         __le64  tx_errors;
 598         __le32  rx_errors;
 599         __le16  rx_missed;
 600         __le16  align_errors;
 601         __le32  tx_one_collision;
 602         __le32  tx_multi_collision;
 603         __le64  rx_unicast;
 604         __le64  rx_broadcast;
 605         __le32  rx_multicast;
 606         __le16  tx_aborted;
 607         __le16  tx_underun;
 608 };
 609
 610 struct rtl8169_tc_offsets {
 611         bool    inited;
 612         __le64  tx_errors;
 613         __le32  tx_multi_collision;
 614         __le16  tx_aborted;
 615 };
 616
 617 enum rtl_flag {
 618         RTL_FLAG_TASK_ENABLED = 0,
 619         RTL_FLAG_TASK_RESET_PENDING,
 620         RTL_FLAG_MAX
 621 };
 622
 623 struct rtl8169_stats {
 624         u64                     packets;
 625         u64                     bytes;
 626         struct u64_stats_sync   syncp;
 627 };
 628
 629 struct rtl8169_private;
 630 typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val);
 631 typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg);
 632
 633 struct rtl8169_private {
 634         void __iomem *mmio_addr;        /* memory map physical address */
 635         struct pci_dev *pci_dev;
 636         struct net_device *dev;
 637         struct phy_device *phydev;
 638         struct napi_struct napi;
 639         u32 msg_enable;
 640         enum mac_version mac_version;
 641         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 642         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 643         u32 dirty_tx;
 644         struct rtl8169_stats rx_stats;
 645         struct rtl8169_stats tx_stats;
 646         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 647         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 648         dma_addr_t TxPhyAddr;
 649         dma_addr_t RxPhyAddr;
 650         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 651         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 652         u16 cp_cmd;
 653
 654         u16 irq_mask;
 655         const struct rtl_coalesce_info *coalesce_info;
 656         struct clk *clk;
 657
 658         void (*hw_start)(struct rtl8169_private *tp);
 659
 660         struct {
 661                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 662                 struct mutex mutex;
 663                 struct work_struct work;
 664         } wk;
 665
 666         unsigned irq_enabled:1;
 667         unsigned supports_gmii:1;
 668         dma_addr_t counters_phys_addr;
 669         struct rtl8169_counters *counters;
 670         struct rtl8169_tc_offsets tc_offset;
 671         u32 saved_wolopts;
 672
 673         const char *fw_name;
 674         struct rtl_fw {
 675                 rtl_fw_write_t phy_write;
 676                 rtl_fw_read_t phy_read;
 677                 rtl_fw_write_t mac_mcu_write;
 678                 rtl_fw_read_t mac_mcu_read;
 679                 const struct firmware *fw;
 680                 const char *fw_name;
 681                 struct device *dev;
 682
 683 #define RTL_VER_SIZE            32
 684
 685                 char version[RTL_VER_SIZE];
 686
 687                 struct rtl_fw_phy_action {
 688                         __le32 *code;
 689                         size_t size;
 690                 } phy_action;
 691         } *rtl_fw;
 692
 693         u32 ocp_base;
 694 };
 695
 696 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 697
 698 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 699 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 700 module_param_named(debug, debug.msg_enable, int, 0);
 701 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 702 MODULE_SOFTDEP("pre: realtek");
 703 MODULE_LICENSE("GPL");
 704 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 705 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 706 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 707 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 708 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 709 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 710 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 712 MODULE_FIRMWARE(FIRMWARE_8402_1);
 713 MODULE_FIRMWARE(FIRMWARE_8411_1);
 714 MODULE_FIRMWARE(FIRMWARE_8411_2);
 715 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 716 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 717 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 718 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 719 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 720 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 721 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 722 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 723
 724 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 725 {
 726         return &tp->pci_dev->dev;
 727 }
 728
 729 static void rtl_lock_work(struct rtl8169_private *tp)
 730 {
 731         mutex_lock(&tp->wk.mutex);
 732 }
 733
 734 static void rtl_unlock_work(struct rtl8169_private *tp)
 735 {
 736         mutex_unlock(&tp->wk.mutex);
 737 }
 738
 739 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 740 {
 741         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 742 }
 743
 744 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 745 {
 746         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 747 }
 748
 749 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 750 {
 751         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 752                                            PCI_EXP_DEVCTL_READRQ, force);
 753 }
 754
 755 struct rtl_cond {
 756         bool (*check)(struct rtl8169_private *);
 757         const char *msg;
 758 };
 759
 760 static void rtl_udelay(unsigned int d)
 761 {
 762         udelay(d);
 763 }
 764
 765 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 766                           void (*delay)(unsigned int), unsigned int d, int n,
 767                           bool high)
 768 {
 769         int i;
 770
 771         for (i = 0; i < n; i++) {
 772                 if (c->check(tp) == high)
 773                         return true;
 774                 delay(d);
 775         }
 776         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 777                   c->msg, !high, n, d);
 778         return false;
 779 }
 780
 781 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 782                                       const struct rtl_cond *c,
 783                                       unsigned int d, int n)
 784 {
 785         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 786 }
 787
 788 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 789                                      const struct rtl_cond *c,
 790                                      unsigned int d, int n)
 791 {
 792         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 793 }
 794
 795 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 796                                       const struct rtl_cond *c,
 797                                       unsigned int d, int n)
 798 {
 799         return rtl_loop_wait(tp, c, msleep, d, n, true);
 800 }
 801
 802 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 803                                      const struct rtl_cond *c,
 804                                      unsigned int d, int n)
 805 {
 806         return rtl_loop_wait(tp, c, msleep, d, n, false);
 807 }
 808
 809 #define DECLARE_RTL_COND(name)                          \
 810 static bool name ## _check(struct rtl8169_private *);   \
 811                                                         \
 812 static const struct rtl_cond name = {                   \
 813         .check  = name ## _check,                       \
 814         .msg    = #name                                 \
 815 };                                                      \
 816                                                         \
 817 static bool name ## _check(struct rtl8169_private *tp)
 818
 819 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 820 {
 821         if (reg & 0xffff0001) {
 822                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 823                 return true;
 824         }
 825         return false;
 826 }
 827
 828 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 829 {
 830         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 831 }
 832
 833 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 834 {
 835         if (rtl_ocp_reg_failure(tp, reg))
 836                 return;
 837
 838         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 839
 840         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 841 }
 842
 843 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 844 {
 845         if (rtl_ocp_reg_failure(tp, reg))
 846                 return 0;
 847
 848         RTL_W32(tp, GPHY_OCP, reg << 15);
 849
 850         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 851                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 852 }
 853
 854 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 855 {
 856         if (rtl_ocp_reg_failure(tp, reg))
 857                 return;
 858
 859         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 860 }
 861
 862 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 863 {
 864         if (rtl_ocp_reg_failure(tp, reg))
 865                 return 0;
 866
 867         RTL_W32(tp, OCPDR, reg << 15);
 868
 869         return RTL_R32(tp, OCPDR);
 870 }
 871
 872 #define OCP_STD_PHY_BASE        0xa400
 873
 874 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 875 {
 876         if (reg == 0x1f) {
 877                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 878                 return;
 879         }
 880
 881         if (tp->ocp_base != OCP_STD_PHY_BASE)
 882                 reg -= 0x10;
 883
 884         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 885 }
 886
 887 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 888 {
 889         if (tp->ocp_base != OCP_STD_PHY_BASE)
 890                 reg -= 0x10;
 891
 892         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 893 }
 894
 895 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 896 {
 897         if (reg == 0x1f) {
 898                 tp->ocp_base = value << 4;
 899                 return;
 900         }
 901
 902         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 903 }
 904
 905 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 906 {
 907         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 908 }
 909
 910 DECLARE_RTL_COND(rtl_phyar_cond)
 911 {
 912         return RTL_R32(tp, PHYAR) & 0x80000000;
 913 }
 914
 915 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 916 {
 917         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 918
 919         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 920         /*
 921          * According to hardware specs a 20us delay is required after write
 922          * complete indication, but before sending next command.
 923          */
 924         udelay(20);
 925 }
 926
 927 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 928 {
 929         int value;
 930
 931         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 932
 933         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 934                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 935
 936         /*
 937          * According to hardware specs a 20us delay is required after read
 938          * complete indication, but before sending next command.
 939          */
 940         udelay(20);
 941
 942         return value;
 943 }
 944
 945 DECLARE_RTL_COND(rtl_ocpar_cond)
 946 {
 947         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 948 }
 949
 950 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 951 {
 952         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 953         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 954         RTL_W32(tp, EPHY_RXER_NUM, 0);
 955
 956         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 957 }
 958
 959 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 960 {
 961         r8168dp_1_mdio_access(tp, reg,
 962                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 963 }
 964
 965 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 966 {
 967         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 968
 969         mdelay(1);
 970         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 971         RTL_W32(tp, EPHY_RXER_NUM, 0);
 972
 973         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 974                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 975 }
 976
 977 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 978
 979 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 980 {
 981         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 982 }
 983
 984 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 985 {
 986         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 987 }
 988
 989 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 990 {
 991         r8168dp_2_mdio_start(tp);
 992
 993         r8169_mdio_write(tp, reg, value);
 994
 995         r8168dp_2_mdio_stop(tp);
 996 }
 997
 998 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 999 {
1000         int value;
1001
1002         r8168dp_2_mdio_start(tp);
1003
1004         value = r8169_mdio_read(tp, reg);
1005
1006         r8168dp_2_mdio_stop(tp);
1007
1008         return value;
1009 }
1010
1011 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1012 {
1013         switch (tp->mac_version) {
1014         case RTL_GIGA_MAC_VER_27:
1015                 r8168dp_1_mdio_write(tp, location, val);
1016                 break;
1017         case RTL_GIGA_MAC_VER_28:
1018         case RTL_GIGA_MAC_VER_31:
1019                 r8168dp_2_mdio_write(tp, location, val);
1020                 break;
1021         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1022                 r8168g_mdio_write(tp, location, val);
1023                 break;
1024         default:
1025                 r8169_mdio_write(tp, location, val);
1026                 break;
1027         }
1028 }
1029
1030 static int rtl_readphy(struct rtl8169_private *tp, int location)
1031 {
1032         switch (tp->mac_version) {
1033         case RTL_GIGA_MAC_VER_27:
1034                 return r8168dp_1_mdio_read(tp, location);
1035         case RTL_GIGA_MAC_VER_28:
1036         case RTL_GIGA_MAC_VER_31:
1037                 return r8168dp_2_mdio_read(tp, location);
1038         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1039                 return r8168g_mdio_read(tp, location);
1040         default:
1041                 return r8169_mdio_read(tp, location);
1042         }
1043 }
1044
1045 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1046 {
1047         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1048 }
1049
1050 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1051 {
1052         int val;
1053
1054         val = rtl_readphy(tp, reg_addr);
1055         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1056 }
1057
1058 DECLARE_RTL_COND(rtl_ephyar_cond)
1059 {
1060         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1061 }
1062
1063 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1064 {
1065         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1066                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1067
1068         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1069
1070         udelay(10);
1071 }
1072
1073 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1074 {
1075         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1076
1077         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1078                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1079 }
1080
1081 DECLARE_RTL_COND(rtl_eriar_cond)
1082 {
1083         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1084 }
1085
1086 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1087                            u32 val, int type)
1088 {
1089         BUG_ON((addr & 3) || (mask == 0));
1090         RTL_W32(tp, ERIDR, val);
1091         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1092
1093         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1094 }
1095
1096 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1097                           u32 val)
1098 {
1099         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1100 }
1101
1102 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1103 {
1104         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1105
1106         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1107                 RTL_R32(tp, ERIDR) : ~0;
1108 }
1109
1110 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1111 {
1112         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1113 }
1114
1115 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1116                          u32 m)
1117 {
1118         u32 val;
1119
1120         val = rtl_eri_read(tp, addr);
1121         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1122 }
1123
1124 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1125                              u32 p)
1126 {
1127         rtl_w0w1_eri(tp, addr, mask, p, 0);
1128 }
1129
1130 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1131                                u32 m)
1132 {
1133         rtl_w0w1_eri(tp, addr, mask, 0, m);
1134 }
1135
1136 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1137 {
1138         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1139         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1140                 RTL_R32(tp, OCPDR) : ~0;
1141 }
1142
1143 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1144 {
1145         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1146 }
1147
1148 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1149                               u32 data)
1150 {
1151         RTL_W32(tp, OCPDR, data);
1152         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1153         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1154 }
1155
1156 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1157                               u32 data)
1158 {
1159         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1160                        data, ERIAR_OOB);
1161 }
1162
1163 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1164 {
1165         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1166
1167         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1168 }
1169
1170 #define OOB_CMD_RESET           0x00
1171 #define OOB_CMD_DRIVER_START    0x05
1172 #define OOB_CMD_DRIVER_STOP     0x06
1173
1174 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1175 {
1176         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1177 }
1178
1179 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1180 {
1181         u16 reg;
1182
1183         reg = rtl8168_get_ocp_reg(tp);
1184
1185         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1186 }
1187
1188 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1189 {
1190         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1191 }
1192
1193 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1194 {
1195         return RTL_R8(tp, IBISR0) & 0x20;
1196 }
1197
1198 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1199 {
1200         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1201         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1202         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1203         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1204 }
1205
1206 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1207 {
1208         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1209         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1210 }
1211
1212 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1213 {
1214         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1215         r8168ep_ocp_write(tp, 0x01, 0x30,
1216                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1217         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1218 }
1219
1220 static void rtl8168_driver_start(struct rtl8169_private *tp)
1221 {
1222         switch (tp->mac_version) {
1223         case RTL_GIGA_MAC_VER_27:
1224         case RTL_GIGA_MAC_VER_28:
1225         case RTL_GIGA_MAC_VER_31:
1226                 rtl8168dp_driver_start(tp);
1227                 break;
1228         case RTL_GIGA_MAC_VER_49:
1229         case RTL_GIGA_MAC_VER_50:
1230         case RTL_GIGA_MAC_VER_51:
1231                 rtl8168ep_driver_start(tp);
1232                 break;
1233         default:
1234                 BUG();
1235                 break;
1236         }
1237 }
1238
1239 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1240 {
1241         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1242         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1243 }
1244
1245 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1246 {
1247         rtl8168ep_stop_cmac(tp);
1248         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1249         r8168ep_ocp_write(tp, 0x01, 0x30,
1250                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1251         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1252 }
1253
1254 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1255 {
1256         switch (tp->mac_version) {
1257         case RTL_GIGA_MAC_VER_27:
1258         case RTL_GIGA_MAC_VER_28:
1259         case RTL_GIGA_MAC_VER_31:
1260                 rtl8168dp_driver_stop(tp);
1261                 break;
1262         case RTL_GIGA_MAC_VER_49:
1263         case RTL_GIGA_MAC_VER_50:
1264         case RTL_GIGA_MAC_VER_51:
1265                 rtl8168ep_driver_stop(tp);
1266                 break;
1267         default:
1268                 BUG();
1269                 break;
1270         }
1271 }
1272
1273 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1274 {
1275         u16 reg = rtl8168_get_ocp_reg(tp);
1276
1277         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1278 }
1279
1280 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1281 {
1282         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1283 }
1284
1285 static bool r8168_check_dash(struct rtl8169_private *tp)
1286 {
1287         switch (tp->mac_version) {
1288         case RTL_GIGA_MAC_VER_27:
1289         case RTL_GIGA_MAC_VER_28:
1290         case RTL_GIGA_MAC_VER_31:
1291                 return r8168dp_check_dash(tp);
1292         case RTL_GIGA_MAC_VER_49:
1293         case RTL_GIGA_MAC_VER_50:
1294         case RTL_GIGA_MAC_VER_51:
1295                 return r8168ep_check_dash(tp);
1296         default:
1297                 return false;
1298         }
1299 }
1300
1301 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1302 {
1303         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1304         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1305 }
1306
1307 DECLARE_RTL_COND(rtl_efusear_cond)
1308 {
1309         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1310 }
1311
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1313 {
1314         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1315
1316         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1318 }
1319
1320 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1321 {
1322         RTL_W16(tp, IntrStatus, bits);
1323 }
1324
1325 static void rtl_irq_disable(struct rtl8169_private *tp)
1326 {
1327         RTL_W16(tp, IntrMask, 0);
1328         tp->irq_enabled = 0;
1329 }
1330
1331 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1332 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1333 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1334
1335 static void rtl_irq_enable(struct rtl8169_private *tp)
1336 {
1337         tp->irq_enabled = 1;
1338         RTL_W16(tp, IntrMask, tp->irq_mask);
1339 }
1340
1341 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1342 {
1343         rtl_irq_disable(tp);
1344         rtl_ack_events(tp, 0xffff);
1345         /* PCI commit */
1346         RTL_R8(tp, ChipCmd);
1347 }
1348
1349 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1350 {
1351         struct net_device *dev = tp->dev;
1352         struct phy_device *phydev = tp->phydev;
1353
1354         if (!netif_running(dev))
1355                 return;
1356
1357         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1358             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1359                 if (phydev->speed == SPEED_1000) {
1360                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1361                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1362                 } else if (phydev->speed == SPEED_100) {
1363                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1364                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1365                 } else {
1366                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1367                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1368                 }
1369                 rtl_reset_packet_filter(tp);
1370         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1371                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1372                 if (phydev->speed == SPEED_1000) {
1373                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1374                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1375                 } else {
1376                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1377                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1378                 }
1379         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1380                 if (phydev->speed == SPEED_10) {
1381                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1382                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1383                 } else {
1384                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1385                 }
1386         }
1387 }
1388
1389 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1390
1391 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1392 {
1393         struct rtl8169_private *tp = netdev_priv(dev);
1394
1395         rtl_lock_work(tp);
1396         wol->supported = WAKE_ANY;
1397         wol->wolopts = tp->saved_wolopts;
1398         rtl_unlock_work(tp);
1399 }
1400
1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1402 {
1403         unsigned int i, tmp;
1404         static const struct {
1405                 u32 opt;
1406                 u16 reg;
1407                 u8  mask;
1408         } cfg[] = {
1409                 { WAKE_PHY,   Config3, LinkUp },
1410                 { WAKE_UCAST, Config5, UWF },
1411                 { WAKE_BCAST, Config5, BWF },
1412                 { WAKE_MCAST, Config5, MWF },
1413                 { WAKE_ANY,   Config5, LanWake },
1414                 { WAKE_MAGIC, Config3, MagicPacket }
1415         };
1416         u8 options;
1417
1418         rtl_unlock_config_regs(tp);
1419
1420         switch (tp->mac_version) {
1421         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1422         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1423                 tmp = ARRAY_SIZE(cfg) - 1;
1424                 if (wolopts & WAKE_MAGIC)
1425                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1426                                          MagicPacket_v2);
1427                 else
1428                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1429                                            MagicPacket_v2);
1430                 break;
1431         default:
1432                 tmp = ARRAY_SIZE(cfg);
1433                 break;
1434         }
1435
1436         for (i = 0; i < tmp; i++) {
1437                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1438                 if (wolopts & cfg[i].opt)
1439                         options |= cfg[i].mask;
1440                 RTL_W8(tp, cfg[i].reg, options);
1441         }
1442
1443         switch (tp->mac_version) {
1444         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1445                 options = RTL_R8(tp, Config1) & ~PMEnable;
1446                 if (wolopts)
1447                         options |= PMEnable;
1448                 RTL_W8(tp, Config1, options);
1449                 break;
1450         default:
1451                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1452                 if (wolopts)
1453                         options |= PME_SIGNAL;
1454                 RTL_W8(tp, Config2, options);
1455                 break;
1456         }
1457
1458         rtl_lock_config_regs(tp);
1459
1460         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1461 }
1462
1463 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1464 {
1465         struct rtl8169_private *tp = netdev_priv(dev);
1466         struct device *d = tp_to_dev(tp);
1467
1468         if (wol->wolopts & ~WAKE_ANY)
1469                 return -EINVAL;
1470
1471         pm_runtime_get_noresume(d);
1472
1473         rtl_lock_work(tp);
1474
1475         tp->saved_wolopts = wol->wolopts;
1476
1477         if (pm_runtime_active(d))
1478                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1479
1480         rtl_unlock_work(tp);
1481
1482         pm_runtime_put_noidle(d);
1483
1484         return 0;
1485 }
1486
1487 static void rtl8169_get_drvinfo(struct net_device *dev,
1488                                 struct ethtool_drvinfo *info)
1489 {
1490         struct rtl8169_private *tp = netdev_priv(dev);
1491         struct rtl_fw *rtl_fw = tp->rtl_fw;
1492
1493         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1494         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1495         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1496         if (rtl_fw)
1497                 strlcpy(info->fw_version, rtl_fw->version,
1498                         sizeof(info->fw_version));
1499 }
1500
1501 static int rtl8169_get_regs_len(struct net_device *dev)
1502 {
1503         return R8169_REGS_SIZE;
1504 }
1505
1506 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1507         netdev_features_t features)
1508 {
1509         struct rtl8169_private *tp = netdev_priv(dev);
1510
1511         if (dev->mtu > TD_MSS_MAX)
1512                 features &= ~NETIF_F_ALL_TSO;
1513
1514         if (dev->mtu > JUMBO_1K &&
1515             tp->mac_version > RTL_GIGA_MAC_VER_06)
1516                 features &= ~NETIF_F_IP_CSUM;
1517
1518         return features;
1519 }
1520
1521 static int rtl8169_set_features(struct net_device *dev,
1522                                 netdev_features_t features)
1523 {
1524         struct rtl8169_private *tp = netdev_priv(dev);
1525         u32 rx_config;
1526
1527         rtl_lock_work(tp);
1528
1529         rx_config = RTL_R32(tp, RxConfig);
1530         if (features & NETIF_F_RXALL)
1531                 rx_config |= (AcceptErr | AcceptRunt);
1532         else
1533                 rx_config &= ~(AcceptErr | AcceptRunt);
1534
1535         RTL_W32(tp, RxConfig, rx_config);
1536
1537         if (features & NETIF_F_RXCSUM)
1538                 tp->cp_cmd |= RxChkSum;
1539         else
1540                 tp->cp_cmd &= ~RxChkSum;
1541
1542         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1543                 tp->cp_cmd |= RxVlan;
1544         else
1545                 tp->cp_cmd &= ~RxVlan;
1546
1547         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1548         RTL_R16(tp, CPlusCmd);
1549
1550         rtl_unlock_work(tp);
1551
1552         return 0;
1553 }
1554
1555 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1556 {
1557         return (skb_vlan_tag_present(skb)) ?
1558                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1559 }
1560
1561 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1562 {
1563         u32 opts2 = le32_to_cpu(desc->opts2);
1564
1565         if (opts2 & RxVlanTag)
1566                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1567 }
1568
1569 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1570                              void *p)
1571 {
1572         struct rtl8169_private *tp = netdev_priv(dev);
1573         u32 __iomem *data = tp->mmio_addr;
1574         u32 *dw = p;
1575         int i;
1576
1577         rtl_lock_work(tp);
1578         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1579                 memcpy_fromio(dw++, data++, 4);
1580         rtl_unlock_work(tp);
1581 }
1582
1583 static u32 rtl8169_get_msglevel(struct net_device *dev)
1584 {
1585         struct rtl8169_private *tp = netdev_priv(dev);
1586
1587         return tp->msg_enable;
1588 }
1589
1590 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1591 {
1592         struct rtl8169_private *tp = netdev_priv(dev);
1593
1594         tp->msg_enable = value;
1595 }
1596
1597 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1598         "tx_packets",
1599         "rx_packets",
1600         "tx_errors",
1601         "rx_errors",
1602         "rx_missed",
1603         "align_errors",
1604         "tx_single_collisions",
1605         "tx_multi_collisions",
1606         "unicast",
1607         "broadcast",
1608         "multicast",
1609         "tx_aborted",
1610         "tx_underrun",
1611 };
1612
1613 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1614 {
1615         switch (sset) {
1616         case ETH_SS_STATS:
1617                 return ARRAY_SIZE(rtl8169_gstrings);
1618         default:
1619                 return -EOPNOTSUPP;
1620         }
1621 }
1622
1623 DECLARE_RTL_COND(rtl_counters_cond)
1624 {
1625         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1626 }
1627
1628 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1629 {
1630         dma_addr_t paddr = tp->counters_phys_addr;
1631         u32 cmd;
1632
1633         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1634         RTL_R32(tp, CounterAddrHigh);
1635         cmd = (u64)paddr & DMA_BIT_MASK(32);
1636         RTL_W32(tp, CounterAddrLow, cmd);
1637         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1638
1639         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1640 }
1641
1642 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1643 {
1644         /*
1645          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1646          * tally counters.
1647          */
1648         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1649                 return true;
1650
1651         return rtl8169_do_counters(tp, CounterReset);
1652 }
1653
1654 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1655 {
1656         u8 val = RTL_R8(tp, ChipCmd);
1657
1658         /*
1659          * Some chips are unable to dump tally counters when the receiver
1660          * is disabled. If 0xff chip may be in a PCI power-save state.
1661          */
1662         if (!(val & CmdRxEnb) || val == 0xff)
1663                 return true;
1664
1665         return rtl8169_do_counters(tp, CounterDump);
1666 }
1667
1668 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1669 {
1670         struct rtl8169_counters *counters = tp->counters;
1671         bool ret = false;
1672
1673         /*
1674          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1675          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1676          * reset by a power cycle, while the counter values collected by the
1677          * driver are reset at every driver unload/load cycle.
1678          *
1679          * To make sure the HW values returned by @get_stats64 match the SW
1680          * values, we collect the initial values at first open(*) and use them
1681          * as offsets to normalize the values returned by @get_stats64.
1682          *
1683          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1684          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1685          * set at open time by rtl_hw_start.
1686          */
1687
1688         if (tp->tc_offset.inited)
1689                 return true;
1690
1691         /* If both, reset and update fail, propagate to caller. */
1692         if (rtl8169_reset_counters(tp))
1693                 ret = true;
1694
1695         if (rtl8169_update_counters(tp))
1696                 ret = true;
1697
1698         tp->tc_offset.tx_errors = counters->tx_errors;
1699         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1700         tp->tc_offset.tx_aborted = counters->tx_aborted;
1701         tp->tc_offset.inited = true;
1702
1703         return ret;
1704 }
1705
1706 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1707                                       struct ethtool_stats *stats, u64 *data)
1708 {
1709         struct rtl8169_private *tp = netdev_priv(dev);
1710         struct device *d = tp_to_dev(tp);
1711         struct rtl8169_counters *counters = tp->counters;
1712
1713         ASSERT_RTNL();
1714
1715         pm_runtime_get_noresume(d);
1716
1717         if (pm_runtime_active(d))
1718                 rtl8169_update_counters(tp);
1719
1720         pm_runtime_put_noidle(d);
1721
1722         data[0] = le64_to_cpu(counters->tx_packets);
1723         data[1] = le64_to_cpu(counters->rx_packets);
1724         data[2] = le64_to_cpu(counters->tx_errors);
1725         data[3] = le32_to_cpu(counters->rx_errors);
1726         data[4] = le16_to_cpu(counters->rx_missed);
1727         data[5] = le16_to_cpu(counters->align_errors);
1728         data[6] = le32_to_cpu(counters->tx_one_collision);
1729         data[7] = le32_to_cpu(counters->tx_multi_collision);
1730         data[8] = le64_to_cpu(counters->rx_unicast);
1731         data[9] = le64_to_cpu(counters->rx_broadcast);
1732         data[10] = le32_to_cpu(counters->rx_multicast);
1733         data[11] = le16_to_cpu(counters->tx_aborted);
1734         data[12] = le16_to_cpu(counters->tx_underun);
1735 }
1736
1737 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1738 {
1739         switch(stringset) {
1740         case ETH_SS_STATS:
1741                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1742                 break;
1743         }
1744 }
1745
1746 /*
1747  * Interrupt coalescing
1748  *
1749  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1750  * >     8169, 8168 and 810x line of chipsets
1751  *
1752  * 8169, 8168, and 8136(810x) serial chipsets support it.
1753  *
1754  * > 2 - the Tx timer unit at gigabit speed
1755  *
1756  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1757  * (0xe0) bit 1 and bit 0.
1758  *
1759  * For 8169
1760  * bit[1:0] \ speed        1000M           100M            10M
1761  * 0 0                     320ns           2.56us          40.96us
1762  * 0 1                     2.56us          20.48us         327.7us
1763  * 1 0                     5.12us          40.96us         655.4us
1764  * 1 1                     10.24us         81.92us         1.31ms
1765  *
1766  * For the other
1767  * bit[1:0] \ speed        1000M           100M            10M
1768  * 0 0                     5us             2.56us          40.96us
1769  * 0 1                     40us            20.48us         327.7us
1770  * 1 0                     80us            40.96us         655.4us
1771  * 1 1                     160us           81.92us         1.31ms
1772  */
1773
1774 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1775 struct rtl_coalesce_scale {
1776         /* Rx / Tx */
1777         u32 nsecs[2];
1778 };
1779
1780 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1781 struct rtl_coalesce_info {
1782         u32 speed;
1783         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1784 };
1785
1786 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1787 #define rxtx_x1822(r, t) {              \
1788         {{(r),          (t)}},          \
1789         {{(r)*8,        (t)*8}},        \
1790         {{(r)*8*2,      (t)*8*2}},      \
1791         {{(r)*8*2*2,    (t)*8*2*2}},    \
1792 }
1793 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1794         /* speed        delays:     rx00   tx00 */
1795         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1796         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1797         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1798         { 0 },
1799 };
1800
1801 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1802         /* speed        delays:     rx00   tx00 */
1803         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1804         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1805         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1806         { 0 },
1807 };
1808 #undef rxtx_x1822
1809
1810 /* get rx/tx scale vector corresponding to current speed */
1811 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1812 {
1813         struct rtl8169_private *tp = netdev_priv(dev);
1814         struct ethtool_link_ksettings ecmd;
1815         const struct rtl_coalesce_info *ci;
1816         int rc;
1817
1818         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1819         if (rc < 0)
1820                 return ERR_PTR(rc);
1821
1822         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1823                 if (ecmd.base.speed == ci->speed) {
1824                         return ci;
1825                 }
1826         }
1827
1828         return ERR_PTR(-ELNRNG);
1829 }
1830
1831 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1832 {
1833         struct rtl8169_private *tp = netdev_priv(dev);
1834         const struct rtl_coalesce_info *ci;
1835         const struct rtl_coalesce_scale *scale;
1836         struct {
1837                 u32 *max_frames;
1838                 u32 *usecs;
1839         } coal_settings [] = {
1840                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1841                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1842         }, *p = coal_settings;
1843         int i;
1844         u16 w;
1845
1846         memset(ec, 0, sizeof(*ec));
1847
1848         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1849         ci = rtl_coalesce_info(dev);
1850         if (IS_ERR(ci))
1851                 return PTR_ERR(ci);
1852
1853         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1854
1855         /* read IntrMitigate and adjust according to scale */
1856         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1857                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1858                 w >>= RTL_COALESCE_SHIFT;
1859                 *p->usecs = w & RTL_COALESCE_MASK;
1860         }
1861
1862         for (i = 0; i < 2; i++) {
1863                 p = coal_settings + i;
1864                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1865
1866                 /*
1867                  * ethtool_coalesce says it is illegal to set both usecs and
1868                  * max_frames to 0.
1869                  */
1870                 if (!*p->usecs && !*p->max_frames)
1871                         *p->max_frames = 1;
1872         }
1873
1874         return 0;
1875 }
1876
1877 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1878 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1879                         struct net_device *dev, u32 nsec, u16 *cp01)
1880 {
1881         const struct rtl_coalesce_info *ci;
1882         u16 i;
1883
1884         ci = rtl_coalesce_info(dev);
1885         if (IS_ERR(ci))
1886                 return ERR_CAST(ci);
1887
1888         for (i = 0; i < 4; i++) {
1889                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1890                                         ci->scalev[i].nsecs[1]);
1891                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1892                         *cp01 = i;
1893                         return &ci->scalev[i];
1894                 }
1895         }
1896
1897         return ERR_PTR(-EINVAL);
1898 }
1899
1900 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1901 {
1902         struct rtl8169_private *tp = netdev_priv(dev);
1903         const struct rtl_coalesce_scale *scale;
1904         struct {
1905                 u32 frames;
1906                 u32 usecs;
1907         } coal_settings [] = {
1908                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1909                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1910         }, *p = coal_settings;
1911         u16 w = 0, cp01;
1912         int i;
1913
1914         scale = rtl_coalesce_choose_scale(dev,
1915                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1916         if (IS_ERR(scale))
1917                 return PTR_ERR(scale);
1918
1919         for (i = 0; i < 2; i++, p++) {
1920                 u32 units;
1921
1922                 /*
1923                  * accept max_frames=1 we returned in rtl_get_coalesce.
1924                  * accept it not only when usecs=0 because of e.g. the following scenario:
1925                  *
1926                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1927                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1928                  * - then user does `ethtool -C eth0 rx-usecs 100`
1929                  *
1930                  * since ethtool sends to kernel whole ethtool_coalesce
1931                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1932                  * we'll reject it below in `frames % 4 != 0`.
1933                  */
1934                 if (p->frames == 1) {
1935                         p->frames = 0;
1936                 }
1937
1938                 units = p->usecs * 1000 / scale->nsecs[i];
1939                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1940                         return -EINVAL;
1941
1942                 w <<= RTL_COALESCE_SHIFT;
1943                 w |= units;
1944                 w <<= RTL_COALESCE_SHIFT;
1945                 w |= p->frames >> 2;
1946         }
1947
1948         rtl_lock_work(tp);
1949
1950         RTL_W16(tp, IntrMitigate, swab16(w));
1951
1952         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1953         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1954         RTL_R16(tp, CPlusCmd);
1955
1956         rtl_unlock_work(tp);
1957
1958         return 0;
1959 }
1960
1961 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1962 {
1963         struct phy_device *phydev = tp->phydev;
1964         int ret;
1965
1966         switch (tp->mac_version) {
1967         case RTL_GIGA_MAC_VER_34:
1968         case RTL_GIGA_MAC_VER_35:
1969         case RTL_GIGA_MAC_VER_36:
1970         case RTL_GIGA_MAC_VER_38:
1971                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1972                 break;
1973         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1974                 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1975                 break;
1976         default:
1977                 ret = -EPROTONOSUPPORT;
1978                 break;
1979         }
1980
1981         return ret;
1982 }
1983
1984 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1985 {
1986         struct phy_device *phydev = tp->phydev;
1987         int ret;
1988
1989         switch (tp->mac_version) {
1990         case RTL_GIGA_MAC_VER_34:
1991         case RTL_GIGA_MAC_VER_35:
1992         case RTL_GIGA_MAC_VER_36:
1993         case RTL_GIGA_MAC_VER_38:
1994                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1995                 break;
1996         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1997                 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1998                 break;
1999         default:
2000                 ret = -EPROTONOSUPPORT;
2001                 break;
2002         }
2003
2004         return ret;
2005 }
2006
2007 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2008 {
2009         struct phy_device *phydev = tp->phydev;
2010         int ret;
2011
2012         switch (tp->mac_version) {
2013         case RTL_GIGA_MAC_VER_34:
2014         case RTL_GIGA_MAC_VER_35:
2015         case RTL_GIGA_MAC_VER_36:
2016         case RTL_GIGA_MAC_VER_38:
2017                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2018                 break;
2019         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2020                 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
2021                 break;
2022         default:
2023                 ret = -EPROTONOSUPPORT;
2024                 break;
2025         }
2026
2027         return ret;
2028 }
2029
2030 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2031 {
2032         struct phy_device *phydev = tp->phydev;
2033         int ret = 0;
2034
2035         switch (tp->mac_version) {
2036         case RTL_GIGA_MAC_VER_34:
2037         case RTL_GIGA_MAC_VER_35:
2038         case RTL_GIGA_MAC_VER_36:
2039         case RTL_GIGA_MAC_VER_38:
2040                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2041                 break;
2042         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2043                 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2044                 break;
2045         default:
2046                 ret = -EPROTONOSUPPORT;
2047                 break;
2048         }
2049
2050         return ret;
2051 }
2052
2053 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2054 {
2055         struct rtl8169_private *tp = netdev_priv(dev);
2056         struct device *d = tp_to_dev(tp);
2057         int ret;
2058
2059         pm_runtime_get_noresume(d);
2060
2061         if (!pm_runtime_active(d)) {
2062                 ret = -EOPNOTSUPP;
2063                 goto out;
2064         }
2065
2066         /* Get Supported EEE */
2067         ret = rtl_get_eee_supp(tp);
2068         if (ret < 0)
2069                 goto out;
2070         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2071
2072         /* Get advertisement EEE */
2073         ret = rtl_get_eee_adv(tp);
2074         if (ret < 0)
2075                 goto out;
2076         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2077         data->eee_enabled = !!data->advertised;
2078
2079         /* Get LP advertisement EEE */
2080         ret = rtl_get_eee_lpadv(tp);
2081         if (ret < 0)
2082                 goto out;
2083         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2084         data->eee_active = !!(data->advertised & data->lp_advertised);
2085 out:
2086         pm_runtime_put_noidle(d);
2087         return ret < 0 ? ret : 0;
2088 }
2089
2090 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2091 {
2092         struct rtl8169_private *tp = netdev_priv(dev);
2093         struct device *d = tp_to_dev(tp);
2094         int old_adv, adv = 0, cap, ret;
2095
2096         pm_runtime_get_noresume(d);
2097
2098         if (!dev->phydev || !pm_runtime_active(d)) {
2099                 ret = -EOPNOTSUPP;
2100                 goto out;
2101         }
2102
2103         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2104             dev->phydev->duplex != DUPLEX_FULL) {
2105                 ret = -EPROTONOSUPPORT;
2106                 goto out;
2107         }
2108
2109         /* Get Supported EEE */
2110         ret = rtl_get_eee_supp(tp);
2111         if (ret < 0)
2112                 goto out;
2113         cap = ret;
2114
2115         ret = rtl_get_eee_adv(tp);
2116         if (ret < 0)
2117                 goto out;
2118         old_adv = ret;
2119
2120         if (data->eee_enabled) {
2121                 adv = !data->advertised ? cap :
2122                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2123                 /* Mask prohibited EEE modes */
2124                 adv &= ~dev->phydev->eee_broken_modes;
2125         }
2126
2127         if (old_adv != adv) {
2128                 ret = rtl_set_eee_adv(tp, adv);
2129                 if (ret < 0)
2130                         goto out;
2131
2132                 /* Restart autonegotiation so the new modes get sent to the
2133                  * link partner.
2134                  */
2135                 ret = phy_restart_aneg(dev->phydev);
2136         }
2137
2138 out:
2139         pm_runtime_put_noidle(d);
2140         return ret < 0 ? ret : 0;
2141 }
2142
2143 static const struct ethtool_ops rtl8169_ethtool_ops = {
2144         .get_drvinfo            = rtl8169_get_drvinfo,
2145         .get_regs_len           = rtl8169_get_regs_len,
2146         .get_link               = ethtool_op_get_link,
2147         .get_coalesce           = rtl_get_coalesce,
2148         .set_coalesce           = rtl_set_coalesce,
2149         .get_msglevel           = rtl8169_get_msglevel,
2150         .set_msglevel           = rtl8169_set_msglevel,
2151         .get_regs               = rtl8169_get_regs,
2152         .get_wol                = rtl8169_get_wol,
2153         .set_wol                = rtl8169_set_wol,
2154         .get_strings            = rtl8169_get_strings,
2155         .get_sset_count         = rtl8169_get_sset_count,
2156         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2157         .get_ts_info            = ethtool_op_get_ts_info,
2158         .nway_reset             = phy_ethtool_nway_reset,
2159         .get_eee                = rtl8169_get_eee,
2160         .set_eee                = rtl8169_set_eee,
2161         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2162         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2163 };
2164
2165 static void rtl_enable_eee(struct rtl8169_private *tp)
2166 {
2167         int supported = rtl_get_eee_supp(tp);
2168
2169         if (supported > 0)
2170                 rtl_set_eee_adv(tp, supported);
2171 }
2172
2173 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2174 {
2175         /*
2176          * The driver currently handles the 8168Bf and the 8168Be identically
2177          * but they can be identified more specifically through the test below
2178          * if needed:
2179          *
2180          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2181          *
2182          * Same thing for the 8101Eb and the 8101Ec:
2183          *
2184          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2185          */
2186         static const struct rtl_mac_info {
2187                 u16 mask;
2188                 u16 val;
2189                 u16 mac_version;
2190         } mac_info[] = {
2191                 /* 8168EP family. */
2192                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2193                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2194                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2195
2196                 /* 8168H family. */
2197                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2198                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2199
2200                 /* 8168G family. */
2201                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2202                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2203                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2204                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2205
2206                 /* 8168F family. */
2207                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2208                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2209                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2210
2211                 /* 8168E family. */
2212                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2213                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2214                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2215
2216                 /* 8168D family. */
2217                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2218                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2219
2220                 /* 8168DP family. */
2221                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2222                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2223                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2224
2225                 /* 8168C family. */
2226                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2227                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2228                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2229                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2230                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2231                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2232                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2233
2234                 /* 8168B family. */
2235                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2236                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2237                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2238
2239                 /* 8101 family. */
2240                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2241                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2242                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2243                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2244                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2245                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2246                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2247                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2248                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2249                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2250                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2251                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2252                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2253                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2254                 /* FIXME: where did these entries come from ? -- FR */
2255                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2256                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2257
2258                 /* 8110 family. */
2259                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2260                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2261                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2262                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2263                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2264
2265                 /* Catch-all */
2266                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2267         };
2268         const struct rtl_mac_info *p = mac_info;
2269         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2270
2271         while ((reg & p->mask) != p->val)
2272                 p++;
2273         tp->mac_version = p->mac_version;
2274
2275         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2276                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2277         } else if (!tp->supports_gmii) {
2278                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2279                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2280                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2281                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2282                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2283                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2284         }
2285 }
2286
2287 struct phy_reg {
2288         u16 reg;
2289         u16 val;
2290 };
2291
2292 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2293                                  const struct phy_reg *regs, int len)
2294 {
2295         while (len-- > 0) {
2296                 rtl_writephy(tp, regs->reg, regs->val);
2297                 regs++;
2298         }
2299 }
2300
2301 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2302
2303 enum rtl_fw_opcode {
2304         PHY_READ                = 0x0,
2305         PHY_DATA_OR             = 0x1,
2306         PHY_DATA_AND            = 0x2,
2307         PHY_BJMPN               = 0x3,
2308         PHY_MDIO_CHG            = 0x4,
2309         PHY_CLEAR_READCOUNT     = 0x7,
2310         PHY_WRITE               = 0x8,
2311         PHY_READCOUNT_EQ_SKIP   = 0x9,
2312         PHY_COMP_EQ_SKIPN       = 0xa,
2313         PHY_COMP_NEQ_SKIPN      = 0xb,
2314         PHY_WRITE_PREVIOUS      = 0xc,
2315         PHY_SKIPN               = 0xd,
2316         PHY_DELAY_MS            = 0xe,
2317 };
2318
2319 struct fw_info {
2320         u32     magic;
2321         char    version[RTL_VER_SIZE];
2322         __le32  fw_start;
2323         __le32  fw_len;
2324         u8      chksum;
2325 } __packed;
2326
2327 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2328
2329 static bool rtl_fw_format_ok(struct rtl_fw *rtl_fw)
2330 {
2331         const struct firmware *fw = rtl_fw->fw;
2332         struct fw_info *fw_info = (struct fw_info *)fw->data;
2333         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2334
2335         if (fw->size < FW_OPCODE_SIZE)
2336                 return false;
2337
2338         if (!fw_info->magic) {
2339                 size_t i, size, start;
2340                 u8 checksum = 0;
2341
2342                 if (fw->size < sizeof(*fw_info))
2343                         return false;
2344
2345                 for (i = 0; i < fw->size; i++)
2346                         checksum += fw->data[i];
2347                 if (checksum != 0)
2348                         return false;
2349
2350                 start = le32_to_cpu(fw_info->fw_start);
2351                 if (start > fw->size)
2352                         return false;
2353
2354                 size = le32_to_cpu(fw_info->fw_len);
2355                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2356                         return false;
2357
2358                 strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
2359
2360                 pa->code = (__le32 *)(fw->data + start);
2361                 pa->size = size;
2362         } else {
2363                 if (fw->size % FW_OPCODE_SIZE)
2364                         return false;
2365
2366                 strscpy(rtl_fw->version, rtl_fw->fw_name, RTL_VER_SIZE);
2367
2368                 pa->code = (__le32 *)fw->data;
2369                 pa->size = fw->size / FW_OPCODE_SIZE;
2370         }
2371
2372         return true;
2373 }
2374
2375 static bool rtl_fw_data_ok(struct rtl_fw *rtl_fw)
2376 {
2377         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2378         size_t index;
2379
2380         for (index = 0; index < pa->size; index++) {
2381                 u32 action = le32_to_cpu(pa->code[index]);
2382                 u32 regno = (action & 0x0fff0000) >> 16;
2383
2384                 switch (action >> 28) {
2385                 case PHY_READ:
2386                 case PHY_DATA_OR:
2387                 case PHY_DATA_AND:
2388                 case PHY_MDIO_CHG:
2389                 case PHY_CLEAR_READCOUNT:
2390                 case PHY_WRITE:
2391                 case PHY_WRITE_PREVIOUS:
2392                 case PHY_DELAY_MS:
2393                         break;
2394
2395                 case PHY_BJMPN:
2396                         if (regno > index)
2397                                 goto out;
2398                         break;
2399                 case PHY_READCOUNT_EQ_SKIP:
2400                         if (index + 2 >= pa->size)
2401                                 goto out;
2402                         break;
2403                 case PHY_COMP_EQ_SKIPN:
2404                 case PHY_COMP_NEQ_SKIPN:
2405                 case PHY_SKIPN:
2406                         if (index + 1 + regno >= pa->size)
2407                                 goto out;
2408                         break;
2409
2410                 default:
2411                         dev_err(rtl_fw->dev, "Invalid action 0x%08x\n", action);
2412                         return false;
2413                 }
2414         }
2415
2416         return true;
2417 out:
2418         dev_err(rtl_fw->dev, "Out of range of firmware\n");
2419         return false;
2420 }
2421
2422 static void rtl_fw_write_firmware(struct rtl8169_private *tp,
2423                                   struct rtl_fw *rtl_fw)
2424 {
2425         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2426         rtl_fw_write_t fw_write = rtl_fw->phy_write;
2427         rtl_fw_read_t fw_read = rtl_fw->phy_read;
2428         int predata = 0, count = 0;
2429         size_t index;
2430
2431         for (index = 0; index < pa->size; index++) {
2432                 u32 action = le32_to_cpu(pa->code[index]);
2433                 u32 data = action & 0x0000ffff;
2434                 u32 regno = (action & 0x0fff0000) >> 16;
2435                 enum rtl_fw_opcode opcode = action >> 28;
2436
2437                 if (!action)
2438                         break;
2439
2440                 switch (opcode) {
2441                 case PHY_READ:
2442                         predata = fw_read(tp, regno);
2443                         count++;
2444                         break;
2445                 case PHY_DATA_OR:
2446                         predata |= data;
2447                         break;
2448                 case PHY_DATA_AND:
2449                         predata &= data;
2450                         break;
2451                 case PHY_BJMPN:
2452                         index -= (regno + 1);
2453                         break;
2454                 case PHY_MDIO_CHG:
2455                         if (data == 0) {
2456                                 fw_write = rtl_fw->phy_write;
2457                                 fw_read = rtl_fw->phy_read;
2458                         } else if (data == 1) {
2459                                 fw_write = rtl_fw->mac_mcu_write;
2460                                 fw_read = rtl_fw->mac_mcu_read;
2461                         }
2462
2463                         break;
2464                 case PHY_CLEAR_READCOUNT:
2465                         count = 0;
2466                         break;
2467                 case PHY_WRITE:
2468                         fw_write(tp, regno, data);
2469                         break;
2470                 case PHY_READCOUNT_EQ_SKIP:
2471                         if (count == data)
2472                                 index++;
2473                         break;
2474                 case PHY_COMP_EQ_SKIPN:
2475                         if (predata == data)
2476                                 index += regno;
2477                         break;
2478                 case PHY_COMP_NEQ_SKIPN:
2479                         if (predata != data)
2480                                 index += regno;
2481                         break;
2482                 case PHY_WRITE_PREVIOUS:
2483                         fw_write(tp, regno, predata);
2484                         break;
2485                 case PHY_SKIPN:
2486                         index += regno;
2487                         break;
2488                 case PHY_DELAY_MS:
2489                         mdelay(data);
2490                         break;
2491                 }
2492         }
2493 }
2494
2495 static void rtl_release_firmware(struct rtl8169_private *tp)
2496 {
2497         if (tp->rtl_fw) {
2498                 release_firmware(tp->rtl_fw->fw);
2499                 kfree(tp->rtl_fw);
2500                 tp->rtl_fw = NULL;
2501         }
2502 }
2503
2504 static void rtl_apply_firmware(struct rtl8169_private *tp)
2505 {
2506         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2507         if (tp->rtl_fw)
2508                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2509 }
2510
2511 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2512 {
2513         if (rtl_readphy(tp, reg) != val)
2514                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2515         else
2516                 rtl_apply_firmware(tp);
2517 }
2518
2519 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2520 {
2521         /* Adjust EEE LED frequency */
2522         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2523                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2524
2525         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2526 }
2527
2528 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2529 {
2530         struct phy_device *phydev = tp->phydev;
2531
2532         phy_write(phydev, 0x1f, 0x0007);
2533         phy_write(phydev, 0x1e, 0x0020);
2534         phy_set_bits(phydev, 0x15, BIT(8));
2535
2536         phy_write(phydev, 0x1f, 0x0005);
2537         phy_write(phydev, 0x05, 0x8b85);
2538         phy_set_bits(phydev, 0x06, BIT(13));
2539
2540         phy_write(phydev, 0x1f, 0x0000);
2541 }
2542
2543 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2544 {
2545         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2546 }
2547
2548 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2549 {
2550         static const struct phy_reg phy_reg_init[] = {
2551                 { 0x1f, 0x0001 },
2552                 { 0x06, 0x006e },
2553                 { 0x08, 0x0708 },
2554                 { 0x15, 0x4000 },
2555                 { 0x18, 0x65c7 },
2556
2557                 { 0x1f, 0x0001 },
2558                 { 0x03, 0x00a1 },
2559                 { 0x02, 0x0008 },
2560                 { 0x01, 0x0120 },
2561                 { 0x00, 0x1000 },
2562                 { 0x04, 0x0800 },
2563                 { 0x04, 0x0000 },
2564
2565                 { 0x03, 0xff41 },
2566                 { 0x02, 0xdf60 },
2567                 { 0x01, 0x0140 },
2568                 { 0x00, 0x0077 },
2569                 { 0x04, 0x7800 },
2570                 { 0x04, 0x7000 },
2571
2572                 { 0x03, 0x802f },
2573                 { 0x02, 0x4f02 },
2574                 { 0x01, 0x0409 },
2575                 { 0x00, 0xf0f9 },
2576                 { 0x04, 0x9800 },
2577                 { 0x04, 0x9000 },
2578
2579                 { 0x03, 0xdf01 },
2580                 { 0x02, 0xdf20 },
2581                 { 0x01, 0xff95 },
2582                 { 0x00, 0xba00 },
2583                 { 0x04, 0xa800 },
2584                 { 0x04, 0xa000 },
2585
2586                 { 0x03, 0xff41 },
2587                 { 0x02, 0xdf20 },
2588                 { 0x01, 0x0140 },
2589                 { 0x00, 0x00bb },
2590                 { 0x04, 0xb800 },
2591                 { 0x04, 0xb000 },
2592
2593                 { 0x03, 0xdf41 },
2594                 { 0x02, 0xdc60 },
2595                 { 0x01, 0x6340 },
2596                 { 0x00, 0x007d },
2597                 { 0x04, 0xd800 },
2598                 { 0x04, 0xd000 },
2599
2600                 { 0x03, 0xdf01 },
2601                 { 0x02, 0xdf20 },
2602                 { 0x01, 0x100a },
2603                 { 0x00, 0xa0ff },
2604                 { 0x04, 0xf800 },
2605                 { 0x04, 0xf000 },
2606
2607                 { 0x1f, 0x0000 },
2608                 { 0x0b, 0x0000 },
2609                 { 0x00, 0x9200 }
2610         };
2611
2612         rtl_writephy_batch(tp, phy_reg_init);
2613 }
2614
2615 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2616 {
2617         static const struct phy_reg phy_reg_init[] = {
2618                 { 0x1f, 0x0002 },
2619                 { 0x01, 0x90d0 },
2620                 { 0x1f, 0x0000 }
2621         };
2622
2623         rtl_writephy_batch(tp, phy_reg_init);
2624 }
2625
2626 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2627 {
2628         struct pci_dev *pdev = tp->pci_dev;
2629
2630         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2631             (pdev->subsystem_device != 0xe000))
2632                 return;
2633
2634         rtl_writephy(tp, 0x1f, 0x0001);
2635         rtl_writephy(tp, 0x10, 0xf01b);
2636         rtl_writephy(tp, 0x1f, 0x0000);
2637 }
2638
2639 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2640 {
2641         static const struct phy_reg phy_reg_init[] = {
2642                 { 0x1f, 0x0001 },
2643                 { 0x04, 0x0000 },
2644                 { 0x03, 0x00a1 },
2645                 { 0x02, 0x0008 },
2646                 { 0x01, 0x0120 },
2647                 { 0x00, 0x1000 },
2648                 { 0x04, 0x0800 },
2649                 { 0x04, 0x9000 },
2650                 { 0x03, 0x802f },
2651                 { 0x02, 0x4f02 },
2652                 { 0x01, 0x0409 },
2653                 { 0x00, 0xf099 },
2654                 { 0x04, 0x9800 },
2655                 { 0x04, 0xa000 },
2656                 { 0x03, 0xdf01 },
2657                 { 0x02, 0xdf20 },
2658                 { 0x01, 0xff95 },
2659                 { 0x00, 0xba00 },
2660                 { 0x04, 0xa800 },
2661                 { 0x04, 0xf000 },
2662                 { 0x03, 0xdf01 },
2663                 { 0x02, 0xdf20 },
2664                 { 0x01, 0x101a },
2665                 { 0x00, 0xa0ff },
2666                 { 0x04, 0xf800 },
2667                 { 0x04, 0x0000 },
2668                 { 0x1f, 0x0000 },
2669
2670                 { 0x1f, 0x0001 },
2671                 { 0x10, 0xf41b },
2672                 { 0x14, 0xfb54 },
2673                 { 0x18, 0xf5c7 },
2674                 { 0x1f, 0x0000 },
2675
2676                 { 0x1f, 0x0001 },
2677                 { 0x17, 0x0cc0 },
2678                 { 0x1f, 0x0000 }
2679         };
2680
2681         rtl_writephy_batch(tp, phy_reg_init);
2682
2683         rtl8169scd_hw_phy_config_quirk(tp);
2684 }
2685
2686 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2687 {
2688         static const struct phy_reg phy_reg_init[] = {
2689                 { 0x1f, 0x0001 },
2690                 { 0x04, 0x0000 },
2691                 { 0x03, 0x00a1 },
2692                 { 0x02, 0x0008 },
2693                 { 0x01, 0x0120 },
2694                 { 0x00, 0x1000 },
2695                 { 0x04, 0x0800 },
2696                 { 0x04, 0x9000 },
2697                 { 0x03, 0x802f },
2698                 { 0x02, 0x4f02 },
2699                 { 0x01, 0x0409 },
2700                 { 0x00, 0xf099 },
2701                 { 0x04, 0x9800 },
2702                 { 0x04, 0xa000 },
2703                 { 0x03, 0xdf01 },
2704                 { 0x02, 0xdf20 },
2705                 { 0x01, 0xff95 },
2706                 { 0x00, 0xba00 },
2707                 { 0x04, 0xa800 },
2708                 { 0x04, 0xf000 },
2709                 { 0x03, 0xdf01 },
2710                 { 0x02, 0xdf20 },
2711                 { 0x01, 0x101a },
2712                 { 0x00, 0xa0ff },
2713                 { 0x04, 0xf800 },
2714                 { 0x04, 0x0000 },
2715                 { 0x1f, 0x0000 },
2716
2717                 { 0x1f, 0x0001 },
2718                 { 0x0b, 0x8480 },
2719                 { 0x1f, 0x0000 },
2720
2721                 { 0x1f, 0x0001 },
2722                 { 0x18, 0x67c7 },
2723                 { 0x04, 0x2000 },
2724                 { 0x03, 0x002f },
2725                 { 0x02, 0x4360 },
2726                 { 0x01, 0x0109 },
2727                 { 0x00, 0x3022 },
2728                 { 0x04, 0x2800 },
2729                 { 0x1f, 0x0000 },
2730
2731                 { 0x1f, 0x0001 },
2732                 { 0x17, 0x0cc0 },
2733                 { 0x1f, 0x0000 }
2734         };
2735
2736         rtl_writephy_batch(tp, phy_reg_init);
2737 }
2738
2739 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2740 {
2741         static const struct phy_reg phy_reg_init[] = {
2742                 { 0x10, 0xf41b },
2743                 { 0x1f, 0x0000 }
2744         };
2745
2746         rtl_writephy(tp, 0x1f, 0x0001);
2747         rtl_patchphy(tp, 0x16, 1 << 0);
2748
2749         rtl_writephy_batch(tp, phy_reg_init);
2750 }
2751
2752 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2753 {
2754         static const struct phy_reg phy_reg_init[] = {
2755                 { 0x1f, 0x0001 },
2756                 { 0x10, 0xf41b },
2757                 { 0x1f, 0x0000 }
2758         };
2759
2760         rtl_writephy_batch(tp, phy_reg_init);
2761 }
2762
2763 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2764 {
2765         static const struct phy_reg phy_reg_init[] = {
2766                 { 0x1f, 0x0000 },
2767                 { 0x1d, 0x0f00 },
2768                 { 0x1f, 0x0002 },
2769                 { 0x0c, 0x1ec8 },
2770                 { 0x1f, 0x0000 }
2771         };
2772
2773         rtl_writephy_batch(tp, phy_reg_init);
2774 }
2775
2776 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2777 {
2778         static const struct phy_reg phy_reg_init[] = {
2779                 { 0x1f, 0x0001 },
2780                 { 0x1d, 0x3d98 },
2781                 { 0x1f, 0x0000 }
2782         };
2783
2784         rtl_writephy(tp, 0x1f, 0x0000);
2785         rtl_patchphy(tp, 0x14, 1 << 5);
2786         rtl_patchphy(tp, 0x0d, 1 << 5);
2787
2788         rtl_writephy_batch(tp, phy_reg_init);
2789 }
2790
2791 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2792 {
2793         static const struct phy_reg phy_reg_init[] = {
2794                 { 0x1f, 0x0001 },
2795                 { 0x12, 0x2300 },
2796                 { 0x1f, 0x0002 },
2797                 { 0x00, 0x88d4 },
2798                 { 0x01, 0x82b1 },
2799                 { 0x03, 0x7002 },
2800                 { 0x08, 0x9e30 },
2801                 { 0x09, 0x01f0 },
2802                 { 0x0a, 0x5500 },
2803                 { 0x0c, 0x00c8 },
2804                 { 0x1f, 0x0003 },
2805                 { 0x12, 0xc096 },
2806                 { 0x16, 0x000a },
2807                 { 0x1f, 0x0000 },
2808                 { 0x1f, 0x0000 },
2809                 { 0x09, 0x2000 },
2810                 { 0x09, 0x0000 }
2811         };
2812
2813         rtl_writephy_batch(tp, phy_reg_init);
2814
2815         rtl_patchphy(tp, 0x14, 1 << 5);
2816         rtl_patchphy(tp, 0x0d, 1 << 5);
2817         rtl_writephy(tp, 0x1f, 0x0000);
2818 }
2819
2820 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2821 {
2822         static const struct phy_reg phy_reg_init[] = {
2823                 { 0x1f, 0x0001 },
2824                 { 0x12, 0x2300 },
2825                 { 0x03, 0x802f },
2826                 { 0x02, 0x4f02 },
2827                 { 0x01, 0x0409 },
2828                 { 0x00, 0xf099 },
2829                 { 0x04, 0x9800 },
2830                 { 0x04, 0x9000 },
2831                 { 0x1d, 0x3d98 },
2832                 { 0x1f, 0x0002 },
2833                 { 0x0c, 0x7eb8 },
2834                 { 0x06, 0x0761 },
2835                 { 0x1f, 0x0003 },
2836                 { 0x16, 0x0f0a },
2837                 { 0x1f, 0x0000 }
2838         };
2839
2840         rtl_writephy_batch(tp, phy_reg_init);
2841
2842         rtl_patchphy(tp, 0x16, 1 << 0);
2843         rtl_patchphy(tp, 0x14, 1 << 5);
2844         rtl_patchphy(tp, 0x0d, 1 << 5);
2845         rtl_writephy(tp, 0x1f, 0x0000);
2846 }
2847
2848 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2849 {
2850         static const struct phy_reg phy_reg_init[] = {
2851                 { 0x1f, 0x0001 },
2852                 { 0x12, 0x2300 },
2853                 { 0x1d, 0x3d98 },
2854                 { 0x1f, 0x0002 },
2855                 { 0x0c, 0x7eb8 },
2856                 { 0x06, 0x5461 },
2857                 { 0x1f, 0x0003 },
2858                 { 0x16, 0x0f0a },
2859                 { 0x1f, 0x0000 }
2860         };
2861
2862         rtl_writephy_batch(tp, phy_reg_init);
2863
2864         rtl_patchphy(tp, 0x16, 1 << 0);
2865         rtl_patchphy(tp, 0x14, 1 << 5);
2866         rtl_patchphy(tp, 0x0d, 1 << 5);
2867         rtl_writephy(tp, 0x1f, 0x0000);
2868 }
2869
2870 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2871 {
2872         rtl8168c_3_hw_phy_config(tp);
2873 }
2874
2875 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2876         /* Channel Estimation */
2877         { 0x1f, 0x0001 },
2878         { 0x06, 0x4064 },
2879         { 0x07, 0x2863 },
2880         { 0x08, 0x059c },
2881         { 0x09, 0x26b4 },
2882         { 0x0a, 0x6a19 },
2883         { 0x0b, 0xdcc8 },
2884         { 0x10, 0xf06d },
2885         { 0x14, 0x7f68 },
2886         { 0x18, 0x7fd9 },
2887         { 0x1c, 0xf0ff },
2888         { 0x1d, 0x3d9c },
2889         { 0x1f, 0x0003 },
2890         { 0x12, 0xf49f },
2891         { 0x13, 0x070b },
2892         { 0x1a, 0x05ad },
2893         { 0x14, 0x94c0 },
2894
2895         /*
2896          * Tx Error Issue
2897          * Enhance line driver power
2898          */
2899         { 0x1f, 0x0002 },
2900         { 0x06, 0x5561 },
2901         { 0x1f, 0x0005 },
2902         { 0x05, 0x8332 },
2903         { 0x06, 0x5561 },
2904
2905         /*
2906          * Can not link to 1Gbps with bad cable
2907          * Decrease SNR threshold form 21.07dB to 19.04dB
2908          */
2909         { 0x1f, 0x0001 },
2910         { 0x17, 0x0cc0 },
2911
2912         { 0x1f, 0x0000 },
2913         { 0x0d, 0xf880 }
2914 };
2915
2916 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2917         { 0x1f, 0x0002 },
2918         { 0x05, 0x669a },
2919         { 0x1f, 0x0005 },
2920         { 0x05, 0x8330 },
2921         { 0x06, 0x669a },
2922         { 0x1f, 0x0002 }
2923 };
2924
2925 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2926 {
2927         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2928
2929         /*
2930          * Rx Error Issue
2931          * Fine Tune Switching regulator parameter
2932          */
2933         rtl_writephy(tp, 0x1f, 0x0002);
2934         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2935         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2936
2937         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2938                 int val;
2939
2940                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2941
2942                 val = rtl_readphy(tp, 0x0d);
2943
2944                 if ((val & 0x00ff) != 0x006c) {
2945                         static const u32 set[] = {
2946                                 0x0065, 0x0066, 0x0067, 0x0068,
2947                                 0x0069, 0x006a, 0x006b, 0x006c
2948                         };
2949                         int i;
2950
2951                         rtl_writephy(tp, 0x1f, 0x0002);
2952
2953                         val &= 0xff00;
2954                         for (i = 0; i < ARRAY_SIZE(set); i++)
2955                                 rtl_writephy(tp, 0x0d, val | set[i]);
2956                 }
2957         } else {
2958                 static const struct phy_reg phy_reg_init[] = {
2959                         { 0x1f, 0x0002 },
2960                         { 0x05, 0x6662 },
2961                         { 0x1f, 0x0005 },
2962                         { 0x05, 0x8330 },
2963                         { 0x06, 0x6662 }
2964                 };
2965
2966                 rtl_writephy_batch(tp, phy_reg_init);
2967         }
2968
2969         /* RSET couple improve */
2970         rtl_writephy(tp, 0x1f, 0x0002);
2971         rtl_patchphy(tp, 0x0d, 0x0300);
2972         rtl_patchphy(tp, 0x0f, 0x0010);
2973
2974         /* Fine tune PLL performance */
2975         rtl_writephy(tp, 0x1f, 0x0002);
2976         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2977         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2978
2979         rtl_writephy(tp, 0x1f, 0x0005);
2980         rtl_writephy(tp, 0x05, 0x001b);
2981
2982         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2983
2984         rtl_writephy(tp, 0x1f, 0x0000);
2985 }
2986
2987 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2988 {
2989         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2990
2991         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2992                 int val;
2993
2994                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2995
2996                 val = rtl_readphy(tp, 0x0d);
2997                 if ((val & 0x00ff) != 0x006c) {
2998                         static const u32 set[] = {
2999                                 0x0065, 0x0066, 0x0067, 0x0068,
3000                                 0x0069, 0x006a, 0x006b, 0x006c
3001                         };
3002                         int i;
3003
3004                         rtl_writephy(tp, 0x1f, 0x0002);
3005
3006                         val &= 0xff00;
3007                         for (i = 0; i < ARRAY_SIZE(set); i++)
3008                                 rtl_writephy(tp, 0x0d, val | set[i]);
3009                 }
3010         } else {
3011                 static const struct phy_reg phy_reg_init[] = {
3012                         { 0x1f, 0x0002 },
3013                         { 0x05, 0x2642 },
3014                         { 0x1f, 0x0005 },
3015                         { 0x05, 0x8330 },
3016                         { 0x06, 0x2642 }
3017                 };
3018
3019                 rtl_writephy_batch(tp, phy_reg_init);
3020         }
3021
3022         /* Fine tune PLL performance */
3023         rtl_writephy(tp, 0x1f, 0x0002);
3024         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3025         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3026
3027         /* Switching regulator Slew rate */
3028         rtl_writephy(tp, 0x1f, 0x0002);
3029         rtl_patchphy(tp, 0x0f, 0x0017);
3030
3031         rtl_writephy(tp, 0x1f, 0x0005);
3032         rtl_writephy(tp, 0x05, 0x001b);
3033
3034         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3035
3036         rtl_writephy(tp, 0x1f, 0x0000);
3037 }
3038
3039 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3040 {
3041         static const struct phy_reg phy_reg_init[] = {
3042                 { 0x1f, 0x0002 },
3043                 { 0x10, 0x0008 },
3044                 { 0x0d, 0x006c },
3045
3046                 { 0x1f, 0x0000 },
3047                 { 0x0d, 0xf880 },
3048
3049                 { 0x1f, 0x0001 },
3050                 { 0x17, 0x0cc0 },
3051
3052                 { 0x1f, 0x0001 },
3053                 { 0x0b, 0xa4d8 },
3054                 { 0x09, 0x281c },
3055                 { 0x07, 0x2883 },
3056                 { 0x0a, 0x6b35 },
3057                 { 0x1d, 0x3da4 },
3058                 { 0x1c, 0xeffd },
3059                 { 0x14, 0x7f52 },
3060                 { 0x18, 0x7fc6 },
3061                 { 0x08, 0x0601 },
3062                 { 0x06, 0x4063 },
3063                 { 0x10, 0xf074 },
3064                 { 0x1f, 0x0003 },
3065                 { 0x13, 0x0789 },
3066                 { 0x12, 0xf4bd },
3067                 { 0x1a, 0x04fd },
3068                 { 0x14, 0x84b0 },
3069                 { 0x1f, 0x0000 },
3070                 { 0x00, 0x9200 },
3071
3072                 { 0x1f, 0x0005 },
3073                 { 0x01, 0x0340 },
3074                 { 0x1f, 0x0001 },
3075                 { 0x04, 0x4000 },
3076                 { 0x03, 0x1d21 },
3077                 { 0x02, 0x0c32 },
3078                 { 0x01, 0x0200 },
3079                 { 0x00, 0x5554 },
3080                 { 0x04, 0x4800 },
3081                 { 0x04, 0x4000 },
3082                 { 0x04, 0xf000 },
3083                 { 0x03, 0xdf01 },
3084                 { 0x02, 0xdf20 },
3085                 { 0x01, 0x101a },
3086                 { 0x00, 0xa0ff },
3087                 { 0x04, 0xf800 },
3088                 { 0x04, 0xf000 },
3089                 { 0x1f, 0x0000 },
3090
3091                 { 0x1f, 0x0007 },
3092                 { 0x1e, 0x0023 },
3093                 { 0x16, 0x0000 },
3094                 { 0x1f, 0x0000 }
3095         };
3096
3097         rtl_writephy_batch(tp, phy_reg_init);
3098 }
3099
3100 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3101 {
3102         static const struct phy_reg phy_reg_init[] = {
3103                 { 0x1f, 0x0001 },
3104                 { 0x17, 0x0cc0 },
3105
3106                 { 0x1f, 0x0007 },
3107                 { 0x1e, 0x002d },
3108                 { 0x18, 0x0040 },
3109                 { 0x1f, 0x0000 }
3110         };
3111
3112         rtl_writephy_batch(tp, phy_reg_init);
3113         rtl_patchphy(tp, 0x0d, 1 << 5);
3114 }
3115
3116 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3117 {
3118         static const struct phy_reg phy_reg_init[] = {
3119                 /* Enable Delay cap */
3120                 { 0x1f, 0x0005 },
3121                 { 0x05, 0x8b80 },
3122                 { 0x06, 0xc896 },
3123                 { 0x1f, 0x0000 },
3124
3125                 /* Channel estimation fine tune */
3126                 { 0x1f, 0x0001 },
3127                 { 0x0b, 0x6c20 },
3128                 { 0x07, 0x2872 },
3129                 { 0x1c, 0xefff },
3130                 { 0x1f, 0x0003 },
3131                 { 0x14, 0x6420 },
3132                 { 0x1f, 0x0000 },
3133
3134                 /* Update PFM & 10M TX idle timer */
3135                 { 0x1f, 0x0007 },
3136                 { 0x1e, 0x002f },
3137                 { 0x15, 0x1919 },
3138                 { 0x1f, 0x0000 },
3139
3140                 { 0x1f, 0x0007 },
3141                 { 0x1e, 0x00ac },
3142                 { 0x18, 0x0006 },
3143                 { 0x1f, 0x0000 }
3144         };
3145
3146         rtl_apply_firmware(tp);
3147
3148         rtl_writephy_batch(tp, phy_reg_init);
3149
3150         /* DCO enable for 10M IDLE Power */
3151         rtl_writephy(tp, 0x1f, 0x0007);
3152         rtl_writephy(tp, 0x1e, 0x0023);
3153         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3154         rtl_writephy(tp, 0x1f, 0x0000);
3155
3156         /* For impedance matching */
3157         rtl_writephy(tp, 0x1f, 0x0002);
3158         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3159         rtl_writephy(tp, 0x1f, 0x0000);
3160
3161         /* PHY auto speed down */
3162         rtl_writephy(tp, 0x1f, 0x0007);
3163         rtl_writephy(tp, 0x1e, 0x002d);
3164         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3165         rtl_writephy(tp, 0x1f, 0x0000);
3166         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3167
3168         rtl_writephy(tp, 0x1f, 0x0005);
3169         rtl_writephy(tp, 0x05, 0x8b86);
3170         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3171         rtl_writephy(tp, 0x1f, 0x0000);
3172
3173         rtl_writephy(tp, 0x1f, 0x0005);
3174         rtl_writephy(tp, 0x05, 0x8b85);
3175         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3176         rtl_writephy(tp, 0x1f, 0x0007);
3177         rtl_writephy(tp, 0x1e, 0x0020);
3178         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3179         rtl_writephy(tp, 0x1f, 0x0006);
3180         rtl_writephy(tp, 0x00, 0x5a00);
3181         rtl_writephy(tp, 0x1f, 0x0000);
3182         rtl_writephy(tp, 0x0d, 0x0007);
3183         rtl_writephy(tp, 0x0e, 0x003c);
3184         rtl_writephy(tp, 0x0d, 0x4007);
3185         rtl_writephy(tp, 0x0e, 0x0000);
3186         rtl_writephy(tp, 0x0d, 0x0000);
3187 }
3188
3189 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3190 {
3191         const u16 w[] = {
3192                 addr[0] | (addr[1] << 8),
3193                 addr[2] | (addr[3] << 8),
3194                 addr[4] | (addr[5] << 8)
3195         };
3196
3197         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3198         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3199         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3200         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3201 }
3202
3203 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3204 {
3205         static const struct phy_reg phy_reg_init[] = {
3206                 /* Enable Delay cap */
3207                 { 0x1f, 0x0004 },
3208                 { 0x1f, 0x0007 },
3209                 { 0x1e, 0x00ac },
3210                 { 0x18, 0x0006 },
3211                 { 0x1f, 0x0002 },
3212                 { 0x1f, 0x0000 },
3213                 { 0x1f, 0x0000 },
3214
3215                 /* Channel estimation fine tune */
3216                 { 0x1f, 0x0003 },
3217                 { 0x09, 0xa20f },
3218                 { 0x1f, 0x0000 },
3219                 { 0x1f, 0x0000 },
3220
3221                 /* Green Setting */
3222                 { 0x1f, 0x0005 },
3223                 { 0x05, 0x8b5b },
3224                 { 0x06, 0x9222 },
3225                 { 0x05, 0x8b6d },
3226                 { 0x06, 0x8000 },
3227                 { 0x05, 0x8b76 },
3228                 { 0x06, 0x8000 },
3229                 { 0x1f, 0x0000 }
3230         };
3231
3232         rtl_apply_firmware(tp);
3233
3234         rtl_writephy_batch(tp, phy_reg_init);
3235
3236         /* For 4-corner performance improve */
3237         rtl_writephy(tp, 0x1f, 0x0005);
3238         rtl_writephy(tp, 0x05, 0x8b80);
3239         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3240         rtl_writephy(tp, 0x1f, 0x0000);
3241
3242         /* PHY auto speed down */
3243         rtl_writephy(tp, 0x1f, 0x0004);
3244         rtl_writephy(tp, 0x1f, 0x0007);
3245         rtl_writephy(tp, 0x1e, 0x002d);
3246         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3247         rtl_writephy(tp, 0x1f, 0x0002);
3248         rtl_writephy(tp, 0x1f, 0x0000);
3249         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3250
3251         /* improve 10M EEE waveform */
3252         rtl_writephy(tp, 0x1f, 0x0005);
3253         rtl_writephy(tp, 0x05, 0x8b86);
3254         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3255         rtl_writephy(tp, 0x1f, 0x0000);
3256
3257         /* Improve 2-pair detection performance */
3258         rtl_writephy(tp, 0x1f, 0x0005);
3259         rtl_writephy(tp, 0x05, 0x8b85);
3260         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3261         rtl_writephy(tp, 0x1f, 0x0000);
3262
3263         rtl8168f_config_eee_phy(tp);
3264         rtl_enable_eee(tp);
3265
3266         /* Green feature */
3267         rtl_writephy(tp, 0x1f, 0x0003);
3268         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3269         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3270         rtl_writephy(tp, 0x1f, 0x0000);
3271         rtl_writephy(tp, 0x1f, 0x0005);
3272         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3273         rtl_writephy(tp, 0x1f, 0x0000);
3274
3275         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3276         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3277 }
3278
3279 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3280 {
3281         /* For 4-corner performance improve */
3282         rtl_writephy(tp, 0x1f, 0x0005);
3283         rtl_writephy(tp, 0x05, 0x8b80);
3284         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3285         rtl_writephy(tp, 0x1f, 0x0000);
3286
3287         /* PHY auto speed down */
3288         rtl_writephy(tp, 0x1f, 0x0007);
3289         rtl_writephy(tp, 0x1e, 0x002d);
3290         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3291         rtl_writephy(tp, 0x1f, 0x0000);
3292         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3293
3294         /* Improve 10M EEE waveform */
3295         rtl_writephy(tp, 0x1f, 0x0005);
3296         rtl_writephy(tp, 0x05, 0x8b86);
3297         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3298         rtl_writephy(tp, 0x1f, 0x0000);
3299
3300         rtl8168f_config_eee_phy(tp);
3301         rtl_enable_eee(tp);
3302 }
3303
3304 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3305 {
3306         static const struct phy_reg phy_reg_init[] = {
3307                 /* Channel estimation fine tune */
3308                 { 0x1f, 0x0003 },
3309                 { 0x09, 0xa20f },
3310                 { 0x1f, 0x0000 },
3311
3312                 /* Modify green table for giga & fnet */
3313                 { 0x1f, 0x0005 },
3314                 { 0x05, 0x8b55 },
3315                 { 0x06, 0x0000 },
3316                 { 0x05, 0x8b5e },
3317                 { 0x06, 0x0000 },
3318                 { 0x05, 0x8b67 },
3319                 { 0x06, 0x0000 },
3320                 { 0x05, 0x8b70 },
3321                 { 0x06, 0x0000 },
3322                 { 0x1f, 0x0000 },
3323                 { 0x1f, 0x0007 },
3324                 { 0x1e, 0x0078 },
3325                 { 0x17, 0x0000 },
3326                 { 0x19, 0x00fb },
3327                 { 0x1f, 0x0000 },
3328
3329                 /* Modify green table for 10M */
3330                 { 0x1f, 0x0005 },
3331                 { 0x05, 0x8b79 },
3332                 { 0x06, 0xaa00 },
3333                 { 0x1f, 0x0000 },
3334
3335                 /* Disable hiimpedance detection (RTCT) */
3336                 { 0x1f, 0x0003 },
3337                 { 0x01, 0x328a },
3338                 { 0x1f, 0x0000 }
3339         };
3340
3341         rtl_apply_firmware(tp);
3342
3343         rtl_writephy_batch(tp, phy_reg_init);
3344
3345         rtl8168f_hw_phy_config(tp);
3346
3347         /* Improve 2-pair detection performance */
3348         rtl_writephy(tp, 0x1f, 0x0005);
3349         rtl_writephy(tp, 0x05, 0x8b85);
3350         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3351         rtl_writephy(tp, 0x1f, 0x0000);
3352 }
3353
3354 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3355 {
3356         rtl_apply_firmware(tp);
3357
3358         rtl8168f_hw_phy_config(tp);
3359 }
3360
3361 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3362 {
3363         static const struct phy_reg phy_reg_init[] = {
3364                 /* Channel estimation fine tune */
3365                 { 0x1f, 0x0003 },
3366                 { 0x09, 0xa20f },
3367                 { 0x1f, 0x0000 },
3368
3369                 /* Modify green table for giga & fnet */
3370                 { 0x1f, 0x0005 },
3371                 { 0x05, 0x8b55 },
3372                 { 0x06, 0x0000 },
3373                 { 0x05, 0x8b5e },
3374                 { 0x06, 0x0000 },
3375                 { 0x05, 0x8b67 },
3376                 { 0x06, 0x0000 },
3377                 { 0x05, 0x8b70 },
3378                 { 0x06, 0x0000 },
3379                 { 0x1f, 0x0000 },
3380                 { 0x1f, 0x0007 },
3381                 { 0x1e, 0x0078 },
3382                 { 0x17, 0x0000 },
3383                 { 0x19, 0x00aa },
3384                 { 0x1f, 0x0000 },
3385
3386                 /* Modify green table for 10M */
3387                 { 0x1f, 0x0005 },
3388                 { 0x05, 0x8b79 },
3389                 { 0x06, 0xaa00 },
3390                 { 0x1f, 0x0000 },
3391
3392                 /* Disable hiimpedance detection (RTCT) */
3393                 { 0x1f, 0x0003 },
3394                 { 0x01, 0x328a },
3395                 { 0x1f, 0x0000 }
3396         };
3397
3398
3399         rtl_apply_firmware(tp);
3400
3401         rtl8168f_hw_phy_config(tp);
3402
3403         /* Improve 2-pair detection performance */
3404         rtl_writephy(tp, 0x1f, 0x0005);
3405         rtl_writephy(tp, 0x05, 0x8b85);
3406         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3407         rtl_writephy(tp, 0x1f, 0x0000);
3408
3409         rtl_writephy_batch(tp, phy_reg_init);
3410
3411         /* Modify green table for giga */
3412         rtl_writephy(tp, 0x1f, 0x0005);
3413         rtl_writephy(tp, 0x05, 0x8b54);
3414         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3415         rtl_writephy(tp, 0x05, 0x8b5d);
3416         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3417         rtl_writephy(tp, 0x05, 0x8a7c);
3418         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3419         rtl_writephy(tp, 0x05, 0x8a7f);
3420         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3421         rtl_writephy(tp, 0x05, 0x8a82);
3422         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3423         rtl_writephy(tp, 0x05, 0x8a85);
3424         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3425         rtl_writephy(tp, 0x05, 0x8a88);
3426         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3427         rtl_writephy(tp, 0x1f, 0x0000);
3428
3429         /* uc same-seed solution */
3430         rtl_writephy(tp, 0x1f, 0x0005);
3431         rtl_writephy(tp, 0x05, 0x8b85);
3432         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3433         rtl_writephy(tp, 0x1f, 0x0000);
3434
3435         /* Green feature */
3436         rtl_writephy(tp, 0x1f, 0x0003);
3437         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3438         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3439         rtl_writephy(tp, 0x1f, 0x0000);
3440 }
3441
3442 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3443 {
3444         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3445 }
3446
3447 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3448 {
3449         struct phy_device *phydev = tp->phydev;
3450
3451         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3452         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3453         phy_write(phydev, 0x1f, 0x0a43);
3454         phy_write(phydev, 0x13, 0x8084);
3455         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3456         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3457
3458         phy_write(phydev, 0x1f, 0x0000);
3459 }
3460
3461 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3462 {
3463         int ret;
3464
3465         rtl_apply_firmware(tp);
3466
3467         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3468         if (ret & BIT(8))
3469                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3470         else
3471                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3472
3473         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3474         if (ret & BIT(8))
3475                 phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
3476         else
3477                 phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
3478
3479         /* Enable PHY auto speed down */
3480         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3481
3482         rtl8168g_phy_adjust_10m_aldps(tp);
3483
3484         /* EEE auto-fallback function */
3485         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3486
3487         /* Enable UC LPF tune function */
3488         rtl_writephy(tp, 0x1f, 0x0a43);
3489         rtl_writephy(tp, 0x13, 0x8012);
3490         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3491
3492         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3493
3494         /* Improve SWR Efficiency */
3495         rtl_writephy(tp, 0x1f, 0x0bcd);
3496         rtl_writephy(tp, 0x14, 0x5065);
3497         rtl_writephy(tp, 0x14, 0xd065);
3498         rtl_writephy(tp, 0x1f, 0x0bc8);
3499         rtl_writephy(tp, 0x11, 0x5655);
3500         rtl_writephy(tp, 0x1f, 0x0bcd);
3501         rtl_writephy(tp, 0x14, 0x1065);
3502         rtl_writephy(tp, 0x14, 0x9065);
3503         rtl_writephy(tp, 0x14, 0x1065);
3504         rtl_writephy(tp, 0x1f, 0x0000);
3505
3506         rtl8168g_disable_aldps(tp);
3507         rtl8168g_config_eee_phy(tp);
3508         rtl_enable_eee(tp);
3509 }
3510
3511 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3512 {
3513         rtl_apply_firmware(tp);
3514         rtl8168g_config_eee_phy(tp);
3515         rtl_enable_eee(tp);
3516 }
3517
3518 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3519 {
3520         u16 dout_tapbin;
3521         u32 data;
3522
3523         rtl_apply_firmware(tp);
3524
3525         /* CHN EST parameters adjust - giga master */
3526         rtl_writephy(tp, 0x1f, 0x0a43);
3527         rtl_writephy(tp, 0x13, 0x809b);
3528         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3529         rtl_writephy(tp, 0x13, 0x80a2);
3530         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3531         rtl_writephy(tp, 0x13, 0x80a4);
3532         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3533         rtl_writephy(tp, 0x13, 0x809c);
3534         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3535         rtl_writephy(tp, 0x1f, 0x0000);
3536
3537         /* CHN EST parameters adjust - giga slave */
3538         rtl_writephy(tp, 0x1f, 0x0a43);
3539         rtl_writephy(tp, 0x13, 0x80ad);
3540         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3541         rtl_writephy(tp, 0x13, 0x80b4);
3542         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3543         rtl_writephy(tp, 0x13, 0x80ac);
3544         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3545         rtl_writephy(tp, 0x1f, 0x0000);
3546
3547         /* CHN EST parameters adjust - fnet */
3548         rtl_writephy(tp, 0x1f, 0x0a43);
3549         rtl_writephy(tp, 0x13, 0x808e);
3550         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3551         rtl_writephy(tp, 0x13, 0x8090);
3552         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3553         rtl_writephy(tp, 0x13, 0x8092);
3554         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3555         rtl_writephy(tp, 0x1f, 0x0000);
3556
3557         /* enable R-tune & PGA-retune function */
3558         dout_tapbin = 0;
3559         rtl_writephy(tp, 0x1f, 0x0a46);
3560         data = rtl_readphy(tp, 0x13);
3561         data &= 3;
3562         data <<= 2;
3563         dout_tapbin |= data;
3564         data = rtl_readphy(tp, 0x12);
3565         data &= 0xc000;
3566         data >>= 14;
3567         dout_tapbin |= data;
3568         dout_tapbin = ~(dout_tapbin^0x08);
3569         dout_tapbin <<= 12;
3570         dout_tapbin &= 0xf000;
3571         rtl_writephy(tp, 0x1f, 0x0a43);
3572         rtl_writephy(tp, 0x13, 0x827a);
3573         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3574         rtl_writephy(tp, 0x13, 0x827b);
3575         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3576         rtl_writephy(tp, 0x13, 0x827c);
3577         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3578         rtl_writephy(tp, 0x13, 0x827d);
3579         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3580
3581         rtl_writephy(tp, 0x1f, 0x0a43);
3582         rtl_writephy(tp, 0x13, 0x0811);
3583         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3584         rtl_writephy(tp, 0x1f, 0x0a42);
3585         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3586         rtl_writephy(tp, 0x1f, 0x0000);
3587
3588         /* enable GPHY 10M */
3589         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3590
3591         /* SAR ADC performance */
3592         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3593
3594         rtl_writephy(tp, 0x1f, 0x0a43);
3595         rtl_writephy(tp, 0x13, 0x803f);
3596         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3597         rtl_writephy(tp, 0x13, 0x8047);
3598         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3599         rtl_writephy(tp, 0x13, 0x804f);
3600         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3601         rtl_writephy(tp, 0x13, 0x8057);
3602         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3603         rtl_writephy(tp, 0x13, 0x805f);
3604         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3605         rtl_writephy(tp, 0x13, 0x8067);
3606         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3607         rtl_writephy(tp, 0x13, 0x806f);
3608         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3609         rtl_writephy(tp, 0x1f, 0x0000);
3610
3611         /* disable phy pfm mode */
3612         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3613
3614         rtl8168g_disable_aldps(tp);
3615         rtl8168g_config_eee_phy(tp);
3616         rtl_enable_eee(tp);
3617 }
3618
3619 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3620 {
3621         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3622         u16 rlen;
3623         u32 data;
3624
3625         rtl_apply_firmware(tp);
3626
3627         /* CHIN EST parameter update */
3628         rtl_writephy(tp, 0x1f, 0x0a43);
3629         rtl_writephy(tp, 0x13, 0x808a);
3630         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3631         rtl_writephy(tp, 0x1f, 0x0000);
3632
3633         /* enable R-tune & PGA-retune function */
3634         rtl_writephy(tp, 0x1f, 0x0a43);
3635         rtl_writephy(tp, 0x13, 0x0811);
3636         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3637         rtl_writephy(tp, 0x1f, 0x0a42);
3638         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3639         rtl_writephy(tp, 0x1f, 0x0000);
3640
3641         /* enable GPHY 10M */
3642         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3643
3644         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3645         data = r8168_mac_ocp_read(tp, 0xdd02);
3646         ioffset_p3 = ((data & 0x80)>>7);
3647         ioffset_p3 <<= 3;
3648
3649         data = r8168_mac_ocp_read(tp, 0xdd00);
3650         ioffset_p3 |= ((data & (0xe000))>>13);
3651         ioffset_p2 = ((data & (0x1e00))>>9);
3652         ioffset_p1 = ((data & (0x01e0))>>5);
3653         ioffset_p0 = ((data & 0x0010)>>4);
3654         ioffset_p0 <<= 3;
3655         ioffset_p0 |= (data & (0x07));
3656         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3657
3658         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3659             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3660                 rtl_writephy(tp, 0x1f, 0x0bcf);
3661                 rtl_writephy(tp, 0x16, data);
3662                 rtl_writephy(tp, 0x1f, 0x0000);
3663         }
3664
3665         /* Modify rlen (TX LPF corner frequency) level */
3666         rtl_writephy(tp, 0x1f, 0x0bcd);
3667         data = rtl_readphy(tp, 0x16);
3668         data &= 0x000f;
3669         rlen = 0;
3670         if (data > 3)
3671                 rlen = data - 3;
3672         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3673         rtl_writephy(tp, 0x17, data);
3674         rtl_writephy(tp, 0x1f, 0x0bcd);
3675         rtl_writephy(tp, 0x1f, 0x0000);
3676
3677         /* disable phy pfm mode */
3678         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3679
3680         rtl8168g_disable_aldps(tp);
3681         rtl8168g_config_eee_phy(tp);
3682         rtl_enable_eee(tp);
3683 }
3684
3685 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3686 {
3687         /* Enable PHY auto speed down */
3688         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3689
3690         rtl8168g_phy_adjust_10m_aldps(tp);
3691
3692         /* Enable EEE auto-fallback function */
3693         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3694
3695         /* Enable UC LPF tune function */
3696         rtl_writephy(tp, 0x1f, 0x0a43);
3697         rtl_writephy(tp, 0x13, 0x8012);
3698         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3699         rtl_writephy(tp, 0x1f, 0x0000);
3700
3701         /* set rg_sel_sdm_rate */
3702         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3703
3704         rtl8168g_disable_aldps(tp);
3705         rtl8168g_config_eee_phy(tp);
3706         rtl_enable_eee(tp);
3707 }
3708
3709 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3710 {
3711         rtl8168g_phy_adjust_10m_aldps(tp);
3712
3713         /* Enable UC LPF tune function */
3714         rtl_writephy(tp, 0x1f, 0x0a43);
3715         rtl_writephy(tp, 0x13, 0x8012);
3716         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3717         rtl_writephy(tp, 0x1f, 0x0000);
3718
3719         /* Set rg_sel_sdm_rate */
3720         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3721
3722         /* Channel estimation parameters */
3723         rtl_writephy(tp, 0x1f, 0x0a43);
3724         rtl_writephy(tp, 0x13, 0x80f3);
3725         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3726         rtl_writephy(tp, 0x13, 0x80f0);
3727         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3728         rtl_writephy(tp, 0x13, 0x80ef);
3729         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3730         rtl_writephy(tp, 0x13, 0x80f6);
3731         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3732         rtl_writephy(tp, 0x13, 0x80ec);
3733         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3734         rtl_writephy(tp, 0x13, 0x80ed);
3735         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3736         rtl_writephy(tp, 0x13, 0x80f2);
3737         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3738         rtl_writephy(tp, 0x13, 0x80f4);
3739         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3740         rtl_writephy(tp, 0x1f, 0x0a43);
3741         rtl_writephy(tp, 0x13, 0x8110);
3742         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3743         rtl_writephy(tp, 0x13, 0x810f);
3744         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3745         rtl_writephy(tp, 0x13, 0x8111);
3746         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3747         rtl_writephy(tp, 0x13, 0x8113);
3748         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3749         rtl_writephy(tp, 0x13, 0x8115);
3750         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3751         rtl_writephy(tp, 0x13, 0x810e);
3752         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3753         rtl_writephy(tp, 0x13, 0x810c);
3754         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3755         rtl_writephy(tp, 0x13, 0x810b);
3756         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3757         rtl_writephy(tp, 0x1f, 0x0a43);
3758         rtl_writephy(tp, 0x13, 0x80d1);
3759         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3760         rtl_writephy(tp, 0x13, 0x80cd);
3761         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3762         rtl_writephy(tp, 0x13, 0x80d3);
3763         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3764         rtl_writephy(tp, 0x13, 0x80d5);
3765         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3766         rtl_writephy(tp, 0x13, 0x80d7);
3767         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3768
3769         /* Force PWM-mode */
3770         rtl_writephy(tp, 0x1f, 0x0bcd);
3771         rtl_writephy(tp, 0x14, 0x5065);
3772         rtl_writephy(tp, 0x14, 0xd065);
3773         rtl_writephy(tp, 0x1f, 0x0bc8);
3774         rtl_writephy(tp, 0x12, 0x00ed);
3775         rtl_writephy(tp, 0x1f, 0x0bcd);
3776         rtl_writephy(tp, 0x14, 0x1065);
3777         rtl_writephy(tp, 0x14, 0x9065);
3778         rtl_writephy(tp, 0x14, 0x1065);
3779         rtl_writephy(tp, 0x1f, 0x0000);
3780
3781         rtl8168g_disable_aldps(tp);
3782         rtl8168g_config_eee_phy(tp);
3783         rtl_enable_eee(tp);
3784 }
3785
3786 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3787 {
3788         static const struct phy_reg phy_reg_init[] = {
3789                 { 0x1f, 0x0003 },
3790                 { 0x08, 0x441d },
3791                 { 0x01, 0x9100 },
3792                 { 0x1f, 0x0000 }
3793         };
3794
3795         rtl_writephy(tp, 0x1f, 0x0000);
3796         rtl_patchphy(tp, 0x11, 1 << 12);
3797         rtl_patchphy(tp, 0x19, 1 << 13);
3798         rtl_patchphy(tp, 0x10, 1 << 15);
3799
3800         rtl_writephy_batch(tp, phy_reg_init);
3801 }
3802
3803 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3804 {
3805         static const struct phy_reg phy_reg_init[] = {
3806                 { 0x1f, 0x0005 },
3807                 { 0x1a, 0x0000 },
3808                 { 0x1f, 0x0000 },
3809
3810                 { 0x1f, 0x0004 },
3811                 { 0x1c, 0x0000 },
3812                 { 0x1f, 0x0000 },
3813
3814                 { 0x1f, 0x0001 },
3815                 { 0x15, 0x7701 },
3816                 { 0x1f, 0x0000 }
3817         };
3818
3819         /* Disable ALDPS before ram code */
3820         rtl_writephy(tp, 0x1f, 0x0000);
3821         rtl_writephy(tp, 0x18, 0x0310);
3822         msleep(100);
3823
3824         rtl_apply_firmware(tp);
3825
3826         rtl_writephy_batch(tp, phy_reg_init);
3827 }
3828
3829 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3830 {
3831         /* Disable ALDPS before setting firmware */
3832         rtl_writephy(tp, 0x1f, 0x0000);
3833         rtl_writephy(tp, 0x18, 0x0310);
3834         msleep(20);
3835
3836         rtl_apply_firmware(tp);
3837
3838         /* EEE setting */
3839         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3840         rtl_writephy(tp, 0x1f, 0x0004);
3841         rtl_writephy(tp, 0x10, 0x401f);
3842         rtl_writephy(tp, 0x19, 0x7030);
3843         rtl_writephy(tp, 0x1f, 0x0000);
3844 }
3845
3846 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3847 {
3848         static const struct phy_reg phy_reg_init[] = {
3849                 { 0x1f, 0x0004 },
3850                 { 0x10, 0xc07f },
3851                 { 0x19, 0x7030 },
3852                 { 0x1f, 0x0000 }
3853         };
3854
3855         /* Disable ALDPS before ram code */
3856         rtl_writephy(tp, 0x1f, 0x0000);
3857         rtl_writephy(tp, 0x18, 0x0310);
3858         msleep(100);
3859
3860         rtl_apply_firmware(tp);
3861
3862         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3863         rtl_writephy_batch(tp, phy_reg_init);
3864
3865         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3866 }
3867
3868 static void rtl_hw_phy_config(struct net_device *dev)
3869 {
3870         static const rtl_generic_fct phy_configs[] = {
3871                 /* PCI devices. */
3872                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3873                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3874                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3875                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3876                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3877                 /* PCI-E devices. */
3878                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3879                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3880                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3881                 [RTL_GIGA_MAC_VER_10] = NULL,
3882                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3883                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3884                 [RTL_GIGA_MAC_VER_13] = NULL,
3885                 [RTL_GIGA_MAC_VER_14] = NULL,
3886                 [RTL_GIGA_MAC_VER_15] = NULL,
3887                 [RTL_GIGA_MAC_VER_16] = NULL,
3888                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3889                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3890                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3891                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3892                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3893                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3894                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3895                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3896                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3897                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3898                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3899                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3900                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3901                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3902                 [RTL_GIGA_MAC_VER_31] = NULL,
3903                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3904                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3905                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3906                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3907                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3908                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3909                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3910                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3911                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3912                 [RTL_GIGA_MAC_VER_41] = NULL,
3913                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3914                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3915                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3916                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3917                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3918                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3919                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3920                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3921                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3922                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3923         };
3924         struct rtl8169_private *tp = netdev_priv(dev);
3925
3926         if (phy_configs[tp->mac_version])
3927                 phy_configs[tp->mac_version](tp);
3928 }
3929
3930 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3931 {
3932         if (!test_and_set_bit(flag, tp->wk.flags))
3933                 schedule_work(&tp->wk.work);
3934 }
3935
3936 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3937 {
3938         rtl_hw_phy_config(dev);
3939
3940         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3941                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3942                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3943                 netif_dbg(tp, drv, dev,
3944                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3945                 RTL_W8(tp, 0x82, 0x01);
3946         }
3947
3948         /* We may have called phy_speed_down before */
3949         phy_speed_up(tp->phydev);
3950
3951         genphy_soft_reset(tp->phydev);
3952 }
3953
3954 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3955 {
3956         rtl_lock_work(tp);
3957
3958         rtl_unlock_config_regs(tp);
3959
3960         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3961         RTL_R32(tp, MAC4);
3962
3963         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3964         RTL_R32(tp, MAC0);
3965
3966         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3967                 rtl_rar_exgmac_set(tp, addr);
3968
3969         rtl_lock_config_regs(tp);
3970
3971         rtl_unlock_work(tp);
3972 }
3973
3974 static int rtl_set_mac_address(struct net_device *dev, void *p)
3975 {
3976         struct rtl8169_private *tp = netdev_priv(dev);
3977         struct device *d = tp_to_dev(tp);
3978         int ret;
3979
3980         ret = eth_mac_addr(dev, p);
3981         if (ret)
3982                 return ret;
3983
3984         pm_runtime_get_noresume(d);
3985
3986         if (pm_runtime_active(d))
3987                 rtl_rar_set(tp, dev->dev_addr);
3988
3989         pm_runtime_put_noidle(d);
3990
3991         return 0;
3992 }
3993
3994 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3995 {
3996         struct rtl8169_private *tp = netdev_priv(dev);
3997
3998         if (!netif_running(dev))
3999                 return -ENODEV;
4000
4001         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4002 }
4003
4004 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4005 {
4006         switch (tp->mac_version) {
4007         case RTL_GIGA_MAC_VER_25:
4008         case RTL_GIGA_MAC_VER_26:
4009         case RTL_GIGA_MAC_VER_29:
4010         case RTL_GIGA_MAC_VER_30:
4011         case RTL_GIGA_MAC_VER_32:
4012         case RTL_GIGA_MAC_VER_33:
4013         case RTL_GIGA_MAC_VER_34:
4014         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4015                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4016                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4017                 break;
4018         default:
4019                 break;
4020         }
4021 }
4022
4023 static void rtl_pll_power_down(struct rtl8169_private *tp)
4024 {
4025         if (r8168_check_dash(tp))
4026                 return;
4027
4028         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4029             tp->mac_version == RTL_GIGA_MAC_VER_33)
4030                 rtl_ephy_write(tp, 0x19, 0xff64);
4031
4032         if (device_may_wakeup(tp_to_dev(tp))) {
4033                 phy_speed_down(tp->phydev, false);
4034                 rtl_wol_suspend_quirk(tp);
4035                 return;
4036         }
4037
4038         switch (tp->mac_version) {
4039         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4040         case RTL_GIGA_MAC_VER_37:
4041         case RTL_GIGA_MAC_VER_39:
4042         case RTL_GIGA_MAC_VER_43:
4043         case RTL_GIGA_MAC_VER_44:
4044         case RTL_GIGA_MAC_VER_45:
4045         case RTL_GIGA_MAC_VER_46:
4046         case RTL_GIGA_MAC_VER_47:
4047         case RTL_GIGA_MAC_VER_48:
4048         case RTL_GIGA_MAC_VER_50:
4049         case RTL_GIGA_MAC_VER_51:
4050                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4051                 break;
4052         case RTL_GIGA_MAC_VER_40:
4053         case RTL_GIGA_MAC_VER_41:
4054         case RTL_GIGA_MAC_VER_49:
4055                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4056                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4057                 break;
4058         default:
4059                 break;
4060         }
4061 }
4062
4063 static void rtl_pll_power_up(struct rtl8169_private *tp)
4064 {
4065         switch (tp->mac_version) {
4066         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4067         case RTL_GIGA_MAC_VER_37:
4068         case RTL_GIGA_MAC_VER_39:
4069         case RTL_GIGA_MAC_VER_43:
4070                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4071                 break;
4072         case RTL_GIGA_MAC_VER_44:
4073         case RTL_GIGA_MAC_VER_45:
4074         case RTL_GIGA_MAC_VER_46:
4075         case RTL_GIGA_MAC_VER_47:
4076         case RTL_GIGA_MAC_VER_48:
4077         case RTL_GIGA_MAC_VER_50:
4078         case RTL_GIGA_MAC_VER_51:
4079                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4080                 break;
4081         case RTL_GIGA_MAC_VER_40:
4082         case RTL_GIGA_MAC_VER_41:
4083         case RTL_GIGA_MAC_VER_49:
4084                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4085                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4086                 break;
4087         default:
4088                 break;
4089         }
4090
4091         phy_resume(tp->phydev);
4092         /* give MAC/PHY some time to resume */
4093         msleep(20);
4094 }
4095
4096 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4097 {
4098         switch (tp->mac_version) {
4099         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4100         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4101                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4102                 break;
4103         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4104         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4105         case RTL_GIGA_MAC_VER_38:
4106                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4107                 break;
4108         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4109                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4110                 break;
4111         default:
4112                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4113                 break;
4114         }
4115 }
4116
4117 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4118 {
4119         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4120 }
4121
4122 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4123 {
4124         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4125         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4126         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4127 }
4128
4129 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4130 {
4131         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4132         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4133         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4134 }
4135
4136 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4137 {
4138         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4139 }
4140
4141 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4142 {
4143         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4144 }
4145
4146 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4147 {
4148         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4149         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4150         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4151         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4152 }
4153
4154 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4155 {
4156         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4157         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4158         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4159         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4160 }
4161
4162 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4163 {
4164         rtl_tx_performance_tweak(tp,
4165                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4166 }
4167
4168 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4169 {
4170         rtl_tx_performance_tweak(tp,
4171                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4172 }
4173
4174 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4175 {
4176         r8168b_0_hw_jumbo_enable(tp);
4177
4178         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4179 }
4180
4181 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4182 {
4183         r8168b_0_hw_jumbo_disable(tp);
4184
4185         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4186 }
4187
4188 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4189 {
4190         rtl_unlock_config_regs(tp);
4191         switch (tp->mac_version) {
4192         case RTL_GIGA_MAC_VER_11:
4193                 r8168b_0_hw_jumbo_enable(tp);
4194                 break;
4195         case RTL_GIGA_MAC_VER_12:
4196         case RTL_GIGA_MAC_VER_17:
4197                 r8168b_1_hw_jumbo_enable(tp);
4198                 break;
4199         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4200                 r8168c_hw_jumbo_enable(tp);
4201                 break;
4202         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4203                 r8168dp_hw_jumbo_enable(tp);
4204                 break;
4205         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4206                 r8168e_hw_jumbo_enable(tp);
4207                 break;
4208         default:
4209                 break;
4210         }
4211         rtl_lock_config_regs(tp);
4212 }
4213
4214 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4215 {
4216         rtl_unlock_config_regs(tp);
4217         switch (tp->mac_version) {
4218         case RTL_GIGA_MAC_VER_11:
4219                 r8168b_0_hw_jumbo_disable(tp);
4220                 break;
4221         case RTL_GIGA_MAC_VER_12:
4222         case RTL_GIGA_MAC_VER_17:
4223                 r8168b_1_hw_jumbo_disable(tp);
4224                 break;
4225         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4226                 r8168c_hw_jumbo_disable(tp);
4227                 break;
4228         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4229                 r8168dp_hw_jumbo_disable(tp);
4230                 break;
4231         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4232                 r8168e_hw_jumbo_disable(tp);
4233                 break;
4234         default:
4235                 break;
4236         }
4237         rtl_lock_config_regs(tp);
4238 }
4239
4240 DECLARE_RTL_COND(rtl_chipcmd_cond)
4241 {
4242         return RTL_R8(tp, ChipCmd) & CmdReset;
4243 }
4244
4245 static void rtl_hw_reset(struct rtl8169_private *tp)
4246 {
4247         RTL_W8(tp, ChipCmd, CmdReset);
4248
4249         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4250 }
4251
4252 static void rtl_request_firmware(struct rtl8169_private *tp)
4253 {
4254         struct rtl_fw *rtl_fw;
4255         int rc = -ENOMEM;
4256
4257         /* firmware loaded already or no firmware available */
4258         if (tp->rtl_fw || !tp->fw_name)
4259                 return;
4260
4261         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4262         if (!rtl_fw)
4263                 goto err_warn;
4264
4265         rtl_fw->phy_write = rtl_writephy;
4266         rtl_fw->phy_read = rtl_readphy;
4267         rtl_fw->mac_mcu_write = mac_mcu_write;
4268         rtl_fw->mac_mcu_read = mac_mcu_read;
4269         rtl_fw->fw_name = tp->fw_name;
4270         rtl_fw->dev = tp_to_dev(tp);
4271
4272         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4273         if (rc < 0)
4274                 goto err_free;
4275
4276         if (!rtl_fw_format_ok(rtl_fw) || !rtl_fw_data_ok(rtl_fw)) {
4277                 dev_err(rtl_fw->dev, "invalid firmware\n");
4278                 goto err_release_firmware;
4279         }
4280
4281         tp->rtl_fw = rtl_fw;
4282
4283         return;
4284
4285 err_release_firmware:
4286         release_firmware(rtl_fw->fw);
4287 err_free:
4288         kfree(rtl_fw);
4289 err_warn:
4290         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4291                    tp->fw_name, rc);
4292 }
4293
4294 static void rtl_rx_close(struct rtl8169_private *tp)
4295 {
4296         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4297 }
4298
4299 DECLARE_RTL_COND(rtl_npq_cond)
4300 {
4301         return RTL_R8(tp, TxPoll) & NPQ;
4302 }
4303
4304 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4305 {
4306         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4307 }
4308
4309 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4310 {
4311         /* Disable interrupts */
4312         rtl8169_irq_mask_and_ack(tp);
4313
4314         rtl_rx_close(tp);
4315
4316         switch (tp->mac_version) {
4317         case RTL_GIGA_MAC_VER_27:
4318         case RTL_GIGA_MAC_VER_28:
4319         case RTL_GIGA_MAC_VER_31:
4320                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4321                 break;
4322         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4323         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4324                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4325                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4326                 break;
4327         default:
4328                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4329                 udelay(100);
4330                 break;
4331         }
4332
4333         rtl_hw_reset(tp);
4334 }
4335
4336 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4337 {
4338         u32 val = TX_DMA_BURST << TxDMAShift |
4339                   InterFrameGap << TxInterFrameGapShift;
4340
4341         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4342             tp->mac_version != RTL_GIGA_MAC_VER_39)
4343                 val |= TXCFG_AUTO_FIFO;
4344
4345         RTL_W32(tp, TxConfig, val);
4346 }
4347
4348 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4349 {
4350         /* Low hurts. Let's disable the filtering. */
4351         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4352 }
4353
4354 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4355 {
4356         /*
4357          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4358          * register to be written before TxDescAddrLow to work.
4359          * Switching from MMIO to I/O access fixes the issue as well.
4360          */
4361         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4362         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4363         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4364         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4365 }
4366
4367 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4368 {
4369         u32 val;
4370
4371         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4372                 val = 0x000fff00;
4373         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4374                 val = 0x00ffff00;
4375         else
4376                 return;
4377
4378         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4379                 val |= 0xff;
4380
4381         RTL_W32(tp, 0x7c, val);
4382 }
4383
4384 static void rtl_set_rx_mode(struct net_device *dev)
4385 {
4386         struct rtl8169_private *tp = netdev_priv(dev);
4387         u32 mc_filter[2];       /* Multicast hash filter */
4388         int rx_mode;
4389         u32 tmp = 0;
4390
4391         if (dev->flags & IFF_PROMISC) {
4392                 /* Unconditionally log net taps. */
4393                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4394                 rx_mode =
4395                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4396                     AcceptAllPhys;
4397                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4398         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4399                    (dev->flags & IFF_ALLMULTI)) {
4400                 /* Too many to filter perfectly -- accept all multicasts. */
4401                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4402                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4403         } else {
4404                 struct netdev_hw_addr *ha;
4405
4406                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4407                 mc_filter[1] = mc_filter[0] = 0;
4408                 netdev_for_each_mc_addr(ha, dev) {
4409                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4410                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4411                         rx_mode |= AcceptMulticast;
4412                 }
4413         }
4414
4415         if (dev->features & NETIF_F_RXALL)
4416                 rx_mode |= (AcceptErr | AcceptRunt);
4417
4418         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4419
4420         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4421                 u32 data = mc_filter[0];
4422
4423                 mc_filter[0] = swab32(mc_filter[1]);
4424                 mc_filter[1] = swab32(data);
4425         }
4426
4427         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4428                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4429
4430         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4431         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4432
4433         RTL_W32(tp, RxConfig, tmp);
4434 }
4435
4436 static void rtl_hw_start(struct  rtl8169_private *tp)
4437 {
4438         rtl_unlock_config_regs(tp);
4439
4440         tp->hw_start(tp);
4441
4442         rtl_set_rx_max_size(tp);
4443         rtl_set_rx_tx_desc_registers(tp);
4444         rtl_lock_config_regs(tp);
4445
4446         /* disable interrupt coalescing */
4447         RTL_W16(tp, IntrMitigate, 0x0000);
4448         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4449         RTL_R8(tp, IntrMask);
4450         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4451         rtl_init_rxcfg(tp);
4452         rtl_set_tx_config_registers(tp);
4453
4454         rtl_set_rx_mode(tp->dev);
4455         /* no early-rx interrupts */
4456         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4457         rtl_irq_enable(tp);
4458 }
4459
4460 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4461 {
4462         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4463                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4464
4465         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4466
4467         tp->cp_cmd |= PCIMulRW;
4468
4469         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4470             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4471                 netif_dbg(tp, drv, tp->dev,
4472                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4473                 tp->cp_cmd |= (1 << 14);
4474         }
4475
4476         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4477
4478         rtl8169_set_magic_reg(tp, tp->mac_version);
4479
4480         RTL_W32(tp, RxMissed, 0);
4481 }
4482
4483 DECLARE_RTL_COND(rtl_csiar_cond)
4484 {
4485         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4486 }
4487
4488 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4489 {
4490         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4491
4492         RTL_W32(tp, CSIDR, value);
4493         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4494                 CSIAR_BYTE_ENABLE | func << 16);
4495
4496         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4497 }
4498
4499 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4500 {
4501         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4502
4503         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4504                 CSIAR_BYTE_ENABLE);
4505
4506         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4507                 RTL_R32(tp, CSIDR) : ~0;
4508 }
4509
4510 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4511 {
4512         struct pci_dev *pdev = tp->pci_dev;
4513         u32 csi;
4514
4515         /* According to Realtek the value at config space address 0x070f
4516          * controls the L0s/L1 entrance latency. We try standard ECAM access
4517          * first and if it fails fall back to CSI.
4518          */
4519         if (pdev->cfg_size > 0x070f &&
4520             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4521                 return;
4522
4523         netdev_notice_once(tp->dev,
4524                 "No native access to PCI extended config space, falling back to CSI\n");
4525         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4526         rtl_csi_write(tp, 0x070c, csi | val << 24);
4527 }
4528
4529 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4530 {
4531         rtl_csi_access_enable(tp, 0x27);
4532 }
4533
4534 struct ephy_info {
4535         unsigned int offset;
4536         u16 mask;
4537         u16 bits;
4538 };
4539
4540 static void __rtl_ephy_init(struct rtl8169_private *tp,
4541                             const struct ephy_info *e, int len)
4542 {
4543         u16 w;
4544
4545         while (len-- > 0) {
4546                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4547                 rtl_ephy_write(tp, e->offset, w);
4548                 e++;
4549         }
4550 }
4551
4552 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4553
4554 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4555 {
4556         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4557                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4558 }
4559
4560 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4561 {
4562         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4563                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4564 }
4565
4566 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4567 {
4568         /* work around an issue when PCI reset occurs during L2/L3 state */
4569         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4570 }
4571
4572 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4573 {
4574         if (enable) {
4575                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4576                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4577         } else {
4578                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4579                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4580         }
4581
4582         udelay(10);
4583 }
4584
4585 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4586                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4587 {
4588         /* Usage of dynamic vs. static FIFO is controlled by bit
4589          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4590          */
4591         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4592         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4593 }
4594
4595 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4596                                           u8 low, u8 high)
4597 {
4598         /* FIFO thresholds for pause flow control */
4599         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4600         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4601 }
4602
4603 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4604 {
4605         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4606
4607         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4608         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4609
4610         if (tp->dev->mtu <= ETH_DATA_LEN) {
4611                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4612                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4613         }
4614 }
4615
4616 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4617 {
4618         rtl_hw_start_8168bb(tp);
4619
4620         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4621
4622         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4623 }
4624
4625 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4626 {
4627         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4628
4629         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4630
4631         if (tp->dev->mtu <= ETH_DATA_LEN)
4632                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4633
4634         rtl_disable_clock_request(tp);
4635
4636         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4637         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4638 }
4639
4640 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4641 {
4642         static const struct ephy_info e_info_8168cp[] = {
4643                 { 0x01, 0,      0x0001 },
4644                 { 0x02, 0x0800, 0x1000 },
4645                 { 0x03, 0,      0x0042 },
4646                 { 0x06, 0x0080, 0x0000 },
4647                 { 0x07, 0,      0x2000 }
4648         };
4649
4650         rtl_set_def_aspm_entry_latency(tp);
4651
4652         rtl_ephy_init(tp, e_info_8168cp);
4653
4654         __rtl_hw_start_8168cp(tp);
4655 }
4656
4657 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4658 {
4659         rtl_set_def_aspm_entry_latency(tp);
4660
4661         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4662
4663         if (tp->dev->mtu <= ETH_DATA_LEN)
4664                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4665
4666         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4667         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4668 }
4669
4670 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4671 {
4672         rtl_set_def_aspm_entry_latency(tp);
4673
4674         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4675
4676         /* Magic. */
4677         RTL_W8(tp, DBG_REG, 0x20);
4678
4679         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4680
4681         if (tp->dev->mtu <= ETH_DATA_LEN)
4682                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4683
4684         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4685         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4686 }
4687
4688 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4689 {
4690         static const struct ephy_info e_info_8168c_1[] = {
4691                 { 0x02, 0x0800, 0x1000 },
4692                 { 0x03, 0,      0x0002 },
4693                 { 0x06, 0x0080, 0x0000 }
4694         };
4695
4696         rtl_set_def_aspm_entry_latency(tp);
4697
4698         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4699
4700         rtl_ephy_init(tp, e_info_8168c_1);
4701
4702         __rtl_hw_start_8168cp(tp);
4703 }
4704
4705 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4706 {
4707         static const struct ephy_info e_info_8168c_2[] = {
4708                 { 0x01, 0,      0x0001 },
4709                 { 0x03, 0x0400, 0x0220 }
4710         };
4711
4712         rtl_set_def_aspm_entry_latency(tp);
4713
4714         rtl_ephy_init(tp, e_info_8168c_2);
4715
4716         __rtl_hw_start_8168cp(tp);
4717 }
4718
4719 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4720 {
4721         rtl_hw_start_8168c_2(tp);
4722 }
4723
4724 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4725 {
4726         rtl_set_def_aspm_entry_latency(tp);
4727
4728         __rtl_hw_start_8168cp(tp);
4729 }
4730
4731 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4732 {
4733         rtl_set_def_aspm_entry_latency(tp);
4734
4735         rtl_disable_clock_request(tp);
4736
4737         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4738
4739         if (tp->dev->mtu <= ETH_DATA_LEN)
4740                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4741
4742         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4743         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4744 }
4745
4746 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4747 {
4748         rtl_set_def_aspm_entry_latency(tp);
4749
4750         if (tp->dev->mtu <= ETH_DATA_LEN)
4751                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4752
4753         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4754
4755         rtl_disable_clock_request(tp);
4756 }
4757
4758 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4759 {
4760         static const struct ephy_info e_info_8168d_4[] = {
4761                 { 0x0b, 0x0000, 0x0048 },
4762                 { 0x19, 0x0020, 0x0050 },
4763                 { 0x0c, 0x0100, 0x0020 }
4764         };
4765
4766         rtl_set_def_aspm_entry_latency(tp);
4767
4768         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4769
4770         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4771
4772         rtl_ephy_init(tp, e_info_8168d_4);
4773
4774         rtl_enable_clock_request(tp);
4775 }
4776
4777 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4778 {
4779         static const struct ephy_info e_info_8168e_1[] = {
4780                 { 0x00, 0x0200, 0x0100 },
4781                 { 0x00, 0x0000, 0x0004 },
4782                 { 0x06, 0x0002, 0x0001 },
4783                 { 0x06, 0x0000, 0x0030 },
4784                 { 0x07, 0x0000, 0x2000 },
4785                 { 0x00, 0x0000, 0x0020 },
4786                 { 0x03, 0x5800, 0x2000 },
4787                 { 0x03, 0x0000, 0x0001 },
4788                 { 0x01, 0x0800, 0x1000 },
4789                 { 0x07, 0x0000, 0x4000 },
4790                 { 0x1e, 0x0000, 0x2000 },
4791                 { 0x19, 0xffff, 0xfe6c },
4792                 { 0x0a, 0x0000, 0x0040 }
4793         };
4794
4795         rtl_set_def_aspm_entry_latency(tp);
4796
4797         rtl_ephy_init(tp, e_info_8168e_1);
4798
4799         if (tp->dev->mtu <= ETH_DATA_LEN)
4800                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4801
4802         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4803
4804         rtl_disable_clock_request(tp);
4805
4806         /* Reset tx FIFO pointer */
4807         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4808         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4809
4810         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4811 }
4812
4813 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4814 {
4815         static const struct ephy_info e_info_8168e_2[] = {
4816                 { 0x09, 0x0000, 0x0080 },
4817                 { 0x19, 0x0000, 0x0224 }
4818         };
4819
4820         rtl_set_def_aspm_entry_latency(tp);
4821
4822         rtl_ephy_init(tp, e_info_8168e_2);
4823
4824         if (tp->dev->mtu <= ETH_DATA_LEN)
4825                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4826
4827         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4828         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4829         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4830         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4831         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4832         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4833         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4834
4835         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4836
4837         rtl_disable_clock_request(tp);
4838
4839         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4840
4841         rtl8168_config_eee_mac(tp);
4842
4843         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4844         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4845         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4846
4847         rtl_hw_aspm_clkreq_enable(tp, true);
4848 }
4849
4850 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4851 {
4852         rtl_set_def_aspm_entry_latency(tp);
4853
4854         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4855
4856         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4857         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4858         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4859         rtl_reset_packet_filter(tp);
4860         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4861         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4862         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4863         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4864
4865         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4866
4867         rtl_disable_clock_request(tp);
4868
4869         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4870         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4871         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4872         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4873
4874         rtl8168_config_eee_mac(tp);
4875 }
4876
4877 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4878 {
4879         static const struct ephy_info e_info_8168f_1[] = {
4880                 { 0x06, 0x00c0, 0x0020 },
4881                 { 0x08, 0x0001, 0x0002 },
4882                 { 0x09, 0x0000, 0x0080 },
4883                 { 0x19, 0x0000, 0x0224 }
4884         };
4885
4886         rtl_hw_start_8168f(tp);
4887
4888         rtl_ephy_init(tp, e_info_8168f_1);
4889
4890         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4891 }
4892
4893 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4894 {
4895         static const struct ephy_info e_info_8168f_1[] = {
4896                 { 0x06, 0x00c0, 0x0020 },
4897                 { 0x0f, 0xffff, 0x5200 },
4898                 { 0x1e, 0x0000, 0x4000 },
4899                 { 0x19, 0x0000, 0x0224 }
4900         };
4901
4902         rtl_hw_start_8168f(tp);
4903         rtl_pcie_state_l2l3_disable(tp);
4904
4905         rtl_ephy_init(tp, e_info_8168f_1);
4906
4907         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4908 }
4909
4910 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4911 {
4912         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4913         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4914
4915         rtl_set_def_aspm_entry_latency(tp);
4916
4917         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4918
4919         rtl_reset_packet_filter(tp);
4920         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4921
4922         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4923         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4924
4925         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4926         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4927
4928         rtl8168_config_eee_mac(tp);
4929
4930         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4931         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4932
4933         rtl_pcie_state_l2l3_disable(tp);
4934 }
4935
4936 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4937 {
4938         static const struct ephy_info e_info_8168g_1[] = {
4939                 { 0x00, 0x0000, 0x0008 },
4940                 { 0x0c, 0x37d0, 0x0820 },
4941                 { 0x1e, 0x0000, 0x0001 },
4942                 { 0x19, 0x8000, 0x0000 }
4943         };
4944
4945         rtl_hw_start_8168g(tp);
4946
4947         /* disable aspm and clock request before access ephy */
4948         rtl_hw_aspm_clkreq_enable(tp, false);
4949         rtl_ephy_init(tp, e_info_8168g_1);
4950         rtl_hw_aspm_clkreq_enable(tp, true);
4951 }
4952
4953 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4954 {
4955         static const struct ephy_info e_info_8168g_2[] = {
4956                 { 0x00, 0x0000, 0x0008 },
4957                 { 0x0c, 0x3df0, 0x0200 },
4958                 { 0x19, 0xffff, 0xfc00 },
4959                 { 0x1e, 0xffff, 0x20eb }
4960         };
4961
4962         rtl_hw_start_8168g(tp);
4963
4964         /* disable aspm and clock request before access ephy */
4965         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4966         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4967         rtl_ephy_init(tp, e_info_8168g_2);
4968 }
4969
4970 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4971 {
4972         static const struct ephy_info e_info_8411_2[] = {
4973                 { 0x00, 0x0000, 0x0008 },
4974                 { 0x0c, 0x3df0, 0x0200 },
4975                 { 0x0f, 0xffff, 0x5200 },
4976                 { 0x19, 0x0020, 0x0000 },
4977                 { 0x1e, 0x0000, 0x2000 }
4978         };
4979
4980         rtl_hw_start_8168g(tp);
4981
4982         /* disable aspm and clock request before access ephy */
4983         rtl_hw_aspm_clkreq_enable(tp, false);
4984         rtl_ephy_init(tp, e_info_8411_2);
4985         rtl_hw_aspm_clkreq_enable(tp, true);
4986 }
4987
4988 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4989 {
4990         int rg_saw_cnt;
4991         u32 data;
4992         static const struct ephy_info e_info_8168h_1[] = {
4993                 { 0x1e, 0x0800, 0x0001 },
4994                 { 0x1d, 0x0000, 0x0800 },
4995                 { 0x05, 0xffff, 0x2089 },
4996                 { 0x06, 0xffff, 0x5881 },
4997                 { 0x04, 0xffff, 0x154a },
4998                 { 0x01, 0xffff, 0x068b }
4999         };
5000
5001         /* disable aspm and clock request before access ephy */
5002         rtl_hw_aspm_clkreq_enable(tp, false);
5003         rtl_ephy_init(tp, e_info_8168h_1);
5004
5005         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5006         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5007
5008         rtl_set_def_aspm_entry_latency(tp);
5009
5010         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5011
5012         rtl_reset_packet_filter(tp);
5013
5014         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5015
5016         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5017
5018         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5019
5020         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5021         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5022
5023         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5024         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5025
5026         rtl8168_config_eee_mac(tp);
5027
5028         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5029         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5030
5031         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5032
5033         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5034
5035         rtl_pcie_state_l2l3_disable(tp);
5036
5037         rtl_writephy(tp, 0x1f, 0x0c42);
5038         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5039         rtl_writephy(tp, 0x1f, 0x0000);
5040         if (rg_saw_cnt > 0) {
5041                 u16 sw_cnt_1ms_ini;
5042
5043                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5044                 sw_cnt_1ms_ini &= 0x0fff;
5045                 data = r8168_mac_ocp_read(tp, 0xd412);
5046                 data &= ~0x0fff;
5047                 data |= sw_cnt_1ms_ini;
5048                 r8168_mac_ocp_write(tp, 0xd412, data);
5049         }
5050
5051         data = r8168_mac_ocp_read(tp, 0xe056);
5052         data &= ~0xf0;
5053         data |= 0x70;
5054         r8168_mac_ocp_write(tp, 0xe056, data);
5055
5056         data = r8168_mac_ocp_read(tp, 0xe052);
5057         data &= ~0x6000;
5058         data |= 0x8008;
5059         r8168_mac_ocp_write(tp, 0xe052, data);
5060
5061         data = r8168_mac_ocp_read(tp, 0xe0d6);
5062         data &= ~0x01ff;
5063         data |= 0x017f;
5064         r8168_mac_ocp_write(tp, 0xe0d6, data);
5065
5066         data = r8168_mac_ocp_read(tp, 0xd420);
5067         data &= ~0x0fff;
5068         data |= 0x047f;
5069         r8168_mac_ocp_write(tp, 0xd420, data);
5070
5071         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5072         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5073         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5074         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5075
5076         rtl_hw_aspm_clkreq_enable(tp, true);
5077 }
5078
5079 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5080 {
5081         rtl8168ep_stop_cmac(tp);
5082
5083         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5084         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5085
5086         rtl_set_def_aspm_entry_latency(tp);
5087
5088         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5089
5090         rtl_reset_packet_filter(tp);
5091
5092         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5093
5094         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5095
5096         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5097         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5098
5099         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5100         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5101
5102         rtl8168_config_eee_mac(tp);
5103
5104         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5105
5106         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5107
5108         rtl_pcie_state_l2l3_disable(tp);
5109 }
5110
5111 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5112 {
5113         static const struct ephy_info e_info_8168ep_1[] = {
5114                 { 0x00, 0xffff, 0x10ab },
5115                 { 0x06, 0xffff, 0xf030 },
5116                 { 0x08, 0xffff, 0x2006 },
5117                 { 0x0d, 0xffff, 0x1666 },
5118                 { 0x0c, 0x3ff0, 0x0000 }
5119         };
5120
5121         /* disable aspm and clock request before access ephy */
5122         rtl_hw_aspm_clkreq_enable(tp, false);
5123         rtl_ephy_init(tp, e_info_8168ep_1);
5124
5125         rtl_hw_start_8168ep(tp);
5126
5127         rtl_hw_aspm_clkreq_enable(tp, true);
5128 }
5129
5130 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5131 {
5132         static const struct ephy_info e_info_8168ep_2[] = {
5133                 { 0x00, 0xffff, 0x10a3 },
5134                 { 0x19, 0xffff, 0xfc00 },
5135                 { 0x1e, 0xffff, 0x20ea }
5136         };
5137
5138         /* disable aspm and clock request before access ephy */
5139         rtl_hw_aspm_clkreq_enable(tp, false);
5140         rtl_ephy_init(tp, e_info_8168ep_2);
5141
5142         rtl_hw_start_8168ep(tp);
5143
5144         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5145         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5146
5147         rtl_hw_aspm_clkreq_enable(tp, true);
5148 }
5149
5150 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5151 {
5152         u32 data;
5153         static const struct ephy_info e_info_8168ep_3[] = {
5154                 { 0x00, 0xffff, 0x10a3 },
5155                 { 0x19, 0xffff, 0x7c00 },
5156                 { 0x1e, 0xffff, 0x20eb },
5157                 { 0x0d, 0xffff, 0x1666 }
5158         };
5159
5160         /* disable aspm and clock request before access ephy */
5161         rtl_hw_aspm_clkreq_enable(tp, false);
5162         rtl_ephy_init(tp, e_info_8168ep_3);
5163
5164         rtl_hw_start_8168ep(tp);
5165
5166         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5167         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5168
5169         data = r8168_mac_ocp_read(tp, 0xd3e2);
5170         data &= 0xf000;
5171         data |= 0x0271;
5172         r8168_mac_ocp_write(tp, 0xd3e2, data);
5173
5174         data = r8168_mac_ocp_read(tp, 0xd3e4);
5175         data &= 0xff00;
5176         r8168_mac_ocp_write(tp, 0xd3e4, data);
5177
5178         data = r8168_mac_ocp_read(tp, 0xe860);
5179         data |= 0x0080;
5180         r8168_mac_ocp_write(tp, 0xe860, data);
5181
5182         rtl_hw_aspm_clkreq_enable(tp, true);
5183 }
5184
5185 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5186 {
5187         static const struct ephy_info e_info_8102e_1[] = {
5188                 { 0x01, 0, 0x6e65 },
5189                 { 0x02, 0, 0x091f },
5190                 { 0x03, 0, 0xc2f9 },
5191                 { 0x06, 0, 0xafb5 },
5192                 { 0x07, 0, 0x0e00 },
5193                 { 0x19, 0, 0xec80 },
5194                 { 0x01, 0, 0x2e65 },
5195                 { 0x01, 0, 0x6e65 }
5196         };
5197         u8 cfg1;
5198
5199         rtl_set_def_aspm_entry_latency(tp);
5200
5201         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5202
5203         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5204
5205         RTL_W8(tp, Config1,
5206                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5207         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5208
5209         cfg1 = RTL_R8(tp, Config1);
5210         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5211                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5212
5213         rtl_ephy_init(tp, e_info_8102e_1);
5214 }
5215
5216 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5217 {
5218         rtl_set_def_aspm_entry_latency(tp);
5219
5220         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5221
5222         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5223         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5224 }
5225
5226 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5227 {
5228         rtl_hw_start_8102e_2(tp);
5229
5230         rtl_ephy_write(tp, 0x03, 0xc2f9);
5231 }
5232
5233 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5234 {
5235         static const struct ephy_info e_info_8105e_1[] = {
5236                 { 0x07, 0, 0x4000 },
5237                 { 0x19, 0, 0x0200 },
5238                 { 0x19, 0, 0x0020 },
5239                 { 0x1e, 0, 0x2000 },
5240                 { 0x03, 0, 0x0001 },
5241                 { 0x19, 0, 0x0100 },
5242                 { 0x19, 0, 0x0004 },
5243                 { 0x0a, 0, 0x0020 }
5244         };
5245
5246         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5247         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5248
5249         /* Disable Early Tally Counter */
5250         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5251
5252         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5253         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5254
5255         rtl_ephy_init(tp, e_info_8105e_1);
5256
5257         rtl_pcie_state_l2l3_disable(tp);
5258 }
5259
5260 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5261 {
5262         rtl_hw_start_8105e_1(tp);
5263         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5264 }
5265
5266 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5267 {
5268         static const struct ephy_info e_info_8402[] = {
5269                 { 0x19, 0xffff, 0xff64 },
5270                 { 0x1e, 0, 0x4000 }
5271         };
5272
5273         rtl_set_def_aspm_entry_latency(tp);
5274
5275         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5276         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5277
5278         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5279
5280         rtl_ephy_init(tp, e_info_8402);
5281
5282         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5283
5284         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5285         rtl_reset_packet_filter(tp);
5286         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5287         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5288         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5289
5290         rtl_pcie_state_l2l3_disable(tp);
5291 }
5292
5293 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5294 {
5295         rtl_hw_aspm_clkreq_enable(tp, false);
5296
5297         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5298         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5299
5300         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5301         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5302         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5303
5304         rtl_pcie_state_l2l3_disable(tp);
5305         rtl_hw_aspm_clkreq_enable(tp, true);
5306 }
5307
5308 static void rtl_hw_config(struct rtl8169_private *tp)
5309 {
5310         static const rtl_generic_fct hw_configs[] = {
5311                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5312                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5313                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5314                 [RTL_GIGA_MAC_VER_10] = NULL,
5315                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5316                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5317                 [RTL_GIGA_MAC_VER_13] = NULL,
5318                 [RTL_GIGA_MAC_VER_14] = NULL,
5319                 [RTL_GIGA_MAC_VER_15] = NULL,
5320                 [RTL_GIGA_MAC_VER_16] = NULL,
5321                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5322                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5323                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5324                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5325                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5326                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5327                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5328                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5329                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5330                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5331                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5332                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5333                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5334                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5335                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5336                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5337                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5338                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5339                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5340                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5341                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5342                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5343                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5344                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5345                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5346                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5347                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5348                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5349                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5350                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5351                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5352                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5353                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5354                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5355                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5356         };
5357
5358         if (hw_configs[tp->mac_version])
5359                 hw_configs[tp->mac_version](tp);
5360 }
5361
5362 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5363 {
5364         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5365
5366         /* Workaround for RxFIFO overflow. */
5367         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5368                 tp->irq_mask |= RxFIFOOver;
5369                 tp->irq_mask &= ~RxOverflow;
5370         }
5371
5372         rtl_hw_config(tp);
5373 }
5374
5375 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5376 {
5377         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5378                 tp->irq_mask &= ~RxFIFOOver;
5379
5380         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5381             tp->mac_version == RTL_GIGA_MAC_VER_16)
5382                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5383                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5384
5385         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5386
5387         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5388         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5389
5390         rtl_hw_config(tp);
5391 }
5392
5393 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5394 {
5395         struct rtl8169_private *tp = netdev_priv(dev);
5396
5397         if (new_mtu > ETH_DATA_LEN)
5398                 rtl_hw_jumbo_enable(tp);
5399         else
5400                 rtl_hw_jumbo_disable(tp);
5401
5402         dev->mtu = new_mtu;
5403         netdev_update_features(dev);
5404
5405         return 0;
5406 }
5407
5408 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5409 {
5410         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5411         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5412 }
5413
5414 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5415                                      void **data_buff, struct RxDesc *desc)
5416 {
5417         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5418                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5419
5420         kfree(*data_buff);
5421         *data_buff = NULL;
5422         rtl8169_make_unusable_by_asic(desc);
5423 }
5424
5425 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5426 {
5427         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5428
5429         /* Force memory writes to complete before releasing descriptor */
5430         dma_wmb();
5431
5432         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5433 }
5434
5435 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5436                                              struct RxDesc *desc)
5437 {
5438         void *data;
5439         dma_addr_t mapping;
5440         struct device *d = tp_to_dev(tp);
5441         int node = dev_to_node(d);
5442
5443         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5444         if (!data)
5445                 return NULL;
5446
5447         /* Memory should be properly aligned, but better check. */
5448         if (!IS_ALIGNED((unsigned long)data, 8)) {
5449                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5450                 goto err_out;
5451         }
5452
5453         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5454         if (unlikely(dma_mapping_error(d, mapping))) {
5455                 if (net_ratelimit())
5456                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5457                 goto err_out;
5458         }
5459
5460         desc->addr = cpu_to_le64(mapping);
5461         rtl8169_mark_to_asic(desc);
5462         return data;
5463
5464 err_out:
5465         kfree(data);
5466         return NULL;
5467 }
5468
5469 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5470 {
5471         unsigned int i;
5472
5473         for (i = 0; i < NUM_RX_DESC; i++) {
5474                 if (tp->Rx_databuff[i]) {
5475                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5476                                             tp->RxDescArray + i);
5477                 }
5478         }
5479 }
5480
5481 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5482 {
5483         desc->opts1 |= cpu_to_le32(RingEnd);
5484 }
5485
5486 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5487 {
5488         unsigned int i;
5489
5490         for (i = 0; i < NUM_RX_DESC; i++) {
5491                 void *data;
5492
5493                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5494                 if (!data) {
5495                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5496                         goto err_out;
5497                 }
5498                 tp->Rx_databuff[i] = data;
5499         }
5500
5501         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5502         return 0;
5503
5504 err_out:
5505         rtl8169_rx_clear(tp);
5506         return -ENOMEM;
5507 }
5508
5509 static int rtl8169_init_ring(struct rtl8169_private *tp)
5510 {
5511         rtl8169_init_ring_indexes(tp);
5512
5513         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5514         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5515
5516         return rtl8169_rx_fill(tp);
5517 }
5518
5519 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5520                                  struct TxDesc *desc)
5521 {
5522         unsigned int len = tx_skb->len;
5523
5524         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5525
5526         desc->opts1 = 0x00;
5527         desc->opts2 = 0x00;
5528         desc->addr = 0x00;
5529         tx_skb->len = 0;
5530 }
5531
5532 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5533                                    unsigned int n)
5534 {
5535         unsigned int i;
5536
5537         for (i = 0; i < n; i++) {
5538                 unsigned int entry = (start + i) % NUM_TX_DESC;
5539                 struct ring_info *tx_skb = tp->tx_skb + entry;
5540                 unsigned int len = tx_skb->len;
5541
5542                 if (len) {
5543                         struct sk_buff *skb = tx_skb->skb;
5544
5545                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5546                                              tp->TxDescArray + entry);
5547                         if (skb) {
5548                                 dev_consume_skb_any(skb);
5549                                 tx_skb->skb = NULL;
5550                         }
5551                 }
5552         }
5553 }
5554
5555 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5556 {
5557         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5558         tp->cur_tx = tp->dirty_tx = 0;
5559         netdev_reset_queue(tp->dev);
5560 }
5561
5562 static void rtl_reset_work(struct rtl8169_private *tp)
5563 {
5564         struct net_device *dev = tp->dev;
5565         int i;
5566
5567         napi_disable(&tp->napi);
5568         netif_stop_queue(dev);
5569         synchronize_rcu();
5570
5571         rtl8169_hw_reset(tp);
5572
5573         for (i = 0; i < NUM_RX_DESC; i++)
5574                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5575
5576         rtl8169_tx_clear(tp);
5577         rtl8169_init_ring_indexes(tp);
5578
5579         napi_enable(&tp->napi);
5580         rtl_hw_start(tp);
5581         netif_wake_queue(dev);
5582 }
5583
5584 static void rtl8169_tx_timeout(struct net_device *dev)
5585 {
5586         struct rtl8169_private *tp = netdev_priv(dev);
5587
5588         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5589 }
5590
5591 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5592 {
5593         u32 status = opts0 | len;
5594
5595         if (entry == NUM_TX_DESC - 1)
5596                 status |= RingEnd;
5597
5598         return cpu_to_le32(status);
5599 }
5600
5601 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5602                               u32 *opts)
5603 {
5604         struct skb_shared_info *info = skb_shinfo(skb);
5605         unsigned int cur_frag, entry;
5606         struct TxDesc *uninitialized_var(txd);
5607         struct device *d = tp_to_dev(tp);
5608
5609         entry = tp->cur_tx;
5610         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5611                 const skb_frag_t *frag = info->frags + cur_frag;
5612                 dma_addr_t mapping;
5613                 u32 len;
5614                 void *addr;
5615
5616                 entry = (entry + 1) % NUM_TX_DESC;
5617
5618                 txd = tp->TxDescArray + entry;
5619                 len = skb_frag_size(frag);
5620                 addr = skb_frag_address(frag);
5621                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5622                 if (unlikely(dma_mapping_error(d, mapping))) {
5623                         if (net_ratelimit())
5624                                 netif_err(tp, drv, tp->dev,
5625                                           "Failed to map TX fragments DMA!\n");
5626                         goto err_out;
5627                 }
5628
5629                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5630                 txd->opts2 = cpu_to_le32(opts[1]);
5631                 txd->addr = cpu_to_le64(mapping);
5632
5633                 tp->tx_skb[entry].len = len;
5634         }
5635
5636         if (cur_frag) {
5637                 tp->tx_skb[entry].skb = skb;
5638                 txd->opts1 |= cpu_to_le32(LastFrag);
5639         }
5640
5641         return cur_frag;
5642
5643 err_out:
5644         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5645         return -EIO;
5646 }
5647
5648 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5649 {
5650         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5651 }
5652
5653 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5654                                       struct net_device *dev);
5655 /* r8169_csum_workaround()
5656  * The hw limites the value the transport offset. When the offset is out of the
5657  * range, calculate the checksum by sw.
5658  */
5659 static void r8169_csum_workaround(struct rtl8169_private *tp,
5660                                   struct sk_buff *skb)
5661 {
5662         if (skb_is_gso(skb)) {
5663                 netdev_features_t features = tp->dev->features;
5664                 struct sk_buff *segs, *nskb;
5665
5666                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5667                 segs = skb_gso_segment(skb, features);
5668                 if (IS_ERR(segs) || !segs)
5669                         goto drop;
5670
5671                 do {
5672                         nskb = segs;
5673                         segs = segs->next;
5674                         nskb->next = NULL;
5675                         rtl8169_start_xmit(nskb, tp->dev);
5676                 } while (segs);
5677
5678                 dev_consume_skb_any(skb);
5679         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5680                 if (skb_checksum_help(skb) < 0)
5681                         goto drop;
5682
5683                 rtl8169_start_xmit(skb, tp->dev);
5684         } else {
5685 drop:
5686                 tp->dev->stats.tx_dropped++;
5687                 dev_kfree_skb_any(skb);
5688         }
5689 }
5690
5691 /* msdn_giant_send_check()
5692  * According to the document of microsoft, the TCP Pseudo Header excludes the
5693  * packet length for IPv6 TCP large packets.
5694  */
5695 static int msdn_giant_send_check(struct sk_buff *skb)
5696 {
5697         const struct ipv6hdr *ipv6h;
5698         struct tcphdr *th;
5699         int ret;
5700
5701         ret = skb_cow_head(skb, 0);
5702         if (ret)
5703                 return ret;
5704
5705         ipv6h = ipv6_hdr(skb);
5706         th = tcp_hdr(skb);
5707
5708         th->check = 0;
5709         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5710
5711         return ret;
5712 }
5713
5714 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5715 {
5716         u32 mss = skb_shinfo(skb)->gso_size;
5717
5718         if (mss) {
5719                 opts[0] |= TD_LSO;
5720                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5721         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5722                 const struct iphdr *ip = ip_hdr(skb);
5723
5724                 if (ip->protocol == IPPROTO_TCP)
5725                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5726                 else if (ip->protocol == IPPROTO_UDP)
5727                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5728                 else
5729                         WARN_ON_ONCE(1);
5730         }
5731 }
5732
5733 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5734                                 struct sk_buff *skb, u32 *opts)
5735 {
5736         u32 transport_offset = (u32)skb_transport_offset(skb);
5737         u32 mss = skb_shinfo(skb)->gso_size;
5738
5739         if (mss) {
5740                 if (transport_offset > GTTCPHO_MAX) {
5741                         netif_warn(tp, tx_err, tp->dev,
5742                                    "Invalid transport offset 0x%x for TSO\n",
5743                                    transport_offset);
5744                         return false;
5745                 }
5746
5747                 switch (vlan_get_protocol(skb)) {
5748                 case htons(ETH_P_IP):
5749                         opts[0] |= TD1_GTSENV4;
5750                         break;
5751
5752                 case htons(ETH_P_IPV6):
5753                         if (msdn_giant_send_check(skb))
5754                                 return false;
5755
5756                         opts[0] |= TD1_GTSENV6;
5757                         break;
5758
5759                 default:
5760                         WARN_ON_ONCE(1);
5761                         break;
5762                 }
5763
5764                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5765                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5766         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5767                 u8 ip_protocol;
5768
5769                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5770                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5771
5772                 if (transport_offset > TCPHO_MAX) {
5773                         netif_warn(tp, tx_err, tp->dev,
5774                                    "Invalid transport offset 0x%x\n",
5775                                    transport_offset);
5776                         return false;
5777                 }
5778
5779                 switch (vlan_get_protocol(skb)) {
5780                 case htons(ETH_P_IP):
5781                         opts[1] |= TD1_IPv4_CS;
5782                         ip_protocol = ip_hdr(skb)->protocol;
5783                         break;
5784
5785                 case htons(ETH_P_IPV6):
5786                         opts[1] |= TD1_IPv6_CS;
5787                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5788                         break;
5789
5790                 default:
5791                         ip_protocol = IPPROTO_RAW;
5792                         break;
5793                 }
5794
5795                 if (ip_protocol == IPPROTO_TCP)
5796                         opts[1] |= TD1_TCP_CS;
5797                 else if (ip_protocol == IPPROTO_UDP)
5798                         opts[1] |= TD1_UDP_CS;
5799                 else
5800                         WARN_ON_ONCE(1);
5801
5802                 opts[1] |= transport_offset << TCPHO_SHIFT;
5803         } else {
5804                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5805                         return !eth_skb_pad(skb);
5806         }
5807
5808         return true;
5809 }
5810
5811 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5812                                unsigned int nr_frags)
5813 {
5814         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5815
5816         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5817         return slots_avail > nr_frags;
5818 }
5819
5820 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5821 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5822 {
5823         switch (tp->mac_version) {
5824         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5825         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5826                 return false;
5827         default:
5828                 return true;
5829         }
5830 }
5831
5832 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5833                                       struct net_device *dev)
5834 {
5835         struct rtl8169_private *tp = netdev_priv(dev);
5836         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5837         struct TxDesc *txd = tp->TxDescArray + entry;
5838         struct device *d = tp_to_dev(tp);
5839         dma_addr_t mapping;
5840         u32 opts[2], len;
5841         int frags;
5842
5843         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5844                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5845                 goto err_stop_0;
5846         }
5847
5848         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5849                 goto err_stop_0;
5850
5851         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5852         opts[0] = DescOwn;
5853
5854         if (rtl_chip_supports_csum_v2(tp)) {
5855                 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5856                         r8169_csum_workaround(tp, skb);
5857                         return NETDEV_TX_OK;
5858                 }
5859         } else {
5860                 rtl8169_tso_csum_v1(skb, opts);
5861         }
5862
5863         len = skb_headlen(skb);
5864         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5865         if (unlikely(dma_mapping_error(d, mapping))) {
5866                 if (net_ratelimit())
5867                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5868                 goto err_dma_0;
5869         }
5870
5871         tp->tx_skb[entry].len = len;
5872         txd->addr = cpu_to_le64(mapping);
5873
5874         frags = rtl8169_xmit_frags(tp, skb, opts);
5875         if (frags < 0)
5876                 goto err_dma_1;
5877         else if (frags)
5878                 opts[0] |= FirstFrag;
5879         else {
5880                 opts[0] |= FirstFrag | LastFrag;
5881                 tp->tx_skb[entry].skb = skb;
5882         }
5883
5884         txd->opts2 = cpu_to_le32(opts[1]);
5885
5886         netdev_sent_queue(dev, skb->len);
5887
5888         skb_tx_timestamp(skb);
5889
5890         /* Force memory writes to complete before releasing descriptor */
5891         dma_wmb();
5892
5893         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5894
5895         /* Force all memory writes to complete before notifying device */
5896         wmb();
5897
5898         tp->cur_tx += frags + 1;
5899
5900         RTL_W8(tp, TxPoll, NPQ);
5901
5902         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5903                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5904                  * not miss a ring update when it notices a stopped queue.
5905                  */
5906                 smp_wmb();
5907                 netif_stop_queue(dev);
5908                 /* Sync with rtl_tx:
5909                  * - publish queue status and cur_tx ring index (write barrier)
5910                  * - refresh dirty_tx ring index (read barrier).
5911                  * May the current thread have a pessimistic view of the ring
5912                  * status and forget to wake up queue, a racing rtl_tx thread
5913                  * can't.
5914                  */
5915                 smp_mb();
5916                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5917                         netif_start_queue(dev);
5918         }
5919
5920         return NETDEV_TX_OK;
5921
5922 err_dma_1:
5923         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5924 err_dma_0:
5925         dev_kfree_skb_any(skb);
5926         dev->stats.tx_dropped++;
5927         return NETDEV_TX_OK;
5928
5929 err_stop_0:
5930         netif_stop_queue(dev);
5931         dev->stats.tx_dropped++;
5932         return NETDEV_TX_BUSY;
5933 }
5934
5935 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5936 {
5937         struct rtl8169_private *tp = netdev_priv(dev);
5938         struct pci_dev *pdev = tp->pci_dev;
5939         u16 pci_status, pci_cmd;
5940
5941         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5942         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5943
5944         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5945                   pci_cmd, pci_status);
5946
5947         /*
5948          * The recovery sequence below admits a very elaborated explanation:
5949          * - it seems to work;
5950          * - I did not see what else could be done;
5951          * - it makes iop3xx happy.
5952          *
5953          * Feel free to adjust to your needs.
5954          */
5955         if (pdev->broken_parity_status)
5956                 pci_cmd &= ~PCI_COMMAND_PARITY;
5957         else
5958                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5959
5960         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5961
5962         pci_write_config_word(pdev, PCI_STATUS,
5963                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5964                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5965                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5966
5967         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5968 }
5969
5970 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5971                    int budget)
5972 {
5973         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5974
5975         dirty_tx = tp->dirty_tx;
5976         smp_rmb();
5977         tx_left = tp->cur_tx - dirty_tx;
5978
5979         while (tx_left > 0) {
5980                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5981                 struct ring_info *tx_skb = tp->tx_skb + entry;
5982                 u32 status;
5983
5984                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5985                 if (status & DescOwn)
5986                         break;
5987
5988                 /* This barrier is needed to keep us from reading
5989                  * any other fields out of the Tx descriptor until
5990                  * we know the status of DescOwn
5991                  */
5992                 dma_rmb();
5993
5994                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5995                                      tp->TxDescArray + entry);
5996                 if (status & LastFrag) {
5997                         pkts_compl++;
5998                         bytes_compl += tx_skb->skb->len;
5999                         napi_consume_skb(tx_skb->skb, budget);
6000                         tx_skb->skb = NULL;
6001                 }
6002                 dirty_tx++;
6003                 tx_left--;
6004         }
6005
6006         if (tp->dirty_tx != dirty_tx) {
6007                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6008
6009                 u64_stats_update_begin(&tp->tx_stats.syncp);
6010                 tp->tx_stats.packets += pkts_compl;
6011                 tp->tx_stats.bytes += bytes_compl;
6012                 u64_stats_update_end(&tp->tx_stats.syncp);
6013
6014                 tp->dirty_tx = dirty_tx;
6015                 /* Sync with rtl8169_start_xmit:
6016                  * - publish dirty_tx ring index (write barrier)
6017                  * - refresh cur_tx ring index and queue status (read barrier)
6018                  * May the current thread miss the stopped queue condition,
6019                  * a racing xmit thread can only have a right view of the
6020                  * ring status.
6021                  */
6022                 smp_mb();
6023                 if (netif_queue_stopped(dev) &&
6024                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6025                         netif_wake_queue(dev);
6026                 }
6027                 /*
6028                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6029                  * too close. Let's kick an extra TxPoll request when a burst
6030                  * of start_xmit activity is detected (if it is not detected,
6031                  * it is slow enough). -- FR
6032                  */
6033                 if (tp->cur_tx != dirty_tx)
6034                         RTL_W8(tp, TxPoll, NPQ);
6035         }
6036 }
6037
6038 static inline int rtl8169_fragmented_frame(u32 status)
6039 {
6040         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6041 }
6042
6043 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6044 {
6045         u32 status = opts1 & RxProtoMask;
6046
6047         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6048             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6049                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6050         else
6051                 skb_checksum_none_assert(skb);
6052 }
6053
6054 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6055                                            struct rtl8169_private *tp,
6056                                            int pkt_size,
6057                                            dma_addr_t addr)
6058 {
6059         struct sk_buff *skb;
6060         struct device *d = tp_to_dev(tp);
6061
6062         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6063         prefetch(data);
6064         skb = napi_alloc_skb(&tp->napi, pkt_size);
6065         if (skb)
6066                 skb_copy_to_linear_data(skb, data, pkt_size);
6067         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6068
6069         return skb;
6070 }
6071
6072 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6073 {
6074         unsigned int cur_rx, rx_left;
6075         unsigned int count;
6076
6077         cur_rx = tp->cur_rx;
6078
6079         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6080                 unsigned int entry = cur_rx % NUM_RX_DESC;
6081                 struct RxDesc *desc = tp->RxDescArray + entry;
6082                 u32 status;
6083
6084                 status = le32_to_cpu(desc->opts1);
6085                 if (status & DescOwn)
6086                         break;
6087
6088                 /* This barrier is needed to keep us from reading
6089                  * any other fields out of the Rx descriptor until
6090                  * we know the status of DescOwn
6091                  */
6092                 dma_rmb();
6093
6094                 if (unlikely(status & RxRES)) {
6095                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6096                                    status);
6097                         dev->stats.rx_errors++;
6098                         if (status & (RxRWT | RxRUNT))
6099                                 dev->stats.rx_length_errors++;
6100                         if (status & RxCRC)
6101                                 dev->stats.rx_crc_errors++;
6102                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6103                             dev->features & NETIF_F_RXALL) {
6104                                 goto process_pkt;
6105                         }
6106                 } else {
6107                         struct sk_buff *skb;
6108                         dma_addr_t addr;
6109                         int pkt_size;
6110
6111 process_pkt:
6112                         addr = le64_to_cpu(desc->addr);
6113                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6114                                 pkt_size = (status & 0x00003fff) - 4;
6115                         else
6116                                 pkt_size = status & 0x00003fff;
6117
6118                         /*
6119                          * The driver does not support incoming fragmented
6120                          * frames. They are seen as a symptom of over-mtu
6121                          * sized frames.
6122                          */
6123                         if (unlikely(rtl8169_fragmented_frame(status))) {
6124                                 dev->stats.rx_dropped++;
6125                                 dev->stats.rx_length_errors++;
6126                                 goto release_descriptor;
6127                         }
6128
6129                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6130                                                   tp, pkt_size, addr);
6131                         if (!skb) {
6132                                 dev->stats.rx_dropped++;
6133                                 goto release_descriptor;
6134                         }
6135
6136                         rtl8169_rx_csum(skb, status);
6137                         skb_put(skb, pkt_size);
6138                         skb->protocol = eth_type_trans(skb, dev);
6139
6140                         rtl8169_rx_vlan_tag(desc, skb);
6141
6142                         if (skb->pkt_type == PACKET_MULTICAST)
6143                                 dev->stats.multicast++;
6144
6145                         napi_gro_receive(&tp->napi, skb);
6146
6147                         u64_stats_update_begin(&tp->rx_stats.syncp);
6148                         tp->rx_stats.packets++;
6149                         tp->rx_stats.bytes += pkt_size;
6150                         u64_stats_update_end(&tp->rx_stats.syncp);
6151                 }
6152 release_descriptor:
6153                 desc->opts2 = 0;
6154                 rtl8169_mark_to_asic(desc);
6155         }
6156
6157         count = cur_rx - tp->cur_rx;
6158         tp->cur_rx = cur_rx;
6159
6160         return count;
6161 }
6162
6163 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6164 {
6165         struct rtl8169_private *tp = dev_instance;
6166         u16 status = RTL_R16(tp, IntrStatus);
6167
6168         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6169                 return IRQ_NONE;
6170
6171         if (unlikely(status & SYSErr)) {
6172                 rtl8169_pcierr_interrupt(tp->dev);
6173                 goto out;
6174         }
6175
6176         if (status & LinkChg)
6177                 phy_mac_interrupt(tp->phydev);
6178
6179         if (unlikely(status & RxFIFOOver &&
6180             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6181                 netif_stop_queue(tp->dev);
6182                 /* XXX - Hack alert. See rtl_task(). */
6183                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6184         }
6185
6186         rtl_irq_disable(tp);
6187         napi_schedule_irqoff(&tp->napi);
6188 out:
6189         rtl_ack_events(tp, status);
6190
6191         return IRQ_HANDLED;
6192 }
6193
6194 static void rtl_task(struct work_struct *work)
6195 {
6196         static const struct {
6197                 int bitnr;
6198                 void (*action)(struct rtl8169_private *);
6199         } rtl_work[] = {
6200                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6201         };
6202         struct rtl8169_private *tp =
6203                 container_of(work, struct rtl8169_private, wk.work);
6204         struct net_device *dev = tp->dev;
6205         int i;
6206
6207         rtl_lock_work(tp);
6208
6209         if (!netif_running(dev) ||
6210             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6211                 goto out_unlock;
6212
6213         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6214                 bool pending;
6215
6216                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6217                 if (pending)
6218                         rtl_work[i].action(tp);
6219         }
6220
6221 out_unlock:
6222         rtl_unlock_work(tp);
6223 }
6224
6225 static int rtl8169_poll(struct napi_struct *napi, int budget)
6226 {
6227         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6228         struct net_device *dev = tp->dev;
6229         int work_done;
6230
6231         work_done = rtl_rx(dev, tp, (u32) budget);
6232
6233         rtl_tx(dev, tp, budget);
6234
6235         if (work_done < budget) {
6236                 napi_complete_done(napi, work_done);
6237                 rtl_irq_enable(tp);
6238         }
6239
6240         return work_done;
6241 }
6242
6243 static void rtl8169_rx_missed(struct net_device *dev)
6244 {
6245         struct rtl8169_private *tp = netdev_priv(dev);
6246
6247         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6248                 return;
6249
6250         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6251         RTL_W32(tp, RxMissed, 0);
6252 }
6253
6254 static void r8169_phylink_handler(struct net_device *ndev)
6255 {
6256         struct rtl8169_private *tp = netdev_priv(ndev);
6257
6258         if (netif_carrier_ok(ndev)) {
6259                 rtl_link_chg_patch(tp);
6260                 pm_request_resume(&tp->pci_dev->dev);
6261         } else {
6262                 pm_runtime_idle(&tp->pci_dev->dev);
6263         }
6264
6265         if (net_ratelimit())
6266                 phy_print_status(tp->phydev);
6267 }
6268
6269 static int r8169_phy_connect(struct rtl8169_private *tp)
6270 {
6271         struct phy_device *phydev = tp->phydev;
6272         phy_interface_t phy_mode;
6273         int ret;
6274
6275         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6276                    PHY_INTERFACE_MODE_MII;
6277
6278         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6279                                  phy_mode);
6280         if (ret)
6281                 return ret;
6282
6283         if (tp->supports_gmii)
6284                 phy_remove_link_mode(phydev,
6285                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6286         else
6287                 phy_set_max_speed(phydev, SPEED_100);
6288
6289         phy_support_asym_pause(phydev);
6290
6291         phy_attached_info(phydev);
6292
6293         return 0;
6294 }
6295
6296 static void rtl8169_down(struct net_device *dev)
6297 {
6298         struct rtl8169_private *tp = netdev_priv(dev);
6299
6300         phy_stop(tp->phydev);
6301
6302         napi_disable(&tp->napi);
6303         netif_stop_queue(dev);
6304
6305         rtl8169_hw_reset(tp);
6306         /*
6307          * At this point device interrupts can not be enabled in any function,
6308          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6309          * and napi is disabled (rtl8169_poll).
6310          */
6311         rtl8169_rx_missed(dev);
6312
6313         /* Give a racing hard_start_xmit a few cycles to complete. */
6314         synchronize_rcu();
6315
6316         rtl8169_tx_clear(tp);
6317
6318         rtl8169_rx_clear(tp);
6319
6320         rtl_pll_power_down(tp);
6321 }
6322
6323 static int rtl8169_close(struct net_device *dev)
6324 {
6325         struct rtl8169_private *tp = netdev_priv(dev);
6326         struct pci_dev *pdev = tp->pci_dev;
6327
6328         pm_runtime_get_sync(&pdev->dev);
6329
6330         /* Update counters before going down */
6331         rtl8169_update_counters(tp);
6332
6333         rtl_lock_work(tp);
6334         /* Clear all task flags */
6335         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6336
6337         rtl8169_down(dev);
6338         rtl_unlock_work(tp);
6339
6340         cancel_work_sync(&tp->wk.work);
6341
6342         phy_disconnect(tp->phydev);
6343
6344         pci_free_irq(pdev, 0, tp);
6345
6346         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6347                           tp->RxPhyAddr);
6348         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6349                           tp->TxPhyAddr);
6350         tp->TxDescArray = NULL;
6351         tp->RxDescArray = NULL;
6352
6353         pm_runtime_put_sync(&pdev->dev);
6354
6355         return 0;
6356 }
6357
6358 #ifdef CONFIG_NET_POLL_CONTROLLER
6359 static void rtl8169_netpoll(struct net_device *dev)
6360 {
6361         struct rtl8169_private *tp = netdev_priv(dev);
6362
6363         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6364 }
6365 #endif
6366
6367 static int rtl_open(struct net_device *dev)
6368 {
6369         struct rtl8169_private *tp = netdev_priv(dev);
6370         struct pci_dev *pdev = tp->pci_dev;
6371         int retval = -ENOMEM;
6372
6373         pm_runtime_get_sync(&pdev->dev);
6374
6375         /*
6376          * Rx and Tx descriptors needs 256 bytes alignment.
6377          * dma_alloc_coherent provides more.
6378          */
6379         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6380                                              &tp->TxPhyAddr, GFP_KERNEL);
6381         if (!tp->TxDescArray)
6382                 goto err_pm_runtime_put;
6383
6384         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6385                                              &tp->RxPhyAddr, GFP_KERNEL);
6386         if (!tp->RxDescArray)
6387                 goto err_free_tx_0;
6388
6389         retval = rtl8169_init_ring(tp);
6390         if (retval < 0)
6391                 goto err_free_rx_1;
6392
6393         rtl_request_firmware(tp);
6394
6395         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6396                                  dev->name);
6397         if (retval < 0)
6398                 goto err_release_fw_2;
6399
6400         retval = r8169_phy_connect(tp);
6401         if (retval)
6402                 goto err_free_irq;
6403
6404         rtl_lock_work(tp);
6405
6406         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6407
6408         napi_enable(&tp->napi);
6409
6410         rtl8169_init_phy(dev, tp);
6411
6412         rtl_pll_power_up(tp);
6413
6414         rtl_hw_start(tp);
6415
6416         if (!rtl8169_init_counter_offsets(tp))
6417                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6418
6419         phy_start(tp->phydev);
6420         netif_start_queue(dev);
6421
6422         rtl_unlock_work(tp);
6423
6424         pm_runtime_put_sync(&pdev->dev);
6425 out:
6426         return retval;
6427
6428 err_free_irq:
6429         pci_free_irq(pdev, 0, tp);
6430 err_release_fw_2:
6431         rtl_release_firmware(tp);
6432         rtl8169_rx_clear(tp);
6433 err_free_rx_1:
6434         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6435                           tp->RxPhyAddr);
6436         tp->RxDescArray = NULL;
6437 err_free_tx_0:
6438         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6439                           tp->TxPhyAddr);
6440         tp->TxDescArray = NULL;
6441 err_pm_runtime_put:
6442         pm_runtime_put_noidle(&pdev->dev);
6443         goto out;
6444 }
6445
6446 static void
6447 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6448 {
6449         struct rtl8169_private *tp = netdev_priv(dev);
6450         struct pci_dev *pdev = tp->pci_dev;
6451         struct rtl8169_counters *counters = tp->counters;
6452         unsigned int start;
6453
6454         pm_runtime_get_noresume(&pdev->dev);
6455
6456         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6457                 rtl8169_rx_missed(dev);
6458
6459         do {
6460                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6461                 stats->rx_packets = tp->rx_stats.packets;
6462                 stats->rx_bytes = tp->rx_stats.bytes;
6463         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6464
6465         do {
6466                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6467                 stats->tx_packets = tp->tx_stats.packets;
6468                 stats->tx_bytes = tp->tx_stats.bytes;
6469         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6470
6471         stats->rx_dropped       = dev->stats.rx_dropped;
6472         stats->tx_dropped       = dev->stats.tx_dropped;
6473         stats->rx_length_errors = dev->stats.rx_length_errors;
6474         stats->rx_errors        = dev->stats.rx_errors;
6475         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6476         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6477         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6478         stats->multicast        = dev->stats.multicast;
6479
6480         /*
6481          * Fetch additonal counter values missing in stats collected by driver
6482          * from tally counters.
6483          */
6484         if (pm_runtime_active(&pdev->dev))
6485                 rtl8169_update_counters(tp);
6486
6487         /*
6488          * Subtract values fetched during initalization.
6489          * See rtl8169_init_counter_offsets for a description why we do that.
6490          */
6491         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6492                 le64_to_cpu(tp->tc_offset.tx_errors);
6493         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6494                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6495         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6496                 le16_to_cpu(tp->tc_offset.tx_aborted);
6497
6498         pm_runtime_put_noidle(&pdev->dev);
6499 }
6500
6501 static void rtl8169_net_suspend(struct net_device *dev)
6502 {
6503         struct rtl8169_private *tp = netdev_priv(dev);
6504
6505         if (!netif_running(dev))
6506                 return;
6507
6508         phy_stop(tp->phydev);
6509         netif_device_detach(dev);
6510
6511         rtl_lock_work(tp);
6512         napi_disable(&tp->napi);
6513         /* Clear all task flags */
6514         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6515
6516         rtl_unlock_work(tp);
6517
6518         rtl_pll_power_down(tp);
6519 }
6520
6521 #ifdef CONFIG_PM
6522
6523 static int rtl8169_suspend(struct device *device)
6524 {
6525         struct net_device *dev = dev_get_drvdata(device);
6526         struct rtl8169_private *tp = netdev_priv(dev);
6527
6528         rtl8169_net_suspend(dev);
6529         clk_disable_unprepare(tp->clk);
6530
6531         return 0;
6532 }
6533
6534 static void __rtl8169_resume(struct net_device *dev)
6535 {
6536         struct rtl8169_private *tp = netdev_priv(dev);
6537
6538         netif_device_attach(dev);
6539
6540         rtl_pll_power_up(tp);
6541         rtl8169_init_phy(dev, tp);
6542
6543         phy_start(tp->phydev);
6544
6545         rtl_lock_work(tp);
6546         napi_enable(&tp->napi);
6547         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6548         rtl_reset_work(tp);
6549         rtl_unlock_work(tp);
6550 }
6551
6552 static int rtl8169_resume(struct device *device)
6553 {
6554         struct net_device *dev = dev_get_drvdata(device);
6555         struct rtl8169_private *tp = netdev_priv(dev);
6556
6557         rtl_rar_set(tp, dev->dev_addr);
6558
6559         clk_prepare_enable(tp->clk);
6560
6561         if (netif_running(dev))
6562                 __rtl8169_resume(dev);
6563
6564         return 0;
6565 }
6566
6567 static int rtl8169_runtime_suspend(struct device *device)
6568 {
6569         struct net_device *dev = dev_get_drvdata(device);
6570         struct rtl8169_private *tp = netdev_priv(dev);
6571
6572         if (!tp->TxDescArray)
6573                 return 0;
6574
6575         rtl_lock_work(tp);
6576         __rtl8169_set_wol(tp, WAKE_ANY);
6577         rtl_unlock_work(tp);
6578
6579         rtl8169_net_suspend(dev);
6580
6581         /* Update counters before going runtime suspend */
6582         rtl8169_rx_missed(dev);
6583         rtl8169_update_counters(tp);
6584
6585         return 0;
6586 }
6587
6588 static int rtl8169_runtime_resume(struct device *device)
6589 {
6590         struct net_device *dev = dev_get_drvdata(device);
6591         struct rtl8169_private *tp = netdev_priv(dev);
6592
6593         rtl_rar_set(tp, dev->dev_addr);
6594
6595         if (!tp->TxDescArray)
6596                 return 0;
6597
6598         rtl_lock_work(tp);
6599         __rtl8169_set_wol(tp, tp->saved_wolopts);
6600         rtl_unlock_work(tp);
6601
6602         __rtl8169_resume(dev);
6603
6604         return 0;
6605 }
6606
6607 static int rtl8169_runtime_idle(struct device *device)
6608 {
6609         struct net_device *dev = dev_get_drvdata(device);
6610
6611         if (!netif_running(dev) || !netif_carrier_ok(dev))
6612                 pm_schedule_suspend(device, 10000);
6613
6614         return -EBUSY;
6615 }
6616
6617 static const struct dev_pm_ops rtl8169_pm_ops = {
6618         .suspend                = rtl8169_suspend,
6619         .resume                 = rtl8169_resume,
6620         .freeze                 = rtl8169_suspend,
6621         .thaw                   = rtl8169_resume,
6622         .poweroff               = rtl8169_suspend,
6623         .restore                = rtl8169_resume,
6624         .runtime_suspend        = rtl8169_runtime_suspend,
6625         .runtime_resume         = rtl8169_runtime_resume,
6626         .runtime_idle           = rtl8169_runtime_idle,
6627 };
6628
6629 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6630
6631 #else /* !CONFIG_PM */
6632
6633 #define RTL8169_PM_OPS  NULL
6634
6635 #endif /* !CONFIG_PM */
6636
6637 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6638 {
6639         /* WoL fails with 8168b when the receiver is disabled. */
6640         switch (tp->mac_version) {
6641         case RTL_GIGA_MAC_VER_11:
6642         case RTL_GIGA_MAC_VER_12:
6643         case RTL_GIGA_MAC_VER_17:
6644                 pci_clear_master(tp->pci_dev);
6645
6646                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6647                 /* PCI commit */
6648                 RTL_R8(tp, ChipCmd);
6649                 break;
6650         default:
6651                 break;
6652         }
6653 }
6654
6655 static void rtl_shutdown(struct pci_dev *pdev)
6656 {
6657         struct net_device *dev = pci_get_drvdata(pdev);
6658         struct rtl8169_private *tp = netdev_priv(dev);
6659
6660         rtl8169_net_suspend(dev);
6661
6662         /* Restore original MAC address */
6663         rtl_rar_set(tp, dev->perm_addr);
6664
6665         rtl8169_hw_reset(tp);
6666
6667         if (system_state == SYSTEM_POWER_OFF) {
6668                 if (tp->saved_wolopts) {
6669                         rtl_wol_suspend_quirk(tp);
6670                         rtl_wol_shutdown_quirk(tp);
6671                 }
6672
6673                 pci_wake_from_d3(pdev, true);
6674                 pci_set_power_state(pdev, PCI_D3hot);
6675         }
6676 }
6677
6678 static void rtl_remove_one(struct pci_dev *pdev)
6679 {
6680         struct net_device *dev = pci_get_drvdata(pdev);
6681         struct rtl8169_private *tp = netdev_priv(dev);
6682
6683         if (r8168_check_dash(tp))
6684                 rtl8168_driver_stop(tp);
6685
6686         netif_napi_del(&tp->napi);
6687
6688         unregister_netdev(dev);
6689         mdiobus_unregister(tp->phydev->mdio.bus);
6690
6691         rtl_release_firmware(tp);
6692
6693         if (pci_dev_run_wake(pdev))
6694                 pm_runtime_get_noresume(&pdev->dev);
6695
6696         /* restore original MAC address */
6697         rtl_rar_set(tp, dev->perm_addr);
6698 }
6699
6700 static const struct net_device_ops rtl_netdev_ops = {
6701         .ndo_open               = rtl_open,
6702         .ndo_stop               = rtl8169_close,
6703         .ndo_get_stats64        = rtl8169_get_stats64,
6704         .ndo_start_xmit         = rtl8169_start_xmit,
6705         .ndo_tx_timeout         = rtl8169_tx_timeout,
6706         .ndo_validate_addr      = eth_validate_addr,
6707         .ndo_change_mtu         = rtl8169_change_mtu,
6708         .ndo_fix_features       = rtl8169_fix_features,
6709         .ndo_set_features       = rtl8169_set_features,
6710         .ndo_set_mac_address    = rtl_set_mac_address,
6711         .ndo_do_ioctl           = rtl8169_ioctl,
6712         .ndo_set_rx_mode        = rtl_set_rx_mode,
6713 #ifdef CONFIG_NET_POLL_CONTROLLER
6714         .ndo_poll_controller    = rtl8169_netpoll,
6715 #endif
6716
6717 };
6718
6719 static const struct rtl_cfg_info {
6720         void (*hw_start)(struct rtl8169_private *tp);
6721         u16 irq_mask;
6722         unsigned int has_gmii:1;
6723         const struct rtl_coalesce_info *coalesce_info;
6724 } rtl_cfg_infos [] = {
6725         [RTL_CFG_0] = {
6726                 .hw_start       = rtl_hw_start_8169,
6727                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6728                 .has_gmii       = 1,
6729                 .coalesce_info  = rtl_coalesce_info_8169,
6730         },
6731         [RTL_CFG_1] = {
6732                 .hw_start       = rtl_hw_start_8168,
6733                 .irq_mask       = LinkChg | RxOverflow,
6734                 .has_gmii       = 1,
6735                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6736         },
6737         [RTL_CFG_2] = {
6738                 .hw_start       = rtl_hw_start_8101,
6739                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6740                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6741         }
6742 };
6743
6744 static int rtl_alloc_irq(struct rtl8169_private *tp)
6745 {
6746         unsigned int flags;
6747
6748         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6749                 rtl_unlock_config_regs(tp);
6750                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6751                 rtl_lock_config_regs(tp);
6752                 flags = PCI_IRQ_LEGACY;
6753         } else {
6754                 flags = PCI_IRQ_ALL_TYPES;
6755         }
6756
6757         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6758 }
6759
6760 static void rtl_read_mac_address(struct rtl8169_private *tp,
6761                                  u8 mac_addr[ETH_ALEN])
6762 {
6763         u32 value;
6764
6765         /* Get MAC address */
6766         switch (tp->mac_version) {
6767         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6768         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6769                 value = rtl_eri_read(tp, 0xe0);
6770                 mac_addr[0] = (value >>  0) & 0xff;
6771                 mac_addr[1] = (value >>  8) & 0xff;
6772                 mac_addr[2] = (value >> 16) & 0xff;
6773                 mac_addr[3] = (value >> 24) & 0xff;
6774
6775                 value = rtl_eri_read(tp, 0xe4);
6776                 mac_addr[4] = (value >>  0) & 0xff;
6777                 mac_addr[5] = (value >>  8) & 0xff;
6778                 break;
6779         default:
6780                 break;
6781         }
6782 }
6783
6784 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6785 {
6786         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6787 }
6788
6789 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6790 {
6791         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6792 }
6793
6794 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6795 {
6796         struct rtl8169_private *tp = mii_bus->priv;
6797
6798         if (phyaddr > 0)
6799                 return -ENODEV;
6800
6801         return rtl_readphy(tp, phyreg);
6802 }
6803
6804 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6805                                 int phyreg, u16 val)
6806 {
6807         struct rtl8169_private *tp = mii_bus->priv;
6808
6809         if (phyaddr > 0)
6810                 return -ENODEV;
6811
6812         rtl_writephy(tp, phyreg, val);
6813
6814         return 0;
6815 }
6816
6817 static int r8169_mdio_register(struct rtl8169_private *tp)
6818 {
6819         struct pci_dev *pdev = tp->pci_dev;
6820         struct mii_bus *new_bus;
6821         int ret;
6822
6823         new_bus = devm_mdiobus_alloc(&pdev->dev);
6824         if (!new_bus)
6825                 return -ENOMEM;
6826
6827         new_bus->name = "r8169";
6828         new_bus->priv = tp;
6829         new_bus->parent = &pdev->dev;
6830         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6831         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6832
6833         new_bus->read = r8169_mdio_read_reg;
6834         new_bus->write = r8169_mdio_write_reg;
6835
6836         ret = mdiobus_register(new_bus);
6837         if (ret)
6838                 return ret;
6839
6840         tp->phydev = mdiobus_get_phy(new_bus, 0);
6841         if (!tp->phydev) {
6842                 mdiobus_unregister(new_bus);
6843                 return -ENODEV;
6844         }
6845
6846         /* PHY will be woken up in rtl_open() */
6847         phy_suspend(tp->phydev);
6848
6849         return 0;
6850 }
6851
6852 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6853 {
6854         u32 data;
6855
6856         tp->ocp_base = OCP_STD_PHY_BASE;
6857
6858         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6859
6860         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6861                 return;
6862
6863         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6864                 return;
6865
6866         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6867         msleep(1);
6868         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6869
6870         data = r8168_mac_ocp_read(tp, 0xe8de);
6871         data &= ~(1 << 14);
6872         r8168_mac_ocp_write(tp, 0xe8de, data);
6873
6874         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6875                 return;
6876
6877         data = r8168_mac_ocp_read(tp, 0xe8de);
6878         data |= (1 << 15);
6879         r8168_mac_ocp_write(tp, 0xe8de, data);
6880
6881         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6882 }
6883
6884 static void rtl_hw_initialize(struct rtl8169_private *tp)
6885 {
6886         switch (tp->mac_version) {
6887         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6888                 rtl8168ep_stop_cmac(tp);
6889                 /* fall through */
6890         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6891                 rtl_hw_init_8168g(tp);
6892                 break;
6893         default:
6894                 break;
6895         }
6896 }
6897
6898 static int rtl_jumbo_max(struct rtl8169_private *tp)
6899 {
6900         /* Non-GBit versions don't support jumbo frames */
6901         if (!tp->supports_gmii)
6902                 return JUMBO_1K;
6903
6904         switch (tp->mac_version) {
6905         /* RTL8169 */
6906         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6907                 return JUMBO_7K;
6908         /* RTL8168b */
6909         case RTL_GIGA_MAC_VER_11:
6910         case RTL_GIGA_MAC_VER_12:
6911         case RTL_GIGA_MAC_VER_17:
6912                 return JUMBO_4K;
6913         /* RTL8168c */
6914         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6915                 return JUMBO_6K;
6916         default:
6917                 return JUMBO_9K;
6918         }
6919 }
6920
6921 static void rtl_disable_clk(void *data)
6922 {
6923         clk_disable_unprepare(data);
6924 }
6925
6926 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6927 {
6928         struct device *d = tp_to_dev(tp);
6929         struct clk *clk;
6930         int rc;
6931
6932         clk = devm_clk_get(d, "ether_clk");
6933         if (IS_ERR(clk)) {
6934                 rc = PTR_ERR(clk);
6935                 if (rc == -ENOENT)
6936                         /* clk-core allows NULL (for suspend / resume) */
6937                         rc = 0;
6938                 else if (rc != -EPROBE_DEFER)
6939                         dev_err(d, "failed to get clk: %d\n", rc);
6940         } else {
6941                 tp->clk = clk;
6942                 rc = clk_prepare_enable(clk);
6943                 if (rc)
6944                         dev_err(d, "failed to enable clk: %d\n", rc);
6945                 else
6946                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6947         }
6948
6949         return rc;
6950 }
6951
6952 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6953 {
6954         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6955         /* align to u16 for is_valid_ether_addr() */
6956         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
6957         struct rtl8169_private *tp;
6958         struct net_device *dev;
6959         int chipset, region, i;
6960         int jumbo_max, rc;
6961
6962         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6963         if (!dev)
6964                 return -ENOMEM;
6965
6966         SET_NETDEV_DEV(dev, &pdev->dev);
6967         dev->netdev_ops = &rtl_netdev_ops;
6968         tp = netdev_priv(dev);
6969         tp->dev = dev;
6970         tp->pci_dev = pdev;
6971         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6972         tp->supports_gmii = cfg->has_gmii;
6973
6974         /* Get the *optional* external "ether_clk" used on some boards */
6975         rc = rtl_get_ether_clk(tp);
6976         if (rc)
6977                 return rc;
6978
6979         /* Disable ASPM completely as that cause random device stop working
6980          * problems as well as full system hangs for some PCIe devices users.
6981          */
6982         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
6983
6984         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6985         rc = pcim_enable_device(pdev);
6986         if (rc < 0) {
6987                 dev_err(&pdev->dev, "enable failure\n");
6988                 return rc;
6989         }
6990
6991         if (pcim_set_mwi(pdev) < 0)
6992                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6993
6994         /* use first MMIO region */
6995         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6996         if (region < 0) {
6997                 dev_err(&pdev->dev, "no MMIO resource found\n");
6998                 return -ENODEV;
6999         }
7000
7001         /* check for weird/broken PCI region reporting */
7002         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7003                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7004                 return -ENODEV;
7005         }
7006
7007         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7008         if (rc < 0) {
7009                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7010                 return rc;
7011         }
7012
7013         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7014
7015         /* Identify chip attached to board */
7016         rtl8169_get_mac_version(tp);
7017         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7018                 return -ENODEV;
7019
7020         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7021
7022         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7023             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7024                 dev->features |= NETIF_F_HIGHDMA;
7025         } else {
7026                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7027                 if (rc < 0) {
7028                         dev_err(&pdev->dev, "DMA configuration failed\n");
7029                         return rc;
7030                 }
7031         }
7032
7033         rtl_init_rxcfg(tp);
7034
7035         rtl8169_irq_mask_and_ack(tp);
7036
7037         rtl_hw_initialize(tp);
7038
7039         rtl_hw_reset(tp);
7040
7041         pci_set_master(pdev);
7042
7043         chipset = tp->mac_version;
7044
7045         rc = rtl_alloc_irq(tp);
7046         if (rc < 0) {
7047                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7048                 return rc;
7049         }
7050
7051         mutex_init(&tp->wk.mutex);
7052         INIT_WORK(&tp->wk.work, rtl_task);
7053         u64_stats_init(&tp->rx_stats.syncp);
7054         u64_stats_init(&tp->tx_stats.syncp);
7055
7056         /* get MAC address */
7057         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7058         if (rc)
7059                 rtl_read_mac_address(tp, mac_addr);
7060
7061         if (is_valid_ether_addr(mac_addr))
7062                 rtl_rar_set(tp, mac_addr);
7063
7064         for (i = 0; i < ETH_ALEN; i++)
7065                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7066
7067         dev->ethtool_ops = &rtl8169_ethtool_ops;
7068
7069         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7070
7071         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7072          * properly for all devices */
7073         dev->features |= NETIF_F_RXCSUM |
7074                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7075
7076         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7077                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7078                 NETIF_F_HW_VLAN_CTAG_RX;
7079         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7080                 NETIF_F_HIGHDMA;
7081         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7082
7083         tp->cp_cmd |= RxChkSum | RxVlan;
7084
7085         /*
7086          * Pretend we are using VLANs; This bypasses a nasty bug where
7087          * Interrupts stop flowing on high load on 8110SCd controllers.
7088          */
7089         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7090                 /* Disallow toggling */
7091                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7092
7093         if (rtl_chip_supports_csum_v2(tp))
7094                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7095
7096         dev->hw_features |= NETIF_F_RXALL;
7097         dev->hw_features |= NETIF_F_RXFCS;
7098
7099         /* MTU range: 60 - hw-specific max */
7100         dev->min_mtu = ETH_ZLEN;
7101         jumbo_max = rtl_jumbo_max(tp);
7102         dev->max_mtu = jumbo_max;
7103
7104         tp->hw_start = cfg->hw_start;
7105         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7106         tp->coalesce_info = cfg->coalesce_info;
7107
7108         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7109
7110         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7111                                             &tp->counters_phys_addr,
7112                                             GFP_KERNEL);
7113         if (!tp->counters)
7114                 return -ENOMEM;
7115
7116         pci_set_drvdata(pdev, dev);
7117
7118         rc = r8169_mdio_register(tp);
7119         if (rc)
7120                 return rc;
7121
7122         /* chip gets powered up in rtl_open() */
7123         rtl_pll_power_down(tp);
7124
7125         rc = register_netdev(dev);
7126         if (rc)
7127                 goto err_mdio_unregister;
7128
7129         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7130                    rtl_chip_infos[chipset].name, dev->dev_addr,
7131                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7132                    pci_irq_vector(pdev, 0));
7133
7134         if (jumbo_max > JUMBO_1K)
7135                 netif_info(tp, probe, dev,
7136                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7137                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7138                            "ok" : "ko");
7139
7140         if (r8168_check_dash(tp))
7141                 rtl8168_driver_start(tp);
7142
7143         if (pci_dev_run_wake(pdev))
7144                 pm_runtime_put_sync(&pdev->dev);
7145
7146         return 0;
7147
7148 err_mdio_unregister:
7149         mdiobus_unregister(tp->phydev->mdio.bus);
7150         return rc;
7151 }
7152
7153 static struct pci_driver rtl8169_pci_driver = {
7154         .name           = MODULENAME,
7155         .id_table       = rtl8169_pci_tbl,
7156         .probe          = rtl_init_one,
7157         .remove         = rtl_remove_one,
7158         .shutdown       = rtl_shutdown,
7159         .driver.pm      = RTL8169_PM_OPS,
7160 };
7161
7162 module_pci_driver(rtl8169_pci_driver);