drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 #define TX_SLOTS_AVAIL(tp) \
  63         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  64
  65 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  66 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  67         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  68
  69 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  70    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  71 static const int multicast_filter_limit = 32;
  72
  73 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  74 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  75
  76 #define R8169_REGS_SIZE         256
  77 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  78 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  79 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  80 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  81 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  82
  83 #define RTL8169_TX_TIMEOUT      (6*HZ)
  84
  85 /* write/read MMIO register */
  86 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  87 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  88 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  89 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  90 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  91 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  92
  93 enum mac_version {
  94         RTL_GIGA_MAC_VER_01 = 0,
  95         RTL_GIGA_MAC_VER_02,
  96         RTL_GIGA_MAC_VER_03,
  97         RTL_GIGA_MAC_VER_04,
  98         RTL_GIGA_MAC_VER_05,
  99         RTL_GIGA_MAC_VER_06,
 100         RTL_GIGA_MAC_VER_07,
 101         RTL_GIGA_MAC_VER_08,
 102         RTL_GIGA_MAC_VER_09,
 103         RTL_GIGA_MAC_VER_10,
 104         RTL_GIGA_MAC_VER_11,
 105         RTL_GIGA_MAC_VER_12,
 106         RTL_GIGA_MAC_VER_13,
 107         RTL_GIGA_MAC_VER_14,
 108         RTL_GIGA_MAC_VER_15,
 109         RTL_GIGA_MAC_VER_16,
 110         RTL_GIGA_MAC_VER_17,
 111         RTL_GIGA_MAC_VER_18,
 112         RTL_GIGA_MAC_VER_19,
 113         RTL_GIGA_MAC_VER_20,
 114         RTL_GIGA_MAC_VER_21,
 115         RTL_GIGA_MAC_VER_22,
 116         RTL_GIGA_MAC_VER_23,
 117         RTL_GIGA_MAC_VER_24,
 118         RTL_GIGA_MAC_VER_25,
 119         RTL_GIGA_MAC_VER_26,
 120         RTL_GIGA_MAC_VER_27,
 121         RTL_GIGA_MAC_VER_28,
 122         RTL_GIGA_MAC_VER_29,
 123         RTL_GIGA_MAC_VER_30,
 124         RTL_GIGA_MAC_VER_31,
 125         RTL_GIGA_MAC_VER_32,
 126         RTL_GIGA_MAC_VER_33,
 127         RTL_GIGA_MAC_VER_34,
 128         RTL_GIGA_MAC_VER_35,
 129         RTL_GIGA_MAC_VER_36,
 130         RTL_GIGA_MAC_VER_37,
 131         RTL_GIGA_MAC_VER_38,
 132         RTL_GIGA_MAC_VER_39,
 133         RTL_GIGA_MAC_VER_40,
 134         RTL_GIGA_MAC_VER_41,
 135         RTL_GIGA_MAC_VER_42,
 136         RTL_GIGA_MAC_VER_43,
 137         RTL_GIGA_MAC_VER_44,
 138         RTL_GIGA_MAC_VER_45,
 139         RTL_GIGA_MAC_VER_46,
 140         RTL_GIGA_MAC_VER_47,
 141         RTL_GIGA_MAC_VER_48,
 142         RTL_GIGA_MAC_VER_49,
 143         RTL_GIGA_MAC_VER_50,
 144         RTL_GIGA_MAC_VER_51,
 145         RTL_GIGA_MAC_NONE   = 0xff,
 146 };
 147
 148 enum rtl_tx_desc_version {
 149         RTL_TD_0        = 0,
 150         RTL_TD_1        = 1,
 151 };
 152
 153 #define JUMBO_1K        ETH_DATA_LEN
 154 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 155 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 156 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 157 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 158
 159 #define _R(NAME,TD,FW,SZ) {     \
 160         .name = NAME,           \
 161         .txd_version = TD,      \
 162         .fw_name = FW,          \
 163         .jumbo_max = SZ,        \
 164 }
 165
 166 static const struct {
 167         const char *name;
 168         enum rtl_tx_desc_version txd_version;
 169         const char *fw_name;
 170         u16 jumbo_max;
 171 } rtl_chip_infos[] = {
 172         /* PCI devices. */
 173         [RTL_GIGA_MAC_VER_01] =
 174                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K),
 175         [RTL_GIGA_MAC_VER_02] =
 176                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K),
 177         [RTL_GIGA_MAC_VER_03] =
 178                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K),
 179         [RTL_GIGA_MAC_VER_04] =
 180                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K),
 181         [RTL_GIGA_MAC_VER_05] =
 182                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 183         [RTL_GIGA_MAC_VER_06] =
 184                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 185         /* PCI-E devices. */
 186         [RTL_GIGA_MAC_VER_07] =
 187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 188         [RTL_GIGA_MAC_VER_08] =
 189                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 190         [RTL_GIGA_MAC_VER_09] =
 191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 192         [RTL_GIGA_MAC_VER_10] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 194         [RTL_GIGA_MAC_VER_11] =
 195                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 196         [RTL_GIGA_MAC_VER_12] =
 197                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 198         [RTL_GIGA_MAC_VER_13] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 200         [RTL_GIGA_MAC_VER_14] =
 201                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 202         [RTL_GIGA_MAC_VER_15] =
 203                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 204         [RTL_GIGA_MAC_VER_16] =
 205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 206         [RTL_GIGA_MAC_VER_17] =
 207                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 208         [RTL_GIGA_MAC_VER_18] =
 209                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 210         [RTL_GIGA_MAC_VER_19] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 212         [RTL_GIGA_MAC_VER_20] =
 213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 214         [RTL_GIGA_MAC_VER_21] =
 215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 216         [RTL_GIGA_MAC_VER_22] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 218         [RTL_GIGA_MAC_VER_23] =
 219                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 220         [RTL_GIGA_MAC_VER_24] =
 221                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 222         [RTL_GIGA_MAC_VER_25] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
 224         [RTL_GIGA_MAC_VER_26] =
 225                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
 226         [RTL_GIGA_MAC_VER_27] =
 227                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 228         [RTL_GIGA_MAC_VER_28] =
 229                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 230         [RTL_GIGA_MAC_VER_29] =
 231                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 232         [RTL_GIGA_MAC_VER_30] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 234         [RTL_GIGA_MAC_VER_31] =
 235                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 236         [RTL_GIGA_MAC_VER_32] =
 237                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
 238         [RTL_GIGA_MAC_VER_33] =
 239                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
 240         [RTL_GIGA_MAC_VER_34] =
 241                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
 242         [RTL_GIGA_MAC_VER_35] =
 243                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
 244         [RTL_GIGA_MAC_VER_36] =
 245                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
 246         [RTL_GIGA_MAC_VER_37] =
 247                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,  JUMBO_1K),
 248         [RTL_GIGA_MAC_VER_38] =
 249                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,  JUMBO_9K),
 250         [RTL_GIGA_MAC_VER_39] =
 251                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
 252         [RTL_GIGA_MAC_VER_40] =
 253                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
 254         [RTL_GIGA_MAC_VER_41] =
 255                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K),
 256         [RTL_GIGA_MAC_VER_42] =
 257                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
 258         [RTL_GIGA_MAC_VER_43] =
 259                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
 260         [RTL_GIGA_MAC_VER_44] =
 261                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,  JUMBO_9K),
 262         [RTL_GIGA_MAC_VER_45] =
 263                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
 264         [RTL_GIGA_MAC_VER_46] =
 265                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
 266         [RTL_GIGA_MAC_VER_47] =
 267                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
 268         [RTL_GIGA_MAC_VER_48] =
 269                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
 270         [RTL_GIGA_MAC_VER_49] =
 271                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 272         [RTL_GIGA_MAC_VER_50] =
 273                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 274         [RTL_GIGA_MAC_VER_51] =
 275                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 276 };
 277 #undef _R
 278
 279 enum cfg_version {
 280         RTL_CFG_0 = 0x00,
 281         RTL_CFG_1,
 282         RTL_CFG_2
 283 };
 284
 285 static const struct pci_device_id rtl8169_pci_tbl[] = {
 286         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 287         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 288         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 289         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 290         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 291         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 292         { PCI_VENDOR_ID_DLINK,                  0x4300,
 293                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 294         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 295         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 296         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 297         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 298         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 299                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 300         { 0x0001,                               0x8168,
 301                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 302         {0,},
 303 };
 304
 305 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 306
 307 static int use_dac = -1;
 308 static struct {
 309         u32 msg_enable;
 310 } debug = { -1 };
 311
 312 enum rtl_registers {
 313         MAC0            = 0,    /* Ethernet hardware address. */
 314         MAC4            = 4,
 315         MAR0            = 8,    /* Multicast filter. */
 316         CounterAddrLow          = 0x10,
 317         CounterAddrHigh         = 0x14,
 318         TxDescStartAddrLow      = 0x20,
 319         TxDescStartAddrHigh     = 0x24,
 320         TxHDescStartAddrLow     = 0x28,
 321         TxHDescStartAddrHigh    = 0x2c,
 322         FLASH           = 0x30,
 323         ERSR            = 0x36,
 324         ChipCmd         = 0x37,
 325         TxPoll          = 0x38,
 326         IntrMask        = 0x3c,
 327         IntrStatus      = 0x3e,
 328
 329         TxConfig        = 0x40,
 330 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 331 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 332
 333         RxConfig        = 0x44,
 334 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 335 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 336 #define RXCFG_FIFO_SHIFT                13
 337                                         /* No threshold before first PCI xfer */
 338 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 339 #define RX_EARLY_OFF                    (1 << 11)
 340 #define RXCFG_DMA_SHIFT                 8
 341                                         /* Unlimited maximum PCI burst. */
 342 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 343
 344         RxMissed        = 0x4c,
 345         Cfg9346         = 0x50,
 346         Config0         = 0x51,
 347         Config1         = 0x52,
 348         Config2         = 0x53,
 349 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 350
 351         Config3         = 0x54,
 352         Config4         = 0x55,
 353         Config5         = 0x56,
 354         MultiIntr       = 0x5c,
 355         PHYAR           = 0x60,
 356         PHYstatus       = 0x6c,
 357         RxMaxSize       = 0xda,
 358         CPlusCmd        = 0xe0,
 359         IntrMitigate    = 0xe2,
 360
 361 #define RTL_COALESCE_MASK       0x0f
 362 #define RTL_COALESCE_SHIFT      4
 363 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 364 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 365
 366         RxDescAddrLow   = 0xe4,
 367         RxDescAddrHigh  = 0xe8,
 368         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 369
 370 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 371
 372         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 373
 374 #define TxPacketMax     (8064 >> 7)
 375 #define EarlySize       0x27
 376
 377         FuncEvent       = 0xf0,
 378         FuncEventMask   = 0xf4,
 379         FuncPresetState = 0xf8,
 380         IBCR0           = 0xf8,
 381         IBCR2           = 0xf9,
 382         IBIMR0          = 0xfa,
 383         IBISR0          = 0xfb,
 384         FuncForceEvent  = 0xfc,
 385 };
 386
 387 enum rtl8168_8101_registers {
 388         CSIDR                   = 0x64,
 389         CSIAR                   = 0x68,
 390 #define CSIAR_FLAG                      0x80000000
 391 #define CSIAR_WRITE_CMD                 0x80000000
 392 #define CSIAR_BYTE_ENABLE               0x0000f000
 393 #define CSIAR_ADDR_MASK                 0x00000fff
 394         PMCH                    = 0x6f,
 395         EPHYAR                  = 0x80,
 396 #define EPHYAR_FLAG                     0x80000000
 397 #define EPHYAR_WRITE_CMD                0x80000000
 398 #define EPHYAR_REG_MASK                 0x1f
 399 #define EPHYAR_REG_SHIFT                16
 400 #define EPHYAR_DATA_MASK                0xffff
 401         DLLPR                   = 0xd0,
 402 #define PFM_EN                          (1 << 6)
 403 #define TX_10M_PS_EN                    (1 << 7)
 404         DBG_REG                 = 0xd1,
 405 #define FIX_NAK_1                       (1 << 4)
 406 #define FIX_NAK_2                       (1 << 3)
 407         TWSI                    = 0xd2,
 408         MCU                     = 0xd3,
 409 #define NOW_IS_OOB                      (1 << 7)
 410 #define TX_EMPTY                        (1 << 5)
 411 #define RX_EMPTY                        (1 << 4)
 412 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 413 #define EN_NDP                          (1 << 3)
 414 #define EN_OOB_RESET                    (1 << 2)
 415 #define LINK_LIST_RDY                   (1 << 1)
 416         EFUSEAR                 = 0xdc,
 417 #define EFUSEAR_FLAG                    0x80000000
 418 #define EFUSEAR_WRITE_CMD               0x80000000
 419 #define EFUSEAR_READ_CMD                0x00000000
 420 #define EFUSEAR_REG_MASK                0x03ff
 421 #define EFUSEAR_REG_SHIFT               8
 422 #define EFUSEAR_DATA_MASK               0xff
 423         MISC_1                  = 0xf2,
 424 #define PFM_D3COLD_EN                   (1 << 6)
 425 };
 426
 427 enum rtl8168_registers {
 428         LED_FREQ                = 0x1a,
 429         EEE_LED                 = 0x1b,
 430         ERIDR                   = 0x70,
 431         ERIAR                   = 0x74,
 432 #define ERIAR_FLAG                      0x80000000
 433 #define ERIAR_WRITE_CMD                 0x80000000
 434 #define ERIAR_READ_CMD                  0x00000000
 435 #define ERIAR_ADDR_BYTE_ALIGN           4
 436 #define ERIAR_TYPE_SHIFT                16
 437 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 438 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 439 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 440 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 441 #define ERIAR_MASK_SHIFT                12
 442 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 443 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 444 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 445 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 446 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 447         EPHY_RXER_NUM           = 0x7c,
 448         OCPDR                   = 0xb0, /* OCP GPHY access */
 449 #define OCPDR_WRITE_CMD                 0x80000000
 450 #define OCPDR_READ_CMD                  0x00000000
 451 #define OCPDR_REG_MASK                  0x7f
 452 #define OCPDR_GPHY_REG_SHIFT            16
 453 #define OCPDR_DATA_MASK                 0xffff
 454         OCPAR                   = 0xb4,
 455 #define OCPAR_FLAG                      0x80000000
 456 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 457 #define OCPAR_GPHY_READ_CMD             0x0000f060
 458         GPHY_OCP                = 0xb8,
 459         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 460         MISC                    = 0xf0, /* 8168e only. */
 461 #define TXPLA_RST                       (1 << 29)
 462 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 463 #define PWM_EN                          (1 << 22)
 464 #define RXDV_GATED_EN                   (1 << 19)
 465 #define EARLY_TALLY_EN                  (1 << 16)
 466 };
 467
 468 enum rtl_register_content {
 469         /* InterruptStatusBits */
 470         SYSErr          = 0x8000,
 471         PCSTimeout      = 0x4000,
 472         SWInt           = 0x0100,
 473         TxDescUnavail   = 0x0080,
 474         RxFIFOOver      = 0x0040,
 475         LinkChg         = 0x0020,
 476         RxOverflow      = 0x0010,
 477         TxErr           = 0x0008,
 478         TxOK            = 0x0004,
 479         RxErr           = 0x0002,
 480         RxOK            = 0x0001,
 481
 482         /* RxStatusDesc */
 483         RxBOVF  = (1 << 24),
 484         RxFOVF  = (1 << 23),
 485         RxRWT   = (1 << 22),
 486         RxRES   = (1 << 21),
 487         RxRUNT  = (1 << 20),
 488         RxCRC   = (1 << 19),
 489
 490         /* ChipCmdBits */
 491         StopReq         = 0x80,
 492         CmdReset        = 0x10,
 493         CmdRxEnb        = 0x08,
 494         CmdTxEnb        = 0x04,
 495         RxBufEmpty      = 0x01,
 496
 497         /* TXPoll register p.5 */
 498         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 499         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 500         FSWInt          = 0x01,         /* Forced software interrupt */
 501
 502         /* Cfg9346Bits */
 503         Cfg9346_Lock    = 0x00,
 504         Cfg9346_Unlock  = 0xc0,
 505
 506         /* rx_mode_bits */
 507         AcceptErr       = 0x20,
 508         AcceptRunt      = 0x10,
 509         AcceptBroadcast = 0x08,
 510         AcceptMulticast = 0x04,
 511         AcceptMyPhys    = 0x02,
 512         AcceptAllPhys   = 0x01,
 513 #define RX_CONFIG_ACCEPT_MASK           0x3f
 514
 515         /* TxConfigBits */
 516         TxInterFrameGapShift = 24,
 517         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 518
 519         /* Config1 register p.24 */
 520         LEDS1           = (1 << 7),
 521         LEDS0           = (1 << 6),
 522         Speed_down      = (1 << 4),
 523         MEMMAP          = (1 << 3),
 524         IOMAP           = (1 << 2),
 525         VPD             = (1 << 1),
 526         PMEnable        = (1 << 0),     /* Power Management Enable */
 527
 528         /* Config2 register p. 25 */
 529         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 530         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 531         PCI_Clock_66MHz = 0x01,
 532         PCI_Clock_33MHz = 0x00,
 533
 534         /* Config3 register p.25 */
 535         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 536         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 537         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 538         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 539         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 540
 541         /* Config4 register */
 542         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 543
 544         /* Config5 register p.27 */
 545         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 546         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 547         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 548         Spi_en          = (1 << 3),
 549         LanWake         = (1 << 1),     /* LanWake enable/disable */
 550         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 551         ASPM_en         = (1 << 0),     /* ASPM enable */
 552
 553         /* CPlusCmd p.31 */
 554         EnableBist      = (1 << 15),    // 8168 8101
 555         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 556         Normal_mode     = (1 << 13),    // unused
 557         Force_half_dup  = (1 << 12),    // 8168 8101
 558         Force_rxflow_en = (1 << 11),    // 8168 8101
 559         Force_txflow_en = (1 << 10),    // 8168 8101
 560         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 561         ASF             = (1 << 8),     // 8168 8101
 562         PktCntrDisable  = (1 << 7),     // 8168 8101
 563         Mac_dbgo_sel    = 0x001c,       // 8168
 564         RxVlan          = (1 << 6),
 565         RxChkSum        = (1 << 5),
 566         PCIDAC          = (1 << 4),
 567         PCIMulRW        = (1 << 3),
 568 #define INTT_MASK       GENMASK(1, 0)
 569         INTT_0          = 0x0000,       // 8168
 570         INTT_1          = 0x0001,       // 8168
 571         INTT_2          = 0x0002,       // 8168
 572         INTT_3          = 0x0003,       // 8168
 573
 574         /* rtl8169_PHYstatus */
 575         TBI_Enable      = 0x80,
 576         TxFlowCtrl      = 0x40,
 577         RxFlowCtrl      = 0x20,
 578         _1000bpsF       = 0x10,
 579         _100bps         = 0x08,
 580         _10bps          = 0x04,
 581         LinkStatus      = 0x02,
 582         FullDup         = 0x01,
 583
 584         /* _TBICSRBit */
 585         TBILinkOK       = 0x02000000,
 586
 587         /* ResetCounterCommand */
 588         CounterReset    = 0x1,
 589
 590         /* DumpCounterCommand */
 591         CounterDump     = 0x8,
 592
 593         /* magic enable v2 */
 594         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 595 };
 596
 597 enum rtl_desc_bit {
 598         /* First doubleword. */
 599         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 600         RingEnd         = (1 << 30), /* End of descriptor ring */
 601         FirstFrag       = (1 << 29), /* First segment of a packet */
 602         LastFrag        = (1 << 28), /* Final segment of a packet */
 603 };
 604
 605 /* Generic case. */
 606 enum rtl_tx_desc_bit {
 607         /* First doubleword. */
 608         TD_LSO          = (1 << 27),            /* Large Send Offload */
 609 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 610
 611         /* Second doubleword. */
 612         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 613 };
 614
 615 /* 8169, 8168b and 810x except 8102e. */
 616 enum rtl_tx_desc_bit_0 {
 617         /* First doubleword. */
 618 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 619         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 620         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 621         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 622 };
 623
 624 /* 8102e, 8168c and beyond. */
 625 enum rtl_tx_desc_bit_1 {
 626         /* First doubleword. */
 627         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 628         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 629 #define GTTCPHO_SHIFT                   18
 630 #define GTTCPHO_MAX                     0x7fU
 631
 632         /* Second doubleword. */
 633 #define TCPHO_SHIFT                     18
 634 #define TCPHO_MAX                       0x3ffU
 635 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 636         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 637         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 638         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 639         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 640 };
 641
 642 enum rtl_rx_desc_bit {
 643         /* Rx private */
 644         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 645         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 646
 647 #define RxProtoUDP      (PID1)
 648 #define RxProtoTCP      (PID0)
 649 #define RxProtoIP       (PID1 | PID0)
 650 #define RxProtoMask     RxProtoIP
 651
 652         IPFail          = (1 << 16), /* IP checksum failed */
 653         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 654         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 655         RxVlanTag       = (1 << 16), /* VLAN tag available */
 656 };
 657
 658 #define RsvdMask        0x3fffc000
 659 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 660
 661 struct TxDesc {
 662         __le32 opts1;
 663         __le32 opts2;
 664         __le64 addr;
 665 };
 666
 667 struct RxDesc {
 668         __le32 opts1;
 669         __le32 opts2;
 670         __le64 addr;
 671 };
 672
 673 struct ring_info {
 674         struct sk_buff  *skb;
 675         u32             len;
 676         u8              __pad[sizeof(void *) - sizeof(u32)];
 677 };
 678
 679 struct rtl8169_counters {
 680         __le64  tx_packets;
 681         __le64  rx_packets;
 682         __le64  tx_errors;
 683         __le32  rx_errors;
 684         __le16  rx_missed;
 685         __le16  align_errors;
 686         __le32  tx_one_collision;
 687         __le32  tx_multi_collision;
 688         __le64  rx_unicast;
 689         __le64  rx_broadcast;
 690         __le32  rx_multicast;
 691         __le16  tx_aborted;
 692         __le16  tx_underun;
 693 };
 694
 695 struct rtl8169_tc_offsets {
 696         bool    inited;
 697         __le64  tx_errors;
 698         __le32  tx_multi_collision;
 699         __le16  tx_aborted;
 700 };
 701
 702 enum rtl_flag {
 703         RTL_FLAG_TASK_ENABLED,
 704         RTL_FLAG_TASK_SLOW_PENDING,
 705         RTL_FLAG_TASK_RESET_PENDING,
 706         RTL_FLAG_MAX
 707 };
 708
 709 struct rtl8169_stats {
 710         u64                     packets;
 711         u64                     bytes;
 712         struct u64_stats_sync   syncp;
 713 };
 714
 715 struct rtl8169_private {
 716         void __iomem *mmio_addr;        /* memory map physical address */
 717         struct pci_dev *pci_dev;
 718         struct net_device *dev;
 719         struct napi_struct napi;
 720         u32 msg_enable;
 721         u16 mac_version;
 722         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 723         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 724         u32 dirty_tx;
 725         struct rtl8169_stats rx_stats;
 726         struct rtl8169_stats tx_stats;
 727         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 728         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 729         dma_addr_t TxPhyAddr;
 730         dma_addr_t RxPhyAddr;
 731         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 732         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 733         u16 cp_cmd;
 734
 735         u16 event_slow;
 736         const struct rtl_coalesce_info *coalesce_info;
 737
 738         struct mdio_ops {
 739                 void (*write)(struct rtl8169_private *, int, int);
 740                 int (*read)(struct rtl8169_private *, int);
 741         } mdio_ops;
 742
 743         struct jumbo_ops {
 744                 void (*enable)(struct rtl8169_private *);
 745                 void (*disable)(struct rtl8169_private *);
 746         } jumbo_ops;
 747
 748         void (*hw_start)(struct rtl8169_private *tp);
 749         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 750
 751         struct {
 752                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 753                 struct mutex mutex;
 754                 struct work_struct work;
 755         } wk;
 756
 757         struct mii_if_info mii;
 758         struct mii_bus *mii_bus;
 759         dma_addr_t counters_phys_addr;
 760         struct rtl8169_counters *counters;
 761         struct rtl8169_tc_offsets tc_offset;
 762         u32 saved_wolopts;
 763
 764         struct rtl_fw {
 765                 const struct firmware *fw;
 766
 767 #define RTL_VER_SIZE            32
 768
 769                 char version[RTL_VER_SIZE];
 770
 771                 struct rtl_fw_phy_action {
 772                         __le32 *code;
 773                         size_t size;
 774                 } phy_action;
 775         } *rtl_fw;
 776 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 777
 778         u32 ocp_base;
 779 };
 780
 781 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 782 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 783 module_param(use_dac, int, 0);
 784 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 785 module_param_named(debug, debug.msg_enable, int, 0);
 786 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 787 MODULE_LICENSE("GPL");
 788 MODULE_VERSION(RTL8169_VERSION);
 789 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 790 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 791 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 792 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 793 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 794 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 795 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 796 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 797 MODULE_FIRMWARE(FIRMWARE_8402_1);
 798 MODULE_FIRMWARE(FIRMWARE_8411_1);
 799 MODULE_FIRMWARE(FIRMWARE_8411_2);
 800 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 801 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 802 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 803 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 804 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 805 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 806 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 807 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 808
 809 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 810 {
 811         return &tp->pci_dev->dev;
 812 }
 813
 814 static void rtl_lock_work(struct rtl8169_private *tp)
 815 {
 816         mutex_lock(&tp->wk.mutex);
 817 }
 818
 819 static void rtl_unlock_work(struct rtl8169_private *tp)
 820 {
 821         mutex_unlock(&tp->wk.mutex);
 822 }
 823
 824 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 825 {
 826         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 827                                            PCI_EXP_DEVCTL_READRQ, force);
 828 }
 829
 830 struct rtl_cond {
 831         bool (*check)(struct rtl8169_private *);
 832         const char *msg;
 833 };
 834
 835 static void rtl_udelay(unsigned int d)
 836 {
 837         udelay(d);
 838 }
 839
 840 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 841                           void (*delay)(unsigned int), unsigned int d, int n,
 842                           bool high)
 843 {
 844         int i;
 845
 846         for (i = 0; i < n; i++) {
 847                 delay(d);
 848                 if (c->check(tp) == high)
 849                         return true;
 850         }
 851         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 852                   c->msg, !high, n, d);
 853         return false;
 854 }
 855
 856 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 857                                       const struct rtl_cond *c,
 858                                       unsigned int d, int n)
 859 {
 860         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 861 }
 862
 863 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 864                                      const struct rtl_cond *c,
 865                                      unsigned int d, int n)
 866 {
 867         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 868 }
 869
 870 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 871                                       const struct rtl_cond *c,
 872                                       unsigned int d, int n)
 873 {
 874         return rtl_loop_wait(tp, c, msleep, d, n, true);
 875 }
 876
 877 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 878                                      const struct rtl_cond *c,
 879                                      unsigned int d, int n)
 880 {
 881         return rtl_loop_wait(tp, c, msleep, d, n, false);
 882 }
 883
 884 #define DECLARE_RTL_COND(name)                          \
 885 static bool name ## _check(struct rtl8169_private *);   \
 886                                                         \
 887 static const struct rtl_cond name = {                   \
 888         .check  = name ## _check,                       \
 889         .msg    = #name                                 \
 890 };                                                      \
 891                                                         \
 892 static bool name ## _check(struct rtl8169_private *tp)
 893
 894 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 895 {
 896         if (reg & 0xffff0001) {
 897                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 898                 return true;
 899         }
 900         return false;
 901 }
 902
 903 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 904 {
 905         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 906 }
 907
 908 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 909 {
 910         if (rtl_ocp_reg_failure(tp, reg))
 911                 return;
 912
 913         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 914
 915         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 916 }
 917
 918 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 919 {
 920         if (rtl_ocp_reg_failure(tp, reg))
 921                 return 0;
 922
 923         RTL_W32(tp, GPHY_OCP, reg << 15);
 924
 925         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 926                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 927 }
 928
 929 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 930 {
 931         if (rtl_ocp_reg_failure(tp, reg))
 932                 return;
 933
 934         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 935 }
 936
 937 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 938 {
 939         if (rtl_ocp_reg_failure(tp, reg))
 940                 return 0;
 941
 942         RTL_W32(tp, OCPDR, reg << 15);
 943
 944         return RTL_R32(tp, OCPDR);
 945 }
 946
 947 #define OCP_STD_PHY_BASE        0xa400
 948
 949 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 950 {
 951         if (reg == 0x1f) {
 952                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 953                 return;
 954         }
 955
 956         if (tp->ocp_base != OCP_STD_PHY_BASE)
 957                 reg -= 0x10;
 958
 959         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 960 }
 961
 962 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 963 {
 964         if (tp->ocp_base != OCP_STD_PHY_BASE)
 965                 reg -= 0x10;
 966
 967         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 968 }
 969
 970 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 971 {
 972         if (reg == 0x1f) {
 973                 tp->ocp_base = value << 4;
 974                 return;
 975         }
 976
 977         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 978 }
 979
 980 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 981 {
 982         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 983 }
 984
 985 DECLARE_RTL_COND(rtl_phyar_cond)
 986 {
 987         return RTL_R32(tp, PHYAR) & 0x80000000;
 988 }
 989
 990 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 991 {
 992         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 993
 994         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 995         /*
 996          * According to hardware specs a 20us delay is required after write
 997          * complete indication, but before sending next command.
 998          */
 999         udelay(20);
1000 }
1001
1002 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1003 {
1004         int value;
1005
1006         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1007
1008         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1009                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1010
1011         /*
1012          * According to hardware specs a 20us delay is required after read
1013          * complete indication, but before sending next command.
1014          */
1015         udelay(20);
1016
1017         return value;
1018 }
1019
1020 DECLARE_RTL_COND(rtl_ocpar_cond)
1021 {
1022         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1023 }
1024
1025 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1026 {
1027         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1028         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1029         RTL_W32(tp, EPHY_RXER_NUM, 0);
1030
1031         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1032 }
1033
1034 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1035 {
1036         r8168dp_1_mdio_access(tp, reg,
1037                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1038 }
1039
1040 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1041 {
1042         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1043
1044         mdelay(1);
1045         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1046         RTL_W32(tp, EPHY_RXER_NUM, 0);
1047
1048         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1049                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1050 }
1051
1052 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1053
1054 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1055 {
1056         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1057 }
1058
1059 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1060 {
1061         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1062 }
1063
1064 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 {
1066         r8168dp_2_mdio_start(tp);
1067
1068         r8169_mdio_write(tp, reg, value);
1069
1070         r8168dp_2_mdio_stop(tp);
1071 }
1072
1073 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1074 {
1075         int value;
1076
1077         r8168dp_2_mdio_start(tp);
1078
1079         value = r8169_mdio_read(tp, reg);
1080
1081         r8168dp_2_mdio_stop(tp);
1082
1083         return value;
1084 }
1085
1086 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1087 {
1088         tp->mdio_ops.write(tp, location, val);
1089 }
1090
1091 static int rtl_readphy(struct rtl8169_private *tp, int location)
1092 {
1093         return tp->mdio_ops.read(tp, location);
1094 }
1095
1096 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1097 {
1098         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1099 }
1100
1101 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1102 {
1103         int val;
1104
1105         val = rtl_readphy(tp, reg_addr);
1106         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1107 }
1108
1109 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1110                            int val)
1111 {
1112         struct rtl8169_private *tp = netdev_priv(dev);
1113
1114         rtl_writephy(tp, location, val);
1115 }
1116
1117 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1118 {
1119         struct rtl8169_private *tp = netdev_priv(dev);
1120
1121         return rtl_readphy(tp, location);
1122 }
1123
1124 DECLARE_RTL_COND(rtl_ephyar_cond)
1125 {
1126         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1127 }
1128
1129 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1130 {
1131         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1132                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1133
1134         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1135
1136         udelay(10);
1137 }
1138
1139 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1140 {
1141         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1142
1143         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1144                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1145 }
1146
1147 DECLARE_RTL_COND(rtl_eriar_cond)
1148 {
1149         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1150 }
1151
1152 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1153                           u32 val, int type)
1154 {
1155         BUG_ON((addr & 3) || (mask == 0));
1156         RTL_W32(tp, ERIDR, val);
1157         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1158
1159         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1160 }
1161
1162 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1163 {
1164         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1165
1166         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1167                 RTL_R32(tp, ERIDR) : ~0;
1168 }
1169
1170 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1171                          u32 m, int type)
1172 {
1173         u32 val;
1174
1175         val = rtl_eri_read(tp, addr, type);
1176         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1177 }
1178
1179 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1180 {
1181         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1182         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1183                 RTL_R32(tp, OCPDR) : ~0;
1184 }
1185
1186 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1187 {
1188         return rtl_eri_read(tp, reg, ERIAR_OOB);
1189 }
1190
1191 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1192 {
1193         switch (tp->mac_version) {
1194         case RTL_GIGA_MAC_VER_27:
1195         case RTL_GIGA_MAC_VER_28:
1196         case RTL_GIGA_MAC_VER_31:
1197                 return r8168dp_ocp_read(tp, mask, reg);
1198         case RTL_GIGA_MAC_VER_49:
1199         case RTL_GIGA_MAC_VER_50:
1200         case RTL_GIGA_MAC_VER_51:
1201                 return r8168ep_ocp_read(tp, mask, reg);
1202         default:
1203                 BUG();
1204                 return ~0;
1205         }
1206 }
1207
1208 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1209                               u32 data)
1210 {
1211         RTL_W32(tp, OCPDR, data);
1212         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1213         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1214 }
1215
1216 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1217                               u32 data)
1218 {
1219         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1220                       data, ERIAR_OOB);
1221 }
1222
1223 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1224 {
1225         switch (tp->mac_version) {
1226         case RTL_GIGA_MAC_VER_27:
1227         case RTL_GIGA_MAC_VER_28:
1228         case RTL_GIGA_MAC_VER_31:
1229                 r8168dp_ocp_write(tp, mask, reg, data);
1230                 break;
1231         case RTL_GIGA_MAC_VER_49:
1232         case RTL_GIGA_MAC_VER_50:
1233         case RTL_GIGA_MAC_VER_51:
1234                 r8168ep_ocp_write(tp, mask, reg, data);
1235                 break;
1236         default:
1237                 BUG();
1238                 break;
1239         }
1240 }
1241
1242 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1243 {
1244         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1245
1246         ocp_write(tp, 0x1, 0x30, 0x00000001);
1247 }
1248
1249 #define OOB_CMD_RESET           0x00
1250 #define OOB_CMD_DRIVER_START    0x05
1251 #define OOB_CMD_DRIVER_STOP     0x06
1252
1253 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1254 {
1255         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1256 }
1257
1258 DECLARE_RTL_COND(rtl_ocp_read_cond)
1259 {
1260         u16 reg;
1261
1262         reg = rtl8168_get_ocp_reg(tp);
1263
1264         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1265 }
1266
1267 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1268 {
1269         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1270 }
1271
1272 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1273 {
1274         return RTL_R8(tp, IBISR0) & 0x20;
1275 }
1276
1277 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1278 {
1279         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1280         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1281         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1282         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1283 }
1284
1285 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1286 {
1287         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1288         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1289 }
1290
1291 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1292 {
1293         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1294         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1295         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1296 }
1297
1298 static void rtl8168_driver_start(struct rtl8169_private *tp)
1299 {
1300         switch (tp->mac_version) {
1301         case RTL_GIGA_MAC_VER_27:
1302         case RTL_GIGA_MAC_VER_28:
1303         case RTL_GIGA_MAC_VER_31:
1304                 rtl8168dp_driver_start(tp);
1305                 break;
1306         case RTL_GIGA_MAC_VER_49:
1307         case RTL_GIGA_MAC_VER_50:
1308         case RTL_GIGA_MAC_VER_51:
1309                 rtl8168ep_driver_start(tp);
1310                 break;
1311         default:
1312                 BUG();
1313                 break;
1314         }
1315 }
1316
1317 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1318 {
1319         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1320         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1321 }
1322
1323 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1324 {
1325         rtl8168ep_stop_cmac(tp);
1326         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1327         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1328         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1329 }
1330
1331 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1332 {
1333         switch (tp->mac_version) {
1334         case RTL_GIGA_MAC_VER_27:
1335         case RTL_GIGA_MAC_VER_28:
1336         case RTL_GIGA_MAC_VER_31:
1337                 rtl8168dp_driver_stop(tp);
1338                 break;
1339         case RTL_GIGA_MAC_VER_49:
1340         case RTL_GIGA_MAC_VER_50:
1341         case RTL_GIGA_MAC_VER_51:
1342                 rtl8168ep_driver_stop(tp);
1343                 break;
1344         default:
1345                 BUG();
1346                 break;
1347         }
1348 }
1349
1350 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1351 {
1352         u16 reg = rtl8168_get_ocp_reg(tp);
1353
1354         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1355 }
1356
1357 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1358 {
1359         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1360 }
1361
1362 static bool r8168_check_dash(struct rtl8169_private *tp)
1363 {
1364         switch (tp->mac_version) {
1365         case RTL_GIGA_MAC_VER_27:
1366         case RTL_GIGA_MAC_VER_28:
1367         case RTL_GIGA_MAC_VER_31:
1368                 return r8168dp_check_dash(tp);
1369         case RTL_GIGA_MAC_VER_49:
1370         case RTL_GIGA_MAC_VER_50:
1371         case RTL_GIGA_MAC_VER_51:
1372                 return r8168ep_check_dash(tp);
1373         default:
1374                 return false;
1375         }
1376 }
1377
1378 struct exgmac_reg {
1379         u16 addr;
1380         u16 mask;
1381         u32 val;
1382 };
1383
1384 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1385                                    const struct exgmac_reg *r, int len)
1386 {
1387         while (len-- > 0) {
1388                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1389                 r++;
1390         }
1391 }
1392
1393 DECLARE_RTL_COND(rtl_efusear_cond)
1394 {
1395         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1396 }
1397
1398 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1399 {
1400         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1401
1402         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1403                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1404 }
1405
1406 static u16 rtl_get_events(struct rtl8169_private *tp)
1407 {
1408         return RTL_R16(tp, IntrStatus);
1409 }
1410
1411 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1412 {
1413         RTL_W16(tp, IntrStatus, bits);
1414         mmiowb();
1415 }
1416
1417 static void rtl_irq_disable(struct rtl8169_private *tp)
1418 {
1419         RTL_W16(tp, IntrMask, 0);
1420         mmiowb();
1421 }
1422
1423 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1424 {
1425         RTL_W16(tp, IntrMask, bits);
1426 }
1427
1428 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1429 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1430 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1431
1432 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1433 {
1434         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1435 }
1436
1437 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1438 {
1439         rtl_irq_disable(tp);
1440         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1441         RTL_R8(tp, ChipCmd);
1442 }
1443
1444 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1445 {
1446         struct net_device *dev = tp->dev;
1447
1448         if (!netif_running(dev))
1449                 return;
1450
1451         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1452             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1453                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1454                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1455                                       ERIAR_EXGMAC);
1456                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1457                                       ERIAR_EXGMAC);
1458                 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1459                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1460                                       ERIAR_EXGMAC);
1461                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1462                                       ERIAR_EXGMAC);
1463                 } else {
1464                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1465                                       ERIAR_EXGMAC);
1466                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1467                                       ERIAR_EXGMAC);
1468                 }
1469                 /* Reset packet filter */
1470                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1471                              ERIAR_EXGMAC);
1472                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1473                              ERIAR_EXGMAC);
1474         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1475                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1476                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1477                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1478                                       ERIAR_EXGMAC);
1479                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1480                                       ERIAR_EXGMAC);
1481                 } else {
1482                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1483                                       ERIAR_EXGMAC);
1484                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1485                                       ERIAR_EXGMAC);
1486                 }
1487         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1488                 if (RTL_R8(tp, PHYstatus) & _10bps) {
1489                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1490                                       ERIAR_EXGMAC);
1491                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1492                                       ERIAR_EXGMAC);
1493                 } else {
1494                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1495                                       ERIAR_EXGMAC);
1496                 }
1497         }
1498 }
1499
1500 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1501
1502 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1503 {
1504         u8 options;
1505         u32 wolopts = 0;
1506
1507         options = RTL_R8(tp, Config1);
1508         if (!(options & PMEnable))
1509                 return 0;
1510
1511         options = RTL_R8(tp, Config3);
1512         if (options & LinkUp)
1513                 wolopts |= WAKE_PHY;
1514         switch (tp->mac_version) {
1515         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1516         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1517                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1518                         wolopts |= WAKE_MAGIC;
1519                 break;
1520         default:
1521                 if (options & MagicPacket)
1522                         wolopts |= WAKE_MAGIC;
1523                 break;
1524         }
1525
1526         options = RTL_R8(tp, Config5);
1527         if (options & UWF)
1528                 wolopts |= WAKE_UCAST;
1529         if (options & BWF)
1530                 wolopts |= WAKE_BCAST;
1531         if (options & MWF)
1532                 wolopts |= WAKE_MCAST;
1533
1534         return wolopts;
1535 }
1536
1537 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1538 {
1539         struct rtl8169_private *tp = netdev_priv(dev);
1540
1541         rtl_lock_work(tp);
1542         wol->supported = WAKE_ANY;
1543         wol->wolopts = tp->saved_wolopts;
1544         rtl_unlock_work(tp);
1545 }
1546
1547 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1548 {
1549         unsigned int i, tmp;
1550         static const struct {
1551                 u32 opt;
1552                 u16 reg;
1553                 u8  mask;
1554         } cfg[] = {
1555                 { WAKE_PHY,   Config3, LinkUp },
1556                 { WAKE_UCAST, Config5, UWF },
1557                 { WAKE_BCAST, Config5, BWF },
1558                 { WAKE_MCAST, Config5, MWF },
1559                 { WAKE_ANY,   Config5, LanWake },
1560                 { WAKE_MAGIC, Config3, MagicPacket }
1561         };
1562         u8 options;
1563
1564         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1565
1566         switch (tp->mac_version) {
1567         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1568         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1569                 tmp = ARRAY_SIZE(cfg) - 1;
1570                 if (wolopts & WAKE_MAGIC)
1571                         rtl_w0w1_eri(tp,
1572                                      0x0dc,
1573                                      ERIAR_MASK_0100,
1574                                      MagicPacket_v2,
1575                                      0x0000,
1576                                      ERIAR_EXGMAC);
1577                 else
1578                         rtl_w0w1_eri(tp,
1579                                      0x0dc,
1580                                      ERIAR_MASK_0100,
1581                                      0x0000,
1582                                      MagicPacket_v2,
1583                                      ERIAR_EXGMAC);
1584                 break;
1585         default:
1586                 tmp = ARRAY_SIZE(cfg);
1587                 break;
1588         }
1589
1590         for (i = 0; i < tmp; i++) {
1591                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1592                 if (wolopts & cfg[i].opt)
1593                         options |= cfg[i].mask;
1594                 RTL_W8(tp, cfg[i].reg, options);
1595         }
1596
1597         switch (tp->mac_version) {
1598         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1599                 options = RTL_R8(tp, Config1) & ~PMEnable;
1600                 if (wolopts)
1601                         options |= PMEnable;
1602                 RTL_W8(tp, Config1, options);
1603                 break;
1604         default:
1605                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1606                 if (wolopts)
1607                         options |= PME_SIGNAL;
1608                 RTL_W8(tp, Config2, options);
1609                 break;
1610         }
1611
1612         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1613 }
1614
1615 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1616 {
1617         struct rtl8169_private *tp = netdev_priv(dev);
1618         struct device *d = tp_to_dev(tp);
1619
1620         if (wol->wolopts & ~WAKE_ANY)
1621                 return -EINVAL;
1622
1623         pm_runtime_get_noresume(d);
1624
1625         rtl_lock_work(tp);
1626
1627         tp->saved_wolopts = wol->wolopts;
1628
1629         if (pm_runtime_active(d))
1630                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1631
1632         rtl_unlock_work(tp);
1633
1634         device_set_wakeup_enable(d, tp->saved_wolopts);
1635
1636         pm_runtime_put_noidle(d);
1637
1638         return 0;
1639 }
1640
1641 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1642 {
1643         return rtl_chip_infos[tp->mac_version].fw_name;
1644 }
1645
1646 static void rtl8169_get_drvinfo(struct net_device *dev,
1647                                 struct ethtool_drvinfo *info)
1648 {
1649         struct rtl8169_private *tp = netdev_priv(dev);
1650         struct rtl_fw *rtl_fw = tp->rtl_fw;
1651
1652         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1653         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1654         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1655         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1656         if (!IS_ERR_OR_NULL(rtl_fw))
1657                 strlcpy(info->fw_version, rtl_fw->version,
1658                         sizeof(info->fw_version));
1659 }
1660
1661 static int rtl8169_get_regs_len(struct net_device *dev)
1662 {
1663         return R8169_REGS_SIZE;
1664 }
1665
1666 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1667         netdev_features_t features)
1668 {
1669         struct rtl8169_private *tp = netdev_priv(dev);
1670
1671         if (dev->mtu > TD_MSS_MAX)
1672                 features &= ~NETIF_F_ALL_TSO;
1673
1674         if (dev->mtu > JUMBO_1K &&
1675             tp->mac_version > RTL_GIGA_MAC_VER_06)
1676                 features &= ~NETIF_F_IP_CSUM;
1677
1678         return features;
1679 }
1680
1681 static int rtl8169_set_features(struct net_device *dev,
1682                                 netdev_features_t features)
1683 {
1684         struct rtl8169_private *tp = netdev_priv(dev);
1685         u32 rx_config;
1686
1687         rtl_lock_work(tp);
1688
1689         rx_config = RTL_R32(tp, RxConfig);
1690         if (features & NETIF_F_RXALL)
1691                 rx_config |= (AcceptErr | AcceptRunt);
1692         else
1693                 rx_config &= ~(AcceptErr | AcceptRunt);
1694
1695         RTL_W32(tp, RxConfig, rx_config);
1696
1697         if (features & NETIF_F_RXCSUM)
1698                 tp->cp_cmd |= RxChkSum;
1699         else
1700                 tp->cp_cmd &= ~RxChkSum;
1701
1702         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1703                 tp->cp_cmd |= RxVlan;
1704         else
1705                 tp->cp_cmd &= ~RxVlan;
1706
1707         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1708         RTL_R16(tp, CPlusCmd);
1709
1710         rtl_unlock_work(tp);
1711
1712         return 0;
1713 }
1714
1715 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1716 {
1717         return (skb_vlan_tag_present(skb)) ?
1718                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1719 }
1720
1721 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1722 {
1723         u32 opts2 = le32_to_cpu(desc->opts2);
1724
1725         if (opts2 & RxVlanTag)
1726                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1727 }
1728
1729 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1730                              void *p)
1731 {
1732         struct rtl8169_private *tp = netdev_priv(dev);
1733         u32 __iomem *data = tp->mmio_addr;
1734         u32 *dw = p;
1735         int i;
1736
1737         rtl_lock_work(tp);
1738         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1739                 memcpy_fromio(dw++, data++, 4);
1740         rtl_unlock_work(tp);
1741 }
1742
1743 static u32 rtl8169_get_msglevel(struct net_device *dev)
1744 {
1745         struct rtl8169_private *tp = netdev_priv(dev);
1746
1747         return tp->msg_enable;
1748 }
1749
1750 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1751 {
1752         struct rtl8169_private *tp = netdev_priv(dev);
1753
1754         tp->msg_enable = value;
1755 }
1756
1757 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1758         "tx_packets",
1759         "rx_packets",
1760         "tx_errors",
1761         "rx_errors",
1762         "rx_missed",
1763         "align_errors",
1764         "tx_single_collisions",
1765         "tx_multi_collisions",
1766         "unicast",
1767         "broadcast",
1768         "multicast",
1769         "tx_aborted",
1770         "tx_underrun",
1771 };
1772
1773 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1774 {
1775         switch (sset) {
1776         case ETH_SS_STATS:
1777                 return ARRAY_SIZE(rtl8169_gstrings);
1778         default:
1779                 return -EOPNOTSUPP;
1780         }
1781 }
1782
1783 DECLARE_RTL_COND(rtl_counters_cond)
1784 {
1785         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1786 }
1787
1788 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1789 {
1790         dma_addr_t paddr = tp->counters_phys_addr;
1791         u32 cmd;
1792
1793         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1794         RTL_R32(tp, CounterAddrHigh);
1795         cmd = (u64)paddr & DMA_BIT_MASK(32);
1796         RTL_W32(tp, CounterAddrLow, cmd);
1797         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1798
1799         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1800 }
1801
1802 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1803 {
1804         /*
1805          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1806          * tally counters.
1807          */
1808         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1809                 return true;
1810
1811         return rtl8169_do_counters(tp, CounterReset);
1812 }
1813
1814 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1815 {
1816         /*
1817          * Some chips are unable to dump tally counters when the receiver
1818          * is disabled.
1819          */
1820         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1821                 return true;
1822
1823         return rtl8169_do_counters(tp, CounterDump);
1824 }
1825
1826 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1827 {
1828         struct rtl8169_counters *counters = tp->counters;
1829         bool ret = false;
1830
1831         /*
1832          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1833          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1834          * reset by a power cycle, while the counter values collected by the
1835          * driver are reset at every driver unload/load cycle.
1836          *
1837          * To make sure the HW values returned by @get_stats64 match the SW
1838          * values, we collect the initial values at first open(*) and use them
1839          * as offsets to normalize the values returned by @get_stats64.
1840          *
1841          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1842          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1843          * set at open time by rtl_hw_start.
1844          */
1845
1846         if (tp->tc_offset.inited)
1847                 return true;
1848
1849         /* If both, reset and update fail, propagate to caller. */
1850         if (rtl8169_reset_counters(tp))
1851                 ret = true;
1852
1853         if (rtl8169_update_counters(tp))
1854                 ret = true;
1855
1856         tp->tc_offset.tx_errors = counters->tx_errors;
1857         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1858         tp->tc_offset.tx_aborted = counters->tx_aborted;
1859         tp->tc_offset.inited = true;
1860
1861         return ret;
1862 }
1863
1864 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1865                                       struct ethtool_stats *stats, u64 *data)
1866 {
1867         struct rtl8169_private *tp = netdev_priv(dev);
1868         struct device *d = tp_to_dev(tp);
1869         struct rtl8169_counters *counters = tp->counters;
1870
1871         ASSERT_RTNL();
1872
1873         pm_runtime_get_noresume(d);
1874
1875         if (pm_runtime_active(d))
1876                 rtl8169_update_counters(tp);
1877
1878         pm_runtime_put_noidle(d);
1879
1880         data[0] = le64_to_cpu(counters->tx_packets);
1881         data[1] = le64_to_cpu(counters->rx_packets);
1882         data[2] = le64_to_cpu(counters->tx_errors);
1883         data[3] = le32_to_cpu(counters->rx_errors);
1884         data[4] = le16_to_cpu(counters->rx_missed);
1885         data[5] = le16_to_cpu(counters->align_errors);
1886         data[6] = le32_to_cpu(counters->tx_one_collision);
1887         data[7] = le32_to_cpu(counters->tx_multi_collision);
1888         data[8] = le64_to_cpu(counters->rx_unicast);
1889         data[9] = le64_to_cpu(counters->rx_broadcast);
1890         data[10] = le32_to_cpu(counters->rx_multicast);
1891         data[11] = le16_to_cpu(counters->tx_aborted);
1892         data[12] = le16_to_cpu(counters->tx_underun);
1893 }
1894
1895 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1896 {
1897         switch(stringset) {
1898         case ETH_SS_STATS:
1899                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1900                 break;
1901         }
1902 }
1903
1904 /*
1905  * Interrupt coalescing
1906  *
1907  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1908  * >     8169, 8168 and 810x line of chipsets
1909  *
1910  * 8169, 8168, and 8136(810x) serial chipsets support it.
1911  *
1912  * > 2 - the Tx timer unit at gigabit speed
1913  *
1914  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1915  * (0xe0) bit 1 and bit 0.
1916  *
1917  * For 8169
1918  * bit[1:0] \ speed        1000M           100M            10M
1919  * 0 0                     320ns           2.56us          40.96us
1920  * 0 1                     2.56us          20.48us         327.7us
1921  * 1 0                     5.12us          40.96us         655.4us
1922  * 1 1                     10.24us         81.92us         1.31ms
1923  *
1924  * For the other
1925  * bit[1:0] \ speed        1000M           100M            10M
1926  * 0 0                     5us             2.56us          40.96us
1927  * 0 1                     40us            20.48us         327.7us
1928  * 1 0                     80us            40.96us         655.4us
1929  * 1 1                     160us           81.92us         1.31ms
1930  */
1931
1932 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1933 struct rtl_coalesce_scale {
1934         /* Rx / Tx */
1935         u32 nsecs[2];
1936 };
1937
1938 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1939 struct rtl_coalesce_info {
1940         u32 speed;
1941         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1942 };
1943
1944 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1945 #define rxtx_x1822(r, t) {              \
1946         {{(r),          (t)}},          \
1947         {{(r)*8,        (t)*8}},        \
1948         {{(r)*8*2,      (t)*8*2}},      \
1949         {{(r)*8*2*2,    (t)*8*2*2}},    \
1950 }
1951 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1952         /* speed        delays:     rx00   tx00 */
1953         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1954         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1955         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1956         { 0 },
1957 };
1958
1959 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1960         /* speed        delays:     rx00   tx00 */
1961         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1962         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1963         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1964         { 0 },
1965 };
1966 #undef rxtx_x1822
1967
1968 /* get rx/tx scale vector corresponding to current speed */
1969 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1970 {
1971         struct rtl8169_private *tp = netdev_priv(dev);
1972         struct ethtool_link_ksettings ecmd;
1973         const struct rtl_coalesce_info *ci;
1974         int rc;
1975
1976         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1977         if (rc < 0)
1978                 return ERR_PTR(rc);
1979
1980         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1981                 if (ecmd.base.speed == ci->speed) {
1982                         return ci;
1983                 }
1984         }
1985
1986         return ERR_PTR(-ELNRNG);
1987 }
1988
1989 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1990 {
1991         struct rtl8169_private *tp = netdev_priv(dev);
1992         const struct rtl_coalesce_info *ci;
1993         const struct rtl_coalesce_scale *scale;
1994         struct {
1995                 u32 *max_frames;
1996                 u32 *usecs;
1997         } coal_settings [] = {
1998                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1999                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2000         }, *p = coal_settings;
2001         int i;
2002         u16 w;
2003
2004         memset(ec, 0, sizeof(*ec));
2005
2006         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2007         ci = rtl_coalesce_info(dev);
2008         if (IS_ERR(ci))
2009                 return PTR_ERR(ci);
2010
2011         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
2012
2013         /* read IntrMitigate and adjust according to scale */
2014         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2015                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2016                 w >>= RTL_COALESCE_SHIFT;
2017                 *p->usecs = w & RTL_COALESCE_MASK;
2018         }
2019
2020         for (i = 0; i < 2; i++) {
2021                 p = coal_settings + i;
2022                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2023
2024                 /*
2025                  * ethtool_coalesce says it is illegal to set both usecs and
2026                  * max_frames to 0.
2027                  */
2028                 if (!*p->usecs && !*p->max_frames)
2029                         *p->max_frames = 1;
2030         }
2031
2032         return 0;
2033 }
2034
2035 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2036 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2037                         struct net_device *dev, u32 nsec, u16 *cp01)
2038 {
2039         const struct rtl_coalesce_info *ci;
2040         u16 i;
2041
2042         ci = rtl_coalesce_info(dev);
2043         if (IS_ERR(ci))
2044                 return ERR_CAST(ci);
2045
2046         for (i = 0; i < 4; i++) {
2047                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2048                                         ci->scalev[i].nsecs[1]);
2049                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2050                         *cp01 = i;
2051                         return &ci->scalev[i];
2052                 }
2053         }
2054
2055         return ERR_PTR(-EINVAL);
2056 }
2057
2058 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2059 {
2060         struct rtl8169_private *tp = netdev_priv(dev);
2061         const struct rtl_coalesce_scale *scale;
2062         struct {
2063                 u32 frames;
2064                 u32 usecs;
2065         } coal_settings [] = {
2066                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2067                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2068         }, *p = coal_settings;
2069         u16 w = 0, cp01;
2070         int i;
2071
2072         scale = rtl_coalesce_choose_scale(dev,
2073                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2074         if (IS_ERR(scale))
2075                 return PTR_ERR(scale);
2076
2077         for (i = 0; i < 2; i++, p++) {
2078                 u32 units;
2079
2080                 /*
2081                  * accept max_frames=1 we returned in rtl_get_coalesce.
2082                  * accept it not only when usecs=0 because of e.g. the following scenario:
2083                  *
2084                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2085                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2086                  * - then user does `ethtool -C eth0 rx-usecs 100`
2087                  *
2088                  * since ethtool sends to kernel whole ethtool_coalesce
2089                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2090                  * we'll reject it below in `frames % 4 != 0`.
2091                  */
2092                 if (p->frames == 1) {
2093                         p->frames = 0;
2094                 }
2095
2096                 units = p->usecs * 1000 / scale->nsecs[i];
2097                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2098                         return -EINVAL;
2099
2100                 w <<= RTL_COALESCE_SHIFT;
2101                 w |= units;
2102                 w <<= RTL_COALESCE_SHIFT;
2103                 w |= p->frames >> 2;
2104         }
2105
2106         rtl_lock_work(tp);
2107
2108         RTL_W16(tp, IntrMitigate, swab16(w));
2109
2110         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2111         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2112         RTL_R16(tp, CPlusCmd);
2113
2114         rtl_unlock_work(tp);
2115
2116         return 0;
2117 }
2118
2119 static const struct ethtool_ops rtl8169_ethtool_ops = {
2120         .get_drvinfo            = rtl8169_get_drvinfo,
2121         .get_regs_len           = rtl8169_get_regs_len,
2122         .get_link               = ethtool_op_get_link,
2123         .get_coalesce           = rtl_get_coalesce,
2124         .set_coalesce           = rtl_set_coalesce,
2125         .get_msglevel           = rtl8169_get_msglevel,
2126         .set_msglevel           = rtl8169_set_msglevel,
2127         .get_regs               = rtl8169_get_regs,
2128         .get_wol                = rtl8169_get_wol,
2129         .set_wol                = rtl8169_set_wol,
2130         .get_strings            = rtl8169_get_strings,
2131         .get_sset_count         = rtl8169_get_sset_count,
2132         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2133         .get_ts_info            = ethtool_op_get_ts_info,
2134         .nway_reset             = phy_ethtool_nway_reset,
2135         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2136         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2137 };
2138
2139 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2140                                     u8 default_version)
2141 {
2142         /*
2143          * The driver currently handles the 8168Bf and the 8168Be identically
2144          * but they can be identified more specifically through the test below
2145          * if needed:
2146          *
2147          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2148          *
2149          * Same thing for the 8101Eb and the 8101Ec:
2150          *
2151          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2152          */
2153         static const struct rtl_mac_info {
2154                 u32 mask;
2155                 u32 val;
2156                 int mac_version;
2157         } mac_info[] = {
2158                 /* 8168EP family. */
2159                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2160                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2161                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2162
2163                 /* 8168H family. */
2164                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2165                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2166
2167                 /* 8168G family. */
2168                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2169                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2170                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2171                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2172
2173                 /* 8168F family. */
2174                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2175                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2176                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2177
2178                 /* 8168E family. */
2179                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2180                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2181                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2182
2183                 /* 8168D family. */
2184                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2185                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2186
2187                 /* 8168DP family. */
2188                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2189                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2190                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2191
2192                 /* 8168C family. */
2193                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2194                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2195                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2196                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2197                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2198                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2199                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2200
2201                 /* 8168B family. */
2202                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2203                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2204                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2205
2206                 /* 8101 family. */
2207                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2208                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2209                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2210                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2211                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2212                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2213                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2214                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2215                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2216                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2217                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2218                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2219                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2220                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2221                 /* FIXME: where did these entries come from ? -- FR */
2222                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2223                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2224
2225                 /* 8110 family. */
2226                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2227                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2228                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2229                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2230                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2231                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2232
2233                 /* Catch-all */
2234                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2235         };
2236         const struct rtl_mac_info *p = mac_info;
2237         u32 reg;
2238
2239         reg = RTL_R32(tp, TxConfig);
2240         while ((reg & p->mask) != p->val)
2241                 p++;
2242         tp->mac_version = p->mac_version;
2243
2244         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2245                 dev_notice(tp_to_dev(tp),
2246                            "unknown MAC, using family default\n");
2247                 tp->mac_version = default_version;
2248         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2249                 tp->mac_version = tp->mii.supports_gmii ?
2250                                   RTL_GIGA_MAC_VER_42 :
2251                                   RTL_GIGA_MAC_VER_43;
2252         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2253                 tp->mac_version = tp->mii.supports_gmii ?
2254                                   RTL_GIGA_MAC_VER_45 :
2255                                   RTL_GIGA_MAC_VER_47;
2256         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2257                 tp->mac_version = tp->mii.supports_gmii ?
2258                                   RTL_GIGA_MAC_VER_46 :
2259                                   RTL_GIGA_MAC_VER_48;
2260         }
2261 }
2262
2263 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2264 {
2265         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2266 }
2267
2268 struct phy_reg {
2269         u16 reg;
2270         u16 val;
2271 };
2272
2273 static void rtl_writephy_batch(struct rtl8169_private *tp,
2274                                const struct phy_reg *regs, int len)
2275 {
2276         while (len-- > 0) {
2277                 rtl_writephy(tp, regs->reg, regs->val);
2278                 regs++;
2279         }
2280 }
2281
2282 #define PHY_READ                0x00000000
2283 #define PHY_DATA_OR             0x10000000
2284 #define PHY_DATA_AND            0x20000000
2285 #define PHY_BJMPN               0x30000000
2286 #define PHY_MDIO_CHG            0x40000000
2287 #define PHY_CLEAR_READCOUNT     0x70000000
2288 #define PHY_WRITE               0x80000000
2289 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2290 #define PHY_COMP_EQ_SKIPN       0xa0000000
2291 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2292 #define PHY_WRITE_PREVIOUS      0xc0000000
2293 #define PHY_SKIPN               0xd0000000
2294 #define PHY_DELAY_MS            0xe0000000
2295
2296 struct fw_info {
2297         u32     magic;
2298         char    version[RTL_VER_SIZE];
2299         __le32  fw_start;
2300         __le32  fw_len;
2301         u8      chksum;
2302 } __packed;
2303
2304 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2305
2306 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2307 {
2308         const struct firmware *fw = rtl_fw->fw;
2309         struct fw_info *fw_info = (struct fw_info *)fw->data;
2310         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2311         char *version = rtl_fw->version;
2312         bool rc = false;
2313
2314         if (fw->size < FW_OPCODE_SIZE)
2315                 goto out;
2316
2317         if (!fw_info->magic) {
2318                 size_t i, size, start;
2319                 u8 checksum = 0;
2320
2321                 if (fw->size < sizeof(*fw_info))
2322                         goto out;
2323
2324                 for (i = 0; i < fw->size; i++)
2325                         checksum += fw->data[i];
2326                 if (checksum != 0)
2327                         goto out;
2328
2329                 start = le32_to_cpu(fw_info->fw_start);
2330                 if (start > fw->size)
2331                         goto out;
2332
2333                 size = le32_to_cpu(fw_info->fw_len);
2334                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2335                         goto out;
2336
2337                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2338
2339                 pa->code = (__le32 *)(fw->data + start);
2340                 pa->size = size;
2341         } else {
2342                 if (fw->size % FW_OPCODE_SIZE)
2343                         goto out;
2344
2345                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2346
2347                 pa->code = (__le32 *)fw->data;
2348                 pa->size = fw->size / FW_OPCODE_SIZE;
2349         }
2350         version[RTL_VER_SIZE - 1] = 0;
2351
2352         rc = true;
2353 out:
2354         return rc;
2355 }
2356
2357 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2358                            struct rtl_fw_phy_action *pa)
2359 {
2360         bool rc = false;
2361         size_t index;
2362
2363         for (index = 0; index < pa->size; index++) {
2364                 u32 action = le32_to_cpu(pa->code[index]);
2365                 u32 regno = (action & 0x0fff0000) >> 16;
2366
2367                 switch(action & 0xf0000000) {
2368                 case PHY_READ:
2369                 case PHY_DATA_OR:
2370                 case PHY_DATA_AND:
2371                 case PHY_MDIO_CHG:
2372                 case PHY_CLEAR_READCOUNT:
2373                 case PHY_WRITE:
2374                 case PHY_WRITE_PREVIOUS:
2375                 case PHY_DELAY_MS:
2376                         break;
2377
2378                 case PHY_BJMPN:
2379                         if (regno > index) {
2380                                 netif_err(tp, ifup, tp->dev,
2381                                           "Out of range of firmware\n");
2382                                 goto out;
2383                         }
2384                         break;
2385                 case PHY_READCOUNT_EQ_SKIP:
2386                         if (index + 2 >= pa->size) {
2387                                 netif_err(tp, ifup, tp->dev,
2388                                           "Out of range of firmware\n");
2389                                 goto out;
2390                         }
2391                         break;
2392                 case PHY_COMP_EQ_SKIPN:
2393                 case PHY_COMP_NEQ_SKIPN:
2394                 case PHY_SKIPN:
2395                         if (index + 1 + regno >= pa->size) {
2396                                 netif_err(tp, ifup, tp->dev,
2397                                           "Out of range of firmware\n");
2398                                 goto out;
2399                         }
2400                         break;
2401
2402                 default:
2403                         netif_err(tp, ifup, tp->dev,
2404                                   "Invalid action 0x%08x\n", action);
2405                         goto out;
2406                 }
2407         }
2408         rc = true;
2409 out:
2410         return rc;
2411 }
2412
2413 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2414 {
2415         struct net_device *dev = tp->dev;
2416         int rc = -EINVAL;
2417
2418         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2419                 netif_err(tp, ifup, dev, "invalid firmware\n");
2420                 goto out;
2421         }
2422
2423         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2424                 rc = 0;
2425 out:
2426         return rc;
2427 }
2428
2429 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2430 {
2431         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2432         struct mdio_ops org, *ops = &tp->mdio_ops;
2433         u32 predata, count;
2434         size_t index;
2435
2436         predata = count = 0;
2437         org.write = ops->write;
2438         org.read = ops->read;
2439
2440         for (index = 0; index < pa->size; ) {
2441                 u32 action = le32_to_cpu(pa->code[index]);
2442                 u32 data = action & 0x0000ffff;
2443                 u32 regno = (action & 0x0fff0000) >> 16;
2444
2445                 if (!action)
2446                         break;
2447
2448                 switch(action & 0xf0000000) {
2449                 case PHY_READ:
2450                         predata = rtl_readphy(tp, regno);
2451                         count++;
2452                         index++;
2453                         break;
2454                 case PHY_DATA_OR:
2455                         predata |= data;
2456                         index++;
2457                         break;
2458                 case PHY_DATA_AND:
2459                         predata &= data;
2460                         index++;
2461                         break;
2462                 case PHY_BJMPN:
2463                         index -= regno;
2464                         break;
2465                 case PHY_MDIO_CHG:
2466                         if (data == 0) {
2467                                 ops->write = org.write;
2468                                 ops->read = org.read;
2469                         } else if (data == 1) {
2470                                 ops->write = mac_mcu_write;
2471                                 ops->read = mac_mcu_read;
2472                         }
2473
2474                         index++;
2475                         break;
2476                 case PHY_CLEAR_READCOUNT:
2477                         count = 0;
2478                         index++;
2479                         break;
2480                 case PHY_WRITE:
2481                         rtl_writephy(tp, regno, data);
2482                         index++;
2483                         break;
2484                 case PHY_READCOUNT_EQ_SKIP:
2485                         index += (count == data) ? 2 : 1;
2486                         break;
2487                 case PHY_COMP_EQ_SKIPN:
2488                         if (predata == data)
2489                                 index += regno;
2490                         index++;
2491                         break;
2492                 case PHY_COMP_NEQ_SKIPN:
2493                         if (predata != data)
2494                                 index += regno;
2495                         index++;
2496                         break;
2497                 case PHY_WRITE_PREVIOUS:
2498                         rtl_writephy(tp, regno, predata);
2499                         index++;
2500                         break;
2501                 case PHY_SKIPN:
2502                         index += regno + 1;
2503                         break;
2504                 case PHY_DELAY_MS:
2505                         mdelay(data);
2506                         index++;
2507                         break;
2508
2509                 default:
2510                         BUG();
2511                 }
2512         }
2513
2514         ops->write = org.write;
2515         ops->read = org.read;
2516 }
2517
2518 static void rtl_release_firmware(struct rtl8169_private *tp)
2519 {
2520         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2521                 release_firmware(tp->rtl_fw->fw);
2522                 kfree(tp->rtl_fw);
2523         }
2524         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2525 }
2526
2527 static void rtl_apply_firmware(struct rtl8169_private *tp)
2528 {
2529         struct rtl_fw *rtl_fw = tp->rtl_fw;
2530
2531         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2532         if (!IS_ERR_OR_NULL(rtl_fw))
2533                 rtl_phy_write_fw(tp, rtl_fw);
2534 }
2535
2536 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2537 {
2538         if (rtl_readphy(tp, reg) != val)
2539                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2540         else
2541                 rtl_apply_firmware(tp);
2542 }
2543
2544 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2545 {
2546         static const struct phy_reg phy_reg_init[] = {
2547                 { 0x1f, 0x0001 },
2548                 { 0x06, 0x006e },
2549                 { 0x08, 0x0708 },
2550                 { 0x15, 0x4000 },
2551                 { 0x18, 0x65c7 },
2552
2553                 { 0x1f, 0x0001 },
2554                 { 0x03, 0x00a1 },
2555                 { 0x02, 0x0008 },
2556                 { 0x01, 0x0120 },
2557                 { 0x00, 0x1000 },
2558                 { 0x04, 0x0800 },
2559                 { 0x04, 0x0000 },
2560
2561                 { 0x03, 0xff41 },
2562                 { 0x02, 0xdf60 },
2563                 { 0x01, 0x0140 },
2564                 { 0x00, 0x0077 },
2565                 { 0x04, 0x7800 },
2566                 { 0x04, 0x7000 },
2567
2568                 { 0x03, 0x802f },
2569                 { 0x02, 0x4f02 },
2570                 { 0x01, 0x0409 },
2571                 { 0x00, 0xf0f9 },
2572                 { 0x04, 0x9800 },
2573                 { 0x04, 0x9000 },
2574
2575                 { 0x03, 0xdf01 },
2576                 { 0x02, 0xdf20 },
2577                 { 0x01, 0xff95 },
2578                 { 0x00, 0xba00 },
2579                 { 0x04, 0xa800 },
2580                 { 0x04, 0xa000 },
2581
2582                 { 0x03, 0xff41 },
2583                 { 0x02, 0xdf20 },
2584                 { 0x01, 0x0140 },
2585                 { 0x00, 0x00bb },
2586                 { 0x04, 0xb800 },
2587                 { 0x04, 0xb000 },
2588
2589                 { 0x03, 0xdf41 },
2590                 { 0x02, 0xdc60 },
2591                 { 0x01, 0x6340 },
2592                 { 0x00, 0x007d },
2593                 { 0x04, 0xd800 },
2594                 { 0x04, 0xd000 },
2595
2596                 { 0x03, 0xdf01 },
2597                 { 0x02, 0xdf20 },
2598                 { 0x01, 0x100a },
2599                 { 0x00, 0xa0ff },
2600                 { 0x04, 0xf800 },
2601                 { 0x04, 0xf000 },
2602
2603                 { 0x1f, 0x0000 },
2604                 { 0x0b, 0x0000 },
2605                 { 0x00, 0x9200 }
2606         };
2607
2608         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2609 }
2610
2611 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2612 {
2613         static const struct phy_reg phy_reg_init[] = {
2614                 { 0x1f, 0x0002 },
2615                 { 0x01, 0x90d0 },
2616                 { 0x1f, 0x0000 }
2617         };
2618
2619         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2620 }
2621
2622 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2623 {
2624         struct pci_dev *pdev = tp->pci_dev;
2625
2626         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2627             (pdev->subsystem_device != 0xe000))
2628                 return;
2629
2630         rtl_writephy(tp, 0x1f, 0x0001);
2631         rtl_writephy(tp, 0x10, 0xf01b);
2632         rtl_writephy(tp, 0x1f, 0x0000);
2633 }
2634
2635 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2636 {
2637         static const struct phy_reg phy_reg_init[] = {
2638                 { 0x1f, 0x0001 },
2639                 { 0x04, 0x0000 },
2640                 { 0x03, 0x00a1 },
2641                 { 0x02, 0x0008 },
2642                 { 0x01, 0x0120 },
2643                 { 0x00, 0x1000 },
2644                 { 0x04, 0x0800 },
2645                 { 0x04, 0x9000 },
2646                 { 0x03, 0x802f },
2647                 { 0x02, 0x4f02 },
2648                 { 0x01, 0x0409 },
2649                 { 0x00, 0xf099 },
2650                 { 0x04, 0x9800 },
2651                 { 0x04, 0xa000 },
2652                 { 0x03, 0xdf01 },
2653                 { 0x02, 0xdf20 },
2654                 { 0x01, 0xff95 },
2655                 { 0x00, 0xba00 },
2656                 { 0x04, 0xa800 },
2657                 { 0x04, 0xf000 },
2658                 { 0x03, 0xdf01 },
2659                 { 0x02, 0xdf20 },
2660                 { 0x01, 0x101a },
2661                 { 0x00, 0xa0ff },
2662                 { 0x04, 0xf800 },
2663                 { 0x04, 0x0000 },
2664                 { 0x1f, 0x0000 },
2665
2666                 { 0x1f, 0x0001 },
2667                 { 0x10, 0xf41b },
2668                 { 0x14, 0xfb54 },
2669                 { 0x18, 0xf5c7 },
2670                 { 0x1f, 0x0000 },
2671
2672                 { 0x1f, 0x0001 },
2673                 { 0x17, 0x0cc0 },
2674                 { 0x1f, 0x0000 }
2675         };
2676
2677         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2678
2679         rtl8169scd_hw_phy_config_quirk(tp);
2680 }
2681
2682 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2683 {
2684         static const struct phy_reg phy_reg_init[] = {
2685                 { 0x1f, 0x0001 },
2686                 { 0x04, 0x0000 },
2687                 { 0x03, 0x00a1 },
2688                 { 0x02, 0x0008 },
2689                 { 0x01, 0x0120 },
2690                 { 0x00, 0x1000 },
2691                 { 0x04, 0x0800 },
2692                 { 0x04, 0x9000 },
2693                 { 0x03, 0x802f },
2694                 { 0x02, 0x4f02 },
2695                 { 0x01, 0x0409 },
2696                 { 0x00, 0xf099 },
2697                 { 0x04, 0x9800 },
2698                 { 0x04, 0xa000 },
2699                 { 0x03, 0xdf01 },
2700                 { 0x02, 0xdf20 },
2701                 { 0x01, 0xff95 },
2702                 { 0x00, 0xba00 },
2703                 { 0x04, 0xa800 },
2704                 { 0x04, 0xf000 },
2705                 { 0x03, 0xdf01 },
2706                 { 0x02, 0xdf20 },
2707                 { 0x01, 0x101a },
2708                 { 0x00, 0xa0ff },
2709                 { 0x04, 0xf800 },
2710                 { 0x04, 0x0000 },
2711                 { 0x1f, 0x0000 },
2712
2713                 { 0x1f, 0x0001 },
2714                 { 0x0b, 0x8480 },
2715                 { 0x1f, 0x0000 },
2716
2717                 { 0x1f, 0x0001 },
2718                 { 0x18, 0x67c7 },
2719                 { 0x04, 0x2000 },
2720                 { 0x03, 0x002f },
2721                 { 0x02, 0x4360 },
2722                 { 0x01, 0x0109 },
2723                 { 0x00, 0x3022 },
2724                 { 0x04, 0x2800 },
2725                 { 0x1f, 0x0000 },
2726
2727                 { 0x1f, 0x0001 },
2728                 { 0x17, 0x0cc0 },
2729                 { 0x1f, 0x0000 }
2730         };
2731
2732         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2733 }
2734
2735 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2736 {
2737         static const struct phy_reg phy_reg_init[] = {
2738                 { 0x10, 0xf41b },
2739                 { 0x1f, 0x0000 }
2740         };
2741
2742         rtl_writephy(tp, 0x1f, 0x0001);
2743         rtl_patchphy(tp, 0x16, 1 << 0);
2744
2745         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2746 }
2747
2748 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2749 {
2750         static const struct phy_reg phy_reg_init[] = {
2751                 { 0x1f, 0x0001 },
2752                 { 0x10, 0xf41b },
2753                 { 0x1f, 0x0000 }
2754         };
2755
2756         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2757 }
2758
2759 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2760 {
2761         static const struct phy_reg phy_reg_init[] = {
2762                 { 0x1f, 0x0000 },
2763                 { 0x1d, 0x0f00 },
2764                 { 0x1f, 0x0002 },
2765                 { 0x0c, 0x1ec8 },
2766                 { 0x1f, 0x0000 }
2767         };
2768
2769         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2770 }
2771
2772 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2773 {
2774         static const struct phy_reg phy_reg_init[] = {
2775                 { 0x1f, 0x0001 },
2776                 { 0x1d, 0x3d98 },
2777                 { 0x1f, 0x0000 }
2778         };
2779
2780         rtl_writephy(tp, 0x1f, 0x0000);
2781         rtl_patchphy(tp, 0x14, 1 << 5);
2782         rtl_patchphy(tp, 0x0d, 1 << 5);
2783
2784         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2785 }
2786
2787 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2788 {
2789         static const struct phy_reg phy_reg_init[] = {
2790                 { 0x1f, 0x0001 },
2791                 { 0x12, 0x2300 },
2792                 { 0x1f, 0x0002 },
2793                 { 0x00, 0x88d4 },
2794                 { 0x01, 0x82b1 },
2795                 { 0x03, 0x7002 },
2796                 { 0x08, 0x9e30 },
2797                 { 0x09, 0x01f0 },
2798                 { 0x0a, 0x5500 },
2799                 { 0x0c, 0x00c8 },
2800                 { 0x1f, 0x0003 },
2801                 { 0x12, 0xc096 },
2802                 { 0x16, 0x000a },
2803                 { 0x1f, 0x0000 },
2804                 { 0x1f, 0x0000 },
2805                 { 0x09, 0x2000 },
2806                 { 0x09, 0x0000 }
2807         };
2808
2809         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2810
2811         rtl_patchphy(tp, 0x14, 1 << 5);
2812         rtl_patchphy(tp, 0x0d, 1 << 5);
2813         rtl_writephy(tp, 0x1f, 0x0000);
2814 }
2815
2816 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2817 {
2818         static const struct phy_reg phy_reg_init[] = {
2819                 { 0x1f, 0x0001 },
2820                 { 0x12, 0x2300 },
2821                 { 0x03, 0x802f },
2822                 { 0x02, 0x4f02 },
2823                 { 0x01, 0x0409 },
2824                 { 0x00, 0xf099 },
2825                 { 0x04, 0x9800 },
2826                 { 0x04, 0x9000 },
2827                 { 0x1d, 0x3d98 },
2828                 { 0x1f, 0x0002 },
2829                 { 0x0c, 0x7eb8 },
2830                 { 0x06, 0x0761 },
2831                 { 0x1f, 0x0003 },
2832                 { 0x16, 0x0f0a },
2833                 { 0x1f, 0x0000 }
2834         };
2835
2836         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2837
2838         rtl_patchphy(tp, 0x16, 1 << 0);
2839         rtl_patchphy(tp, 0x14, 1 << 5);
2840         rtl_patchphy(tp, 0x0d, 1 << 5);
2841         rtl_writephy(tp, 0x1f, 0x0000);
2842 }
2843
2844 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2845 {
2846         static const struct phy_reg phy_reg_init[] = {
2847                 { 0x1f, 0x0001 },
2848                 { 0x12, 0x2300 },
2849                 { 0x1d, 0x3d98 },
2850                 { 0x1f, 0x0002 },
2851                 { 0x0c, 0x7eb8 },
2852                 { 0x06, 0x5461 },
2853                 { 0x1f, 0x0003 },
2854                 { 0x16, 0x0f0a },
2855                 { 0x1f, 0x0000 }
2856         };
2857
2858         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2859
2860         rtl_patchphy(tp, 0x16, 1 << 0);
2861         rtl_patchphy(tp, 0x14, 1 << 5);
2862         rtl_patchphy(tp, 0x0d, 1 << 5);
2863         rtl_writephy(tp, 0x1f, 0x0000);
2864 }
2865
2866 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2867 {
2868         rtl8168c_3_hw_phy_config(tp);
2869 }
2870
2871 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2872 {
2873         static const struct phy_reg phy_reg_init_0[] = {
2874                 /* Channel Estimation */
2875                 { 0x1f, 0x0001 },
2876                 { 0x06, 0x4064 },
2877                 { 0x07, 0x2863 },
2878                 { 0x08, 0x059c },
2879                 { 0x09, 0x26b4 },
2880                 { 0x0a, 0x6a19 },
2881                 { 0x0b, 0xdcc8 },
2882                 { 0x10, 0xf06d },
2883                 { 0x14, 0x7f68 },
2884                 { 0x18, 0x7fd9 },
2885                 { 0x1c, 0xf0ff },
2886                 { 0x1d, 0x3d9c },
2887                 { 0x1f, 0x0003 },
2888                 { 0x12, 0xf49f },
2889                 { 0x13, 0x070b },
2890                 { 0x1a, 0x05ad },
2891                 { 0x14, 0x94c0 },
2892
2893                 /*
2894                  * Tx Error Issue
2895                  * Enhance line driver power
2896                  */
2897                 { 0x1f, 0x0002 },
2898                 { 0x06, 0x5561 },
2899                 { 0x1f, 0x0005 },
2900                 { 0x05, 0x8332 },
2901                 { 0x06, 0x5561 },
2902
2903                 /*
2904                  * Can not link to 1Gbps with bad cable
2905                  * Decrease SNR threshold form 21.07dB to 19.04dB
2906                  */
2907                 { 0x1f, 0x0001 },
2908                 { 0x17, 0x0cc0 },
2909
2910                 { 0x1f, 0x0000 },
2911                 { 0x0d, 0xf880 }
2912         };
2913
2914         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2915
2916         /*
2917          * Rx Error Issue
2918          * Fine Tune Switching regulator parameter
2919          */
2920         rtl_writephy(tp, 0x1f, 0x0002);
2921         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2922         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2923
2924         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2925                 static const struct phy_reg phy_reg_init[] = {
2926                         { 0x1f, 0x0002 },
2927                         { 0x05, 0x669a },
2928                         { 0x1f, 0x0005 },
2929                         { 0x05, 0x8330 },
2930                         { 0x06, 0x669a },
2931                         { 0x1f, 0x0002 }
2932                 };
2933                 int val;
2934
2935                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2936
2937                 val = rtl_readphy(tp, 0x0d);
2938
2939                 if ((val & 0x00ff) != 0x006c) {
2940                         static const u32 set[] = {
2941                                 0x0065, 0x0066, 0x0067, 0x0068,
2942                                 0x0069, 0x006a, 0x006b, 0x006c
2943                         };
2944                         int i;
2945
2946                         rtl_writephy(tp, 0x1f, 0x0002);
2947
2948                         val &= 0xff00;
2949                         for (i = 0; i < ARRAY_SIZE(set); i++)
2950                                 rtl_writephy(tp, 0x0d, val | set[i]);
2951                 }
2952         } else {
2953                 static const struct phy_reg phy_reg_init[] = {
2954                         { 0x1f, 0x0002 },
2955                         { 0x05, 0x6662 },
2956                         { 0x1f, 0x0005 },
2957                         { 0x05, 0x8330 },
2958                         { 0x06, 0x6662 }
2959                 };
2960
2961                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2962         }
2963
2964         /* RSET couple improve */
2965         rtl_writephy(tp, 0x1f, 0x0002);
2966         rtl_patchphy(tp, 0x0d, 0x0300);
2967         rtl_patchphy(tp, 0x0f, 0x0010);
2968
2969         /* Fine tune PLL performance */
2970         rtl_writephy(tp, 0x1f, 0x0002);
2971         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2972         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2973
2974         rtl_writephy(tp, 0x1f, 0x0005);
2975         rtl_writephy(tp, 0x05, 0x001b);
2976
2977         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2978
2979         rtl_writephy(tp, 0x1f, 0x0000);
2980 }
2981
2982 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2983 {
2984         static const struct phy_reg phy_reg_init_0[] = {
2985                 /* Channel Estimation */
2986                 { 0x1f, 0x0001 },
2987                 { 0x06, 0x4064 },
2988                 { 0x07, 0x2863 },
2989                 { 0x08, 0x059c },
2990                 { 0x09, 0x26b4 },
2991                 { 0x0a, 0x6a19 },
2992                 { 0x0b, 0xdcc8 },
2993                 { 0x10, 0xf06d },
2994                 { 0x14, 0x7f68 },
2995                 { 0x18, 0x7fd9 },
2996                 { 0x1c, 0xf0ff },
2997                 { 0x1d, 0x3d9c },
2998                 { 0x1f, 0x0003 },
2999                 { 0x12, 0xf49f },
3000                 { 0x13, 0x070b },
3001                 { 0x1a, 0x05ad },
3002                 { 0x14, 0x94c0 },
3003
3004                 /*
3005                  * Tx Error Issue
3006                  * Enhance line driver power
3007                  */
3008                 { 0x1f, 0x0002 },
3009                 { 0x06, 0x5561 },
3010                 { 0x1f, 0x0005 },
3011                 { 0x05, 0x8332 },
3012                 { 0x06, 0x5561 },
3013
3014                 /*
3015                  * Can not link to 1Gbps with bad cable
3016                  * Decrease SNR threshold form 21.07dB to 19.04dB
3017                  */
3018                 { 0x1f, 0x0001 },
3019                 { 0x17, 0x0cc0 },
3020
3021                 { 0x1f, 0x0000 },
3022                 { 0x0d, 0xf880 }
3023         };
3024
3025         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3026
3027         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3028                 static const struct phy_reg phy_reg_init[] = {
3029                         { 0x1f, 0x0002 },
3030                         { 0x05, 0x669a },
3031                         { 0x1f, 0x0005 },
3032                         { 0x05, 0x8330 },
3033                         { 0x06, 0x669a },
3034
3035                         { 0x1f, 0x0002 }
3036                 };
3037                 int val;
3038
3039                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3040
3041                 val = rtl_readphy(tp, 0x0d);
3042                 if ((val & 0x00ff) != 0x006c) {
3043                         static const u32 set[] = {
3044                                 0x0065, 0x0066, 0x0067, 0x0068,
3045                                 0x0069, 0x006a, 0x006b, 0x006c
3046                         };
3047                         int i;
3048
3049                         rtl_writephy(tp, 0x1f, 0x0002);
3050
3051                         val &= 0xff00;
3052                         for (i = 0; i < ARRAY_SIZE(set); i++)
3053                                 rtl_writephy(tp, 0x0d, val | set[i]);
3054                 }
3055         } else {
3056                 static const struct phy_reg phy_reg_init[] = {
3057                         { 0x1f, 0x0002 },
3058                         { 0x05, 0x2642 },
3059                         { 0x1f, 0x0005 },
3060                         { 0x05, 0x8330 },
3061                         { 0x06, 0x2642 }
3062                 };
3063
3064                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3065         }
3066
3067         /* Fine tune PLL performance */
3068         rtl_writephy(tp, 0x1f, 0x0002);
3069         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3070         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3071
3072         /* Switching regulator Slew rate */
3073         rtl_writephy(tp, 0x1f, 0x0002);
3074         rtl_patchphy(tp, 0x0f, 0x0017);
3075
3076         rtl_writephy(tp, 0x1f, 0x0005);
3077         rtl_writephy(tp, 0x05, 0x001b);
3078
3079         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3080
3081         rtl_writephy(tp, 0x1f, 0x0000);
3082 }
3083
3084 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3085 {
3086         static const struct phy_reg phy_reg_init[] = {
3087                 { 0x1f, 0x0002 },
3088                 { 0x10, 0x0008 },
3089                 { 0x0d, 0x006c },
3090
3091                 { 0x1f, 0x0000 },
3092                 { 0x0d, 0xf880 },
3093
3094                 { 0x1f, 0x0001 },
3095                 { 0x17, 0x0cc0 },
3096
3097                 { 0x1f, 0x0001 },
3098                 { 0x0b, 0xa4d8 },
3099                 { 0x09, 0x281c },
3100                 { 0x07, 0x2883 },
3101                 { 0x0a, 0x6b35 },
3102                 { 0x1d, 0x3da4 },
3103                 { 0x1c, 0xeffd },
3104                 { 0x14, 0x7f52 },
3105                 { 0x18, 0x7fc6 },
3106                 { 0x08, 0x0601 },
3107                 { 0x06, 0x4063 },
3108                 { 0x10, 0xf074 },
3109                 { 0x1f, 0x0003 },
3110                 { 0x13, 0x0789 },
3111                 { 0x12, 0xf4bd },
3112                 { 0x1a, 0x04fd },
3113                 { 0x14, 0x84b0 },
3114                 { 0x1f, 0x0000 },
3115                 { 0x00, 0x9200 },
3116
3117                 { 0x1f, 0x0005 },
3118                 { 0x01, 0x0340 },
3119                 { 0x1f, 0x0001 },
3120                 { 0x04, 0x4000 },
3121                 { 0x03, 0x1d21 },
3122                 { 0x02, 0x0c32 },
3123                 { 0x01, 0x0200 },
3124                 { 0x00, 0x5554 },
3125                 { 0x04, 0x4800 },
3126                 { 0x04, 0x4000 },
3127                 { 0x04, 0xf000 },
3128                 { 0x03, 0xdf01 },
3129                 { 0x02, 0xdf20 },
3130                 { 0x01, 0x101a },
3131                 { 0x00, 0xa0ff },
3132                 { 0x04, 0xf800 },
3133                 { 0x04, 0xf000 },
3134                 { 0x1f, 0x0000 },
3135
3136                 { 0x1f, 0x0007 },
3137                 { 0x1e, 0x0023 },
3138                 { 0x16, 0x0000 },
3139                 { 0x1f, 0x0000 }
3140         };
3141
3142         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3143 }
3144
3145 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3146 {
3147         static const struct phy_reg phy_reg_init[] = {
3148                 { 0x1f, 0x0001 },
3149                 { 0x17, 0x0cc0 },
3150
3151                 { 0x1f, 0x0007 },
3152                 { 0x1e, 0x002d },
3153                 { 0x18, 0x0040 },
3154                 { 0x1f, 0x0000 }
3155         };
3156
3157         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3158         rtl_patchphy(tp, 0x0d, 1 << 5);
3159 }
3160
3161 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3162 {
3163         static const struct phy_reg phy_reg_init[] = {
3164                 /* Enable Delay cap */
3165                 { 0x1f, 0x0005 },
3166                 { 0x05, 0x8b80 },
3167                 { 0x06, 0xc896 },
3168                 { 0x1f, 0x0000 },
3169
3170                 /* Channel estimation fine tune */
3171                 { 0x1f, 0x0001 },
3172                 { 0x0b, 0x6c20 },
3173                 { 0x07, 0x2872 },
3174                 { 0x1c, 0xefff },
3175                 { 0x1f, 0x0003 },
3176                 { 0x14, 0x6420 },
3177                 { 0x1f, 0x0000 },
3178
3179                 /* Update PFM & 10M TX idle timer */
3180                 { 0x1f, 0x0007 },
3181                 { 0x1e, 0x002f },
3182                 { 0x15, 0x1919 },
3183                 { 0x1f, 0x0000 },
3184
3185                 { 0x1f, 0x0007 },
3186                 { 0x1e, 0x00ac },
3187                 { 0x18, 0x0006 },
3188                 { 0x1f, 0x0000 }
3189         };
3190
3191         rtl_apply_firmware(tp);
3192
3193         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3194
3195         /* DCO enable for 10M IDLE Power */
3196         rtl_writephy(tp, 0x1f, 0x0007);
3197         rtl_writephy(tp, 0x1e, 0x0023);
3198         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3199         rtl_writephy(tp, 0x1f, 0x0000);
3200
3201         /* For impedance matching */
3202         rtl_writephy(tp, 0x1f, 0x0002);
3203         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3204         rtl_writephy(tp, 0x1f, 0x0000);
3205
3206         /* PHY auto speed down */
3207         rtl_writephy(tp, 0x1f, 0x0007);
3208         rtl_writephy(tp, 0x1e, 0x002d);
3209         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3210         rtl_writephy(tp, 0x1f, 0x0000);
3211         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3212
3213         rtl_writephy(tp, 0x1f, 0x0005);
3214         rtl_writephy(tp, 0x05, 0x8b86);
3215         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3216         rtl_writephy(tp, 0x1f, 0x0000);
3217
3218         rtl_writephy(tp, 0x1f, 0x0005);
3219         rtl_writephy(tp, 0x05, 0x8b85);
3220         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3221         rtl_writephy(tp, 0x1f, 0x0007);
3222         rtl_writephy(tp, 0x1e, 0x0020);
3223         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3224         rtl_writephy(tp, 0x1f, 0x0006);
3225         rtl_writephy(tp, 0x00, 0x5a00);
3226         rtl_writephy(tp, 0x1f, 0x0000);
3227         rtl_writephy(tp, 0x0d, 0x0007);
3228         rtl_writephy(tp, 0x0e, 0x003c);
3229         rtl_writephy(tp, 0x0d, 0x4007);
3230         rtl_writephy(tp, 0x0e, 0x0000);
3231         rtl_writephy(tp, 0x0d, 0x0000);
3232 }
3233
3234 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3235 {
3236         const u16 w[] = {
3237                 addr[0] | (addr[1] << 8),
3238                 addr[2] | (addr[3] << 8),
3239                 addr[4] | (addr[5] << 8)
3240         };
3241         const struct exgmac_reg e[] = {
3242                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3243                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3244                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3245                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3246         };
3247
3248         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3249 }
3250
3251 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3252 {
3253         static const struct phy_reg phy_reg_init[] = {
3254                 /* Enable Delay cap */
3255                 { 0x1f, 0x0004 },
3256                 { 0x1f, 0x0007 },
3257                 { 0x1e, 0x00ac },
3258                 { 0x18, 0x0006 },
3259                 { 0x1f, 0x0002 },
3260                 { 0x1f, 0x0000 },
3261                 { 0x1f, 0x0000 },
3262
3263                 /* Channel estimation fine tune */
3264                 { 0x1f, 0x0003 },
3265                 { 0x09, 0xa20f },
3266                 { 0x1f, 0x0000 },
3267                 { 0x1f, 0x0000 },
3268
3269                 /* Green Setting */
3270                 { 0x1f, 0x0005 },
3271                 { 0x05, 0x8b5b },
3272                 { 0x06, 0x9222 },
3273                 { 0x05, 0x8b6d },
3274                 { 0x06, 0x8000 },
3275                 { 0x05, 0x8b76 },
3276                 { 0x06, 0x8000 },
3277                 { 0x1f, 0x0000 }
3278         };
3279
3280         rtl_apply_firmware(tp);
3281
3282         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3283
3284         /* For 4-corner performance improve */
3285         rtl_writephy(tp, 0x1f, 0x0005);
3286         rtl_writephy(tp, 0x05, 0x8b80);
3287         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3288         rtl_writephy(tp, 0x1f, 0x0000);
3289
3290         /* PHY auto speed down */
3291         rtl_writephy(tp, 0x1f, 0x0004);
3292         rtl_writephy(tp, 0x1f, 0x0007);
3293         rtl_writephy(tp, 0x1e, 0x002d);
3294         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3295         rtl_writephy(tp, 0x1f, 0x0002);
3296         rtl_writephy(tp, 0x1f, 0x0000);
3297         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3298
3299         /* improve 10M EEE waveform */
3300         rtl_writephy(tp, 0x1f, 0x0005);
3301         rtl_writephy(tp, 0x05, 0x8b86);
3302         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3303         rtl_writephy(tp, 0x1f, 0x0000);
3304
3305         /* Improve 2-pair detection performance */
3306         rtl_writephy(tp, 0x1f, 0x0005);
3307         rtl_writephy(tp, 0x05, 0x8b85);
3308         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3309         rtl_writephy(tp, 0x1f, 0x0000);
3310
3311         /* EEE setting */
3312         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3313         rtl_writephy(tp, 0x1f, 0x0005);
3314         rtl_writephy(tp, 0x05, 0x8b85);
3315         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3316         rtl_writephy(tp, 0x1f, 0x0004);
3317         rtl_writephy(tp, 0x1f, 0x0007);
3318         rtl_writephy(tp, 0x1e, 0x0020);
3319         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3320         rtl_writephy(tp, 0x1f, 0x0002);
3321         rtl_writephy(tp, 0x1f, 0x0000);
3322         rtl_writephy(tp, 0x0d, 0x0007);
3323         rtl_writephy(tp, 0x0e, 0x003c);
3324         rtl_writephy(tp, 0x0d, 0x4007);
3325         rtl_writephy(tp, 0x0e, 0x0006);
3326         rtl_writephy(tp, 0x0d, 0x0000);
3327
3328         /* Green feature */
3329         rtl_writephy(tp, 0x1f, 0x0003);
3330         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3331         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3332         rtl_writephy(tp, 0x1f, 0x0000);
3333         rtl_writephy(tp, 0x1f, 0x0005);
3334         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3335         rtl_writephy(tp, 0x1f, 0x0000);
3336
3337         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3338         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3339 }
3340
3341 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3342 {
3343         /* For 4-corner performance improve */
3344         rtl_writephy(tp, 0x1f, 0x0005);
3345         rtl_writephy(tp, 0x05, 0x8b80);
3346         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3347         rtl_writephy(tp, 0x1f, 0x0000);
3348
3349         /* PHY auto speed down */
3350         rtl_writephy(tp, 0x1f, 0x0007);
3351         rtl_writephy(tp, 0x1e, 0x002d);
3352         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3353         rtl_writephy(tp, 0x1f, 0x0000);
3354         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3355
3356         /* Improve 10M EEE waveform */
3357         rtl_writephy(tp, 0x1f, 0x0005);
3358         rtl_writephy(tp, 0x05, 0x8b86);
3359         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3360         rtl_writephy(tp, 0x1f, 0x0000);
3361 }
3362
3363 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3364 {
3365         static const struct phy_reg phy_reg_init[] = {
3366                 /* Channel estimation fine tune */
3367                 { 0x1f, 0x0003 },
3368                 { 0x09, 0xa20f },
3369                 { 0x1f, 0x0000 },
3370
3371                 /* Modify green table for giga & fnet */
3372                 { 0x1f, 0x0005 },
3373                 { 0x05, 0x8b55 },
3374                 { 0x06, 0x0000 },
3375                 { 0x05, 0x8b5e },
3376                 { 0x06, 0x0000 },
3377                 { 0x05, 0x8b67 },
3378                 { 0x06, 0x0000 },
3379                 { 0x05, 0x8b70 },
3380                 { 0x06, 0x0000 },
3381                 { 0x1f, 0x0000 },
3382                 { 0x1f, 0x0007 },
3383                 { 0x1e, 0x0078 },
3384                 { 0x17, 0x0000 },
3385                 { 0x19, 0x00fb },
3386                 { 0x1f, 0x0000 },
3387
3388                 /* Modify green table for 10M */
3389                 { 0x1f, 0x0005 },
3390                 { 0x05, 0x8b79 },
3391                 { 0x06, 0xaa00 },
3392                 { 0x1f, 0x0000 },
3393
3394                 /* Disable hiimpedance detection (RTCT) */
3395                 { 0x1f, 0x0003 },
3396                 { 0x01, 0x328a },
3397                 { 0x1f, 0x0000 }
3398         };
3399
3400         rtl_apply_firmware(tp);
3401
3402         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3403
3404         rtl8168f_hw_phy_config(tp);
3405
3406         /* Improve 2-pair detection performance */
3407         rtl_writephy(tp, 0x1f, 0x0005);
3408         rtl_writephy(tp, 0x05, 0x8b85);
3409         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3410         rtl_writephy(tp, 0x1f, 0x0000);
3411 }
3412
3413 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3414 {
3415         rtl_apply_firmware(tp);
3416
3417         rtl8168f_hw_phy_config(tp);
3418 }
3419
3420 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3421 {
3422         static const struct phy_reg phy_reg_init[] = {
3423                 /* Channel estimation fine tune */
3424                 { 0x1f, 0x0003 },
3425                 { 0x09, 0xa20f },
3426                 { 0x1f, 0x0000 },
3427
3428                 /* Modify green table for giga & fnet */
3429                 { 0x1f, 0x0005 },
3430                 { 0x05, 0x8b55 },
3431                 { 0x06, 0x0000 },
3432                 { 0x05, 0x8b5e },
3433                 { 0x06, 0x0000 },
3434                 { 0x05, 0x8b67 },
3435                 { 0x06, 0x0000 },
3436                 { 0x05, 0x8b70 },
3437                 { 0x06, 0x0000 },
3438                 { 0x1f, 0x0000 },
3439                 { 0x1f, 0x0007 },
3440                 { 0x1e, 0x0078 },
3441                 { 0x17, 0x0000 },
3442                 { 0x19, 0x00aa },
3443                 { 0x1f, 0x0000 },
3444
3445                 /* Modify green table for 10M */
3446                 { 0x1f, 0x0005 },
3447                 { 0x05, 0x8b79 },
3448                 { 0x06, 0xaa00 },
3449                 { 0x1f, 0x0000 },
3450
3451                 /* Disable hiimpedance detection (RTCT) */
3452                 { 0x1f, 0x0003 },
3453                 { 0x01, 0x328a },
3454                 { 0x1f, 0x0000 }
3455         };
3456
3457
3458         rtl_apply_firmware(tp);
3459
3460         rtl8168f_hw_phy_config(tp);
3461
3462         /* Improve 2-pair detection performance */
3463         rtl_writephy(tp, 0x1f, 0x0005);
3464         rtl_writephy(tp, 0x05, 0x8b85);
3465         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3466         rtl_writephy(tp, 0x1f, 0x0000);
3467
3468         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3469
3470         /* Modify green table for giga */
3471         rtl_writephy(tp, 0x1f, 0x0005);
3472         rtl_writephy(tp, 0x05, 0x8b54);
3473         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3474         rtl_writephy(tp, 0x05, 0x8b5d);
3475         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3476         rtl_writephy(tp, 0x05, 0x8a7c);
3477         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3478         rtl_writephy(tp, 0x05, 0x8a7f);
3479         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3480         rtl_writephy(tp, 0x05, 0x8a82);
3481         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3482         rtl_writephy(tp, 0x05, 0x8a85);
3483         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3484         rtl_writephy(tp, 0x05, 0x8a88);
3485         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3486         rtl_writephy(tp, 0x1f, 0x0000);
3487
3488         /* uc same-seed solution */
3489         rtl_writephy(tp, 0x1f, 0x0005);
3490         rtl_writephy(tp, 0x05, 0x8b85);
3491         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3492         rtl_writephy(tp, 0x1f, 0x0000);
3493
3494         /* eee setting */
3495         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3496         rtl_writephy(tp, 0x1f, 0x0005);
3497         rtl_writephy(tp, 0x05, 0x8b85);
3498         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3499         rtl_writephy(tp, 0x1f, 0x0004);
3500         rtl_writephy(tp, 0x1f, 0x0007);
3501         rtl_writephy(tp, 0x1e, 0x0020);
3502         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3503         rtl_writephy(tp, 0x1f, 0x0000);
3504         rtl_writephy(tp, 0x0d, 0x0007);
3505         rtl_writephy(tp, 0x0e, 0x003c);
3506         rtl_writephy(tp, 0x0d, 0x4007);
3507         rtl_writephy(tp, 0x0e, 0x0000);
3508         rtl_writephy(tp, 0x0d, 0x0000);
3509
3510         /* Green feature */
3511         rtl_writephy(tp, 0x1f, 0x0003);
3512         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3513         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3514         rtl_writephy(tp, 0x1f, 0x0000);
3515 }
3516
3517 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3518 {
3519         rtl_apply_firmware(tp);
3520
3521         rtl_writephy(tp, 0x1f, 0x0a46);
3522         if (rtl_readphy(tp, 0x10) & 0x0100) {
3523                 rtl_writephy(tp, 0x1f, 0x0bcc);
3524                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3525         } else {
3526                 rtl_writephy(tp, 0x1f, 0x0bcc);
3527                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3528         }
3529
3530         rtl_writephy(tp, 0x1f, 0x0a46);
3531         if (rtl_readphy(tp, 0x13) & 0x0100) {
3532                 rtl_writephy(tp, 0x1f, 0x0c41);
3533                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3534         } else {
3535                 rtl_writephy(tp, 0x1f, 0x0c41);
3536                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3537         }
3538
3539         /* Enable PHY auto speed down */
3540         rtl_writephy(tp, 0x1f, 0x0a44);
3541         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3542
3543         rtl_writephy(tp, 0x1f, 0x0bcc);
3544         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3545         rtl_writephy(tp, 0x1f, 0x0a44);
3546         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3547         rtl_writephy(tp, 0x1f, 0x0a43);
3548         rtl_writephy(tp, 0x13, 0x8084);
3549         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3550         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3551
3552         /* EEE auto-fallback function */
3553         rtl_writephy(tp, 0x1f, 0x0a4b);
3554         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3555
3556         /* Enable UC LPF tune function */
3557         rtl_writephy(tp, 0x1f, 0x0a43);
3558         rtl_writephy(tp, 0x13, 0x8012);
3559         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3560
3561         rtl_writephy(tp, 0x1f, 0x0c42);
3562         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3563
3564         /* Improve SWR Efficiency */
3565         rtl_writephy(tp, 0x1f, 0x0bcd);
3566         rtl_writephy(tp, 0x14, 0x5065);
3567         rtl_writephy(tp, 0x14, 0xd065);
3568         rtl_writephy(tp, 0x1f, 0x0bc8);
3569         rtl_writephy(tp, 0x11, 0x5655);
3570         rtl_writephy(tp, 0x1f, 0x0bcd);
3571         rtl_writephy(tp, 0x14, 0x1065);
3572         rtl_writephy(tp, 0x14, 0x9065);
3573         rtl_writephy(tp, 0x14, 0x1065);
3574
3575         /* Check ALDPS bit, disable it if enabled */
3576         rtl_writephy(tp, 0x1f, 0x0a43);
3577         if (rtl_readphy(tp, 0x10) & 0x0004)
3578                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3579
3580         rtl_writephy(tp, 0x1f, 0x0000);
3581 }
3582
3583 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3584 {
3585         rtl_apply_firmware(tp);
3586 }
3587
3588 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3589 {
3590         u16 dout_tapbin;
3591         u32 data;
3592
3593         rtl_apply_firmware(tp);
3594
3595         /* CHN EST parameters adjust - giga master */
3596         rtl_writephy(tp, 0x1f, 0x0a43);
3597         rtl_writephy(tp, 0x13, 0x809b);
3598         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3599         rtl_writephy(tp, 0x13, 0x80a2);
3600         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3601         rtl_writephy(tp, 0x13, 0x80a4);
3602         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3603         rtl_writephy(tp, 0x13, 0x809c);
3604         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3605         rtl_writephy(tp, 0x1f, 0x0000);
3606
3607         /* CHN EST parameters adjust - giga slave */
3608         rtl_writephy(tp, 0x1f, 0x0a43);
3609         rtl_writephy(tp, 0x13, 0x80ad);
3610         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3611         rtl_writephy(tp, 0x13, 0x80b4);
3612         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3613         rtl_writephy(tp, 0x13, 0x80ac);
3614         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3615         rtl_writephy(tp, 0x1f, 0x0000);
3616
3617         /* CHN EST parameters adjust - fnet */
3618         rtl_writephy(tp, 0x1f, 0x0a43);
3619         rtl_writephy(tp, 0x13, 0x808e);
3620         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3621         rtl_writephy(tp, 0x13, 0x8090);
3622         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3623         rtl_writephy(tp, 0x13, 0x8092);
3624         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3625         rtl_writephy(tp, 0x1f, 0x0000);
3626
3627         /* enable R-tune & PGA-retune function */
3628         dout_tapbin = 0;
3629         rtl_writephy(tp, 0x1f, 0x0a46);
3630         data = rtl_readphy(tp, 0x13);
3631         data &= 3;
3632         data <<= 2;
3633         dout_tapbin |= data;
3634         data = rtl_readphy(tp, 0x12);
3635         data &= 0xc000;
3636         data >>= 14;
3637         dout_tapbin |= data;
3638         dout_tapbin = ~(dout_tapbin^0x08);
3639         dout_tapbin <<= 12;
3640         dout_tapbin &= 0xf000;
3641         rtl_writephy(tp, 0x1f, 0x0a43);
3642         rtl_writephy(tp, 0x13, 0x827a);
3643         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3644         rtl_writephy(tp, 0x13, 0x827b);
3645         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3646         rtl_writephy(tp, 0x13, 0x827c);
3647         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3648         rtl_writephy(tp, 0x13, 0x827d);
3649         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3650
3651         rtl_writephy(tp, 0x1f, 0x0a43);
3652         rtl_writephy(tp, 0x13, 0x0811);
3653         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3654         rtl_writephy(tp, 0x1f, 0x0a42);
3655         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3656         rtl_writephy(tp, 0x1f, 0x0000);
3657
3658         /* enable GPHY 10M */
3659         rtl_writephy(tp, 0x1f, 0x0a44);
3660         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3661         rtl_writephy(tp, 0x1f, 0x0000);
3662
3663         /* SAR ADC performance */
3664         rtl_writephy(tp, 0x1f, 0x0bca);
3665         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3666         rtl_writephy(tp, 0x1f, 0x0000);
3667
3668         rtl_writephy(tp, 0x1f, 0x0a43);
3669         rtl_writephy(tp, 0x13, 0x803f);
3670         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3671         rtl_writephy(tp, 0x13, 0x8047);
3672         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3673         rtl_writephy(tp, 0x13, 0x804f);
3674         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3675         rtl_writephy(tp, 0x13, 0x8057);
3676         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3677         rtl_writephy(tp, 0x13, 0x805f);
3678         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3679         rtl_writephy(tp, 0x13, 0x8067);
3680         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3681         rtl_writephy(tp, 0x13, 0x806f);
3682         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3683         rtl_writephy(tp, 0x1f, 0x0000);
3684
3685         /* disable phy pfm mode */
3686         rtl_writephy(tp, 0x1f, 0x0a44);
3687         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3688         rtl_writephy(tp, 0x1f, 0x0000);
3689
3690         /* Check ALDPS bit, disable it if enabled */
3691         rtl_writephy(tp, 0x1f, 0x0a43);
3692         if (rtl_readphy(tp, 0x10) & 0x0004)
3693                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3694
3695         rtl_writephy(tp, 0x1f, 0x0000);
3696 }
3697
3698 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3699 {
3700         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3701         u16 rlen;
3702         u32 data;
3703
3704         rtl_apply_firmware(tp);
3705
3706         /* CHIN EST parameter update */
3707         rtl_writephy(tp, 0x1f, 0x0a43);
3708         rtl_writephy(tp, 0x13, 0x808a);
3709         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3710         rtl_writephy(tp, 0x1f, 0x0000);
3711
3712         /* enable R-tune & PGA-retune function */
3713         rtl_writephy(tp, 0x1f, 0x0a43);
3714         rtl_writephy(tp, 0x13, 0x0811);
3715         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3716         rtl_writephy(tp, 0x1f, 0x0a42);
3717         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3718         rtl_writephy(tp, 0x1f, 0x0000);
3719
3720         /* enable GPHY 10M */
3721         rtl_writephy(tp, 0x1f, 0x0a44);
3722         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3723         rtl_writephy(tp, 0x1f, 0x0000);
3724
3725         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3726         data = r8168_mac_ocp_read(tp, 0xdd02);
3727         ioffset_p3 = ((data & 0x80)>>7);
3728         ioffset_p3 <<= 3;
3729
3730         data = r8168_mac_ocp_read(tp, 0xdd00);
3731         ioffset_p3 |= ((data & (0xe000))>>13);
3732         ioffset_p2 = ((data & (0x1e00))>>9);
3733         ioffset_p1 = ((data & (0x01e0))>>5);
3734         ioffset_p0 = ((data & 0x0010)>>4);
3735         ioffset_p0 <<= 3;
3736         ioffset_p0 |= (data & (0x07));
3737         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3738
3739         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3740             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3741                 rtl_writephy(tp, 0x1f, 0x0bcf);
3742                 rtl_writephy(tp, 0x16, data);
3743                 rtl_writephy(tp, 0x1f, 0x0000);
3744         }
3745
3746         /* Modify rlen (TX LPF corner frequency) level */
3747         rtl_writephy(tp, 0x1f, 0x0bcd);
3748         data = rtl_readphy(tp, 0x16);
3749         data &= 0x000f;
3750         rlen = 0;
3751         if (data > 3)
3752                 rlen = data - 3;
3753         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3754         rtl_writephy(tp, 0x17, data);
3755         rtl_writephy(tp, 0x1f, 0x0bcd);
3756         rtl_writephy(tp, 0x1f, 0x0000);
3757
3758         /* disable phy pfm mode */
3759         rtl_writephy(tp, 0x1f, 0x0a44);
3760         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3761         rtl_writephy(tp, 0x1f, 0x0000);
3762
3763         /* Check ALDPS bit, disable it if enabled */
3764         rtl_writephy(tp, 0x1f, 0x0a43);
3765         if (rtl_readphy(tp, 0x10) & 0x0004)
3766                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3767
3768         rtl_writephy(tp, 0x1f, 0x0000);
3769 }
3770
3771 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3772 {
3773         /* Enable PHY auto speed down */
3774         rtl_writephy(tp, 0x1f, 0x0a44);
3775         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3776         rtl_writephy(tp, 0x1f, 0x0000);
3777
3778         /* patch 10M & ALDPS */
3779         rtl_writephy(tp, 0x1f, 0x0bcc);
3780         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3781         rtl_writephy(tp, 0x1f, 0x0a44);
3782         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3783         rtl_writephy(tp, 0x1f, 0x0a43);
3784         rtl_writephy(tp, 0x13, 0x8084);
3785         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3786         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3787         rtl_writephy(tp, 0x1f, 0x0000);
3788
3789         /* Enable EEE auto-fallback function */
3790         rtl_writephy(tp, 0x1f, 0x0a4b);
3791         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3792         rtl_writephy(tp, 0x1f, 0x0000);
3793
3794         /* Enable UC LPF tune function */
3795         rtl_writephy(tp, 0x1f, 0x0a43);
3796         rtl_writephy(tp, 0x13, 0x8012);
3797         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3798         rtl_writephy(tp, 0x1f, 0x0000);
3799
3800         /* set rg_sel_sdm_rate */
3801         rtl_writephy(tp, 0x1f, 0x0c42);
3802         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3803         rtl_writephy(tp, 0x1f, 0x0000);
3804
3805         /* Check ALDPS bit, disable it if enabled */
3806         rtl_writephy(tp, 0x1f, 0x0a43);
3807         if (rtl_readphy(tp, 0x10) & 0x0004)
3808                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3809
3810         rtl_writephy(tp, 0x1f, 0x0000);
3811 }
3812
3813 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3814 {
3815         /* patch 10M & ALDPS */
3816         rtl_writephy(tp, 0x1f, 0x0bcc);
3817         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3818         rtl_writephy(tp, 0x1f, 0x0a44);
3819         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3820         rtl_writephy(tp, 0x1f, 0x0a43);
3821         rtl_writephy(tp, 0x13, 0x8084);
3822         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3823         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3824         rtl_writephy(tp, 0x1f, 0x0000);
3825
3826         /* Enable UC LPF tune function */
3827         rtl_writephy(tp, 0x1f, 0x0a43);
3828         rtl_writephy(tp, 0x13, 0x8012);
3829         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3830         rtl_writephy(tp, 0x1f, 0x0000);
3831
3832         /* Set rg_sel_sdm_rate */
3833         rtl_writephy(tp, 0x1f, 0x0c42);
3834         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3835         rtl_writephy(tp, 0x1f, 0x0000);
3836
3837         /* Channel estimation parameters */
3838         rtl_writephy(tp, 0x1f, 0x0a43);
3839         rtl_writephy(tp, 0x13, 0x80f3);
3840         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3841         rtl_writephy(tp, 0x13, 0x80f0);
3842         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3843         rtl_writephy(tp, 0x13, 0x80ef);
3844         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3845         rtl_writephy(tp, 0x13, 0x80f6);
3846         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3847         rtl_writephy(tp, 0x13, 0x80ec);
3848         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3849         rtl_writephy(tp, 0x13, 0x80ed);
3850         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3851         rtl_writephy(tp, 0x13, 0x80f2);
3852         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3853         rtl_writephy(tp, 0x13, 0x80f4);
3854         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3855         rtl_writephy(tp, 0x1f, 0x0a43);
3856         rtl_writephy(tp, 0x13, 0x8110);
3857         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3858         rtl_writephy(tp, 0x13, 0x810f);
3859         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3860         rtl_writephy(tp, 0x13, 0x8111);
3861         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3862         rtl_writephy(tp, 0x13, 0x8113);
3863         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3864         rtl_writephy(tp, 0x13, 0x8115);
3865         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3866         rtl_writephy(tp, 0x13, 0x810e);
3867         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3868         rtl_writephy(tp, 0x13, 0x810c);
3869         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3870         rtl_writephy(tp, 0x13, 0x810b);
3871         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3872         rtl_writephy(tp, 0x1f, 0x0a43);
3873         rtl_writephy(tp, 0x13, 0x80d1);
3874         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3875         rtl_writephy(tp, 0x13, 0x80cd);
3876         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3877         rtl_writephy(tp, 0x13, 0x80d3);
3878         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3879         rtl_writephy(tp, 0x13, 0x80d5);
3880         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3881         rtl_writephy(tp, 0x13, 0x80d7);
3882         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3883
3884         /* Force PWM-mode */
3885         rtl_writephy(tp, 0x1f, 0x0bcd);
3886         rtl_writephy(tp, 0x14, 0x5065);
3887         rtl_writephy(tp, 0x14, 0xd065);
3888         rtl_writephy(tp, 0x1f, 0x0bc8);
3889         rtl_writephy(tp, 0x12, 0x00ed);
3890         rtl_writephy(tp, 0x1f, 0x0bcd);
3891         rtl_writephy(tp, 0x14, 0x1065);
3892         rtl_writephy(tp, 0x14, 0x9065);
3893         rtl_writephy(tp, 0x14, 0x1065);
3894         rtl_writephy(tp, 0x1f, 0x0000);
3895
3896         /* Check ALDPS bit, disable it if enabled */
3897         rtl_writephy(tp, 0x1f, 0x0a43);
3898         if (rtl_readphy(tp, 0x10) & 0x0004)
3899                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3900
3901         rtl_writephy(tp, 0x1f, 0x0000);
3902 }
3903
3904 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3905 {
3906         static const struct phy_reg phy_reg_init[] = {
3907                 { 0x1f, 0x0003 },
3908                 { 0x08, 0x441d },
3909                 { 0x01, 0x9100 },
3910                 { 0x1f, 0x0000 }
3911         };
3912
3913         rtl_writephy(tp, 0x1f, 0x0000);
3914         rtl_patchphy(tp, 0x11, 1 << 12);
3915         rtl_patchphy(tp, 0x19, 1 << 13);
3916         rtl_patchphy(tp, 0x10, 1 << 15);
3917
3918         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3919 }
3920
3921 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3922 {
3923         static const struct phy_reg phy_reg_init[] = {
3924                 { 0x1f, 0x0005 },
3925                 { 0x1a, 0x0000 },
3926                 { 0x1f, 0x0000 },
3927
3928                 { 0x1f, 0x0004 },
3929                 { 0x1c, 0x0000 },
3930                 { 0x1f, 0x0000 },
3931
3932                 { 0x1f, 0x0001 },
3933                 { 0x15, 0x7701 },
3934                 { 0x1f, 0x0000 }
3935         };
3936
3937         /* Disable ALDPS before ram code */
3938         rtl_writephy(tp, 0x1f, 0x0000);
3939         rtl_writephy(tp, 0x18, 0x0310);
3940         msleep(100);
3941
3942         rtl_apply_firmware(tp);
3943
3944         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3945 }
3946
3947 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3948 {
3949         /* Disable ALDPS before setting firmware */
3950         rtl_writephy(tp, 0x1f, 0x0000);
3951         rtl_writephy(tp, 0x18, 0x0310);
3952         msleep(20);
3953
3954         rtl_apply_firmware(tp);
3955
3956         /* EEE setting */
3957         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3958         rtl_writephy(tp, 0x1f, 0x0004);
3959         rtl_writephy(tp, 0x10, 0x401f);
3960         rtl_writephy(tp, 0x19, 0x7030);
3961         rtl_writephy(tp, 0x1f, 0x0000);
3962 }
3963
3964 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3965 {
3966         static const struct phy_reg phy_reg_init[] = {
3967                 { 0x1f, 0x0004 },
3968                 { 0x10, 0xc07f },
3969                 { 0x19, 0x7030 },
3970                 { 0x1f, 0x0000 }
3971         };
3972
3973         /* Disable ALDPS before ram code */
3974         rtl_writephy(tp, 0x1f, 0x0000);
3975         rtl_writephy(tp, 0x18, 0x0310);
3976         msleep(100);
3977
3978         rtl_apply_firmware(tp);
3979
3980         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3981         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3982
3983         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3984 }
3985
3986 static void rtl_hw_phy_config(struct net_device *dev)
3987 {
3988         struct rtl8169_private *tp = netdev_priv(dev);
3989
3990         rtl8169_print_mac_version(tp);
3991
3992         switch (tp->mac_version) {
3993         case RTL_GIGA_MAC_VER_01:
3994                 break;
3995         case RTL_GIGA_MAC_VER_02:
3996         case RTL_GIGA_MAC_VER_03:
3997                 rtl8169s_hw_phy_config(tp);
3998                 break;
3999         case RTL_GIGA_MAC_VER_04:
4000                 rtl8169sb_hw_phy_config(tp);
4001                 break;
4002         case RTL_GIGA_MAC_VER_05:
4003                 rtl8169scd_hw_phy_config(tp);
4004                 break;
4005         case RTL_GIGA_MAC_VER_06:
4006                 rtl8169sce_hw_phy_config(tp);
4007                 break;
4008         case RTL_GIGA_MAC_VER_07:
4009         case RTL_GIGA_MAC_VER_08:
4010         case RTL_GIGA_MAC_VER_09:
4011                 rtl8102e_hw_phy_config(tp);
4012                 break;
4013         case RTL_GIGA_MAC_VER_11:
4014                 rtl8168bb_hw_phy_config(tp);
4015                 break;
4016         case RTL_GIGA_MAC_VER_12:
4017                 rtl8168bef_hw_phy_config(tp);
4018                 break;
4019         case RTL_GIGA_MAC_VER_17:
4020                 rtl8168bef_hw_phy_config(tp);
4021                 break;
4022         case RTL_GIGA_MAC_VER_18:
4023                 rtl8168cp_1_hw_phy_config(tp);
4024                 break;
4025         case RTL_GIGA_MAC_VER_19:
4026                 rtl8168c_1_hw_phy_config(tp);
4027                 break;
4028         case RTL_GIGA_MAC_VER_20:
4029                 rtl8168c_2_hw_phy_config(tp);
4030                 break;
4031         case RTL_GIGA_MAC_VER_21:
4032                 rtl8168c_3_hw_phy_config(tp);
4033                 break;
4034         case RTL_GIGA_MAC_VER_22:
4035                 rtl8168c_4_hw_phy_config(tp);
4036                 break;
4037         case RTL_GIGA_MAC_VER_23:
4038         case RTL_GIGA_MAC_VER_24:
4039                 rtl8168cp_2_hw_phy_config(tp);
4040                 break;
4041         case RTL_GIGA_MAC_VER_25:
4042                 rtl8168d_1_hw_phy_config(tp);
4043                 break;
4044         case RTL_GIGA_MAC_VER_26:
4045                 rtl8168d_2_hw_phy_config(tp);
4046                 break;
4047         case RTL_GIGA_MAC_VER_27:
4048                 rtl8168d_3_hw_phy_config(tp);
4049                 break;
4050         case RTL_GIGA_MAC_VER_28:
4051                 rtl8168d_4_hw_phy_config(tp);
4052                 break;
4053         case RTL_GIGA_MAC_VER_29:
4054         case RTL_GIGA_MAC_VER_30:
4055                 rtl8105e_hw_phy_config(tp);
4056                 break;
4057         case RTL_GIGA_MAC_VER_31:
4058                 /* None. */
4059                 break;
4060         case RTL_GIGA_MAC_VER_32:
4061         case RTL_GIGA_MAC_VER_33:
4062                 rtl8168e_1_hw_phy_config(tp);
4063                 break;
4064         case RTL_GIGA_MAC_VER_34:
4065                 rtl8168e_2_hw_phy_config(tp);
4066                 break;
4067         case RTL_GIGA_MAC_VER_35:
4068                 rtl8168f_1_hw_phy_config(tp);
4069                 break;
4070         case RTL_GIGA_MAC_VER_36:
4071                 rtl8168f_2_hw_phy_config(tp);
4072                 break;
4073
4074         case RTL_GIGA_MAC_VER_37:
4075                 rtl8402_hw_phy_config(tp);
4076                 break;
4077
4078         case RTL_GIGA_MAC_VER_38:
4079                 rtl8411_hw_phy_config(tp);
4080                 break;
4081
4082         case RTL_GIGA_MAC_VER_39:
4083                 rtl8106e_hw_phy_config(tp);
4084                 break;
4085
4086         case RTL_GIGA_MAC_VER_40:
4087                 rtl8168g_1_hw_phy_config(tp);
4088                 break;
4089         case RTL_GIGA_MAC_VER_42:
4090         case RTL_GIGA_MAC_VER_43:
4091         case RTL_GIGA_MAC_VER_44:
4092                 rtl8168g_2_hw_phy_config(tp);
4093                 break;
4094         case RTL_GIGA_MAC_VER_45:
4095         case RTL_GIGA_MAC_VER_47:
4096                 rtl8168h_1_hw_phy_config(tp);
4097                 break;
4098         case RTL_GIGA_MAC_VER_46:
4099         case RTL_GIGA_MAC_VER_48:
4100                 rtl8168h_2_hw_phy_config(tp);
4101                 break;
4102
4103         case RTL_GIGA_MAC_VER_49:
4104                 rtl8168ep_1_hw_phy_config(tp);
4105                 break;
4106         case RTL_GIGA_MAC_VER_50:
4107         case RTL_GIGA_MAC_VER_51:
4108                 rtl8168ep_2_hw_phy_config(tp);
4109                 break;
4110
4111         case RTL_GIGA_MAC_VER_41:
4112         default:
4113                 break;
4114         }
4115 }
4116
4117 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4118 {
4119         if (!test_and_set_bit(flag, tp->wk.flags))
4120                 schedule_work(&tp->wk.work);
4121 }
4122
4123 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4124 {
4125         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4126                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4127 }
4128
4129 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4130 {
4131         rtl_hw_phy_config(dev);
4132
4133         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4134                 netif_dbg(tp, drv, dev,
4135                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4136                 RTL_W8(tp, 0x82, 0x01);
4137         }
4138
4139         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4140
4141         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4142                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4143
4144         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4145                 netif_dbg(tp, drv, dev,
4146                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4147                 RTL_W8(tp, 0x82, 0x01);
4148                 netif_dbg(tp, drv, dev,
4149                           "Set PHY Reg 0x0bh = 0x00h\n");
4150                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4151         }
4152
4153         /* We may have called phy_speed_down before */
4154         phy_speed_up(dev->phydev);
4155
4156         genphy_soft_reset(dev->phydev);
4157 }
4158
4159 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4160 {
4161         rtl_lock_work(tp);
4162
4163         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4164
4165         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4166         RTL_R32(tp, MAC4);
4167
4168         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4169         RTL_R32(tp, MAC0);
4170
4171         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4172                 rtl_rar_exgmac_set(tp, addr);
4173
4174         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4175
4176         rtl_unlock_work(tp);
4177 }
4178
4179 static int rtl_set_mac_address(struct net_device *dev, void *p)
4180 {
4181         struct rtl8169_private *tp = netdev_priv(dev);
4182         struct device *d = tp_to_dev(tp);
4183         int ret;
4184
4185         ret = eth_mac_addr(dev, p);
4186         if (ret)
4187                 return ret;
4188
4189         pm_runtime_get_noresume(d);
4190
4191         if (pm_runtime_active(d))
4192                 rtl_rar_set(tp, dev->dev_addr);
4193
4194         pm_runtime_put_noidle(d);
4195
4196         return 0;
4197 }
4198
4199 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4200 {
4201         if (!netif_running(dev))
4202                 return -ENODEV;
4203
4204         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4205 }
4206
4207 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4208 {
4209         struct mdio_ops *ops = &tp->mdio_ops;
4210
4211         switch (tp->mac_version) {
4212         case RTL_GIGA_MAC_VER_27:
4213                 ops->write      = r8168dp_1_mdio_write;
4214                 ops->read       = r8168dp_1_mdio_read;
4215                 break;
4216         case RTL_GIGA_MAC_VER_28:
4217         case RTL_GIGA_MAC_VER_31:
4218                 ops->write      = r8168dp_2_mdio_write;
4219                 ops->read       = r8168dp_2_mdio_read;
4220                 break;
4221         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4222                 ops->write      = r8168g_mdio_write;
4223                 ops->read       = r8168g_mdio_read;
4224                 break;
4225         default:
4226                 ops->write      = r8169_mdio_write;
4227                 ops->read       = r8169_mdio_read;
4228                 break;
4229         }
4230 }
4231
4232 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4233 {
4234         switch (tp->mac_version) {
4235         case RTL_GIGA_MAC_VER_25:
4236         case RTL_GIGA_MAC_VER_26:
4237         case RTL_GIGA_MAC_VER_29:
4238         case RTL_GIGA_MAC_VER_30:
4239         case RTL_GIGA_MAC_VER_32:
4240         case RTL_GIGA_MAC_VER_33:
4241         case RTL_GIGA_MAC_VER_34:
4242         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4243                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4244                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4245                 break;
4246         default:
4247                 break;
4248         }
4249 }
4250
4251 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4252 {
4253         if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4254                 return false;
4255
4256         phy_speed_down(tp->dev->phydev, false);
4257         rtl_wol_suspend_quirk(tp);
4258
4259         return true;
4260 }
4261
4262 static void r8168_pll_power_down(struct rtl8169_private *tp)
4263 {
4264         if (r8168_check_dash(tp))
4265                 return;
4266
4267         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4268             tp->mac_version == RTL_GIGA_MAC_VER_33)
4269                 rtl_ephy_write(tp, 0x19, 0xff64);
4270
4271         if (rtl_wol_pll_power_down(tp))
4272                 return;
4273
4274         switch (tp->mac_version) {
4275         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4276         case RTL_GIGA_MAC_VER_37:
4277         case RTL_GIGA_MAC_VER_39:
4278         case RTL_GIGA_MAC_VER_43:
4279         case RTL_GIGA_MAC_VER_44:
4280         case RTL_GIGA_MAC_VER_45:
4281         case RTL_GIGA_MAC_VER_46:
4282         case RTL_GIGA_MAC_VER_47:
4283         case RTL_GIGA_MAC_VER_48:
4284         case RTL_GIGA_MAC_VER_50:
4285         case RTL_GIGA_MAC_VER_51:
4286                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4287                 break;
4288         case RTL_GIGA_MAC_VER_40:
4289         case RTL_GIGA_MAC_VER_41:
4290         case RTL_GIGA_MAC_VER_49:
4291                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4292                              0xfc000000, ERIAR_EXGMAC);
4293                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4294                 break;
4295         }
4296 }
4297
4298 static void r8168_pll_power_up(struct rtl8169_private *tp)
4299 {
4300         switch (tp->mac_version) {
4301         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4302         case RTL_GIGA_MAC_VER_37:
4303         case RTL_GIGA_MAC_VER_39:
4304         case RTL_GIGA_MAC_VER_43:
4305                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4306                 break;
4307         case RTL_GIGA_MAC_VER_44:
4308         case RTL_GIGA_MAC_VER_45:
4309         case RTL_GIGA_MAC_VER_46:
4310         case RTL_GIGA_MAC_VER_47:
4311         case RTL_GIGA_MAC_VER_48:
4312         case RTL_GIGA_MAC_VER_50:
4313         case RTL_GIGA_MAC_VER_51:
4314                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4315                 break;
4316         case RTL_GIGA_MAC_VER_40:
4317         case RTL_GIGA_MAC_VER_41:
4318         case RTL_GIGA_MAC_VER_49:
4319                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4320                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4321                              0x00000000, ERIAR_EXGMAC);
4322                 break;
4323         }
4324
4325         phy_resume(tp->dev->phydev);
4326         /* give MAC/PHY some time to resume */
4327         msleep(20);
4328 }
4329
4330 static void rtl_pll_power_down(struct rtl8169_private *tp)
4331 {
4332         switch (tp->mac_version) {
4333         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4334         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4335                 break;
4336         default:
4337                 r8168_pll_power_down(tp);
4338         }
4339 }
4340
4341 static void rtl_pll_power_up(struct rtl8169_private *tp)
4342 {
4343         switch (tp->mac_version) {
4344         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4345         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4346                 break;
4347         default:
4348                 r8168_pll_power_up(tp);
4349         }
4350 }
4351
4352 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4353 {
4354         switch (tp->mac_version) {
4355         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4356         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4357                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4358                 break;
4359         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4360         case RTL_GIGA_MAC_VER_34:
4361         case RTL_GIGA_MAC_VER_35:
4362                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4363                 break;
4364         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4365                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4366                 break;
4367         default:
4368                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4369                 break;
4370         }
4371 }
4372
4373 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4374 {
4375         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4376 }
4377
4378 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4379 {
4380         if (tp->jumbo_ops.enable) {
4381                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4382                 tp->jumbo_ops.enable(tp);
4383                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4384         }
4385 }
4386
4387 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4388 {
4389         if (tp->jumbo_ops.disable) {
4390                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4391                 tp->jumbo_ops.disable(tp);
4392                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4393         }
4394 }
4395
4396 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4397 {
4398         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4399         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4400         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4401 }
4402
4403 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4404 {
4405         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4406         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4407         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4408 }
4409
4410 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4411 {
4412         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4413 }
4414
4415 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4416 {
4417         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4418 }
4419
4420 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4421 {
4422         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4423         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4424         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4425         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4426 }
4427
4428 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4429 {
4430         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4431         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4432         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4433         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4434 }
4435
4436 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4437 {
4438         rtl_tx_performance_tweak(tp,
4439                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4440 }
4441
4442 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4443 {
4444         rtl_tx_performance_tweak(tp,
4445                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4446 }
4447
4448 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4449 {
4450         r8168b_0_hw_jumbo_enable(tp);
4451
4452         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4453 }
4454
4455 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4456 {
4457         r8168b_0_hw_jumbo_disable(tp);
4458
4459         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4460 }
4461
4462 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4463 {
4464         struct jumbo_ops *ops = &tp->jumbo_ops;
4465
4466         switch (tp->mac_version) {
4467         case RTL_GIGA_MAC_VER_11:
4468                 ops->disable    = r8168b_0_hw_jumbo_disable;
4469                 ops->enable     = r8168b_0_hw_jumbo_enable;
4470                 break;
4471         case RTL_GIGA_MAC_VER_12:
4472         case RTL_GIGA_MAC_VER_17:
4473                 ops->disable    = r8168b_1_hw_jumbo_disable;
4474                 ops->enable     = r8168b_1_hw_jumbo_enable;
4475                 break;
4476         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4477         case RTL_GIGA_MAC_VER_19:
4478         case RTL_GIGA_MAC_VER_20:
4479         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4480         case RTL_GIGA_MAC_VER_22:
4481         case RTL_GIGA_MAC_VER_23:
4482         case RTL_GIGA_MAC_VER_24:
4483         case RTL_GIGA_MAC_VER_25:
4484         case RTL_GIGA_MAC_VER_26:
4485                 ops->disable    = r8168c_hw_jumbo_disable;
4486                 ops->enable     = r8168c_hw_jumbo_enable;
4487                 break;
4488         case RTL_GIGA_MAC_VER_27:
4489         case RTL_GIGA_MAC_VER_28:
4490                 ops->disable    = r8168dp_hw_jumbo_disable;
4491                 ops->enable     = r8168dp_hw_jumbo_enable;
4492                 break;
4493         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4494         case RTL_GIGA_MAC_VER_32:
4495         case RTL_GIGA_MAC_VER_33:
4496         case RTL_GIGA_MAC_VER_34:
4497                 ops->disable    = r8168e_hw_jumbo_disable;
4498                 ops->enable     = r8168e_hw_jumbo_enable;
4499                 break;
4500
4501         /*
4502          * No action needed for jumbo frames with 8169.
4503          * No jumbo for 810x at all.
4504          */
4505         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4506         default:
4507                 ops->disable    = NULL;
4508                 ops->enable     = NULL;
4509                 break;
4510         }
4511 }
4512
4513 DECLARE_RTL_COND(rtl_chipcmd_cond)
4514 {
4515         return RTL_R8(tp, ChipCmd) & CmdReset;
4516 }
4517
4518 static void rtl_hw_reset(struct rtl8169_private *tp)
4519 {
4520         RTL_W8(tp, ChipCmd, CmdReset);
4521
4522         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4523 }
4524
4525 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4526 {
4527         struct rtl_fw *rtl_fw;
4528         const char *name;
4529         int rc = -ENOMEM;
4530
4531         name = rtl_lookup_firmware_name(tp);
4532         if (!name)
4533                 goto out_no_firmware;
4534
4535         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4536         if (!rtl_fw)
4537                 goto err_warn;
4538
4539         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4540         if (rc < 0)
4541                 goto err_free;
4542
4543         rc = rtl_check_firmware(tp, rtl_fw);
4544         if (rc < 0)
4545                 goto err_release_firmware;
4546
4547         tp->rtl_fw = rtl_fw;
4548 out:
4549         return;
4550
4551 err_release_firmware:
4552         release_firmware(rtl_fw->fw);
4553 err_free:
4554         kfree(rtl_fw);
4555 err_warn:
4556         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4557                    name, rc);
4558 out_no_firmware:
4559         tp->rtl_fw = NULL;
4560         goto out;
4561 }
4562
4563 static void rtl_request_firmware(struct rtl8169_private *tp)
4564 {
4565         if (IS_ERR(tp->rtl_fw))
4566                 rtl_request_uncached_firmware(tp);
4567 }
4568
4569 static void rtl_rx_close(struct rtl8169_private *tp)
4570 {
4571         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4572 }
4573
4574 DECLARE_RTL_COND(rtl_npq_cond)
4575 {
4576         return RTL_R8(tp, TxPoll) & NPQ;
4577 }
4578
4579 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4580 {
4581         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4582 }
4583
4584 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4585 {
4586         /* Disable interrupts */
4587         rtl8169_irq_mask_and_ack(tp);
4588
4589         rtl_rx_close(tp);
4590
4591         switch (tp->mac_version) {
4592         case RTL_GIGA_MAC_VER_27:
4593         case RTL_GIGA_MAC_VER_28:
4594         case RTL_GIGA_MAC_VER_31:
4595                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4596                 break;
4597         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4598         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4599                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4600                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4601                 break;
4602         default:
4603                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4604                 udelay(100);
4605                 break;
4606         }
4607
4608         rtl_hw_reset(tp);
4609 }
4610
4611 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4612 {
4613         /* Set DMA burst size and Interframe Gap Time */
4614         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
4615                 (InterFrameGap << TxInterFrameGapShift));
4616 }
4617
4618 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4619 {
4620         /* Low hurts. Let's disable the filtering. */
4621         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4622 }
4623
4624 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4625 {
4626         /*
4627          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4628          * register to be written before TxDescAddrLow to work.
4629          * Switching from MMIO to I/O access fixes the issue as well.
4630          */
4631         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4632         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4633         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4634         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4635 }
4636
4637 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4638 {
4639         static const struct rtl_cfg2_info {
4640                 u32 mac_version;
4641                 u32 clk;
4642                 u32 val;
4643         } cfg2_info [] = {
4644                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4645                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4646                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4647                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4648         };
4649         const struct rtl_cfg2_info *p = cfg2_info;
4650         unsigned int i;
4651         u32 clk;
4652
4653         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4654         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4655                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4656                         RTL_W32(tp, 0x7c, p->val);
4657                         break;
4658                 }
4659         }
4660 }
4661
4662 static void rtl_set_rx_mode(struct net_device *dev)
4663 {
4664         struct rtl8169_private *tp = netdev_priv(dev);
4665         u32 mc_filter[2];       /* Multicast hash filter */
4666         int rx_mode;
4667         u32 tmp = 0;
4668
4669         if (dev->flags & IFF_PROMISC) {
4670                 /* Unconditionally log net taps. */
4671                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4672                 rx_mode =
4673                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4674                     AcceptAllPhys;
4675                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4676         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4677                    (dev->flags & IFF_ALLMULTI)) {
4678                 /* Too many to filter perfectly -- accept all multicasts. */
4679                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4680                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4681         } else {
4682                 struct netdev_hw_addr *ha;
4683
4684                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4685                 mc_filter[1] = mc_filter[0] = 0;
4686                 netdev_for_each_mc_addr(ha, dev) {
4687                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4688                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4689                         rx_mode |= AcceptMulticast;
4690                 }
4691         }
4692
4693         if (dev->features & NETIF_F_RXALL)
4694                 rx_mode |= (AcceptErr | AcceptRunt);
4695
4696         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4697
4698         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4699                 u32 data = mc_filter[0];
4700
4701                 mc_filter[0] = swab32(mc_filter[1]);
4702                 mc_filter[1] = swab32(data);
4703         }
4704
4705         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4706                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4707
4708         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4709         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4710
4711         RTL_W32(tp, RxConfig, tmp);
4712 }
4713
4714 static void rtl_hw_start(struct  rtl8169_private *tp)
4715 {
4716         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4717
4718         tp->hw_start(tp);
4719
4720         rtl_set_rx_max_size(tp);
4721         rtl_set_rx_tx_desc_registers(tp);
4722         rtl_set_rx_tx_config_registers(tp);
4723         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4724
4725         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4726         RTL_R8(tp, IntrMask);
4727         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4728         rtl_set_rx_mode(tp->dev);
4729         /* no early-rx interrupts */
4730         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4731         rtl_irq_enable_all(tp);
4732 }
4733
4734 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4735 {
4736         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4737                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4738
4739         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4740
4741         tp->cp_cmd |= PCIMulRW;
4742
4743         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4744             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4745                 netif_dbg(tp, drv, tp->dev,
4746                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4747                 tp->cp_cmd |= (1 << 14);
4748         }
4749
4750         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4751
4752         rtl8169_set_magic_reg(tp, tp->mac_version);
4753
4754         /*
4755          * Undocumented corner. Supposedly:
4756          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4757          */
4758         RTL_W16(tp, IntrMitigate, 0x0000);
4759
4760         RTL_W32(tp, RxMissed, 0);
4761 }
4762
4763 DECLARE_RTL_COND(rtl_csiar_cond)
4764 {
4765         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4766 }
4767
4768 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4769 {
4770         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4771
4772         RTL_W32(tp, CSIDR, value);
4773         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4774                 CSIAR_BYTE_ENABLE | func << 16);
4775
4776         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4777 }
4778
4779 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4780 {
4781         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4782
4783         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4784                 CSIAR_BYTE_ENABLE);
4785
4786         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4787                 RTL_R32(tp, CSIDR) : ~0;
4788 }
4789
4790 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4791 {
4792         struct pci_dev *pdev = tp->pci_dev;
4793         u32 csi;
4794
4795         /* According to Realtek the value at config space address 0x070f
4796          * controls the L0s/L1 entrance latency. We try standard ECAM access
4797          * first and if it fails fall back to CSI.
4798          */
4799         if (pdev->cfg_size > 0x070f &&
4800             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4801                 return;
4802
4803         netdev_notice_once(tp->dev,
4804                 "No native access to PCI extended config space, falling back to CSI\n");
4805         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4806         rtl_csi_write(tp, 0x070c, csi | val << 24);
4807 }
4808
4809 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4810 {
4811         rtl_csi_access_enable(tp, 0x27);
4812 }
4813
4814 struct ephy_info {
4815         unsigned int offset;
4816         u16 mask;
4817         u16 bits;
4818 };
4819
4820 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4821                           int len)
4822 {
4823         u16 w;
4824
4825         while (len-- > 0) {
4826                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4827                 rtl_ephy_write(tp, e->offset, w);
4828                 e++;
4829         }
4830 }
4831
4832 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4833 {
4834         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4835                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4836 }
4837
4838 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4839 {
4840         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4841                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4842 }
4843
4844 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4845 {
4846         u8 data;
4847
4848         data = RTL_R8(tp, Config3);
4849
4850         if (enable)
4851                 data |= Rdy_to_L23;
4852         else
4853                 data &= ~Rdy_to_L23;
4854
4855         RTL_W8(tp, Config3, data);
4856 }
4857
4858 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4859 {
4860         if (enable) {
4861                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4862                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4863         } else {
4864                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4865                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4866         }
4867 }
4868
4869 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4870 {
4871         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4872
4873         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4874         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4875
4876         if (tp->dev->mtu <= ETH_DATA_LEN) {
4877                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4878                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4879         }
4880 }
4881
4882 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4883 {
4884         rtl_hw_start_8168bb(tp);
4885
4886         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4887
4888         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4889 }
4890
4891 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4892 {
4893         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4894
4895         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4896
4897         if (tp->dev->mtu <= ETH_DATA_LEN)
4898                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4899
4900         rtl_disable_clock_request(tp);
4901
4902         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4903         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4904 }
4905
4906 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4907 {
4908         static const struct ephy_info e_info_8168cp[] = {
4909                 { 0x01, 0,      0x0001 },
4910                 { 0x02, 0x0800, 0x1000 },
4911                 { 0x03, 0,      0x0042 },
4912                 { 0x06, 0x0080, 0x0000 },
4913                 { 0x07, 0,      0x2000 }
4914         };
4915
4916         rtl_set_def_aspm_entry_latency(tp);
4917
4918         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4919
4920         __rtl_hw_start_8168cp(tp);
4921 }
4922
4923 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4924 {
4925         rtl_set_def_aspm_entry_latency(tp);
4926
4927         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4928
4929         if (tp->dev->mtu <= ETH_DATA_LEN)
4930                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4931
4932         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4933         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4934 }
4935
4936 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4937 {
4938         rtl_set_def_aspm_entry_latency(tp);
4939
4940         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4941
4942         /* Magic. */
4943         RTL_W8(tp, DBG_REG, 0x20);
4944
4945         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4946
4947         if (tp->dev->mtu <= ETH_DATA_LEN)
4948                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4949
4950         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4951         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4952 }
4953
4954 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4955 {
4956         static const struct ephy_info e_info_8168c_1[] = {
4957                 { 0x02, 0x0800, 0x1000 },
4958                 { 0x03, 0,      0x0002 },
4959                 { 0x06, 0x0080, 0x0000 }
4960         };
4961
4962         rtl_set_def_aspm_entry_latency(tp);
4963
4964         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4965
4966         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4967
4968         __rtl_hw_start_8168cp(tp);
4969 }
4970
4971 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4972 {
4973         static const struct ephy_info e_info_8168c_2[] = {
4974                 { 0x01, 0,      0x0001 },
4975                 { 0x03, 0x0400, 0x0220 }
4976         };
4977
4978         rtl_set_def_aspm_entry_latency(tp);
4979
4980         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4981
4982         __rtl_hw_start_8168cp(tp);
4983 }
4984
4985 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4986 {
4987         rtl_hw_start_8168c_2(tp);
4988 }
4989
4990 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4991 {
4992         rtl_set_def_aspm_entry_latency(tp);
4993
4994         __rtl_hw_start_8168cp(tp);
4995 }
4996
4997 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4998 {
4999         rtl_set_def_aspm_entry_latency(tp);
5000
5001         rtl_disable_clock_request(tp);
5002
5003         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5004
5005         if (tp->dev->mtu <= ETH_DATA_LEN)
5006                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5007
5008         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5009         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5010 }
5011
5012 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5013 {
5014         rtl_set_def_aspm_entry_latency(tp);
5015
5016         if (tp->dev->mtu <= ETH_DATA_LEN)
5017                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5018
5019         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5020
5021         rtl_disable_clock_request(tp);
5022 }
5023
5024 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5025 {
5026         static const struct ephy_info e_info_8168d_4[] = {
5027                 { 0x0b, 0x0000, 0x0048 },
5028                 { 0x19, 0x0020, 0x0050 },
5029                 { 0x0c, 0x0100, 0x0020 }
5030         };
5031
5032         rtl_set_def_aspm_entry_latency(tp);
5033
5034         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5035
5036         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5037
5038         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5039
5040         rtl_enable_clock_request(tp);
5041 }
5042
5043 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5044 {
5045         static const struct ephy_info e_info_8168e_1[] = {
5046                 { 0x00, 0x0200, 0x0100 },
5047                 { 0x00, 0x0000, 0x0004 },
5048                 { 0x06, 0x0002, 0x0001 },
5049                 { 0x06, 0x0000, 0x0030 },
5050                 { 0x07, 0x0000, 0x2000 },
5051                 { 0x00, 0x0000, 0x0020 },
5052                 { 0x03, 0x5800, 0x2000 },
5053                 { 0x03, 0x0000, 0x0001 },
5054                 { 0x01, 0x0800, 0x1000 },
5055                 { 0x07, 0x0000, 0x4000 },
5056                 { 0x1e, 0x0000, 0x2000 },
5057                 { 0x19, 0xffff, 0xfe6c },
5058                 { 0x0a, 0x0000, 0x0040 }
5059         };
5060
5061         rtl_set_def_aspm_entry_latency(tp);
5062
5063         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5064
5065         if (tp->dev->mtu <= ETH_DATA_LEN)
5066                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5067
5068         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5069
5070         rtl_disable_clock_request(tp);
5071
5072         /* Reset tx FIFO pointer */
5073         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5074         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5075
5076         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5077 }
5078
5079 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5080 {
5081         static const struct ephy_info e_info_8168e_2[] = {
5082                 { 0x09, 0x0000, 0x0080 },
5083                 { 0x19, 0x0000, 0x0224 }
5084         };
5085
5086         rtl_set_def_aspm_entry_latency(tp);
5087
5088         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5089
5090         if (tp->dev->mtu <= ETH_DATA_LEN)
5091                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5092
5093         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5094         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5095         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5096         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5097         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5098         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5099         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5100         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5101
5102         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5103
5104         rtl_disable_clock_request(tp);
5105
5106         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5107         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5108
5109         /* Adjust EEE LED frequency */
5110         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5111
5112         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5113         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5114         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5115
5116         rtl_hw_aspm_clkreq_enable(tp, true);
5117 }
5118
5119 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5120 {
5121         rtl_set_def_aspm_entry_latency(tp);
5122
5123         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5124
5125         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5126         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5127         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5128         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5129         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5130         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5131         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5132         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5133         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5134         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5135
5136         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5137
5138         rtl_disable_clock_request(tp);
5139
5140         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5141         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5142         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5143         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5144         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5145 }
5146
5147 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5148 {
5149         static const struct ephy_info e_info_8168f_1[] = {
5150                 { 0x06, 0x00c0, 0x0020 },
5151                 { 0x08, 0x0001, 0x0002 },
5152                 { 0x09, 0x0000, 0x0080 },
5153                 { 0x19, 0x0000, 0x0224 }
5154         };
5155
5156         rtl_hw_start_8168f(tp);
5157
5158         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5159
5160         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5161
5162         /* Adjust EEE LED frequency */
5163         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5164 }
5165
5166 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5167 {
5168         static const struct ephy_info e_info_8168f_1[] = {
5169                 { 0x06, 0x00c0, 0x0020 },
5170                 { 0x0f, 0xffff, 0x5200 },
5171                 { 0x1e, 0x0000, 0x4000 },
5172                 { 0x19, 0x0000, 0x0224 }
5173         };
5174
5175         rtl_hw_start_8168f(tp);
5176         rtl_pcie_state_l2l3_enable(tp, false);
5177
5178         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5179
5180         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5181 }
5182
5183 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5184 {
5185         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5186
5187         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5188         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5189         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5190         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5191
5192         rtl_set_def_aspm_entry_latency(tp);
5193
5194         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5195
5196         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5197         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5198         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5199
5200         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5201         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5202
5203         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5204         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5205
5206         /* Adjust EEE LED frequency */
5207         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5208
5209         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5210         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5211
5212         rtl_pcie_state_l2l3_enable(tp, false);
5213 }
5214
5215 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5216 {
5217         static const struct ephy_info e_info_8168g_1[] = {
5218                 { 0x00, 0x0000, 0x0008 },
5219                 { 0x0c, 0x37d0, 0x0820 },
5220                 { 0x1e, 0x0000, 0x0001 },
5221                 { 0x19, 0x8000, 0x0000 }
5222         };
5223
5224         rtl_hw_start_8168g(tp);
5225
5226         /* disable aspm and clock request before access ephy */
5227         rtl_hw_aspm_clkreq_enable(tp, false);
5228         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5229         rtl_hw_aspm_clkreq_enable(tp, true);
5230 }
5231
5232 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5233 {
5234         static const struct ephy_info e_info_8168g_2[] = {
5235                 { 0x00, 0x0000, 0x0008 },
5236                 { 0x0c, 0x3df0, 0x0200 },
5237                 { 0x19, 0xffff, 0xfc00 },
5238                 { 0x1e, 0xffff, 0x20eb }
5239         };
5240
5241         rtl_hw_start_8168g(tp);
5242
5243         /* disable aspm and clock request before access ephy */
5244         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5245         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5246         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5247 }
5248
5249 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5250 {
5251         static const struct ephy_info e_info_8411_2[] = {
5252                 { 0x00, 0x0000, 0x0008 },
5253                 { 0x0c, 0x3df0, 0x0200 },
5254                 { 0x0f, 0xffff, 0x5200 },
5255                 { 0x19, 0x0020, 0x0000 },
5256                 { 0x1e, 0x0000, 0x2000 }
5257         };
5258
5259         rtl_hw_start_8168g(tp);
5260
5261         /* disable aspm and clock request before access ephy */
5262         rtl_hw_aspm_clkreq_enable(tp, false);
5263         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5264         rtl_hw_aspm_clkreq_enable(tp, true);
5265 }
5266
5267 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5268 {
5269         int rg_saw_cnt;
5270         u32 data;
5271         static const struct ephy_info e_info_8168h_1[] = {
5272                 { 0x1e, 0x0800, 0x0001 },
5273                 { 0x1d, 0x0000, 0x0800 },
5274                 { 0x05, 0xffff, 0x2089 },
5275                 { 0x06, 0xffff, 0x5881 },
5276                 { 0x04, 0xffff, 0x154a },
5277                 { 0x01, 0xffff, 0x068b }
5278         };
5279
5280         /* disable aspm and clock request before access ephy */
5281         rtl_hw_aspm_clkreq_enable(tp, false);
5282         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5283
5284         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5285
5286         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5287         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5288         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5289         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5290
5291         rtl_set_def_aspm_entry_latency(tp);
5292
5293         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5294
5295         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5296         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5297
5298         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5299
5300         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5301
5302         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5303
5304         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5305         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5306
5307         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5308         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5309
5310         /* Adjust EEE LED frequency */
5311         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5312
5313         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5314         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5315
5316         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5317
5318         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5319
5320         rtl_pcie_state_l2l3_enable(tp, false);
5321
5322         rtl_writephy(tp, 0x1f, 0x0c42);
5323         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5324         rtl_writephy(tp, 0x1f, 0x0000);
5325         if (rg_saw_cnt > 0) {
5326                 u16 sw_cnt_1ms_ini;
5327
5328                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5329                 sw_cnt_1ms_ini &= 0x0fff;
5330                 data = r8168_mac_ocp_read(tp, 0xd412);
5331                 data &= ~0x0fff;
5332                 data |= sw_cnt_1ms_ini;
5333                 r8168_mac_ocp_write(tp, 0xd412, data);
5334         }
5335
5336         data = r8168_mac_ocp_read(tp, 0xe056);
5337         data &= ~0xf0;
5338         data |= 0x70;
5339         r8168_mac_ocp_write(tp, 0xe056, data);
5340
5341         data = r8168_mac_ocp_read(tp, 0xe052);
5342         data &= ~0x6000;
5343         data |= 0x8008;
5344         r8168_mac_ocp_write(tp, 0xe052, data);
5345
5346         data = r8168_mac_ocp_read(tp, 0xe0d6);
5347         data &= ~0x01ff;
5348         data |= 0x017f;
5349         r8168_mac_ocp_write(tp, 0xe0d6, data);
5350
5351         data = r8168_mac_ocp_read(tp, 0xd420);
5352         data &= ~0x0fff;
5353         data |= 0x047f;
5354         r8168_mac_ocp_write(tp, 0xd420, data);
5355
5356         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5357         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5358         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5359         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5360
5361         rtl_hw_aspm_clkreq_enable(tp, true);
5362 }
5363
5364 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5365 {
5366         rtl8168ep_stop_cmac(tp);
5367
5368         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5369
5370         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5371         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5372         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5373         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5374
5375         rtl_set_def_aspm_entry_latency(tp);
5376
5377         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5378
5379         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5380         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5381
5382         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5383
5384         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5385
5386         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5387         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5388
5389         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5390         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5391
5392         /* Adjust EEE LED frequency */
5393         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5394
5395         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5396
5397         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5398
5399         rtl_pcie_state_l2l3_enable(tp, false);
5400 }
5401
5402 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5403 {
5404         static const struct ephy_info e_info_8168ep_1[] = {
5405                 { 0x00, 0xffff, 0x10ab },
5406                 { 0x06, 0xffff, 0xf030 },
5407                 { 0x08, 0xffff, 0x2006 },
5408                 { 0x0d, 0xffff, 0x1666 },
5409                 { 0x0c, 0x3ff0, 0x0000 }
5410         };
5411
5412         /* disable aspm and clock request before access ephy */
5413         rtl_hw_aspm_clkreq_enable(tp, false);
5414         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5415
5416         rtl_hw_start_8168ep(tp);
5417
5418         rtl_hw_aspm_clkreq_enable(tp, true);
5419 }
5420
5421 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5422 {
5423         static const struct ephy_info e_info_8168ep_2[] = {
5424                 { 0x00, 0xffff, 0x10a3 },
5425                 { 0x19, 0xffff, 0xfc00 },
5426                 { 0x1e, 0xffff, 0x20ea }
5427         };
5428
5429         /* disable aspm and clock request before access ephy */
5430         rtl_hw_aspm_clkreq_enable(tp, false);
5431         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5432
5433         rtl_hw_start_8168ep(tp);
5434
5435         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5436         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5437
5438         rtl_hw_aspm_clkreq_enable(tp, true);
5439 }
5440
5441 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5442 {
5443         u32 data;
5444         static const struct ephy_info e_info_8168ep_3[] = {
5445                 { 0x00, 0xffff, 0x10a3 },
5446                 { 0x19, 0xffff, 0x7c00 },
5447                 { 0x1e, 0xffff, 0x20eb },
5448                 { 0x0d, 0xffff, 0x1666 }
5449         };
5450
5451         /* disable aspm and clock request before access ephy */
5452         rtl_hw_aspm_clkreq_enable(tp, false);
5453         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5454
5455         rtl_hw_start_8168ep(tp);
5456
5457         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5458         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5459
5460         data = r8168_mac_ocp_read(tp, 0xd3e2);
5461         data &= 0xf000;
5462         data |= 0x0271;
5463         r8168_mac_ocp_write(tp, 0xd3e2, data);
5464
5465         data = r8168_mac_ocp_read(tp, 0xd3e4);
5466         data &= 0xff00;
5467         r8168_mac_ocp_write(tp, 0xd3e4, data);
5468
5469         data = r8168_mac_ocp_read(tp, 0xe860);
5470         data |= 0x0080;
5471         r8168_mac_ocp_write(tp, 0xe860, data);
5472
5473         rtl_hw_aspm_clkreq_enable(tp, true);
5474 }
5475
5476 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5477 {
5478         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5479
5480         tp->cp_cmd &= ~INTT_MASK;
5481         tp->cp_cmd |= PktCntrDisable | INTT_1;
5482         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5483
5484         RTL_W16(tp, IntrMitigate, 0x5151);
5485
5486         /* Work around for RxFIFO overflow. */
5487         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5488                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5489                 tp->event_slow &= ~RxOverflow;
5490         }
5491
5492         switch (tp->mac_version) {
5493         case RTL_GIGA_MAC_VER_11:
5494                 rtl_hw_start_8168bb(tp);
5495                 break;
5496
5497         case RTL_GIGA_MAC_VER_12:
5498         case RTL_GIGA_MAC_VER_17:
5499                 rtl_hw_start_8168bef(tp);
5500                 break;
5501
5502         case RTL_GIGA_MAC_VER_18:
5503                 rtl_hw_start_8168cp_1(tp);
5504                 break;
5505
5506         case RTL_GIGA_MAC_VER_19:
5507                 rtl_hw_start_8168c_1(tp);
5508                 break;
5509
5510         case RTL_GIGA_MAC_VER_20:
5511                 rtl_hw_start_8168c_2(tp);
5512                 break;
5513
5514         case RTL_GIGA_MAC_VER_21:
5515                 rtl_hw_start_8168c_3(tp);
5516                 break;
5517
5518         case RTL_GIGA_MAC_VER_22:
5519                 rtl_hw_start_8168c_4(tp);
5520                 break;
5521
5522         case RTL_GIGA_MAC_VER_23:
5523                 rtl_hw_start_8168cp_2(tp);
5524                 break;
5525
5526         case RTL_GIGA_MAC_VER_24:
5527                 rtl_hw_start_8168cp_3(tp);
5528                 break;
5529
5530         case RTL_GIGA_MAC_VER_25:
5531         case RTL_GIGA_MAC_VER_26:
5532         case RTL_GIGA_MAC_VER_27:
5533                 rtl_hw_start_8168d(tp);
5534                 break;
5535
5536         case RTL_GIGA_MAC_VER_28:
5537                 rtl_hw_start_8168d_4(tp);
5538                 break;
5539
5540         case RTL_GIGA_MAC_VER_31:
5541                 rtl_hw_start_8168dp(tp);
5542                 break;
5543
5544         case RTL_GIGA_MAC_VER_32:
5545         case RTL_GIGA_MAC_VER_33:
5546                 rtl_hw_start_8168e_1(tp);
5547                 break;
5548         case RTL_GIGA_MAC_VER_34:
5549                 rtl_hw_start_8168e_2(tp);
5550                 break;
5551
5552         case RTL_GIGA_MAC_VER_35:
5553         case RTL_GIGA_MAC_VER_36:
5554                 rtl_hw_start_8168f_1(tp);
5555                 break;
5556
5557         case RTL_GIGA_MAC_VER_38:
5558                 rtl_hw_start_8411(tp);
5559                 break;
5560
5561         case RTL_GIGA_MAC_VER_40:
5562         case RTL_GIGA_MAC_VER_41:
5563                 rtl_hw_start_8168g_1(tp);
5564                 break;
5565         case RTL_GIGA_MAC_VER_42:
5566                 rtl_hw_start_8168g_2(tp);
5567                 break;
5568
5569         case RTL_GIGA_MAC_VER_44:
5570                 rtl_hw_start_8411_2(tp);
5571                 break;
5572
5573         case RTL_GIGA_MAC_VER_45:
5574         case RTL_GIGA_MAC_VER_46:
5575                 rtl_hw_start_8168h_1(tp);
5576                 break;
5577
5578         case RTL_GIGA_MAC_VER_49:
5579                 rtl_hw_start_8168ep_1(tp);
5580                 break;
5581
5582         case RTL_GIGA_MAC_VER_50:
5583                 rtl_hw_start_8168ep_2(tp);
5584                 break;
5585
5586         case RTL_GIGA_MAC_VER_51:
5587                 rtl_hw_start_8168ep_3(tp);
5588                 break;
5589
5590         default:
5591                 netif_err(tp, drv, tp->dev,
5592                           "unknown chipset (mac_version = %d)\n",
5593                           tp->mac_version);
5594                 break;
5595         }
5596 }
5597
5598 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5599 {
5600         static const struct ephy_info e_info_8102e_1[] = {
5601                 { 0x01, 0, 0x6e65 },
5602                 { 0x02, 0, 0x091f },
5603                 { 0x03, 0, 0xc2f9 },
5604                 { 0x06, 0, 0xafb5 },
5605                 { 0x07, 0, 0x0e00 },
5606                 { 0x19, 0, 0xec80 },
5607                 { 0x01, 0, 0x2e65 },
5608                 { 0x01, 0, 0x6e65 }
5609         };
5610         u8 cfg1;
5611
5612         rtl_set_def_aspm_entry_latency(tp);
5613
5614         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5615
5616         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5617
5618         RTL_W8(tp, Config1,
5619                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5620         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5621
5622         cfg1 = RTL_R8(tp, Config1);
5623         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5624                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5625
5626         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5627 }
5628
5629 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5630 {
5631         rtl_set_def_aspm_entry_latency(tp);
5632
5633         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5634
5635         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5636         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5637 }
5638
5639 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5640 {
5641         rtl_hw_start_8102e_2(tp);
5642
5643         rtl_ephy_write(tp, 0x03, 0xc2f9);
5644 }
5645
5646 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5647 {
5648         static const struct ephy_info e_info_8105e_1[] = {
5649                 { 0x07, 0, 0x4000 },
5650                 { 0x19, 0, 0x0200 },
5651                 { 0x19, 0, 0x0020 },
5652                 { 0x1e, 0, 0x2000 },
5653                 { 0x03, 0, 0x0001 },
5654                 { 0x19, 0, 0x0100 },
5655                 { 0x19, 0, 0x0004 },
5656                 { 0x0a, 0, 0x0020 }
5657         };
5658
5659         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5660         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5661
5662         /* Disable Early Tally Counter */
5663         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5664
5665         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5666         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5667
5668         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5669
5670         rtl_pcie_state_l2l3_enable(tp, false);
5671 }
5672
5673 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5674 {
5675         rtl_hw_start_8105e_1(tp);
5676         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5677 }
5678
5679 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5680 {
5681         static const struct ephy_info e_info_8402[] = {
5682                 { 0x19, 0xffff, 0xff64 },
5683                 { 0x1e, 0, 0x4000 }
5684         };
5685
5686         rtl_set_def_aspm_entry_latency(tp);
5687
5688         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5689         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5690
5691         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5692         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5693
5694         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5695
5696         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5697
5698         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5699         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5700         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5701         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5702         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5703         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5704         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5705
5706         rtl_pcie_state_l2l3_enable(tp, false);
5707 }
5708
5709 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5710 {
5711         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5712         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5713
5714         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5715         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5716         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5717
5718         rtl_pcie_state_l2l3_enable(tp, false);
5719 }
5720
5721 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5722 {
5723         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5724                 tp->event_slow &= ~RxFIFOOver;
5725
5726         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5727             tp->mac_version == RTL_GIGA_MAC_VER_16)
5728                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5729                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5730
5731         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5732
5733         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5734         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5735
5736         switch (tp->mac_version) {
5737         case RTL_GIGA_MAC_VER_07:
5738                 rtl_hw_start_8102e_1(tp);
5739                 break;
5740
5741         case RTL_GIGA_MAC_VER_08:
5742                 rtl_hw_start_8102e_3(tp);
5743                 break;
5744
5745         case RTL_GIGA_MAC_VER_09:
5746                 rtl_hw_start_8102e_2(tp);
5747                 break;
5748
5749         case RTL_GIGA_MAC_VER_29:
5750                 rtl_hw_start_8105e_1(tp);
5751                 break;
5752         case RTL_GIGA_MAC_VER_30:
5753                 rtl_hw_start_8105e_2(tp);
5754                 break;
5755
5756         case RTL_GIGA_MAC_VER_37:
5757                 rtl_hw_start_8402(tp);
5758                 break;
5759
5760         case RTL_GIGA_MAC_VER_39:
5761                 rtl_hw_start_8106(tp);
5762                 break;
5763         case RTL_GIGA_MAC_VER_43:
5764                 rtl_hw_start_8168g_2(tp);
5765                 break;
5766         case RTL_GIGA_MAC_VER_47:
5767         case RTL_GIGA_MAC_VER_48:
5768                 rtl_hw_start_8168h_1(tp);
5769                 break;
5770         }
5771
5772         RTL_W16(tp, IntrMitigate, 0x0000);
5773 }
5774
5775 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5776 {
5777         struct rtl8169_private *tp = netdev_priv(dev);
5778
5779         if (new_mtu > ETH_DATA_LEN)
5780                 rtl_hw_jumbo_enable(tp);
5781         else
5782                 rtl_hw_jumbo_disable(tp);
5783
5784         dev->mtu = new_mtu;
5785         netdev_update_features(dev);
5786
5787         return 0;
5788 }
5789
5790 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5791 {
5792         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5793         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5794 }
5795
5796 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5797                                      void **data_buff, struct RxDesc *desc)
5798 {
5799         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5800                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5801
5802         kfree(*data_buff);
5803         *data_buff = NULL;
5804         rtl8169_make_unusable_by_asic(desc);
5805 }
5806
5807 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5808 {
5809         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5810
5811         /* Force memory writes to complete before releasing descriptor */
5812         dma_wmb();
5813
5814         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5815 }
5816
5817 static inline void *rtl8169_align(void *data)
5818 {
5819         return (void *)ALIGN((long)data, 16);
5820 }
5821
5822 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5823                                              struct RxDesc *desc)
5824 {
5825         void *data;
5826         dma_addr_t mapping;
5827         struct device *d = tp_to_dev(tp);
5828         int node = dev_to_node(d);
5829
5830         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5831         if (!data)
5832                 return NULL;
5833
5834         if (rtl8169_align(data) != data) {
5835                 kfree(data);
5836                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5837                 if (!data)
5838                         return NULL;
5839         }
5840
5841         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5842                                  DMA_FROM_DEVICE);
5843         if (unlikely(dma_mapping_error(d, mapping))) {
5844                 if (net_ratelimit())
5845                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5846                 goto err_out;
5847         }
5848
5849         desc->addr = cpu_to_le64(mapping);
5850         rtl8169_mark_to_asic(desc);
5851         return data;
5852
5853 err_out:
5854         kfree(data);
5855         return NULL;
5856 }
5857
5858 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5859 {
5860         unsigned int i;
5861
5862         for (i = 0; i < NUM_RX_DESC; i++) {
5863                 if (tp->Rx_databuff[i]) {
5864                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5865                                             tp->RxDescArray + i);
5866                 }
5867         }
5868 }
5869
5870 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5871 {
5872         desc->opts1 |= cpu_to_le32(RingEnd);
5873 }
5874
5875 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5876 {
5877         unsigned int i;
5878
5879         for (i = 0; i < NUM_RX_DESC; i++) {
5880                 void *data;
5881
5882                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5883                 if (!data) {
5884                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5885                         goto err_out;
5886                 }
5887                 tp->Rx_databuff[i] = data;
5888         }
5889
5890         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5891         return 0;
5892
5893 err_out:
5894         rtl8169_rx_clear(tp);
5895         return -ENOMEM;
5896 }
5897
5898 static int rtl8169_init_ring(struct rtl8169_private *tp)
5899 {
5900         rtl8169_init_ring_indexes(tp);
5901
5902         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5903         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5904
5905         return rtl8169_rx_fill(tp);
5906 }
5907
5908 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5909                                  struct TxDesc *desc)
5910 {
5911         unsigned int len = tx_skb->len;
5912
5913         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5914
5915         desc->opts1 = 0x00;
5916         desc->opts2 = 0x00;
5917         desc->addr = 0x00;
5918         tx_skb->len = 0;
5919 }
5920
5921 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5922                                    unsigned int n)
5923 {
5924         unsigned int i;
5925
5926         for (i = 0; i < n; i++) {
5927                 unsigned int entry = (start + i) % NUM_TX_DESC;
5928                 struct ring_info *tx_skb = tp->tx_skb + entry;
5929                 unsigned int len = tx_skb->len;
5930
5931                 if (len) {
5932                         struct sk_buff *skb = tx_skb->skb;
5933
5934                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5935                                              tp->TxDescArray + entry);
5936                         if (skb) {
5937                                 dev_consume_skb_any(skb);
5938                                 tx_skb->skb = NULL;
5939                         }
5940                 }
5941         }
5942 }
5943
5944 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5945 {
5946         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5947         tp->cur_tx = tp->dirty_tx = 0;
5948 }
5949
5950 static void rtl_reset_work(struct rtl8169_private *tp)
5951 {
5952         struct net_device *dev = tp->dev;
5953         int i;
5954
5955         napi_disable(&tp->napi);
5956         netif_stop_queue(dev);
5957         synchronize_sched();
5958
5959         rtl8169_hw_reset(tp);
5960
5961         for (i = 0; i < NUM_RX_DESC; i++)
5962                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5963
5964         rtl8169_tx_clear(tp);
5965         rtl8169_init_ring_indexes(tp);
5966
5967         napi_enable(&tp->napi);
5968         rtl_hw_start(tp);
5969         netif_wake_queue(dev);
5970 }
5971
5972 static void rtl8169_tx_timeout(struct net_device *dev)
5973 {
5974         struct rtl8169_private *tp = netdev_priv(dev);
5975
5976         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5977 }
5978
5979 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5980                               u32 *opts)
5981 {
5982         struct skb_shared_info *info = skb_shinfo(skb);
5983         unsigned int cur_frag, entry;
5984         struct TxDesc *uninitialized_var(txd);
5985         struct device *d = tp_to_dev(tp);
5986
5987         entry = tp->cur_tx;
5988         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5989                 const skb_frag_t *frag = info->frags + cur_frag;
5990                 dma_addr_t mapping;
5991                 u32 status, len;
5992                 void *addr;
5993
5994                 entry = (entry + 1) % NUM_TX_DESC;
5995
5996                 txd = tp->TxDescArray + entry;
5997                 len = skb_frag_size(frag);
5998                 addr = skb_frag_address(frag);
5999                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6000                 if (unlikely(dma_mapping_error(d, mapping))) {
6001                         if (net_ratelimit())
6002                                 netif_err(tp, drv, tp->dev,
6003                                           "Failed to map TX fragments DMA!\n");
6004                         goto err_out;
6005                 }
6006
6007                 /* Anti gcc 2.95.3 bugware (sic) */
6008                 status = opts[0] | len |
6009                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6010
6011                 txd->opts1 = cpu_to_le32(status);
6012                 txd->opts2 = cpu_to_le32(opts[1]);
6013                 txd->addr = cpu_to_le64(mapping);
6014
6015                 tp->tx_skb[entry].len = len;
6016         }
6017
6018         if (cur_frag) {
6019                 tp->tx_skb[entry].skb = skb;
6020                 txd->opts1 |= cpu_to_le32(LastFrag);
6021         }
6022
6023         return cur_frag;
6024
6025 err_out:
6026         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6027         return -EIO;
6028 }
6029
6030 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6031 {
6032         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6033 }
6034
6035 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6036                                       struct net_device *dev);
6037 /* r8169_csum_workaround()
6038  * The hw limites the value the transport offset. When the offset is out of the
6039  * range, calculate the checksum by sw.
6040  */
6041 static void r8169_csum_workaround(struct rtl8169_private *tp,
6042                                   struct sk_buff *skb)
6043 {
6044         if (skb_shinfo(skb)->gso_size) {
6045                 netdev_features_t features = tp->dev->features;
6046                 struct sk_buff *segs, *nskb;
6047
6048                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6049                 segs = skb_gso_segment(skb, features);
6050                 if (IS_ERR(segs) || !segs)
6051                         goto drop;
6052
6053                 do {
6054                         nskb = segs;
6055                         segs = segs->next;
6056                         nskb->next = NULL;
6057                         rtl8169_start_xmit(nskb, tp->dev);
6058                 } while (segs);
6059
6060                 dev_consume_skb_any(skb);
6061         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6062                 if (skb_checksum_help(skb) < 0)
6063                         goto drop;
6064
6065                 rtl8169_start_xmit(skb, tp->dev);
6066         } else {
6067                 struct net_device_stats *stats;
6068
6069 drop:
6070                 stats = &tp->dev->stats;
6071                 stats->tx_dropped++;
6072                 dev_kfree_skb_any(skb);
6073         }
6074 }
6075
6076 /* msdn_giant_send_check()
6077  * According to the document of microsoft, the TCP Pseudo Header excludes the
6078  * packet length for IPv6 TCP large packets.
6079  */
6080 static int msdn_giant_send_check(struct sk_buff *skb)
6081 {
6082         const struct ipv6hdr *ipv6h;
6083         struct tcphdr *th;
6084         int ret;
6085
6086         ret = skb_cow_head(skb, 0);
6087         if (ret)
6088                 return ret;
6089
6090         ipv6h = ipv6_hdr(skb);
6091         th = tcp_hdr(skb);
6092
6093         th->check = 0;
6094         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6095
6096         return ret;
6097 }
6098
6099 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6100                                 struct sk_buff *skb, u32 *opts)
6101 {
6102         u32 mss = skb_shinfo(skb)->gso_size;
6103
6104         if (mss) {
6105                 opts[0] |= TD_LSO;
6106                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6107         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6108                 const struct iphdr *ip = ip_hdr(skb);
6109
6110                 if (ip->protocol == IPPROTO_TCP)
6111                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6112                 else if (ip->protocol == IPPROTO_UDP)
6113                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6114                 else
6115                         WARN_ON_ONCE(1);
6116         }
6117
6118         return true;
6119 }
6120
6121 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6122                                 struct sk_buff *skb, u32 *opts)
6123 {
6124         u32 transport_offset = (u32)skb_transport_offset(skb);
6125         u32 mss = skb_shinfo(skb)->gso_size;
6126
6127         if (mss) {
6128                 if (transport_offset > GTTCPHO_MAX) {
6129                         netif_warn(tp, tx_err, tp->dev,
6130                                    "Invalid transport offset 0x%x for TSO\n",
6131                                    transport_offset);
6132                         return false;
6133                 }
6134
6135                 switch (vlan_get_protocol(skb)) {
6136                 case htons(ETH_P_IP):
6137                         opts[0] |= TD1_GTSENV4;
6138                         break;
6139
6140                 case htons(ETH_P_IPV6):
6141                         if (msdn_giant_send_check(skb))
6142                                 return false;
6143
6144                         opts[0] |= TD1_GTSENV6;
6145                         break;
6146
6147                 default:
6148                         WARN_ON_ONCE(1);
6149                         break;
6150                 }
6151
6152                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6153                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6154         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6155                 u8 ip_protocol;
6156
6157                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6158                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6159
6160                 if (transport_offset > TCPHO_MAX) {
6161                         netif_warn(tp, tx_err, tp->dev,
6162                                    "Invalid transport offset 0x%x\n",
6163                                    transport_offset);
6164                         return false;
6165                 }
6166
6167                 switch (vlan_get_protocol(skb)) {
6168                 case htons(ETH_P_IP):
6169                         opts[1] |= TD1_IPv4_CS;
6170                         ip_protocol = ip_hdr(skb)->protocol;
6171                         break;
6172
6173                 case htons(ETH_P_IPV6):
6174                         opts[1] |= TD1_IPv6_CS;
6175                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6176                         break;
6177
6178                 default:
6179                         ip_protocol = IPPROTO_RAW;
6180                         break;
6181                 }
6182
6183                 if (ip_protocol == IPPROTO_TCP)
6184                         opts[1] |= TD1_TCP_CS;
6185                 else if (ip_protocol == IPPROTO_UDP)
6186                         opts[1] |= TD1_UDP_CS;
6187                 else
6188                         WARN_ON_ONCE(1);
6189
6190                 opts[1] |= transport_offset << TCPHO_SHIFT;
6191         } else {
6192                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6193                         return !eth_skb_pad(skb);
6194         }
6195
6196         return true;
6197 }
6198
6199 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6200                                       struct net_device *dev)
6201 {
6202         struct rtl8169_private *tp = netdev_priv(dev);
6203         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6204         struct TxDesc *txd = tp->TxDescArray + entry;
6205         struct device *d = tp_to_dev(tp);
6206         dma_addr_t mapping;
6207         u32 status, len;
6208         u32 opts[2];
6209         int frags;
6210
6211         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6212                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6213                 goto err_stop_0;
6214         }
6215
6216         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6217                 goto err_stop_0;
6218
6219         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6220         opts[0] = DescOwn;
6221
6222         if (!tp->tso_csum(tp, skb, opts)) {
6223                 r8169_csum_workaround(tp, skb);
6224                 return NETDEV_TX_OK;
6225         }
6226
6227         len = skb_headlen(skb);
6228         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6229         if (unlikely(dma_mapping_error(d, mapping))) {
6230                 if (net_ratelimit())
6231                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6232                 goto err_dma_0;
6233         }
6234
6235         tp->tx_skb[entry].len = len;
6236         txd->addr = cpu_to_le64(mapping);
6237
6238         frags = rtl8169_xmit_frags(tp, skb, opts);
6239         if (frags < 0)
6240                 goto err_dma_1;
6241         else if (frags)
6242                 opts[0] |= FirstFrag;
6243         else {
6244                 opts[0] |= FirstFrag | LastFrag;
6245                 tp->tx_skb[entry].skb = skb;
6246         }
6247
6248         txd->opts2 = cpu_to_le32(opts[1]);
6249
6250         skb_tx_timestamp(skb);
6251
6252         /* Force memory writes to complete before releasing descriptor */
6253         dma_wmb();
6254
6255         /* Anti gcc 2.95.3 bugware (sic) */
6256         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6257         txd->opts1 = cpu_to_le32(status);
6258
6259         /* Force all memory writes to complete before notifying device */
6260         wmb();
6261
6262         tp->cur_tx += frags + 1;
6263
6264         RTL_W8(tp, TxPoll, NPQ);
6265
6266         mmiowb();
6267
6268         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6269                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6270                  * not miss a ring update when it notices a stopped queue.
6271                  */
6272                 smp_wmb();
6273                 netif_stop_queue(dev);
6274                 /* Sync with rtl_tx:
6275                  * - publish queue status and cur_tx ring index (write barrier)
6276                  * - refresh dirty_tx ring index (read barrier).
6277                  * May the current thread have a pessimistic view of the ring
6278                  * status and forget to wake up queue, a racing rtl_tx thread
6279                  * can't.
6280                  */
6281                 smp_mb();
6282                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6283                         netif_wake_queue(dev);
6284         }
6285
6286         return NETDEV_TX_OK;
6287
6288 err_dma_1:
6289         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6290 err_dma_0:
6291         dev_kfree_skb_any(skb);
6292         dev->stats.tx_dropped++;
6293         return NETDEV_TX_OK;
6294
6295 err_stop_0:
6296         netif_stop_queue(dev);
6297         dev->stats.tx_dropped++;
6298         return NETDEV_TX_BUSY;
6299 }
6300
6301 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6302 {
6303         struct rtl8169_private *tp = netdev_priv(dev);
6304         struct pci_dev *pdev = tp->pci_dev;
6305         u16 pci_status, pci_cmd;
6306
6307         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6308         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6309
6310         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6311                   pci_cmd, pci_status);
6312
6313         /*
6314          * The recovery sequence below admits a very elaborated explanation:
6315          * - it seems to work;
6316          * - I did not see what else could be done;
6317          * - it makes iop3xx happy.
6318          *
6319          * Feel free to adjust to your needs.
6320          */
6321         if (pdev->broken_parity_status)
6322                 pci_cmd &= ~PCI_COMMAND_PARITY;
6323         else
6324                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6325
6326         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6327
6328         pci_write_config_word(pdev, PCI_STATUS,
6329                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6330                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6331                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6332
6333         /* The infamous DAC f*ckup only happens at boot time */
6334         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6335                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6336                 tp->cp_cmd &= ~PCIDAC;
6337                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6338                 dev->features &= ~NETIF_F_HIGHDMA;
6339         }
6340
6341         rtl8169_hw_reset(tp);
6342
6343         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6344 }
6345
6346 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6347 {
6348         unsigned int dirty_tx, tx_left;
6349
6350         dirty_tx = tp->dirty_tx;
6351         smp_rmb();
6352         tx_left = tp->cur_tx - dirty_tx;
6353
6354         while (tx_left > 0) {
6355                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6356                 struct ring_info *tx_skb = tp->tx_skb + entry;
6357                 u32 status;
6358
6359                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6360                 if (status & DescOwn)
6361                         break;
6362
6363                 /* This barrier is needed to keep us from reading
6364                  * any other fields out of the Tx descriptor until
6365                  * we know the status of DescOwn
6366                  */
6367                 dma_rmb();
6368
6369                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6370                                      tp->TxDescArray + entry);
6371                 if (status & LastFrag) {
6372                         u64_stats_update_begin(&tp->tx_stats.syncp);
6373                         tp->tx_stats.packets++;
6374                         tp->tx_stats.bytes += tx_skb->skb->len;
6375                         u64_stats_update_end(&tp->tx_stats.syncp);
6376                         dev_consume_skb_any(tx_skb->skb);
6377                         tx_skb->skb = NULL;
6378                 }
6379                 dirty_tx++;
6380                 tx_left--;
6381         }
6382
6383         if (tp->dirty_tx != dirty_tx) {
6384                 tp->dirty_tx = dirty_tx;
6385                 /* Sync with rtl8169_start_xmit:
6386                  * - publish dirty_tx ring index (write barrier)
6387                  * - refresh cur_tx ring index and queue status (read barrier)
6388                  * May the current thread miss the stopped queue condition,
6389                  * a racing xmit thread can only have a right view of the
6390                  * ring status.
6391                  */
6392                 smp_mb();
6393                 if (netif_queue_stopped(dev) &&
6394                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6395                         netif_wake_queue(dev);
6396                 }
6397                 /*
6398                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6399                  * too close. Let's kick an extra TxPoll request when a burst
6400                  * of start_xmit activity is detected (if it is not detected,
6401                  * it is slow enough). -- FR
6402                  */
6403                 if (tp->cur_tx != dirty_tx)
6404                         RTL_W8(tp, TxPoll, NPQ);
6405         }
6406 }
6407
6408 static inline int rtl8169_fragmented_frame(u32 status)
6409 {
6410         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6411 }
6412
6413 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6414 {
6415         u32 status = opts1 & RxProtoMask;
6416
6417         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6418             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6419                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6420         else
6421                 skb_checksum_none_assert(skb);
6422 }
6423
6424 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6425                                            struct rtl8169_private *tp,
6426                                            int pkt_size,
6427                                            dma_addr_t addr)
6428 {
6429         struct sk_buff *skb;
6430         struct device *d = tp_to_dev(tp);
6431
6432         data = rtl8169_align(data);
6433         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6434         prefetch(data);
6435         skb = napi_alloc_skb(&tp->napi, pkt_size);
6436         if (skb)
6437                 skb_copy_to_linear_data(skb, data, pkt_size);
6438         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6439
6440         return skb;
6441 }
6442
6443 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6444 {
6445         unsigned int cur_rx, rx_left;
6446         unsigned int count;
6447
6448         cur_rx = tp->cur_rx;
6449
6450         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6451                 unsigned int entry = cur_rx % NUM_RX_DESC;
6452                 struct RxDesc *desc = tp->RxDescArray + entry;
6453                 u32 status;
6454
6455                 status = le32_to_cpu(desc->opts1);
6456                 if (status & DescOwn)
6457                         break;
6458
6459                 /* This barrier is needed to keep us from reading
6460                  * any other fields out of the Rx descriptor until
6461                  * we know the status of DescOwn
6462                  */
6463                 dma_rmb();
6464
6465                 if (unlikely(status & RxRES)) {
6466                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6467                                    status);
6468                         dev->stats.rx_errors++;
6469                         if (status & (RxRWT | RxRUNT))
6470                                 dev->stats.rx_length_errors++;
6471                         if (status & RxCRC)
6472                                 dev->stats.rx_crc_errors++;
6473                         /* RxFOVF is a reserved bit on later chip versions */
6474                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6475                             status & RxFOVF) {
6476                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6477                                 dev->stats.rx_fifo_errors++;
6478                         } else if (status & (RxRUNT | RxCRC) &&
6479                                    !(status & RxRWT) &&
6480                                    dev->features & NETIF_F_RXALL) {
6481                                 goto process_pkt;
6482                         }
6483                 } else {
6484                         struct sk_buff *skb;
6485                         dma_addr_t addr;
6486                         int pkt_size;
6487
6488 process_pkt:
6489                         addr = le64_to_cpu(desc->addr);
6490                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6491                                 pkt_size = (status & 0x00003fff) - 4;
6492                         else
6493                                 pkt_size = status & 0x00003fff;
6494
6495                         /*
6496                          * The driver does not support incoming fragmented
6497                          * frames. They are seen as a symptom of over-mtu
6498                          * sized frames.
6499                          */
6500                         if (unlikely(rtl8169_fragmented_frame(status))) {
6501                                 dev->stats.rx_dropped++;
6502                                 dev->stats.rx_length_errors++;
6503                                 goto release_descriptor;
6504                         }
6505
6506                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6507                                                   tp, pkt_size, addr);
6508                         if (!skb) {
6509                                 dev->stats.rx_dropped++;
6510                                 goto release_descriptor;
6511                         }
6512
6513                         rtl8169_rx_csum(skb, status);
6514                         skb_put(skb, pkt_size);
6515                         skb->protocol = eth_type_trans(skb, dev);
6516
6517                         rtl8169_rx_vlan_tag(desc, skb);
6518
6519                         if (skb->pkt_type == PACKET_MULTICAST)
6520                                 dev->stats.multicast++;
6521
6522                         napi_gro_receive(&tp->napi, skb);
6523
6524                         u64_stats_update_begin(&tp->rx_stats.syncp);
6525                         tp->rx_stats.packets++;
6526                         tp->rx_stats.bytes += pkt_size;
6527                         u64_stats_update_end(&tp->rx_stats.syncp);
6528                 }
6529 release_descriptor:
6530                 desc->opts2 = 0;
6531                 rtl8169_mark_to_asic(desc);
6532         }
6533
6534         count = cur_rx - tp->cur_rx;
6535         tp->cur_rx = cur_rx;
6536
6537         return count;
6538 }
6539
6540 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6541 {
6542         struct rtl8169_private *tp = dev_instance;
6543         int handled = 0;
6544         u16 status;
6545
6546         status = rtl_get_events(tp);
6547         if (status && status != 0xffff) {
6548                 status &= RTL_EVENT_NAPI | tp->event_slow;
6549                 if (status) {
6550                         handled = 1;
6551
6552                         rtl_irq_disable(tp);
6553                         napi_schedule_irqoff(&tp->napi);
6554                 }
6555         }
6556         return IRQ_RETVAL(handled);
6557 }
6558
6559 /*
6560  * Workqueue context.
6561  */
6562 static void rtl_slow_event_work(struct rtl8169_private *tp)
6563 {
6564         struct net_device *dev = tp->dev;
6565         u16 status;
6566
6567         status = rtl_get_events(tp) & tp->event_slow;
6568         rtl_ack_events(tp, status);
6569
6570         if (unlikely(status & RxFIFOOver)) {
6571                 switch (tp->mac_version) {
6572                 /* Work around for rx fifo overflow */
6573                 case RTL_GIGA_MAC_VER_11:
6574                         netif_stop_queue(dev);
6575                         /* XXX - Hack alert. See rtl_task(). */
6576                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6577                 default:
6578                         break;
6579                 }
6580         }
6581
6582         if (unlikely(status & SYSErr))
6583                 rtl8169_pcierr_interrupt(dev);
6584
6585         if (status & LinkChg)
6586                 phy_mac_interrupt(dev->phydev);
6587
6588         rtl_irq_enable_all(tp);
6589 }
6590
6591 static void rtl_task(struct work_struct *work)
6592 {
6593         static const struct {
6594                 int bitnr;
6595                 void (*action)(struct rtl8169_private *);
6596         } rtl_work[] = {
6597                 /* XXX - keep rtl_slow_event_work() as first element. */
6598                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6599                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6600         };
6601         struct rtl8169_private *tp =
6602                 container_of(work, struct rtl8169_private, wk.work);
6603         struct net_device *dev = tp->dev;
6604         int i;
6605
6606         rtl_lock_work(tp);
6607
6608         if (!netif_running(dev) ||
6609             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6610                 goto out_unlock;
6611
6612         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6613                 bool pending;
6614
6615                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6616                 if (pending)
6617                         rtl_work[i].action(tp);
6618         }
6619
6620 out_unlock:
6621         rtl_unlock_work(tp);
6622 }
6623
6624 static int rtl8169_poll(struct napi_struct *napi, int budget)
6625 {
6626         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6627         struct net_device *dev = tp->dev;
6628         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6629         int work_done= 0;
6630         u16 status;
6631
6632         status = rtl_get_events(tp);
6633         rtl_ack_events(tp, status & ~tp->event_slow);
6634
6635         if (status & RTL_EVENT_NAPI_RX)
6636                 work_done = rtl_rx(dev, tp, (u32) budget);
6637
6638         if (status & RTL_EVENT_NAPI_TX)
6639                 rtl_tx(dev, tp);
6640
6641         if (status & tp->event_slow) {
6642                 enable_mask &= ~tp->event_slow;
6643
6644                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6645         }
6646
6647         if (work_done < budget) {
6648                 napi_complete_done(napi, work_done);
6649
6650                 rtl_irq_enable(tp, enable_mask);
6651                 mmiowb();
6652         }
6653
6654         return work_done;
6655 }
6656
6657 static void rtl8169_rx_missed(struct net_device *dev)
6658 {
6659         struct rtl8169_private *tp = netdev_priv(dev);
6660
6661         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6662                 return;
6663
6664         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6665         RTL_W32(tp, RxMissed, 0);
6666 }
6667
6668 static void r8169_phylink_handler(struct net_device *ndev)
6669 {
6670         struct rtl8169_private *tp = netdev_priv(ndev);
6671
6672         if (netif_carrier_ok(ndev)) {
6673                 rtl_link_chg_patch(tp);
6674                 pm_request_resume(&tp->pci_dev->dev);
6675         } else {
6676                 pm_runtime_idle(&tp->pci_dev->dev);
6677         }
6678
6679         if (net_ratelimit())
6680                 phy_print_status(ndev->phydev);
6681 }
6682
6683 static int r8169_phy_connect(struct rtl8169_private *tp)
6684 {
6685         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6686         phy_interface_t phy_mode;
6687         int ret;
6688
6689         phy_mode = tp->mii.supports_gmii ? PHY_INTERFACE_MODE_GMII :
6690                    PHY_INTERFACE_MODE_MII;
6691
6692         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6693                                  phy_mode);
6694         if (ret)
6695                 return ret;
6696
6697         if (!tp->mii.supports_gmii)
6698                 phy_set_max_speed(phydev, SPEED_100);
6699
6700         /* Ensure to advertise everything, incl. pause */
6701         phydev->advertising = phydev->supported;
6702
6703         phy_attached_info(phydev);
6704
6705         return 0;
6706 }
6707
6708 static void rtl8169_down(struct net_device *dev)
6709 {
6710         struct rtl8169_private *tp = netdev_priv(dev);
6711
6712         phy_stop(dev->phydev);
6713
6714         napi_disable(&tp->napi);
6715         netif_stop_queue(dev);
6716
6717         rtl8169_hw_reset(tp);
6718         /*
6719          * At this point device interrupts can not be enabled in any function,
6720          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6721          * and napi is disabled (rtl8169_poll).
6722          */
6723         rtl8169_rx_missed(dev);
6724
6725         /* Give a racing hard_start_xmit a few cycles to complete. */
6726         synchronize_sched();
6727
6728         rtl8169_tx_clear(tp);
6729
6730         rtl8169_rx_clear(tp);
6731
6732         rtl_pll_power_down(tp);
6733 }
6734
6735 static int rtl8169_close(struct net_device *dev)
6736 {
6737         struct rtl8169_private *tp = netdev_priv(dev);
6738         struct pci_dev *pdev = tp->pci_dev;
6739
6740         pm_runtime_get_sync(&pdev->dev);
6741
6742         /* Update counters before going down */
6743         rtl8169_update_counters(tp);
6744
6745         rtl_lock_work(tp);
6746         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6747
6748         rtl8169_down(dev);
6749         rtl_unlock_work(tp);
6750
6751         cancel_work_sync(&tp->wk.work);
6752
6753         phy_disconnect(dev->phydev);
6754
6755         pci_free_irq(pdev, 0, tp);
6756
6757         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6758                           tp->RxPhyAddr);
6759         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6760                           tp->TxPhyAddr);
6761         tp->TxDescArray = NULL;
6762         tp->RxDescArray = NULL;
6763
6764         pm_runtime_put_sync(&pdev->dev);
6765
6766         return 0;
6767 }
6768
6769 #ifdef CONFIG_NET_POLL_CONTROLLER
6770 static void rtl8169_netpoll(struct net_device *dev)
6771 {
6772         struct rtl8169_private *tp = netdev_priv(dev);
6773
6774         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6775 }
6776 #endif
6777
6778 static int rtl_open(struct net_device *dev)
6779 {
6780         struct rtl8169_private *tp = netdev_priv(dev);
6781         struct pci_dev *pdev = tp->pci_dev;
6782         int retval = -ENOMEM;
6783
6784         pm_runtime_get_sync(&pdev->dev);
6785
6786         /*
6787          * Rx and Tx descriptors needs 256 bytes alignment.
6788          * dma_alloc_coherent provides more.
6789          */
6790         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6791                                              &tp->TxPhyAddr, GFP_KERNEL);
6792         if (!tp->TxDescArray)
6793                 goto err_pm_runtime_put;
6794
6795         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6796                                              &tp->RxPhyAddr, GFP_KERNEL);
6797         if (!tp->RxDescArray)
6798                 goto err_free_tx_0;
6799
6800         retval = rtl8169_init_ring(tp);
6801         if (retval < 0)
6802                 goto err_free_rx_1;
6803
6804         INIT_WORK(&tp->wk.work, rtl_task);
6805
6806         smp_mb();
6807
6808         rtl_request_firmware(tp);
6809
6810         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6811                                  dev->name);
6812         if (retval < 0)
6813                 goto err_release_fw_2;
6814
6815         retval = r8169_phy_connect(tp);
6816         if (retval)
6817                 goto err_free_irq;
6818
6819         rtl_lock_work(tp);
6820
6821         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6822
6823         napi_enable(&tp->napi);
6824
6825         rtl8169_init_phy(dev, tp);
6826
6827         rtl_pll_power_up(tp);
6828
6829         rtl_hw_start(tp);
6830
6831         if (!rtl8169_init_counter_offsets(tp))
6832                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6833
6834         phy_start(dev->phydev);
6835         netif_start_queue(dev);
6836
6837         rtl_unlock_work(tp);
6838
6839         pm_runtime_put_sync(&pdev->dev);
6840 out:
6841         return retval;
6842
6843 err_free_irq:
6844         pci_free_irq(pdev, 0, tp);
6845 err_release_fw_2:
6846         rtl_release_firmware(tp);
6847         rtl8169_rx_clear(tp);
6848 err_free_rx_1:
6849         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6850                           tp->RxPhyAddr);
6851         tp->RxDescArray = NULL;
6852 err_free_tx_0:
6853         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6854                           tp->TxPhyAddr);
6855         tp->TxDescArray = NULL;
6856 err_pm_runtime_put:
6857         pm_runtime_put_noidle(&pdev->dev);
6858         goto out;
6859 }
6860
6861 static void
6862 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6863 {
6864         struct rtl8169_private *tp = netdev_priv(dev);
6865         struct pci_dev *pdev = tp->pci_dev;
6866         struct rtl8169_counters *counters = tp->counters;
6867         unsigned int start;
6868
6869         pm_runtime_get_noresume(&pdev->dev);
6870
6871         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6872                 rtl8169_rx_missed(dev);
6873
6874         do {
6875                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6876                 stats->rx_packets = tp->rx_stats.packets;
6877                 stats->rx_bytes = tp->rx_stats.bytes;
6878         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6879
6880         do {
6881                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6882                 stats->tx_packets = tp->tx_stats.packets;
6883                 stats->tx_bytes = tp->tx_stats.bytes;
6884         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6885
6886         stats->rx_dropped       = dev->stats.rx_dropped;
6887         stats->tx_dropped       = dev->stats.tx_dropped;
6888         stats->rx_length_errors = dev->stats.rx_length_errors;
6889         stats->rx_errors        = dev->stats.rx_errors;
6890         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6891         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6892         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6893         stats->multicast        = dev->stats.multicast;
6894
6895         /*
6896          * Fetch additonal counter values missing in stats collected by driver
6897          * from tally counters.
6898          */
6899         if (pm_runtime_active(&pdev->dev))
6900                 rtl8169_update_counters(tp);
6901
6902         /*
6903          * Subtract values fetched during initalization.
6904          * See rtl8169_init_counter_offsets for a description why we do that.
6905          */
6906         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6907                 le64_to_cpu(tp->tc_offset.tx_errors);
6908         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6909                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6910         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6911                 le16_to_cpu(tp->tc_offset.tx_aborted);
6912
6913         pm_runtime_put_noidle(&pdev->dev);
6914 }
6915
6916 static void rtl8169_net_suspend(struct net_device *dev)
6917 {
6918         struct rtl8169_private *tp = netdev_priv(dev);
6919
6920         if (!netif_running(dev))
6921                 return;
6922
6923         phy_stop(dev->phydev);
6924         netif_device_detach(dev);
6925         netif_stop_queue(dev);
6926
6927         rtl_lock_work(tp);
6928         napi_disable(&tp->napi);
6929         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6930         rtl_unlock_work(tp);
6931
6932         rtl_pll_power_down(tp);
6933 }
6934
6935 #ifdef CONFIG_PM
6936
6937 static int rtl8169_suspend(struct device *device)
6938 {
6939         struct pci_dev *pdev = to_pci_dev(device);
6940         struct net_device *dev = pci_get_drvdata(pdev);
6941
6942         rtl8169_net_suspend(dev);
6943
6944         return 0;
6945 }
6946
6947 static void __rtl8169_resume(struct net_device *dev)
6948 {
6949         struct rtl8169_private *tp = netdev_priv(dev);
6950
6951         netif_device_attach(dev);
6952
6953         rtl_pll_power_up(tp);
6954         rtl8169_init_phy(dev, tp);
6955
6956         phy_start(tp->dev->phydev);
6957
6958         rtl_lock_work(tp);
6959         napi_enable(&tp->napi);
6960         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6961         rtl_unlock_work(tp);
6962
6963         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6964 }
6965
6966 static int rtl8169_resume(struct device *device)
6967 {
6968         struct pci_dev *pdev = to_pci_dev(device);
6969         struct net_device *dev = pci_get_drvdata(pdev);
6970
6971         if (netif_running(dev))
6972                 __rtl8169_resume(dev);
6973
6974         return 0;
6975 }
6976
6977 static int rtl8169_runtime_suspend(struct device *device)
6978 {
6979         struct pci_dev *pdev = to_pci_dev(device);
6980         struct net_device *dev = pci_get_drvdata(pdev);
6981         struct rtl8169_private *tp = netdev_priv(dev);
6982
6983         if (!tp->TxDescArray) {
6984                 rtl_pll_power_down(tp);
6985                 return 0;
6986         }
6987
6988         rtl_lock_work(tp);
6989         __rtl8169_set_wol(tp, WAKE_ANY);
6990         rtl_unlock_work(tp);
6991
6992         rtl8169_net_suspend(dev);
6993
6994         /* Update counters before going runtime suspend */
6995         rtl8169_rx_missed(dev);
6996         rtl8169_update_counters(tp);
6997
6998         return 0;
6999 }
7000
7001 static int rtl8169_runtime_resume(struct device *device)
7002 {
7003         struct pci_dev *pdev = to_pci_dev(device);
7004         struct net_device *dev = pci_get_drvdata(pdev);
7005         struct rtl8169_private *tp = netdev_priv(dev);
7006         rtl_rar_set(tp, dev->dev_addr);
7007
7008         if (!tp->TxDescArray)
7009                 return 0;
7010
7011         rtl_lock_work(tp);
7012         __rtl8169_set_wol(tp, tp->saved_wolopts);
7013         rtl_unlock_work(tp);
7014
7015         __rtl8169_resume(dev);
7016
7017         return 0;
7018 }
7019
7020 static int rtl8169_runtime_idle(struct device *device)
7021 {
7022         struct pci_dev *pdev = to_pci_dev(device);
7023         struct net_device *dev = pci_get_drvdata(pdev);
7024
7025         if (!netif_running(dev) || !netif_carrier_ok(dev))
7026                 pm_schedule_suspend(device, 10000);
7027
7028         return -EBUSY;
7029 }
7030
7031 static const struct dev_pm_ops rtl8169_pm_ops = {
7032         .suspend                = rtl8169_suspend,
7033         .resume                 = rtl8169_resume,
7034         .freeze                 = rtl8169_suspend,
7035         .thaw                   = rtl8169_resume,
7036         .poweroff               = rtl8169_suspend,
7037         .restore                = rtl8169_resume,
7038         .runtime_suspend        = rtl8169_runtime_suspend,
7039         .runtime_resume         = rtl8169_runtime_resume,
7040         .runtime_idle           = rtl8169_runtime_idle,
7041 };
7042
7043 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7044
7045 #else /* !CONFIG_PM */
7046
7047 #define RTL8169_PM_OPS  NULL
7048
7049 #endif /* !CONFIG_PM */
7050
7051 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7052 {
7053         /* WoL fails with 8168b when the receiver is disabled. */
7054         switch (tp->mac_version) {
7055         case RTL_GIGA_MAC_VER_11:
7056         case RTL_GIGA_MAC_VER_12:
7057         case RTL_GIGA_MAC_VER_17:
7058                 pci_clear_master(tp->pci_dev);
7059
7060                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7061                 /* PCI commit */
7062                 RTL_R8(tp, ChipCmd);
7063                 break;
7064         default:
7065                 break;
7066         }
7067 }
7068
7069 static void rtl_shutdown(struct pci_dev *pdev)
7070 {
7071         struct net_device *dev = pci_get_drvdata(pdev);
7072         struct rtl8169_private *tp = netdev_priv(dev);
7073
7074         rtl8169_net_suspend(dev);
7075
7076         /* Restore original MAC address */
7077         rtl_rar_set(tp, dev->perm_addr);
7078
7079         rtl8169_hw_reset(tp);
7080
7081         if (system_state == SYSTEM_POWER_OFF) {
7082                 if (tp->saved_wolopts) {
7083                         rtl_wol_suspend_quirk(tp);
7084                         rtl_wol_shutdown_quirk(tp);
7085                 }
7086
7087                 pci_wake_from_d3(pdev, true);
7088                 pci_set_power_state(pdev, PCI_D3hot);
7089         }
7090 }
7091
7092 static void rtl_remove_one(struct pci_dev *pdev)
7093 {
7094         struct net_device *dev = pci_get_drvdata(pdev);
7095         struct rtl8169_private *tp = netdev_priv(dev);
7096
7097         if (r8168_check_dash(tp))
7098                 rtl8168_driver_stop(tp);
7099
7100         netif_napi_del(&tp->napi);
7101
7102         unregister_netdev(dev);
7103         mdiobus_unregister(tp->mii_bus);
7104
7105         rtl_release_firmware(tp);
7106
7107         if (pci_dev_run_wake(pdev))
7108                 pm_runtime_get_noresume(&pdev->dev);
7109
7110         /* restore original MAC address */
7111         rtl_rar_set(tp, dev->perm_addr);
7112 }
7113
7114 static const struct net_device_ops rtl_netdev_ops = {
7115         .ndo_open               = rtl_open,
7116         .ndo_stop               = rtl8169_close,
7117         .ndo_get_stats64        = rtl8169_get_stats64,
7118         .ndo_start_xmit         = rtl8169_start_xmit,
7119         .ndo_tx_timeout         = rtl8169_tx_timeout,
7120         .ndo_validate_addr      = eth_validate_addr,
7121         .ndo_change_mtu         = rtl8169_change_mtu,
7122         .ndo_fix_features       = rtl8169_fix_features,
7123         .ndo_set_features       = rtl8169_set_features,
7124         .ndo_set_mac_address    = rtl_set_mac_address,
7125         .ndo_do_ioctl           = rtl8169_ioctl,
7126         .ndo_set_rx_mode        = rtl_set_rx_mode,
7127 #ifdef CONFIG_NET_POLL_CONTROLLER
7128         .ndo_poll_controller    = rtl8169_netpoll,
7129 #endif
7130
7131 };
7132
7133 static const struct rtl_cfg_info {
7134         void (*hw_start)(struct rtl8169_private *tp);
7135         u16 event_slow;
7136         unsigned int has_gmii:1;
7137         const struct rtl_coalesce_info *coalesce_info;
7138         u8 default_ver;
7139 } rtl_cfg_infos [] = {
7140         [RTL_CFG_0] = {
7141                 .hw_start       = rtl_hw_start_8169,
7142                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7143                 .has_gmii       = 1,
7144                 .coalesce_info  = rtl_coalesce_info_8169,
7145                 .default_ver    = RTL_GIGA_MAC_VER_01,
7146         },
7147         [RTL_CFG_1] = {
7148                 .hw_start       = rtl_hw_start_8168,
7149                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7150                 .has_gmii       = 1,
7151                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7152                 .default_ver    = RTL_GIGA_MAC_VER_11,
7153         },
7154         [RTL_CFG_2] = {
7155                 .hw_start       = rtl_hw_start_8101,
7156                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7157                                   PCSTimeout,
7158                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7159                 .default_ver    = RTL_GIGA_MAC_VER_13,
7160         }
7161 };
7162
7163 static int rtl_alloc_irq(struct rtl8169_private *tp)
7164 {
7165         unsigned int flags;
7166
7167         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7168                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7169                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7170                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7171                 flags = PCI_IRQ_LEGACY;
7172         } else {
7173                 flags = PCI_IRQ_ALL_TYPES;
7174         }
7175
7176         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7177 }
7178
7179 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7180 {
7181         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7182 }
7183
7184 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7185 {
7186         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7187 }
7188
7189 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7190 {
7191         struct rtl8169_private *tp = mii_bus->priv;
7192
7193         if (phyaddr > 0)
7194                 return -ENODEV;
7195
7196         return rtl_readphy(tp, phyreg);
7197 }
7198
7199 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7200                                 int phyreg, u16 val)
7201 {
7202         struct rtl8169_private *tp = mii_bus->priv;
7203
7204         if (phyaddr > 0)
7205                 return -ENODEV;
7206
7207         rtl_writephy(tp, phyreg, val);
7208
7209         return 0;
7210 }
7211
7212 static int r8169_mdio_register(struct rtl8169_private *tp)
7213 {
7214         struct pci_dev *pdev = tp->pci_dev;
7215         struct phy_device *phydev;
7216         struct mii_bus *new_bus;
7217         int ret;
7218
7219         new_bus = devm_mdiobus_alloc(&pdev->dev);
7220         if (!new_bus)
7221                 return -ENOMEM;
7222
7223         new_bus->name = "r8169";
7224         new_bus->priv = tp;
7225         new_bus->parent = &pdev->dev;
7226         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7227         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7228                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7229
7230         new_bus->read = r8169_mdio_read_reg;
7231         new_bus->write = r8169_mdio_write_reg;
7232
7233         ret = mdiobus_register(new_bus);
7234         if (ret)
7235                 return ret;
7236
7237         phydev = mdiobus_get_phy(new_bus, 0);
7238         if (!phydev) {
7239                 mdiobus_unregister(new_bus);
7240                 return -ENODEV;
7241         }
7242
7243         /* PHY will be woken up in rtl_open() */
7244         phy_suspend(phydev);
7245
7246         tp->mii_bus = new_bus;
7247
7248         return 0;
7249 }
7250
7251 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7252 {
7253         u32 data;
7254
7255         tp->ocp_base = OCP_STD_PHY_BASE;
7256
7257         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7258
7259         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7260                 return;
7261
7262         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7263                 return;
7264
7265         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7266         msleep(1);
7267         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7268
7269         data = r8168_mac_ocp_read(tp, 0xe8de);
7270         data &= ~(1 << 14);
7271         r8168_mac_ocp_write(tp, 0xe8de, data);
7272
7273         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7274                 return;
7275
7276         data = r8168_mac_ocp_read(tp, 0xe8de);
7277         data |= (1 << 15);
7278         r8168_mac_ocp_write(tp, 0xe8de, data);
7279
7280         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7281                 return;
7282 }
7283
7284 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7285 {
7286         rtl8168ep_stop_cmac(tp);
7287         rtl_hw_init_8168g(tp);
7288 }
7289
7290 static void rtl_hw_initialize(struct rtl8169_private *tp)
7291 {
7292         switch (tp->mac_version) {
7293         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7294                 rtl_hw_init_8168g(tp);
7295                 break;
7296         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7297                 rtl_hw_init_8168ep(tp);
7298                 break;
7299         default:
7300                 break;
7301         }
7302 }
7303
7304 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7305 {
7306         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7307         struct rtl8169_private *tp;
7308         struct mii_if_info *mii;
7309         struct net_device *dev;
7310         int chipset, region, i;
7311         int rc;
7312
7313         if (netif_msg_drv(&debug)) {
7314                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7315                        MODULENAME, RTL8169_VERSION);
7316         }
7317
7318         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7319         if (!dev)
7320                 return -ENOMEM;
7321
7322         SET_NETDEV_DEV(dev, &pdev->dev);
7323         dev->netdev_ops = &rtl_netdev_ops;
7324         tp = netdev_priv(dev);
7325         tp->dev = dev;
7326         tp->pci_dev = pdev;
7327         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7328
7329         mii = &tp->mii;
7330         mii->dev = dev;
7331         mii->mdio_read = rtl_mdio_read;
7332         mii->mdio_write = rtl_mdio_write;
7333         mii->phy_id_mask = 0x1f;
7334         mii->reg_num_mask = 0x1f;
7335         mii->supports_gmii = cfg->has_gmii;
7336
7337         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7338         rc = pcim_enable_device(pdev);
7339         if (rc < 0) {
7340                 dev_err(&pdev->dev, "enable failure\n");
7341                 return rc;
7342         }
7343
7344         if (pcim_set_mwi(pdev) < 0)
7345                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7346
7347         /* use first MMIO region */
7348         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7349         if (region < 0) {
7350                 dev_err(&pdev->dev, "no MMIO resource found\n");
7351                 return -ENODEV;
7352         }
7353
7354         /* check for weird/broken PCI region reporting */
7355         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7356                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7357                 return -ENODEV;
7358         }
7359
7360         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7361         if (rc < 0) {
7362                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7363                 return rc;
7364         }
7365
7366         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7367
7368         if (!pci_is_pcie(pdev))
7369                 dev_info(&pdev->dev, "not PCI Express\n");
7370
7371         /* Identify chip attached to board */
7372         rtl8169_get_mac_version(tp, cfg->default_ver);
7373
7374         if (rtl_tbi_enabled(tp)) {
7375                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7376                 return -ENODEV;
7377         }
7378
7379         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7380
7381         if ((sizeof(dma_addr_t) > 4) &&
7382             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7383                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7384             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7385             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7386
7387                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7388                 if (!pci_is_pcie(pdev))
7389                         tp->cp_cmd |= PCIDAC;
7390                 dev->features |= NETIF_F_HIGHDMA;
7391         } else {
7392                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7393                 if (rc < 0) {
7394                         dev_err(&pdev->dev, "DMA configuration failed\n");
7395                         return rc;
7396                 }
7397         }
7398
7399         rtl_init_rxcfg(tp);
7400
7401         rtl_irq_disable(tp);
7402
7403         rtl_hw_initialize(tp);
7404
7405         rtl_hw_reset(tp);
7406
7407         rtl_ack_events(tp, 0xffff);
7408
7409         pci_set_master(pdev);
7410
7411         rtl_init_mdio_ops(tp);
7412         rtl_init_jumbo_ops(tp);
7413
7414         rtl8169_print_mac_version(tp);
7415
7416         chipset = tp->mac_version;
7417
7418         rc = rtl_alloc_irq(tp);
7419         if (rc < 0) {
7420                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7421                 return rc;
7422         }
7423
7424         /* override BIOS settings, use userspace tools to enable WOL */
7425         __rtl8169_set_wol(tp, 0);
7426
7427         mutex_init(&tp->wk.mutex);
7428         u64_stats_init(&tp->rx_stats.syncp);
7429         u64_stats_init(&tp->tx_stats.syncp);
7430
7431         /* Get MAC address */
7432         switch (tp->mac_version) {
7433                 u8 mac_addr[ETH_ALEN] __aligned(4);
7434         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7435         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7436                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7437                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7438
7439                 if (is_valid_ether_addr(mac_addr))
7440                         rtl_rar_set(tp, mac_addr);
7441                 break;
7442         default:
7443                 break;
7444         }
7445         for (i = 0; i < ETH_ALEN; i++)
7446                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7447
7448         dev->ethtool_ops = &rtl8169_ethtool_ops;
7449         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7450
7451         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7452
7453         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7454          * properly for all devices */
7455         dev->features |= NETIF_F_RXCSUM |
7456                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7457
7458         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7459                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7460                 NETIF_F_HW_VLAN_CTAG_RX;
7461         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7462                 NETIF_F_HIGHDMA;
7463
7464         tp->cp_cmd |= RxChkSum | RxVlan;
7465
7466         /*
7467          * Pretend we are using VLANs; This bypasses a nasty bug where
7468          * Interrupts stop flowing on high load on 8110SCd controllers.
7469          */
7470         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7471                 /* Disallow toggling */
7472                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7473
7474         switch (rtl_chip_infos[chipset].txd_version) {
7475         case RTL_TD_0:
7476                 tp->tso_csum = rtl8169_tso_csum_v1;
7477                 break;
7478         case RTL_TD_1:
7479                 tp->tso_csum = rtl8169_tso_csum_v2;
7480                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7481                 break;
7482         default:
7483                 WARN_ON_ONCE(1);
7484         }
7485
7486         dev->hw_features |= NETIF_F_RXALL;
7487         dev->hw_features |= NETIF_F_RXFCS;
7488
7489         /* MTU range: 60 - hw-specific max */
7490         dev->min_mtu = ETH_ZLEN;
7491         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7492
7493         tp->hw_start = cfg->hw_start;
7494         tp->event_slow = cfg->event_slow;
7495         tp->coalesce_info = cfg->coalesce_info;
7496
7497         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7498
7499         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7500                                             &tp->counters_phys_addr,
7501                                             GFP_KERNEL);
7502         if (!tp->counters)
7503                 return -ENOMEM;
7504
7505         pci_set_drvdata(pdev, dev);
7506
7507         rc = r8169_mdio_register(tp);
7508         if (rc)
7509                 return rc;
7510
7511         rc = register_netdev(dev);
7512         if (rc)
7513                 goto err_mdio_unregister;
7514
7515         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7516                    rtl_chip_infos[chipset].name, dev->dev_addr,
7517                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7518                    pci_irq_vector(pdev, 0));
7519         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7520                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7521                            "tx checksumming: %s]\n",
7522                            rtl_chip_infos[chipset].jumbo_max,
7523                           tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
7524         }
7525
7526         if (r8168_check_dash(tp))
7527                 rtl8168_driver_start(tp);
7528
7529         if (pci_dev_run_wake(pdev))
7530                 pm_runtime_put_sync(&pdev->dev);
7531
7532         return 0;
7533
7534 err_mdio_unregister:
7535         mdiobus_unregister(tp->mii_bus);
7536         return rc;
7537 }
7538
7539 static struct pci_driver rtl8169_pci_driver = {
7540         .name           = MODULENAME,
7541         .id_table       = rtl8169_pci_tbl,
7542         .probe          = rtl_init_one,
7543         .remove         = rtl_remove_one,
7544         .shutdown       = rtl_shutdown,
7545         .driver.pm      = RTL8169_PM_OPS,
7546 };
7547
7548 module_pci_driver(rtl8169_pci_driver);