drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/pci-aspm.h>
  32 #include <linux/ipv6.h>
  33 #include <net/ip6_checksum.h>
  34
  35 #define MODULENAME "r8169"
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  40 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  41 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  42 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  43 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  46 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  47 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  48 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  49 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  50 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  51 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  52 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  53 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  54 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  55 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  56
  57 #define R8169_MSG_DEFAULT \
  58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  59
  60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  61    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  62 static const int multicast_filter_limit = 32;
  63
  64 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  65 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  66
  67 #define R8169_REGS_SIZE         256
  68 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  69 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  70 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  71 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  72 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  73
  74 /* write/read MMIO register */
  75 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  76 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  77 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  78 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  79 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  80 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  81
  82 enum mac_version {
  83         RTL_GIGA_MAC_VER_01 = 0,
  84         RTL_GIGA_MAC_VER_02,
  85         RTL_GIGA_MAC_VER_03,
  86         RTL_GIGA_MAC_VER_04,
  87         RTL_GIGA_MAC_VER_05,
  88         RTL_GIGA_MAC_VER_06,
  89         RTL_GIGA_MAC_VER_07,
  90         RTL_GIGA_MAC_VER_08,
  91         RTL_GIGA_MAC_VER_09,
  92         RTL_GIGA_MAC_VER_10,
  93         RTL_GIGA_MAC_VER_11,
  94         RTL_GIGA_MAC_VER_12,
  95         RTL_GIGA_MAC_VER_13,
  96         RTL_GIGA_MAC_VER_14,
  97         RTL_GIGA_MAC_VER_15,
  98         RTL_GIGA_MAC_VER_16,
  99         RTL_GIGA_MAC_VER_17,
 100         RTL_GIGA_MAC_VER_18,
 101         RTL_GIGA_MAC_VER_19,
 102         RTL_GIGA_MAC_VER_20,
 103         RTL_GIGA_MAC_VER_21,
 104         RTL_GIGA_MAC_VER_22,
 105         RTL_GIGA_MAC_VER_23,
 106         RTL_GIGA_MAC_VER_24,
 107         RTL_GIGA_MAC_VER_25,
 108         RTL_GIGA_MAC_VER_26,
 109         RTL_GIGA_MAC_VER_27,
 110         RTL_GIGA_MAC_VER_28,
 111         RTL_GIGA_MAC_VER_29,
 112         RTL_GIGA_MAC_VER_30,
 113         RTL_GIGA_MAC_VER_31,
 114         RTL_GIGA_MAC_VER_32,
 115         RTL_GIGA_MAC_VER_33,
 116         RTL_GIGA_MAC_VER_34,
 117         RTL_GIGA_MAC_VER_35,
 118         RTL_GIGA_MAC_VER_36,
 119         RTL_GIGA_MAC_VER_37,
 120         RTL_GIGA_MAC_VER_38,
 121         RTL_GIGA_MAC_VER_39,
 122         RTL_GIGA_MAC_VER_40,
 123         RTL_GIGA_MAC_VER_41,
 124         RTL_GIGA_MAC_VER_42,
 125         RTL_GIGA_MAC_VER_43,
 126         RTL_GIGA_MAC_VER_44,
 127         RTL_GIGA_MAC_VER_45,
 128         RTL_GIGA_MAC_VER_46,
 129         RTL_GIGA_MAC_VER_47,
 130         RTL_GIGA_MAC_VER_48,
 131         RTL_GIGA_MAC_VER_49,
 132         RTL_GIGA_MAC_VER_50,
 133         RTL_GIGA_MAC_VER_51,
 134         RTL_GIGA_MAC_NONE   = 0xff,
 135 };
 136
 137 #define JUMBO_1K        ETH_DATA_LEN
 138 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 139 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 140 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 141 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 142
 143 static const struct {
 144         const char *name;
 145         const char *fw_name;
 146 } rtl_chip_infos[] = {
 147         /* PCI devices. */
 148         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxBOVF  = (1 << 24),
 409         RxFOVF  = (1 << 23),
 410         RxRWT   = (1 << 22),
 411         RxRES   = (1 << 21),
 412         RxRUNT  = (1 << 20),
 413         RxCRC   = (1 << 19),
 414
 415         /* ChipCmdBits */
 416         StopReq         = 0x80,
 417         CmdReset        = 0x10,
 418         CmdRxEnb        = 0x08,
 419         CmdTxEnb        = 0x04,
 420         RxBufEmpty      = 0x01,
 421
 422         /* TXPoll register p.5 */
 423         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 424         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 425         FSWInt          = 0x01,         /* Forced software interrupt */
 426
 427         /* Cfg9346Bits */
 428         Cfg9346_Lock    = 0x00,
 429         Cfg9346_Unlock  = 0xc0,
 430
 431         /* rx_mode_bits */
 432         AcceptErr       = 0x20,
 433         AcceptRunt      = 0x10,
 434         AcceptBroadcast = 0x08,
 435         AcceptMulticast = 0x04,
 436         AcceptMyPhys    = 0x02,
 437         AcceptAllPhys   = 0x01,
 438 #define RX_CONFIG_ACCEPT_MASK           0x3f
 439
 440         /* TxConfigBits */
 441         TxInterFrameGapShift = 24,
 442         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 443
 444         /* Config1 register p.24 */
 445         LEDS1           = (1 << 7),
 446         LEDS0           = (1 << 6),
 447         Speed_down      = (1 << 4),
 448         MEMMAP          = (1 << 3),
 449         IOMAP           = (1 << 2),
 450         VPD             = (1 << 1),
 451         PMEnable        = (1 << 0),     /* Power Management Enable */
 452
 453         /* Config2 register p. 25 */
 454         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 455         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 456         PCI_Clock_66MHz = 0x01,
 457         PCI_Clock_33MHz = 0x00,
 458
 459         /* Config3 register p.25 */
 460         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 461         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 462         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 463         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 464         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 465
 466         /* Config4 register */
 467         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 468
 469         /* Config5 register p.27 */
 470         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 471         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 472         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 473         Spi_en          = (1 << 3),
 474         LanWake         = (1 << 1),     /* LanWake enable/disable */
 475         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 476         ASPM_en         = (1 << 0),     /* ASPM enable */
 477
 478         /* CPlusCmd p.31 */
 479         EnableBist      = (1 << 15),    // 8168 8101
 480         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 481         Normal_mode     = (1 << 13),    // unused
 482         Force_half_dup  = (1 << 12),    // 8168 8101
 483         Force_rxflow_en = (1 << 11),    // 8168 8101
 484         Force_txflow_en = (1 << 10),    // 8168 8101
 485         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 486         ASF             = (1 << 8),     // 8168 8101
 487         PktCntrDisable  = (1 << 7),     // 8168 8101
 488         Mac_dbgo_sel    = 0x001c,       // 8168
 489         RxVlan          = (1 << 6),
 490         RxChkSum        = (1 << 5),
 491         PCIDAC          = (1 << 4),
 492         PCIMulRW        = (1 << 3),
 493 #define INTT_MASK       GENMASK(1, 0)
 494
 495         /* rtl8169_PHYstatus */
 496         TBI_Enable      = 0x80,
 497         TxFlowCtrl      = 0x40,
 498         RxFlowCtrl      = 0x20,
 499         _1000bpsF       = 0x10,
 500         _100bps         = 0x08,
 501         _10bps          = 0x04,
 502         LinkStatus      = 0x02,
 503         FullDup         = 0x01,
 504
 505         /* _TBICSRBit */
 506         TBILinkOK       = 0x02000000,
 507
 508         /* ResetCounterCommand */
 509         CounterReset    = 0x1,
 510
 511         /* DumpCounterCommand */
 512         CounterDump     = 0x8,
 513
 514         /* magic enable v2 */
 515         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 516 };
 517
 518 enum rtl_desc_bit {
 519         /* First doubleword. */
 520         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 521         RingEnd         = (1 << 30), /* End of descriptor ring */
 522         FirstFrag       = (1 << 29), /* First segment of a packet */
 523         LastFrag        = (1 << 28), /* Final segment of a packet */
 524 };
 525
 526 /* Generic case. */
 527 enum rtl_tx_desc_bit {
 528         /* First doubleword. */
 529         TD_LSO          = (1 << 27),            /* Large Send Offload */
 530 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 531
 532         /* Second doubleword. */
 533         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 534 };
 535
 536 /* 8169, 8168b and 810x except 8102e. */
 537 enum rtl_tx_desc_bit_0 {
 538         /* First doubleword. */
 539 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 540         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 541         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 542         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 543 };
 544
 545 /* 8102e, 8168c and beyond. */
 546 enum rtl_tx_desc_bit_1 {
 547         /* First doubleword. */
 548         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 549         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 550 #define GTTCPHO_SHIFT                   18
 551 #define GTTCPHO_MAX                     0x7fU
 552
 553         /* Second doubleword. */
 554 #define TCPHO_SHIFT                     18
 555 #define TCPHO_MAX                       0x3ffU
 556 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 557         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 558         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 559         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 560         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 561 };
 562
 563 enum rtl_rx_desc_bit {
 564         /* Rx private */
 565         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 566         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 567
 568 #define RxProtoUDP      (PID1)
 569 #define RxProtoTCP      (PID0)
 570 #define RxProtoIP       (PID1 | PID0)
 571 #define RxProtoMask     RxProtoIP
 572
 573         IPFail          = (1 << 16), /* IP checksum failed */
 574         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 575         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 576         RxVlanTag       = (1 << 16), /* VLAN tag available */
 577 };
 578
 579 #define RsvdMask        0x3fffc000
 580 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 581
 582 struct TxDesc {
 583         __le32 opts1;
 584         __le32 opts2;
 585         __le64 addr;
 586 };
 587
 588 struct RxDesc {
 589         __le32 opts1;
 590         __le32 opts2;
 591         __le64 addr;
 592 };
 593
 594 struct ring_info {
 595         struct sk_buff  *skb;
 596         u32             len;
 597 };
 598
 599 struct rtl8169_counters {
 600         __le64  tx_packets;
 601         __le64  rx_packets;
 602         __le64  tx_errors;
 603         __le32  rx_errors;
 604         __le16  rx_missed;
 605         __le16  align_errors;
 606         __le32  tx_one_collision;
 607         __le32  tx_multi_collision;
 608         __le64  rx_unicast;
 609         __le64  rx_broadcast;
 610         __le32  rx_multicast;
 611         __le16  tx_aborted;
 612         __le16  tx_underun;
 613 };
 614
 615 struct rtl8169_tc_offsets {
 616         bool    inited;
 617         __le64  tx_errors;
 618         __le32  tx_multi_collision;
 619         __le16  tx_aborted;
 620 };
 621
 622 enum rtl_flag {
 623         RTL_FLAG_TASK_ENABLED = 0,
 624         RTL_FLAG_TASK_RESET_PENDING,
 625         RTL_FLAG_MAX
 626 };
 627
 628 struct rtl8169_stats {
 629         u64                     packets;
 630         u64                     bytes;
 631         struct u64_stats_sync   syncp;
 632 };
 633
 634 struct rtl8169_private {
 635         void __iomem *mmio_addr;        /* memory map physical address */
 636         struct pci_dev *pci_dev;
 637         struct net_device *dev;
 638         struct phy_device *phydev;
 639         struct napi_struct napi;
 640         u32 msg_enable;
 641         u16 mac_version;
 642         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 643         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 644         u32 dirty_tx;
 645         struct rtl8169_stats rx_stats;
 646         struct rtl8169_stats tx_stats;
 647         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 648         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 649         dma_addr_t TxPhyAddr;
 650         dma_addr_t RxPhyAddr;
 651         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 652         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 653         u16 cp_cmd;
 654
 655         u16 irq_mask;
 656         const struct rtl_coalesce_info *coalesce_info;
 657         struct clk *clk;
 658
 659         struct mdio_ops {
 660                 void (*write)(struct rtl8169_private *, int, int);
 661                 int (*read)(struct rtl8169_private *, int);
 662         } mdio_ops;
 663
 664         struct jumbo_ops {
 665                 void (*enable)(struct rtl8169_private *);
 666                 void (*disable)(struct rtl8169_private *);
 667         } jumbo_ops;
 668
 669         void (*hw_start)(struct rtl8169_private *tp);
 670         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 671
 672         struct {
 673                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 674                 struct mutex mutex;
 675                 struct work_struct work;
 676         } wk;
 677
 678         unsigned irq_enabled:1;
 679         unsigned supports_gmii:1;
 680         dma_addr_t counters_phys_addr;
 681         struct rtl8169_counters *counters;
 682         struct rtl8169_tc_offsets tc_offset;
 683         u32 saved_wolopts;
 684
 685         const char *fw_name;
 686         struct rtl_fw {
 687                 const struct firmware *fw;
 688
 689 #define RTL_VER_SIZE            32
 690
 691                 char version[RTL_VER_SIZE];
 692
 693                 struct rtl_fw_phy_action {
 694                         __le32 *code;
 695                         size_t size;
 696                 } phy_action;
 697         } *rtl_fw;
 698
 699         u32 ocp_base;
 700 };
 701
 702 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 703
 704 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 705 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 706 module_param_named(debug, debug.msg_enable, int, 0);
 707 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 708 MODULE_SOFTDEP("pre: realtek");
 709 MODULE_LICENSE("GPL");
 710 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 712 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 713 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 715 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 716 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 717 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 718 MODULE_FIRMWARE(FIRMWARE_8402_1);
 719 MODULE_FIRMWARE(FIRMWARE_8411_1);
 720 MODULE_FIRMWARE(FIRMWARE_8411_2);
 721 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 722 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 723 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 724 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 725 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 726 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 727 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 728 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 729
 730 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 731 {
 732         return &tp->pci_dev->dev;
 733 }
 734
 735 static void rtl_lock_work(struct rtl8169_private *tp)
 736 {
 737         mutex_lock(&tp->wk.mutex);
 738 }
 739
 740 static void rtl_unlock_work(struct rtl8169_private *tp)
 741 {
 742         mutex_unlock(&tp->wk.mutex);
 743 }
 744
 745 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 746 {
 747         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 748 }
 749
 750 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 751 {
 752         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 753 }
 754
 755 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 756 {
 757         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 758                                            PCI_EXP_DEVCTL_READRQ, force);
 759 }
 760
 761 struct rtl_cond {
 762         bool (*check)(struct rtl8169_private *);
 763         const char *msg;
 764 };
 765
 766 static void rtl_udelay(unsigned int d)
 767 {
 768         udelay(d);
 769 }
 770
 771 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 772                           void (*delay)(unsigned int), unsigned int d, int n,
 773                           bool high)
 774 {
 775         int i;
 776
 777         for (i = 0; i < n; i++) {
 778                 delay(d);
 779                 if (c->check(tp) == high)
 780                         return true;
 781         }
 782         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 783                   c->msg, !high, n, d);
 784         return false;
 785 }
 786
 787 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 788                                       const struct rtl_cond *c,
 789                                       unsigned int d, int n)
 790 {
 791         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 792 }
 793
 794 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 795                                      const struct rtl_cond *c,
 796                                      unsigned int d, int n)
 797 {
 798         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 799 }
 800
 801 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 802                                       const struct rtl_cond *c,
 803                                       unsigned int d, int n)
 804 {
 805         return rtl_loop_wait(tp, c, msleep, d, n, true);
 806 }
 807
 808 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 809                                      const struct rtl_cond *c,
 810                                      unsigned int d, int n)
 811 {
 812         return rtl_loop_wait(tp, c, msleep, d, n, false);
 813 }
 814
 815 #define DECLARE_RTL_COND(name)                          \
 816 static bool name ## _check(struct rtl8169_private *);   \
 817                                                         \
 818 static const struct rtl_cond name = {                   \
 819         .check  = name ## _check,                       \
 820         .msg    = #name                                 \
 821 };                                                      \
 822                                                         \
 823 static bool name ## _check(struct rtl8169_private *tp)
 824
 825 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 826 {
 827         if (reg & 0xffff0001) {
 828                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 829                 return true;
 830         }
 831         return false;
 832 }
 833
 834 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 835 {
 836         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 837 }
 838
 839 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 840 {
 841         if (rtl_ocp_reg_failure(tp, reg))
 842                 return;
 843
 844         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 845
 846         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 847 }
 848
 849 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 850 {
 851         if (rtl_ocp_reg_failure(tp, reg))
 852                 return 0;
 853
 854         RTL_W32(tp, GPHY_OCP, reg << 15);
 855
 856         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 857                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 858 }
 859
 860 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 861 {
 862         if (rtl_ocp_reg_failure(tp, reg))
 863                 return;
 864
 865         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 866 }
 867
 868 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 869 {
 870         if (rtl_ocp_reg_failure(tp, reg))
 871                 return 0;
 872
 873         RTL_W32(tp, OCPDR, reg << 15);
 874
 875         return RTL_R32(tp, OCPDR);
 876 }
 877
 878 #define OCP_STD_PHY_BASE        0xa400
 879
 880 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 881 {
 882         if (reg == 0x1f) {
 883                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 884                 return;
 885         }
 886
 887         if (tp->ocp_base != OCP_STD_PHY_BASE)
 888                 reg -= 0x10;
 889
 890         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 891 }
 892
 893 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 894 {
 895         if (tp->ocp_base != OCP_STD_PHY_BASE)
 896                 reg -= 0x10;
 897
 898         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 899 }
 900
 901 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 902 {
 903         if (reg == 0x1f) {
 904                 tp->ocp_base = value << 4;
 905                 return;
 906         }
 907
 908         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 909 }
 910
 911 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 912 {
 913         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 914 }
 915
 916 DECLARE_RTL_COND(rtl_phyar_cond)
 917 {
 918         return RTL_R32(tp, PHYAR) & 0x80000000;
 919 }
 920
 921 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 922 {
 923         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 924
 925         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 926         /*
 927          * According to hardware specs a 20us delay is required after write
 928          * complete indication, but before sending next command.
 929          */
 930         udelay(20);
 931 }
 932
 933 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 934 {
 935         int value;
 936
 937         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 938
 939         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 940                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 941
 942         /*
 943          * According to hardware specs a 20us delay is required after read
 944          * complete indication, but before sending next command.
 945          */
 946         udelay(20);
 947
 948         return value;
 949 }
 950
 951 DECLARE_RTL_COND(rtl_ocpar_cond)
 952 {
 953         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 954 }
 955
 956 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 957 {
 958         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 959         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 960         RTL_W32(tp, EPHY_RXER_NUM, 0);
 961
 962         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 963 }
 964
 965 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 966 {
 967         r8168dp_1_mdio_access(tp, reg,
 968                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 969 }
 970
 971 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 972 {
 973         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 974
 975         mdelay(1);
 976         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 977         RTL_W32(tp, EPHY_RXER_NUM, 0);
 978
 979         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 980                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 981 }
 982
 983 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 984
 985 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 986 {
 987         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 988 }
 989
 990 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 991 {
 992         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 993 }
 994
 995 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 996 {
 997         r8168dp_2_mdio_start(tp);
 998
 999         r8169_mdio_write(tp, reg, value);
1000
1001         r8168dp_2_mdio_stop(tp);
1002 }
1003
1004 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1005 {
1006         int value;
1007
1008         r8168dp_2_mdio_start(tp);
1009
1010         value = r8169_mdio_read(tp, reg);
1011
1012         r8168dp_2_mdio_stop(tp);
1013
1014         return value;
1015 }
1016
1017 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1018 {
1019         tp->mdio_ops.write(tp, location, val);
1020 }
1021
1022 static int rtl_readphy(struct rtl8169_private *tp, int location)
1023 {
1024         return tp->mdio_ops.read(tp, location);
1025 }
1026
1027 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1028 {
1029         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 }
1031
1032 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1033 {
1034         int val;
1035
1036         val = rtl_readphy(tp, reg_addr);
1037         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1038 }
1039
1040 DECLARE_RTL_COND(rtl_ephyar_cond)
1041 {
1042         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1043 }
1044
1045 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1046 {
1047         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1048                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1049
1050         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1051
1052         udelay(10);
1053 }
1054
1055 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1056 {
1057         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1058
1059         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1060                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1061 }
1062
1063 DECLARE_RTL_COND(rtl_eriar_cond)
1064 {
1065         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1066 }
1067
1068 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1069                            u32 val, int type)
1070 {
1071         BUG_ON((addr & 3) || (mask == 0));
1072         RTL_W32(tp, ERIDR, val);
1073         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1074
1075         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1076 }
1077
1078 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1079                           u32 val)
1080 {
1081         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1082 }
1083
1084 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1085 {
1086         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1087
1088         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1089                 RTL_R32(tp, ERIDR) : ~0;
1090 }
1091
1092 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1093 {
1094         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1095 }
1096
1097 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1098                          u32 m)
1099 {
1100         u32 val;
1101
1102         val = rtl_eri_read(tp, addr);
1103         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1104 }
1105
1106 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1107                              u32 p)
1108 {
1109         rtl_w0w1_eri(tp, addr, mask, p, 0);
1110 }
1111
1112 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1113                                u32 m)
1114 {
1115         rtl_w0w1_eri(tp, addr, mask, 0, m);
1116 }
1117
1118 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1119 {
1120         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1121         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1122                 RTL_R32(tp, OCPDR) : ~0;
1123 }
1124
1125 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1126 {
1127         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1128 }
1129
1130 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1131                               u32 data)
1132 {
1133         RTL_W32(tp, OCPDR, data);
1134         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1135         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1136 }
1137
1138 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1139                               u32 data)
1140 {
1141         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1142                        data, ERIAR_OOB);
1143 }
1144
1145 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1146 {
1147         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1148
1149         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1150 }
1151
1152 #define OOB_CMD_RESET           0x00
1153 #define OOB_CMD_DRIVER_START    0x05
1154 #define OOB_CMD_DRIVER_STOP     0x06
1155
1156 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1157 {
1158         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1159 }
1160
1161 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1162 {
1163         u16 reg;
1164
1165         reg = rtl8168_get_ocp_reg(tp);
1166
1167         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1168 }
1169
1170 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1171 {
1172         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1173 }
1174
1175 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1176 {
1177         return RTL_R8(tp, IBISR0) & 0x20;
1178 }
1179
1180 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1181 {
1182         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1183         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1184         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1185         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1186 }
1187
1188 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1189 {
1190         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1191         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1192 }
1193
1194 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1195 {
1196         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1197         r8168ep_ocp_write(tp, 0x01, 0x30,
1198                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1199         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1200 }
1201
1202 static void rtl8168_driver_start(struct rtl8169_private *tp)
1203 {
1204         switch (tp->mac_version) {
1205         case RTL_GIGA_MAC_VER_27:
1206         case RTL_GIGA_MAC_VER_28:
1207         case RTL_GIGA_MAC_VER_31:
1208                 rtl8168dp_driver_start(tp);
1209                 break;
1210         case RTL_GIGA_MAC_VER_49:
1211         case RTL_GIGA_MAC_VER_50:
1212         case RTL_GIGA_MAC_VER_51:
1213                 rtl8168ep_driver_start(tp);
1214                 break;
1215         default:
1216                 BUG();
1217                 break;
1218         }
1219 }
1220
1221 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1222 {
1223         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1224         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1225 }
1226
1227 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1228 {
1229         rtl8168ep_stop_cmac(tp);
1230         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1231         r8168ep_ocp_write(tp, 0x01, 0x30,
1232                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1233         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1234 }
1235
1236 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1237 {
1238         switch (tp->mac_version) {
1239         case RTL_GIGA_MAC_VER_27:
1240         case RTL_GIGA_MAC_VER_28:
1241         case RTL_GIGA_MAC_VER_31:
1242                 rtl8168dp_driver_stop(tp);
1243                 break;
1244         case RTL_GIGA_MAC_VER_49:
1245         case RTL_GIGA_MAC_VER_50:
1246         case RTL_GIGA_MAC_VER_51:
1247                 rtl8168ep_driver_stop(tp);
1248                 break;
1249         default:
1250                 BUG();
1251                 break;
1252         }
1253 }
1254
1255 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1256 {
1257         u16 reg = rtl8168_get_ocp_reg(tp);
1258
1259         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1260 }
1261
1262 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1263 {
1264         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1265 }
1266
1267 static bool r8168_check_dash(struct rtl8169_private *tp)
1268 {
1269         switch (tp->mac_version) {
1270         case RTL_GIGA_MAC_VER_27:
1271         case RTL_GIGA_MAC_VER_28:
1272         case RTL_GIGA_MAC_VER_31:
1273                 return r8168dp_check_dash(tp);
1274         case RTL_GIGA_MAC_VER_49:
1275         case RTL_GIGA_MAC_VER_50:
1276         case RTL_GIGA_MAC_VER_51:
1277                 return r8168ep_check_dash(tp);
1278         default:
1279                 return false;
1280         }
1281 }
1282
1283 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1284 {
1285         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1286         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1287 }
1288
1289 struct exgmac_reg {
1290         u16 addr;
1291         u16 mask;
1292         u32 val;
1293 };
1294
1295 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1296                                    const struct exgmac_reg *r, int len)
1297 {
1298         while (len-- > 0) {
1299                 rtl_eri_write(tp, r->addr, r->mask, r->val);
1300                 r++;
1301         }
1302 }
1303
1304 DECLARE_RTL_COND(rtl_efusear_cond)
1305 {
1306         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1307 }
1308
1309 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1310 {
1311         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1312
1313         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1314                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1315 }
1316
1317 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1318 {
1319         RTL_W16(tp, IntrStatus, bits);
1320 }
1321
1322 static void rtl_irq_disable(struct rtl8169_private *tp)
1323 {
1324         RTL_W16(tp, IntrMask, 0);
1325         tp->irq_enabled = 0;
1326 }
1327
1328 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1329 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1330 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1331
1332 static void rtl_irq_enable(struct rtl8169_private *tp)
1333 {
1334         tp->irq_enabled = 1;
1335         RTL_W16(tp, IntrMask, tp->irq_mask);
1336 }
1337
1338 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1339 {
1340         rtl_irq_disable(tp);
1341         rtl_ack_events(tp, 0xffff);
1342         /* PCI commit */
1343         RTL_R8(tp, ChipCmd);
1344 }
1345
1346 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1347 {
1348         struct net_device *dev = tp->dev;
1349         struct phy_device *phydev = tp->phydev;
1350
1351         if (!netif_running(dev))
1352                 return;
1353
1354         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1355             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1356                 if (phydev->speed == SPEED_1000) {
1357                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1358                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1359                 } else if (phydev->speed == SPEED_100) {
1360                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1361                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1362                 } else {
1363                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1364                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1365                 }
1366                 rtl_reset_packet_filter(tp);
1367         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1368                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1369                 if (phydev->speed == SPEED_1000) {
1370                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1371                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1372                 } else {
1373                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1374                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1375                 }
1376         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1377                 if (phydev->speed == SPEED_10) {
1378                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1379                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1380                 } else {
1381                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1382                 }
1383         }
1384 }
1385
1386 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1387
1388 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1389 {
1390         struct rtl8169_private *tp = netdev_priv(dev);
1391
1392         rtl_lock_work(tp);
1393         wol->supported = WAKE_ANY;
1394         wol->wolopts = tp->saved_wolopts;
1395         rtl_unlock_work(tp);
1396 }
1397
1398 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1399 {
1400         unsigned int i, tmp;
1401         static const struct {
1402                 u32 opt;
1403                 u16 reg;
1404                 u8  mask;
1405         } cfg[] = {
1406                 { WAKE_PHY,   Config3, LinkUp },
1407                 { WAKE_UCAST, Config5, UWF },
1408                 { WAKE_BCAST, Config5, BWF },
1409                 { WAKE_MCAST, Config5, MWF },
1410                 { WAKE_ANY,   Config5, LanWake },
1411                 { WAKE_MAGIC, Config3, MagicPacket }
1412         };
1413         u8 options;
1414
1415         rtl_unlock_config_regs(tp);
1416
1417         switch (tp->mac_version) {
1418         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1419         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1420                 tmp = ARRAY_SIZE(cfg) - 1;
1421                 if (wolopts & WAKE_MAGIC)
1422                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1423                                          MagicPacket_v2);
1424                 else
1425                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1426                                            MagicPacket_v2);
1427                 break;
1428         default:
1429                 tmp = ARRAY_SIZE(cfg);
1430                 break;
1431         }
1432
1433         for (i = 0; i < tmp; i++) {
1434                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1435                 if (wolopts & cfg[i].opt)
1436                         options |= cfg[i].mask;
1437                 RTL_W8(tp, cfg[i].reg, options);
1438         }
1439
1440         switch (tp->mac_version) {
1441         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1442                 options = RTL_R8(tp, Config1) & ~PMEnable;
1443                 if (wolopts)
1444                         options |= PMEnable;
1445                 RTL_W8(tp, Config1, options);
1446                 break;
1447         default:
1448                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1449                 if (wolopts)
1450                         options |= PME_SIGNAL;
1451                 RTL_W8(tp, Config2, options);
1452                 break;
1453         }
1454
1455         rtl_lock_config_regs(tp);
1456
1457         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1458 }
1459
1460 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1461 {
1462         struct rtl8169_private *tp = netdev_priv(dev);
1463         struct device *d = tp_to_dev(tp);
1464
1465         if (wol->wolopts & ~WAKE_ANY)
1466                 return -EINVAL;
1467
1468         pm_runtime_get_noresume(d);
1469
1470         rtl_lock_work(tp);
1471
1472         tp->saved_wolopts = wol->wolopts;
1473
1474         if (pm_runtime_active(d))
1475                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1476
1477         rtl_unlock_work(tp);
1478
1479         pm_runtime_put_noidle(d);
1480
1481         return 0;
1482 }
1483
1484 static void rtl8169_get_drvinfo(struct net_device *dev,
1485                                 struct ethtool_drvinfo *info)
1486 {
1487         struct rtl8169_private *tp = netdev_priv(dev);
1488         struct rtl_fw *rtl_fw = tp->rtl_fw;
1489
1490         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1491         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1492         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1493         if (rtl_fw)
1494                 strlcpy(info->fw_version, rtl_fw->version,
1495                         sizeof(info->fw_version));
1496 }
1497
1498 static int rtl8169_get_regs_len(struct net_device *dev)
1499 {
1500         return R8169_REGS_SIZE;
1501 }
1502
1503 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1504         netdev_features_t features)
1505 {
1506         struct rtl8169_private *tp = netdev_priv(dev);
1507
1508         if (dev->mtu > TD_MSS_MAX)
1509                 features &= ~NETIF_F_ALL_TSO;
1510
1511         if (dev->mtu > JUMBO_1K &&
1512             tp->mac_version > RTL_GIGA_MAC_VER_06)
1513                 features &= ~NETIF_F_IP_CSUM;
1514
1515         return features;
1516 }
1517
1518 static int rtl8169_set_features(struct net_device *dev,
1519                                 netdev_features_t features)
1520 {
1521         struct rtl8169_private *tp = netdev_priv(dev);
1522         u32 rx_config;
1523
1524         rtl_lock_work(tp);
1525
1526         rx_config = RTL_R32(tp, RxConfig);
1527         if (features & NETIF_F_RXALL)
1528                 rx_config |= (AcceptErr | AcceptRunt);
1529         else
1530                 rx_config &= ~(AcceptErr | AcceptRunt);
1531
1532         RTL_W32(tp, RxConfig, rx_config);
1533
1534         if (features & NETIF_F_RXCSUM)
1535                 tp->cp_cmd |= RxChkSum;
1536         else
1537                 tp->cp_cmd &= ~RxChkSum;
1538
1539         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1540                 tp->cp_cmd |= RxVlan;
1541         else
1542                 tp->cp_cmd &= ~RxVlan;
1543
1544         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1545         RTL_R16(tp, CPlusCmd);
1546
1547         rtl_unlock_work(tp);
1548
1549         return 0;
1550 }
1551
1552 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1553 {
1554         return (skb_vlan_tag_present(skb)) ?
1555                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1556 }
1557
1558 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1559 {
1560         u32 opts2 = le32_to_cpu(desc->opts2);
1561
1562         if (opts2 & RxVlanTag)
1563                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1564 }
1565
1566 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1567                              void *p)
1568 {
1569         struct rtl8169_private *tp = netdev_priv(dev);
1570         u32 __iomem *data = tp->mmio_addr;
1571         u32 *dw = p;
1572         int i;
1573
1574         rtl_lock_work(tp);
1575         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1576                 memcpy_fromio(dw++, data++, 4);
1577         rtl_unlock_work(tp);
1578 }
1579
1580 static u32 rtl8169_get_msglevel(struct net_device *dev)
1581 {
1582         struct rtl8169_private *tp = netdev_priv(dev);
1583
1584         return tp->msg_enable;
1585 }
1586
1587 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1588 {
1589         struct rtl8169_private *tp = netdev_priv(dev);
1590
1591         tp->msg_enable = value;
1592 }
1593
1594 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1595         "tx_packets",
1596         "rx_packets",
1597         "tx_errors",
1598         "rx_errors",
1599         "rx_missed",
1600         "align_errors",
1601         "tx_single_collisions",
1602         "tx_multi_collisions",
1603         "unicast",
1604         "broadcast",
1605         "multicast",
1606         "tx_aborted",
1607         "tx_underrun",
1608 };
1609
1610 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1611 {
1612         switch (sset) {
1613         case ETH_SS_STATS:
1614                 return ARRAY_SIZE(rtl8169_gstrings);
1615         default:
1616                 return -EOPNOTSUPP;
1617         }
1618 }
1619
1620 DECLARE_RTL_COND(rtl_counters_cond)
1621 {
1622         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1623 }
1624
1625 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1626 {
1627         dma_addr_t paddr = tp->counters_phys_addr;
1628         u32 cmd;
1629
1630         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1631         RTL_R32(tp, CounterAddrHigh);
1632         cmd = (u64)paddr & DMA_BIT_MASK(32);
1633         RTL_W32(tp, CounterAddrLow, cmd);
1634         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1635
1636         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1637 }
1638
1639 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1640 {
1641         /*
1642          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1643          * tally counters.
1644          */
1645         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1646                 return true;
1647
1648         return rtl8169_do_counters(tp, CounterReset);
1649 }
1650
1651 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1652 {
1653         u8 val = RTL_R8(tp, ChipCmd);
1654
1655         /*
1656          * Some chips are unable to dump tally counters when the receiver
1657          * is disabled. If 0xff chip may be in a PCI power-save state.
1658          */
1659         if (!(val & CmdRxEnb) || val == 0xff)
1660                 return true;
1661
1662         return rtl8169_do_counters(tp, CounterDump);
1663 }
1664
1665 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1666 {
1667         struct rtl8169_counters *counters = tp->counters;
1668         bool ret = false;
1669
1670         /*
1671          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1672          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1673          * reset by a power cycle, while the counter values collected by the
1674          * driver are reset at every driver unload/load cycle.
1675          *
1676          * To make sure the HW values returned by @get_stats64 match the SW
1677          * values, we collect the initial values at first open(*) and use them
1678          * as offsets to normalize the values returned by @get_stats64.
1679          *
1680          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1681          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1682          * set at open time by rtl_hw_start.
1683          */
1684
1685         if (tp->tc_offset.inited)
1686                 return true;
1687
1688         /* If both, reset and update fail, propagate to caller. */
1689         if (rtl8169_reset_counters(tp))
1690                 ret = true;
1691
1692         if (rtl8169_update_counters(tp))
1693                 ret = true;
1694
1695         tp->tc_offset.tx_errors = counters->tx_errors;
1696         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1697         tp->tc_offset.tx_aborted = counters->tx_aborted;
1698         tp->tc_offset.inited = true;
1699
1700         return ret;
1701 }
1702
1703 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1704                                       struct ethtool_stats *stats, u64 *data)
1705 {
1706         struct rtl8169_private *tp = netdev_priv(dev);
1707         struct device *d = tp_to_dev(tp);
1708         struct rtl8169_counters *counters = tp->counters;
1709
1710         ASSERT_RTNL();
1711
1712         pm_runtime_get_noresume(d);
1713
1714         if (pm_runtime_active(d))
1715                 rtl8169_update_counters(tp);
1716
1717         pm_runtime_put_noidle(d);
1718
1719         data[0] = le64_to_cpu(counters->tx_packets);
1720         data[1] = le64_to_cpu(counters->rx_packets);
1721         data[2] = le64_to_cpu(counters->tx_errors);
1722         data[3] = le32_to_cpu(counters->rx_errors);
1723         data[4] = le16_to_cpu(counters->rx_missed);
1724         data[5] = le16_to_cpu(counters->align_errors);
1725         data[6] = le32_to_cpu(counters->tx_one_collision);
1726         data[7] = le32_to_cpu(counters->tx_multi_collision);
1727         data[8] = le64_to_cpu(counters->rx_unicast);
1728         data[9] = le64_to_cpu(counters->rx_broadcast);
1729         data[10] = le32_to_cpu(counters->rx_multicast);
1730         data[11] = le16_to_cpu(counters->tx_aborted);
1731         data[12] = le16_to_cpu(counters->tx_underun);
1732 }
1733
1734 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1735 {
1736         switch(stringset) {
1737         case ETH_SS_STATS:
1738                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1739                 break;
1740         }
1741 }
1742
1743 /*
1744  * Interrupt coalescing
1745  *
1746  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1747  * >     8169, 8168 and 810x line of chipsets
1748  *
1749  * 8169, 8168, and 8136(810x) serial chipsets support it.
1750  *
1751  * > 2 - the Tx timer unit at gigabit speed
1752  *
1753  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1754  * (0xe0) bit 1 and bit 0.
1755  *
1756  * For 8169
1757  * bit[1:0] \ speed        1000M           100M            10M
1758  * 0 0                     320ns           2.56us          40.96us
1759  * 0 1                     2.56us          20.48us         327.7us
1760  * 1 0                     5.12us          40.96us         655.4us
1761  * 1 1                     10.24us         81.92us         1.31ms
1762  *
1763  * For the other
1764  * bit[1:0] \ speed        1000M           100M            10M
1765  * 0 0                     5us             2.56us          40.96us
1766  * 0 1                     40us            20.48us         327.7us
1767  * 1 0                     80us            40.96us         655.4us
1768  * 1 1                     160us           81.92us         1.31ms
1769  */
1770
1771 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1772 struct rtl_coalesce_scale {
1773         /* Rx / Tx */
1774         u32 nsecs[2];
1775 };
1776
1777 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1778 struct rtl_coalesce_info {
1779         u32 speed;
1780         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1781 };
1782
1783 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1784 #define rxtx_x1822(r, t) {              \
1785         {{(r),          (t)}},          \
1786         {{(r)*8,        (t)*8}},        \
1787         {{(r)*8*2,      (t)*8*2}},      \
1788         {{(r)*8*2*2,    (t)*8*2*2}},    \
1789 }
1790 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1791         /* speed        delays:     rx00   tx00 */
1792         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1793         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1794         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1795         { 0 },
1796 };
1797
1798 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1799         /* speed        delays:     rx00   tx00 */
1800         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1801         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1802         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1803         { 0 },
1804 };
1805 #undef rxtx_x1822
1806
1807 /* get rx/tx scale vector corresponding to current speed */
1808 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1809 {
1810         struct rtl8169_private *tp = netdev_priv(dev);
1811         struct ethtool_link_ksettings ecmd;
1812         const struct rtl_coalesce_info *ci;
1813         int rc;
1814
1815         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1816         if (rc < 0)
1817                 return ERR_PTR(rc);
1818
1819         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1820                 if (ecmd.base.speed == ci->speed) {
1821                         return ci;
1822                 }
1823         }
1824
1825         return ERR_PTR(-ELNRNG);
1826 }
1827
1828 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1829 {
1830         struct rtl8169_private *tp = netdev_priv(dev);
1831         const struct rtl_coalesce_info *ci;
1832         const struct rtl_coalesce_scale *scale;
1833         struct {
1834                 u32 *max_frames;
1835                 u32 *usecs;
1836         } coal_settings [] = {
1837                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1838                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1839         }, *p = coal_settings;
1840         int i;
1841         u16 w;
1842
1843         memset(ec, 0, sizeof(*ec));
1844
1845         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1846         ci = rtl_coalesce_info(dev);
1847         if (IS_ERR(ci))
1848                 return PTR_ERR(ci);
1849
1850         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1851
1852         /* read IntrMitigate and adjust according to scale */
1853         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1854                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1855                 w >>= RTL_COALESCE_SHIFT;
1856                 *p->usecs = w & RTL_COALESCE_MASK;
1857         }
1858
1859         for (i = 0; i < 2; i++) {
1860                 p = coal_settings + i;
1861                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1862
1863                 /*
1864                  * ethtool_coalesce says it is illegal to set both usecs and
1865                  * max_frames to 0.
1866                  */
1867                 if (!*p->usecs && !*p->max_frames)
1868                         *p->max_frames = 1;
1869         }
1870
1871         return 0;
1872 }
1873
1874 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1875 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1876                         struct net_device *dev, u32 nsec, u16 *cp01)
1877 {
1878         const struct rtl_coalesce_info *ci;
1879         u16 i;
1880
1881         ci = rtl_coalesce_info(dev);
1882         if (IS_ERR(ci))
1883                 return ERR_CAST(ci);
1884
1885         for (i = 0; i < 4; i++) {
1886                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1887                                         ci->scalev[i].nsecs[1]);
1888                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1889                         *cp01 = i;
1890                         return &ci->scalev[i];
1891                 }
1892         }
1893
1894         return ERR_PTR(-EINVAL);
1895 }
1896
1897 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1898 {
1899         struct rtl8169_private *tp = netdev_priv(dev);
1900         const struct rtl_coalesce_scale *scale;
1901         struct {
1902                 u32 frames;
1903                 u32 usecs;
1904         } coal_settings [] = {
1905                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1906                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1907         }, *p = coal_settings;
1908         u16 w = 0, cp01;
1909         int i;
1910
1911         scale = rtl_coalesce_choose_scale(dev,
1912                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1913         if (IS_ERR(scale))
1914                 return PTR_ERR(scale);
1915
1916         for (i = 0; i < 2; i++, p++) {
1917                 u32 units;
1918
1919                 /*
1920                  * accept max_frames=1 we returned in rtl_get_coalesce.
1921                  * accept it not only when usecs=0 because of e.g. the following scenario:
1922                  *
1923                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1924                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1925                  * - then user does `ethtool -C eth0 rx-usecs 100`
1926                  *
1927                  * since ethtool sends to kernel whole ethtool_coalesce
1928                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1929                  * we'll reject it below in `frames % 4 != 0`.
1930                  */
1931                 if (p->frames == 1) {
1932                         p->frames = 0;
1933                 }
1934
1935                 units = p->usecs * 1000 / scale->nsecs[i];
1936                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1937                         return -EINVAL;
1938
1939                 w <<= RTL_COALESCE_SHIFT;
1940                 w |= units;
1941                 w <<= RTL_COALESCE_SHIFT;
1942                 w |= p->frames >> 2;
1943         }
1944
1945         rtl_lock_work(tp);
1946
1947         RTL_W16(tp, IntrMitigate, swab16(w));
1948
1949         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1950         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1951         RTL_R16(tp, CPlusCmd);
1952
1953         rtl_unlock_work(tp);
1954
1955         return 0;
1956 }
1957
1958 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1959 {
1960         struct phy_device *phydev = tp->phydev;
1961         int ret;
1962
1963         switch (tp->mac_version) {
1964         case RTL_GIGA_MAC_VER_34:
1965         case RTL_GIGA_MAC_VER_35:
1966         case RTL_GIGA_MAC_VER_36:
1967         case RTL_GIGA_MAC_VER_38:
1968                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1969                 break;
1970         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1971                 phy_write(phydev, 0x1f, 0x0a5c);
1972                 ret = phy_read(phydev, 0x12);
1973                 phy_write(phydev, 0x1f, 0x0000);
1974                 break;
1975         default:
1976                 ret = -EPROTONOSUPPORT;
1977                 break;
1978         }
1979
1980         return ret;
1981 }
1982
1983 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1984 {
1985         struct phy_device *phydev = tp->phydev;
1986         int ret;
1987
1988         switch (tp->mac_version) {
1989         case RTL_GIGA_MAC_VER_34:
1990         case RTL_GIGA_MAC_VER_35:
1991         case RTL_GIGA_MAC_VER_36:
1992         case RTL_GIGA_MAC_VER_38:
1993                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1994                 break;
1995         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1996                 phy_write(phydev, 0x1f, 0x0a5d);
1997                 ret = phy_read(phydev, 0x11);
1998                 phy_write(phydev, 0x1f, 0x0000);
1999                 break;
2000         default:
2001                 ret = -EPROTONOSUPPORT;
2002                 break;
2003         }
2004
2005         return ret;
2006 }
2007
2008 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2009 {
2010         struct phy_device *phydev = tp->phydev;
2011         int ret;
2012
2013         switch (tp->mac_version) {
2014         case RTL_GIGA_MAC_VER_34:
2015         case RTL_GIGA_MAC_VER_35:
2016         case RTL_GIGA_MAC_VER_36:
2017         case RTL_GIGA_MAC_VER_38:
2018                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2019                 break;
2020         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2021                 phy_write(phydev, 0x1f, 0x0a5d);
2022                 ret = phy_read(phydev, 0x10);
2023                 phy_write(phydev, 0x1f, 0x0000);
2024                 break;
2025         default:
2026                 ret = -EPROTONOSUPPORT;
2027                 break;
2028         }
2029
2030         return ret;
2031 }
2032
2033 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2034 {
2035         struct phy_device *phydev = tp->phydev;
2036         int ret = 0;
2037
2038         switch (tp->mac_version) {
2039         case RTL_GIGA_MAC_VER_34:
2040         case RTL_GIGA_MAC_VER_35:
2041         case RTL_GIGA_MAC_VER_36:
2042         case RTL_GIGA_MAC_VER_38:
2043                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2044                 break;
2045         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2046                 phy_write(phydev, 0x1f, 0x0a5d);
2047                 phy_write(phydev, 0x10, val);
2048                 phy_write(phydev, 0x1f, 0x0000);
2049                 break;
2050         default:
2051                 ret = -EPROTONOSUPPORT;
2052                 break;
2053         }
2054
2055         return ret;
2056 }
2057
2058 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2059 {
2060         struct rtl8169_private *tp = netdev_priv(dev);
2061         struct device *d = tp_to_dev(tp);
2062         int ret;
2063
2064         pm_runtime_get_noresume(d);
2065
2066         if (!pm_runtime_active(d)) {
2067                 ret = -EOPNOTSUPP;
2068                 goto out;
2069         }
2070
2071         /* Get Supported EEE */
2072         ret = rtl_get_eee_supp(tp);
2073         if (ret < 0)
2074                 goto out;
2075         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2076
2077         /* Get advertisement EEE */
2078         ret = rtl_get_eee_adv(tp);
2079         if (ret < 0)
2080                 goto out;
2081         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2082         data->eee_enabled = !!data->advertised;
2083
2084         /* Get LP advertisement EEE */
2085         ret = rtl_get_eee_lpadv(tp);
2086         if (ret < 0)
2087                 goto out;
2088         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2089         data->eee_active = !!(data->advertised & data->lp_advertised);
2090 out:
2091         pm_runtime_put_noidle(d);
2092         return ret < 0 ? ret : 0;
2093 }
2094
2095 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2096 {
2097         struct rtl8169_private *tp = netdev_priv(dev);
2098         struct device *d = tp_to_dev(tp);
2099         int old_adv, adv = 0, cap, ret;
2100
2101         pm_runtime_get_noresume(d);
2102
2103         if (!dev->phydev || !pm_runtime_active(d)) {
2104                 ret = -EOPNOTSUPP;
2105                 goto out;
2106         }
2107
2108         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2109             dev->phydev->duplex != DUPLEX_FULL) {
2110                 ret = -EPROTONOSUPPORT;
2111                 goto out;
2112         }
2113
2114         /* Get Supported EEE */
2115         ret = rtl_get_eee_supp(tp);
2116         if (ret < 0)
2117                 goto out;
2118         cap = ret;
2119
2120         ret = rtl_get_eee_adv(tp);
2121         if (ret < 0)
2122                 goto out;
2123         old_adv = ret;
2124
2125         if (data->eee_enabled) {
2126                 adv = !data->advertised ? cap :
2127                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2128                 /* Mask prohibited EEE modes */
2129                 adv &= ~dev->phydev->eee_broken_modes;
2130         }
2131
2132         if (old_adv != adv) {
2133                 ret = rtl_set_eee_adv(tp, adv);
2134                 if (ret < 0)
2135                         goto out;
2136
2137                 /* Restart autonegotiation so the new modes get sent to the
2138                  * link partner.
2139                  */
2140                 ret = phy_restart_aneg(dev->phydev);
2141         }
2142
2143 out:
2144         pm_runtime_put_noidle(d);
2145         return ret < 0 ? ret : 0;
2146 }
2147
2148 static const struct ethtool_ops rtl8169_ethtool_ops = {
2149         .get_drvinfo            = rtl8169_get_drvinfo,
2150         .get_regs_len           = rtl8169_get_regs_len,
2151         .get_link               = ethtool_op_get_link,
2152         .get_coalesce           = rtl_get_coalesce,
2153         .set_coalesce           = rtl_set_coalesce,
2154         .get_msglevel           = rtl8169_get_msglevel,
2155         .set_msglevel           = rtl8169_set_msglevel,
2156         .get_regs               = rtl8169_get_regs,
2157         .get_wol                = rtl8169_get_wol,
2158         .set_wol                = rtl8169_set_wol,
2159         .get_strings            = rtl8169_get_strings,
2160         .get_sset_count         = rtl8169_get_sset_count,
2161         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2162         .get_ts_info            = ethtool_op_get_ts_info,
2163         .nway_reset             = phy_ethtool_nway_reset,
2164         .get_eee                = rtl8169_get_eee,
2165         .set_eee                = rtl8169_set_eee,
2166         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2167         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2168 };
2169
2170 static void rtl_enable_eee(struct rtl8169_private *tp)
2171 {
2172         int supported = rtl_get_eee_supp(tp);
2173
2174         if (supported > 0)
2175                 rtl_set_eee_adv(tp, supported);
2176 }
2177
2178 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2179 {
2180         /*
2181          * The driver currently handles the 8168Bf and the 8168Be identically
2182          * but they can be identified more specifically through the test below
2183          * if needed:
2184          *
2185          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2186          *
2187          * Same thing for the 8101Eb and the 8101Ec:
2188          *
2189          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2190          */
2191         static const struct rtl_mac_info {
2192                 u16 mask;
2193                 u16 val;
2194                 u16 mac_version;
2195         } mac_info[] = {
2196                 /* 8168EP family. */
2197                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2198                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2199                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2200
2201                 /* 8168H family. */
2202                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2203                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2204
2205                 /* 8168G family. */
2206                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2207                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2208                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2209                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2210
2211                 /* 8168F family. */
2212                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2213                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2214                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2215
2216                 /* 8168E family. */
2217                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2218                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2219                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2220
2221                 /* 8168D family. */
2222                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2223                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2224
2225                 /* 8168DP family. */
2226                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2227                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2228                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2229
2230                 /* 8168C family. */
2231                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2232                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2233                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2234                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2235                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2236                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2237                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2238
2239                 /* 8168B family. */
2240                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2241                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2242                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2243
2244                 /* 8101 family. */
2245                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2246                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2247                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2248                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2249                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2250                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2251                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2252                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2253                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2254                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2255                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2256                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2257                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2258                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2259                 /* FIXME: where did these entries come from ? -- FR */
2260                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2261                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2262
2263                 /* 8110 family. */
2264                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2265                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2266                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2267                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2268                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2269                 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2270
2271                 /* Catch-all */
2272                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2273         };
2274         const struct rtl_mac_info *p = mac_info;
2275         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2276
2277         while ((reg & p->mask) != p->val)
2278                 p++;
2279         tp->mac_version = p->mac_version;
2280
2281         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2282                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2283         } else if (!tp->supports_gmii) {
2284                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2285                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2286                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2287                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2288                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2289                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2290         }
2291 }
2292
2293 struct phy_reg {
2294         u16 reg;
2295         u16 val;
2296 };
2297
2298 static void rtl_writephy_batch(struct rtl8169_private *tp,
2299                                const struct phy_reg *regs, int len)
2300 {
2301         while (len-- > 0) {
2302                 rtl_writephy(tp, regs->reg, regs->val);
2303                 regs++;
2304         }
2305 }
2306
2307 #define PHY_READ                0x00000000
2308 #define PHY_DATA_OR             0x10000000
2309 #define PHY_DATA_AND            0x20000000
2310 #define PHY_BJMPN               0x30000000
2311 #define PHY_MDIO_CHG            0x40000000
2312 #define PHY_CLEAR_READCOUNT     0x70000000
2313 #define PHY_WRITE               0x80000000
2314 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2315 #define PHY_COMP_EQ_SKIPN       0xa0000000
2316 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2317 #define PHY_WRITE_PREVIOUS      0xc0000000
2318 #define PHY_SKIPN               0xd0000000
2319 #define PHY_DELAY_MS            0xe0000000
2320
2321 struct fw_info {
2322         u32     magic;
2323         char    version[RTL_VER_SIZE];
2324         __le32  fw_start;
2325         __le32  fw_len;
2326         u8      chksum;
2327 } __packed;
2328
2329 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2330
2331 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2332 {
2333         const struct firmware *fw = rtl_fw->fw;
2334         struct fw_info *fw_info = (struct fw_info *)fw->data;
2335         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2336         char *version = rtl_fw->version;
2337         bool rc = false;
2338
2339         if (fw->size < FW_OPCODE_SIZE)
2340                 goto out;
2341
2342         if (!fw_info->magic) {
2343                 size_t i, size, start;
2344                 u8 checksum = 0;
2345
2346                 if (fw->size < sizeof(*fw_info))
2347                         goto out;
2348
2349                 for (i = 0; i < fw->size; i++)
2350                         checksum += fw->data[i];
2351                 if (checksum != 0)
2352                         goto out;
2353
2354                 start = le32_to_cpu(fw_info->fw_start);
2355                 if (start > fw->size)
2356                         goto out;
2357
2358                 size = le32_to_cpu(fw_info->fw_len);
2359                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2360                         goto out;
2361
2362                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2363
2364                 pa->code = (__le32 *)(fw->data + start);
2365                 pa->size = size;
2366         } else {
2367                 if (fw->size % FW_OPCODE_SIZE)
2368                         goto out;
2369
2370                 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2371
2372                 pa->code = (__le32 *)fw->data;
2373                 pa->size = fw->size / FW_OPCODE_SIZE;
2374         }
2375         version[RTL_VER_SIZE - 1] = 0;
2376
2377         rc = true;
2378 out:
2379         return rc;
2380 }
2381
2382 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2383                            struct rtl_fw_phy_action *pa)
2384 {
2385         bool rc = false;
2386         size_t index;
2387
2388         for (index = 0; index < pa->size; index++) {
2389                 u32 action = le32_to_cpu(pa->code[index]);
2390                 u32 regno = (action & 0x0fff0000) >> 16;
2391
2392                 switch(action & 0xf0000000) {
2393                 case PHY_READ:
2394                 case PHY_DATA_OR:
2395                 case PHY_DATA_AND:
2396                 case PHY_MDIO_CHG:
2397                 case PHY_CLEAR_READCOUNT:
2398                 case PHY_WRITE:
2399                 case PHY_WRITE_PREVIOUS:
2400                 case PHY_DELAY_MS:
2401                         break;
2402
2403                 case PHY_BJMPN:
2404                         if (regno > index) {
2405                                 netif_err(tp, ifup, tp->dev,
2406                                           "Out of range of firmware\n");
2407                                 goto out;
2408                         }
2409                         break;
2410                 case PHY_READCOUNT_EQ_SKIP:
2411                         if (index + 2 >= pa->size) {
2412                                 netif_err(tp, ifup, tp->dev,
2413                                           "Out of range of firmware\n");
2414                                 goto out;
2415                         }
2416                         break;
2417                 case PHY_COMP_EQ_SKIPN:
2418                 case PHY_COMP_NEQ_SKIPN:
2419                 case PHY_SKIPN:
2420                         if (index + 1 + regno >= pa->size) {
2421                                 netif_err(tp, ifup, tp->dev,
2422                                           "Out of range of firmware\n");
2423                                 goto out;
2424                         }
2425                         break;
2426
2427                 default:
2428                         netif_err(tp, ifup, tp->dev,
2429                                   "Invalid action 0x%08x\n", action);
2430                         goto out;
2431                 }
2432         }
2433         rc = true;
2434 out:
2435         return rc;
2436 }
2437
2438 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2439 {
2440         struct net_device *dev = tp->dev;
2441         int rc = -EINVAL;
2442
2443         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2444                 netif_err(tp, ifup, dev, "invalid firmware\n");
2445                 goto out;
2446         }
2447
2448         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2449                 rc = 0;
2450 out:
2451         return rc;
2452 }
2453
2454 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2455 {
2456         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2457         struct mdio_ops org, *ops = &tp->mdio_ops;
2458         u32 predata, count;
2459         size_t index;
2460
2461         predata = count = 0;
2462         org.write = ops->write;
2463         org.read = ops->read;
2464
2465         for (index = 0; index < pa->size; ) {
2466                 u32 action = le32_to_cpu(pa->code[index]);
2467                 u32 data = action & 0x0000ffff;
2468                 u32 regno = (action & 0x0fff0000) >> 16;
2469
2470                 if (!action)
2471                         break;
2472
2473                 switch(action & 0xf0000000) {
2474                 case PHY_READ:
2475                         predata = rtl_readphy(tp, regno);
2476                         count++;
2477                         index++;
2478                         break;
2479                 case PHY_DATA_OR:
2480                         predata |= data;
2481                         index++;
2482                         break;
2483                 case PHY_DATA_AND:
2484                         predata &= data;
2485                         index++;
2486                         break;
2487                 case PHY_BJMPN:
2488                         index -= regno;
2489                         break;
2490                 case PHY_MDIO_CHG:
2491                         if (data == 0) {
2492                                 ops->write = org.write;
2493                                 ops->read = org.read;
2494                         } else if (data == 1) {
2495                                 ops->write = mac_mcu_write;
2496                                 ops->read = mac_mcu_read;
2497                         }
2498
2499                         index++;
2500                         break;
2501                 case PHY_CLEAR_READCOUNT:
2502                         count = 0;
2503                         index++;
2504                         break;
2505                 case PHY_WRITE:
2506                         rtl_writephy(tp, regno, data);
2507                         index++;
2508                         break;
2509                 case PHY_READCOUNT_EQ_SKIP:
2510                         index += (count == data) ? 2 : 1;
2511                         break;
2512                 case PHY_COMP_EQ_SKIPN:
2513                         if (predata == data)
2514                                 index += regno;
2515                         index++;
2516                         break;
2517                 case PHY_COMP_NEQ_SKIPN:
2518                         if (predata != data)
2519                                 index += regno;
2520                         index++;
2521                         break;
2522                 case PHY_WRITE_PREVIOUS:
2523                         rtl_writephy(tp, regno, predata);
2524                         index++;
2525                         break;
2526                 case PHY_SKIPN:
2527                         index += regno + 1;
2528                         break;
2529                 case PHY_DELAY_MS:
2530                         mdelay(data);
2531                         index++;
2532                         break;
2533
2534                 default:
2535                         BUG();
2536                 }
2537         }
2538
2539         ops->write = org.write;
2540         ops->read = org.read;
2541 }
2542
2543 static void rtl_release_firmware(struct rtl8169_private *tp)
2544 {
2545         if (tp->rtl_fw) {
2546                 release_firmware(tp->rtl_fw->fw);
2547                 kfree(tp->rtl_fw);
2548                 tp->rtl_fw = NULL;
2549         }
2550 }
2551
2552 static void rtl_apply_firmware(struct rtl8169_private *tp)
2553 {
2554         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2555         if (tp->rtl_fw)
2556                 rtl_phy_write_fw(tp, tp->rtl_fw);
2557 }
2558
2559 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2560 {
2561         if (rtl_readphy(tp, reg) != val)
2562                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2563         else
2564                 rtl_apply_firmware(tp);
2565 }
2566
2567 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2568 {
2569         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2570 }
2571
2572 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2573 {
2574         struct phy_device *phydev = tp->phydev;
2575
2576         phy_write(phydev, 0x1f, 0x0007);
2577         phy_write(phydev, 0x1e, 0x0020);
2578         phy_set_bits(phydev, 0x15, BIT(8));
2579
2580         phy_write(phydev, 0x1f, 0x0005);
2581         phy_write(phydev, 0x05, 0x8b85);
2582         phy_set_bits(phydev, 0x06, BIT(13));
2583
2584         phy_write(phydev, 0x1f, 0x0000);
2585 }
2586
2587 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2588 {
2589         phy_write(tp->phydev, 0x1f, 0x0a43);
2590         phy_set_bits(tp->phydev, 0x11, BIT(4));
2591         phy_write(tp->phydev, 0x1f, 0x0000);
2592 }
2593
2594 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2595 {
2596         static const struct phy_reg phy_reg_init[] = {
2597                 { 0x1f, 0x0001 },
2598                 { 0x06, 0x006e },
2599                 { 0x08, 0x0708 },
2600                 { 0x15, 0x4000 },
2601                 { 0x18, 0x65c7 },
2602
2603                 { 0x1f, 0x0001 },
2604                 { 0x03, 0x00a1 },
2605                 { 0x02, 0x0008 },
2606                 { 0x01, 0x0120 },
2607                 { 0x00, 0x1000 },
2608                 { 0x04, 0x0800 },
2609                 { 0x04, 0x0000 },
2610
2611                 { 0x03, 0xff41 },
2612                 { 0x02, 0xdf60 },
2613                 { 0x01, 0x0140 },
2614                 { 0x00, 0x0077 },
2615                 { 0x04, 0x7800 },
2616                 { 0x04, 0x7000 },
2617
2618                 { 0x03, 0x802f },
2619                 { 0x02, 0x4f02 },
2620                 { 0x01, 0x0409 },
2621                 { 0x00, 0xf0f9 },
2622                 { 0x04, 0x9800 },
2623                 { 0x04, 0x9000 },
2624
2625                 { 0x03, 0xdf01 },
2626                 { 0x02, 0xdf20 },
2627                 { 0x01, 0xff95 },
2628                 { 0x00, 0xba00 },
2629                 { 0x04, 0xa800 },
2630                 { 0x04, 0xa000 },
2631
2632                 { 0x03, 0xff41 },
2633                 { 0x02, 0xdf20 },
2634                 { 0x01, 0x0140 },
2635                 { 0x00, 0x00bb },
2636                 { 0x04, 0xb800 },
2637                 { 0x04, 0xb000 },
2638
2639                 { 0x03, 0xdf41 },
2640                 { 0x02, 0xdc60 },
2641                 { 0x01, 0x6340 },
2642                 { 0x00, 0x007d },
2643                 { 0x04, 0xd800 },
2644                 { 0x04, 0xd000 },
2645
2646                 { 0x03, 0xdf01 },
2647                 { 0x02, 0xdf20 },
2648                 { 0x01, 0x100a },
2649                 { 0x00, 0xa0ff },
2650                 { 0x04, 0xf800 },
2651                 { 0x04, 0xf000 },
2652
2653                 { 0x1f, 0x0000 },
2654                 { 0x0b, 0x0000 },
2655                 { 0x00, 0x9200 }
2656         };
2657
2658         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2659 }
2660
2661 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2662 {
2663         static const struct phy_reg phy_reg_init[] = {
2664                 { 0x1f, 0x0002 },
2665                 { 0x01, 0x90d0 },
2666                 { 0x1f, 0x0000 }
2667         };
2668
2669         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2670 }
2671
2672 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2673 {
2674         struct pci_dev *pdev = tp->pci_dev;
2675
2676         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2677             (pdev->subsystem_device != 0xe000))
2678                 return;
2679
2680         rtl_writephy(tp, 0x1f, 0x0001);
2681         rtl_writephy(tp, 0x10, 0xf01b);
2682         rtl_writephy(tp, 0x1f, 0x0000);
2683 }
2684
2685 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2686 {
2687         static const struct phy_reg phy_reg_init[] = {
2688                 { 0x1f, 0x0001 },
2689                 { 0x04, 0x0000 },
2690                 { 0x03, 0x00a1 },
2691                 { 0x02, 0x0008 },
2692                 { 0x01, 0x0120 },
2693                 { 0x00, 0x1000 },
2694                 { 0x04, 0x0800 },
2695                 { 0x04, 0x9000 },
2696                 { 0x03, 0x802f },
2697                 { 0x02, 0x4f02 },
2698                 { 0x01, 0x0409 },
2699                 { 0x00, 0xf099 },
2700                 { 0x04, 0x9800 },
2701                 { 0x04, 0xa000 },
2702                 { 0x03, 0xdf01 },
2703                 { 0x02, 0xdf20 },
2704                 { 0x01, 0xff95 },
2705                 { 0x00, 0xba00 },
2706                 { 0x04, 0xa800 },
2707                 { 0x04, 0xf000 },
2708                 { 0x03, 0xdf01 },
2709                 { 0x02, 0xdf20 },
2710                 { 0x01, 0x101a },
2711                 { 0x00, 0xa0ff },
2712                 { 0x04, 0xf800 },
2713                 { 0x04, 0x0000 },
2714                 { 0x1f, 0x0000 },
2715
2716                 { 0x1f, 0x0001 },
2717                 { 0x10, 0xf41b },
2718                 { 0x14, 0xfb54 },
2719                 { 0x18, 0xf5c7 },
2720                 { 0x1f, 0x0000 },
2721
2722                 { 0x1f, 0x0001 },
2723                 { 0x17, 0x0cc0 },
2724                 { 0x1f, 0x0000 }
2725         };
2726
2727         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2728
2729         rtl8169scd_hw_phy_config_quirk(tp);
2730 }
2731
2732 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2733 {
2734         static const struct phy_reg phy_reg_init[] = {
2735                 { 0x1f, 0x0001 },
2736                 { 0x04, 0x0000 },
2737                 { 0x03, 0x00a1 },
2738                 { 0x02, 0x0008 },
2739                 { 0x01, 0x0120 },
2740                 { 0x00, 0x1000 },
2741                 { 0x04, 0x0800 },
2742                 { 0x04, 0x9000 },
2743                 { 0x03, 0x802f },
2744                 { 0x02, 0x4f02 },
2745                 { 0x01, 0x0409 },
2746                 { 0x00, 0xf099 },
2747                 { 0x04, 0x9800 },
2748                 { 0x04, 0xa000 },
2749                 { 0x03, 0xdf01 },
2750                 { 0x02, 0xdf20 },
2751                 { 0x01, 0xff95 },
2752                 { 0x00, 0xba00 },
2753                 { 0x04, 0xa800 },
2754                 { 0x04, 0xf000 },
2755                 { 0x03, 0xdf01 },
2756                 { 0x02, 0xdf20 },
2757                 { 0x01, 0x101a },
2758                 { 0x00, 0xa0ff },
2759                 { 0x04, 0xf800 },
2760                 { 0x04, 0x0000 },
2761                 { 0x1f, 0x0000 },
2762
2763                 { 0x1f, 0x0001 },
2764                 { 0x0b, 0x8480 },
2765                 { 0x1f, 0x0000 },
2766
2767                 { 0x1f, 0x0001 },
2768                 { 0x18, 0x67c7 },
2769                 { 0x04, 0x2000 },
2770                 { 0x03, 0x002f },
2771                 { 0x02, 0x4360 },
2772                 { 0x01, 0x0109 },
2773                 { 0x00, 0x3022 },
2774                 { 0x04, 0x2800 },
2775                 { 0x1f, 0x0000 },
2776
2777                 { 0x1f, 0x0001 },
2778                 { 0x17, 0x0cc0 },
2779                 { 0x1f, 0x0000 }
2780         };
2781
2782         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2783 }
2784
2785 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2786 {
2787         static const struct phy_reg phy_reg_init[] = {
2788                 { 0x10, 0xf41b },
2789                 { 0x1f, 0x0000 }
2790         };
2791
2792         rtl_writephy(tp, 0x1f, 0x0001);
2793         rtl_patchphy(tp, 0x16, 1 << 0);
2794
2795         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2796 }
2797
2798 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2799 {
2800         static const struct phy_reg phy_reg_init[] = {
2801                 { 0x1f, 0x0001 },
2802                 { 0x10, 0xf41b },
2803                 { 0x1f, 0x0000 }
2804         };
2805
2806         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2807 }
2808
2809 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2810 {
2811         static const struct phy_reg phy_reg_init[] = {
2812                 { 0x1f, 0x0000 },
2813                 { 0x1d, 0x0f00 },
2814                 { 0x1f, 0x0002 },
2815                 { 0x0c, 0x1ec8 },
2816                 { 0x1f, 0x0000 }
2817         };
2818
2819         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2820 }
2821
2822 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2823 {
2824         static const struct phy_reg phy_reg_init[] = {
2825                 { 0x1f, 0x0001 },
2826                 { 0x1d, 0x3d98 },
2827                 { 0x1f, 0x0000 }
2828         };
2829
2830         rtl_writephy(tp, 0x1f, 0x0000);
2831         rtl_patchphy(tp, 0x14, 1 << 5);
2832         rtl_patchphy(tp, 0x0d, 1 << 5);
2833
2834         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2835 }
2836
2837 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2838 {
2839         static const struct phy_reg phy_reg_init[] = {
2840                 { 0x1f, 0x0001 },
2841                 { 0x12, 0x2300 },
2842                 { 0x1f, 0x0002 },
2843                 { 0x00, 0x88d4 },
2844                 { 0x01, 0x82b1 },
2845                 { 0x03, 0x7002 },
2846                 { 0x08, 0x9e30 },
2847                 { 0x09, 0x01f0 },
2848                 { 0x0a, 0x5500 },
2849                 { 0x0c, 0x00c8 },
2850                 { 0x1f, 0x0003 },
2851                 { 0x12, 0xc096 },
2852                 { 0x16, 0x000a },
2853                 { 0x1f, 0x0000 },
2854                 { 0x1f, 0x0000 },
2855                 { 0x09, 0x2000 },
2856                 { 0x09, 0x0000 }
2857         };
2858
2859         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2860
2861         rtl_patchphy(tp, 0x14, 1 << 5);
2862         rtl_patchphy(tp, 0x0d, 1 << 5);
2863         rtl_writephy(tp, 0x1f, 0x0000);
2864 }
2865
2866 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2867 {
2868         static const struct phy_reg phy_reg_init[] = {
2869                 { 0x1f, 0x0001 },
2870                 { 0x12, 0x2300 },
2871                 { 0x03, 0x802f },
2872                 { 0x02, 0x4f02 },
2873                 { 0x01, 0x0409 },
2874                 { 0x00, 0xf099 },
2875                 { 0x04, 0x9800 },
2876                 { 0x04, 0x9000 },
2877                 { 0x1d, 0x3d98 },
2878                 { 0x1f, 0x0002 },
2879                 { 0x0c, 0x7eb8 },
2880                 { 0x06, 0x0761 },
2881                 { 0x1f, 0x0003 },
2882                 { 0x16, 0x0f0a },
2883                 { 0x1f, 0x0000 }
2884         };
2885
2886         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2887
2888         rtl_patchphy(tp, 0x16, 1 << 0);
2889         rtl_patchphy(tp, 0x14, 1 << 5);
2890         rtl_patchphy(tp, 0x0d, 1 << 5);
2891         rtl_writephy(tp, 0x1f, 0x0000);
2892 }
2893
2894 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2895 {
2896         static const struct phy_reg phy_reg_init[] = {
2897                 { 0x1f, 0x0001 },
2898                 { 0x12, 0x2300 },
2899                 { 0x1d, 0x3d98 },
2900                 { 0x1f, 0x0002 },
2901                 { 0x0c, 0x7eb8 },
2902                 { 0x06, 0x5461 },
2903                 { 0x1f, 0x0003 },
2904                 { 0x16, 0x0f0a },
2905                 { 0x1f, 0x0000 }
2906         };
2907
2908         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2909
2910         rtl_patchphy(tp, 0x16, 1 << 0);
2911         rtl_patchphy(tp, 0x14, 1 << 5);
2912         rtl_patchphy(tp, 0x0d, 1 << 5);
2913         rtl_writephy(tp, 0x1f, 0x0000);
2914 }
2915
2916 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2917 {
2918         rtl8168c_3_hw_phy_config(tp);
2919 }
2920
2921 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2922 {
2923         static const struct phy_reg phy_reg_init_0[] = {
2924                 /* Channel Estimation */
2925                 { 0x1f, 0x0001 },
2926                 { 0x06, 0x4064 },
2927                 { 0x07, 0x2863 },
2928                 { 0x08, 0x059c },
2929                 { 0x09, 0x26b4 },
2930                 { 0x0a, 0x6a19 },
2931                 { 0x0b, 0xdcc8 },
2932                 { 0x10, 0xf06d },
2933                 { 0x14, 0x7f68 },
2934                 { 0x18, 0x7fd9 },
2935                 { 0x1c, 0xf0ff },
2936                 { 0x1d, 0x3d9c },
2937                 { 0x1f, 0x0003 },
2938                 { 0x12, 0xf49f },
2939                 { 0x13, 0x070b },
2940                 { 0x1a, 0x05ad },
2941                 { 0x14, 0x94c0 },
2942
2943                 /*
2944                  * Tx Error Issue
2945                  * Enhance line driver power
2946                  */
2947                 { 0x1f, 0x0002 },
2948                 { 0x06, 0x5561 },
2949                 { 0x1f, 0x0005 },
2950                 { 0x05, 0x8332 },
2951                 { 0x06, 0x5561 },
2952
2953                 /*
2954                  * Can not link to 1Gbps with bad cable
2955                  * Decrease SNR threshold form 21.07dB to 19.04dB
2956                  */
2957                 { 0x1f, 0x0001 },
2958                 { 0x17, 0x0cc0 },
2959
2960                 { 0x1f, 0x0000 },
2961                 { 0x0d, 0xf880 }
2962         };
2963
2964         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2965
2966         /*
2967          * Rx Error Issue
2968          * Fine Tune Switching regulator parameter
2969          */
2970         rtl_writephy(tp, 0x1f, 0x0002);
2971         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2972         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2973
2974         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2975                 static const struct phy_reg phy_reg_init[] = {
2976                         { 0x1f, 0x0002 },
2977                         { 0x05, 0x669a },
2978                         { 0x1f, 0x0005 },
2979                         { 0x05, 0x8330 },
2980                         { 0x06, 0x669a },
2981                         { 0x1f, 0x0002 }
2982                 };
2983                 int val;
2984
2985                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2986
2987                 val = rtl_readphy(tp, 0x0d);
2988
2989                 if ((val & 0x00ff) != 0x006c) {
2990                         static const u32 set[] = {
2991                                 0x0065, 0x0066, 0x0067, 0x0068,
2992                                 0x0069, 0x006a, 0x006b, 0x006c
2993                         };
2994                         int i;
2995
2996                         rtl_writephy(tp, 0x1f, 0x0002);
2997
2998                         val &= 0xff00;
2999                         for (i = 0; i < ARRAY_SIZE(set); i++)
3000                                 rtl_writephy(tp, 0x0d, val | set[i]);
3001                 }
3002         } else {
3003                 static const struct phy_reg phy_reg_init[] = {
3004                         { 0x1f, 0x0002 },
3005                         { 0x05, 0x6662 },
3006                         { 0x1f, 0x0005 },
3007                         { 0x05, 0x8330 },
3008                         { 0x06, 0x6662 }
3009                 };
3010
3011                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3012         }
3013
3014         /* RSET couple improve */
3015         rtl_writephy(tp, 0x1f, 0x0002);
3016         rtl_patchphy(tp, 0x0d, 0x0300);
3017         rtl_patchphy(tp, 0x0f, 0x0010);
3018
3019         /* Fine tune PLL performance */
3020         rtl_writephy(tp, 0x1f, 0x0002);
3021         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3022         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3023
3024         rtl_writephy(tp, 0x1f, 0x0005);
3025         rtl_writephy(tp, 0x05, 0x001b);
3026
3027         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3028
3029         rtl_writephy(tp, 0x1f, 0x0000);
3030 }
3031
3032 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3033 {
3034         static const struct phy_reg phy_reg_init_0[] = {
3035                 /* Channel Estimation */
3036                 { 0x1f, 0x0001 },
3037                 { 0x06, 0x4064 },
3038                 { 0x07, 0x2863 },
3039                 { 0x08, 0x059c },
3040                 { 0x09, 0x26b4 },
3041                 { 0x0a, 0x6a19 },
3042                 { 0x0b, 0xdcc8 },
3043                 { 0x10, 0xf06d },
3044                 { 0x14, 0x7f68 },
3045                 { 0x18, 0x7fd9 },
3046                 { 0x1c, 0xf0ff },
3047                 { 0x1d, 0x3d9c },
3048                 { 0x1f, 0x0003 },
3049                 { 0x12, 0xf49f },
3050                 { 0x13, 0x070b },
3051                 { 0x1a, 0x05ad },
3052                 { 0x14, 0x94c0 },
3053
3054                 /*
3055                  * Tx Error Issue
3056                  * Enhance line driver power
3057                  */
3058                 { 0x1f, 0x0002 },
3059                 { 0x06, 0x5561 },
3060                 { 0x1f, 0x0005 },
3061                 { 0x05, 0x8332 },
3062                 { 0x06, 0x5561 },
3063
3064                 /*
3065                  * Can not link to 1Gbps with bad cable
3066                  * Decrease SNR threshold form 21.07dB to 19.04dB
3067                  */
3068                 { 0x1f, 0x0001 },
3069                 { 0x17, 0x0cc0 },
3070
3071                 { 0x1f, 0x0000 },
3072                 { 0x0d, 0xf880 }
3073         };
3074
3075         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3076
3077         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3078                 static const struct phy_reg phy_reg_init[] = {
3079                         { 0x1f, 0x0002 },
3080                         { 0x05, 0x669a },
3081                         { 0x1f, 0x0005 },
3082                         { 0x05, 0x8330 },
3083                         { 0x06, 0x669a },
3084
3085                         { 0x1f, 0x0002 }
3086                 };
3087                 int val;
3088
3089                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3090
3091                 val = rtl_readphy(tp, 0x0d);
3092                 if ((val & 0x00ff) != 0x006c) {
3093                         static const u32 set[] = {
3094                                 0x0065, 0x0066, 0x0067, 0x0068,
3095                                 0x0069, 0x006a, 0x006b, 0x006c
3096                         };
3097                         int i;
3098
3099                         rtl_writephy(tp, 0x1f, 0x0002);
3100
3101                         val &= 0xff00;
3102                         for (i = 0; i < ARRAY_SIZE(set); i++)
3103                                 rtl_writephy(tp, 0x0d, val | set[i]);
3104                 }
3105         } else {
3106                 static const struct phy_reg phy_reg_init[] = {
3107                         { 0x1f, 0x0002 },
3108                         { 0x05, 0x2642 },
3109                         { 0x1f, 0x0005 },
3110                         { 0x05, 0x8330 },
3111                         { 0x06, 0x2642 }
3112                 };
3113
3114                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3115         }
3116
3117         /* Fine tune PLL performance */
3118         rtl_writephy(tp, 0x1f, 0x0002);
3119         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3120         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3121
3122         /* Switching regulator Slew rate */
3123         rtl_writephy(tp, 0x1f, 0x0002);
3124         rtl_patchphy(tp, 0x0f, 0x0017);
3125
3126         rtl_writephy(tp, 0x1f, 0x0005);
3127         rtl_writephy(tp, 0x05, 0x001b);
3128
3129         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3130
3131         rtl_writephy(tp, 0x1f, 0x0000);
3132 }
3133
3134 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3135 {
3136         static const struct phy_reg phy_reg_init[] = {
3137                 { 0x1f, 0x0002 },
3138                 { 0x10, 0x0008 },
3139                 { 0x0d, 0x006c },
3140
3141                 { 0x1f, 0x0000 },
3142                 { 0x0d, 0xf880 },
3143
3144                 { 0x1f, 0x0001 },
3145                 { 0x17, 0x0cc0 },
3146
3147                 { 0x1f, 0x0001 },
3148                 { 0x0b, 0xa4d8 },
3149                 { 0x09, 0x281c },
3150                 { 0x07, 0x2883 },
3151                 { 0x0a, 0x6b35 },
3152                 { 0x1d, 0x3da4 },
3153                 { 0x1c, 0xeffd },
3154                 { 0x14, 0x7f52 },
3155                 { 0x18, 0x7fc6 },
3156                 { 0x08, 0x0601 },
3157                 { 0x06, 0x4063 },
3158                 { 0x10, 0xf074 },
3159                 { 0x1f, 0x0003 },
3160                 { 0x13, 0x0789 },
3161                 { 0x12, 0xf4bd },
3162                 { 0x1a, 0x04fd },
3163                 { 0x14, 0x84b0 },
3164                 { 0x1f, 0x0000 },
3165                 { 0x00, 0x9200 },
3166
3167                 { 0x1f, 0x0005 },
3168                 { 0x01, 0x0340 },
3169                 { 0x1f, 0x0001 },
3170                 { 0x04, 0x4000 },
3171                 { 0x03, 0x1d21 },
3172                 { 0x02, 0x0c32 },
3173                 { 0x01, 0x0200 },
3174                 { 0x00, 0x5554 },
3175                 { 0x04, 0x4800 },
3176                 { 0x04, 0x4000 },
3177                 { 0x04, 0xf000 },
3178                 { 0x03, 0xdf01 },
3179                 { 0x02, 0xdf20 },
3180                 { 0x01, 0x101a },
3181                 { 0x00, 0xa0ff },
3182                 { 0x04, 0xf800 },
3183                 { 0x04, 0xf000 },
3184                 { 0x1f, 0x0000 },
3185
3186                 { 0x1f, 0x0007 },
3187                 { 0x1e, 0x0023 },
3188                 { 0x16, 0x0000 },
3189                 { 0x1f, 0x0000 }
3190         };
3191
3192         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3193 }
3194
3195 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3196 {
3197         static const struct phy_reg phy_reg_init[] = {
3198                 { 0x1f, 0x0001 },
3199                 { 0x17, 0x0cc0 },
3200
3201                 { 0x1f, 0x0007 },
3202                 { 0x1e, 0x002d },
3203                 { 0x18, 0x0040 },
3204                 { 0x1f, 0x0000 }
3205         };
3206
3207         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3208         rtl_patchphy(tp, 0x0d, 1 << 5);
3209 }
3210
3211 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3212 {
3213         static const struct phy_reg phy_reg_init[] = {
3214                 /* Enable Delay cap */
3215                 { 0x1f, 0x0005 },
3216                 { 0x05, 0x8b80 },
3217                 { 0x06, 0xc896 },
3218                 { 0x1f, 0x0000 },
3219
3220                 /* Channel estimation fine tune */
3221                 { 0x1f, 0x0001 },
3222                 { 0x0b, 0x6c20 },
3223                 { 0x07, 0x2872 },
3224                 { 0x1c, 0xefff },
3225                 { 0x1f, 0x0003 },
3226                 { 0x14, 0x6420 },
3227                 { 0x1f, 0x0000 },
3228
3229                 /* Update PFM & 10M TX idle timer */
3230                 { 0x1f, 0x0007 },
3231                 { 0x1e, 0x002f },
3232                 { 0x15, 0x1919 },
3233                 { 0x1f, 0x0000 },
3234
3235                 { 0x1f, 0x0007 },
3236                 { 0x1e, 0x00ac },
3237                 { 0x18, 0x0006 },
3238                 { 0x1f, 0x0000 }
3239         };
3240
3241         rtl_apply_firmware(tp);
3242
3243         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3244
3245         /* DCO enable for 10M IDLE Power */
3246         rtl_writephy(tp, 0x1f, 0x0007);
3247         rtl_writephy(tp, 0x1e, 0x0023);
3248         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3249         rtl_writephy(tp, 0x1f, 0x0000);
3250
3251         /* For impedance matching */
3252         rtl_writephy(tp, 0x1f, 0x0002);
3253         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3254         rtl_writephy(tp, 0x1f, 0x0000);
3255
3256         /* PHY auto speed down */
3257         rtl_writephy(tp, 0x1f, 0x0007);
3258         rtl_writephy(tp, 0x1e, 0x002d);
3259         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3260         rtl_writephy(tp, 0x1f, 0x0000);
3261         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3262
3263         rtl_writephy(tp, 0x1f, 0x0005);
3264         rtl_writephy(tp, 0x05, 0x8b86);
3265         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3266         rtl_writephy(tp, 0x1f, 0x0000);
3267
3268         rtl_writephy(tp, 0x1f, 0x0005);
3269         rtl_writephy(tp, 0x05, 0x8b85);
3270         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3271         rtl_writephy(tp, 0x1f, 0x0007);
3272         rtl_writephy(tp, 0x1e, 0x0020);
3273         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3274         rtl_writephy(tp, 0x1f, 0x0006);
3275         rtl_writephy(tp, 0x00, 0x5a00);
3276         rtl_writephy(tp, 0x1f, 0x0000);
3277         rtl_writephy(tp, 0x0d, 0x0007);
3278         rtl_writephy(tp, 0x0e, 0x003c);
3279         rtl_writephy(tp, 0x0d, 0x4007);
3280         rtl_writephy(tp, 0x0e, 0x0000);
3281         rtl_writephy(tp, 0x0d, 0x0000);
3282 }
3283
3284 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3285 {
3286         const u16 w[] = {
3287                 addr[0] | (addr[1] << 8),
3288                 addr[2] | (addr[3] << 8),
3289                 addr[4] | (addr[5] << 8)
3290         };
3291         const struct exgmac_reg e[] = {
3292                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3293                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3294                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3295                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3296         };
3297
3298         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3299 }
3300
3301 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3302 {
3303         static const struct phy_reg phy_reg_init[] = {
3304                 /* Enable Delay cap */
3305                 { 0x1f, 0x0004 },
3306                 { 0x1f, 0x0007 },
3307                 { 0x1e, 0x00ac },
3308                 { 0x18, 0x0006 },
3309                 { 0x1f, 0x0002 },
3310                 { 0x1f, 0x0000 },
3311                 { 0x1f, 0x0000 },
3312
3313                 /* Channel estimation fine tune */
3314                 { 0x1f, 0x0003 },
3315                 { 0x09, 0xa20f },
3316                 { 0x1f, 0x0000 },
3317                 { 0x1f, 0x0000 },
3318
3319                 /* Green Setting */
3320                 { 0x1f, 0x0005 },
3321                 { 0x05, 0x8b5b },
3322                 { 0x06, 0x9222 },
3323                 { 0x05, 0x8b6d },
3324                 { 0x06, 0x8000 },
3325                 { 0x05, 0x8b76 },
3326                 { 0x06, 0x8000 },
3327                 { 0x1f, 0x0000 }
3328         };
3329
3330         rtl_apply_firmware(tp);
3331
3332         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3333
3334         /* For 4-corner performance improve */
3335         rtl_writephy(tp, 0x1f, 0x0005);
3336         rtl_writephy(tp, 0x05, 0x8b80);
3337         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3338         rtl_writephy(tp, 0x1f, 0x0000);
3339
3340         /* PHY auto speed down */
3341         rtl_writephy(tp, 0x1f, 0x0004);
3342         rtl_writephy(tp, 0x1f, 0x0007);
3343         rtl_writephy(tp, 0x1e, 0x002d);
3344         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3345         rtl_writephy(tp, 0x1f, 0x0002);
3346         rtl_writephy(tp, 0x1f, 0x0000);
3347         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3348
3349         /* improve 10M EEE waveform */
3350         rtl_writephy(tp, 0x1f, 0x0005);
3351         rtl_writephy(tp, 0x05, 0x8b86);
3352         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3353         rtl_writephy(tp, 0x1f, 0x0000);
3354
3355         /* Improve 2-pair detection performance */
3356         rtl_writephy(tp, 0x1f, 0x0005);
3357         rtl_writephy(tp, 0x05, 0x8b85);
3358         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3359         rtl_writephy(tp, 0x1f, 0x0000);
3360
3361         rtl8168f_config_eee_phy(tp);
3362         rtl_enable_eee(tp);
3363
3364         /* Green feature */
3365         rtl_writephy(tp, 0x1f, 0x0003);
3366         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3367         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3368         rtl_writephy(tp, 0x1f, 0x0000);
3369         rtl_writephy(tp, 0x1f, 0x0005);
3370         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3371         rtl_writephy(tp, 0x1f, 0x0000);
3372
3373         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3374         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3375 }
3376
3377 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3378 {
3379         /* For 4-corner performance improve */
3380         rtl_writephy(tp, 0x1f, 0x0005);
3381         rtl_writephy(tp, 0x05, 0x8b80);
3382         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3383         rtl_writephy(tp, 0x1f, 0x0000);
3384
3385         /* PHY auto speed down */
3386         rtl_writephy(tp, 0x1f, 0x0007);
3387         rtl_writephy(tp, 0x1e, 0x002d);
3388         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3389         rtl_writephy(tp, 0x1f, 0x0000);
3390         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3391
3392         /* Improve 10M EEE waveform */
3393         rtl_writephy(tp, 0x1f, 0x0005);
3394         rtl_writephy(tp, 0x05, 0x8b86);
3395         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3396         rtl_writephy(tp, 0x1f, 0x0000);
3397
3398         rtl8168f_config_eee_phy(tp);
3399         rtl_enable_eee(tp);
3400 }
3401
3402 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3403 {
3404         static const struct phy_reg phy_reg_init[] = {
3405                 /* Channel estimation fine tune */
3406                 { 0x1f, 0x0003 },
3407                 { 0x09, 0xa20f },
3408                 { 0x1f, 0x0000 },
3409
3410                 /* Modify green table for giga & fnet */
3411                 { 0x1f, 0x0005 },
3412                 { 0x05, 0x8b55 },
3413                 { 0x06, 0x0000 },
3414                 { 0x05, 0x8b5e },
3415                 { 0x06, 0x0000 },
3416                 { 0x05, 0x8b67 },
3417                 { 0x06, 0x0000 },
3418                 { 0x05, 0x8b70 },
3419                 { 0x06, 0x0000 },
3420                 { 0x1f, 0x0000 },
3421                 { 0x1f, 0x0007 },
3422                 { 0x1e, 0x0078 },
3423                 { 0x17, 0x0000 },
3424                 { 0x19, 0x00fb },
3425                 { 0x1f, 0x0000 },
3426
3427                 /* Modify green table for 10M */
3428                 { 0x1f, 0x0005 },
3429                 { 0x05, 0x8b79 },
3430                 { 0x06, 0xaa00 },
3431                 { 0x1f, 0x0000 },
3432
3433                 /* Disable hiimpedance detection (RTCT) */
3434                 { 0x1f, 0x0003 },
3435                 { 0x01, 0x328a },
3436                 { 0x1f, 0x0000 }
3437         };
3438
3439         rtl_apply_firmware(tp);
3440
3441         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3442
3443         rtl8168f_hw_phy_config(tp);
3444
3445         /* Improve 2-pair detection performance */
3446         rtl_writephy(tp, 0x1f, 0x0005);
3447         rtl_writephy(tp, 0x05, 0x8b85);
3448         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3449         rtl_writephy(tp, 0x1f, 0x0000);
3450 }
3451
3452 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3453 {
3454         rtl_apply_firmware(tp);
3455
3456         rtl8168f_hw_phy_config(tp);
3457 }
3458
3459 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3460 {
3461         static const struct phy_reg phy_reg_init[] = {
3462                 /* Channel estimation fine tune */
3463                 { 0x1f, 0x0003 },
3464                 { 0x09, 0xa20f },
3465                 { 0x1f, 0x0000 },
3466
3467                 /* Modify green table for giga & fnet */
3468                 { 0x1f, 0x0005 },
3469                 { 0x05, 0x8b55 },
3470                 { 0x06, 0x0000 },
3471                 { 0x05, 0x8b5e },
3472                 { 0x06, 0x0000 },
3473                 { 0x05, 0x8b67 },
3474                 { 0x06, 0x0000 },
3475                 { 0x05, 0x8b70 },
3476                 { 0x06, 0x0000 },
3477                 { 0x1f, 0x0000 },
3478                 { 0x1f, 0x0007 },
3479                 { 0x1e, 0x0078 },
3480                 { 0x17, 0x0000 },
3481                 { 0x19, 0x00aa },
3482                 { 0x1f, 0x0000 },
3483
3484                 /* Modify green table for 10M */
3485                 { 0x1f, 0x0005 },
3486                 { 0x05, 0x8b79 },
3487                 { 0x06, 0xaa00 },
3488                 { 0x1f, 0x0000 },
3489
3490                 /* Disable hiimpedance detection (RTCT) */
3491                 { 0x1f, 0x0003 },
3492                 { 0x01, 0x328a },
3493                 { 0x1f, 0x0000 }
3494         };
3495
3496
3497         rtl_apply_firmware(tp);
3498
3499         rtl8168f_hw_phy_config(tp);
3500
3501         /* Improve 2-pair detection performance */
3502         rtl_writephy(tp, 0x1f, 0x0005);
3503         rtl_writephy(tp, 0x05, 0x8b85);
3504         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3505         rtl_writephy(tp, 0x1f, 0x0000);
3506
3507         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3508
3509         /* Modify green table for giga */
3510         rtl_writephy(tp, 0x1f, 0x0005);
3511         rtl_writephy(tp, 0x05, 0x8b54);
3512         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3513         rtl_writephy(tp, 0x05, 0x8b5d);
3514         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3515         rtl_writephy(tp, 0x05, 0x8a7c);
3516         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3517         rtl_writephy(tp, 0x05, 0x8a7f);
3518         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3519         rtl_writephy(tp, 0x05, 0x8a82);
3520         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3521         rtl_writephy(tp, 0x05, 0x8a85);
3522         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3523         rtl_writephy(tp, 0x05, 0x8a88);
3524         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3525         rtl_writephy(tp, 0x1f, 0x0000);
3526
3527         /* uc same-seed solution */
3528         rtl_writephy(tp, 0x1f, 0x0005);
3529         rtl_writephy(tp, 0x05, 0x8b85);
3530         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3531         rtl_writephy(tp, 0x1f, 0x0000);
3532
3533         /* Green feature */
3534         rtl_writephy(tp, 0x1f, 0x0003);
3535         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3536         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3537         rtl_writephy(tp, 0x1f, 0x0000);
3538 }
3539
3540 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3541 {
3542         phy_write(tp->phydev, 0x1f, 0x0a43);
3543         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3544 }
3545
3546 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3547 {
3548         struct phy_device *phydev = tp->phydev;
3549
3550         phy_write(phydev, 0x1f, 0x0bcc);
3551         phy_clear_bits(phydev, 0x14, BIT(8));
3552
3553         phy_write(phydev, 0x1f, 0x0a44);
3554         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3555
3556         phy_write(phydev, 0x1f, 0x0a43);
3557         phy_write(phydev, 0x13, 0x8084);
3558         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3559         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3560
3561         phy_write(phydev, 0x1f, 0x0000);
3562 }
3563
3564 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3565 {
3566         rtl_apply_firmware(tp);
3567
3568         rtl_writephy(tp, 0x1f, 0x0a46);
3569         if (rtl_readphy(tp, 0x10) & 0x0100) {
3570                 rtl_writephy(tp, 0x1f, 0x0bcc);
3571                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3572         } else {
3573                 rtl_writephy(tp, 0x1f, 0x0bcc);
3574                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3575         }
3576
3577         rtl_writephy(tp, 0x1f, 0x0a46);
3578         if (rtl_readphy(tp, 0x13) & 0x0100) {
3579                 rtl_writephy(tp, 0x1f, 0x0c41);
3580                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3581         } else {
3582                 rtl_writephy(tp, 0x1f, 0x0c41);
3583                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3584         }
3585
3586         /* Enable PHY auto speed down */
3587         rtl_writephy(tp, 0x1f, 0x0a44);
3588         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3589
3590         rtl8168g_phy_adjust_10m_aldps(tp);
3591
3592         /* EEE auto-fallback function */
3593         rtl_writephy(tp, 0x1f, 0x0a4b);
3594         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3595
3596         /* Enable UC LPF tune function */
3597         rtl_writephy(tp, 0x1f, 0x0a43);
3598         rtl_writephy(tp, 0x13, 0x8012);
3599         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3600
3601         rtl_writephy(tp, 0x1f, 0x0c42);
3602         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3603
3604         /* Improve SWR Efficiency */
3605         rtl_writephy(tp, 0x1f, 0x0bcd);
3606         rtl_writephy(tp, 0x14, 0x5065);
3607         rtl_writephy(tp, 0x14, 0xd065);
3608         rtl_writephy(tp, 0x1f, 0x0bc8);
3609         rtl_writephy(tp, 0x11, 0x5655);
3610         rtl_writephy(tp, 0x1f, 0x0bcd);
3611         rtl_writephy(tp, 0x14, 0x1065);
3612         rtl_writephy(tp, 0x14, 0x9065);
3613         rtl_writephy(tp, 0x14, 0x1065);
3614
3615         rtl8168g_disable_aldps(tp);
3616         rtl8168g_config_eee_phy(tp);
3617         rtl_enable_eee(tp);
3618 }
3619
3620 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3621 {
3622         rtl_apply_firmware(tp);
3623         rtl8168g_config_eee_phy(tp);
3624         rtl_enable_eee(tp);
3625 }
3626
3627 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3628 {
3629         u16 dout_tapbin;
3630         u32 data;
3631
3632         rtl_apply_firmware(tp);
3633
3634         /* CHN EST parameters adjust - giga master */
3635         rtl_writephy(tp, 0x1f, 0x0a43);
3636         rtl_writephy(tp, 0x13, 0x809b);
3637         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3638         rtl_writephy(tp, 0x13, 0x80a2);
3639         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3640         rtl_writephy(tp, 0x13, 0x80a4);
3641         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3642         rtl_writephy(tp, 0x13, 0x809c);
3643         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3644         rtl_writephy(tp, 0x1f, 0x0000);
3645
3646         /* CHN EST parameters adjust - giga slave */
3647         rtl_writephy(tp, 0x1f, 0x0a43);
3648         rtl_writephy(tp, 0x13, 0x80ad);
3649         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3650         rtl_writephy(tp, 0x13, 0x80b4);
3651         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3652         rtl_writephy(tp, 0x13, 0x80ac);
3653         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3654         rtl_writephy(tp, 0x1f, 0x0000);
3655
3656         /* CHN EST parameters adjust - fnet */
3657         rtl_writephy(tp, 0x1f, 0x0a43);
3658         rtl_writephy(tp, 0x13, 0x808e);
3659         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3660         rtl_writephy(tp, 0x13, 0x8090);
3661         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3662         rtl_writephy(tp, 0x13, 0x8092);
3663         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3664         rtl_writephy(tp, 0x1f, 0x0000);
3665
3666         /* enable R-tune & PGA-retune function */
3667         dout_tapbin = 0;
3668         rtl_writephy(tp, 0x1f, 0x0a46);
3669         data = rtl_readphy(tp, 0x13);
3670         data &= 3;
3671         data <<= 2;
3672         dout_tapbin |= data;
3673         data = rtl_readphy(tp, 0x12);
3674         data &= 0xc000;
3675         data >>= 14;
3676         dout_tapbin |= data;
3677         dout_tapbin = ~(dout_tapbin^0x08);
3678         dout_tapbin <<= 12;
3679         dout_tapbin &= 0xf000;
3680         rtl_writephy(tp, 0x1f, 0x0a43);
3681         rtl_writephy(tp, 0x13, 0x827a);
3682         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3683         rtl_writephy(tp, 0x13, 0x827b);
3684         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3685         rtl_writephy(tp, 0x13, 0x827c);
3686         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3687         rtl_writephy(tp, 0x13, 0x827d);
3688         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3689
3690         rtl_writephy(tp, 0x1f, 0x0a43);
3691         rtl_writephy(tp, 0x13, 0x0811);
3692         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3693         rtl_writephy(tp, 0x1f, 0x0a42);
3694         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3695         rtl_writephy(tp, 0x1f, 0x0000);
3696
3697         /* enable GPHY 10M */
3698         rtl_writephy(tp, 0x1f, 0x0a44);
3699         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3700         rtl_writephy(tp, 0x1f, 0x0000);
3701
3702         /* SAR ADC performance */
3703         rtl_writephy(tp, 0x1f, 0x0bca);
3704         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3705         rtl_writephy(tp, 0x1f, 0x0000);
3706
3707         rtl_writephy(tp, 0x1f, 0x0a43);
3708         rtl_writephy(tp, 0x13, 0x803f);
3709         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3710         rtl_writephy(tp, 0x13, 0x8047);
3711         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3712         rtl_writephy(tp, 0x13, 0x804f);
3713         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3714         rtl_writephy(tp, 0x13, 0x8057);
3715         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3716         rtl_writephy(tp, 0x13, 0x805f);
3717         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3718         rtl_writephy(tp, 0x13, 0x8067);
3719         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3720         rtl_writephy(tp, 0x13, 0x806f);
3721         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3722         rtl_writephy(tp, 0x1f, 0x0000);
3723
3724         /* disable phy pfm mode */
3725         rtl_writephy(tp, 0x1f, 0x0a44);
3726         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3727         rtl_writephy(tp, 0x1f, 0x0000);
3728
3729         rtl8168g_disable_aldps(tp);
3730         rtl8168g_config_eee_phy(tp);
3731         rtl_enable_eee(tp);
3732 }
3733
3734 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3735 {
3736         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3737         u16 rlen;
3738         u32 data;
3739
3740         rtl_apply_firmware(tp);
3741
3742         /* CHIN EST parameter update */
3743         rtl_writephy(tp, 0x1f, 0x0a43);
3744         rtl_writephy(tp, 0x13, 0x808a);
3745         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3746         rtl_writephy(tp, 0x1f, 0x0000);
3747
3748         /* enable R-tune & PGA-retune function */
3749         rtl_writephy(tp, 0x1f, 0x0a43);
3750         rtl_writephy(tp, 0x13, 0x0811);
3751         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3752         rtl_writephy(tp, 0x1f, 0x0a42);
3753         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3754         rtl_writephy(tp, 0x1f, 0x0000);
3755
3756         /* enable GPHY 10M */
3757         rtl_writephy(tp, 0x1f, 0x0a44);
3758         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3759         rtl_writephy(tp, 0x1f, 0x0000);
3760
3761         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3762         data = r8168_mac_ocp_read(tp, 0xdd02);
3763         ioffset_p3 = ((data & 0x80)>>7);
3764         ioffset_p3 <<= 3;
3765
3766         data = r8168_mac_ocp_read(tp, 0xdd00);
3767         ioffset_p3 |= ((data & (0xe000))>>13);
3768         ioffset_p2 = ((data & (0x1e00))>>9);
3769         ioffset_p1 = ((data & (0x01e0))>>5);
3770         ioffset_p0 = ((data & 0x0010)>>4);
3771         ioffset_p0 <<= 3;
3772         ioffset_p0 |= (data & (0x07));
3773         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3774
3775         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3776             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3777                 rtl_writephy(tp, 0x1f, 0x0bcf);
3778                 rtl_writephy(tp, 0x16, data);
3779                 rtl_writephy(tp, 0x1f, 0x0000);
3780         }
3781
3782         /* Modify rlen (TX LPF corner frequency) level */
3783         rtl_writephy(tp, 0x1f, 0x0bcd);
3784         data = rtl_readphy(tp, 0x16);
3785         data &= 0x000f;
3786         rlen = 0;
3787         if (data > 3)
3788                 rlen = data - 3;
3789         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3790         rtl_writephy(tp, 0x17, data);
3791         rtl_writephy(tp, 0x1f, 0x0bcd);
3792         rtl_writephy(tp, 0x1f, 0x0000);
3793
3794         /* disable phy pfm mode */
3795         rtl_writephy(tp, 0x1f, 0x0a44);
3796         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3797         rtl_writephy(tp, 0x1f, 0x0000);
3798
3799         rtl8168g_disable_aldps(tp);
3800         rtl8168g_config_eee_phy(tp);
3801         rtl_enable_eee(tp);
3802 }
3803
3804 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3805 {
3806         /* Enable PHY auto speed down */
3807         rtl_writephy(tp, 0x1f, 0x0a44);
3808         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3809         rtl_writephy(tp, 0x1f, 0x0000);
3810
3811         rtl8168g_phy_adjust_10m_aldps(tp);
3812
3813         /* Enable EEE auto-fallback function */
3814         rtl_writephy(tp, 0x1f, 0x0a4b);
3815         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3816         rtl_writephy(tp, 0x1f, 0x0000);
3817
3818         /* Enable UC LPF tune function */
3819         rtl_writephy(tp, 0x1f, 0x0a43);
3820         rtl_writephy(tp, 0x13, 0x8012);
3821         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3822         rtl_writephy(tp, 0x1f, 0x0000);
3823
3824         /* set rg_sel_sdm_rate */
3825         rtl_writephy(tp, 0x1f, 0x0c42);
3826         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3827         rtl_writephy(tp, 0x1f, 0x0000);
3828
3829         rtl8168g_disable_aldps(tp);
3830         rtl8168g_config_eee_phy(tp);
3831         rtl_enable_eee(tp);
3832 }
3833
3834 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3835 {
3836         rtl8168g_phy_adjust_10m_aldps(tp);
3837
3838         /* Enable UC LPF tune function */
3839         rtl_writephy(tp, 0x1f, 0x0a43);
3840         rtl_writephy(tp, 0x13, 0x8012);
3841         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3842         rtl_writephy(tp, 0x1f, 0x0000);
3843
3844         /* Set rg_sel_sdm_rate */
3845         rtl_writephy(tp, 0x1f, 0x0c42);
3846         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3847         rtl_writephy(tp, 0x1f, 0x0000);
3848
3849         /* Channel estimation parameters */
3850         rtl_writephy(tp, 0x1f, 0x0a43);
3851         rtl_writephy(tp, 0x13, 0x80f3);
3852         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3853         rtl_writephy(tp, 0x13, 0x80f0);
3854         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3855         rtl_writephy(tp, 0x13, 0x80ef);
3856         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3857         rtl_writephy(tp, 0x13, 0x80f6);
3858         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3859         rtl_writephy(tp, 0x13, 0x80ec);
3860         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3861         rtl_writephy(tp, 0x13, 0x80ed);
3862         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3863         rtl_writephy(tp, 0x13, 0x80f2);
3864         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3865         rtl_writephy(tp, 0x13, 0x80f4);
3866         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3867         rtl_writephy(tp, 0x1f, 0x0a43);
3868         rtl_writephy(tp, 0x13, 0x8110);
3869         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3870         rtl_writephy(tp, 0x13, 0x810f);
3871         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3872         rtl_writephy(tp, 0x13, 0x8111);
3873         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3874         rtl_writephy(tp, 0x13, 0x8113);
3875         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3876         rtl_writephy(tp, 0x13, 0x8115);
3877         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3878         rtl_writephy(tp, 0x13, 0x810e);
3879         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3880         rtl_writephy(tp, 0x13, 0x810c);
3881         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3882         rtl_writephy(tp, 0x13, 0x810b);
3883         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3884         rtl_writephy(tp, 0x1f, 0x0a43);
3885         rtl_writephy(tp, 0x13, 0x80d1);
3886         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3887         rtl_writephy(tp, 0x13, 0x80cd);
3888         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3889         rtl_writephy(tp, 0x13, 0x80d3);
3890         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3891         rtl_writephy(tp, 0x13, 0x80d5);
3892         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3893         rtl_writephy(tp, 0x13, 0x80d7);
3894         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3895
3896         /* Force PWM-mode */
3897         rtl_writephy(tp, 0x1f, 0x0bcd);
3898         rtl_writephy(tp, 0x14, 0x5065);
3899         rtl_writephy(tp, 0x14, 0xd065);
3900         rtl_writephy(tp, 0x1f, 0x0bc8);
3901         rtl_writephy(tp, 0x12, 0x00ed);
3902         rtl_writephy(tp, 0x1f, 0x0bcd);
3903         rtl_writephy(tp, 0x14, 0x1065);
3904         rtl_writephy(tp, 0x14, 0x9065);
3905         rtl_writephy(tp, 0x14, 0x1065);
3906         rtl_writephy(tp, 0x1f, 0x0000);
3907
3908         rtl8168g_disable_aldps(tp);
3909         rtl8168g_config_eee_phy(tp);
3910         rtl_enable_eee(tp);
3911 }
3912
3913 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3914 {
3915         static const struct phy_reg phy_reg_init[] = {
3916                 { 0x1f, 0x0003 },
3917                 { 0x08, 0x441d },
3918                 { 0x01, 0x9100 },
3919                 { 0x1f, 0x0000 }
3920         };
3921
3922         rtl_writephy(tp, 0x1f, 0x0000);
3923         rtl_patchphy(tp, 0x11, 1 << 12);
3924         rtl_patchphy(tp, 0x19, 1 << 13);
3925         rtl_patchphy(tp, 0x10, 1 << 15);
3926
3927         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3928 }
3929
3930 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3931 {
3932         static const struct phy_reg phy_reg_init[] = {
3933                 { 0x1f, 0x0005 },
3934                 { 0x1a, 0x0000 },
3935                 { 0x1f, 0x0000 },
3936
3937                 { 0x1f, 0x0004 },
3938                 { 0x1c, 0x0000 },
3939                 { 0x1f, 0x0000 },
3940
3941                 { 0x1f, 0x0001 },
3942                 { 0x15, 0x7701 },
3943                 { 0x1f, 0x0000 }
3944         };
3945
3946         /* Disable ALDPS before ram code */
3947         rtl_writephy(tp, 0x1f, 0x0000);
3948         rtl_writephy(tp, 0x18, 0x0310);
3949         msleep(100);
3950
3951         rtl_apply_firmware(tp);
3952
3953         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3954 }
3955
3956 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3957 {
3958         /* Disable ALDPS before setting firmware */
3959         rtl_writephy(tp, 0x1f, 0x0000);
3960         rtl_writephy(tp, 0x18, 0x0310);
3961         msleep(20);
3962
3963         rtl_apply_firmware(tp);
3964
3965         /* EEE setting */
3966         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3967         rtl_writephy(tp, 0x1f, 0x0004);
3968         rtl_writephy(tp, 0x10, 0x401f);
3969         rtl_writephy(tp, 0x19, 0x7030);
3970         rtl_writephy(tp, 0x1f, 0x0000);
3971 }
3972
3973 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3974 {
3975         static const struct phy_reg phy_reg_init[] = {
3976                 { 0x1f, 0x0004 },
3977                 { 0x10, 0xc07f },
3978                 { 0x19, 0x7030 },
3979                 { 0x1f, 0x0000 }
3980         };
3981
3982         /* Disable ALDPS before ram code */
3983         rtl_writephy(tp, 0x1f, 0x0000);
3984         rtl_writephy(tp, 0x18, 0x0310);
3985         msleep(100);
3986
3987         rtl_apply_firmware(tp);
3988
3989         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3990         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3991
3992         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3993 }
3994
3995 static void rtl_hw_phy_config(struct net_device *dev)
3996 {
3997         static const rtl_generic_fct phy_configs[] = {
3998                 /* PCI devices. */
3999                 [RTL_GIGA_MAC_VER_01] = NULL,
4000                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
4001                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
4002                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
4003                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
4004                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
4005                 /* PCI-E devices. */
4006                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
4007                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
4008                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
4009                 [RTL_GIGA_MAC_VER_10] = NULL,
4010                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
4011                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
4012                 [RTL_GIGA_MAC_VER_13] = NULL,
4013                 [RTL_GIGA_MAC_VER_14] = NULL,
4014                 [RTL_GIGA_MAC_VER_15] = NULL,
4015                 [RTL_GIGA_MAC_VER_16] = NULL,
4016                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
4017                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
4018                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
4019                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
4020                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
4021                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
4022                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
4023                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
4024                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
4025                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
4026                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
4027                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
4028                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
4029                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
4030                 [RTL_GIGA_MAC_VER_31] = NULL,
4031                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
4032                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
4033                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
4034                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
4035                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
4036                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
4037                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
4038                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
4039                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
4040                 [RTL_GIGA_MAC_VER_41] = NULL,
4041                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
4042                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
4043                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
4044                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
4045                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
4046                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
4047                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
4048                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
4049                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
4050                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
4051         };
4052         struct rtl8169_private *tp = netdev_priv(dev);
4053
4054         if (phy_configs[tp->mac_version])
4055                 phy_configs[tp->mac_version](tp);
4056 }
4057
4058 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4059 {
4060         if (!test_and_set_bit(flag, tp->wk.flags))
4061                 schedule_work(&tp->wk.work);
4062 }
4063
4064 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4065 {
4066         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4067                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4068 }
4069
4070 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4071 {
4072         rtl_hw_phy_config(dev);
4073
4074         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4075                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4076                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4077                 netif_dbg(tp, drv, dev,
4078                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4079                 RTL_W8(tp, 0x82, 0x01);
4080         }
4081
4082         /* We may have called phy_speed_down before */
4083         phy_speed_up(tp->phydev);
4084
4085         genphy_soft_reset(tp->phydev);
4086 }
4087
4088 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4089 {
4090         rtl_lock_work(tp);
4091
4092         rtl_unlock_config_regs(tp);
4093
4094         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4095         RTL_R32(tp, MAC4);
4096
4097         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4098         RTL_R32(tp, MAC0);
4099
4100         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4101                 rtl_rar_exgmac_set(tp, addr);
4102
4103         rtl_lock_config_regs(tp);
4104
4105         rtl_unlock_work(tp);
4106 }
4107
4108 static int rtl_set_mac_address(struct net_device *dev, void *p)
4109 {
4110         struct rtl8169_private *tp = netdev_priv(dev);
4111         struct device *d = tp_to_dev(tp);
4112         int ret;
4113
4114         ret = eth_mac_addr(dev, p);
4115         if (ret)
4116                 return ret;
4117
4118         pm_runtime_get_noresume(d);
4119
4120         if (pm_runtime_active(d))
4121                 rtl_rar_set(tp, dev->dev_addr);
4122
4123         pm_runtime_put_noidle(d);
4124
4125         return 0;
4126 }
4127
4128 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4129 {
4130         struct rtl8169_private *tp = netdev_priv(dev);
4131
4132         if (!netif_running(dev))
4133                 return -ENODEV;
4134
4135         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4136 }
4137
4138 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4139 {
4140         struct mdio_ops *ops = &tp->mdio_ops;
4141
4142         switch (tp->mac_version) {
4143         case RTL_GIGA_MAC_VER_27:
4144                 ops->write      = r8168dp_1_mdio_write;
4145                 ops->read       = r8168dp_1_mdio_read;
4146                 break;
4147         case RTL_GIGA_MAC_VER_28:
4148         case RTL_GIGA_MAC_VER_31:
4149                 ops->write      = r8168dp_2_mdio_write;
4150                 ops->read       = r8168dp_2_mdio_read;
4151                 break;
4152         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4153                 ops->write      = r8168g_mdio_write;
4154                 ops->read       = r8168g_mdio_read;
4155                 break;
4156         default:
4157                 ops->write      = r8169_mdio_write;
4158                 ops->read       = r8169_mdio_read;
4159                 break;
4160         }
4161 }
4162
4163 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4164 {
4165         switch (tp->mac_version) {
4166         case RTL_GIGA_MAC_VER_25:
4167         case RTL_GIGA_MAC_VER_26:
4168         case RTL_GIGA_MAC_VER_29:
4169         case RTL_GIGA_MAC_VER_30:
4170         case RTL_GIGA_MAC_VER_32:
4171         case RTL_GIGA_MAC_VER_33:
4172         case RTL_GIGA_MAC_VER_34:
4173         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4174                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4175                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4176                 break;
4177         default:
4178                 break;
4179         }
4180 }
4181
4182 static void r8168_pll_power_down(struct rtl8169_private *tp)
4183 {
4184         if (r8168_check_dash(tp))
4185                 return;
4186
4187         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4188             tp->mac_version == RTL_GIGA_MAC_VER_33)
4189                 rtl_ephy_write(tp, 0x19, 0xff64);
4190
4191         if (device_may_wakeup(tp_to_dev(tp))) {
4192                 phy_speed_down(tp->phydev, false);
4193                 rtl_wol_suspend_quirk(tp);
4194                 return;
4195         }
4196
4197         switch (tp->mac_version) {
4198         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4199         case RTL_GIGA_MAC_VER_37:
4200         case RTL_GIGA_MAC_VER_39:
4201         case RTL_GIGA_MAC_VER_43:
4202         case RTL_GIGA_MAC_VER_44:
4203         case RTL_GIGA_MAC_VER_45:
4204         case RTL_GIGA_MAC_VER_46:
4205         case RTL_GIGA_MAC_VER_47:
4206         case RTL_GIGA_MAC_VER_48:
4207         case RTL_GIGA_MAC_VER_50:
4208         case RTL_GIGA_MAC_VER_51:
4209                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4210                 break;
4211         case RTL_GIGA_MAC_VER_40:
4212         case RTL_GIGA_MAC_VER_41:
4213         case RTL_GIGA_MAC_VER_49:
4214                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4215                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4216                 break;
4217         }
4218 }
4219
4220 static void r8168_pll_power_up(struct rtl8169_private *tp)
4221 {
4222         switch (tp->mac_version) {
4223         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4224         case RTL_GIGA_MAC_VER_37:
4225         case RTL_GIGA_MAC_VER_39:
4226         case RTL_GIGA_MAC_VER_43:
4227                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4228                 break;
4229         case RTL_GIGA_MAC_VER_44:
4230         case RTL_GIGA_MAC_VER_45:
4231         case RTL_GIGA_MAC_VER_46:
4232         case RTL_GIGA_MAC_VER_47:
4233         case RTL_GIGA_MAC_VER_48:
4234         case RTL_GIGA_MAC_VER_50:
4235         case RTL_GIGA_MAC_VER_51:
4236                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4237                 break;
4238         case RTL_GIGA_MAC_VER_40:
4239         case RTL_GIGA_MAC_VER_41:
4240         case RTL_GIGA_MAC_VER_49:
4241                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4242                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4243                 break;
4244         }
4245
4246         phy_resume(tp->phydev);
4247         /* give MAC/PHY some time to resume */
4248         msleep(20);
4249 }
4250
4251 static void rtl_pll_power_down(struct rtl8169_private *tp)
4252 {
4253         switch (tp->mac_version) {
4254         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4255         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4256                 break;
4257         default:
4258                 r8168_pll_power_down(tp);
4259         }
4260 }
4261
4262 static void rtl_pll_power_up(struct rtl8169_private *tp)
4263 {
4264         switch (tp->mac_version) {
4265         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4266         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4267                 break;
4268         default:
4269                 r8168_pll_power_up(tp);
4270         }
4271 }
4272
4273 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4274 {
4275         switch (tp->mac_version) {
4276         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4277         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4278                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4279                 break;
4280         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4281         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4282         case RTL_GIGA_MAC_VER_38:
4283                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4284                 break;
4285         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4286                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4287                 break;
4288         default:
4289                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4290                 break;
4291         }
4292 }
4293
4294 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4295 {
4296         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4297 }
4298
4299 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4300 {
4301         if (tp->jumbo_ops.enable) {
4302                 rtl_unlock_config_regs(tp);
4303                 tp->jumbo_ops.enable(tp);
4304                 rtl_lock_config_regs(tp);
4305         }
4306 }
4307
4308 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4309 {
4310         if (tp->jumbo_ops.disable) {
4311                 rtl_unlock_config_regs(tp);
4312                 tp->jumbo_ops.disable(tp);
4313                 rtl_lock_config_regs(tp);
4314         }
4315 }
4316
4317 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4318 {
4319         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4320         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4321         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4322 }
4323
4324 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4325 {
4326         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4327         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4328         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4329 }
4330
4331 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4332 {
4333         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4334 }
4335
4336 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4337 {
4338         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4339 }
4340
4341 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4342 {
4343         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4344         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4345         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4346         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4347 }
4348
4349 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4350 {
4351         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4352         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4353         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4354         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4355 }
4356
4357 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4358 {
4359         rtl_tx_performance_tweak(tp,
4360                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4361 }
4362
4363 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4364 {
4365         rtl_tx_performance_tweak(tp,
4366                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4367 }
4368
4369 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4370 {
4371         r8168b_0_hw_jumbo_enable(tp);
4372
4373         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4374 }
4375
4376 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4377 {
4378         r8168b_0_hw_jumbo_disable(tp);
4379
4380         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4381 }
4382
4383 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4384 {
4385         struct jumbo_ops *ops = &tp->jumbo_ops;
4386
4387         switch (tp->mac_version) {
4388         case RTL_GIGA_MAC_VER_11:
4389                 ops->disable    = r8168b_0_hw_jumbo_disable;
4390                 ops->enable     = r8168b_0_hw_jumbo_enable;
4391                 break;
4392         case RTL_GIGA_MAC_VER_12:
4393         case RTL_GIGA_MAC_VER_17:
4394                 ops->disable    = r8168b_1_hw_jumbo_disable;
4395                 ops->enable     = r8168b_1_hw_jumbo_enable;
4396                 break;
4397         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4398         case RTL_GIGA_MAC_VER_19:
4399         case RTL_GIGA_MAC_VER_20:
4400         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4401         case RTL_GIGA_MAC_VER_22:
4402         case RTL_GIGA_MAC_VER_23:
4403         case RTL_GIGA_MAC_VER_24:
4404         case RTL_GIGA_MAC_VER_25:
4405         case RTL_GIGA_MAC_VER_26:
4406                 ops->disable    = r8168c_hw_jumbo_disable;
4407                 ops->enable     = r8168c_hw_jumbo_enable;
4408                 break;
4409         case RTL_GIGA_MAC_VER_27:
4410         case RTL_GIGA_MAC_VER_28:
4411                 ops->disable    = r8168dp_hw_jumbo_disable;
4412                 ops->enable     = r8168dp_hw_jumbo_enable;
4413                 break;
4414         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4415         case RTL_GIGA_MAC_VER_32:
4416         case RTL_GIGA_MAC_VER_33:
4417         case RTL_GIGA_MAC_VER_34:
4418                 ops->disable    = r8168e_hw_jumbo_disable;
4419                 ops->enable     = r8168e_hw_jumbo_enable;
4420                 break;
4421
4422         /*
4423          * No action needed for jumbo frames with 8169.
4424          * No jumbo for 810x at all.
4425          */
4426         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4427         default:
4428                 ops->disable    = NULL;
4429                 ops->enable     = NULL;
4430                 break;
4431         }
4432 }
4433
4434 DECLARE_RTL_COND(rtl_chipcmd_cond)
4435 {
4436         return RTL_R8(tp, ChipCmd) & CmdReset;
4437 }
4438
4439 static void rtl_hw_reset(struct rtl8169_private *tp)
4440 {
4441         RTL_W8(tp, ChipCmd, CmdReset);
4442
4443         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4444 }
4445
4446 static void rtl_request_firmware(struct rtl8169_private *tp)
4447 {
4448         struct rtl_fw *rtl_fw;
4449         int rc = -ENOMEM;
4450
4451         /* firmware loaded already or no firmware available */
4452         if (tp->rtl_fw || !tp->fw_name)
4453                 return;
4454
4455         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4456         if (!rtl_fw)
4457                 goto err_warn;
4458
4459         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4460         if (rc < 0)
4461                 goto err_free;
4462
4463         rc = rtl_check_firmware(tp, rtl_fw);
4464         if (rc < 0)
4465                 goto err_release_firmware;
4466
4467         tp->rtl_fw = rtl_fw;
4468
4469         return;
4470
4471 err_release_firmware:
4472         release_firmware(rtl_fw->fw);
4473 err_free:
4474         kfree(rtl_fw);
4475 err_warn:
4476         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4477                    tp->fw_name, rc);
4478 }
4479
4480 static void rtl_rx_close(struct rtl8169_private *tp)
4481 {
4482         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4483 }
4484
4485 DECLARE_RTL_COND(rtl_npq_cond)
4486 {
4487         return RTL_R8(tp, TxPoll) & NPQ;
4488 }
4489
4490 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4491 {
4492         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4493 }
4494
4495 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4496 {
4497         /* Disable interrupts */
4498         rtl8169_irq_mask_and_ack(tp);
4499
4500         rtl_rx_close(tp);
4501
4502         switch (tp->mac_version) {
4503         case RTL_GIGA_MAC_VER_27:
4504         case RTL_GIGA_MAC_VER_28:
4505         case RTL_GIGA_MAC_VER_31:
4506                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4507                 break;
4508         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4509         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4510                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4511                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4512                 break;
4513         default:
4514                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4515                 udelay(100);
4516                 break;
4517         }
4518
4519         rtl_hw_reset(tp);
4520 }
4521
4522 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4523 {
4524         u32 val = TX_DMA_BURST << TxDMAShift |
4525                   InterFrameGap << TxInterFrameGapShift;
4526
4527         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4528             tp->mac_version != RTL_GIGA_MAC_VER_39)
4529                 val |= TXCFG_AUTO_FIFO;
4530
4531         RTL_W32(tp, TxConfig, val);
4532 }
4533
4534 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4535 {
4536         /* Low hurts. Let's disable the filtering. */
4537         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4538 }
4539
4540 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4541 {
4542         /*
4543          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4544          * register to be written before TxDescAddrLow to work.
4545          * Switching from MMIO to I/O access fixes the issue as well.
4546          */
4547         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4548         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4549         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4550         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4551 }
4552
4553 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4554 {
4555         u32 val;
4556
4557         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4558                 val = 0x000fff00;
4559         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4560                 val = 0x00ffff00;
4561         else
4562                 return;
4563
4564         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4565                 val |= 0xff;
4566
4567         RTL_W32(tp, 0x7c, val);
4568 }
4569
4570 static void rtl_set_rx_mode(struct net_device *dev)
4571 {
4572         struct rtl8169_private *tp = netdev_priv(dev);
4573         u32 mc_filter[2];       /* Multicast hash filter */
4574         int rx_mode;
4575         u32 tmp = 0;
4576
4577         if (dev->flags & IFF_PROMISC) {
4578                 /* Unconditionally log net taps. */
4579                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4580                 rx_mode =
4581                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4582                     AcceptAllPhys;
4583                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4584         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4585                    (dev->flags & IFF_ALLMULTI)) {
4586                 /* Too many to filter perfectly -- accept all multicasts. */
4587                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4588                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4589         } else {
4590                 struct netdev_hw_addr *ha;
4591
4592                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4593                 mc_filter[1] = mc_filter[0] = 0;
4594                 netdev_for_each_mc_addr(ha, dev) {
4595                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4596                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4597                         rx_mode |= AcceptMulticast;
4598                 }
4599         }
4600
4601         if (dev->features & NETIF_F_RXALL)
4602                 rx_mode |= (AcceptErr | AcceptRunt);
4603
4604         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4605
4606         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4607                 u32 data = mc_filter[0];
4608
4609                 mc_filter[0] = swab32(mc_filter[1]);
4610                 mc_filter[1] = swab32(data);
4611         }
4612
4613         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4614                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4615
4616         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4617         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4618
4619         RTL_W32(tp, RxConfig, tmp);
4620 }
4621
4622 static void rtl_hw_start(struct  rtl8169_private *tp)
4623 {
4624         rtl_unlock_config_regs(tp);
4625
4626         tp->hw_start(tp);
4627
4628         rtl_set_rx_max_size(tp);
4629         rtl_set_rx_tx_desc_registers(tp);
4630         rtl_lock_config_regs(tp);
4631
4632         /* disable interrupt coalescing */
4633         RTL_W16(tp, IntrMitigate, 0x0000);
4634         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4635         RTL_R8(tp, IntrMask);
4636         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4637         rtl_init_rxcfg(tp);
4638         rtl_set_tx_config_registers(tp);
4639
4640         rtl_set_rx_mode(tp->dev);
4641         /* no early-rx interrupts */
4642         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4643         rtl_irq_enable(tp);
4644 }
4645
4646 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4647 {
4648         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4649                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4650
4651         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4652
4653         tp->cp_cmd |= PCIMulRW;
4654
4655         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4656             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4657                 netif_dbg(tp, drv, tp->dev,
4658                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4659                 tp->cp_cmd |= (1 << 14);
4660         }
4661
4662         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4663
4664         rtl8169_set_magic_reg(tp, tp->mac_version);
4665
4666         RTL_W32(tp, RxMissed, 0);
4667 }
4668
4669 DECLARE_RTL_COND(rtl_csiar_cond)
4670 {
4671         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4672 }
4673
4674 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4675 {
4676         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4677
4678         RTL_W32(tp, CSIDR, value);
4679         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4680                 CSIAR_BYTE_ENABLE | func << 16);
4681
4682         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4683 }
4684
4685 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4686 {
4687         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4688
4689         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4690                 CSIAR_BYTE_ENABLE);
4691
4692         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4693                 RTL_R32(tp, CSIDR) : ~0;
4694 }
4695
4696 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4697 {
4698         struct pci_dev *pdev = tp->pci_dev;
4699         u32 csi;
4700
4701         /* According to Realtek the value at config space address 0x070f
4702          * controls the L0s/L1 entrance latency. We try standard ECAM access
4703          * first and if it fails fall back to CSI.
4704          */
4705         if (pdev->cfg_size > 0x070f &&
4706             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4707                 return;
4708
4709         netdev_notice_once(tp->dev,
4710                 "No native access to PCI extended config space, falling back to CSI\n");
4711         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4712         rtl_csi_write(tp, 0x070c, csi | val << 24);
4713 }
4714
4715 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4716 {
4717         rtl_csi_access_enable(tp, 0x27);
4718 }
4719
4720 struct ephy_info {
4721         unsigned int offset;
4722         u16 mask;
4723         u16 bits;
4724 };
4725
4726 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4727                           int len)
4728 {
4729         u16 w;
4730
4731         while (len-- > 0) {
4732                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4733                 rtl_ephy_write(tp, e->offset, w);
4734                 e++;
4735         }
4736 }
4737
4738 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4739 {
4740         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4741                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4742 }
4743
4744 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4745 {
4746         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4747                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4748 }
4749
4750 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4751 {
4752         /* work around an issue when PCI reset occurs during L2/L3 state */
4753         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4754 }
4755
4756 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4757 {
4758         if (enable) {
4759                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4760                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4761         } else {
4762                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4763                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4764         }
4765
4766         udelay(10);
4767 }
4768
4769 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4770 {
4771         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4772
4773         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4774         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4775
4776         if (tp->dev->mtu <= ETH_DATA_LEN) {
4777                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4778                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4779         }
4780 }
4781
4782 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4783 {
4784         rtl_hw_start_8168bb(tp);
4785
4786         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4787
4788         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4789 }
4790
4791 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4792 {
4793         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4794
4795         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4796
4797         if (tp->dev->mtu <= ETH_DATA_LEN)
4798                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4799
4800         rtl_disable_clock_request(tp);
4801
4802         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4803         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4804 }
4805
4806 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4807 {
4808         static const struct ephy_info e_info_8168cp[] = {
4809                 { 0x01, 0,      0x0001 },
4810                 { 0x02, 0x0800, 0x1000 },
4811                 { 0x03, 0,      0x0042 },
4812                 { 0x06, 0x0080, 0x0000 },
4813                 { 0x07, 0,      0x2000 }
4814         };
4815
4816         rtl_set_def_aspm_entry_latency(tp);
4817
4818         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4819
4820         __rtl_hw_start_8168cp(tp);
4821 }
4822
4823 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4824 {
4825         rtl_set_def_aspm_entry_latency(tp);
4826
4827         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4828
4829         if (tp->dev->mtu <= ETH_DATA_LEN)
4830                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4831
4832         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4833         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4834 }
4835
4836 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4837 {
4838         rtl_set_def_aspm_entry_latency(tp);
4839
4840         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4841
4842         /* Magic. */
4843         RTL_W8(tp, DBG_REG, 0x20);
4844
4845         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4846
4847         if (tp->dev->mtu <= ETH_DATA_LEN)
4848                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4849
4850         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4851         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4852 }
4853
4854 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4855 {
4856         static const struct ephy_info e_info_8168c_1[] = {
4857                 { 0x02, 0x0800, 0x1000 },
4858                 { 0x03, 0,      0x0002 },
4859                 { 0x06, 0x0080, 0x0000 }
4860         };
4861
4862         rtl_set_def_aspm_entry_latency(tp);
4863
4864         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4865
4866         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4867
4868         __rtl_hw_start_8168cp(tp);
4869 }
4870
4871 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4872 {
4873         static const struct ephy_info e_info_8168c_2[] = {
4874                 { 0x01, 0,      0x0001 },
4875                 { 0x03, 0x0400, 0x0220 }
4876         };
4877
4878         rtl_set_def_aspm_entry_latency(tp);
4879
4880         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4881
4882         __rtl_hw_start_8168cp(tp);
4883 }
4884
4885 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4886 {
4887         rtl_hw_start_8168c_2(tp);
4888 }
4889
4890 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4891 {
4892         rtl_set_def_aspm_entry_latency(tp);
4893
4894         __rtl_hw_start_8168cp(tp);
4895 }
4896
4897 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4898 {
4899         rtl_set_def_aspm_entry_latency(tp);
4900
4901         rtl_disable_clock_request(tp);
4902
4903         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4904
4905         if (tp->dev->mtu <= ETH_DATA_LEN)
4906                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4907
4908         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4909         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4910 }
4911
4912 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4913 {
4914         rtl_set_def_aspm_entry_latency(tp);
4915
4916         if (tp->dev->mtu <= ETH_DATA_LEN)
4917                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4918
4919         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4920
4921         rtl_disable_clock_request(tp);
4922 }
4923
4924 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4925 {
4926         static const struct ephy_info e_info_8168d_4[] = {
4927                 { 0x0b, 0x0000, 0x0048 },
4928                 { 0x19, 0x0020, 0x0050 },
4929                 { 0x0c, 0x0100, 0x0020 }
4930         };
4931
4932         rtl_set_def_aspm_entry_latency(tp);
4933
4934         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4935
4936         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4937
4938         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4939
4940         rtl_enable_clock_request(tp);
4941 }
4942
4943 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4944 {
4945         static const struct ephy_info e_info_8168e_1[] = {
4946                 { 0x00, 0x0200, 0x0100 },
4947                 { 0x00, 0x0000, 0x0004 },
4948                 { 0x06, 0x0002, 0x0001 },
4949                 { 0x06, 0x0000, 0x0030 },
4950                 { 0x07, 0x0000, 0x2000 },
4951                 { 0x00, 0x0000, 0x0020 },
4952                 { 0x03, 0x5800, 0x2000 },
4953                 { 0x03, 0x0000, 0x0001 },
4954                 { 0x01, 0x0800, 0x1000 },
4955                 { 0x07, 0x0000, 0x4000 },
4956                 { 0x1e, 0x0000, 0x2000 },
4957                 { 0x19, 0xffff, 0xfe6c },
4958                 { 0x0a, 0x0000, 0x0040 }
4959         };
4960
4961         rtl_set_def_aspm_entry_latency(tp);
4962
4963         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4964
4965         if (tp->dev->mtu <= ETH_DATA_LEN)
4966                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4967
4968         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4969
4970         rtl_disable_clock_request(tp);
4971
4972         /* Reset tx FIFO pointer */
4973         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4974         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4975
4976         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4977 }
4978
4979 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4980 {
4981         static const struct ephy_info e_info_8168e_2[] = {
4982                 { 0x09, 0x0000, 0x0080 },
4983                 { 0x19, 0x0000, 0x0224 }
4984         };
4985
4986         rtl_set_def_aspm_entry_latency(tp);
4987
4988         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4989
4990         if (tp->dev->mtu <= ETH_DATA_LEN)
4991                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4992
4993         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4994         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4995         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002);
4996         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
4997         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4998         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4999         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
5000         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5001
5002         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5003
5004         rtl_disable_clock_request(tp);
5005
5006         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5007
5008         /* Adjust EEE LED frequency */
5009         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5010
5011         rtl8168_config_eee_mac(tp);
5012
5013         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5014         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5015         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5016
5017         rtl_hw_aspm_clkreq_enable(tp, true);
5018 }
5019
5020 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5021 {
5022         rtl_set_def_aspm_entry_latency(tp);
5023
5024         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5025
5026         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5027         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5028         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002);
5029         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
5030         rtl_reset_packet_filter(tp);
5031         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
5032         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
5033         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
5034         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
5035
5036         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5037
5038         rtl_disable_clock_request(tp);
5039
5040         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5041         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5042         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5043         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5044
5045         rtl8168_config_eee_mac(tp);
5046 }
5047
5048 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5049 {
5050         static const struct ephy_info e_info_8168f_1[] = {
5051                 { 0x06, 0x00c0, 0x0020 },
5052                 { 0x08, 0x0001, 0x0002 },
5053                 { 0x09, 0x0000, 0x0080 },
5054                 { 0x19, 0x0000, 0x0224 }
5055         };
5056
5057         rtl_hw_start_8168f(tp);
5058
5059         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5060
5061         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5062
5063         /* Adjust EEE LED frequency */
5064         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5065 }
5066
5067 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5068 {
5069         static const struct ephy_info e_info_8168f_1[] = {
5070                 { 0x06, 0x00c0, 0x0020 },
5071                 { 0x0f, 0xffff, 0x5200 },
5072                 { 0x1e, 0x0000, 0x4000 },
5073                 { 0x19, 0x0000, 0x0224 }
5074         };
5075
5076         rtl_hw_start_8168f(tp);
5077         rtl_pcie_state_l2l3_disable(tp);
5078
5079         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5080
5081         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
5082 }
5083
5084 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5085 {
5086         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002);
5087         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38);
5088         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48);
5089         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
5090
5091         rtl_set_def_aspm_entry_latency(tp);
5092
5093         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5094
5095         rtl_reset_packet_filter(tp);
5096         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
5097
5098         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5099         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5100
5101         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5102         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5103
5104         /* Adjust EEE LED frequency */
5105         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5106
5107         rtl8168_config_eee_mac(tp);
5108
5109         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5110         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5111
5112         rtl_pcie_state_l2l3_disable(tp);
5113 }
5114
5115 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5116 {
5117         static const struct ephy_info e_info_8168g_1[] = {
5118                 { 0x00, 0x0000, 0x0008 },
5119                 { 0x0c, 0x37d0, 0x0820 },
5120                 { 0x1e, 0x0000, 0x0001 },
5121                 { 0x19, 0x8000, 0x0000 }
5122         };
5123
5124         rtl_hw_start_8168g(tp);
5125
5126         /* disable aspm and clock request before access ephy */
5127         rtl_hw_aspm_clkreq_enable(tp, false);
5128         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5129         rtl_hw_aspm_clkreq_enable(tp, true);
5130 }
5131
5132 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5133 {
5134         static const struct ephy_info e_info_8168g_2[] = {
5135                 { 0x00, 0x0000, 0x0008 },
5136                 { 0x0c, 0x3df0, 0x0200 },
5137                 { 0x19, 0xffff, 0xfc00 },
5138                 { 0x1e, 0xffff, 0x20eb }
5139         };
5140
5141         rtl_hw_start_8168g(tp);
5142
5143         /* disable aspm and clock request before access ephy */
5144         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5145         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5146         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5147 }
5148
5149 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5150 {
5151         static const struct ephy_info e_info_8411_2[] = {
5152                 { 0x00, 0x0000, 0x0008 },
5153                 { 0x0c, 0x3df0, 0x0200 },
5154                 { 0x0f, 0xffff, 0x5200 },
5155                 { 0x19, 0x0020, 0x0000 },
5156                 { 0x1e, 0x0000, 0x2000 }
5157         };
5158
5159         rtl_hw_start_8168g(tp);
5160
5161         /* disable aspm and clock request before access ephy */
5162         rtl_hw_aspm_clkreq_enable(tp, false);
5163         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5164         rtl_hw_aspm_clkreq_enable(tp, true);
5165 }
5166
5167 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5168 {
5169         int rg_saw_cnt;
5170         u32 data;
5171         static const struct ephy_info e_info_8168h_1[] = {
5172                 { 0x1e, 0x0800, 0x0001 },
5173                 { 0x1d, 0x0000, 0x0800 },
5174                 { 0x05, 0xffff, 0x2089 },
5175                 { 0x06, 0xffff, 0x5881 },
5176                 { 0x04, 0xffff, 0x154a },
5177                 { 0x01, 0xffff, 0x068b }
5178         };
5179
5180         /* disable aspm and clock request before access ephy */
5181         rtl_hw_aspm_clkreq_enable(tp, false);
5182         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5183
5184         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002);
5185         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38);
5186         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48);
5187         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
5188
5189         rtl_set_def_aspm_entry_latency(tp);
5190
5191         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5192
5193         rtl_reset_packet_filter(tp);
5194
5195         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5196
5197         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5198
5199         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5200
5201         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5202         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5203
5204         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5205         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5206
5207         /* Adjust EEE LED frequency */
5208         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5209
5210         rtl8168_config_eee_mac(tp);
5211
5212         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5213         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5214
5215         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5216
5217         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5218
5219         rtl_pcie_state_l2l3_disable(tp);
5220
5221         rtl_writephy(tp, 0x1f, 0x0c42);
5222         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5223         rtl_writephy(tp, 0x1f, 0x0000);
5224         if (rg_saw_cnt > 0) {
5225                 u16 sw_cnt_1ms_ini;
5226
5227                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5228                 sw_cnt_1ms_ini &= 0x0fff;
5229                 data = r8168_mac_ocp_read(tp, 0xd412);
5230                 data &= ~0x0fff;
5231                 data |= sw_cnt_1ms_ini;
5232                 r8168_mac_ocp_write(tp, 0xd412, data);
5233         }
5234
5235         data = r8168_mac_ocp_read(tp, 0xe056);
5236         data &= ~0xf0;
5237         data |= 0x70;
5238         r8168_mac_ocp_write(tp, 0xe056, data);
5239
5240         data = r8168_mac_ocp_read(tp, 0xe052);
5241         data &= ~0x6000;
5242         data |= 0x8008;
5243         r8168_mac_ocp_write(tp, 0xe052, data);
5244
5245         data = r8168_mac_ocp_read(tp, 0xe0d6);
5246         data &= ~0x01ff;
5247         data |= 0x017f;
5248         r8168_mac_ocp_write(tp, 0xe0d6, data);
5249
5250         data = r8168_mac_ocp_read(tp, 0xd420);
5251         data &= ~0x0fff;
5252         data |= 0x047f;
5253         r8168_mac_ocp_write(tp, 0xd420, data);
5254
5255         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5256         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5257         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5258         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5259
5260         rtl_hw_aspm_clkreq_enable(tp, true);
5261 }
5262
5263 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5264 {
5265         rtl8168ep_stop_cmac(tp);
5266
5267         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002);
5268         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f);
5269         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f);
5270         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
5271
5272         rtl_set_def_aspm_entry_latency(tp);
5273
5274         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5275
5276         rtl_reset_packet_filter(tp);
5277
5278         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5279
5280         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5281
5282         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5283         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5284
5285         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5286         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5287
5288         /* Adjust EEE LED frequency */
5289         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5290
5291         rtl8168_config_eee_mac(tp);
5292
5293         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5294
5295         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5296
5297         rtl_pcie_state_l2l3_disable(tp);
5298 }
5299
5300 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5301 {
5302         static const struct ephy_info e_info_8168ep_1[] = {
5303                 { 0x00, 0xffff, 0x10ab },
5304                 { 0x06, 0xffff, 0xf030 },
5305                 { 0x08, 0xffff, 0x2006 },
5306                 { 0x0d, 0xffff, 0x1666 },
5307                 { 0x0c, 0x3ff0, 0x0000 }
5308         };
5309
5310         /* disable aspm and clock request before access ephy */
5311         rtl_hw_aspm_clkreq_enable(tp, false);
5312         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5313
5314         rtl_hw_start_8168ep(tp);
5315
5316         rtl_hw_aspm_clkreq_enable(tp, true);
5317 }
5318
5319 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5320 {
5321         static const struct ephy_info e_info_8168ep_2[] = {
5322                 { 0x00, 0xffff, 0x10a3 },
5323                 { 0x19, 0xffff, 0xfc00 },
5324                 { 0x1e, 0xffff, 0x20ea }
5325         };
5326
5327         /* disable aspm and clock request before access ephy */
5328         rtl_hw_aspm_clkreq_enable(tp, false);
5329         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5330
5331         rtl_hw_start_8168ep(tp);
5332
5333         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5334         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5335
5336         rtl_hw_aspm_clkreq_enable(tp, true);
5337 }
5338
5339 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5340 {
5341         u32 data;
5342         static const struct ephy_info e_info_8168ep_3[] = {
5343                 { 0x00, 0xffff, 0x10a3 },
5344                 { 0x19, 0xffff, 0x7c00 },
5345                 { 0x1e, 0xffff, 0x20eb },
5346                 { 0x0d, 0xffff, 0x1666 }
5347         };
5348
5349         /* disable aspm and clock request before access ephy */
5350         rtl_hw_aspm_clkreq_enable(tp, false);
5351         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5352
5353         rtl_hw_start_8168ep(tp);
5354
5355         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5356         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5357
5358         data = r8168_mac_ocp_read(tp, 0xd3e2);
5359         data &= 0xf000;
5360         data |= 0x0271;
5361         r8168_mac_ocp_write(tp, 0xd3e2, data);
5362
5363         data = r8168_mac_ocp_read(tp, 0xd3e4);
5364         data &= 0xff00;
5365         r8168_mac_ocp_write(tp, 0xd3e4, data);
5366
5367         data = r8168_mac_ocp_read(tp, 0xe860);
5368         data |= 0x0080;
5369         r8168_mac_ocp_write(tp, 0xe860, data);
5370
5371         rtl_hw_aspm_clkreq_enable(tp, true);
5372 }
5373
5374 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5375 {
5376         static const struct ephy_info e_info_8102e_1[] = {
5377                 { 0x01, 0, 0x6e65 },
5378                 { 0x02, 0, 0x091f },
5379                 { 0x03, 0, 0xc2f9 },
5380                 { 0x06, 0, 0xafb5 },
5381                 { 0x07, 0, 0x0e00 },
5382                 { 0x19, 0, 0xec80 },
5383                 { 0x01, 0, 0x2e65 },
5384                 { 0x01, 0, 0x6e65 }
5385         };
5386         u8 cfg1;
5387
5388         rtl_set_def_aspm_entry_latency(tp);
5389
5390         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5391
5392         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5393
5394         RTL_W8(tp, Config1,
5395                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5396         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5397
5398         cfg1 = RTL_R8(tp, Config1);
5399         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5400                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5401
5402         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5403 }
5404
5405 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5406 {
5407         rtl_set_def_aspm_entry_latency(tp);
5408
5409         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5410
5411         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5412         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5413 }
5414
5415 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5416 {
5417         rtl_hw_start_8102e_2(tp);
5418
5419         rtl_ephy_write(tp, 0x03, 0xc2f9);
5420 }
5421
5422 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5423 {
5424         static const struct ephy_info e_info_8105e_1[] = {
5425                 { 0x07, 0, 0x4000 },
5426                 { 0x19, 0, 0x0200 },
5427                 { 0x19, 0, 0x0020 },
5428                 { 0x1e, 0, 0x2000 },
5429                 { 0x03, 0, 0x0001 },
5430                 { 0x19, 0, 0x0100 },
5431                 { 0x19, 0, 0x0004 },
5432                 { 0x0a, 0, 0x0020 }
5433         };
5434
5435         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5436         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5437
5438         /* Disable Early Tally Counter */
5439         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5440
5441         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5442         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5443
5444         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5445
5446         rtl_pcie_state_l2l3_disable(tp);
5447 }
5448
5449 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5450 {
5451         rtl_hw_start_8105e_1(tp);
5452         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5453 }
5454
5455 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5456 {
5457         static const struct ephy_info e_info_8402[] = {
5458                 { 0x19, 0xffff, 0xff64 },
5459                 { 0x1e, 0, 0x4000 }
5460         };
5461
5462         rtl_set_def_aspm_entry_latency(tp);
5463
5464         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5465         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5466
5467         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5468
5469         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5470
5471         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5472
5473         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002);
5474         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006);
5475         rtl_reset_packet_filter(tp);
5476         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5477         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5478         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5479
5480         rtl_pcie_state_l2l3_disable(tp);
5481 }
5482
5483 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5484 {
5485         rtl_hw_aspm_clkreq_enable(tp, false);
5486
5487         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5488         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5489
5490         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5491         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5492         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5493
5494         rtl_pcie_state_l2l3_disable(tp);
5495         rtl_hw_aspm_clkreq_enable(tp, true);
5496 }
5497
5498 static void rtl_hw_config(struct rtl8169_private *tp)
5499 {
5500         static const rtl_generic_fct hw_configs[] = {
5501                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5502                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5503                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5504                 [RTL_GIGA_MAC_VER_10] = NULL,
5505                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5506                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5507                 [RTL_GIGA_MAC_VER_13] = NULL,
5508                 [RTL_GIGA_MAC_VER_14] = NULL,
5509                 [RTL_GIGA_MAC_VER_15] = NULL,
5510                 [RTL_GIGA_MAC_VER_16] = NULL,
5511                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5512                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5513                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5514                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5515                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5516                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5517                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5518                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5519                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5520                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5521                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5522                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5523                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5524                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5525                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5526                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5527                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5528                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5529                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5530                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5531                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5532                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5533                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5534                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5535                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5536                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5537                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5538                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5539                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5540                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5541                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5542                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5543                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5544                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5545                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5546         };
5547
5548         if (hw_configs[tp->mac_version])
5549                 hw_configs[tp->mac_version](tp);
5550 }
5551
5552 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5553 {
5554         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5555
5556         /* Workaround for RxFIFO overflow. */
5557         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5558                 tp->irq_mask |= RxFIFOOver;
5559                 tp->irq_mask &= ~RxOverflow;
5560         }
5561
5562         rtl_hw_config(tp);
5563 }
5564
5565 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5566 {
5567         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5568                 tp->irq_mask &= ~RxFIFOOver;
5569
5570         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5571             tp->mac_version == RTL_GIGA_MAC_VER_16)
5572                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5573                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5574
5575         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5576
5577         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5578         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5579
5580         rtl_hw_config(tp);
5581 }
5582
5583 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5584 {
5585         struct rtl8169_private *tp = netdev_priv(dev);
5586
5587         if (new_mtu > ETH_DATA_LEN)
5588                 rtl_hw_jumbo_enable(tp);
5589         else
5590                 rtl_hw_jumbo_disable(tp);
5591
5592         dev->mtu = new_mtu;
5593         netdev_update_features(dev);
5594
5595         return 0;
5596 }
5597
5598 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5599 {
5600         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5601         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5602 }
5603
5604 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5605                                      void **data_buff, struct RxDesc *desc)
5606 {
5607         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5608                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5609
5610         kfree(*data_buff);
5611         *data_buff = NULL;
5612         rtl8169_make_unusable_by_asic(desc);
5613 }
5614
5615 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5616 {
5617         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5618
5619         /* Force memory writes to complete before releasing descriptor */
5620         dma_wmb();
5621
5622         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5623 }
5624
5625 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5626                                              struct RxDesc *desc)
5627 {
5628         void *data;
5629         dma_addr_t mapping;
5630         struct device *d = tp_to_dev(tp);
5631         int node = dev_to_node(d);
5632
5633         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5634         if (!data)
5635                 return NULL;
5636
5637         /* Memory should be properly aligned, but better check. */
5638         if (!IS_ALIGNED((unsigned long)data, 8)) {
5639                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5640                 goto err_out;
5641         }
5642
5643         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5644         if (unlikely(dma_mapping_error(d, mapping))) {
5645                 if (net_ratelimit())
5646                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5647                 goto err_out;
5648         }
5649
5650         desc->addr = cpu_to_le64(mapping);
5651         rtl8169_mark_to_asic(desc);
5652         return data;
5653
5654 err_out:
5655         kfree(data);
5656         return NULL;
5657 }
5658
5659 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5660 {
5661         unsigned int i;
5662
5663         for (i = 0; i < NUM_RX_DESC; i++) {
5664                 if (tp->Rx_databuff[i]) {
5665                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5666                                             tp->RxDescArray + i);
5667                 }
5668         }
5669 }
5670
5671 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5672 {
5673         desc->opts1 |= cpu_to_le32(RingEnd);
5674 }
5675
5676 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5677 {
5678         unsigned int i;
5679
5680         for (i = 0; i < NUM_RX_DESC; i++) {
5681                 void *data;
5682
5683                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5684                 if (!data) {
5685                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5686                         goto err_out;
5687                 }
5688                 tp->Rx_databuff[i] = data;
5689         }
5690
5691         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5692         return 0;
5693
5694 err_out:
5695         rtl8169_rx_clear(tp);
5696         return -ENOMEM;
5697 }
5698
5699 static int rtl8169_init_ring(struct rtl8169_private *tp)
5700 {
5701         rtl8169_init_ring_indexes(tp);
5702
5703         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5704         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5705
5706         return rtl8169_rx_fill(tp);
5707 }
5708
5709 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5710                                  struct TxDesc *desc)
5711 {
5712         unsigned int len = tx_skb->len;
5713
5714         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5715
5716         desc->opts1 = 0x00;
5717         desc->opts2 = 0x00;
5718         desc->addr = 0x00;
5719         tx_skb->len = 0;
5720 }
5721
5722 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5723                                    unsigned int n)
5724 {
5725         unsigned int i;
5726
5727         for (i = 0; i < n; i++) {
5728                 unsigned int entry = (start + i) % NUM_TX_DESC;
5729                 struct ring_info *tx_skb = tp->tx_skb + entry;
5730                 unsigned int len = tx_skb->len;
5731
5732                 if (len) {
5733                         struct sk_buff *skb = tx_skb->skb;
5734
5735                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5736                                              tp->TxDescArray + entry);
5737                         if (skb) {
5738                                 dev_consume_skb_any(skb);
5739                                 tx_skb->skb = NULL;
5740                         }
5741                 }
5742         }
5743 }
5744
5745 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5746 {
5747         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5748         tp->cur_tx = tp->dirty_tx = 0;
5749         netdev_reset_queue(tp->dev);
5750 }
5751
5752 static void rtl_reset_work(struct rtl8169_private *tp)
5753 {
5754         struct net_device *dev = tp->dev;
5755         int i;
5756
5757         napi_disable(&tp->napi);
5758         netif_stop_queue(dev);
5759         synchronize_rcu();
5760
5761         rtl8169_hw_reset(tp);
5762
5763         for (i = 0; i < NUM_RX_DESC; i++)
5764                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5765
5766         rtl8169_tx_clear(tp);
5767         rtl8169_init_ring_indexes(tp);
5768
5769         napi_enable(&tp->napi);
5770         rtl_hw_start(tp);
5771         netif_wake_queue(dev);
5772 }
5773
5774 static void rtl8169_tx_timeout(struct net_device *dev)
5775 {
5776         struct rtl8169_private *tp = netdev_priv(dev);
5777
5778         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5779 }
5780
5781 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5782 {
5783         u32 status = opts0 | len;
5784
5785         if (entry == NUM_TX_DESC - 1)
5786                 status |= RingEnd;
5787
5788         return cpu_to_le32(status);
5789 }
5790
5791 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5792                               u32 *opts)
5793 {
5794         struct skb_shared_info *info = skb_shinfo(skb);
5795         unsigned int cur_frag, entry;
5796         struct TxDesc *uninitialized_var(txd);
5797         struct device *d = tp_to_dev(tp);
5798
5799         entry = tp->cur_tx;
5800         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5801                 const skb_frag_t *frag = info->frags + cur_frag;
5802                 dma_addr_t mapping;
5803                 u32 len;
5804                 void *addr;
5805
5806                 entry = (entry + 1) % NUM_TX_DESC;
5807
5808                 txd = tp->TxDescArray + entry;
5809                 len = skb_frag_size(frag);
5810                 addr = skb_frag_address(frag);
5811                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5812                 if (unlikely(dma_mapping_error(d, mapping))) {
5813                         if (net_ratelimit())
5814                                 netif_err(tp, drv, tp->dev,
5815                                           "Failed to map TX fragments DMA!\n");
5816                         goto err_out;
5817                 }
5818
5819                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5820                 txd->opts2 = cpu_to_le32(opts[1]);
5821                 txd->addr = cpu_to_le64(mapping);
5822
5823                 tp->tx_skb[entry].len = len;
5824         }
5825
5826         if (cur_frag) {
5827                 tp->tx_skb[entry].skb = skb;
5828                 txd->opts1 |= cpu_to_le32(LastFrag);
5829         }
5830
5831         return cur_frag;
5832
5833 err_out:
5834         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5835         return -EIO;
5836 }
5837
5838 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5839 {
5840         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5841 }
5842
5843 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5844                                       struct net_device *dev);
5845 /* r8169_csum_workaround()
5846  * The hw limites the value the transport offset. When the offset is out of the
5847  * range, calculate the checksum by sw.
5848  */
5849 static void r8169_csum_workaround(struct rtl8169_private *tp,
5850                                   struct sk_buff *skb)
5851 {
5852         if (skb_shinfo(skb)->gso_size) {
5853                 netdev_features_t features = tp->dev->features;
5854                 struct sk_buff *segs, *nskb;
5855
5856                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5857                 segs = skb_gso_segment(skb, features);
5858                 if (IS_ERR(segs) || !segs)
5859                         goto drop;
5860
5861                 do {
5862                         nskb = segs;
5863                         segs = segs->next;
5864                         nskb->next = NULL;
5865                         rtl8169_start_xmit(nskb, tp->dev);
5866                 } while (segs);
5867
5868                 dev_consume_skb_any(skb);
5869         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5870                 if (skb_checksum_help(skb) < 0)
5871                         goto drop;
5872
5873                 rtl8169_start_xmit(skb, tp->dev);
5874         } else {
5875                 struct net_device_stats *stats;
5876
5877 drop:
5878                 stats = &tp->dev->stats;
5879                 stats->tx_dropped++;
5880                 dev_kfree_skb_any(skb);
5881         }
5882 }
5883
5884 /* msdn_giant_send_check()
5885  * According to the document of microsoft, the TCP Pseudo Header excludes the
5886  * packet length for IPv6 TCP large packets.
5887  */
5888 static int msdn_giant_send_check(struct sk_buff *skb)
5889 {
5890         const struct ipv6hdr *ipv6h;
5891         struct tcphdr *th;
5892         int ret;
5893
5894         ret = skb_cow_head(skb, 0);
5895         if (ret)
5896                 return ret;
5897
5898         ipv6h = ipv6_hdr(skb);
5899         th = tcp_hdr(skb);
5900
5901         th->check = 0;
5902         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5903
5904         return ret;
5905 }
5906
5907 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5908                                 struct sk_buff *skb, u32 *opts)
5909 {
5910         u32 mss = skb_shinfo(skb)->gso_size;
5911
5912         if (mss) {
5913                 opts[0] |= TD_LSO;
5914                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5915         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5916                 const struct iphdr *ip = ip_hdr(skb);
5917
5918                 if (ip->protocol == IPPROTO_TCP)
5919                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5920                 else if (ip->protocol == IPPROTO_UDP)
5921                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5922                 else
5923                         WARN_ON_ONCE(1);
5924         }
5925
5926         return true;
5927 }
5928
5929 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5930                                 struct sk_buff *skb, u32 *opts)
5931 {
5932         u32 transport_offset = (u32)skb_transport_offset(skb);
5933         u32 mss = skb_shinfo(skb)->gso_size;
5934
5935         if (mss) {
5936                 if (transport_offset > GTTCPHO_MAX) {
5937                         netif_warn(tp, tx_err, tp->dev,
5938                                    "Invalid transport offset 0x%x for TSO\n",
5939                                    transport_offset);
5940                         return false;
5941                 }
5942
5943                 switch (vlan_get_protocol(skb)) {
5944                 case htons(ETH_P_IP):
5945                         opts[0] |= TD1_GTSENV4;
5946                         break;
5947
5948                 case htons(ETH_P_IPV6):
5949                         if (msdn_giant_send_check(skb))
5950                                 return false;
5951
5952                         opts[0] |= TD1_GTSENV6;
5953                         break;
5954
5955                 default:
5956                         WARN_ON_ONCE(1);
5957                         break;
5958                 }
5959
5960                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5961                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5962         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5963                 u8 ip_protocol;
5964
5965                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5966                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5967
5968                 if (transport_offset > TCPHO_MAX) {
5969                         netif_warn(tp, tx_err, tp->dev,
5970                                    "Invalid transport offset 0x%x\n",
5971                                    transport_offset);
5972                         return false;
5973                 }
5974
5975                 switch (vlan_get_protocol(skb)) {
5976                 case htons(ETH_P_IP):
5977                         opts[1] |= TD1_IPv4_CS;
5978                         ip_protocol = ip_hdr(skb)->protocol;
5979                         break;
5980
5981                 case htons(ETH_P_IPV6):
5982                         opts[1] |= TD1_IPv6_CS;
5983                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5984                         break;
5985
5986                 default:
5987                         ip_protocol = IPPROTO_RAW;
5988                         break;
5989                 }
5990
5991                 if (ip_protocol == IPPROTO_TCP)
5992                         opts[1] |= TD1_TCP_CS;
5993                 else if (ip_protocol == IPPROTO_UDP)
5994                         opts[1] |= TD1_UDP_CS;
5995                 else
5996                         WARN_ON_ONCE(1);
5997
5998                 opts[1] |= transport_offset << TCPHO_SHIFT;
5999         } else {
6000                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6001                         return !eth_skb_pad(skb);
6002         }
6003
6004         return true;
6005 }
6006
6007 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
6008                                unsigned int nr_frags)
6009 {
6010         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
6011
6012         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
6013         return slots_avail > nr_frags;
6014 }
6015
6016 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6017                                       struct net_device *dev)
6018 {
6019         struct rtl8169_private *tp = netdev_priv(dev);
6020         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6021         struct TxDesc *txd = tp->TxDescArray + entry;
6022         struct device *d = tp_to_dev(tp);
6023         dma_addr_t mapping;
6024         u32 opts[2], len;
6025         int frags;
6026
6027         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6028                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6029                 goto err_stop_0;
6030         }
6031
6032         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6033                 goto err_stop_0;
6034
6035         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6036         opts[0] = DescOwn;
6037
6038         if (!tp->tso_csum(tp, skb, opts)) {
6039                 r8169_csum_workaround(tp, skb);
6040                 return NETDEV_TX_OK;
6041         }
6042
6043         len = skb_headlen(skb);
6044         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6045         if (unlikely(dma_mapping_error(d, mapping))) {
6046                 if (net_ratelimit())
6047                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6048                 goto err_dma_0;
6049         }
6050
6051         tp->tx_skb[entry].len = len;
6052         txd->addr = cpu_to_le64(mapping);
6053
6054         frags = rtl8169_xmit_frags(tp, skb, opts);
6055         if (frags < 0)
6056                 goto err_dma_1;
6057         else if (frags)
6058                 opts[0] |= FirstFrag;
6059         else {
6060                 opts[0] |= FirstFrag | LastFrag;
6061                 tp->tx_skb[entry].skb = skb;
6062         }
6063
6064         txd->opts2 = cpu_to_le32(opts[1]);
6065
6066         netdev_sent_queue(dev, skb->len);
6067
6068         skb_tx_timestamp(skb);
6069
6070         /* Force memory writes to complete before releasing descriptor */
6071         dma_wmb();
6072
6073         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6074
6075         /* Force all memory writes to complete before notifying device */
6076         wmb();
6077
6078         tp->cur_tx += frags + 1;
6079
6080         RTL_W8(tp, TxPoll, NPQ);
6081
6082         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6083                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6084                  * not miss a ring update when it notices a stopped queue.
6085                  */
6086                 smp_wmb();
6087                 netif_stop_queue(dev);
6088                 /* Sync with rtl_tx:
6089                  * - publish queue status and cur_tx ring index (write barrier)
6090                  * - refresh dirty_tx ring index (read barrier).
6091                  * May the current thread have a pessimistic view of the ring
6092                  * status and forget to wake up queue, a racing rtl_tx thread
6093                  * can't.
6094                  */
6095                 smp_mb();
6096                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6097                         netif_start_queue(dev);
6098         }
6099
6100         return NETDEV_TX_OK;
6101
6102 err_dma_1:
6103         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6104 err_dma_0:
6105         dev_kfree_skb_any(skb);
6106         dev->stats.tx_dropped++;
6107         return NETDEV_TX_OK;
6108
6109 err_stop_0:
6110         netif_stop_queue(dev);
6111         dev->stats.tx_dropped++;
6112         return NETDEV_TX_BUSY;
6113 }
6114
6115 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6116 {
6117         struct rtl8169_private *tp = netdev_priv(dev);
6118         struct pci_dev *pdev = tp->pci_dev;
6119         u16 pci_status, pci_cmd;
6120
6121         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6122         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6123
6124         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6125                   pci_cmd, pci_status);
6126
6127         /*
6128          * The recovery sequence below admits a very elaborated explanation:
6129          * - it seems to work;
6130          * - I did not see what else could be done;
6131          * - it makes iop3xx happy.
6132          *
6133          * Feel free to adjust to your needs.
6134          */
6135         if (pdev->broken_parity_status)
6136                 pci_cmd &= ~PCI_COMMAND_PARITY;
6137         else
6138                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6139
6140         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6141
6142         pci_write_config_word(pdev, PCI_STATUS,
6143                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6144                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6145                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6146
6147         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6148 }
6149
6150 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6151                    int budget)
6152 {
6153         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6154
6155         dirty_tx = tp->dirty_tx;
6156         smp_rmb();
6157         tx_left = tp->cur_tx - dirty_tx;
6158
6159         while (tx_left > 0) {
6160                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6161                 struct ring_info *tx_skb = tp->tx_skb + entry;
6162                 u32 status;
6163
6164                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6165                 if (status & DescOwn)
6166                         break;
6167
6168                 /* This barrier is needed to keep us from reading
6169                  * any other fields out of the Tx descriptor until
6170                  * we know the status of DescOwn
6171                  */
6172                 dma_rmb();
6173
6174                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6175                                      tp->TxDescArray + entry);
6176                 if (status & LastFrag) {
6177                         pkts_compl++;
6178                         bytes_compl += tx_skb->skb->len;
6179                         napi_consume_skb(tx_skb->skb, budget);
6180                         tx_skb->skb = NULL;
6181                 }
6182                 dirty_tx++;
6183                 tx_left--;
6184         }
6185
6186         if (tp->dirty_tx != dirty_tx) {
6187                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6188
6189                 u64_stats_update_begin(&tp->tx_stats.syncp);
6190                 tp->tx_stats.packets += pkts_compl;
6191                 tp->tx_stats.bytes += bytes_compl;
6192                 u64_stats_update_end(&tp->tx_stats.syncp);
6193
6194                 tp->dirty_tx = dirty_tx;
6195                 /* Sync with rtl8169_start_xmit:
6196                  * - publish dirty_tx ring index (write barrier)
6197                  * - refresh cur_tx ring index and queue status (read barrier)
6198                  * May the current thread miss the stopped queue condition,
6199                  * a racing xmit thread can only have a right view of the
6200                  * ring status.
6201                  */
6202                 smp_mb();
6203                 if (netif_queue_stopped(dev) &&
6204                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6205                         netif_wake_queue(dev);
6206                 }
6207                 /*
6208                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6209                  * too close. Let's kick an extra TxPoll request when a burst
6210                  * of start_xmit activity is detected (if it is not detected,
6211                  * it is slow enough). -- FR
6212                  */
6213                 if (tp->cur_tx != dirty_tx)
6214                         RTL_W8(tp, TxPoll, NPQ);
6215         }
6216 }
6217
6218 static inline int rtl8169_fragmented_frame(u32 status)
6219 {
6220         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6221 }
6222
6223 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6224 {
6225         u32 status = opts1 & RxProtoMask;
6226
6227         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6228             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6229                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6230         else
6231                 skb_checksum_none_assert(skb);
6232 }
6233
6234 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6235                                            struct rtl8169_private *tp,
6236                                            int pkt_size,
6237                                            dma_addr_t addr)
6238 {
6239         struct sk_buff *skb;
6240         struct device *d = tp_to_dev(tp);
6241
6242         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6243         prefetch(data);
6244         skb = napi_alloc_skb(&tp->napi, pkt_size);
6245         if (skb)
6246                 skb_copy_to_linear_data(skb, data, pkt_size);
6247         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6248
6249         return skb;
6250 }
6251
6252 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6253 {
6254         unsigned int cur_rx, rx_left;
6255         unsigned int count;
6256
6257         cur_rx = tp->cur_rx;
6258
6259         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6260                 unsigned int entry = cur_rx % NUM_RX_DESC;
6261                 struct RxDesc *desc = tp->RxDescArray + entry;
6262                 u32 status;
6263
6264                 status = le32_to_cpu(desc->opts1);
6265                 if (status & DescOwn)
6266                         break;
6267
6268                 /* This barrier is needed to keep us from reading
6269                  * any other fields out of the Rx descriptor until
6270                  * we know the status of DescOwn
6271                  */
6272                 dma_rmb();
6273
6274                 if (unlikely(status & RxRES)) {
6275                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6276                                    status);
6277                         dev->stats.rx_errors++;
6278                         if (status & (RxRWT | RxRUNT))
6279                                 dev->stats.rx_length_errors++;
6280                         if (status & RxCRC)
6281                                 dev->stats.rx_crc_errors++;
6282                         /* RxFOVF is a reserved bit on later chip versions */
6283                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6284                             status & RxFOVF) {
6285                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6286                                 dev->stats.rx_fifo_errors++;
6287                         } else if (status & (RxRUNT | RxCRC) &&
6288                                    !(status & RxRWT) &&
6289                                    dev->features & NETIF_F_RXALL) {
6290                                 goto process_pkt;
6291                         }
6292                 } else {
6293                         struct sk_buff *skb;
6294                         dma_addr_t addr;
6295                         int pkt_size;
6296
6297 process_pkt:
6298                         addr = le64_to_cpu(desc->addr);
6299                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6300                                 pkt_size = (status & 0x00003fff) - 4;
6301                         else
6302                                 pkt_size = status & 0x00003fff;
6303
6304                         /*
6305                          * The driver does not support incoming fragmented
6306                          * frames. They are seen as a symptom of over-mtu
6307                          * sized frames.
6308                          */
6309                         if (unlikely(rtl8169_fragmented_frame(status))) {
6310                                 dev->stats.rx_dropped++;
6311                                 dev->stats.rx_length_errors++;
6312                                 goto release_descriptor;
6313                         }
6314
6315                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6316                                                   tp, pkt_size, addr);
6317                         if (!skb) {
6318                                 dev->stats.rx_dropped++;
6319                                 goto release_descriptor;
6320                         }
6321
6322                         rtl8169_rx_csum(skb, status);
6323                         skb_put(skb, pkt_size);
6324                         skb->protocol = eth_type_trans(skb, dev);
6325
6326                         rtl8169_rx_vlan_tag(desc, skb);
6327
6328                         if (skb->pkt_type == PACKET_MULTICAST)
6329                                 dev->stats.multicast++;
6330
6331                         napi_gro_receive(&tp->napi, skb);
6332
6333                         u64_stats_update_begin(&tp->rx_stats.syncp);
6334                         tp->rx_stats.packets++;
6335                         tp->rx_stats.bytes += pkt_size;
6336                         u64_stats_update_end(&tp->rx_stats.syncp);
6337                 }
6338 release_descriptor:
6339                 desc->opts2 = 0;
6340                 rtl8169_mark_to_asic(desc);
6341         }
6342
6343         count = cur_rx - tp->cur_rx;
6344         tp->cur_rx = cur_rx;
6345
6346         return count;
6347 }
6348
6349 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6350 {
6351         struct rtl8169_private *tp = dev_instance;
6352         u16 status = RTL_R16(tp, IntrStatus);
6353
6354         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6355                 return IRQ_NONE;
6356
6357         if (unlikely(status & SYSErr)) {
6358                 rtl8169_pcierr_interrupt(tp->dev);
6359                 goto out;
6360         }
6361
6362         if (status & LinkChg)
6363                 phy_mac_interrupt(tp->phydev);
6364
6365         if (unlikely(status & RxFIFOOver &&
6366             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6367                 netif_stop_queue(tp->dev);
6368                 /* XXX - Hack alert. See rtl_task(). */
6369                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6370         }
6371
6372         rtl_irq_disable(tp);
6373         napi_schedule_irqoff(&tp->napi);
6374 out:
6375         rtl_ack_events(tp, status);
6376
6377         return IRQ_HANDLED;
6378 }
6379
6380 static void rtl_task(struct work_struct *work)
6381 {
6382         static const struct {
6383                 int bitnr;
6384                 void (*action)(struct rtl8169_private *);
6385         } rtl_work[] = {
6386                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6387         };
6388         struct rtl8169_private *tp =
6389                 container_of(work, struct rtl8169_private, wk.work);
6390         struct net_device *dev = tp->dev;
6391         int i;
6392
6393         rtl_lock_work(tp);
6394
6395         if (!netif_running(dev) ||
6396             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6397                 goto out_unlock;
6398
6399         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6400                 bool pending;
6401
6402                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6403                 if (pending)
6404                         rtl_work[i].action(tp);
6405         }
6406
6407 out_unlock:
6408         rtl_unlock_work(tp);
6409 }
6410
6411 static int rtl8169_poll(struct napi_struct *napi, int budget)
6412 {
6413         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6414         struct net_device *dev = tp->dev;
6415         int work_done;
6416
6417         work_done = rtl_rx(dev, tp, (u32) budget);
6418
6419         rtl_tx(dev, tp, budget);
6420
6421         if (work_done < budget) {
6422                 napi_complete_done(napi, work_done);
6423                 rtl_irq_enable(tp);
6424         }
6425
6426         return work_done;
6427 }
6428
6429 static void rtl8169_rx_missed(struct net_device *dev)
6430 {
6431         struct rtl8169_private *tp = netdev_priv(dev);
6432
6433         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6434                 return;
6435
6436         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6437         RTL_W32(tp, RxMissed, 0);
6438 }
6439
6440 static void r8169_phylink_handler(struct net_device *ndev)
6441 {
6442         struct rtl8169_private *tp = netdev_priv(ndev);
6443
6444         if (netif_carrier_ok(ndev)) {
6445                 rtl_link_chg_patch(tp);
6446                 pm_request_resume(&tp->pci_dev->dev);
6447         } else {
6448                 pm_runtime_idle(&tp->pci_dev->dev);
6449         }
6450
6451         if (net_ratelimit())
6452                 phy_print_status(tp->phydev);
6453 }
6454
6455 static int r8169_phy_connect(struct rtl8169_private *tp)
6456 {
6457         struct phy_device *phydev = tp->phydev;
6458         phy_interface_t phy_mode;
6459         int ret;
6460
6461         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6462                    PHY_INTERFACE_MODE_MII;
6463
6464         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6465                                  phy_mode);
6466         if (ret)
6467                 return ret;
6468
6469         if (!tp->supports_gmii)
6470                 phy_set_max_speed(phydev, SPEED_100);
6471
6472         /* Ensure to advertise everything, incl. pause */
6473         linkmode_copy(phydev->advertising, phydev->supported);
6474
6475         phy_attached_info(phydev);
6476
6477         return 0;
6478 }
6479
6480 static void rtl8169_down(struct net_device *dev)
6481 {
6482         struct rtl8169_private *tp = netdev_priv(dev);
6483
6484         phy_stop(tp->phydev);
6485
6486         napi_disable(&tp->napi);
6487         netif_stop_queue(dev);
6488
6489         rtl8169_hw_reset(tp);
6490         /*
6491          * At this point device interrupts can not be enabled in any function,
6492          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6493          * and napi is disabled (rtl8169_poll).
6494          */
6495         rtl8169_rx_missed(dev);
6496
6497         /* Give a racing hard_start_xmit a few cycles to complete. */
6498         synchronize_rcu();
6499
6500         rtl8169_tx_clear(tp);
6501
6502         rtl8169_rx_clear(tp);
6503
6504         rtl_pll_power_down(tp);
6505 }
6506
6507 static int rtl8169_close(struct net_device *dev)
6508 {
6509         struct rtl8169_private *tp = netdev_priv(dev);
6510         struct pci_dev *pdev = tp->pci_dev;
6511
6512         pm_runtime_get_sync(&pdev->dev);
6513
6514         /* Update counters before going down */
6515         rtl8169_update_counters(tp);
6516
6517         rtl_lock_work(tp);
6518         /* Clear all task flags */
6519         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6520
6521         rtl8169_down(dev);
6522         rtl_unlock_work(tp);
6523
6524         cancel_work_sync(&tp->wk.work);
6525
6526         phy_disconnect(tp->phydev);
6527
6528         pci_free_irq(pdev, 0, tp);
6529
6530         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6531                           tp->RxPhyAddr);
6532         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6533                           tp->TxPhyAddr);
6534         tp->TxDescArray = NULL;
6535         tp->RxDescArray = NULL;
6536
6537         pm_runtime_put_sync(&pdev->dev);
6538
6539         return 0;
6540 }
6541
6542 #ifdef CONFIG_NET_POLL_CONTROLLER
6543 static void rtl8169_netpoll(struct net_device *dev)
6544 {
6545         struct rtl8169_private *tp = netdev_priv(dev);
6546
6547         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6548 }
6549 #endif
6550
6551 static int rtl_open(struct net_device *dev)
6552 {
6553         struct rtl8169_private *tp = netdev_priv(dev);
6554         struct pci_dev *pdev = tp->pci_dev;
6555         int retval = -ENOMEM;
6556
6557         pm_runtime_get_sync(&pdev->dev);
6558
6559         /*
6560          * Rx and Tx descriptors needs 256 bytes alignment.
6561          * dma_alloc_coherent provides more.
6562          */
6563         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6564                                              &tp->TxPhyAddr, GFP_KERNEL);
6565         if (!tp->TxDescArray)
6566                 goto err_pm_runtime_put;
6567
6568         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6569                                              &tp->RxPhyAddr, GFP_KERNEL);
6570         if (!tp->RxDescArray)
6571                 goto err_free_tx_0;
6572
6573         retval = rtl8169_init_ring(tp);
6574         if (retval < 0)
6575                 goto err_free_rx_1;
6576
6577         rtl_request_firmware(tp);
6578
6579         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6580                                  dev->name);
6581         if (retval < 0)
6582                 goto err_release_fw_2;
6583
6584         retval = r8169_phy_connect(tp);
6585         if (retval)
6586                 goto err_free_irq;
6587
6588         rtl_lock_work(tp);
6589
6590         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6591
6592         napi_enable(&tp->napi);
6593
6594         rtl8169_init_phy(dev, tp);
6595
6596         rtl_pll_power_up(tp);
6597
6598         rtl_hw_start(tp);
6599
6600         if (!rtl8169_init_counter_offsets(tp))
6601                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6602
6603         phy_start(tp->phydev);
6604         netif_start_queue(dev);
6605
6606         rtl_unlock_work(tp);
6607
6608         pm_runtime_put_sync(&pdev->dev);
6609 out:
6610         return retval;
6611
6612 err_free_irq:
6613         pci_free_irq(pdev, 0, tp);
6614 err_release_fw_2:
6615         rtl_release_firmware(tp);
6616         rtl8169_rx_clear(tp);
6617 err_free_rx_1:
6618         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6619                           tp->RxPhyAddr);
6620         tp->RxDescArray = NULL;
6621 err_free_tx_0:
6622         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6623                           tp->TxPhyAddr);
6624         tp->TxDescArray = NULL;
6625 err_pm_runtime_put:
6626         pm_runtime_put_noidle(&pdev->dev);
6627         goto out;
6628 }
6629
6630 static void
6631 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6632 {
6633         struct rtl8169_private *tp = netdev_priv(dev);
6634         struct pci_dev *pdev = tp->pci_dev;
6635         struct rtl8169_counters *counters = tp->counters;
6636         unsigned int start;
6637
6638         pm_runtime_get_noresume(&pdev->dev);
6639
6640         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6641                 rtl8169_rx_missed(dev);
6642
6643         do {
6644                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6645                 stats->rx_packets = tp->rx_stats.packets;
6646                 stats->rx_bytes = tp->rx_stats.bytes;
6647         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6648
6649         do {
6650                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6651                 stats->tx_packets = tp->tx_stats.packets;
6652                 stats->tx_bytes = tp->tx_stats.bytes;
6653         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6654
6655         stats->rx_dropped       = dev->stats.rx_dropped;
6656         stats->tx_dropped       = dev->stats.tx_dropped;
6657         stats->rx_length_errors = dev->stats.rx_length_errors;
6658         stats->rx_errors        = dev->stats.rx_errors;
6659         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6660         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6661         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6662         stats->multicast        = dev->stats.multicast;
6663
6664         /*
6665          * Fetch additonal counter values missing in stats collected by driver
6666          * from tally counters.
6667          */
6668         if (pm_runtime_active(&pdev->dev))
6669                 rtl8169_update_counters(tp);
6670
6671         /*
6672          * Subtract values fetched during initalization.
6673          * See rtl8169_init_counter_offsets for a description why we do that.
6674          */
6675         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6676                 le64_to_cpu(tp->tc_offset.tx_errors);
6677         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6678                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6679         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6680                 le16_to_cpu(tp->tc_offset.tx_aborted);
6681
6682         pm_runtime_put_noidle(&pdev->dev);
6683 }
6684
6685 static void rtl8169_net_suspend(struct net_device *dev)
6686 {
6687         struct rtl8169_private *tp = netdev_priv(dev);
6688
6689         if (!netif_running(dev))
6690                 return;
6691
6692         phy_stop(tp->phydev);
6693         netif_device_detach(dev);
6694
6695         rtl_lock_work(tp);
6696         napi_disable(&tp->napi);
6697         /* Clear all task flags */
6698         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6699
6700         rtl_unlock_work(tp);
6701
6702         rtl_pll_power_down(tp);
6703 }
6704
6705 #ifdef CONFIG_PM
6706
6707 static int rtl8169_suspend(struct device *device)
6708 {
6709         struct net_device *dev = dev_get_drvdata(device);
6710         struct rtl8169_private *tp = netdev_priv(dev);
6711
6712         rtl8169_net_suspend(dev);
6713         clk_disable_unprepare(tp->clk);
6714
6715         return 0;
6716 }
6717
6718 static void __rtl8169_resume(struct net_device *dev)
6719 {
6720         struct rtl8169_private *tp = netdev_priv(dev);
6721
6722         netif_device_attach(dev);
6723
6724         rtl_pll_power_up(tp);
6725         rtl8169_init_phy(dev, tp);
6726
6727         phy_start(tp->phydev);
6728
6729         rtl_lock_work(tp);
6730         napi_enable(&tp->napi);
6731         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6732         rtl_reset_work(tp);
6733         rtl_unlock_work(tp);
6734 }
6735
6736 static int rtl8169_resume(struct device *device)
6737 {
6738         struct net_device *dev = dev_get_drvdata(device);
6739         struct rtl8169_private *tp = netdev_priv(dev);
6740
6741         clk_prepare_enable(tp->clk);
6742
6743         if (netif_running(dev))
6744                 __rtl8169_resume(dev);
6745
6746         return 0;
6747 }
6748
6749 static int rtl8169_runtime_suspend(struct device *device)
6750 {
6751         struct net_device *dev = dev_get_drvdata(device);
6752         struct rtl8169_private *tp = netdev_priv(dev);
6753
6754         if (!tp->TxDescArray)
6755                 return 0;
6756
6757         rtl_lock_work(tp);
6758         __rtl8169_set_wol(tp, WAKE_ANY);
6759         rtl_unlock_work(tp);
6760
6761         rtl8169_net_suspend(dev);
6762
6763         /* Update counters before going runtime suspend */
6764         rtl8169_rx_missed(dev);
6765         rtl8169_update_counters(tp);
6766
6767         return 0;
6768 }
6769
6770 static int rtl8169_runtime_resume(struct device *device)
6771 {
6772         struct net_device *dev = dev_get_drvdata(device);
6773         struct rtl8169_private *tp = netdev_priv(dev);
6774         rtl_rar_set(tp, dev->dev_addr);
6775
6776         if (!tp->TxDescArray)
6777                 return 0;
6778
6779         rtl_lock_work(tp);
6780         __rtl8169_set_wol(tp, tp->saved_wolopts);
6781         rtl_unlock_work(tp);
6782
6783         __rtl8169_resume(dev);
6784
6785         return 0;
6786 }
6787
6788 static int rtl8169_runtime_idle(struct device *device)
6789 {
6790         struct net_device *dev = dev_get_drvdata(device);
6791
6792         if (!netif_running(dev) || !netif_carrier_ok(dev))
6793                 pm_schedule_suspend(device, 10000);
6794
6795         return -EBUSY;
6796 }
6797
6798 static const struct dev_pm_ops rtl8169_pm_ops = {
6799         .suspend                = rtl8169_suspend,
6800         .resume                 = rtl8169_resume,
6801         .freeze                 = rtl8169_suspend,
6802         .thaw                   = rtl8169_resume,
6803         .poweroff               = rtl8169_suspend,
6804         .restore                = rtl8169_resume,
6805         .runtime_suspend        = rtl8169_runtime_suspend,
6806         .runtime_resume         = rtl8169_runtime_resume,
6807         .runtime_idle           = rtl8169_runtime_idle,
6808 };
6809
6810 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6811
6812 #else /* !CONFIG_PM */
6813
6814 #define RTL8169_PM_OPS  NULL
6815
6816 #endif /* !CONFIG_PM */
6817
6818 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6819 {
6820         /* WoL fails with 8168b when the receiver is disabled. */
6821         switch (tp->mac_version) {
6822         case RTL_GIGA_MAC_VER_11:
6823         case RTL_GIGA_MAC_VER_12:
6824         case RTL_GIGA_MAC_VER_17:
6825                 pci_clear_master(tp->pci_dev);
6826
6827                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6828                 /* PCI commit */
6829                 RTL_R8(tp, ChipCmd);
6830                 break;
6831         default:
6832                 break;
6833         }
6834 }
6835
6836 static void rtl_shutdown(struct pci_dev *pdev)
6837 {
6838         struct net_device *dev = pci_get_drvdata(pdev);
6839         struct rtl8169_private *tp = netdev_priv(dev);
6840
6841         rtl8169_net_suspend(dev);
6842
6843         /* Restore original MAC address */
6844         rtl_rar_set(tp, dev->perm_addr);
6845
6846         rtl8169_hw_reset(tp);
6847
6848         if (system_state == SYSTEM_POWER_OFF) {
6849                 if (tp->saved_wolopts) {
6850                         rtl_wol_suspend_quirk(tp);
6851                         rtl_wol_shutdown_quirk(tp);
6852                 }
6853
6854                 pci_wake_from_d3(pdev, true);
6855                 pci_set_power_state(pdev, PCI_D3hot);
6856         }
6857 }
6858
6859 static void rtl_remove_one(struct pci_dev *pdev)
6860 {
6861         struct net_device *dev = pci_get_drvdata(pdev);
6862         struct rtl8169_private *tp = netdev_priv(dev);
6863
6864         if (r8168_check_dash(tp))
6865                 rtl8168_driver_stop(tp);
6866
6867         netif_napi_del(&tp->napi);
6868
6869         unregister_netdev(dev);
6870         mdiobus_unregister(tp->phydev->mdio.bus);
6871
6872         rtl_release_firmware(tp);
6873
6874         if (pci_dev_run_wake(pdev))
6875                 pm_runtime_get_noresume(&pdev->dev);
6876
6877         /* restore original MAC address */
6878         rtl_rar_set(tp, dev->perm_addr);
6879 }
6880
6881 static const struct net_device_ops rtl_netdev_ops = {
6882         .ndo_open               = rtl_open,
6883         .ndo_stop               = rtl8169_close,
6884         .ndo_get_stats64        = rtl8169_get_stats64,
6885         .ndo_start_xmit         = rtl8169_start_xmit,
6886         .ndo_tx_timeout         = rtl8169_tx_timeout,
6887         .ndo_validate_addr      = eth_validate_addr,
6888         .ndo_change_mtu         = rtl8169_change_mtu,
6889         .ndo_fix_features       = rtl8169_fix_features,
6890         .ndo_set_features       = rtl8169_set_features,
6891         .ndo_set_mac_address    = rtl_set_mac_address,
6892         .ndo_do_ioctl           = rtl8169_ioctl,
6893         .ndo_set_rx_mode        = rtl_set_rx_mode,
6894 #ifdef CONFIG_NET_POLL_CONTROLLER
6895         .ndo_poll_controller    = rtl8169_netpoll,
6896 #endif
6897
6898 };
6899
6900 static const struct rtl_cfg_info {
6901         void (*hw_start)(struct rtl8169_private *tp);
6902         u16 irq_mask;
6903         unsigned int has_gmii:1;
6904         const struct rtl_coalesce_info *coalesce_info;
6905 } rtl_cfg_infos [] = {
6906         [RTL_CFG_0] = {
6907                 .hw_start       = rtl_hw_start_8169,
6908                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6909                 .has_gmii       = 1,
6910                 .coalesce_info  = rtl_coalesce_info_8169,
6911         },
6912         [RTL_CFG_1] = {
6913                 .hw_start       = rtl_hw_start_8168,
6914                 .irq_mask       = LinkChg | RxOverflow,
6915                 .has_gmii       = 1,
6916                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6917         },
6918         [RTL_CFG_2] = {
6919                 .hw_start       = rtl_hw_start_8101,
6920                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6921                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6922         }
6923 };
6924
6925 static int rtl_alloc_irq(struct rtl8169_private *tp)
6926 {
6927         unsigned int flags;
6928
6929         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6930                 rtl_unlock_config_regs(tp);
6931                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6932                 rtl_lock_config_regs(tp);
6933                 flags = PCI_IRQ_LEGACY;
6934         } else {
6935                 flags = PCI_IRQ_ALL_TYPES;
6936         }
6937
6938         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6939 }
6940
6941 static void rtl_read_mac_address(struct rtl8169_private *tp,
6942                                  u8 mac_addr[ETH_ALEN])
6943 {
6944         u32 value;
6945
6946         /* Get MAC address */
6947         switch (tp->mac_version) {
6948         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6949         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6950                 value = rtl_eri_read(tp, 0xe0);
6951                 mac_addr[0] = (value >>  0) & 0xff;
6952                 mac_addr[1] = (value >>  8) & 0xff;
6953                 mac_addr[2] = (value >> 16) & 0xff;
6954                 mac_addr[3] = (value >> 24) & 0xff;
6955
6956                 value = rtl_eri_read(tp, 0xe4);
6957                 mac_addr[4] = (value >>  0) & 0xff;
6958                 mac_addr[5] = (value >>  8) & 0xff;
6959                 break;
6960         default:
6961                 break;
6962         }
6963 }
6964
6965 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6966 {
6967         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6968 }
6969
6970 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6971 {
6972         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6973 }
6974
6975 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6976 {
6977         struct rtl8169_private *tp = mii_bus->priv;
6978
6979         if (phyaddr > 0)
6980                 return -ENODEV;
6981
6982         return rtl_readphy(tp, phyreg);
6983 }
6984
6985 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6986                                 int phyreg, u16 val)
6987 {
6988         struct rtl8169_private *tp = mii_bus->priv;
6989
6990         if (phyaddr > 0)
6991                 return -ENODEV;
6992
6993         rtl_writephy(tp, phyreg, val);
6994
6995         return 0;
6996 }
6997
6998 static int r8169_mdio_register(struct rtl8169_private *tp)
6999 {
7000         struct pci_dev *pdev = tp->pci_dev;
7001         struct mii_bus *new_bus;
7002         int ret;
7003
7004         new_bus = devm_mdiobus_alloc(&pdev->dev);
7005         if (!new_bus)
7006                 return -ENOMEM;
7007
7008         new_bus->name = "r8169";
7009         new_bus->priv = tp;
7010         new_bus->parent = &pdev->dev;
7011         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7012         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7013                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7014
7015         new_bus->read = r8169_mdio_read_reg;
7016         new_bus->write = r8169_mdio_write_reg;
7017
7018         ret = mdiobus_register(new_bus);
7019         if (ret)
7020                 return ret;
7021
7022         tp->phydev = mdiobus_get_phy(new_bus, 0);
7023         if (!tp->phydev) {
7024                 mdiobus_unregister(new_bus);
7025                 return -ENODEV;
7026         }
7027
7028         /* PHY will be woken up in rtl_open() */
7029         phy_suspend(tp->phydev);
7030
7031         return 0;
7032 }
7033
7034 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7035 {
7036         u32 data;
7037
7038         tp->ocp_base = OCP_STD_PHY_BASE;
7039
7040         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7041
7042         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7043                 return;
7044
7045         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7046                 return;
7047
7048         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7049         msleep(1);
7050         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7051
7052         data = r8168_mac_ocp_read(tp, 0xe8de);
7053         data &= ~(1 << 14);
7054         r8168_mac_ocp_write(tp, 0xe8de, data);
7055
7056         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7057                 return;
7058
7059         data = r8168_mac_ocp_read(tp, 0xe8de);
7060         data |= (1 << 15);
7061         r8168_mac_ocp_write(tp, 0xe8de, data);
7062
7063         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7064                 return;
7065 }
7066
7067 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7068 {
7069         rtl8168ep_stop_cmac(tp);
7070         rtl_hw_init_8168g(tp);
7071 }
7072
7073 static void rtl_hw_initialize(struct rtl8169_private *tp)
7074 {
7075         switch (tp->mac_version) {
7076         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7077                 rtl_hw_init_8168g(tp);
7078                 break;
7079         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7080                 rtl_hw_init_8168ep(tp);
7081                 break;
7082         default:
7083                 break;
7084         }
7085 }
7086
7087 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7088 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7089 {
7090         switch (tp->mac_version) {
7091         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7092         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7093                 return false;
7094         default:
7095                 return true;
7096         }
7097 }
7098
7099 static int rtl_jumbo_max(struct rtl8169_private *tp)
7100 {
7101         /* Non-GBit versions don't support jumbo frames */
7102         if (!tp->supports_gmii)
7103                 return JUMBO_1K;
7104
7105         switch (tp->mac_version) {
7106         /* RTL8169 */
7107         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7108                 return JUMBO_7K;
7109         /* RTL8168b */
7110         case RTL_GIGA_MAC_VER_11:
7111         case RTL_GIGA_MAC_VER_12:
7112         case RTL_GIGA_MAC_VER_17:
7113                 return JUMBO_4K;
7114         /* RTL8168c */
7115         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7116                 return JUMBO_6K;
7117         default:
7118                 return JUMBO_9K;
7119         }
7120 }
7121
7122 static void rtl_disable_clk(void *data)
7123 {
7124         clk_disable_unprepare(data);
7125 }
7126
7127 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7128 {
7129         struct device *d = tp_to_dev(tp);
7130         struct clk *clk;
7131         int rc;
7132
7133         clk = devm_clk_get(d, "ether_clk");
7134         if (IS_ERR(clk)) {
7135                 rc = PTR_ERR(clk);
7136                 if (rc == -ENOENT)
7137                         /* clk-core allows NULL (for suspend / resume) */
7138                         rc = 0;
7139                 else if (rc != -EPROBE_DEFER)
7140                         dev_err(d, "failed to get clk: %d\n", rc);
7141         } else {
7142                 tp->clk = clk;
7143                 rc = clk_prepare_enable(clk);
7144                 if (rc)
7145                         dev_err(d, "failed to enable clk: %d\n", rc);
7146                 else
7147                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7148         }
7149
7150         return rc;
7151 }
7152
7153 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7154 {
7155         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7156         /* align to u16 for is_valid_ether_addr() */
7157         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7158         struct rtl8169_private *tp;
7159         struct net_device *dev;
7160         int chipset, region, i;
7161         int jumbo_max, rc;
7162
7163         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7164         if (!dev)
7165                 return -ENOMEM;
7166
7167         SET_NETDEV_DEV(dev, &pdev->dev);
7168         dev->netdev_ops = &rtl_netdev_ops;
7169         tp = netdev_priv(dev);
7170         tp->dev = dev;
7171         tp->pci_dev = pdev;
7172         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7173         tp->supports_gmii = cfg->has_gmii;
7174
7175         /* Get the *optional* external "ether_clk" used on some boards */
7176         rc = rtl_get_ether_clk(tp);
7177         if (rc)
7178                 return rc;
7179
7180         /* Disable ASPM completely as that cause random device stop working
7181          * problems as well as full system hangs for some PCIe devices users.
7182          */
7183         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7184
7185         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7186         rc = pcim_enable_device(pdev);
7187         if (rc < 0) {
7188                 dev_err(&pdev->dev, "enable failure\n");
7189                 return rc;
7190         }
7191
7192         if (pcim_set_mwi(pdev) < 0)
7193                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7194
7195         /* use first MMIO region */
7196         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7197         if (region < 0) {
7198                 dev_err(&pdev->dev, "no MMIO resource found\n");
7199                 return -ENODEV;
7200         }
7201
7202         /* check for weird/broken PCI region reporting */
7203         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7204                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7205                 return -ENODEV;
7206         }
7207
7208         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7209         if (rc < 0) {
7210                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7211                 return rc;
7212         }
7213
7214         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7215
7216         /* Identify chip attached to board */
7217         rtl8169_get_mac_version(tp);
7218         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7219                 return -ENODEV;
7220
7221         if (rtl_tbi_enabled(tp)) {
7222                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7223                 return -ENODEV;
7224         }
7225
7226         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7227
7228         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7229             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7230                 dev->features |= NETIF_F_HIGHDMA;
7231         } else {
7232                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7233                 if (rc < 0) {
7234                         dev_err(&pdev->dev, "DMA configuration failed\n");
7235                         return rc;
7236                 }
7237         }
7238
7239         rtl_init_rxcfg(tp);
7240
7241         rtl8169_irq_mask_and_ack(tp);
7242
7243         rtl_hw_initialize(tp);
7244
7245         rtl_hw_reset(tp);
7246
7247         pci_set_master(pdev);
7248
7249         rtl_init_mdio_ops(tp);
7250         rtl_init_jumbo_ops(tp);
7251
7252         chipset = tp->mac_version;
7253
7254         rc = rtl_alloc_irq(tp);
7255         if (rc < 0) {
7256                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7257                 return rc;
7258         }
7259
7260         mutex_init(&tp->wk.mutex);
7261         INIT_WORK(&tp->wk.work, rtl_task);
7262         u64_stats_init(&tp->rx_stats.syncp);
7263         u64_stats_init(&tp->tx_stats.syncp);
7264
7265         /* get MAC address */
7266         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7267         if (rc)
7268                 rtl_read_mac_address(tp, mac_addr);
7269
7270         if (is_valid_ether_addr(mac_addr))
7271                 rtl_rar_set(tp, mac_addr);
7272
7273         for (i = 0; i < ETH_ALEN; i++)
7274                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7275
7276         dev->ethtool_ops = &rtl8169_ethtool_ops;
7277
7278         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7279
7280         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7281          * properly for all devices */
7282         dev->features |= NETIF_F_RXCSUM |
7283                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7284
7285         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7286                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7287                 NETIF_F_HW_VLAN_CTAG_RX;
7288         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7289                 NETIF_F_HIGHDMA;
7290         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7291
7292         tp->cp_cmd |= RxChkSum | RxVlan;
7293
7294         /*
7295          * Pretend we are using VLANs; This bypasses a nasty bug where
7296          * Interrupts stop flowing on high load on 8110SCd controllers.
7297          */
7298         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7299                 /* Disallow toggling */
7300                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7301
7302         if (rtl_chip_supports_csum_v2(tp)) {
7303                 tp->tso_csum = rtl8169_tso_csum_v2;
7304                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7305         } else {
7306                 tp->tso_csum = rtl8169_tso_csum_v1;
7307         }
7308
7309         dev->hw_features |= NETIF_F_RXALL;
7310         dev->hw_features |= NETIF_F_RXFCS;
7311
7312         /* MTU range: 60 - hw-specific max */
7313         dev->min_mtu = ETH_ZLEN;
7314         jumbo_max = rtl_jumbo_max(tp);
7315         dev->max_mtu = jumbo_max;
7316
7317         tp->hw_start = cfg->hw_start;
7318         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7319         tp->coalesce_info = cfg->coalesce_info;
7320
7321         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7322
7323         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7324                                             &tp->counters_phys_addr,
7325                                             GFP_KERNEL);
7326         if (!tp->counters)
7327                 return -ENOMEM;
7328
7329         pci_set_drvdata(pdev, dev);
7330
7331         rc = r8169_mdio_register(tp);
7332         if (rc)
7333                 return rc;
7334
7335         /* chip gets powered up in rtl_open() */
7336         rtl_pll_power_down(tp);
7337
7338         rc = register_netdev(dev);
7339         if (rc)
7340                 goto err_mdio_unregister;
7341
7342         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7343                    rtl_chip_infos[chipset].name, dev->dev_addr,
7344                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7345                    pci_irq_vector(pdev, 0));
7346
7347         if (jumbo_max > JUMBO_1K)
7348                 netif_info(tp, probe, dev,
7349                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7350                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7351                            "ok" : "ko");
7352
7353         if (r8168_check_dash(tp))
7354                 rtl8168_driver_start(tp);
7355
7356         if (pci_dev_run_wake(pdev))
7357                 pm_runtime_put_sync(&pdev->dev);
7358
7359         return 0;
7360
7361 err_mdio_unregister:
7362         mdiobus_unregister(tp->phydev->mdio.bus);
7363         return rc;
7364 }
7365
7366 static struct pci_driver rtl8169_pci_driver = {
7367         .name           = MODULENAME,
7368         .id_table       = rtl8169_pci_tbl,
7369         .probe          = rtl_init_one,
7370         .remove         = rtl_remove_one,
7371         .shutdown       = rtl_shutdown,
7372         .driver.pm      = RTL8169_PM_OPS,
7373 };
7374
7375 module_pci_driver(rtl8169_pci_driver);