drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #define MODULENAME "r8169"
  35
  36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55
  56 #define R8169_MSG_DEFAULT \
  57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  58
  59 #define TX_SLOTS_AVAIL(tp) \
  60         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  61
  62 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  63 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  64         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  65
  66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68 static const int multicast_filter_limit = 32;
  69
  70 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  79
  80 /* write/read MMIO register */
  81 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  84 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  85 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  86 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  87
  88 enum mac_version {
  89         RTL_GIGA_MAC_VER_01 = 0,
  90         RTL_GIGA_MAC_VER_02,
  91         RTL_GIGA_MAC_VER_03,
  92         RTL_GIGA_MAC_VER_04,
  93         RTL_GIGA_MAC_VER_05,
  94         RTL_GIGA_MAC_VER_06,
  95         RTL_GIGA_MAC_VER_07,
  96         RTL_GIGA_MAC_VER_08,
  97         RTL_GIGA_MAC_VER_09,
  98         RTL_GIGA_MAC_VER_10,
  99         RTL_GIGA_MAC_VER_11,
 100         RTL_GIGA_MAC_VER_12,
 101         RTL_GIGA_MAC_VER_13,
 102         RTL_GIGA_MAC_VER_14,
 103         RTL_GIGA_MAC_VER_15,
 104         RTL_GIGA_MAC_VER_16,
 105         RTL_GIGA_MAC_VER_17,
 106         RTL_GIGA_MAC_VER_18,
 107         RTL_GIGA_MAC_VER_19,
 108         RTL_GIGA_MAC_VER_20,
 109         RTL_GIGA_MAC_VER_21,
 110         RTL_GIGA_MAC_VER_22,
 111         RTL_GIGA_MAC_VER_23,
 112         RTL_GIGA_MAC_VER_24,
 113         RTL_GIGA_MAC_VER_25,
 114         RTL_GIGA_MAC_VER_26,
 115         RTL_GIGA_MAC_VER_27,
 116         RTL_GIGA_MAC_VER_28,
 117         RTL_GIGA_MAC_VER_29,
 118         RTL_GIGA_MAC_VER_30,
 119         RTL_GIGA_MAC_VER_31,
 120         RTL_GIGA_MAC_VER_32,
 121         RTL_GIGA_MAC_VER_33,
 122         RTL_GIGA_MAC_VER_34,
 123         RTL_GIGA_MAC_VER_35,
 124         RTL_GIGA_MAC_VER_36,
 125         RTL_GIGA_MAC_VER_37,
 126         RTL_GIGA_MAC_VER_38,
 127         RTL_GIGA_MAC_VER_39,
 128         RTL_GIGA_MAC_VER_40,
 129         RTL_GIGA_MAC_VER_41,
 130         RTL_GIGA_MAC_VER_42,
 131         RTL_GIGA_MAC_VER_43,
 132         RTL_GIGA_MAC_VER_44,
 133         RTL_GIGA_MAC_VER_45,
 134         RTL_GIGA_MAC_VER_46,
 135         RTL_GIGA_MAC_VER_47,
 136         RTL_GIGA_MAC_VER_48,
 137         RTL_GIGA_MAC_VER_49,
 138         RTL_GIGA_MAC_VER_50,
 139         RTL_GIGA_MAC_VER_51,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 #define JUMBO_1K        ETH_DATA_LEN
 144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149 static const struct {
 150         const char *name;
 151         const char *fw_name;
 152 } rtl_chip_infos[] = {
 153         /* PCI devices. */
 154         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 155         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 156         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 157         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 158         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 159         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 160         /* PCI-E devices. */
 161         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 162         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 163         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 164         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 167         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 169         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 170         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 171         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 172         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 175         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 176         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 177         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 178         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 179         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 180         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 181         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 182         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 184         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 185         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 186         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 187         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 188         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 189         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 190         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 191         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 192         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 193         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 194         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 195         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 196         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 197         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 198         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 199         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 200         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 201         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 202         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 203         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 204         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 205         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 206 };
 207
 208 enum cfg_version {
 209         RTL_CFG_0 = 0x00,
 210         RTL_CFG_1,
 211         RTL_CFG_2
 212 };
 213
 214 static const struct pci_device_id rtl8169_pci_tbl[] = {
 215         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 216         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 217         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 218         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 219         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 220         { PCI_DEVICE(PCI_VENDOR_ID_NCUBE,       0x8168), 0, 0, RTL_CFG_1 },
 221         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 222         { PCI_VENDOR_ID_DLINK,                  0x4300,
 223                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 224         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 225         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 226         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 227         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 228         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 229                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 230         { 0x0001,                               0x8168,
 231                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 232         {0,},
 233 };
 234
 235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 236
 237 static int use_dac = -1;
 238 static struct {
 239         u32 msg_enable;
 240 } debug = { -1 };
 241
 242 enum rtl_registers {
 243         MAC0            = 0,    /* Ethernet hardware address. */
 244         MAC4            = 4,
 245         MAR0            = 8,    /* Multicast filter. */
 246         CounterAddrLow          = 0x10,
 247         CounterAddrHigh         = 0x14,
 248         TxDescStartAddrLow      = 0x20,
 249         TxDescStartAddrHigh     = 0x24,
 250         TxHDescStartAddrLow     = 0x28,
 251         TxHDescStartAddrHigh    = 0x2c,
 252         FLASH           = 0x30,
 253         ERSR            = 0x36,
 254         ChipCmd         = 0x37,
 255         TxPoll          = 0x38,
 256         IntrMask        = 0x3c,
 257         IntrStatus      = 0x3e,
 258
 259         TxConfig        = 0x40,
 260 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 261 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 262
 263         RxConfig        = 0x44,
 264 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 265 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 266 #define RXCFG_FIFO_SHIFT                13
 267                                         /* No threshold before first PCI xfer */
 268 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 269 #define RX_EARLY_OFF                    (1 << 11)
 270 #define RXCFG_DMA_SHIFT                 8
 271                                         /* Unlimited maximum PCI burst. */
 272 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 273
 274         RxMissed        = 0x4c,
 275         Cfg9346         = 0x50,
 276         Config0         = 0x51,
 277         Config1         = 0x52,
 278         Config2         = 0x53,
 279 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 280
 281         Config3         = 0x54,
 282         Config4         = 0x55,
 283         Config5         = 0x56,
 284         MultiIntr       = 0x5c,
 285         PHYAR           = 0x60,
 286         PHYstatus       = 0x6c,
 287         RxMaxSize       = 0xda,
 288         CPlusCmd        = 0xe0,
 289         IntrMitigate    = 0xe2,
 290
 291 #define RTL_COALESCE_MASK       0x0f
 292 #define RTL_COALESCE_SHIFT      4
 293 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 294 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 295
 296         RxDescAddrLow   = 0xe4,
 297         RxDescAddrHigh  = 0xe8,
 298         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 299
 300 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 301
 302         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 303
 304 #define TxPacketMax     (8064 >> 7)
 305 #define EarlySize       0x27
 306
 307         FuncEvent       = 0xf0,
 308         FuncEventMask   = 0xf4,
 309         FuncPresetState = 0xf8,
 310         IBCR0           = 0xf8,
 311         IBCR2           = 0xf9,
 312         IBIMR0          = 0xfa,
 313         IBISR0          = 0xfb,
 314         FuncForceEvent  = 0xfc,
 315 };
 316
 317 enum rtl8168_8101_registers {
 318         CSIDR                   = 0x64,
 319         CSIAR                   = 0x68,
 320 #define CSIAR_FLAG                      0x80000000
 321 #define CSIAR_WRITE_CMD                 0x80000000
 322 #define CSIAR_BYTE_ENABLE               0x0000f000
 323 #define CSIAR_ADDR_MASK                 0x00000fff
 324         PMCH                    = 0x6f,
 325         EPHYAR                  = 0x80,
 326 #define EPHYAR_FLAG                     0x80000000
 327 #define EPHYAR_WRITE_CMD                0x80000000
 328 #define EPHYAR_REG_MASK                 0x1f
 329 #define EPHYAR_REG_SHIFT                16
 330 #define EPHYAR_DATA_MASK                0xffff
 331         DLLPR                   = 0xd0,
 332 #define PFM_EN                          (1 << 6)
 333 #define TX_10M_PS_EN                    (1 << 7)
 334         DBG_REG                 = 0xd1,
 335 #define FIX_NAK_1                       (1 << 4)
 336 #define FIX_NAK_2                       (1 << 3)
 337         TWSI                    = 0xd2,
 338         MCU                     = 0xd3,
 339 #define NOW_IS_OOB                      (1 << 7)
 340 #define TX_EMPTY                        (1 << 5)
 341 #define RX_EMPTY                        (1 << 4)
 342 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 343 #define EN_NDP                          (1 << 3)
 344 #define EN_OOB_RESET                    (1 << 2)
 345 #define LINK_LIST_RDY                   (1 << 1)
 346         EFUSEAR                 = 0xdc,
 347 #define EFUSEAR_FLAG                    0x80000000
 348 #define EFUSEAR_WRITE_CMD               0x80000000
 349 #define EFUSEAR_READ_CMD                0x00000000
 350 #define EFUSEAR_REG_MASK                0x03ff
 351 #define EFUSEAR_REG_SHIFT               8
 352 #define EFUSEAR_DATA_MASK               0xff
 353         MISC_1                  = 0xf2,
 354 #define PFM_D3COLD_EN                   (1 << 6)
 355 };
 356
 357 enum rtl8168_registers {
 358         LED_FREQ                = 0x1a,
 359         EEE_LED                 = 0x1b,
 360         ERIDR                   = 0x70,
 361         ERIAR                   = 0x74,
 362 #define ERIAR_FLAG                      0x80000000
 363 #define ERIAR_WRITE_CMD                 0x80000000
 364 #define ERIAR_READ_CMD                  0x00000000
 365 #define ERIAR_ADDR_BYTE_ALIGN           4
 366 #define ERIAR_TYPE_SHIFT                16
 367 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 368 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 369 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 370 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 371 #define ERIAR_MASK_SHIFT                12
 372 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 373 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 374 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 375 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 376 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 377         EPHY_RXER_NUM           = 0x7c,
 378         OCPDR                   = 0xb0, /* OCP GPHY access */
 379 #define OCPDR_WRITE_CMD                 0x80000000
 380 #define OCPDR_READ_CMD                  0x00000000
 381 #define OCPDR_REG_MASK                  0x7f
 382 #define OCPDR_GPHY_REG_SHIFT            16
 383 #define OCPDR_DATA_MASK                 0xffff
 384         OCPAR                   = 0xb4,
 385 #define OCPAR_FLAG                      0x80000000
 386 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 387 #define OCPAR_GPHY_READ_CMD             0x0000f060
 388         GPHY_OCP                = 0xb8,
 389         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 390         MISC                    = 0xf0, /* 8168e only. */
 391 #define TXPLA_RST                       (1 << 29)
 392 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 393 #define PWM_EN                          (1 << 22)
 394 #define RXDV_GATED_EN                   (1 << 19)
 395 #define EARLY_TALLY_EN                  (1 << 16)
 396 };
 397
 398 enum rtl_register_content {
 399         /* InterruptStatusBits */
 400         SYSErr          = 0x8000,
 401         PCSTimeout      = 0x4000,
 402         SWInt           = 0x0100,
 403         TxDescUnavail   = 0x0080,
 404         RxFIFOOver      = 0x0040,
 405         LinkChg         = 0x0020,
 406         RxOverflow      = 0x0010,
 407         TxErr           = 0x0008,
 408         TxOK            = 0x0004,
 409         RxErr           = 0x0002,
 410         RxOK            = 0x0001,
 411
 412         /* RxStatusDesc */
 413         RxBOVF  = (1 << 24),
 414         RxFOVF  = (1 << 23),
 415         RxRWT   = (1 << 22),
 416         RxRES   = (1 << 21),
 417         RxRUNT  = (1 << 20),
 418         RxCRC   = (1 << 19),
 419
 420         /* ChipCmdBits */
 421         StopReq         = 0x80,
 422         CmdReset        = 0x10,
 423         CmdRxEnb        = 0x08,
 424         CmdTxEnb        = 0x04,
 425         RxBufEmpty      = 0x01,
 426
 427         /* TXPoll register p.5 */
 428         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 429         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 430         FSWInt          = 0x01,         /* Forced software interrupt */
 431
 432         /* Cfg9346Bits */
 433         Cfg9346_Lock    = 0x00,
 434         Cfg9346_Unlock  = 0xc0,
 435
 436         /* rx_mode_bits */
 437         AcceptErr       = 0x20,
 438         AcceptRunt      = 0x10,
 439         AcceptBroadcast = 0x08,
 440         AcceptMulticast = 0x04,
 441         AcceptMyPhys    = 0x02,
 442         AcceptAllPhys   = 0x01,
 443 #define RX_CONFIG_ACCEPT_MASK           0x3f
 444
 445         /* TxConfigBits */
 446         TxInterFrameGapShift = 24,
 447         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 448
 449         /* Config1 register p.24 */
 450         LEDS1           = (1 << 7),
 451         LEDS0           = (1 << 6),
 452         Speed_down      = (1 << 4),
 453         MEMMAP          = (1 << 3),
 454         IOMAP           = (1 << 2),
 455         VPD             = (1 << 1),
 456         PMEnable        = (1 << 0),     /* Power Management Enable */
 457
 458         /* Config2 register p. 25 */
 459         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 460         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 461         PCI_Clock_66MHz = 0x01,
 462         PCI_Clock_33MHz = 0x00,
 463
 464         /* Config3 register p.25 */
 465         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 466         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 467         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 468         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 469         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 470
 471         /* Config4 register */
 472         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 473
 474         /* Config5 register p.27 */
 475         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 476         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 477         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 478         Spi_en          = (1 << 3),
 479         LanWake         = (1 << 1),     /* LanWake enable/disable */
 480         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 481         ASPM_en         = (1 << 0),     /* ASPM enable */
 482
 483         /* CPlusCmd p.31 */
 484         EnableBist      = (1 << 15),    // 8168 8101
 485         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 486         Normal_mode     = (1 << 13),    // unused
 487         Force_half_dup  = (1 << 12),    // 8168 8101
 488         Force_rxflow_en = (1 << 11),    // 8168 8101
 489         Force_txflow_en = (1 << 10),    // 8168 8101
 490         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 491         ASF             = (1 << 8),     // 8168 8101
 492         PktCntrDisable  = (1 << 7),     // 8168 8101
 493         Mac_dbgo_sel    = 0x001c,       // 8168
 494         RxVlan          = (1 << 6),
 495         RxChkSum        = (1 << 5),
 496         PCIDAC          = (1 << 4),
 497         PCIMulRW        = (1 << 3),
 498 #define INTT_MASK       GENMASK(1, 0)
 499         INTT_0          = 0x0000,       // 8168
 500         INTT_1          = 0x0001,       // 8168
 501         INTT_2          = 0x0002,       // 8168
 502         INTT_3          = 0x0003,       // 8168
 503
 504         /* rtl8169_PHYstatus */
 505         TBI_Enable      = 0x80,
 506         TxFlowCtrl      = 0x40,
 507         RxFlowCtrl      = 0x20,
 508         _1000bpsF       = 0x10,
 509         _100bps         = 0x08,
 510         _10bps          = 0x04,
 511         LinkStatus      = 0x02,
 512         FullDup         = 0x01,
 513
 514         /* _TBICSRBit */
 515         TBILinkOK       = 0x02000000,
 516
 517         /* ResetCounterCommand */
 518         CounterReset    = 0x1,
 519
 520         /* DumpCounterCommand */
 521         CounterDump     = 0x8,
 522
 523         /* magic enable v2 */
 524         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 525 };
 526
 527 enum rtl_desc_bit {
 528         /* First doubleword. */
 529         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 530         RingEnd         = (1 << 30), /* End of descriptor ring */
 531         FirstFrag       = (1 << 29), /* First segment of a packet */
 532         LastFrag        = (1 << 28), /* Final segment of a packet */
 533 };
 534
 535 /* Generic case. */
 536 enum rtl_tx_desc_bit {
 537         /* First doubleword. */
 538         TD_LSO          = (1 << 27),            /* Large Send Offload */
 539 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 540
 541         /* Second doubleword. */
 542         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 543 };
 544
 545 /* 8169, 8168b and 810x except 8102e. */
 546 enum rtl_tx_desc_bit_0 {
 547         /* First doubleword. */
 548 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 549         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 550         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 551         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 552 };
 553
 554 /* 8102e, 8168c and beyond. */
 555 enum rtl_tx_desc_bit_1 {
 556         /* First doubleword. */
 557         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 558         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 559 #define GTTCPHO_SHIFT                   18
 560 #define GTTCPHO_MAX                     0x7fU
 561
 562         /* Second doubleword. */
 563 #define TCPHO_SHIFT                     18
 564 #define TCPHO_MAX                       0x3ffU
 565 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 566         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 567         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 568         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 569         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 570 };
 571
 572 enum rtl_rx_desc_bit {
 573         /* Rx private */
 574         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 575         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 576
 577 #define RxProtoUDP      (PID1)
 578 #define RxProtoTCP      (PID0)
 579 #define RxProtoIP       (PID1 | PID0)
 580 #define RxProtoMask     RxProtoIP
 581
 582         IPFail          = (1 << 16), /* IP checksum failed */
 583         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 584         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 585         RxVlanTag       = (1 << 16), /* VLAN tag available */
 586 };
 587
 588 #define RsvdMask        0x3fffc000
 589 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 590
 591 struct TxDesc {
 592         __le32 opts1;
 593         __le32 opts2;
 594         __le64 addr;
 595 };
 596
 597 struct RxDesc {
 598         __le32 opts1;
 599         __le32 opts2;
 600         __le64 addr;
 601 };
 602
 603 struct ring_info {
 604         struct sk_buff  *skb;
 605         u32             len;
 606         u8              __pad[sizeof(void *) - sizeof(u32)];
 607 };
 608
 609 struct rtl8169_counters {
 610         __le64  tx_packets;
 611         __le64  rx_packets;
 612         __le64  tx_errors;
 613         __le32  rx_errors;
 614         __le16  rx_missed;
 615         __le16  align_errors;
 616         __le32  tx_one_collision;
 617         __le32  tx_multi_collision;
 618         __le64  rx_unicast;
 619         __le64  rx_broadcast;
 620         __le32  rx_multicast;
 621         __le16  tx_aborted;
 622         __le16  tx_underun;
 623 };
 624
 625 struct rtl8169_tc_offsets {
 626         bool    inited;
 627         __le64  tx_errors;
 628         __le32  tx_multi_collision;
 629         __le16  tx_aborted;
 630 };
 631
 632 enum rtl_flag {
 633         RTL_FLAG_TASK_ENABLED = 0,
 634         RTL_FLAG_TASK_RESET_PENDING,
 635         RTL_FLAG_MAX
 636 };
 637
 638 struct rtl8169_stats {
 639         u64                     packets;
 640         u64                     bytes;
 641         struct u64_stats_sync   syncp;
 642 };
 643
 644 struct rtl8169_private {
 645         void __iomem *mmio_addr;        /* memory map physical address */
 646         struct pci_dev *pci_dev;
 647         struct net_device *dev;
 648         struct napi_struct napi;
 649         u32 msg_enable;
 650         u16 mac_version;
 651         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 652         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 653         u32 dirty_tx;
 654         struct rtl8169_stats rx_stats;
 655         struct rtl8169_stats tx_stats;
 656         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 657         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 658         dma_addr_t TxPhyAddr;
 659         dma_addr_t RxPhyAddr;
 660         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 661         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 662         u16 cp_cmd;
 663
 664         u16 event_slow;
 665         const struct rtl_coalesce_info *coalesce_info;
 666         struct clk *clk;
 667
 668         struct mdio_ops {
 669                 void (*write)(struct rtl8169_private *, int, int);
 670                 int (*read)(struct rtl8169_private *, int);
 671         } mdio_ops;
 672
 673         struct jumbo_ops {
 674                 void (*enable)(struct rtl8169_private *);
 675                 void (*disable)(struct rtl8169_private *);
 676         } jumbo_ops;
 677
 678         void (*hw_start)(struct rtl8169_private *tp);
 679         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 680
 681         struct {
 682                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 683                 struct mutex mutex;
 684                 struct work_struct work;
 685         } wk;
 686
 687         unsigned supports_gmii:1;
 688         struct mii_bus *mii_bus;
 689         dma_addr_t counters_phys_addr;
 690         struct rtl8169_counters *counters;
 691         struct rtl8169_tc_offsets tc_offset;
 692         u32 saved_wolopts;
 693
 694         struct rtl_fw {
 695                 const struct firmware *fw;
 696
 697 #define RTL_VER_SIZE            32
 698
 699                 char version[RTL_VER_SIZE];
 700
 701                 struct rtl_fw_phy_action {
 702                         __le32 *code;
 703                         size_t size;
 704                 } phy_action;
 705         } *rtl_fw;
 706 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 707
 708         u32 ocp_base;
 709 };
 710
 711 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 712 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 713 module_param(use_dac, int, 0);
 714 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 715 module_param_named(debug, debug.msg_enable, int, 0);
 716 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 717 MODULE_LICENSE("GPL");
 718 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 719 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 720 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 721 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 722 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 723 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 724 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 725 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 726 MODULE_FIRMWARE(FIRMWARE_8402_1);
 727 MODULE_FIRMWARE(FIRMWARE_8411_1);
 728 MODULE_FIRMWARE(FIRMWARE_8411_2);
 729 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 730 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 731 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 732 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 733 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 734 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 735 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 736 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 737
 738 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 739 {
 740         return &tp->pci_dev->dev;
 741 }
 742
 743 static void rtl_lock_work(struct rtl8169_private *tp)
 744 {
 745         mutex_lock(&tp->wk.mutex);
 746 }
 747
 748 static void rtl_unlock_work(struct rtl8169_private *tp)
 749 {
 750         mutex_unlock(&tp->wk.mutex);
 751 }
 752
 753 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 754 {
 755         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 756                                            PCI_EXP_DEVCTL_READRQ, force);
 757 }
 758
 759 struct rtl_cond {
 760         bool (*check)(struct rtl8169_private *);
 761         const char *msg;
 762 };
 763
 764 static void rtl_udelay(unsigned int d)
 765 {
 766         udelay(d);
 767 }
 768
 769 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 770                           void (*delay)(unsigned int), unsigned int d, int n,
 771                           bool high)
 772 {
 773         int i;
 774
 775         for (i = 0; i < n; i++) {
 776                 delay(d);
 777                 if (c->check(tp) == high)
 778                         return true;
 779         }
 780         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 781                   c->msg, !high, n, d);
 782         return false;
 783 }
 784
 785 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 786                                       const struct rtl_cond *c,
 787                                       unsigned int d, int n)
 788 {
 789         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 790 }
 791
 792 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 793                                      const struct rtl_cond *c,
 794                                      unsigned int d, int n)
 795 {
 796         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 797 }
 798
 799 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 800                                       const struct rtl_cond *c,
 801                                       unsigned int d, int n)
 802 {
 803         return rtl_loop_wait(tp, c, msleep, d, n, true);
 804 }
 805
 806 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 807                                      const struct rtl_cond *c,
 808                                      unsigned int d, int n)
 809 {
 810         return rtl_loop_wait(tp, c, msleep, d, n, false);
 811 }
 812
 813 #define DECLARE_RTL_COND(name)                          \
 814 static bool name ## _check(struct rtl8169_private *);   \
 815                                                         \
 816 static const struct rtl_cond name = {                   \
 817         .check  = name ## _check,                       \
 818         .msg    = #name                                 \
 819 };                                                      \
 820                                                         \
 821 static bool name ## _check(struct rtl8169_private *tp)
 822
 823 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 824 {
 825         if (reg & 0xffff0001) {
 826                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 827                 return true;
 828         }
 829         return false;
 830 }
 831
 832 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 833 {
 834         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 835 }
 836
 837 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 838 {
 839         if (rtl_ocp_reg_failure(tp, reg))
 840                 return;
 841
 842         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 843
 844         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 845 }
 846
 847 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 848 {
 849         if (rtl_ocp_reg_failure(tp, reg))
 850                 return 0;
 851
 852         RTL_W32(tp, GPHY_OCP, reg << 15);
 853
 854         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 855                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 856 }
 857
 858 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 859 {
 860         if (rtl_ocp_reg_failure(tp, reg))
 861                 return;
 862
 863         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 864 }
 865
 866 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 867 {
 868         if (rtl_ocp_reg_failure(tp, reg))
 869                 return 0;
 870
 871         RTL_W32(tp, OCPDR, reg << 15);
 872
 873         return RTL_R32(tp, OCPDR);
 874 }
 875
 876 #define OCP_STD_PHY_BASE        0xa400
 877
 878 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 879 {
 880         if (reg == 0x1f) {
 881                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 882                 return;
 883         }
 884
 885         if (tp->ocp_base != OCP_STD_PHY_BASE)
 886                 reg -= 0x10;
 887
 888         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 889 }
 890
 891 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 892 {
 893         if (tp->ocp_base != OCP_STD_PHY_BASE)
 894                 reg -= 0x10;
 895
 896         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 897 }
 898
 899 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 900 {
 901         if (reg == 0x1f) {
 902                 tp->ocp_base = value << 4;
 903                 return;
 904         }
 905
 906         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 907 }
 908
 909 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 910 {
 911         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 912 }
 913
 914 DECLARE_RTL_COND(rtl_phyar_cond)
 915 {
 916         return RTL_R32(tp, PHYAR) & 0x80000000;
 917 }
 918
 919 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 920 {
 921         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 922
 923         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 924         /*
 925          * According to hardware specs a 20us delay is required after write
 926          * complete indication, but before sending next command.
 927          */
 928         udelay(20);
 929 }
 930
 931 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 932 {
 933         int value;
 934
 935         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 936
 937         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 938                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 939
 940         /*
 941          * According to hardware specs a 20us delay is required after read
 942          * complete indication, but before sending next command.
 943          */
 944         udelay(20);
 945
 946         return value;
 947 }
 948
 949 DECLARE_RTL_COND(rtl_ocpar_cond)
 950 {
 951         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 952 }
 953
 954 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 955 {
 956         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 957         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 958         RTL_W32(tp, EPHY_RXER_NUM, 0);
 959
 960         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 961 }
 962
 963 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 964 {
 965         r8168dp_1_mdio_access(tp, reg,
 966                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 967 }
 968
 969 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 970 {
 971         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 972
 973         mdelay(1);
 974         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 975         RTL_W32(tp, EPHY_RXER_NUM, 0);
 976
 977         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 978                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 979 }
 980
 981 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 982
 983 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 984 {
 985         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 986 }
 987
 988 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 989 {
 990         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 991 }
 992
 993 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 994 {
 995         r8168dp_2_mdio_start(tp);
 996
 997         r8169_mdio_write(tp, reg, value);
 998
 999         r8168dp_2_mdio_stop(tp);
1000 }
1001
1002 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1003 {
1004         int value;
1005
1006         r8168dp_2_mdio_start(tp);
1007
1008         value = r8169_mdio_read(tp, reg);
1009
1010         r8168dp_2_mdio_stop(tp);
1011
1012         return value;
1013 }
1014
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1016 {
1017         tp->mdio_ops.write(tp, location, val);
1018 }
1019
1020 static int rtl_readphy(struct rtl8169_private *tp, int location)
1021 {
1022         return tp->mdio_ops.read(tp, location);
1023 }
1024
1025 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1026 {
1027         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1028 }
1029
1030 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1031 {
1032         int val;
1033
1034         val = rtl_readphy(tp, reg_addr);
1035         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1036 }
1037
1038 DECLARE_RTL_COND(rtl_ephyar_cond)
1039 {
1040         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1041 }
1042
1043 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1044 {
1045         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1046                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1047
1048         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1049
1050         udelay(10);
1051 }
1052
1053 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1054 {
1055         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1056
1057         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1058                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1059 }
1060
1061 DECLARE_RTL_COND(rtl_eriar_cond)
1062 {
1063         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1064 }
1065
1066 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1067                           u32 val, int type)
1068 {
1069         BUG_ON((addr & 3) || (mask == 0));
1070         RTL_W32(tp, ERIDR, val);
1071         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1072
1073         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1074 }
1075
1076 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1077 {
1078         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1079
1080         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1081                 RTL_R32(tp, ERIDR) : ~0;
1082 }
1083
1084 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1085                          u32 m, int type)
1086 {
1087         u32 val;
1088
1089         val = rtl_eri_read(tp, addr, type);
1090         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1091 }
1092
1093 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1094 {
1095         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1096         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1097                 RTL_R32(tp, OCPDR) : ~0;
1098 }
1099
1100 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1101 {
1102         return rtl_eri_read(tp, reg, ERIAR_OOB);
1103 }
1104
1105 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1106 {
1107         switch (tp->mac_version) {
1108         case RTL_GIGA_MAC_VER_27:
1109         case RTL_GIGA_MAC_VER_28:
1110         case RTL_GIGA_MAC_VER_31:
1111                 return r8168dp_ocp_read(tp, mask, reg);
1112         case RTL_GIGA_MAC_VER_49:
1113         case RTL_GIGA_MAC_VER_50:
1114         case RTL_GIGA_MAC_VER_51:
1115                 return r8168ep_ocp_read(tp, mask, reg);
1116         default:
1117                 BUG();
1118                 return ~0;
1119         }
1120 }
1121
1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1123                               u32 data)
1124 {
1125         RTL_W32(tp, OCPDR, data);
1126         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1127         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1128 }
1129
1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1131                               u32 data)
1132 {
1133         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1134                       data, ERIAR_OOB);
1135 }
1136
1137 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1138 {
1139         switch (tp->mac_version) {
1140         case RTL_GIGA_MAC_VER_27:
1141         case RTL_GIGA_MAC_VER_28:
1142         case RTL_GIGA_MAC_VER_31:
1143                 r8168dp_ocp_write(tp, mask, reg, data);
1144                 break;
1145         case RTL_GIGA_MAC_VER_49:
1146         case RTL_GIGA_MAC_VER_50:
1147         case RTL_GIGA_MAC_VER_51:
1148                 r8168ep_ocp_write(tp, mask, reg, data);
1149                 break;
1150         default:
1151                 BUG();
1152                 break;
1153         }
1154 }
1155
1156 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1157 {
1158         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1159
1160         ocp_write(tp, 0x1, 0x30, 0x00000001);
1161 }
1162
1163 #define OOB_CMD_RESET           0x00
1164 #define OOB_CMD_DRIVER_START    0x05
1165 #define OOB_CMD_DRIVER_STOP     0x06
1166
1167 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1168 {
1169         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1170 }
1171
1172 DECLARE_RTL_COND(rtl_ocp_read_cond)
1173 {
1174         u16 reg;
1175
1176         reg = rtl8168_get_ocp_reg(tp);
1177
1178         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1179 }
1180
1181 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1182 {
1183         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1184 }
1185
1186 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1187 {
1188         return RTL_R8(tp, IBISR0) & 0x20;
1189 }
1190
1191 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1192 {
1193         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1194         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1195         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1196         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1197 }
1198
1199 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1200 {
1201         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1202         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1203 }
1204
1205 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1206 {
1207         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1208         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1209         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1210 }
1211
1212 static void rtl8168_driver_start(struct rtl8169_private *tp)
1213 {
1214         switch (tp->mac_version) {
1215         case RTL_GIGA_MAC_VER_27:
1216         case RTL_GIGA_MAC_VER_28:
1217         case RTL_GIGA_MAC_VER_31:
1218                 rtl8168dp_driver_start(tp);
1219                 break;
1220         case RTL_GIGA_MAC_VER_49:
1221         case RTL_GIGA_MAC_VER_50:
1222         case RTL_GIGA_MAC_VER_51:
1223                 rtl8168ep_driver_start(tp);
1224                 break;
1225         default:
1226                 BUG();
1227                 break;
1228         }
1229 }
1230
1231 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1232 {
1233         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1234         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1235 }
1236
1237 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1238 {
1239         rtl8168ep_stop_cmac(tp);
1240         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1241         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1242         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1243 }
1244
1245 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1246 {
1247         switch (tp->mac_version) {
1248         case RTL_GIGA_MAC_VER_27:
1249         case RTL_GIGA_MAC_VER_28:
1250         case RTL_GIGA_MAC_VER_31:
1251                 rtl8168dp_driver_stop(tp);
1252                 break;
1253         case RTL_GIGA_MAC_VER_49:
1254         case RTL_GIGA_MAC_VER_50:
1255         case RTL_GIGA_MAC_VER_51:
1256                 rtl8168ep_driver_stop(tp);
1257                 break;
1258         default:
1259                 BUG();
1260                 break;
1261         }
1262 }
1263
1264 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1265 {
1266         u16 reg = rtl8168_get_ocp_reg(tp);
1267
1268         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1269 }
1270
1271 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1272 {
1273         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1274 }
1275
1276 static bool r8168_check_dash(struct rtl8169_private *tp)
1277 {
1278         switch (tp->mac_version) {
1279         case RTL_GIGA_MAC_VER_27:
1280         case RTL_GIGA_MAC_VER_28:
1281         case RTL_GIGA_MAC_VER_31:
1282                 return r8168dp_check_dash(tp);
1283         case RTL_GIGA_MAC_VER_49:
1284         case RTL_GIGA_MAC_VER_50:
1285         case RTL_GIGA_MAC_VER_51:
1286                 return r8168ep_check_dash(tp);
1287         default:
1288                 return false;
1289         }
1290 }
1291
1292 struct exgmac_reg {
1293         u16 addr;
1294         u16 mask;
1295         u32 val;
1296 };
1297
1298 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1299                                    const struct exgmac_reg *r, int len)
1300 {
1301         while (len-- > 0) {
1302                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1303                 r++;
1304         }
1305 }
1306
1307 DECLARE_RTL_COND(rtl_efusear_cond)
1308 {
1309         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1310 }
1311
1312 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1313 {
1314         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1315
1316         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1317                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1318 }
1319
1320 static u16 rtl_get_events(struct rtl8169_private *tp)
1321 {
1322         return RTL_R16(tp, IntrStatus);
1323 }
1324
1325 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1326 {
1327         RTL_W16(tp, IntrStatus, bits);
1328         mmiowb();
1329 }
1330
1331 static void rtl_irq_disable(struct rtl8169_private *tp)
1332 {
1333         RTL_W16(tp, IntrMask, 0);
1334         mmiowb();
1335 }
1336
1337 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1338 {
1339         RTL_W16(tp, IntrMask, bits);
1340 }
1341
1342 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1343 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1344 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1345
1346 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1347 {
1348         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1349 }
1350
1351 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1352 {
1353         rtl_irq_disable(tp);
1354         rtl_ack_events(tp, 0xffff);
1355         /* PCI commit */
1356         RTL_R8(tp, ChipCmd);
1357 }
1358
1359 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1360 {
1361         struct net_device *dev = tp->dev;
1362         struct phy_device *phydev = dev->phydev;
1363
1364         if (!netif_running(dev))
1365                 return;
1366
1367         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1368             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1369                 if (phydev->speed == SPEED_1000) {
1370                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1371                                       ERIAR_EXGMAC);
1372                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1373                                       ERIAR_EXGMAC);
1374                 } else if (phydev->speed == SPEED_100) {
1375                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1376                                       ERIAR_EXGMAC);
1377                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1378                                       ERIAR_EXGMAC);
1379                 } else {
1380                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1381                                       ERIAR_EXGMAC);
1382                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1383                                       ERIAR_EXGMAC);
1384                 }
1385                 /* Reset packet filter */
1386                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1387                              ERIAR_EXGMAC);
1388                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1389                              ERIAR_EXGMAC);
1390         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1391                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1392                 if (phydev->speed == SPEED_1000) {
1393                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1394                                       ERIAR_EXGMAC);
1395                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1396                                       ERIAR_EXGMAC);
1397                 } else {
1398                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1399                                       ERIAR_EXGMAC);
1400                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1401                                       ERIAR_EXGMAC);
1402                 }
1403         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1404                 if (phydev->speed == SPEED_10) {
1405                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1406                                       ERIAR_EXGMAC);
1407                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1408                                       ERIAR_EXGMAC);
1409                 } else {
1410                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1411                                       ERIAR_EXGMAC);
1412                 }
1413         }
1414 }
1415
1416 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1417
1418 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1419 {
1420         u8 options;
1421         u32 wolopts = 0;
1422
1423         options = RTL_R8(tp, Config1);
1424         if (!(options & PMEnable))
1425                 return 0;
1426
1427         options = RTL_R8(tp, Config3);
1428         if (options & LinkUp)
1429                 wolopts |= WAKE_PHY;
1430         switch (tp->mac_version) {
1431         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1432         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1433                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1434                         wolopts |= WAKE_MAGIC;
1435                 break;
1436         default:
1437                 if (options & MagicPacket)
1438                         wolopts |= WAKE_MAGIC;
1439                 break;
1440         }
1441
1442         options = RTL_R8(tp, Config5);
1443         if (options & UWF)
1444                 wolopts |= WAKE_UCAST;
1445         if (options & BWF)
1446                 wolopts |= WAKE_BCAST;
1447         if (options & MWF)
1448                 wolopts |= WAKE_MCAST;
1449
1450         return wolopts;
1451 }
1452
1453 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1454 {
1455         struct rtl8169_private *tp = netdev_priv(dev);
1456
1457         rtl_lock_work(tp);
1458         wol->supported = WAKE_ANY;
1459         wol->wolopts = tp->saved_wolopts;
1460         rtl_unlock_work(tp);
1461 }
1462
1463 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1464 {
1465         unsigned int i, tmp;
1466         static const struct {
1467                 u32 opt;
1468                 u16 reg;
1469                 u8  mask;
1470         } cfg[] = {
1471                 { WAKE_PHY,   Config3, LinkUp },
1472                 { WAKE_UCAST, Config5, UWF },
1473                 { WAKE_BCAST, Config5, BWF },
1474                 { WAKE_MCAST, Config5, MWF },
1475                 { WAKE_ANY,   Config5, LanWake },
1476                 { WAKE_MAGIC, Config3, MagicPacket }
1477         };
1478         u8 options;
1479
1480         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1481
1482         switch (tp->mac_version) {
1483         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1484         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1485                 tmp = ARRAY_SIZE(cfg) - 1;
1486                 if (wolopts & WAKE_MAGIC)
1487                         rtl_w0w1_eri(tp,
1488                                      0x0dc,
1489                                      ERIAR_MASK_0100,
1490                                      MagicPacket_v2,
1491                                      0x0000,
1492                                      ERIAR_EXGMAC);
1493                 else
1494                         rtl_w0w1_eri(tp,
1495                                      0x0dc,
1496                                      ERIAR_MASK_0100,
1497                                      0x0000,
1498                                      MagicPacket_v2,
1499                                      ERIAR_EXGMAC);
1500                 break;
1501         default:
1502                 tmp = ARRAY_SIZE(cfg);
1503                 break;
1504         }
1505
1506         for (i = 0; i < tmp; i++) {
1507                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1508                 if (wolopts & cfg[i].opt)
1509                         options |= cfg[i].mask;
1510                 RTL_W8(tp, cfg[i].reg, options);
1511         }
1512
1513         switch (tp->mac_version) {
1514         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1515                 options = RTL_R8(tp, Config1) & ~PMEnable;
1516                 if (wolopts)
1517                         options |= PMEnable;
1518                 RTL_W8(tp, Config1, options);
1519                 break;
1520         default:
1521                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1522                 if (wolopts)
1523                         options |= PME_SIGNAL;
1524                 RTL_W8(tp, Config2, options);
1525                 break;
1526         }
1527
1528         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1529 }
1530
1531 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1532 {
1533         struct rtl8169_private *tp = netdev_priv(dev);
1534         struct device *d = tp_to_dev(tp);
1535
1536         if (wol->wolopts & ~WAKE_ANY)
1537                 return -EINVAL;
1538
1539         pm_runtime_get_noresume(d);
1540
1541         rtl_lock_work(tp);
1542
1543         tp->saved_wolopts = wol->wolopts;
1544
1545         if (pm_runtime_active(d))
1546                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1547
1548         rtl_unlock_work(tp);
1549
1550         device_set_wakeup_enable(d, tp->saved_wolopts);
1551
1552         pm_runtime_put_noidle(d);
1553
1554         return 0;
1555 }
1556
1557 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1558 {
1559         return rtl_chip_infos[tp->mac_version].fw_name;
1560 }
1561
1562 static void rtl8169_get_drvinfo(struct net_device *dev,
1563                                 struct ethtool_drvinfo *info)
1564 {
1565         struct rtl8169_private *tp = netdev_priv(dev);
1566         struct rtl_fw *rtl_fw = tp->rtl_fw;
1567
1568         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1569         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1570         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1571         if (!IS_ERR_OR_NULL(rtl_fw))
1572                 strlcpy(info->fw_version, rtl_fw->version,
1573                         sizeof(info->fw_version));
1574 }
1575
1576 static int rtl8169_get_regs_len(struct net_device *dev)
1577 {
1578         return R8169_REGS_SIZE;
1579 }
1580
1581 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1582         netdev_features_t features)
1583 {
1584         struct rtl8169_private *tp = netdev_priv(dev);
1585
1586         if (dev->mtu > TD_MSS_MAX)
1587                 features &= ~NETIF_F_ALL_TSO;
1588
1589         if (dev->mtu > JUMBO_1K &&
1590             tp->mac_version > RTL_GIGA_MAC_VER_06)
1591                 features &= ~NETIF_F_IP_CSUM;
1592
1593         return features;
1594 }
1595
1596 static int rtl8169_set_features(struct net_device *dev,
1597                                 netdev_features_t features)
1598 {
1599         struct rtl8169_private *tp = netdev_priv(dev);
1600         u32 rx_config;
1601
1602         rtl_lock_work(tp);
1603
1604         rx_config = RTL_R32(tp, RxConfig);
1605         if (features & NETIF_F_RXALL)
1606                 rx_config |= (AcceptErr | AcceptRunt);
1607         else
1608                 rx_config &= ~(AcceptErr | AcceptRunt);
1609
1610         RTL_W32(tp, RxConfig, rx_config);
1611
1612         if (features & NETIF_F_RXCSUM)
1613                 tp->cp_cmd |= RxChkSum;
1614         else
1615                 tp->cp_cmd &= ~RxChkSum;
1616
1617         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1618                 tp->cp_cmd |= RxVlan;
1619         else
1620                 tp->cp_cmd &= ~RxVlan;
1621
1622         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1623         RTL_R16(tp, CPlusCmd);
1624
1625         rtl_unlock_work(tp);
1626
1627         return 0;
1628 }
1629
1630 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1631 {
1632         return (skb_vlan_tag_present(skb)) ?
1633                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1634 }
1635
1636 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1637 {
1638         u32 opts2 = le32_to_cpu(desc->opts2);
1639
1640         if (opts2 & RxVlanTag)
1641                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1642 }
1643
1644 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1645                              void *p)
1646 {
1647         struct rtl8169_private *tp = netdev_priv(dev);
1648         u32 __iomem *data = tp->mmio_addr;
1649         u32 *dw = p;
1650         int i;
1651
1652         rtl_lock_work(tp);
1653         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1654                 memcpy_fromio(dw++, data++, 4);
1655         rtl_unlock_work(tp);
1656 }
1657
1658 static u32 rtl8169_get_msglevel(struct net_device *dev)
1659 {
1660         struct rtl8169_private *tp = netdev_priv(dev);
1661
1662         return tp->msg_enable;
1663 }
1664
1665 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1666 {
1667         struct rtl8169_private *tp = netdev_priv(dev);
1668
1669         tp->msg_enable = value;
1670 }
1671
1672 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1673         "tx_packets",
1674         "rx_packets",
1675         "tx_errors",
1676         "rx_errors",
1677         "rx_missed",
1678         "align_errors",
1679         "tx_single_collisions",
1680         "tx_multi_collisions",
1681         "unicast",
1682         "broadcast",
1683         "multicast",
1684         "tx_aborted",
1685         "tx_underrun",
1686 };
1687
1688 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1689 {
1690         switch (sset) {
1691         case ETH_SS_STATS:
1692                 return ARRAY_SIZE(rtl8169_gstrings);
1693         default:
1694                 return -EOPNOTSUPP;
1695         }
1696 }
1697
1698 DECLARE_RTL_COND(rtl_counters_cond)
1699 {
1700         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1701 }
1702
1703 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1704 {
1705         dma_addr_t paddr = tp->counters_phys_addr;
1706         u32 cmd;
1707
1708         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1709         RTL_R32(tp, CounterAddrHigh);
1710         cmd = (u64)paddr & DMA_BIT_MASK(32);
1711         RTL_W32(tp, CounterAddrLow, cmd);
1712         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1713
1714         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1715 }
1716
1717 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1718 {
1719         /*
1720          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1721          * tally counters.
1722          */
1723         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1724                 return true;
1725
1726         return rtl8169_do_counters(tp, CounterReset);
1727 }
1728
1729 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1730 {
1731         /*
1732          * Some chips are unable to dump tally counters when the receiver
1733          * is disabled.
1734          */
1735         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1736                 return true;
1737
1738         return rtl8169_do_counters(tp, CounterDump);
1739 }
1740
1741 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1742 {
1743         struct rtl8169_counters *counters = tp->counters;
1744         bool ret = false;
1745
1746         /*
1747          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1748          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1749          * reset by a power cycle, while the counter values collected by the
1750          * driver are reset at every driver unload/load cycle.
1751          *
1752          * To make sure the HW values returned by @get_stats64 match the SW
1753          * values, we collect the initial values at first open(*) and use them
1754          * as offsets to normalize the values returned by @get_stats64.
1755          *
1756          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1757          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1758          * set at open time by rtl_hw_start.
1759          */
1760
1761         if (tp->tc_offset.inited)
1762                 return true;
1763
1764         /* If both, reset and update fail, propagate to caller. */
1765         if (rtl8169_reset_counters(tp))
1766                 ret = true;
1767
1768         if (rtl8169_update_counters(tp))
1769                 ret = true;
1770
1771         tp->tc_offset.tx_errors = counters->tx_errors;
1772         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1773         tp->tc_offset.tx_aborted = counters->tx_aborted;
1774         tp->tc_offset.inited = true;
1775
1776         return ret;
1777 }
1778
1779 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1780                                       struct ethtool_stats *stats, u64 *data)
1781 {
1782         struct rtl8169_private *tp = netdev_priv(dev);
1783         struct device *d = tp_to_dev(tp);
1784         struct rtl8169_counters *counters = tp->counters;
1785
1786         ASSERT_RTNL();
1787
1788         pm_runtime_get_noresume(d);
1789
1790         if (pm_runtime_active(d))
1791                 rtl8169_update_counters(tp);
1792
1793         pm_runtime_put_noidle(d);
1794
1795         data[0] = le64_to_cpu(counters->tx_packets);
1796         data[1] = le64_to_cpu(counters->rx_packets);
1797         data[2] = le64_to_cpu(counters->tx_errors);
1798         data[3] = le32_to_cpu(counters->rx_errors);
1799         data[4] = le16_to_cpu(counters->rx_missed);
1800         data[5] = le16_to_cpu(counters->align_errors);
1801         data[6] = le32_to_cpu(counters->tx_one_collision);
1802         data[7] = le32_to_cpu(counters->tx_multi_collision);
1803         data[8] = le64_to_cpu(counters->rx_unicast);
1804         data[9] = le64_to_cpu(counters->rx_broadcast);
1805         data[10] = le32_to_cpu(counters->rx_multicast);
1806         data[11] = le16_to_cpu(counters->tx_aborted);
1807         data[12] = le16_to_cpu(counters->tx_underun);
1808 }
1809
1810 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1811 {
1812         switch(stringset) {
1813         case ETH_SS_STATS:
1814                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1815                 break;
1816         }
1817 }
1818
1819 /*
1820  * Interrupt coalescing
1821  *
1822  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1823  * >     8169, 8168 and 810x line of chipsets
1824  *
1825  * 8169, 8168, and 8136(810x) serial chipsets support it.
1826  *
1827  * > 2 - the Tx timer unit at gigabit speed
1828  *
1829  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1830  * (0xe0) bit 1 and bit 0.
1831  *
1832  * For 8169
1833  * bit[1:0] \ speed        1000M           100M            10M
1834  * 0 0                     320ns           2.56us          40.96us
1835  * 0 1                     2.56us          20.48us         327.7us
1836  * 1 0                     5.12us          40.96us         655.4us
1837  * 1 1                     10.24us         81.92us         1.31ms
1838  *
1839  * For the other
1840  * bit[1:0] \ speed        1000M           100M            10M
1841  * 0 0                     5us             2.56us          40.96us
1842  * 0 1                     40us            20.48us         327.7us
1843  * 1 0                     80us            40.96us         655.4us
1844  * 1 1                     160us           81.92us         1.31ms
1845  */
1846
1847 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1848 struct rtl_coalesce_scale {
1849         /* Rx / Tx */
1850         u32 nsecs[2];
1851 };
1852
1853 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1854 struct rtl_coalesce_info {
1855         u32 speed;
1856         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1857 };
1858
1859 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1860 #define rxtx_x1822(r, t) {              \
1861         {{(r),          (t)}},          \
1862         {{(r)*8,        (t)*8}},        \
1863         {{(r)*8*2,      (t)*8*2}},      \
1864         {{(r)*8*2*2,    (t)*8*2*2}},    \
1865 }
1866 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1867         /* speed        delays:     rx00   tx00 */
1868         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1869         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1870         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1871         { 0 },
1872 };
1873
1874 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1875         /* speed        delays:     rx00   tx00 */
1876         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1877         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1878         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1879         { 0 },
1880 };
1881 #undef rxtx_x1822
1882
1883 /* get rx/tx scale vector corresponding to current speed */
1884 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1885 {
1886         struct rtl8169_private *tp = netdev_priv(dev);
1887         struct ethtool_link_ksettings ecmd;
1888         const struct rtl_coalesce_info *ci;
1889         int rc;
1890
1891         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1892         if (rc < 0)
1893                 return ERR_PTR(rc);
1894
1895         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1896                 if (ecmd.base.speed == ci->speed) {
1897                         return ci;
1898                 }
1899         }
1900
1901         return ERR_PTR(-ELNRNG);
1902 }
1903
1904 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1905 {
1906         struct rtl8169_private *tp = netdev_priv(dev);
1907         const struct rtl_coalesce_info *ci;
1908         const struct rtl_coalesce_scale *scale;
1909         struct {
1910                 u32 *max_frames;
1911                 u32 *usecs;
1912         } coal_settings [] = {
1913                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1914                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1915         }, *p = coal_settings;
1916         int i;
1917         u16 w;
1918
1919         memset(ec, 0, sizeof(*ec));
1920
1921         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1922         ci = rtl_coalesce_info(dev);
1923         if (IS_ERR(ci))
1924                 return PTR_ERR(ci);
1925
1926         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1927
1928         /* read IntrMitigate and adjust according to scale */
1929         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1930                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1931                 w >>= RTL_COALESCE_SHIFT;
1932                 *p->usecs = w & RTL_COALESCE_MASK;
1933         }
1934
1935         for (i = 0; i < 2; i++) {
1936                 p = coal_settings + i;
1937                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1938
1939                 /*
1940                  * ethtool_coalesce says it is illegal to set both usecs and
1941                  * max_frames to 0.
1942                  */
1943                 if (!*p->usecs && !*p->max_frames)
1944                         *p->max_frames = 1;
1945         }
1946
1947         return 0;
1948 }
1949
1950 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1951 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1952                         struct net_device *dev, u32 nsec, u16 *cp01)
1953 {
1954         const struct rtl_coalesce_info *ci;
1955         u16 i;
1956
1957         ci = rtl_coalesce_info(dev);
1958         if (IS_ERR(ci))
1959                 return ERR_CAST(ci);
1960
1961         for (i = 0; i < 4; i++) {
1962                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1963                                         ci->scalev[i].nsecs[1]);
1964                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1965                         *cp01 = i;
1966                         return &ci->scalev[i];
1967                 }
1968         }
1969
1970         return ERR_PTR(-EINVAL);
1971 }
1972
1973 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1974 {
1975         struct rtl8169_private *tp = netdev_priv(dev);
1976         const struct rtl_coalesce_scale *scale;
1977         struct {
1978                 u32 frames;
1979                 u32 usecs;
1980         } coal_settings [] = {
1981                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1982                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1983         }, *p = coal_settings;
1984         u16 w = 0, cp01;
1985         int i;
1986
1987         scale = rtl_coalesce_choose_scale(dev,
1988                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1989         if (IS_ERR(scale))
1990                 return PTR_ERR(scale);
1991
1992         for (i = 0; i < 2; i++, p++) {
1993                 u32 units;
1994
1995                 /*
1996                  * accept max_frames=1 we returned in rtl_get_coalesce.
1997                  * accept it not only when usecs=0 because of e.g. the following scenario:
1998                  *
1999                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2000                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2001                  * - then user does `ethtool -C eth0 rx-usecs 100`
2002                  *
2003                  * since ethtool sends to kernel whole ethtool_coalesce
2004                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2005                  * we'll reject it below in `frames % 4 != 0`.
2006                  */
2007                 if (p->frames == 1) {
2008                         p->frames = 0;
2009                 }
2010
2011                 units = p->usecs * 1000 / scale->nsecs[i];
2012                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2013                         return -EINVAL;
2014
2015                 w <<= RTL_COALESCE_SHIFT;
2016                 w |= units;
2017                 w <<= RTL_COALESCE_SHIFT;
2018                 w |= p->frames >> 2;
2019         }
2020
2021         rtl_lock_work(tp);
2022
2023         RTL_W16(tp, IntrMitigate, swab16(w));
2024
2025         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2026         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2027         RTL_R16(tp, CPlusCmd);
2028
2029         rtl_unlock_work(tp);
2030
2031         return 0;
2032 }
2033
2034 static const struct ethtool_ops rtl8169_ethtool_ops = {
2035         .get_drvinfo            = rtl8169_get_drvinfo,
2036         .get_regs_len           = rtl8169_get_regs_len,
2037         .get_link               = ethtool_op_get_link,
2038         .get_coalesce           = rtl_get_coalesce,
2039         .set_coalesce           = rtl_set_coalesce,
2040         .get_msglevel           = rtl8169_get_msglevel,
2041         .set_msglevel           = rtl8169_set_msglevel,
2042         .get_regs               = rtl8169_get_regs,
2043         .get_wol                = rtl8169_get_wol,
2044         .set_wol                = rtl8169_set_wol,
2045         .get_strings            = rtl8169_get_strings,
2046         .get_sset_count         = rtl8169_get_sset_count,
2047         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2048         .get_ts_info            = ethtool_op_get_ts_info,
2049         .nway_reset             = phy_ethtool_nway_reset,
2050         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2051         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2052 };
2053
2054 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2055                                     u8 default_version)
2056 {
2057         /*
2058          * The driver currently handles the 8168Bf and the 8168Be identically
2059          * but they can be identified more specifically through the test below
2060          * if needed:
2061          *
2062          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2063          *
2064          * Same thing for the 8101Eb and the 8101Ec:
2065          *
2066          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2067          */
2068         static const struct rtl_mac_info {
2069                 u32 mask;
2070                 u32 val;
2071                 int mac_version;
2072         } mac_info[] = {
2073                 /* 8168EP family. */
2074                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2075                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2076                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2077
2078                 /* 8168H family. */
2079                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2080                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2081
2082                 /* 8168G family. */
2083                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2084                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2085                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2086                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2087
2088                 /* 8168F family. */
2089                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2090                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2091                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2092
2093                 /* 8168E family. */
2094                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2095                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2096                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2097
2098                 /* 8168D family. */
2099                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2100                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2101
2102                 /* 8168DP family. */
2103                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2104                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2105                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2106
2107                 /* 8168C family. */
2108                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2109                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2110                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2111                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2112                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2113                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2114                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2115
2116                 /* 8168B family. */
2117                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2118                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2119                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2120
2121                 /* 8101 family. */
2122                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2123                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2124                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2125                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2126                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2127                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2128                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2129                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2130                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2131                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2132                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2133                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2134                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2135                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2136                 /* FIXME: where did these entries come from ? -- FR */
2137                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2138                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2139
2140                 /* 8110 family. */
2141                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2142                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2143                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2144                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2145                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2146                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2147
2148                 /* Catch-all */
2149                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2150         };
2151         const struct rtl_mac_info *p = mac_info;
2152         u32 reg;
2153
2154         reg = RTL_R32(tp, TxConfig);
2155         while ((reg & p->mask) != p->val)
2156                 p++;
2157         tp->mac_version = p->mac_version;
2158
2159         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2160                 dev_notice(tp_to_dev(tp),
2161                            "unknown MAC, using family default\n");
2162                 tp->mac_version = default_version;
2163         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2164                 tp->mac_version = tp->supports_gmii ?
2165                                   RTL_GIGA_MAC_VER_42 :
2166                                   RTL_GIGA_MAC_VER_43;
2167         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2168                 tp->mac_version = tp->supports_gmii ?
2169                                   RTL_GIGA_MAC_VER_45 :
2170                                   RTL_GIGA_MAC_VER_47;
2171         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2172                 tp->mac_version = tp->supports_gmii ?
2173                                   RTL_GIGA_MAC_VER_46 :
2174                                   RTL_GIGA_MAC_VER_48;
2175         }
2176 }
2177
2178 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2179 {
2180         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2181 }
2182
2183 struct phy_reg {
2184         u16 reg;
2185         u16 val;
2186 };
2187
2188 static void rtl_writephy_batch(struct rtl8169_private *tp,
2189                                const struct phy_reg *regs, int len)
2190 {
2191         while (len-- > 0) {
2192                 rtl_writephy(tp, regs->reg, regs->val);
2193                 regs++;
2194         }
2195 }
2196
2197 #define PHY_READ                0x00000000
2198 #define PHY_DATA_OR             0x10000000
2199 #define PHY_DATA_AND            0x20000000
2200 #define PHY_BJMPN               0x30000000
2201 #define PHY_MDIO_CHG            0x40000000
2202 #define PHY_CLEAR_READCOUNT     0x70000000
2203 #define PHY_WRITE               0x80000000
2204 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2205 #define PHY_COMP_EQ_SKIPN       0xa0000000
2206 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2207 #define PHY_WRITE_PREVIOUS      0xc0000000
2208 #define PHY_SKIPN               0xd0000000
2209 #define PHY_DELAY_MS            0xe0000000
2210
2211 struct fw_info {
2212         u32     magic;
2213         char    version[RTL_VER_SIZE];
2214         __le32  fw_start;
2215         __le32  fw_len;
2216         u8      chksum;
2217 } __packed;
2218
2219 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2220
2221 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2222 {
2223         const struct firmware *fw = rtl_fw->fw;
2224         struct fw_info *fw_info = (struct fw_info *)fw->data;
2225         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2226         char *version = rtl_fw->version;
2227         bool rc = false;
2228
2229         if (fw->size < FW_OPCODE_SIZE)
2230                 goto out;
2231
2232         if (!fw_info->magic) {
2233                 size_t i, size, start;
2234                 u8 checksum = 0;
2235
2236                 if (fw->size < sizeof(*fw_info))
2237                         goto out;
2238
2239                 for (i = 0; i < fw->size; i++)
2240                         checksum += fw->data[i];
2241                 if (checksum != 0)
2242                         goto out;
2243
2244                 start = le32_to_cpu(fw_info->fw_start);
2245                 if (start > fw->size)
2246                         goto out;
2247
2248                 size = le32_to_cpu(fw_info->fw_len);
2249                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2250                         goto out;
2251
2252                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2253
2254                 pa->code = (__le32 *)(fw->data + start);
2255                 pa->size = size;
2256         } else {
2257                 if (fw->size % FW_OPCODE_SIZE)
2258                         goto out;
2259
2260                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2261
2262                 pa->code = (__le32 *)fw->data;
2263                 pa->size = fw->size / FW_OPCODE_SIZE;
2264         }
2265         version[RTL_VER_SIZE - 1] = 0;
2266
2267         rc = true;
2268 out:
2269         return rc;
2270 }
2271
2272 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2273                            struct rtl_fw_phy_action *pa)
2274 {
2275         bool rc = false;
2276         size_t index;
2277
2278         for (index = 0; index < pa->size; index++) {
2279                 u32 action = le32_to_cpu(pa->code[index]);
2280                 u32 regno = (action & 0x0fff0000) >> 16;
2281
2282                 switch(action & 0xf0000000) {
2283                 case PHY_READ:
2284                 case PHY_DATA_OR:
2285                 case PHY_DATA_AND:
2286                 case PHY_MDIO_CHG:
2287                 case PHY_CLEAR_READCOUNT:
2288                 case PHY_WRITE:
2289                 case PHY_WRITE_PREVIOUS:
2290                 case PHY_DELAY_MS:
2291                         break;
2292
2293                 case PHY_BJMPN:
2294                         if (regno > index) {
2295                                 netif_err(tp, ifup, tp->dev,
2296                                           "Out of range of firmware\n");
2297                                 goto out;
2298                         }
2299                         break;
2300                 case PHY_READCOUNT_EQ_SKIP:
2301                         if (index + 2 >= pa->size) {
2302                                 netif_err(tp, ifup, tp->dev,
2303                                           "Out of range of firmware\n");
2304                                 goto out;
2305                         }
2306                         break;
2307                 case PHY_COMP_EQ_SKIPN:
2308                 case PHY_COMP_NEQ_SKIPN:
2309                 case PHY_SKIPN:
2310                         if (index + 1 + regno >= pa->size) {
2311                                 netif_err(tp, ifup, tp->dev,
2312                                           "Out of range of firmware\n");
2313                                 goto out;
2314                         }
2315                         break;
2316
2317                 default:
2318                         netif_err(tp, ifup, tp->dev,
2319                                   "Invalid action 0x%08x\n", action);
2320                         goto out;
2321                 }
2322         }
2323         rc = true;
2324 out:
2325         return rc;
2326 }
2327
2328 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2329 {
2330         struct net_device *dev = tp->dev;
2331         int rc = -EINVAL;
2332
2333         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2334                 netif_err(tp, ifup, dev, "invalid firmware\n");
2335                 goto out;
2336         }
2337
2338         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2339                 rc = 0;
2340 out:
2341         return rc;
2342 }
2343
2344 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2345 {
2346         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2347         struct mdio_ops org, *ops = &tp->mdio_ops;
2348         u32 predata, count;
2349         size_t index;
2350
2351         predata = count = 0;
2352         org.write = ops->write;
2353         org.read = ops->read;
2354
2355         for (index = 0; index < pa->size; ) {
2356                 u32 action = le32_to_cpu(pa->code[index]);
2357                 u32 data = action & 0x0000ffff;
2358                 u32 regno = (action & 0x0fff0000) >> 16;
2359
2360                 if (!action)
2361                         break;
2362
2363                 switch(action & 0xf0000000) {
2364                 case PHY_READ:
2365                         predata = rtl_readphy(tp, regno);
2366                         count++;
2367                         index++;
2368                         break;
2369                 case PHY_DATA_OR:
2370                         predata |= data;
2371                         index++;
2372                         break;
2373                 case PHY_DATA_AND:
2374                         predata &= data;
2375                         index++;
2376                         break;
2377                 case PHY_BJMPN:
2378                         index -= regno;
2379                         break;
2380                 case PHY_MDIO_CHG:
2381                         if (data == 0) {
2382                                 ops->write = org.write;
2383                                 ops->read = org.read;
2384                         } else if (data == 1) {
2385                                 ops->write = mac_mcu_write;
2386                                 ops->read = mac_mcu_read;
2387                         }
2388
2389                         index++;
2390                         break;
2391                 case PHY_CLEAR_READCOUNT:
2392                         count = 0;
2393                         index++;
2394                         break;
2395                 case PHY_WRITE:
2396                         rtl_writephy(tp, regno, data);
2397                         index++;
2398                         break;
2399                 case PHY_READCOUNT_EQ_SKIP:
2400                         index += (count == data) ? 2 : 1;
2401                         break;
2402                 case PHY_COMP_EQ_SKIPN:
2403                         if (predata == data)
2404                                 index += regno;
2405                         index++;
2406                         break;
2407                 case PHY_COMP_NEQ_SKIPN:
2408                         if (predata != data)
2409                                 index += regno;
2410                         index++;
2411                         break;
2412                 case PHY_WRITE_PREVIOUS:
2413                         rtl_writephy(tp, regno, predata);
2414                         index++;
2415                         break;
2416                 case PHY_SKIPN:
2417                         index += regno + 1;
2418                         break;
2419                 case PHY_DELAY_MS:
2420                         mdelay(data);
2421                         index++;
2422                         break;
2423
2424                 default:
2425                         BUG();
2426                 }
2427         }
2428
2429         ops->write = org.write;
2430         ops->read = org.read;
2431 }
2432
2433 static void rtl_release_firmware(struct rtl8169_private *tp)
2434 {
2435         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2436                 release_firmware(tp->rtl_fw->fw);
2437                 kfree(tp->rtl_fw);
2438         }
2439         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2440 }
2441
2442 static void rtl_apply_firmware(struct rtl8169_private *tp)
2443 {
2444         struct rtl_fw *rtl_fw = tp->rtl_fw;
2445
2446         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2447         if (!IS_ERR_OR_NULL(rtl_fw))
2448                 rtl_phy_write_fw(tp, rtl_fw);
2449 }
2450
2451 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2452 {
2453         if (rtl_readphy(tp, reg) != val)
2454                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2455         else
2456                 rtl_apply_firmware(tp);
2457 }
2458
2459 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2460 {
2461         static const struct phy_reg phy_reg_init[] = {
2462                 { 0x1f, 0x0001 },
2463                 { 0x06, 0x006e },
2464                 { 0x08, 0x0708 },
2465                 { 0x15, 0x4000 },
2466                 { 0x18, 0x65c7 },
2467
2468                 { 0x1f, 0x0001 },
2469                 { 0x03, 0x00a1 },
2470                 { 0x02, 0x0008 },
2471                 { 0x01, 0x0120 },
2472                 { 0x00, 0x1000 },
2473                 { 0x04, 0x0800 },
2474                 { 0x04, 0x0000 },
2475
2476                 { 0x03, 0xff41 },
2477                 { 0x02, 0xdf60 },
2478                 { 0x01, 0x0140 },
2479                 { 0x00, 0x0077 },
2480                 { 0x04, 0x7800 },
2481                 { 0x04, 0x7000 },
2482
2483                 { 0x03, 0x802f },
2484                 { 0x02, 0x4f02 },
2485                 { 0x01, 0x0409 },
2486                 { 0x00, 0xf0f9 },
2487                 { 0x04, 0x9800 },
2488                 { 0x04, 0x9000 },
2489
2490                 { 0x03, 0xdf01 },
2491                 { 0x02, 0xdf20 },
2492                 { 0x01, 0xff95 },
2493                 { 0x00, 0xba00 },
2494                 { 0x04, 0xa800 },
2495                 { 0x04, 0xa000 },
2496
2497                 { 0x03, 0xff41 },
2498                 { 0x02, 0xdf20 },
2499                 { 0x01, 0x0140 },
2500                 { 0x00, 0x00bb },
2501                 { 0x04, 0xb800 },
2502                 { 0x04, 0xb000 },
2503
2504                 { 0x03, 0xdf41 },
2505                 { 0x02, 0xdc60 },
2506                 { 0x01, 0x6340 },
2507                 { 0x00, 0x007d },
2508                 { 0x04, 0xd800 },
2509                 { 0x04, 0xd000 },
2510
2511                 { 0x03, 0xdf01 },
2512                 { 0x02, 0xdf20 },
2513                 { 0x01, 0x100a },
2514                 { 0x00, 0xa0ff },
2515                 { 0x04, 0xf800 },
2516                 { 0x04, 0xf000 },
2517
2518                 { 0x1f, 0x0000 },
2519                 { 0x0b, 0x0000 },
2520                 { 0x00, 0x9200 }
2521         };
2522
2523         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2524 }
2525
2526 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2527 {
2528         static const struct phy_reg phy_reg_init[] = {
2529                 { 0x1f, 0x0002 },
2530                 { 0x01, 0x90d0 },
2531                 { 0x1f, 0x0000 }
2532         };
2533
2534         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2535 }
2536
2537 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2538 {
2539         struct pci_dev *pdev = tp->pci_dev;
2540
2541         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2542             (pdev->subsystem_device != 0xe000))
2543                 return;
2544
2545         rtl_writephy(tp, 0x1f, 0x0001);
2546         rtl_writephy(tp, 0x10, 0xf01b);
2547         rtl_writephy(tp, 0x1f, 0x0000);
2548 }
2549
2550 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2551 {
2552         static const struct phy_reg phy_reg_init[] = {
2553                 { 0x1f, 0x0001 },
2554                 { 0x04, 0x0000 },
2555                 { 0x03, 0x00a1 },
2556                 { 0x02, 0x0008 },
2557                 { 0x01, 0x0120 },
2558                 { 0x00, 0x1000 },
2559                 { 0x04, 0x0800 },
2560                 { 0x04, 0x9000 },
2561                 { 0x03, 0x802f },
2562                 { 0x02, 0x4f02 },
2563                 { 0x01, 0x0409 },
2564                 { 0x00, 0xf099 },
2565                 { 0x04, 0x9800 },
2566                 { 0x04, 0xa000 },
2567                 { 0x03, 0xdf01 },
2568                 { 0x02, 0xdf20 },
2569                 { 0x01, 0xff95 },
2570                 { 0x00, 0xba00 },
2571                 { 0x04, 0xa800 },
2572                 { 0x04, 0xf000 },
2573                 { 0x03, 0xdf01 },
2574                 { 0x02, 0xdf20 },
2575                 { 0x01, 0x101a },
2576                 { 0x00, 0xa0ff },
2577                 { 0x04, 0xf800 },
2578                 { 0x04, 0x0000 },
2579                 { 0x1f, 0x0000 },
2580
2581                 { 0x1f, 0x0001 },
2582                 { 0x10, 0xf41b },
2583                 { 0x14, 0xfb54 },
2584                 { 0x18, 0xf5c7 },
2585                 { 0x1f, 0x0000 },
2586
2587                 { 0x1f, 0x0001 },
2588                 { 0x17, 0x0cc0 },
2589                 { 0x1f, 0x0000 }
2590         };
2591
2592         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593
2594         rtl8169scd_hw_phy_config_quirk(tp);
2595 }
2596
2597 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2598 {
2599         static const struct phy_reg phy_reg_init[] = {
2600                 { 0x1f, 0x0001 },
2601                 { 0x04, 0x0000 },
2602                 { 0x03, 0x00a1 },
2603                 { 0x02, 0x0008 },
2604                 { 0x01, 0x0120 },
2605                 { 0x00, 0x1000 },
2606                 { 0x04, 0x0800 },
2607                 { 0x04, 0x9000 },
2608                 { 0x03, 0x802f },
2609                 { 0x02, 0x4f02 },
2610                 { 0x01, 0x0409 },
2611                 { 0x00, 0xf099 },
2612                 { 0x04, 0x9800 },
2613                 { 0x04, 0xa000 },
2614                 { 0x03, 0xdf01 },
2615                 { 0x02, 0xdf20 },
2616                 { 0x01, 0xff95 },
2617                 { 0x00, 0xba00 },
2618                 { 0x04, 0xa800 },
2619                 { 0x04, 0xf000 },
2620                 { 0x03, 0xdf01 },
2621                 { 0x02, 0xdf20 },
2622                 { 0x01, 0x101a },
2623                 { 0x00, 0xa0ff },
2624                 { 0x04, 0xf800 },
2625                 { 0x04, 0x0000 },
2626                 { 0x1f, 0x0000 },
2627
2628                 { 0x1f, 0x0001 },
2629                 { 0x0b, 0x8480 },
2630                 { 0x1f, 0x0000 },
2631
2632                 { 0x1f, 0x0001 },
2633                 { 0x18, 0x67c7 },
2634                 { 0x04, 0x2000 },
2635                 { 0x03, 0x002f },
2636                 { 0x02, 0x4360 },
2637                 { 0x01, 0x0109 },
2638                 { 0x00, 0x3022 },
2639                 { 0x04, 0x2800 },
2640                 { 0x1f, 0x0000 },
2641
2642                 { 0x1f, 0x0001 },
2643                 { 0x17, 0x0cc0 },
2644                 { 0x1f, 0x0000 }
2645         };
2646
2647         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2648 }
2649
2650 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2651 {
2652         static const struct phy_reg phy_reg_init[] = {
2653                 { 0x10, 0xf41b },
2654                 { 0x1f, 0x0000 }
2655         };
2656
2657         rtl_writephy(tp, 0x1f, 0x0001);
2658         rtl_patchphy(tp, 0x16, 1 << 0);
2659
2660         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2661 }
2662
2663 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2664 {
2665         static const struct phy_reg phy_reg_init[] = {
2666                 { 0x1f, 0x0001 },
2667                 { 0x10, 0xf41b },
2668                 { 0x1f, 0x0000 }
2669         };
2670
2671         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2672 }
2673
2674 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2675 {
2676         static const struct phy_reg phy_reg_init[] = {
2677                 { 0x1f, 0x0000 },
2678                 { 0x1d, 0x0f00 },
2679                 { 0x1f, 0x0002 },
2680                 { 0x0c, 0x1ec8 },
2681                 { 0x1f, 0x0000 }
2682         };
2683
2684         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2685 }
2686
2687 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2688 {
2689         static const struct phy_reg phy_reg_init[] = {
2690                 { 0x1f, 0x0001 },
2691                 { 0x1d, 0x3d98 },
2692                 { 0x1f, 0x0000 }
2693         };
2694
2695         rtl_writephy(tp, 0x1f, 0x0000);
2696         rtl_patchphy(tp, 0x14, 1 << 5);
2697         rtl_patchphy(tp, 0x0d, 1 << 5);
2698
2699         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2700 }
2701
2702 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2703 {
2704         static const struct phy_reg phy_reg_init[] = {
2705                 { 0x1f, 0x0001 },
2706                 { 0x12, 0x2300 },
2707                 { 0x1f, 0x0002 },
2708                 { 0x00, 0x88d4 },
2709                 { 0x01, 0x82b1 },
2710                 { 0x03, 0x7002 },
2711                 { 0x08, 0x9e30 },
2712                 { 0x09, 0x01f0 },
2713                 { 0x0a, 0x5500 },
2714                 { 0x0c, 0x00c8 },
2715                 { 0x1f, 0x0003 },
2716                 { 0x12, 0xc096 },
2717                 { 0x16, 0x000a },
2718                 { 0x1f, 0x0000 },
2719                 { 0x1f, 0x0000 },
2720                 { 0x09, 0x2000 },
2721                 { 0x09, 0x0000 }
2722         };
2723
2724         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2725
2726         rtl_patchphy(tp, 0x14, 1 << 5);
2727         rtl_patchphy(tp, 0x0d, 1 << 5);
2728         rtl_writephy(tp, 0x1f, 0x0000);
2729 }
2730
2731 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2732 {
2733         static const struct phy_reg phy_reg_init[] = {
2734                 { 0x1f, 0x0001 },
2735                 { 0x12, 0x2300 },
2736                 { 0x03, 0x802f },
2737                 { 0x02, 0x4f02 },
2738                 { 0x01, 0x0409 },
2739                 { 0x00, 0xf099 },
2740                 { 0x04, 0x9800 },
2741                 { 0x04, 0x9000 },
2742                 { 0x1d, 0x3d98 },
2743                 { 0x1f, 0x0002 },
2744                 { 0x0c, 0x7eb8 },
2745                 { 0x06, 0x0761 },
2746                 { 0x1f, 0x0003 },
2747                 { 0x16, 0x0f0a },
2748                 { 0x1f, 0x0000 }
2749         };
2750
2751         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2752
2753         rtl_patchphy(tp, 0x16, 1 << 0);
2754         rtl_patchphy(tp, 0x14, 1 << 5);
2755         rtl_patchphy(tp, 0x0d, 1 << 5);
2756         rtl_writephy(tp, 0x1f, 0x0000);
2757 }
2758
2759 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2760 {
2761         static const struct phy_reg phy_reg_init[] = {
2762                 { 0x1f, 0x0001 },
2763                 { 0x12, 0x2300 },
2764                 { 0x1d, 0x3d98 },
2765                 { 0x1f, 0x0002 },
2766                 { 0x0c, 0x7eb8 },
2767                 { 0x06, 0x5461 },
2768                 { 0x1f, 0x0003 },
2769                 { 0x16, 0x0f0a },
2770                 { 0x1f, 0x0000 }
2771         };
2772
2773         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2774
2775         rtl_patchphy(tp, 0x16, 1 << 0);
2776         rtl_patchphy(tp, 0x14, 1 << 5);
2777         rtl_patchphy(tp, 0x0d, 1 << 5);
2778         rtl_writephy(tp, 0x1f, 0x0000);
2779 }
2780
2781 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2782 {
2783         rtl8168c_3_hw_phy_config(tp);
2784 }
2785
2786 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2787 {
2788         static const struct phy_reg phy_reg_init_0[] = {
2789                 /* Channel Estimation */
2790                 { 0x1f, 0x0001 },
2791                 { 0x06, 0x4064 },
2792                 { 0x07, 0x2863 },
2793                 { 0x08, 0x059c },
2794                 { 0x09, 0x26b4 },
2795                 { 0x0a, 0x6a19 },
2796                 { 0x0b, 0xdcc8 },
2797                 { 0x10, 0xf06d },
2798                 { 0x14, 0x7f68 },
2799                 { 0x18, 0x7fd9 },
2800                 { 0x1c, 0xf0ff },
2801                 { 0x1d, 0x3d9c },
2802                 { 0x1f, 0x0003 },
2803                 { 0x12, 0xf49f },
2804                 { 0x13, 0x070b },
2805                 { 0x1a, 0x05ad },
2806                 { 0x14, 0x94c0 },
2807
2808                 /*
2809                  * Tx Error Issue
2810                  * Enhance line driver power
2811                  */
2812                 { 0x1f, 0x0002 },
2813                 { 0x06, 0x5561 },
2814                 { 0x1f, 0x0005 },
2815                 { 0x05, 0x8332 },
2816                 { 0x06, 0x5561 },
2817
2818                 /*
2819                  * Can not link to 1Gbps with bad cable
2820                  * Decrease SNR threshold form 21.07dB to 19.04dB
2821                  */
2822                 { 0x1f, 0x0001 },
2823                 { 0x17, 0x0cc0 },
2824
2825                 { 0x1f, 0x0000 },
2826                 { 0x0d, 0xf880 }
2827         };
2828
2829         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2830
2831         /*
2832          * Rx Error Issue
2833          * Fine Tune Switching regulator parameter
2834          */
2835         rtl_writephy(tp, 0x1f, 0x0002);
2836         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2837         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2838
2839         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2840                 static const struct phy_reg phy_reg_init[] = {
2841                         { 0x1f, 0x0002 },
2842                         { 0x05, 0x669a },
2843                         { 0x1f, 0x0005 },
2844                         { 0x05, 0x8330 },
2845                         { 0x06, 0x669a },
2846                         { 0x1f, 0x0002 }
2847                 };
2848                 int val;
2849
2850                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2851
2852                 val = rtl_readphy(tp, 0x0d);
2853
2854                 if ((val & 0x00ff) != 0x006c) {
2855                         static const u32 set[] = {
2856                                 0x0065, 0x0066, 0x0067, 0x0068,
2857                                 0x0069, 0x006a, 0x006b, 0x006c
2858                         };
2859                         int i;
2860
2861                         rtl_writephy(tp, 0x1f, 0x0002);
2862
2863                         val &= 0xff00;
2864                         for (i = 0; i < ARRAY_SIZE(set); i++)
2865                                 rtl_writephy(tp, 0x0d, val | set[i]);
2866                 }
2867         } else {
2868                 static const struct phy_reg phy_reg_init[] = {
2869                         { 0x1f, 0x0002 },
2870                         { 0x05, 0x6662 },
2871                         { 0x1f, 0x0005 },
2872                         { 0x05, 0x8330 },
2873                         { 0x06, 0x6662 }
2874                 };
2875
2876                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2877         }
2878
2879         /* RSET couple improve */
2880         rtl_writephy(tp, 0x1f, 0x0002);
2881         rtl_patchphy(tp, 0x0d, 0x0300);
2882         rtl_patchphy(tp, 0x0f, 0x0010);
2883
2884         /* Fine tune PLL performance */
2885         rtl_writephy(tp, 0x1f, 0x0002);
2886         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2887         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2888
2889         rtl_writephy(tp, 0x1f, 0x0005);
2890         rtl_writephy(tp, 0x05, 0x001b);
2891
2892         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2893
2894         rtl_writephy(tp, 0x1f, 0x0000);
2895 }
2896
2897 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2898 {
2899         static const struct phy_reg phy_reg_init_0[] = {
2900                 /* Channel Estimation */
2901                 { 0x1f, 0x0001 },
2902                 { 0x06, 0x4064 },
2903                 { 0x07, 0x2863 },
2904                 { 0x08, 0x059c },
2905                 { 0x09, 0x26b4 },
2906                 { 0x0a, 0x6a19 },
2907                 { 0x0b, 0xdcc8 },
2908                 { 0x10, 0xf06d },
2909                 { 0x14, 0x7f68 },
2910                 { 0x18, 0x7fd9 },
2911                 { 0x1c, 0xf0ff },
2912                 { 0x1d, 0x3d9c },
2913                 { 0x1f, 0x0003 },
2914                 { 0x12, 0xf49f },
2915                 { 0x13, 0x070b },
2916                 { 0x1a, 0x05ad },
2917                 { 0x14, 0x94c0 },
2918
2919                 /*
2920                  * Tx Error Issue
2921                  * Enhance line driver power
2922                  */
2923                 { 0x1f, 0x0002 },
2924                 { 0x06, 0x5561 },
2925                 { 0x1f, 0x0005 },
2926                 { 0x05, 0x8332 },
2927                 { 0x06, 0x5561 },
2928
2929                 /*
2930                  * Can not link to 1Gbps with bad cable
2931                  * Decrease SNR threshold form 21.07dB to 19.04dB
2932                  */
2933                 { 0x1f, 0x0001 },
2934                 { 0x17, 0x0cc0 },
2935
2936                 { 0x1f, 0x0000 },
2937                 { 0x0d, 0xf880 }
2938         };
2939
2940         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2941
2942         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2943                 static const struct phy_reg phy_reg_init[] = {
2944                         { 0x1f, 0x0002 },
2945                         { 0x05, 0x669a },
2946                         { 0x1f, 0x0005 },
2947                         { 0x05, 0x8330 },
2948                         { 0x06, 0x669a },
2949
2950                         { 0x1f, 0x0002 }
2951                 };
2952                 int val;
2953
2954                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2955
2956                 val = rtl_readphy(tp, 0x0d);
2957                 if ((val & 0x00ff) != 0x006c) {
2958                         static const u32 set[] = {
2959                                 0x0065, 0x0066, 0x0067, 0x0068,
2960                                 0x0069, 0x006a, 0x006b, 0x006c
2961                         };
2962                         int i;
2963
2964                         rtl_writephy(tp, 0x1f, 0x0002);
2965
2966                         val &= 0xff00;
2967                         for (i = 0; i < ARRAY_SIZE(set); i++)
2968                                 rtl_writephy(tp, 0x0d, val | set[i]);
2969                 }
2970         } else {
2971                 static const struct phy_reg phy_reg_init[] = {
2972                         { 0x1f, 0x0002 },
2973                         { 0x05, 0x2642 },
2974                         { 0x1f, 0x0005 },
2975                         { 0x05, 0x8330 },
2976                         { 0x06, 0x2642 }
2977                 };
2978
2979                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2980         }
2981
2982         /* Fine tune PLL performance */
2983         rtl_writephy(tp, 0x1f, 0x0002);
2984         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2985         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2986
2987         /* Switching regulator Slew rate */
2988         rtl_writephy(tp, 0x1f, 0x0002);
2989         rtl_patchphy(tp, 0x0f, 0x0017);
2990
2991         rtl_writephy(tp, 0x1f, 0x0005);
2992         rtl_writephy(tp, 0x05, 0x001b);
2993
2994         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2995
2996         rtl_writephy(tp, 0x1f, 0x0000);
2997 }
2998
2999 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3000 {
3001         static const struct phy_reg phy_reg_init[] = {
3002                 { 0x1f, 0x0002 },
3003                 { 0x10, 0x0008 },
3004                 { 0x0d, 0x006c },
3005
3006                 { 0x1f, 0x0000 },
3007                 { 0x0d, 0xf880 },
3008
3009                 { 0x1f, 0x0001 },
3010                 { 0x17, 0x0cc0 },
3011
3012                 { 0x1f, 0x0001 },
3013                 { 0x0b, 0xa4d8 },
3014                 { 0x09, 0x281c },
3015                 { 0x07, 0x2883 },
3016                 { 0x0a, 0x6b35 },
3017                 { 0x1d, 0x3da4 },
3018                 { 0x1c, 0xeffd },
3019                 { 0x14, 0x7f52 },
3020                 { 0x18, 0x7fc6 },
3021                 { 0x08, 0x0601 },
3022                 { 0x06, 0x4063 },
3023                 { 0x10, 0xf074 },
3024                 { 0x1f, 0x0003 },
3025                 { 0x13, 0x0789 },
3026                 { 0x12, 0xf4bd },
3027                 { 0x1a, 0x04fd },
3028                 { 0x14, 0x84b0 },
3029                 { 0x1f, 0x0000 },
3030                 { 0x00, 0x9200 },
3031
3032                 { 0x1f, 0x0005 },
3033                 { 0x01, 0x0340 },
3034                 { 0x1f, 0x0001 },
3035                 { 0x04, 0x4000 },
3036                 { 0x03, 0x1d21 },
3037                 { 0x02, 0x0c32 },
3038                 { 0x01, 0x0200 },
3039                 { 0x00, 0x5554 },
3040                 { 0x04, 0x4800 },
3041                 { 0x04, 0x4000 },
3042                 { 0x04, 0xf000 },
3043                 { 0x03, 0xdf01 },
3044                 { 0x02, 0xdf20 },
3045                 { 0x01, 0x101a },
3046                 { 0x00, 0xa0ff },
3047                 { 0x04, 0xf800 },
3048                 { 0x04, 0xf000 },
3049                 { 0x1f, 0x0000 },
3050
3051                 { 0x1f, 0x0007 },
3052                 { 0x1e, 0x0023 },
3053                 { 0x16, 0x0000 },
3054                 { 0x1f, 0x0000 }
3055         };
3056
3057         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3058 }
3059
3060 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3061 {
3062         static const struct phy_reg phy_reg_init[] = {
3063                 { 0x1f, 0x0001 },
3064                 { 0x17, 0x0cc0 },
3065
3066                 { 0x1f, 0x0007 },
3067                 { 0x1e, 0x002d },
3068                 { 0x18, 0x0040 },
3069                 { 0x1f, 0x0000 }
3070         };
3071
3072         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3073         rtl_patchphy(tp, 0x0d, 1 << 5);
3074 }
3075
3076 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3077 {
3078         static const struct phy_reg phy_reg_init[] = {
3079                 /* Enable Delay cap */
3080                 { 0x1f, 0x0005 },
3081                 { 0x05, 0x8b80 },
3082                 { 0x06, 0xc896 },
3083                 { 0x1f, 0x0000 },
3084
3085                 /* Channel estimation fine tune */
3086                 { 0x1f, 0x0001 },
3087                 { 0x0b, 0x6c20 },
3088                 { 0x07, 0x2872 },
3089                 { 0x1c, 0xefff },
3090                 { 0x1f, 0x0003 },
3091                 { 0x14, 0x6420 },
3092                 { 0x1f, 0x0000 },
3093
3094                 /* Update PFM & 10M TX idle timer */
3095                 { 0x1f, 0x0007 },
3096                 { 0x1e, 0x002f },
3097                 { 0x15, 0x1919 },
3098                 { 0x1f, 0x0000 },
3099
3100                 { 0x1f, 0x0007 },
3101                 { 0x1e, 0x00ac },
3102                 { 0x18, 0x0006 },
3103                 { 0x1f, 0x0000 }
3104         };
3105
3106         rtl_apply_firmware(tp);
3107
3108         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109
3110         /* DCO enable for 10M IDLE Power */
3111         rtl_writephy(tp, 0x1f, 0x0007);
3112         rtl_writephy(tp, 0x1e, 0x0023);
3113         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3114         rtl_writephy(tp, 0x1f, 0x0000);
3115
3116         /* For impedance matching */
3117         rtl_writephy(tp, 0x1f, 0x0002);
3118         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3119         rtl_writephy(tp, 0x1f, 0x0000);
3120
3121         /* PHY auto speed down */
3122         rtl_writephy(tp, 0x1f, 0x0007);
3123         rtl_writephy(tp, 0x1e, 0x002d);
3124         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3125         rtl_writephy(tp, 0x1f, 0x0000);
3126         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3127
3128         rtl_writephy(tp, 0x1f, 0x0005);
3129         rtl_writephy(tp, 0x05, 0x8b86);
3130         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3131         rtl_writephy(tp, 0x1f, 0x0000);
3132
3133         rtl_writephy(tp, 0x1f, 0x0005);
3134         rtl_writephy(tp, 0x05, 0x8b85);
3135         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3136         rtl_writephy(tp, 0x1f, 0x0007);
3137         rtl_writephy(tp, 0x1e, 0x0020);
3138         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3139         rtl_writephy(tp, 0x1f, 0x0006);
3140         rtl_writephy(tp, 0x00, 0x5a00);
3141         rtl_writephy(tp, 0x1f, 0x0000);
3142         rtl_writephy(tp, 0x0d, 0x0007);
3143         rtl_writephy(tp, 0x0e, 0x003c);
3144         rtl_writephy(tp, 0x0d, 0x4007);
3145         rtl_writephy(tp, 0x0e, 0x0000);
3146         rtl_writephy(tp, 0x0d, 0x0000);
3147 }
3148
3149 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3150 {
3151         const u16 w[] = {
3152                 addr[0] | (addr[1] << 8),
3153                 addr[2] | (addr[3] << 8),
3154                 addr[4] | (addr[5] << 8)
3155         };
3156         const struct exgmac_reg e[] = {
3157                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3158                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3159                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3160                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3161         };
3162
3163         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3164 }
3165
3166 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3167 {
3168         static const struct phy_reg phy_reg_init[] = {
3169                 /* Enable Delay cap */
3170                 { 0x1f, 0x0004 },
3171                 { 0x1f, 0x0007 },
3172                 { 0x1e, 0x00ac },
3173                 { 0x18, 0x0006 },
3174                 { 0x1f, 0x0002 },
3175                 { 0x1f, 0x0000 },
3176                 { 0x1f, 0x0000 },
3177
3178                 /* Channel estimation fine tune */
3179                 { 0x1f, 0x0003 },
3180                 { 0x09, 0xa20f },
3181                 { 0x1f, 0x0000 },
3182                 { 0x1f, 0x0000 },
3183
3184                 /* Green Setting */
3185                 { 0x1f, 0x0005 },
3186                 { 0x05, 0x8b5b },
3187                 { 0x06, 0x9222 },
3188                 { 0x05, 0x8b6d },
3189                 { 0x06, 0x8000 },
3190                 { 0x05, 0x8b76 },
3191                 { 0x06, 0x8000 },
3192                 { 0x1f, 0x0000 }
3193         };
3194
3195         rtl_apply_firmware(tp);
3196
3197         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3198
3199         /* For 4-corner performance improve */
3200         rtl_writephy(tp, 0x1f, 0x0005);
3201         rtl_writephy(tp, 0x05, 0x8b80);
3202         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3203         rtl_writephy(tp, 0x1f, 0x0000);
3204
3205         /* PHY auto speed down */
3206         rtl_writephy(tp, 0x1f, 0x0004);
3207         rtl_writephy(tp, 0x1f, 0x0007);
3208         rtl_writephy(tp, 0x1e, 0x002d);
3209         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3210         rtl_writephy(tp, 0x1f, 0x0002);
3211         rtl_writephy(tp, 0x1f, 0x0000);
3212         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3213
3214         /* improve 10M EEE waveform */
3215         rtl_writephy(tp, 0x1f, 0x0005);
3216         rtl_writephy(tp, 0x05, 0x8b86);
3217         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3218         rtl_writephy(tp, 0x1f, 0x0000);
3219
3220         /* Improve 2-pair detection performance */
3221         rtl_writephy(tp, 0x1f, 0x0005);
3222         rtl_writephy(tp, 0x05, 0x8b85);
3223         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3224         rtl_writephy(tp, 0x1f, 0x0000);
3225
3226         /* EEE setting */
3227         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3228         rtl_writephy(tp, 0x1f, 0x0005);
3229         rtl_writephy(tp, 0x05, 0x8b85);
3230         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3231         rtl_writephy(tp, 0x1f, 0x0004);
3232         rtl_writephy(tp, 0x1f, 0x0007);
3233         rtl_writephy(tp, 0x1e, 0x0020);
3234         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3235         rtl_writephy(tp, 0x1f, 0x0002);
3236         rtl_writephy(tp, 0x1f, 0x0000);
3237         rtl_writephy(tp, 0x0d, 0x0007);
3238         rtl_writephy(tp, 0x0e, 0x003c);
3239         rtl_writephy(tp, 0x0d, 0x4007);
3240         rtl_writephy(tp, 0x0e, 0x0006);
3241         rtl_writephy(tp, 0x0d, 0x0000);
3242
3243         /* Green feature */
3244         rtl_writephy(tp, 0x1f, 0x0003);
3245         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3246         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3247         rtl_writephy(tp, 0x1f, 0x0000);
3248         rtl_writephy(tp, 0x1f, 0x0005);
3249         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3250         rtl_writephy(tp, 0x1f, 0x0000);
3251
3252         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3253         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3254 }
3255
3256 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3257 {
3258         /* For 4-corner performance improve */
3259         rtl_writephy(tp, 0x1f, 0x0005);
3260         rtl_writephy(tp, 0x05, 0x8b80);
3261         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3262         rtl_writephy(tp, 0x1f, 0x0000);
3263
3264         /* PHY auto speed down */
3265         rtl_writephy(tp, 0x1f, 0x0007);
3266         rtl_writephy(tp, 0x1e, 0x002d);
3267         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3268         rtl_writephy(tp, 0x1f, 0x0000);
3269         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3270
3271         /* Improve 10M EEE waveform */
3272         rtl_writephy(tp, 0x1f, 0x0005);
3273         rtl_writephy(tp, 0x05, 0x8b86);
3274         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3275         rtl_writephy(tp, 0x1f, 0x0000);
3276 }
3277
3278 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3279 {
3280         static const struct phy_reg phy_reg_init[] = {
3281                 /* Channel estimation fine tune */
3282                 { 0x1f, 0x0003 },
3283                 { 0x09, 0xa20f },
3284                 { 0x1f, 0x0000 },
3285
3286                 /* Modify green table for giga & fnet */
3287                 { 0x1f, 0x0005 },
3288                 { 0x05, 0x8b55 },
3289                 { 0x06, 0x0000 },
3290                 { 0x05, 0x8b5e },
3291                 { 0x06, 0x0000 },
3292                 { 0x05, 0x8b67 },
3293                 { 0x06, 0x0000 },
3294                 { 0x05, 0x8b70 },
3295                 { 0x06, 0x0000 },
3296                 { 0x1f, 0x0000 },
3297                 { 0x1f, 0x0007 },
3298                 { 0x1e, 0x0078 },
3299                 { 0x17, 0x0000 },
3300                 { 0x19, 0x00fb },
3301                 { 0x1f, 0x0000 },
3302
3303                 /* Modify green table for 10M */
3304                 { 0x1f, 0x0005 },
3305                 { 0x05, 0x8b79 },
3306                 { 0x06, 0xaa00 },
3307                 { 0x1f, 0x0000 },
3308
3309                 /* Disable hiimpedance detection (RTCT) */
3310                 { 0x1f, 0x0003 },
3311                 { 0x01, 0x328a },
3312                 { 0x1f, 0x0000 }
3313         };
3314
3315         rtl_apply_firmware(tp);
3316
3317         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3318
3319         rtl8168f_hw_phy_config(tp);
3320
3321         /* Improve 2-pair detection performance */
3322         rtl_writephy(tp, 0x1f, 0x0005);
3323         rtl_writephy(tp, 0x05, 0x8b85);
3324         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3325         rtl_writephy(tp, 0x1f, 0x0000);
3326 }
3327
3328 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3329 {
3330         rtl_apply_firmware(tp);
3331
3332         rtl8168f_hw_phy_config(tp);
3333 }
3334
3335 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3336 {
3337         static const struct phy_reg phy_reg_init[] = {
3338                 /* Channel estimation fine tune */
3339                 { 0x1f, 0x0003 },
3340                 { 0x09, 0xa20f },
3341                 { 0x1f, 0x0000 },
3342
3343                 /* Modify green table for giga & fnet */
3344                 { 0x1f, 0x0005 },
3345                 { 0x05, 0x8b55 },
3346                 { 0x06, 0x0000 },
3347                 { 0x05, 0x8b5e },
3348                 { 0x06, 0x0000 },
3349                 { 0x05, 0x8b67 },
3350                 { 0x06, 0x0000 },
3351                 { 0x05, 0x8b70 },
3352                 { 0x06, 0x0000 },
3353                 { 0x1f, 0x0000 },
3354                 { 0x1f, 0x0007 },
3355                 { 0x1e, 0x0078 },
3356                 { 0x17, 0x0000 },
3357                 { 0x19, 0x00aa },
3358                 { 0x1f, 0x0000 },
3359
3360                 /* Modify green table for 10M */
3361                 { 0x1f, 0x0005 },
3362                 { 0x05, 0x8b79 },
3363                 { 0x06, 0xaa00 },
3364                 { 0x1f, 0x0000 },
3365
3366                 /* Disable hiimpedance detection (RTCT) */
3367                 { 0x1f, 0x0003 },
3368                 { 0x01, 0x328a },
3369                 { 0x1f, 0x0000 }
3370         };
3371
3372
3373         rtl_apply_firmware(tp);
3374
3375         rtl8168f_hw_phy_config(tp);
3376
3377         /* Improve 2-pair detection performance */
3378         rtl_writephy(tp, 0x1f, 0x0005);
3379         rtl_writephy(tp, 0x05, 0x8b85);
3380         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3381         rtl_writephy(tp, 0x1f, 0x0000);
3382
3383         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3384
3385         /* Modify green table for giga */
3386         rtl_writephy(tp, 0x1f, 0x0005);
3387         rtl_writephy(tp, 0x05, 0x8b54);
3388         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3389         rtl_writephy(tp, 0x05, 0x8b5d);
3390         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3391         rtl_writephy(tp, 0x05, 0x8a7c);
3392         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3393         rtl_writephy(tp, 0x05, 0x8a7f);
3394         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3395         rtl_writephy(tp, 0x05, 0x8a82);
3396         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3397         rtl_writephy(tp, 0x05, 0x8a85);
3398         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3399         rtl_writephy(tp, 0x05, 0x8a88);
3400         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3401         rtl_writephy(tp, 0x1f, 0x0000);
3402
3403         /* uc same-seed solution */
3404         rtl_writephy(tp, 0x1f, 0x0005);
3405         rtl_writephy(tp, 0x05, 0x8b85);
3406         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3407         rtl_writephy(tp, 0x1f, 0x0000);
3408
3409         /* eee setting */
3410         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3411         rtl_writephy(tp, 0x1f, 0x0005);
3412         rtl_writephy(tp, 0x05, 0x8b85);
3413         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3414         rtl_writephy(tp, 0x1f, 0x0004);
3415         rtl_writephy(tp, 0x1f, 0x0007);
3416         rtl_writephy(tp, 0x1e, 0x0020);
3417         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3418         rtl_writephy(tp, 0x1f, 0x0000);
3419         rtl_writephy(tp, 0x0d, 0x0007);
3420         rtl_writephy(tp, 0x0e, 0x003c);
3421         rtl_writephy(tp, 0x0d, 0x4007);
3422         rtl_writephy(tp, 0x0e, 0x0000);
3423         rtl_writephy(tp, 0x0d, 0x0000);
3424
3425         /* Green feature */
3426         rtl_writephy(tp, 0x1f, 0x0003);
3427         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3428         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3429         rtl_writephy(tp, 0x1f, 0x0000);
3430 }
3431
3432 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3433 {
3434         rtl_apply_firmware(tp);
3435
3436         rtl_writephy(tp, 0x1f, 0x0a46);
3437         if (rtl_readphy(tp, 0x10) & 0x0100) {
3438                 rtl_writephy(tp, 0x1f, 0x0bcc);
3439                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3440         } else {
3441                 rtl_writephy(tp, 0x1f, 0x0bcc);
3442                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3443         }
3444
3445         rtl_writephy(tp, 0x1f, 0x0a46);
3446         if (rtl_readphy(tp, 0x13) & 0x0100) {
3447                 rtl_writephy(tp, 0x1f, 0x0c41);
3448                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3449         } else {
3450                 rtl_writephy(tp, 0x1f, 0x0c41);
3451                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3452         }
3453
3454         /* Enable PHY auto speed down */
3455         rtl_writephy(tp, 0x1f, 0x0a44);
3456         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3457
3458         rtl_writephy(tp, 0x1f, 0x0bcc);
3459         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3460         rtl_writephy(tp, 0x1f, 0x0a44);
3461         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3462         rtl_writephy(tp, 0x1f, 0x0a43);
3463         rtl_writephy(tp, 0x13, 0x8084);
3464         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3465         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3466
3467         /* EEE auto-fallback function */
3468         rtl_writephy(tp, 0x1f, 0x0a4b);
3469         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3470
3471         /* Enable UC LPF tune function */
3472         rtl_writephy(tp, 0x1f, 0x0a43);
3473         rtl_writephy(tp, 0x13, 0x8012);
3474         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3475
3476         rtl_writephy(tp, 0x1f, 0x0c42);
3477         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3478
3479         /* Improve SWR Efficiency */
3480         rtl_writephy(tp, 0x1f, 0x0bcd);
3481         rtl_writephy(tp, 0x14, 0x5065);
3482         rtl_writephy(tp, 0x14, 0xd065);
3483         rtl_writephy(tp, 0x1f, 0x0bc8);
3484         rtl_writephy(tp, 0x11, 0x5655);
3485         rtl_writephy(tp, 0x1f, 0x0bcd);
3486         rtl_writephy(tp, 0x14, 0x1065);
3487         rtl_writephy(tp, 0x14, 0x9065);
3488         rtl_writephy(tp, 0x14, 0x1065);
3489
3490         /* Check ALDPS bit, disable it if enabled */
3491         rtl_writephy(tp, 0x1f, 0x0a43);
3492         if (rtl_readphy(tp, 0x10) & 0x0004)
3493                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3494
3495         rtl_writephy(tp, 0x1f, 0x0000);
3496 }
3497
3498 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3499 {
3500         rtl_apply_firmware(tp);
3501 }
3502
3503 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3504 {
3505         u16 dout_tapbin;
3506         u32 data;
3507
3508         rtl_apply_firmware(tp);
3509
3510         /* CHN EST parameters adjust - giga master */
3511         rtl_writephy(tp, 0x1f, 0x0a43);
3512         rtl_writephy(tp, 0x13, 0x809b);
3513         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3514         rtl_writephy(tp, 0x13, 0x80a2);
3515         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3516         rtl_writephy(tp, 0x13, 0x80a4);
3517         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3518         rtl_writephy(tp, 0x13, 0x809c);
3519         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3520         rtl_writephy(tp, 0x1f, 0x0000);
3521
3522         /* CHN EST parameters adjust - giga slave */
3523         rtl_writephy(tp, 0x1f, 0x0a43);
3524         rtl_writephy(tp, 0x13, 0x80ad);
3525         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3526         rtl_writephy(tp, 0x13, 0x80b4);
3527         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3528         rtl_writephy(tp, 0x13, 0x80ac);
3529         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3530         rtl_writephy(tp, 0x1f, 0x0000);
3531
3532         /* CHN EST parameters adjust - fnet */
3533         rtl_writephy(tp, 0x1f, 0x0a43);
3534         rtl_writephy(tp, 0x13, 0x808e);
3535         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3536         rtl_writephy(tp, 0x13, 0x8090);
3537         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3538         rtl_writephy(tp, 0x13, 0x8092);
3539         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3540         rtl_writephy(tp, 0x1f, 0x0000);
3541
3542         /* enable R-tune & PGA-retune function */
3543         dout_tapbin = 0;
3544         rtl_writephy(tp, 0x1f, 0x0a46);
3545         data = rtl_readphy(tp, 0x13);
3546         data &= 3;
3547         data <<= 2;
3548         dout_tapbin |= data;
3549         data = rtl_readphy(tp, 0x12);
3550         data &= 0xc000;
3551         data >>= 14;
3552         dout_tapbin |= data;
3553         dout_tapbin = ~(dout_tapbin^0x08);
3554         dout_tapbin <<= 12;
3555         dout_tapbin &= 0xf000;
3556         rtl_writephy(tp, 0x1f, 0x0a43);
3557         rtl_writephy(tp, 0x13, 0x827a);
3558         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3559         rtl_writephy(tp, 0x13, 0x827b);
3560         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3561         rtl_writephy(tp, 0x13, 0x827c);
3562         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3563         rtl_writephy(tp, 0x13, 0x827d);
3564         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3565
3566         rtl_writephy(tp, 0x1f, 0x0a43);
3567         rtl_writephy(tp, 0x13, 0x0811);
3568         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3569         rtl_writephy(tp, 0x1f, 0x0a42);
3570         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3571         rtl_writephy(tp, 0x1f, 0x0000);
3572
3573         /* enable GPHY 10M */
3574         rtl_writephy(tp, 0x1f, 0x0a44);
3575         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3576         rtl_writephy(tp, 0x1f, 0x0000);
3577
3578         /* SAR ADC performance */
3579         rtl_writephy(tp, 0x1f, 0x0bca);
3580         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3581         rtl_writephy(tp, 0x1f, 0x0000);
3582
3583         rtl_writephy(tp, 0x1f, 0x0a43);
3584         rtl_writephy(tp, 0x13, 0x803f);
3585         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3586         rtl_writephy(tp, 0x13, 0x8047);
3587         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3588         rtl_writephy(tp, 0x13, 0x804f);
3589         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3590         rtl_writephy(tp, 0x13, 0x8057);
3591         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3592         rtl_writephy(tp, 0x13, 0x805f);
3593         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3594         rtl_writephy(tp, 0x13, 0x8067);
3595         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3596         rtl_writephy(tp, 0x13, 0x806f);
3597         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3598         rtl_writephy(tp, 0x1f, 0x0000);
3599
3600         /* disable phy pfm mode */
3601         rtl_writephy(tp, 0x1f, 0x0a44);
3602         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3603         rtl_writephy(tp, 0x1f, 0x0000);
3604
3605         /* Check ALDPS bit, disable it if enabled */
3606         rtl_writephy(tp, 0x1f, 0x0a43);
3607         if (rtl_readphy(tp, 0x10) & 0x0004)
3608                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3609
3610         rtl_writephy(tp, 0x1f, 0x0000);
3611 }
3612
3613 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3614 {
3615         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3616         u16 rlen;
3617         u32 data;
3618
3619         rtl_apply_firmware(tp);
3620
3621         /* CHIN EST parameter update */
3622         rtl_writephy(tp, 0x1f, 0x0a43);
3623         rtl_writephy(tp, 0x13, 0x808a);
3624         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3625         rtl_writephy(tp, 0x1f, 0x0000);
3626
3627         /* enable R-tune & PGA-retune function */
3628         rtl_writephy(tp, 0x1f, 0x0a43);
3629         rtl_writephy(tp, 0x13, 0x0811);
3630         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3631         rtl_writephy(tp, 0x1f, 0x0a42);
3632         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3633         rtl_writephy(tp, 0x1f, 0x0000);
3634
3635         /* enable GPHY 10M */
3636         rtl_writephy(tp, 0x1f, 0x0a44);
3637         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3638         rtl_writephy(tp, 0x1f, 0x0000);
3639
3640         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3641         data = r8168_mac_ocp_read(tp, 0xdd02);
3642         ioffset_p3 = ((data & 0x80)>>7);
3643         ioffset_p3 <<= 3;
3644
3645         data = r8168_mac_ocp_read(tp, 0xdd00);
3646         ioffset_p3 |= ((data & (0xe000))>>13);
3647         ioffset_p2 = ((data & (0x1e00))>>9);
3648         ioffset_p1 = ((data & (0x01e0))>>5);
3649         ioffset_p0 = ((data & 0x0010)>>4);
3650         ioffset_p0 <<= 3;
3651         ioffset_p0 |= (data & (0x07));
3652         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3653
3654         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3655             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3656                 rtl_writephy(tp, 0x1f, 0x0bcf);
3657                 rtl_writephy(tp, 0x16, data);
3658                 rtl_writephy(tp, 0x1f, 0x0000);
3659         }
3660
3661         /* Modify rlen (TX LPF corner frequency) level */
3662         rtl_writephy(tp, 0x1f, 0x0bcd);
3663         data = rtl_readphy(tp, 0x16);
3664         data &= 0x000f;
3665         rlen = 0;
3666         if (data > 3)
3667                 rlen = data - 3;
3668         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3669         rtl_writephy(tp, 0x17, data);
3670         rtl_writephy(tp, 0x1f, 0x0bcd);
3671         rtl_writephy(tp, 0x1f, 0x0000);
3672
3673         /* disable phy pfm mode */
3674         rtl_writephy(tp, 0x1f, 0x0a44);
3675         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3676         rtl_writephy(tp, 0x1f, 0x0000);
3677
3678         /* Check ALDPS bit, disable it if enabled */
3679         rtl_writephy(tp, 0x1f, 0x0a43);
3680         if (rtl_readphy(tp, 0x10) & 0x0004)
3681                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3682
3683         rtl_writephy(tp, 0x1f, 0x0000);
3684 }
3685
3686 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3687 {
3688         /* Enable PHY auto speed down */
3689         rtl_writephy(tp, 0x1f, 0x0a44);
3690         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3691         rtl_writephy(tp, 0x1f, 0x0000);
3692
3693         /* patch 10M & ALDPS */
3694         rtl_writephy(tp, 0x1f, 0x0bcc);
3695         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3696         rtl_writephy(tp, 0x1f, 0x0a44);
3697         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3698         rtl_writephy(tp, 0x1f, 0x0a43);
3699         rtl_writephy(tp, 0x13, 0x8084);
3700         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3701         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3702         rtl_writephy(tp, 0x1f, 0x0000);
3703
3704         /* Enable EEE auto-fallback function */
3705         rtl_writephy(tp, 0x1f, 0x0a4b);
3706         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3707         rtl_writephy(tp, 0x1f, 0x0000);
3708
3709         /* Enable UC LPF tune function */
3710         rtl_writephy(tp, 0x1f, 0x0a43);
3711         rtl_writephy(tp, 0x13, 0x8012);
3712         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3713         rtl_writephy(tp, 0x1f, 0x0000);
3714
3715         /* set rg_sel_sdm_rate */
3716         rtl_writephy(tp, 0x1f, 0x0c42);
3717         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3718         rtl_writephy(tp, 0x1f, 0x0000);
3719
3720         /* Check ALDPS bit, disable it if enabled */
3721         rtl_writephy(tp, 0x1f, 0x0a43);
3722         if (rtl_readphy(tp, 0x10) & 0x0004)
3723                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3724
3725         rtl_writephy(tp, 0x1f, 0x0000);
3726 }
3727
3728 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3729 {
3730         /* patch 10M & ALDPS */
3731         rtl_writephy(tp, 0x1f, 0x0bcc);
3732         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3733         rtl_writephy(tp, 0x1f, 0x0a44);
3734         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3735         rtl_writephy(tp, 0x1f, 0x0a43);
3736         rtl_writephy(tp, 0x13, 0x8084);
3737         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3738         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3739         rtl_writephy(tp, 0x1f, 0x0000);
3740
3741         /* Enable UC LPF tune function */
3742         rtl_writephy(tp, 0x1f, 0x0a43);
3743         rtl_writephy(tp, 0x13, 0x8012);
3744         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3745         rtl_writephy(tp, 0x1f, 0x0000);
3746
3747         /* Set rg_sel_sdm_rate */
3748         rtl_writephy(tp, 0x1f, 0x0c42);
3749         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3750         rtl_writephy(tp, 0x1f, 0x0000);
3751
3752         /* Channel estimation parameters */
3753         rtl_writephy(tp, 0x1f, 0x0a43);
3754         rtl_writephy(tp, 0x13, 0x80f3);
3755         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3756         rtl_writephy(tp, 0x13, 0x80f0);
3757         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3758         rtl_writephy(tp, 0x13, 0x80ef);
3759         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3760         rtl_writephy(tp, 0x13, 0x80f6);
3761         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3762         rtl_writephy(tp, 0x13, 0x80ec);
3763         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3764         rtl_writephy(tp, 0x13, 0x80ed);
3765         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3766         rtl_writephy(tp, 0x13, 0x80f2);
3767         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3768         rtl_writephy(tp, 0x13, 0x80f4);
3769         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3770         rtl_writephy(tp, 0x1f, 0x0a43);
3771         rtl_writephy(tp, 0x13, 0x8110);
3772         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3773         rtl_writephy(tp, 0x13, 0x810f);
3774         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3775         rtl_writephy(tp, 0x13, 0x8111);
3776         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3777         rtl_writephy(tp, 0x13, 0x8113);
3778         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3779         rtl_writephy(tp, 0x13, 0x8115);
3780         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3781         rtl_writephy(tp, 0x13, 0x810e);
3782         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3783         rtl_writephy(tp, 0x13, 0x810c);
3784         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3785         rtl_writephy(tp, 0x13, 0x810b);
3786         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3787         rtl_writephy(tp, 0x1f, 0x0a43);
3788         rtl_writephy(tp, 0x13, 0x80d1);
3789         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3790         rtl_writephy(tp, 0x13, 0x80cd);
3791         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3792         rtl_writephy(tp, 0x13, 0x80d3);
3793         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3794         rtl_writephy(tp, 0x13, 0x80d5);
3795         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3796         rtl_writephy(tp, 0x13, 0x80d7);
3797         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3798
3799         /* Force PWM-mode */
3800         rtl_writephy(tp, 0x1f, 0x0bcd);
3801         rtl_writephy(tp, 0x14, 0x5065);
3802         rtl_writephy(tp, 0x14, 0xd065);
3803         rtl_writephy(tp, 0x1f, 0x0bc8);
3804         rtl_writephy(tp, 0x12, 0x00ed);
3805         rtl_writephy(tp, 0x1f, 0x0bcd);
3806         rtl_writephy(tp, 0x14, 0x1065);
3807         rtl_writephy(tp, 0x14, 0x9065);
3808         rtl_writephy(tp, 0x14, 0x1065);
3809         rtl_writephy(tp, 0x1f, 0x0000);
3810
3811         /* Check ALDPS bit, disable it if enabled */
3812         rtl_writephy(tp, 0x1f, 0x0a43);
3813         if (rtl_readphy(tp, 0x10) & 0x0004)
3814                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3815
3816         rtl_writephy(tp, 0x1f, 0x0000);
3817 }
3818
3819 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3820 {
3821         static const struct phy_reg phy_reg_init[] = {
3822                 { 0x1f, 0x0003 },
3823                 { 0x08, 0x441d },
3824                 { 0x01, 0x9100 },
3825                 { 0x1f, 0x0000 }
3826         };
3827
3828         rtl_writephy(tp, 0x1f, 0x0000);
3829         rtl_patchphy(tp, 0x11, 1 << 12);
3830         rtl_patchphy(tp, 0x19, 1 << 13);
3831         rtl_patchphy(tp, 0x10, 1 << 15);
3832
3833         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3834 }
3835
3836 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3837 {
3838         static const struct phy_reg phy_reg_init[] = {
3839                 { 0x1f, 0x0005 },
3840                 { 0x1a, 0x0000 },
3841                 { 0x1f, 0x0000 },
3842
3843                 { 0x1f, 0x0004 },
3844                 { 0x1c, 0x0000 },
3845                 { 0x1f, 0x0000 },
3846
3847                 { 0x1f, 0x0001 },
3848                 { 0x15, 0x7701 },
3849                 { 0x1f, 0x0000 }
3850         };
3851
3852         /* Disable ALDPS before ram code */
3853         rtl_writephy(tp, 0x1f, 0x0000);
3854         rtl_writephy(tp, 0x18, 0x0310);
3855         msleep(100);
3856
3857         rtl_apply_firmware(tp);
3858
3859         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3860 }
3861
3862 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3863 {
3864         /* Disable ALDPS before setting firmware */
3865         rtl_writephy(tp, 0x1f, 0x0000);
3866         rtl_writephy(tp, 0x18, 0x0310);
3867         msleep(20);
3868
3869         rtl_apply_firmware(tp);
3870
3871         /* EEE setting */
3872         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3873         rtl_writephy(tp, 0x1f, 0x0004);
3874         rtl_writephy(tp, 0x10, 0x401f);
3875         rtl_writephy(tp, 0x19, 0x7030);
3876         rtl_writephy(tp, 0x1f, 0x0000);
3877 }
3878
3879 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3880 {
3881         static const struct phy_reg phy_reg_init[] = {
3882                 { 0x1f, 0x0004 },
3883                 { 0x10, 0xc07f },
3884                 { 0x19, 0x7030 },
3885                 { 0x1f, 0x0000 }
3886         };
3887
3888         /* Disable ALDPS before ram code */
3889         rtl_writephy(tp, 0x1f, 0x0000);
3890         rtl_writephy(tp, 0x18, 0x0310);
3891         msleep(100);
3892
3893         rtl_apply_firmware(tp);
3894
3895         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3896         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3897
3898         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3899 }
3900
3901 static void rtl_hw_phy_config(struct net_device *dev)
3902 {
3903         struct rtl8169_private *tp = netdev_priv(dev);
3904
3905         rtl8169_print_mac_version(tp);
3906
3907         switch (tp->mac_version) {
3908         case RTL_GIGA_MAC_VER_01:
3909                 break;
3910         case RTL_GIGA_MAC_VER_02:
3911         case RTL_GIGA_MAC_VER_03:
3912                 rtl8169s_hw_phy_config(tp);
3913                 break;
3914         case RTL_GIGA_MAC_VER_04:
3915                 rtl8169sb_hw_phy_config(tp);
3916                 break;
3917         case RTL_GIGA_MAC_VER_05:
3918                 rtl8169scd_hw_phy_config(tp);
3919                 break;
3920         case RTL_GIGA_MAC_VER_06:
3921                 rtl8169sce_hw_phy_config(tp);
3922                 break;
3923         case RTL_GIGA_MAC_VER_07:
3924         case RTL_GIGA_MAC_VER_08:
3925         case RTL_GIGA_MAC_VER_09:
3926                 rtl8102e_hw_phy_config(tp);
3927                 break;
3928         case RTL_GIGA_MAC_VER_11:
3929                 rtl8168bb_hw_phy_config(tp);
3930                 break;
3931         case RTL_GIGA_MAC_VER_12:
3932                 rtl8168bef_hw_phy_config(tp);
3933                 break;
3934         case RTL_GIGA_MAC_VER_17:
3935                 rtl8168bef_hw_phy_config(tp);
3936                 break;
3937         case RTL_GIGA_MAC_VER_18:
3938                 rtl8168cp_1_hw_phy_config(tp);
3939                 break;
3940         case RTL_GIGA_MAC_VER_19:
3941                 rtl8168c_1_hw_phy_config(tp);
3942                 break;
3943         case RTL_GIGA_MAC_VER_20:
3944                 rtl8168c_2_hw_phy_config(tp);
3945                 break;
3946         case RTL_GIGA_MAC_VER_21:
3947                 rtl8168c_3_hw_phy_config(tp);
3948                 break;
3949         case RTL_GIGA_MAC_VER_22:
3950                 rtl8168c_4_hw_phy_config(tp);
3951                 break;
3952         case RTL_GIGA_MAC_VER_23:
3953         case RTL_GIGA_MAC_VER_24:
3954                 rtl8168cp_2_hw_phy_config(tp);
3955                 break;
3956         case RTL_GIGA_MAC_VER_25:
3957                 rtl8168d_1_hw_phy_config(tp);
3958                 break;
3959         case RTL_GIGA_MAC_VER_26:
3960                 rtl8168d_2_hw_phy_config(tp);
3961                 break;
3962         case RTL_GIGA_MAC_VER_27:
3963                 rtl8168d_3_hw_phy_config(tp);
3964                 break;
3965         case RTL_GIGA_MAC_VER_28:
3966                 rtl8168d_4_hw_phy_config(tp);
3967                 break;
3968         case RTL_GIGA_MAC_VER_29:
3969         case RTL_GIGA_MAC_VER_30:
3970                 rtl8105e_hw_phy_config(tp);
3971                 break;
3972         case RTL_GIGA_MAC_VER_31:
3973                 /* None. */
3974                 break;
3975         case RTL_GIGA_MAC_VER_32:
3976         case RTL_GIGA_MAC_VER_33:
3977                 rtl8168e_1_hw_phy_config(tp);
3978                 break;
3979         case RTL_GIGA_MAC_VER_34:
3980                 rtl8168e_2_hw_phy_config(tp);
3981                 break;
3982         case RTL_GIGA_MAC_VER_35:
3983                 rtl8168f_1_hw_phy_config(tp);
3984                 break;
3985         case RTL_GIGA_MAC_VER_36:
3986                 rtl8168f_2_hw_phy_config(tp);
3987                 break;
3988
3989         case RTL_GIGA_MAC_VER_37:
3990                 rtl8402_hw_phy_config(tp);
3991                 break;
3992
3993         case RTL_GIGA_MAC_VER_38:
3994                 rtl8411_hw_phy_config(tp);
3995                 break;
3996
3997         case RTL_GIGA_MAC_VER_39:
3998                 rtl8106e_hw_phy_config(tp);
3999                 break;
4000
4001         case RTL_GIGA_MAC_VER_40:
4002                 rtl8168g_1_hw_phy_config(tp);
4003                 break;
4004         case RTL_GIGA_MAC_VER_42:
4005         case RTL_GIGA_MAC_VER_43:
4006         case RTL_GIGA_MAC_VER_44:
4007                 rtl8168g_2_hw_phy_config(tp);
4008                 break;
4009         case RTL_GIGA_MAC_VER_45:
4010         case RTL_GIGA_MAC_VER_47:
4011                 rtl8168h_1_hw_phy_config(tp);
4012                 break;
4013         case RTL_GIGA_MAC_VER_46:
4014         case RTL_GIGA_MAC_VER_48:
4015                 rtl8168h_2_hw_phy_config(tp);
4016                 break;
4017
4018         case RTL_GIGA_MAC_VER_49:
4019                 rtl8168ep_1_hw_phy_config(tp);
4020                 break;
4021         case RTL_GIGA_MAC_VER_50:
4022         case RTL_GIGA_MAC_VER_51:
4023                 rtl8168ep_2_hw_phy_config(tp);
4024                 break;
4025
4026         case RTL_GIGA_MAC_VER_41:
4027         default:
4028                 break;
4029         }
4030 }
4031
4032 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4033 {
4034         if (!test_and_set_bit(flag, tp->wk.flags))
4035                 schedule_work(&tp->wk.work);
4036 }
4037
4038 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4039 {
4040         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4041                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4042 }
4043
4044 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4045 {
4046         rtl_hw_phy_config(dev);
4047
4048         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4049                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4050                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4051                 netif_dbg(tp, drv, dev,
4052                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4053                 RTL_W8(tp, 0x82, 0x01);
4054         }
4055
4056         /* We may have called phy_speed_down before */
4057         phy_speed_up(dev->phydev);
4058
4059         genphy_soft_reset(dev->phydev);
4060
4061         /* It was reported that several chips end up with 10MBit/Half on a
4062          * 1GBit link after resuming from S3. For whatever reason the PHY on
4063          * these chips doesn't properly start a renegotiation when soft-reset.
4064          * Explicitly requesting a renegotiation fixes this.
4065          */
4066         if (dev->phydev->autoneg == AUTONEG_ENABLE)
4067                 phy_restart_aneg(dev->phydev);
4068 }
4069
4070 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4071 {
4072         rtl_lock_work(tp);
4073
4074         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4075
4076         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4077         RTL_R32(tp, MAC4);
4078
4079         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4080         RTL_R32(tp, MAC0);
4081
4082         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4083                 rtl_rar_exgmac_set(tp, addr);
4084
4085         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4086
4087         rtl_unlock_work(tp);
4088 }
4089
4090 static int rtl_set_mac_address(struct net_device *dev, void *p)
4091 {
4092         struct rtl8169_private *tp = netdev_priv(dev);
4093         struct device *d = tp_to_dev(tp);
4094         int ret;
4095
4096         ret = eth_mac_addr(dev, p);
4097         if (ret)
4098                 return ret;
4099
4100         pm_runtime_get_noresume(d);
4101
4102         if (pm_runtime_active(d))
4103                 rtl_rar_set(tp, dev->dev_addr);
4104
4105         pm_runtime_put_noidle(d);
4106
4107         return 0;
4108 }
4109
4110 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4111 {
4112         if (!netif_running(dev))
4113                 return -ENODEV;
4114
4115         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4116 }
4117
4118 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4119 {
4120         struct mdio_ops *ops = &tp->mdio_ops;
4121
4122         switch (tp->mac_version) {
4123         case RTL_GIGA_MAC_VER_27:
4124                 ops->write      = r8168dp_1_mdio_write;
4125                 ops->read       = r8168dp_1_mdio_read;
4126                 break;
4127         case RTL_GIGA_MAC_VER_28:
4128         case RTL_GIGA_MAC_VER_31:
4129                 ops->write      = r8168dp_2_mdio_write;
4130                 ops->read       = r8168dp_2_mdio_read;
4131                 break;
4132         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4133                 ops->write      = r8168g_mdio_write;
4134                 ops->read       = r8168g_mdio_read;
4135                 break;
4136         default:
4137                 ops->write      = r8169_mdio_write;
4138                 ops->read       = r8169_mdio_read;
4139                 break;
4140         }
4141 }
4142
4143 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4144 {
4145         switch (tp->mac_version) {
4146         case RTL_GIGA_MAC_VER_25:
4147         case RTL_GIGA_MAC_VER_26:
4148         case RTL_GIGA_MAC_VER_29:
4149         case RTL_GIGA_MAC_VER_30:
4150         case RTL_GIGA_MAC_VER_32:
4151         case RTL_GIGA_MAC_VER_33:
4152         case RTL_GIGA_MAC_VER_34:
4153         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4154                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4155                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4156                 break;
4157         default:
4158                 break;
4159         }
4160 }
4161
4162 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4163 {
4164         struct phy_device *phydev;
4165
4166         if (!__rtl8169_get_wol(tp))
4167                 return false;
4168
4169         /* phydev may not be attached to netdevice */
4170         phydev = mdiobus_get_phy(tp->mii_bus, 0);
4171
4172         phy_speed_down(phydev, false);
4173         rtl_wol_suspend_quirk(tp);
4174
4175         return true;
4176 }
4177
4178 static void r8168_pll_power_down(struct rtl8169_private *tp)
4179 {
4180         if (r8168_check_dash(tp))
4181                 return;
4182
4183         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4184             tp->mac_version == RTL_GIGA_MAC_VER_33)
4185                 rtl_ephy_write(tp, 0x19, 0xff64);
4186
4187         if (rtl_wol_pll_power_down(tp))
4188                 return;
4189
4190         switch (tp->mac_version) {
4191         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4192         case RTL_GIGA_MAC_VER_37:
4193         case RTL_GIGA_MAC_VER_39:
4194         case RTL_GIGA_MAC_VER_43:
4195         case RTL_GIGA_MAC_VER_44:
4196         case RTL_GIGA_MAC_VER_45:
4197         case RTL_GIGA_MAC_VER_46:
4198         case RTL_GIGA_MAC_VER_47:
4199         case RTL_GIGA_MAC_VER_48:
4200         case RTL_GIGA_MAC_VER_50:
4201         case RTL_GIGA_MAC_VER_51:
4202                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4203                 break;
4204         case RTL_GIGA_MAC_VER_40:
4205         case RTL_GIGA_MAC_VER_41:
4206         case RTL_GIGA_MAC_VER_49:
4207                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4208                              0xfc000000, ERIAR_EXGMAC);
4209                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4210                 break;
4211         }
4212 }
4213
4214 static void r8168_pll_power_up(struct rtl8169_private *tp)
4215 {
4216         switch (tp->mac_version) {
4217         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4218         case RTL_GIGA_MAC_VER_37:
4219         case RTL_GIGA_MAC_VER_39:
4220         case RTL_GIGA_MAC_VER_43:
4221                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4222                 break;
4223         case RTL_GIGA_MAC_VER_44:
4224         case RTL_GIGA_MAC_VER_45:
4225         case RTL_GIGA_MAC_VER_46:
4226         case RTL_GIGA_MAC_VER_47:
4227         case RTL_GIGA_MAC_VER_48:
4228         case RTL_GIGA_MAC_VER_50:
4229         case RTL_GIGA_MAC_VER_51:
4230                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4231                 break;
4232         case RTL_GIGA_MAC_VER_40:
4233         case RTL_GIGA_MAC_VER_41:
4234         case RTL_GIGA_MAC_VER_49:
4235                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4236                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4237                              0x00000000, ERIAR_EXGMAC);
4238                 break;
4239         }
4240
4241         phy_resume(tp->dev->phydev);
4242         /* give MAC/PHY some time to resume */
4243         msleep(20);
4244 }
4245
4246 static void rtl_pll_power_down(struct rtl8169_private *tp)
4247 {
4248         switch (tp->mac_version) {
4249         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4250         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4251                 break;
4252         default:
4253                 r8168_pll_power_down(tp);
4254         }
4255 }
4256
4257 static void rtl_pll_power_up(struct rtl8169_private *tp)
4258 {
4259         switch (tp->mac_version) {
4260         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4261         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4262                 break;
4263         default:
4264                 r8168_pll_power_up(tp);
4265         }
4266 }
4267
4268 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4269 {
4270         switch (tp->mac_version) {
4271         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4272         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4273                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4274                 break;
4275         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4276         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4277         case RTL_GIGA_MAC_VER_38:
4278                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4279                 break;
4280         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4281                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4282                 break;
4283         default:
4284                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4285                 break;
4286         }
4287 }
4288
4289 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4290 {
4291         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4292 }
4293
4294 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4295 {
4296         if (tp->jumbo_ops.enable) {
4297                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4298                 tp->jumbo_ops.enable(tp);
4299                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4300         }
4301 }
4302
4303 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4304 {
4305         if (tp->jumbo_ops.disable) {
4306                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4307                 tp->jumbo_ops.disable(tp);
4308                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4309         }
4310 }
4311
4312 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4313 {
4314         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4315         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4316         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4317 }
4318
4319 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4320 {
4321         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4322         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4323         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4324 }
4325
4326 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4327 {
4328         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4329 }
4330
4331 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4332 {
4333         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4334 }
4335
4336 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4337 {
4338         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4339         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4340         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4341         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4342 }
4343
4344 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4345 {
4346         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4347         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4348         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4349         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4350 }
4351
4352 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4353 {
4354         rtl_tx_performance_tweak(tp,
4355                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4356 }
4357
4358 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4359 {
4360         rtl_tx_performance_tweak(tp,
4361                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4362 }
4363
4364 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4365 {
4366         r8168b_0_hw_jumbo_enable(tp);
4367
4368         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4369 }
4370
4371 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4372 {
4373         r8168b_0_hw_jumbo_disable(tp);
4374
4375         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4376 }
4377
4378 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4379 {
4380         struct jumbo_ops *ops = &tp->jumbo_ops;
4381
4382         switch (tp->mac_version) {
4383         case RTL_GIGA_MAC_VER_11:
4384                 ops->disable    = r8168b_0_hw_jumbo_disable;
4385                 ops->enable     = r8168b_0_hw_jumbo_enable;
4386                 break;
4387         case RTL_GIGA_MAC_VER_12:
4388         case RTL_GIGA_MAC_VER_17:
4389                 ops->disable    = r8168b_1_hw_jumbo_disable;
4390                 ops->enable     = r8168b_1_hw_jumbo_enable;
4391                 break;
4392         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4393         case RTL_GIGA_MAC_VER_19:
4394         case RTL_GIGA_MAC_VER_20:
4395         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4396         case RTL_GIGA_MAC_VER_22:
4397         case RTL_GIGA_MAC_VER_23:
4398         case RTL_GIGA_MAC_VER_24:
4399         case RTL_GIGA_MAC_VER_25:
4400         case RTL_GIGA_MAC_VER_26:
4401                 ops->disable    = r8168c_hw_jumbo_disable;
4402                 ops->enable     = r8168c_hw_jumbo_enable;
4403                 break;
4404         case RTL_GIGA_MAC_VER_27:
4405         case RTL_GIGA_MAC_VER_28:
4406                 ops->disable    = r8168dp_hw_jumbo_disable;
4407                 ops->enable     = r8168dp_hw_jumbo_enable;
4408                 break;
4409         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4410         case RTL_GIGA_MAC_VER_32:
4411         case RTL_GIGA_MAC_VER_33:
4412         case RTL_GIGA_MAC_VER_34:
4413                 ops->disable    = r8168e_hw_jumbo_disable;
4414                 ops->enable     = r8168e_hw_jumbo_enable;
4415                 break;
4416
4417         /*
4418          * No action needed for jumbo frames with 8169.
4419          * No jumbo for 810x at all.
4420          */
4421         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4422         default:
4423                 ops->disable    = NULL;
4424                 ops->enable     = NULL;
4425                 break;
4426         }
4427 }
4428
4429 DECLARE_RTL_COND(rtl_chipcmd_cond)
4430 {
4431         return RTL_R8(tp, ChipCmd) & CmdReset;
4432 }
4433
4434 static void rtl_hw_reset(struct rtl8169_private *tp)
4435 {
4436         RTL_W8(tp, ChipCmd, CmdReset);
4437
4438         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4439 }
4440
4441 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4442 {
4443         struct rtl_fw *rtl_fw;
4444         const char *name;
4445         int rc = -ENOMEM;
4446
4447         name = rtl_lookup_firmware_name(tp);
4448         if (!name)
4449                 goto out_no_firmware;
4450
4451         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4452         if (!rtl_fw)
4453                 goto err_warn;
4454
4455         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4456         if (rc < 0)
4457                 goto err_free;
4458
4459         rc = rtl_check_firmware(tp, rtl_fw);
4460         if (rc < 0)
4461                 goto err_release_firmware;
4462
4463         tp->rtl_fw = rtl_fw;
4464 out:
4465         return;
4466
4467 err_release_firmware:
4468         release_firmware(rtl_fw->fw);
4469 err_free:
4470         kfree(rtl_fw);
4471 err_warn:
4472         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4473                    name, rc);
4474 out_no_firmware:
4475         tp->rtl_fw = NULL;
4476         goto out;
4477 }
4478
4479 static void rtl_request_firmware(struct rtl8169_private *tp)
4480 {
4481         if (IS_ERR(tp->rtl_fw))
4482                 rtl_request_uncached_firmware(tp);
4483 }
4484
4485 static void rtl_rx_close(struct rtl8169_private *tp)
4486 {
4487         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4488 }
4489
4490 DECLARE_RTL_COND(rtl_npq_cond)
4491 {
4492         return RTL_R8(tp, TxPoll) & NPQ;
4493 }
4494
4495 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4496 {
4497         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4498 }
4499
4500 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4501 {
4502         /* Disable interrupts */
4503         rtl8169_irq_mask_and_ack(tp);
4504
4505         rtl_rx_close(tp);
4506
4507         switch (tp->mac_version) {
4508         case RTL_GIGA_MAC_VER_27:
4509         case RTL_GIGA_MAC_VER_28:
4510         case RTL_GIGA_MAC_VER_31:
4511                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4512                 break;
4513         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4514         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4515                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4516                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4517                 break;
4518         default:
4519                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4520                 udelay(100);
4521                 break;
4522         }
4523
4524         rtl_hw_reset(tp);
4525 }
4526
4527 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4528 {
4529         u32 val = TX_DMA_BURST << TxDMAShift |
4530                   InterFrameGap << TxInterFrameGapShift;
4531
4532         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4533             tp->mac_version != RTL_GIGA_MAC_VER_39)
4534                 val |= TXCFG_AUTO_FIFO;
4535
4536         RTL_W32(tp, TxConfig, val);
4537 }
4538
4539 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4540 {
4541         /* Low hurts. Let's disable the filtering. */
4542         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4543 }
4544
4545 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4546 {
4547         /*
4548          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4549          * register to be written before TxDescAddrLow to work.
4550          * Switching from MMIO to I/O access fixes the issue as well.
4551          */
4552         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4553         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4554         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4555         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4556 }
4557
4558 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4559 {
4560         u32 val;
4561
4562         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4563                 val = 0x000fff00;
4564         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4565                 val = 0x00ffff00;
4566         else
4567                 return;
4568
4569         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4570                 val |= 0xff;
4571
4572         RTL_W32(tp, 0x7c, val);
4573 }
4574
4575 static void rtl_set_rx_mode(struct net_device *dev)
4576 {
4577         struct rtl8169_private *tp = netdev_priv(dev);
4578         u32 mc_filter[2];       /* Multicast hash filter */
4579         int rx_mode;
4580         u32 tmp = 0;
4581
4582         if (dev->flags & IFF_PROMISC) {
4583                 /* Unconditionally log net taps. */
4584                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4585                 rx_mode =
4586                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4587                     AcceptAllPhys;
4588                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4589         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4590                    (dev->flags & IFF_ALLMULTI)) {
4591                 /* Too many to filter perfectly -- accept all multicasts. */
4592                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4593                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4594         } else {
4595                 struct netdev_hw_addr *ha;
4596
4597                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4598                 mc_filter[1] = mc_filter[0] = 0;
4599                 netdev_for_each_mc_addr(ha, dev) {
4600                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4601                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4602                         rx_mode |= AcceptMulticast;
4603                 }
4604         }
4605
4606         if (dev->features & NETIF_F_RXALL)
4607                 rx_mode |= (AcceptErr | AcceptRunt);
4608
4609         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4610
4611         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4612                 u32 data = mc_filter[0];
4613
4614                 mc_filter[0] = swab32(mc_filter[1]);
4615                 mc_filter[1] = swab32(data);
4616         }
4617
4618         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4619                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4620
4621         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4622         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4623
4624         RTL_W32(tp, RxConfig, tmp);
4625 }
4626
4627 static void rtl_hw_start(struct  rtl8169_private *tp)
4628 {
4629         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4630
4631         tp->hw_start(tp);
4632
4633         rtl_set_rx_max_size(tp);
4634         rtl_set_rx_tx_desc_registers(tp);
4635         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4636
4637         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4638         RTL_R8(tp, IntrMask);
4639         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4640         rtl_init_rxcfg(tp);
4641         rtl_set_tx_config_registers(tp);
4642
4643         rtl_set_rx_mode(tp->dev);
4644         /* no early-rx interrupts */
4645         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4646         rtl_irq_enable_all(tp);
4647 }
4648
4649 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4650 {
4651         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4652                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4653
4654         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4655
4656         tp->cp_cmd |= PCIMulRW;
4657
4658         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4659             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4660                 netif_dbg(tp, drv, tp->dev,
4661                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4662                 tp->cp_cmd |= (1 << 14);
4663         }
4664
4665         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4666
4667         rtl8169_set_magic_reg(tp, tp->mac_version);
4668
4669         /*
4670          * Undocumented corner. Supposedly:
4671          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4672          */
4673         RTL_W16(tp, IntrMitigate, 0x0000);
4674
4675         RTL_W32(tp, RxMissed, 0);
4676 }
4677
4678 DECLARE_RTL_COND(rtl_csiar_cond)
4679 {
4680         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4681 }
4682
4683 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4684 {
4685         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4686
4687         RTL_W32(tp, CSIDR, value);
4688         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4689                 CSIAR_BYTE_ENABLE | func << 16);
4690
4691         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4692 }
4693
4694 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4695 {
4696         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4697
4698         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4699                 CSIAR_BYTE_ENABLE);
4700
4701         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4702                 RTL_R32(tp, CSIDR) : ~0;
4703 }
4704
4705 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4706 {
4707         struct pci_dev *pdev = tp->pci_dev;
4708         u32 csi;
4709
4710         /* According to Realtek the value at config space address 0x070f
4711          * controls the L0s/L1 entrance latency. We try standard ECAM access
4712          * first and if it fails fall back to CSI.
4713          */
4714         if (pdev->cfg_size > 0x070f &&
4715             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4716                 return;
4717
4718         netdev_notice_once(tp->dev,
4719                 "No native access to PCI extended config space, falling back to CSI\n");
4720         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4721         rtl_csi_write(tp, 0x070c, csi | val << 24);
4722 }
4723
4724 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4725 {
4726         rtl_csi_access_enable(tp, 0x27);
4727 }
4728
4729 struct ephy_info {
4730         unsigned int offset;
4731         u16 mask;
4732         u16 bits;
4733 };
4734
4735 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4736                           int len)
4737 {
4738         u16 w;
4739
4740         while (len-- > 0) {
4741                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4742                 rtl_ephy_write(tp, e->offset, w);
4743                 e++;
4744         }
4745 }
4746
4747 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4748 {
4749         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4750                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4751 }
4752
4753 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4754 {
4755         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4756                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4757 }
4758
4759 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4760 {
4761         u8 data;
4762
4763         data = RTL_R8(tp, Config3);
4764
4765         if (enable)
4766                 data |= Rdy_to_L23;
4767         else
4768                 data &= ~Rdy_to_L23;
4769
4770         RTL_W8(tp, Config3, data);
4771 }
4772
4773 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4774 {
4775         if (enable) {
4776                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4777                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4778         } else {
4779                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4780                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4781         }
4782
4783         udelay(10);
4784 }
4785
4786 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4787 {
4788         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4789
4790         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4791         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4792
4793         if (tp->dev->mtu <= ETH_DATA_LEN) {
4794                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4795                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4796         }
4797 }
4798
4799 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4800 {
4801         rtl_hw_start_8168bb(tp);
4802
4803         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804
4805         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4806 }
4807
4808 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4809 {
4810         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4811
4812         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4813
4814         if (tp->dev->mtu <= ETH_DATA_LEN)
4815                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4816
4817         rtl_disable_clock_request(tp);
4818
4819         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4820         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4821 }
4822
4823 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4824 {
4825         static const struct ephy_info e_info_8168cp[] = {
4826                 { 0x01, 0,      0x0001 },
4827                 { 0x02, 0x0800, 0x1000 },
4828                 { 0x03, 0,      0x0042 },
4829                 { 0x06, 0x0080, 0x0000 },
4830                 { 0x07, 0,      0x2000 }
4831         };
4832
4833         rtl_set_def_aspm_entry_latency(tp);
4834
4835         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4836
4837         __rtl_hw_start_8168cp(tp);
4838 }
4839
4840 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4841 {
4842         rtl_set_def_aspm_entry_latency(tp);
4843
4844         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4845
4846         if (tp->dev->mtu <= ETH_DATA_LEN)
4847                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4848
4849         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4850         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4851 }
4852
4853 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4854 {
4855         rtl_set_def_aspm_entry_latency(tp);
4856
4857         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4858
4859         /* Magic. */
4860         RTL_W8(tp, DBG_REG, 0x20);
4861
4862         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4863
4864         if (tp->dev->mtu <= ETH_DATA_LEN)
4865                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4866
4867         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4868         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4869 }
4870
4871 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4872 {
4873         static const struct ephy_info e_info_8168c_1[] = {
4874                 { 0x02, 0x0800, 0x1000 },
4875                 { 0x03, 0,      0x0002 },
4876                 { 0x06, 0x0080, 0x0000 }
4877         };
4878
4879         rtl_set_def_aspm_entry_latency(tp);
4880
4881         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4882
4883         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4884
4885         __rtl_hw_start_8168cp(tp);
4886 }
4887
4888 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4889 {
4890         static const struct ephy_info e_info_8168c_2[] = {
4891                 { 0x01, 0,      0x0001 },
4892                 { 0x03, 0x0400, 0x0220 }
4893         };
4894
4895         rtl_set_def_aspm_entry_latency(tp);
4896
4897         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4898
4899         __rtl_hw_start_8168cp(tp);
4900 }
4901
4902 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4903 {
4904         rtl_hw_start_8168c_2(tp);
4905 }
4906
4907 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4908 {
4909         rtl_set_def_aspm_entry_latency(tp);
4910
4911         __rtl_hw_start_8168cp(tp);
4912 }
4913
4914 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4915 {
4916         rtl_set_def_aspm_entry_latency(tp);
4917
4918         rtl_disable_clock_request(tp);
4919
4920         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4921
4922         if (tp->dev->mtu <= ETH_DATA_LEN)
4923                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4924
4925         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4926         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4927 }
4928
4929 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4930 {
4931         rtl_set_def_aspm_entry_latency(tp);
4932
4933         if (tp->dev->mtu <= ETH_DATA_LEN)
4934                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4935
4936         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4937
4938         rtl_disable_clock_request(tp);
4939 }
4940
4941 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4942 {
4943         static const struct ephy_info e_info_8168d_4[] = {
4944                 { 0x0b, 0x0000, 0x0048 },
4945                 { 0x19, 0x0020, 0x0050 },
4946                 { 0x0c, 0x0100, 0x0020 }
4947         };
4948
4949         rtl_set_def_aspm_entry_latency(tp);
4950
4951         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4952
4953         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4954
4955         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4956
4957         rtl_enable_clock_request(tp);
4958 }
4959
4960 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4961 {
4962         static const struct ephy_info e_info_8168e_1[] = {
4963                 { 0x00, 0x0200, 0x0100 },
4964                 { 0x00, 0x0000, 0x0004 },
4965                 { 0x06, 0x0002, 0x0001 },
4966                 { 0x06, 0x0000, 0x0030 },
4967                 { 0x07, 0x0000, 0x2000 },
4968                 { 0x00, 0x0000, 0x0020 },
4969                 { 0x03, 0x5800, 0x2000 },
4970                 { 0x03, 0x0000, 0x0001 },
4971                 { 0x01, 0x0800, 0x1000 },
4972                 { 0x07, 0x0000, 0x4000 },
4973                 { 0x1e, 0x0000, 0x2000 },
4974                 { 0x19, 0xffff, 0xfe6c },
4975                 { 0x0a, 0x0000, 0x0040 }
4976         };
4977
4978         rtl_set_def_aspm_entry_latency(tp);
4979
4980         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4981
4982         if (tp->dev->mtu <= ETH_DATA_LEN)
4983                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4984
4985         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4986
4987         rtl_disable_clock_request(tp);
4988
4989         /* Reset tx FIFO pointer */
4990         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4991         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4992
4993         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4994 }
4995
4996 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4997 {
4998         static const struct ephy_info e_info_8168e_2[] = {
4999                 { 0x09, 0x0000, 0x0080 },
5000                 { 0x19, 0x0000, 0x0224 }
5001         };
5002
5003         rtl_set_def_aspm_entry_latency(tp);
5004
5005         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5006
5007         if (tp->dev->mtu <= ETH_DATA_LEN)
5008                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5009
5010         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5011         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5012         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5013         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5014         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5015         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5016         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5017         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5018
5019         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5020
5021         rtl_disable_clock_request(tp);
5022
5023         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5024
5025         /* Adjust EEE LED frequency */
5026         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5027
5028         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5029         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5030         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5031
5032         rtl_hw_aspm_clkreq_enable(tp, true);
5033 }
5034
5035 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5036 {
5037         rtl_set_def_aspm_entry_latency(tp);
5038
5039         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5040
5041         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5042         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5043         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5044         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5045         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5046         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5047         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5048         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5049         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5050         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5051
5052         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5053
5054         rtl_disable_clock_request(tp);
5055
5056         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5057         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5058         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5059         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5060 }
5061
5062 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5063 {
5064         static const struct ephy_info e_info_8168f_1[] = {
5065                 { 0x06, 0x00c0, 0x0020 },
5066                 { 0x08, 0x0001, 0x0002 },
5067                 { 0x09, 0x0000, 0x0080 },
5068                 { 0x19, 0x0000, 0x0224 }
5069         };
5070
5071         rtl_hw_start_8168f(tp);
5072
5073         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5074
5075         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5076
5077         /* Adjust EEE LED frequency */
5078         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5079 }
5080
5081 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5082 {
5083         static const struct ephy_info e_info_8168f_1[] = {
5084                 { 0x06, 0x00c0, 0x0020 },
5085                 { 0x0f, 0xffff, 0x5200 },
5086                 { 0x1e, 0x0000, 0x4000 },
5087                 { 0x19, 0x0000, 0x0224 }
5088         };
5089
5090         rtl_hw_start_8168f(tp);
5091         rtl_pcie_state_l2l3_enable(tp, false);
5092
5093         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5094
5095         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5096 }
5097
5098 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5099 {
5100         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5101         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5102         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5103         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5104
5105         rtl_set_def_aspm_entry_latency(tp);
5106
5107         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5108
5109         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5110         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5111         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5112
5113         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5114         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5115
5116         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5117         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5118
5119         /* Adjust EEE LED frequency */
5120         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5121
5122         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5123         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5124
5125         rtl_pcie_state_l2l3_enable(tp, false);
5126 }
5127
5128 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5129 {
5130         static const struct ephy_info e_info_8168g_1[] = {
5131                 { 0x00, 0x0000, 0x0008 },
5132                 { 0x0c, 0x37d0, 0x0820 },
5133                 { 0x1e, 0x0000, 0x0001 },
5134                 { 0x19, 0x8000, 0x0000 }
5135         };
5136
5137         rtl_hw_start_8168g(tp);
5138
5139         /* disable aspm and clock request before access ephy */
5140         rtl_hw_aspm_clkreq_enable(tp, false);
5141         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5142         rtl_hw_aspm_clkreq_enable(tp, true);
5143 }
5144
5145 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5146 {
5147         static const struct ephy_info e_info_8168g_2[] = {
5148                 { 0x00, 0x0000, 0x0008 },
5149                 { 0x0c, 0x3df0, 0x0200 },
5150                 { 0x19, 0xffff, 0xfc00 },
5151                 { 0x1e, 0xffff, 0x20eb }
5152         };
5153
5154         rtl_hw_start_8168g(tp);
5155
5156         /* disable aspm and clock request before access ephy */
5157         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5158         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5159         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5160 }
5161
5162 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5163 {
5164         static const struct ephy_info e_info_8411_2[] = {
5165                 { 0x00, 0x0000, 0x0008 },
5166                 { 0x0c, 0x3df0, 0x0200 },
5167                 { 0x0f, 0xffff, 0x5200 },
5168                 { 0x19, 0x0020, 0x0000 },
5169                 { 0x1e, 0x0000, 0x2000 }
5170         };
5171
5172         rtl_hw_start_8168g(tp);
5173
5174         /* disable aspm and clock request before access ephy */
5175         rtl_hw_aspm_clkreq_enable(tp, false);
5176         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5177         rtl_hw_aspm_clkreq_enable(tp, true);
5178 }
5179
5180 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5181 {
5182         int rg_saw_cnt;
5183         u32 data;
5184         static const struct ephy_info e_info_8168h_1[] = {
5185                 { 0x1e, 0x0800, 0x0001 },
5186                 { 0x1d, 0x0000, 0x0800 },
5187                 { 0x05, 0xffff, 0x2089 },
5188                 { 0x06, 0xffff, 0x5881 },
5189                 { 0x04, 0xffff, 0x154a },
5190                 { 0x01, 0xffff, 0x068b }
5191         };
5192
5193         /* disable aspm and clock request before access ephy */
5194         rtl_hw_aspm_clkreq_enable(tp, false);
5195         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5196
5197         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5198         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5199         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5200         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5201
5202         rtl_set_def_aspm_entry_latency(tp);
5203
5204         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5205
5206         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5207         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5208
5209         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5210
5211         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5212
5213         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5214
5215         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5216         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5217
5218         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5219         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5220
5221         /* Adjust EEE LED frequency */
5222         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5223
5224         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5225         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5226
5227         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5228
5229         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5230
5231         rtl_pcie_state_l2l3_enable(tp, false);
5232
5233         rtl_writephy(tp, 0x1f, 0x0c42);
5234         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5235         rtl_writephy(tp, 0x1f, 0x0000);
5236         if (rg_saw_cnt > 0) {
5237                 u16 sw_cnt_1ms_ini;
5238
5239                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5240                 sw_cnt_1ms_ini &= 0x0fff;
5241                 data = r8168_mac_ocp_read(tp, 0xd412);
5242                 data &= ~0x0fff;
5243                 data |= sw_cnt_1ms_ini;
5244                 r8168_mac_ocp_write(tp, 0xd412, data);
5245         }
5246
5247         data = r8168_mac_ocp_read(tp, 0xe056);
5248         data &= ~0xf0;
5249         data |= 0x70;
5250         r8168_mac_ocp_write(tp, 0xe056, data);
5251
5252         data = r8168_mac_ocp_read(tp, 0xe052);
5253         data &= ~0x6000;
5254         data |= 0x8008;
5255         r8168_mac_ocp_write(tp, 0xe052, data);
5256
5257         data = r8168_mac_ocp_read(tp, 0xe0d6);
5258         data &= ~0x01ff;
5259         data |= 0x017f;
5260         r8168_mac_ocp_write(tp, 0xe0d6, data);
5261
5262         data = r8168_mac_ocp_read(tp, 0xd420);
5263         data &= ~0x0fff;
5264         data |= 0x047f;
5265         r8168_mac_ocp_write(tp, 0xd420, data);
5266
5267         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5268         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5269         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5270         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5271
5272         rtl_hw_aspm_clkreq_enable(tp, true);
5273 }
5274
5275 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5276 {
5277         rtl8168ep_stop_cmac(tp);
5278
5279         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5280         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5281         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5282         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5283
5284         rtl_set_def_aspm_entry_latency(tp);
5285
5286         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5287
5288         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5289         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5290
5291         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5292
5293         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5294
5295         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5296         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5297
5298         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5299         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5300
5301         /* Adjust EEE LED frequency */
5302         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5303
5304         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5305
5306         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5307
5308         rtl_pcie_state_l2l3_enable(tp, false);
5309 }
5310
5311 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5312 {
5313         static const struct ephy_info e_info_8168ep_1[] = {
5314                 { 0x00, 0xffff, 0x10ab },
5315                 { 0x06, 0xffff, 0xf030 },
5316                 { 0x08, 0xffff, 0x2006 },
5317                 { 0x0d, 0xffff, 0x1666 },
5318                 { 0x0c, 0x3ff0, 0x0000 }
5319         };
5320
5321         /* disable aspm and clock request before access ephy */
5322         rtl_hw_aspm_clkreq_enable(tp, false);
5323         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5324
5325         rtl_hw_start_8168ep(tp);
5326
5327         rtl_hw_aspm_clkreq_enable(tp, true);
5328 }
5329
5330 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5331 {
5332         static const struct ephy_info e_info_8168ep_2[] = {
5333                 { 0x00, 0xffff, 0x10a3 },
5334                 { 0x19, 0xffff, 0xfc00 },
5335                 { 0x1e, 0xffff, 0x20ea }
5336         };
5337
5338         /* disable aspm and clock request before access ephy */
5339         rtl_hw_aspm_clkreq_enable(tp, false);
5340         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5341
5342         rtl_hw_start_8168ep(tp);
5343
5344         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5345         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5346
5347         rtl_hw_aspm_clkreq_enable(tp, true);
5348 }
5349
5350 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5351 {
5352         u32 data;
5353         static const struct ephy_info e_info_8168ep_3[] = {
5354                 { 0x00, 0xffff, 0x10a3 },
5355                 { 0x19, 0xffff, 0x7c00 },
5356                 { 0x1e, 0xffff, 0x20eb },
5357                 { 0x0d, 0xffff, 0x1666 }
5358         };
5359
5360         /* disable aspm and clock request before access ephy */
5361         rtl_hw_aspm_clkreq_enable(tp, false);
5362         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5363
5364         rtl_hw_start_8168ep(tp);
5365
5366         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5367         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5368
5369         data = r8168_mac_ocp_read(tp, 0xd3e2);
5370         data &= 0xf000;
5371         data |= 0x0271;
5372         r8168_mac_ocp_write(tp, 0xd3e2, data);
5373
5374         data = r8168_mac_ocp_read(tp, 0xd3e4);
5375         data &= 0xff00;
5376         r8168_mac_ocp_write(tp, 0xd3e4, data);
5377
5378         data = r8168_mac_ocp_read(tp, 0xe860);
5379         data |= 0x0080;
5380         r8168_mac_ocp_write(tp, 0xe860, data);
5381
5382         rtl_hw_aspm_clkreq_enable(tp, true);
5383 }
5384
5385 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5386 {
5387         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5388
5389         tp->cp_cmd &= ~INTT_MASK;
5390         tp->cp_cmd |= PktCntrDisable | INTT_1;
5391         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5392
5393         RTL_W16(tp, IntrMitigate, 0x5151);
5394
5395         /* Work around for RxFIFO overflow. */
5396         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5397                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5398                 tp->event_slow &= ~RxOverflow;
5399         }
5400
5401         switch (tp->mac_version) {
5402         case RTL_GIGA_MAC_VER_11:
5403                 rtl_hw_start_8168bb(tp);
5404                 break;
5405
5406         case RTL_GIGA_MAC_VER_12:
5407         case RTL_GIGA_MAC_VER_17:
5408                 rtl_hw_start_8168bef(tp);
5409                 break;
5410
5411         case RTL_GIGA_MAC_VER_18:
5412                 rtl_hw_start_8168cp_1(tp);
5413                 break;
5414
5415         case RTL_GIGA_MAC_VER_19:
5416                 rtl_hw_start_8168c_1(tp);
5417                 break;
5418
5419         case RTL_GIGA_MAC_VER_20:
5420                 rtl_hw_start_8168c_2(tp);
5421                 break;
5422
5423         case RTL_GIGA_MAC_VER_21:
5424                 rtl_hw_start_8168c_3(tp);
5425                 break;
5426
5427         case RTL_GIGA_MAC_VER_22:
5428                 rtl_hw_start_8168c_4(tp);
5429                 break;
5430
5431         case RTL_GIGA_MAC_VER_23:
5432                 rtl_hw_start_8168cp_2(tp);
5433                 break;
5434
5435         case RTL_GIGA_MAC_VER_24:
5436                 rtl_hw_start_8168cp_3(tp);
5437                 break;
5438
5439         case RTL_GIGA_MAC_VER_25:
5440         case RTL_GIGA_MAC_VER_26:
5441         case RTL_GIGA_MAC_VER_27:
5442                 rtl_hw_start_8168d(tp);
5443                 break;
5444
5445         case RTL_GIGA_MAC_VER_28:
5446                 rtl_hw_start_8168d_4(tp);
5447                 break;
5448
5449         case RTL_GIGA_MAC_VER_31:
5450                 rtl_hw_start_8168dp(tp);
5451                 break;
5452
5453         case RTL_GIGA_MAC_VER_32:
5454         case RTL_GIGA_MAC_VER_33:
5455                 rtl_hw_start_8168e_1(tp);
5456                 break;
5457         case RTL_GIGA_MAC_VER_34:
5458                 rtl_hw_start_8168e_2(tp);
5459                 break;
5460
5461         case RTL_GIGA_MAC_VER_35:
5462         case RTL_GIGA_MAC_VER_36:
5463                 rtl_hw_start_8168f_1(tp);
5464                 break;
5465
5466         case RTL_GIGA_MAC_VER_38:
5467                 rtl_hw_start_8411(tp);
5468                 break;
5469
5470         case RTL_GIGA_MAC_VER_40:
5471         case RTL_GIGA_MAC_VER_41:
5472                 rtl_hw_start_8168g_1(tp);
5473                 break;
5474         case RTL_GIGA_MAC_VER_42:
5475                 rtl_hw_start_8168g_2(tp);
5476                 break;
5477
5478         case RTL_GIGA_MAC_VER_44:
5479                 rtl_hw_start_8411_2(tp);
5480                 break;
5481
5482         case RTL_GIGA_MAC_VER_45:
5483         case RTL_GIGA_MAC_VER_46:
5484                 rtl_hw_start_8168h_1(tp);
5485                 break;
5486
5487         case RTL_GIGA_MAC_VER_49:
5488                 rtl_hw_start_8168ep_1(tp);
5489                 break;
5490
5491         case RTL_GIGA_MAC_VER_50:
5492                 rtl_hw_start_8168ep_2(tp);
5493                 break;
5494
5495         case RTL_GIGA_MAC_VER_51:
5496                 rtl_hw_start_8168ep_3(tp);
5497                 break;
5498
5499         default:
5500                 netif_err(tp, drv, tp->dev,
5501                           "unknown chipset (mac_version = %d)\n",
5502                           tp->mac_version);
5503                 break;
5504         }
5505 }
5506
5507 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5508 {
5509         static const struct ephy_info e_info_8102e_1[] = {
5510                 { 0x01, 0, 0x6e65 },
5511                 { 0x02, 0, 0x091f },
5512                 { 0x03, 0, 0xc2f9 },
5513                 { 0x06, 0, 0xafb5 },
5514                 { 0x07, 0, 0x0e00 },
5515                 { 0x19, 0, 0xec80 },
5516                 { 0x01, 0, 0x2e65 },
5517                 { 0x01, 0, 0x6e65 }
5518         };
5519         u8 cfg1;
5520
5521         rtl_set_def_aspm_entry_latency(tp);
5522
5523         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5524
5525         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5526
5527         RTL_W8(tp, Config1,
5528                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5529         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5530
5531         cfg1 = RTL_R8(tp, Config1);
5532         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5533                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5534
5535         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5536 }
5537
5538 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5539 {
5540         rtl_set_def_aspm_entry_latency(tp);
5541
5542         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5543
5544         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5545         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5546 }
5547
5548 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5549 {
5550         rtl_hw_start_8102e_2(tp);
5551
5552         rtl_ephy_write(tp, 0x03, 0xc2f9);
5553 }
5554
5555 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5556 {
5557         static const struct ephy_info e_info_8105e_1[] = {
5558                 { 0x07, 0, 0x4000 },
5559                 { 0x19, 0, 0x0200 },
5560                 { 0x19, 0, 0x0020 },
5561                 { 0x1e, 0, 0x2000 },
5562                 { 0x03, 0, 0x0001 },
5563                 { 0x19, 0, 0x0100 },
5564                 { 0x19, 0, 0x0004 },
5565                 { 0x0a, 0, 0x0020 }
5566         };
5567
5568         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5569         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5570
5571         /* Disable Early Tally Counter */
5572         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5573
5574         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5575         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5576
5577         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5578
5579         rtl_pcie_state_l2l3_enable(tp, false);
5580 }
5581
5582 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5583 {
5584         rtl_hw_start_8105e_1(tp);
5585         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5586 }
5587
5588 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5589 {
5590         static const struct ephy_info e_info_8402[] = {
5591                 { 0x19, 0xffff, 0xff64 },
5592                 { 0x1e, 0, 0x4000 }
5593         };
5594
5595         rtl_set_def_aspm_entry_latency(tp);
5596
5597         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5598         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5599
5600         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5601
5602         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5603
5604         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5605
5606         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5607         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5608         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5609         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5610         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5611         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5612         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5613
5614         rtl_pcie_state_l2l3_enable(tp, false);
5615 }
5616
5617 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5618 {
5619         rtl_hw_aspm_clkreq_enable(tp, false);
5620
5621         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5622         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5623
5624         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5625         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5626         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5627
5628         rtl_pcie_state_l2l3_enable(tp, false);
5629         rtl_hw_aspm_clkreq_enable(tp, true);
5630 }
5631
5632 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5633 {
5634         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5635                 tp->event_slow &= ~RxFIFOOver;
5636
5637         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5638             tp->mac_version == RTL_GIGA_MAC_VER_16)
5639                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5640                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5641
5642         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5643
5644         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5645         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5646
5647         switch (tp->mac_version) {
5648         case RTL_GIGA_MAC_VER_07:
5649                 rtl_hw_start_8102e_1(tp);
5650                 break;
5651
5652         case RTL_GIGA_MAC_VER_08:
5653                 rtl_hw_start_8102e_3(tp);
5654                 break;
5655
5656         case RTL_GIGA_MAC_VER_09:
5657                 rtl_hw_start_8102e_2(tp);
5658                 break;
5659
5660         case RTL_GIGA_MAC_VER_29:
5661                 rtl_hw_start_8105e_1(tp);
5662                 break;
5663         case RTL_GIGA_MAC_VER_30:
5664                 rtl_hw_start_8105e_2(tp);
5665                 break;
5666
5667         case RTL_GIGA_MAC_VER_37:
5668                 rtl_hw_start_8402(tp);
5669                 break;
5670
5671         case RTL_GIGA_MAC_VER_39:
5672                 rtl_hw_start_8106(tp);
5673                 break;
5674         case RTL_GIGA_MAC_VER_43:
5675                 rtl_hw_start_8168g_2(tp);
5676                 break;
5677         case RTL_GIGA_MAC_VER_47:
5678         case RTL_GIGA_MAC_VER_48:
5679                 rtl_hw_start_8168h_1(tp);
5680                 break;
5681         }
5682
5683         RTL_W16(tp, IntrMitigate, 0x0000);
5684 }
5685
5686 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5687 {
5688         struct rtl8169_private *tp = netdev_priv(dev);
5689
5690         if (new_mtu > ETH_DATA_LEN)
5691                 rtl_hw_jumbo_enable(tp);
5692         else
5693                 rtl_hw_jumbo_disable(tp);
5694
5695         dev->mtu = new_mtu;
5696         netdev_update_features(dev);
5697
5698         return 0;
5699 }
5700
5701 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5702 {
5703         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5704         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5705 }
5706
5707 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5708                                      void **data_buff, struct RxDesc *desc)
5709 {
5710         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5711                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5712
5713         kfree(*data_buff);
5714         *data_buff = NULL;
5715         rtl8169_make_unusable_by_asic(desc);
5716 }
5717
5718 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5719 {
5720         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5721
5722         /* Force memory writes to complete before releasing descriptor */
5723         dma_wmb();
5724
5725         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5726 }
5727
5728 static inline void *rtl8169_align(void *data)
5729 {
5730         return (void *)ALIGN((long)data, 16);
5731 }
5732
5733 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5734                                              struct RxDesc *desc)
5735 {
5736         void *data;
5737         dma_addr_t mapping;
5738         struct device *d = tp_to_dev(tp);
5739         int node = dev_to_node(d);
5740
5741         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5742         if (!data)
5743                 return NULL;
5744
5745         if (rtl8169_align(data) != data) {
5746                 kfree(data);
5747                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5748                 if (!data)
5749                         return NULL;
5750         }
5751
5752         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5753                                  DMA_FROM_DEVICE);
5754         if (unlikely(dma_mapping_error(d, mapping))) {
5755                 if (net_ratelimit())
5756                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5757                 goto err_out;
5758         }
5759
5760         desc->addr = cpu_to_le64(mapping);
5761         rtl8169_mark_to_asic(desc);
5762         return data;
5763
5764 err_out:
5765         kfree(data);
5766         return NULL;
5767 }
5768
5769 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5770 {
5771         unsigned int i;
5772
5773         for (i = 0; i < NUM_RX_DESC; i++) {
5774                 if (tp->Rx_databuff[i]) {
5775                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5776                                             tp->RxDescArray + i);
5777                 }
5778         }
5779 }
5780
5781 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5782 {
5783         desc->opts1 |= cpu_to_le32(RingEnd);
5784 }
5785
5786 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5787 {
5788         unsigned int i;
5789
5790         for (i = 0; i < NUM_RX_DESC; i++) {
5791                 void *data;
5792
5793                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5794                 if (!data) {
5795                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5796                         goto err_out;
5797                 }
5798                 tp->Rx_databuff[i] = data;
5799         }
5800
5801         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5802         return 0;
5803
5804 err_out:
5805         rtl8169_rx_clear(tp);
5806         return -ENOMEM;
5807 }
5808
5809 static int rtl8169_init_ring(struct rtl8169_private *tp)
5810 {
5811         rtl8169_init_ring_indexes(tp);
5812
5813         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5814         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5815
5816         return rtl8169_rx_fill(tp);
5817 }
5818
5819 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5820                                  struct TxDesc *desc)
5821 {
5822         unsigned int len = tx_skb->len;
5823
5824         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5825
5826         desc->opts1 = 0x00;
5827         desc->opts2 = 0x00;
5828         desc->addr = 0x00;
5829         tx_skb->len = 0;
5830 }
5831
5832 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5833                                    unsigned int n)
5834 {
5835         unsigned int i;
5836
5837         for (i = 0; i < n; i++) {
5838                 unsigned int entry = (start + i) % NUM_TX_DESC;
5839                 struct ring_info *tx_skb = tp->tx_skb + entry;
5840                 unsigned int len = tx_skb->len;
5841
5842                 if (len) {
5843                         struct sk_buff *skb = tx_skb->skb;
5844
5845                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5846                                              tp->TxDescArray + entry);
5847                         if (skb) {
5848                                 dev_consume_skb_any(skb);
5849                                 tx_skb->skb = NULL;
5850                         }
5851                 }
5852         }
5853 }
5854
5855 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5856 {
5857         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5858         tp->cur_tx = tp->dirty_tx = 0;
5859         netdev_reset_queue(tp->dev);
5860 }
5861
5862 static void rtl_reset_work(struct rtl8169_private *tp)
5863 {
5864         struct net_device *dev = tp->dev;
5865         int i;
5866
5867         napi_disable(&tp->napi);
5868         netif_stop_queue(dev);
5869         synchronize_sched();
5870
5871         rtl8169_hw_reset(tp);
5872
5873         for (i = 0; i < NUM_RX_DESC; i++)
5874                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5875
5876         rtl8169_tx_clear(tp);
5877         rtl8169_init_ring_indexes(tp);
5878
5879         napi_enable(&tp->napi);
5880         rtl_hw_start(tp);
5881         netif_wake_queue(dev);
5882 }
5883
5884 static void rtl8169_tx_timeout(struct net_device *dev)
5885 {
5886         struct rtl8169_private *tp = netdev_priv(dev);
5887
5888         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5889 }
5890
5891 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5892                               u32 *opts)
5893 {
5894         struct skb_shared_info *info = skb_shinfo(skb);
5895         unsigned int cur_frag, entry;
5896         struct TxDesc *uninitialized_var(txd);
5897         struct device *d = tp_to_dev(tp);
5898
5899         entry = tp->cur_tx;
5900         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5901                 const skb_frag_t *frag = info->frags + cur_frag;
5902                 dma_addr_t mapping;
5903                 u32 status, len;
5904                 void *addr;
5905
5906                 entry = (entry + 1) % NUM_TX_DESC;
5907
5908                 txd = tp->TxDescArray + entry;
5909                 len = skb_frag_size(frag);
5910                 addr = skb_frag_address(frag);
5911                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5912                 if (unlikely(dma_mapping_error(d, mapping))) {
5913                         if (net_ratelimit())
5914                                 netif_err(tp, drv, tp->dev,
5915                                           "Failed to map TX fragments DMA!\n");
5916                         goto err_out;
5917                 }
5918
5919                 /* Anti gcc 2.95.3 bugware (sic) */
5920                 status = opts[0] | len |
5921                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5922
5923                 txd->opts1 = cpu_to_le32(status);
5924                 txd->opts2 = cpu_to_le32(opts[1]);
5925                 txd->addr = cpu_to_le64(mapping);
5926
5927                 tp->tx_skb[entry].len = len;
5928         }
5929
5930         if (cur_frag) {
5931                 tp->tx_skb[entry].skb = skb;
5932                 txd->opts1 |= cpu_to_le32(LastFrag);
5933         }
5934
5935         return cur_frag;
5936
5937 err_out:
5938         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5939         return -EIO;
5940 }
5941
5942 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5943 {
5944         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5945 }
5946
5947 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5948                                       struct net_device *dev);
5949 /* r8169_csum_workaround()
5950  * The hw limites the value the transport offset. When the offset is out of the
5951  * range, calculate the checksum by sw.
5952  */
5953 static void r8169_csum_workaround(struct rtl8169_private *tp,
5954                                   struct sk_buff *skb)
5955 {
5956         if (skb_shinfo(skb)->gso_size) {
5957                 netdev_features_t features = tp->dev->features;
5958                 struct sk_buff *segs, *nskb;
5959
5960                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5961                 segs = skb_gso_segment(skb, features);
5962                 if (IS_ERR(segs) || !segs)
5963                         goto drop;
5964
5965                 do {
5966                         nskb = segs;
5967                         segs = segs->next;
5968                         nskb->next = NULL;
5969                         rtl8169_start_xmit(nskb, tp->dev);
5970                 } while (segs);
5971
5972                 dev_consume_skb_any(skb);
5973         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5974                 if (skb_checksum_help(skb) < 0)
5975                         goto drop;
5976
5977                 rtl8169_start_xmit(skb, tp->dev);
5978         } else {
5979                 struct net_device_stats *stats;
5980
5981 drop:
5982                 stats = &tp->dev->stats;
5983                 stats->tx_dropped++;
5984                 dev_kfree_skb_any(skb);
5985         }
5986 }
5987
5988 /* msdn_giant_send_check()
5989  * According to the document of microsoft, the TCP Pseudo Header excludes the
5990  * packet length for IPv6 TCP large packets.
5991  */
5992 static int msdn_giant_send_check(struct sk_buff *skb)
5993 {
5994         const struct ipv6hdr *ipv6h;
5995         struct tcphdr *th;
5996         int ret;
5997
5998         ret = skb_cow_head(skb, 0);
5999         if (ret)
6000                 return ret;
6001
6002         ipv6h = ipv6_hdr(skb);
6003         th = tcp_hdr(skb);
6004
6005         th->check = 0;
6006         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6007
6008         return ret;
6009 }
6010
6011 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6012                                 struct sk_buff *skb, u32 *opts)
6013 {
6014         u32 mss = skb_shinfo(skb)->gso_size;
6015
6016         if (mss) {
6017                 opts[0] |= TD_LSO;
6018                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6019         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6020                 const struct iphdr *ip = ip_hdr(skb);
6021
6022                 if (ip->protocol == IPPROTO_TCP)
6023                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6024                 else if (ip->protocol == IPPROTO_UDP)
6025                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6026                 else
6027                         WARN_ON_ONCE(1);
6028         }
6029
6030         return true;
6031 }
6032
6033 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6034                                 struct sk_buff *skb, u32 *opts)
6035 {
6036         u32 transport_offset = (u32)skb_transport_offset(skb);
6037         u32 mss = skb_shinfo(skb)->gso_size;
6038
6039         if (mss) {
6040                 if (transport_offset > GTTCPHO_MAX) {
6041                         netif_warn(tp, tx_err, tp->dev,
6042                                    "Invalid transport offset 0x%x for TSO\n",
6043                                    transport_offset);
6044                         return false;
6045                 }
6046
6047                 switch (vlan_get_protocol(skb)) {
6048                 case htons(ETH_P_IP):
6049                         opts[0] |= TD1_GTSENV4;
6050                         break;
6051
6052                 case htons(ETH_P_IPV6):
6053                         if (msdn_giant_send_check(skb))
6054                                 return false;
6055
6056                         opts[0] |= TD1_GTSENV6;
6057                         break;
6058
6059                 default:
6060                         WARN_ON_ONCE(1);
6061                         break;
6062                 }
6063
6064                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6065                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6066         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6067                 u8 ip_protocol;
6068
6069                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6070                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6071
6072                 if (transport_offset > TCPHO_MAX) {
6073                         netif_warn(tp, tx_err, tp->dev,
6074                                    "Invalid transport offset 0x%x\n",
6075                                    transport_offset);
6076                         return false;
6077                 }
6078
6079                 switch (vlan_get_protocol(skb)) {
6080                 case htons(ETH_P_IP):
6081                         opts[1] |= TD1_IPv4_CS;
6082                         ip_protocol = ip_hdr(skb)->protocol;
6083                         break;
6084
6085                 case htons(ETH_P_IPV6):
6086                         opts[1] |= TD1_IPv6_CS;
6087                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6088                         break;
6089
6090                 default:
6091                         ip_protocol = IPPROTO_RAW;
6092                         break;
6093                 }
6094
6095                 if (ip_protocol == IPPROTO_TCP)
6096                         opts[1] |= TD1_TCP_CS;
6097                 else if (ip_protocol == IPPROTO_UDP)
6098                         opts[1] |= TD1_UDP_CS;
6099                 else
6100                         WARN_ON_ONCE(1);
6101
6102                 opts[1] |= transport_offset << TCPHO_SHIFT;
6103         } else {
6104                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6105                         return !eth_skb_pad(skb);
6106         }
6107
6108         return true;
6109 }
6110
6111 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6112                                       struct net_device *dev)
6113 {
6114         struct rtl8169_private *tp = netdev_priv(dev);
6115         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6116         struct TxDesc *txd = tp->TxDescArray + entry;
6117         struct device *d = tp_to_dev(tp);
6118         dma_addr_t mapping;
6119         u32 status, len;
6120         u32 opts[2];
6121         int frags;
6122
6123         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6124                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6125                 goto err_stop_0;
6126         }
6127
6128         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6129                 goto err_stop_0;
6130
6131         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6132         opts[0] = DescOwn;
6133
6134         if (!tp->tso_csum(tp, skb, opts)) {
6135                 r8169_csum_workaround(tp, skb);
6136                 return NETDEV_TX_OK;
6137         }
6138
6139         len = skb_headlen(skb);
6140         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6141         if (unlikely(dma_mapping_error(d, mapping))) {
6142                 if (net_ratelimit())
6143                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6144                 goto err_dma_0;
6145         }
6146
6147         tp->tx_skb[entry].len = len;
6148         txd->addr = cpu_to_le64(mapping);
6149
6150         frags = rtl8169_xmit_frags(tp, skb, opts);
6151         if (frags < 0)
6152                 goto err_dma_1;
6153         else if (frags)
6154                 opts[0] |= FirstFrag;
6155         else {
6156                 opts[0] |= FirstFrag | LastFrag;
6157                 tp->tx_skb[entry].skb = skb;
6158         }
6159
6160         txd->opts2 = cpu_to_le32(opts[1]);
6161
6162         netdev_sent_queue(dev, skb->len);
6163
6164         skb_tx_timestamp(skb);
6165
6166         /* Force memory writes to complete before releasing descriptor */
6167         dma_wmb();
6168
6169         /* Anti gcc 2.95.3 bugware (sic) */
6170         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6171         txd->opts1 = cpu_to_le32(status);
6172
6173         /* Force all memory writes to complete before notifying device */
6174         wmb();
6175
6176         tp->cur_tx += frags + 1;
6177
6178         RTL_W8(tp, TxPoll, NPQ);
6179
6180         mmiowb();
6181
6182         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6183                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6184                  * not miss a ring update when it notices a stopped queue.
6185                  */
6186                 smp_wmb();
6187                 netif_stop_queue(dev);
6188                 /* Sync with rtl_tx:
6189                  * - publish queue status and cur_tx ring index (write barrier)
6190                  * - refresh dirty_tx ring index (read barrier).
6191                  * May the current thread have a pessimistic view of the ring
6192                  * status and forget to wake up queue, a racing rtl_tx thread
6193                  * can't.
6194                  */
6195                 smp_mb();
6196                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6197                         netif_wake_queue(dev);
6198         }
6199
6200         return NETDEV_TX_OK;
6201
6202 err_dma_1:
6203         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6204 err_dma_0:
6205         dev_kfree_skb_any(skb);
6206         dev->stats.tx_dropped++;
6207         return NETDEV_TX_OK;
6208
6209 err_stop_0:
6210         netif_stop_queue(dev);
6211         dev->stats.tx_dropped++;
6212         return NETDEV_TX_BUSY;
6213 }
6214
6215 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6216 {
6217         struct rtl8169_private *tp = netdev_priv(dev);
6218         struct pci_dev *pdev = tp->pci_dev;
6219         u16 pci_status, pci_cmd;
6220
6221         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6222         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6223
6224         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6225                   pci_cmd, pci_status);
6226
6227         /*
6228          * The recovery sequence below admits a very elaborated explanation:
6229          * - it seems to work;
6230          * - I did not see what else could be done;
6231          * - it makes iop3xx happy.
6232          *
6233          * Feel free to adjust to your needs.
6234          */
6235         if (pdev->broken_parity_status)
6236                 pci_cmd &= ~PCI_COMMAND_PARITY;
6237         else
6238                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6239
6240         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6241
6242         pci_write_config_word(pdev, PCI_STATUS,
6243                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6244                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6245                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6246
6247         /* The infamous DAC f*ckup only happens at boot time */
6248         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6249                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6250                 tp->cp_cmd &= ~PCIDAC;
6251                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6252                 dev->features &= ~NETIF_F_HIGHDMA;
6253         }
6254
6255         rtl8169_hw_reset(tp);
6256
6257         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6258 }
6259
6260 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6261 {
6262         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6263
6264         dirty_tx = tp->dirty_tx;
6265         smp_rmb();
6266         tx_left = tp->cur_tx - dirty_tx;
6267
6268         while (tx_left > 0) {
6269                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6270                 struct ring_info *tx_skb = tp->tx_skb + entry;
6271                 u32 status;
6272
6273                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6274                 if (status & DescOwn)
6275                         break;
6276
6277                 /* This barrier is needed to keep us from reading
6278                  * any other fields out of the Tx descriptor until
6279                  * we know the status of DescOwn
6280                  */
6281                 dma_rmb();
6282
6283                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6284                                      tp->TxDescArray + entry);
6285                 if (status & LastFrag) {
6286                         pkts_compl++;
6287                         bytes_compl += tx_skb->skb->len;
6288                         dev_consume_skb_any(tx_skb->skb);
6289                         tx_skb->skb = NULL;
6290                 }
6291                 dirty_tx++;
6292                 tx_left--;
6293         }
6294
6295         if (tp->dirty_tx != dirty_tx) {
6296                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6297
6298                 u64_stats_update_begin(&tp->tx_stats.syncp);
6299                 tp->tx_stats.packets += pkts_compl;
6300                 tp->tx_stats.bytes += bytes_compl;
6301                 u64_stats_update_end(&tp->tx_stats.syncp);
6302
6303                 tp->dirty_tx = dirty_tx;
6304                 /* Sync with rtl8169_start_xmit:
6305                  * - publish dirty_tx ring index (write barrier)
6306                  * - refresh cur_tx ring index and queue status (read barrier)
6307                  * May the current thread miss the stopped queue condition,
6308                  * a racing xmit thread can only have a right view of the
6309                  * ring status.
6310                  */
6311                 smp_mb();
6312                 if (netif_queue_stopped(dev) &&
6313                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6314                         netif_wake_queue(dev);
6315                 }
6316                 /*
6317                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6318                  * too close. Let's kick an extra TxPoll request when a burst
6319                  * of start_xmit activity is detected (if it is not detected,
6320                  * it is slow enough). -- FR
6321                  */
6322                 if (tp->cur_tx != dirty_tx)
6323                         RTL_W8(tp, TxPoll, NPQ);
6324         }
6325 }
6326
6327 static inline int rtl8169_fragmented_frame(u32 status)
6328 {
6329         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6330 }
6331
6332 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6333 {
6334         u32 status = opts1 & RxProtoMask;
6335
6336         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6337             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6338                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6339         else
6340                 skb_checksum_none_assert(skb);
6341 }
6342
6343 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6344                                            struct rtl8169_private *tp,
6345                                            int pkt_size,
6346                                            dma_addr_t addr)
6347 {
6348         struct sk_buff *skb;
6349         struct device *d = tp_to_dev(tp);
6350
6351         data = rtl8169_align(data);
6352         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6353         prefetch(data);
6354         skb = napi_alloc_skb(&tp->napi, pkt_size);
6355         if (skb)
6356                 skb_copy_to_linear_data(skb, data, pkt_size);
6357         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6358
6359         return skb;
6360 }
6361
6362 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6363 {
6364         unsigned int cur_rx, rx_left;
6365         unsigned int count;
6366
6367         cur_rx = tp->cur_rx;
6368
6369         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6370                 unsigned int entry = cur_rx % NUM_RX_DESC;
6371                 struct RxDesc *desc = tp->RxDescArray + entry;
6372                 u32 status;
6373
6374                 status = le32_to_cpu(desc->opts1);
6375                 if (status & DescOwn)
6376                         break;
6377
6378                 /* This barrier is needed to keep us from reading
6379                  * any other fields out of the Rx descriptor until
6380                  * we know the status of DescOwn
6381                  */
6382                 dma_rmb();
6383
6384                 if (unlikely(status & RxRES)) {
6385                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6386                                    status);
6387                         dev->stats.rx_errors++;
6388                         if (status & (RxRWT | RxRUNT))
6389                                 dev->stats.rx_length_errors++;
6390                         if (status & RxCRC)
6391                                 dev->stats.rx_crc_errors++;
6392                         /* RxFOVF is a reserved bit on later chip versions */
6393                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6394                             status & RxFOVF) {
6395                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6396                                 dev->stats.rx_fifo_errors++;
6397                         } else if (status & (RxRUNT | RxCRC) &&
6398                                    !(status & RxRWT) &&
6399                                    dev->features & NETIF_F_RXALL) {
6400                                 goto process_pkt;
6401                         }
6402                 } else {
6403                         struct sk_buff *skb;
6404                         dma_addr_t addr;
6405                         int pkt_size;
6406
6407 process_pkt:
6408                         addr = le64_to_cpu(desc->addr);
6409                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6410                                 pkt_size = (status & 0x00003fff) - 4;
6411                         else
6412                                 pkt_size = status & 0x00003fff;
6413
6414                         /*
6415                          * The driver does not support incoming fragmented
6416                          * frames. They are seen as a symptom of over-mtu
6417                          * sized frames.
6418                          */
6419                         if (unlikely(rtl8169_fragmented_frame(status))) {
6420                                 dev->stats.rx_dropped++;
6421                                 dev->stats.rx_length_errors++;
6422                                 goto release_descriptor;
6423                         }
6424
6425                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6426                                                   tp, pkt_size, addr);
6427                         if (!skb) {
6428                                 dev->stats.rx_dropped++;
6429                                 goto release_descriptor;
6430                         }
6431
6432                         rtl8169_rx_csum(skb, status);
6433                         skb_put(skb, pkt_size);
6434                         skb->protocol = eth_type_trans(skb, dev);
6435
6436                         rtl8169_rx_vlan_tag(desc, skb);
6437
6438                         if (skb->pkt_type == PACKET_MULTICAST)
6439                                 dev->stats.multicast++;
6440
6441                         napi_gro_receive(&tp->napi, skb);
6442
6443                         u64_stats_update_begin(&tp->rx_stats.syncp);
6444                         tp->rx_stats.packets++;
6445                         tp->rx_stats.bytes += pkt_size;
6446                         u64_stats_update_end(&tp->rx_stats.syncp);
6447                 }
6448 release_descriptor:
6449                 desc->opts2 = 0;
6450                 rtl8169_mark_to_asic(desc);
6451         }
6452
6453         count = cur_rx - tp->cur_rx;
6454         tp->cur_rx = cur_rx;
6455
6456         return count;
6457 }
6458
6459 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6460 {
6461         struct rtl8169_private *tp = dev_instance;
6462         u16 status = rtl_get_events(tp);
6463
6464         if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6465                 return IRQ_NONE;
6466
6467         if (unlikely(status & SYSErr)) {
6468                 rtl8169_pcierr_interrupt(tp->dev);
6469                 goto out;
6470         }
6471
6472         if (status & LinkChg)
6473                 phy_mac_interrupt(tp->dev->phydev);
6474
6475         if (unlikely(status & RxFIFOOver &&
6476             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6477                 netif_stop_queue(tp->dev);
6478                 /* XXX - Hack alert. See rtl_task(). */
6479                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6480         }
6481
6482         if (status & RTL_EVENT_NAPI) {
6483                 rtl_irq_disable(tp);
6484                 napi_schedule_irqoff(&tp->napi);
6485         }
6486 out:
6487         rtl_ack_events(tp, status);
6488
6489         return IRQ_HANDLED;
6490 }
6491
6492 static void rtl_task(struct work_struct *work)
6493 {
6494         static const struct {
6495                 int bitnr;
6496                 void (*action)(struct rtl8169_private *);
6497         } rtl_work[] = {
6498                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6499         };
6500         struct rtl8169_private *tp =
6501                 container_of(work, struct rtl8169_private, wk.work);
6502         struct net_device *dev = tp->dev;
6503         int i;
6504
6505         rtl_lock_work(tp);
6506
6507         if (!netif_running(dev) ||
6508             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6509                 goto out_unlock;
6510
6511         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6512                 bool pending;
6513
6514                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6515                 if (pending)
6516                         rtl_work[i].action(tp);
6517         }
6518
6519 out_unlock:
6520         rtl_unlock_work(tp);
6521 }
6522
6523 static int rtl8169_poll(struct napi_struct *napi, int budget)
6524 {
6525         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6526         struct net_device *dev = tp->dev;
6527         int work_done;
6528
6529         work_done = rtl_rx(dev, tp, (u32) budget);
6530
6531         rtl_tx(dev, tp);
6532
6533         if (work_done < budget) {
6534                 napi_complete_done(napi, work_done);
6535
6536                 rtl_irq_enable_all(tp);
6537                 mmiowb();
6538         }
6539
6540         return work_done;
6541 }
6542
6543 static void rtl8169_rx_missed(struct net_device *dev)
6544 {
6545         struct rtl8169_private *tp = netdev_priv(dev);
6546
6547         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6548                 return;
6549
6550         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6551         RTL_W32(tp, RxMissed, 0);
6552 }
6553
6554 static void r8169_phylink_handler(struct net_device *ndev)
6555 {
6556         struct rtl8169_private *tp = netdev_priv(ndev);
6557
6558         if (netif_carrier_ok(ndev)) {
6559                 rtl_link_chg_patch(tp);
6560                 pm_request_resume(&tp->pci_dev->dev);
6561         } else {
6562                 pm_runtime_idle(&tp->pci_dev->dev);
6563         }
6564
6565         if (net_ratelimit())
6566                 phy_print_status(ndev->phydev);
6567 }
6568
6569 static int r8169_phy_connect(struct rtl8169_private *tp)
6570 {
6571         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6572         phy_interface_t phy_mode;
6573         int ret;
6574
6575         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6576                    PHY_INTERFACE_MODE_MII;
6577
6578         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6579                                  phy_mode);
6580         if (ret)
6581                 return ret;
6582
6583         if (!tp->supports_gmii)
6584                 phy_set_max_speed(phydev, SPEED_100);
6585
6586         /* Ensure to advertise everything, incl. pause */
6587         phydev->advertising = phydev->supported;
6588
6589         phy_attached_info(phydev);
6590
6591         return 0;
6592 }
6593
6594 static void rtl8169_down(struct net_device *dev)
6595 {
6596         struct rtl8169_private *tp = netdev_priv(dev);
6597
6598         phy_stop(dev->phydev);
6599
6600         napi_disable(&tp->napi);
6601         netif_stop_queue(dev);
6602
6603         rtl8169_hw_reset(tp);
6604         /*
6605          * At this point device interrupts can not be enabled in any function,
6606          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6607          * and napi is disabled (rtl8169_poll).
6608          */
6609         rtl8169_rx_missed(dev);
6610
6611         /* Give a racing hard_start_xmit a few cycles to complete. */
6612         synchronize_sched();
6613
6614         rtl8169_tx_clear(tp);
6615
6616         rtl8169_rx_clear(tp);
6617
6618         rtl_pll_power_down(tp);
6619 }
6620
6621 static int rtl8169_close(struct net_device *dev)
6622 {
6623         struct rtl8169_private *tp = netdev_priv(dev);
6624         struct pci_dev *pdev = tp->pci_dev;
6625
6626         pm_runtime_get_sync(&pdev->dev);
6627
6628         /* Update counters before going down */
6629         rtl8169_update_counters(tp);
6630
6631         rtl_lock_work(tp);
6632         /* Clear all task flags */
6633         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6634
6635         rtl8169_down(dev);
6636         rtl_unlock_work(tp);
6637
6638         cancel_work_sync(&tp->wk.work);
6639
6640         phy_disconnect(dev->phydev);
6641
6642         pci_free_irq(pdev, 0, tp);
6643
6644         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6645                           tp->RxPhyAddr);
6646         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6647                           tp->TxPhyAddr);
6648         tp->TxDescArray = NULL;
6649         tp->RxDescArray = NULL;
6650
6651         pm_runtime_put_sync(&pdev->dev);
6652
6653         return 0;
6654 }
6655
6656 #ifdef CONFIG_NET_POLL_CONTROLLER
6657 static void rtl8169_netpoll(struct net_device *dev)
6658 {
6659         struct rtl8169_private *tp = netdev_priv(dev);
6660
6661         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6662 }
6663 #endif
6664
6665 static int rtl_open(struct net_device *dev)
6666 {
6667         struct rtl8169_private *tp = netdev_priv(dev);
6668         struct pci_dev *pdev = tp->pci_dev;
6669         int retval = -ENOMEM;
6670
6671         pm_runtime_get_sync(&pdev->dev);
6672
6673         /*
6674          * Rx and Tx descriptors needs 256 bytes alignment.
6675          * dma_alloc_coherent provides more.
6676          */
6677         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6678                                              &tp->TxPhyAddr, GFP_KERNEL);
6679         if (!tp->TxDescArray)
6680                 goto err_pm_runtime_put;
6681
6682         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6683                                              &tp->RxPhyAddr, GFP_KERNEL);
6684         if (!tp->RxDescArray)
6685                 goto err_free_tx_0;
6686
6687         retval = rtl8169_init_ring(tp);
6688         if (retval < 0)
6689                 goto err_free_rx_1;
6690
6691         INIT_WORK(&tp->wk.work, rtl_task);
6692
6693         smp_mb();
6694
6695         rtl_request_firmware(tp);
6696
6697         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6698                                  dev->name);
6699         if (retval < 0)
6700                 goto err_release_fw_2;
6701
6702         retval = r8169_phy_connect(tp);
6703         if (retval)
6704                 goto err_free_irq;
6705
6706         rtl_lock_work(tp);
6707
6708         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6709
6710         napi_enable(&tp->napi);
6711
6712         rtl8169_init_phy(dev, tp);
6713
6714         rtl_pll_power_up(tp);
6715
6716         rtl_hw_start(tp);
6717
6718         if (!rtl8169_init_counter_offsets(tp))
6719                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6720
6721         phy_start(dev->phydev);
6722         netif_start_queue(dev);
6723
6724         rtl_unlock_work(tp);
6725
6726         pm_runtime_put_sync(&pdev->dev);
6727 out:
6728         return retval;
6729
6730 err_free_irq:
6731         pci_free_irq(pdev, 0, tp);
6732 err_release_fw_2:
6733         rtl_release_firmware(tp);
6734         rtl8169_rx_clear(tp);
6735 err_free_rx_1:
6736         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6737                           tp->RxPhyAddr);
6738         tp->RxDescArray = NULL;
6739 err_free_tx_0:
6740         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6741                           tp->TxPhyAddr);
6742         tp->TxDescArray = NULL;
6743 err_pm_runtime_put:
6744         pm_runtime_put_noidle(&pdev->dev);
6745         goto out;
6746 }
6747
6748 static void
6749 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6750 {
6751         struct rtl8169_private *tp = netdev_priv(dev);
6752         struct pci_dev *pdev = tp->pci_dev;
6753         struct rtl8169_counters *counters = tp->counters;
6754         unsigned int start;
6755
6756         pm_runtime_get_noresume(&pdev->dev);
6757
6758         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6759                 rtl8169_rx_missed(dev);
6760
6761         do {
6762                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6763                 stats->rx_packets = tp->rx_stats.packets;
6764                 stats->rx_bytes = tp->rx_stats.bytes;
6765         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6766
6767         do {
6768                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6769                 stats->tx_packets = tp->tx_stats.packets;
6770                 stats->tx_bytes = tp->tx_stats.bytes;
6771         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6772
6773         stats->rx_dropped       = dev->stats.rx_dropped;
6774         stats->tx_dropped       = dev->stats.tx_dropped;
6775         stats->rx_length_errors = dev->stats.rx_length_errors;
6776         stats->rx_errors        = dev->stats.rx_errors;
6777         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6778         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6779         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6780         stats->multicast        = dev->stats.multicast;
6781
6782         /*
6783          * Fetch additonal counter values missing in stats collected by driver
6784          * from tally counters.
6785          */
6786         if (pm_runtime_active(&pdev->dev))
6787                 rtl8169_update_counters(tp);
6788
6789         /*
6790          * Subtract values fetched during initalization.
6791          * See rtl8169_init_counter_offsets for a description why we do that.
6792          */
6793         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6794                 le64_to_cpu(tp->tc_offset.tx_errors);
6795         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6796                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6797         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6798                 le16_to_cpu(tp->tc_offset.tx_aborted);
6799
6800         pm_runtime_put_noidle(&pdev->dev);
6801 }
6802
6803 static void rtl8169_net_suspend(struct net_device *dev)
6804 {
6805         struct rtl8169_private *tp = netdev_priv(dev);
6806
6807         if (!netif_running(dev))
6808                 return;
6809
6810         phy_stop(dev->phydev);
6811         netif_device_detach(dev);
6812
6813         rtl_lock_work(tp);
6814         napi_disable(&tp->napi);
6815         /* Clear all task flags */
6816         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6817
6818         rtl_unlock_work(tp);
6819
6820         rtl_pll_power_down(tp);
6821 }
6822
6823 #ifdef CONFIG_PM
6824
6825 static int rtl8169_suspend(struct device *device)
6826 {
6827         struct pci_dev *pdev = to_pci_dev(device);
6828         struct net_device *dev = pci_get_drvdata(pdev);
6829         struct rtl8169_private *tp = netdev_priv(dev);
6830
6831         rtl8169_net_suspend(dev);
6832         clk_disable_unprepare(tp->clk);
6833
6834         return 0;
6835 }
6836
6837 static void __rtl8169_resume(struct net_device *dev)
6838 {
6839         struct rtl8169_private *tp = netdev_priv(dev);
6840
6841         netif_device_attach(dev);
6842
6843         rtl_pll_power_up(tp);
6844         rtl8169_init_phy(dev, tp);
6845
6846         phy_start(tp->dev->phydev);
6847
6848         rtl_lock_work(tp);
6849         napi_enable(&tp->napi);
6850         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6851         rtl_unlock_work(tp);
6852
6853         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6854 }
6855
6856 static int rtl8169_resume(struct device *device)
6857 {
6858         struct pci_dev *pdev = to_pci_dev(device);
6859         struct net_device *dev = pci_get_drvdata(pdev);
6860         struct rtl8169_private *tp = netdev_priv(dev);
6861
6862         clk_prepare_enable(tp->clk);
6863
6864         if (netif_running(dev))
6865                 __rtl8169_resume(dev);
6866
6867         return 0;
6868 }
6869
6870 static int rtl8169_runtime_suspend(struct device *device)
6871 {
6872         struct pci_dev *pdev = to_pci_dev(device);
6873         struct net_device *dev = pci_get_drvdata(pdev);
6874         struct rtl8169_private *tp = netdev_priv(dev);
6875
6876         if (!tp->TxDescArray)
6877                 return 0;
6878
6879         rtl_lock_work(tp);
6880         __rtl8169_set_wol(tp, WAKE_ANY);
6881         rtl_unlock_work(tp);
6882
6883         rtl8169_net_suspend(dev);
6884
6885         /* Update counters before going runtime suspend */
6886         rtl8169_rx_missed(dev);
6887         rtl8169_update_counters(tp);
6888
6889         return 0;
6890 }
6891
6892 static int rtl8169_runtime_resume(struct device *device)
6893 {
6894         struct pci_dev *pdev = to_pci_dev(device);
6895         struct net_device *dev = pci_get_drvdata(pdev);
6896         struct rtl8169_private *tp = netdev_priv(dev);
6897         rtl_rar_set(tp, dev->dev_addr);
6898
6899         if (!tp->TxDescArray)
6900                 return 0;
6901
6902         rtl_lock_work(tp);
6903         __rtl8169_set_wol(tp, tp->saved_wolopts);
6904         rtl_unlock_work(tp);
6905
6906         __rtl8169_resume(dev);
6907
6908         return 0;
6909 }
6910
6911 static int rtl8169_runtime_idle(struct device *device)
6912 {
6913         struct pci_dev *pdev = to_pci_dev(device);
6914         struct net_device *dev = pci_get_drvdata(pdev);
6915
6916         if (!netif_running(dev) || !netif_carrier_ok(dev))
6917                 pm_schedule_suspend(device, 10000);
6918
6919         return -EBUSY;
6920 }
6921
6922 static const struct dev_pm_ops rtl8169_pm_ops = {
6923         .suspend                = rtl8169_suspend,
6924         .resume                 = rtl8169_resume,
6925         .freeze                 = rtl8169_suspend,
6926         .thaw                   = rtl8169_resume,
6927         .poweroff               = rtl8169_suspend,
6928         .restore                = rtl8169_resume,
6929         .runtime_suspend        = rtl8169_runtime_suspend,
6930         .runtime_resume         = rtl8169_runtime_resume,
6931         .runtime_idle           = rtl8169_runtime_idle,
6932 };
6933
6934 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6935
6936 #else /* !CONFIG_PM */
6937
6938 #define RTL8169_PM_OPS  NULL
6939
6940 #endif /* !CONFIG_PM */
6941
6942 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6943 {
6944         /* WoL fails with 8168b when the receiver is disabled. */
6945         switch (tp->mac_version) {
6946         case RTL_GIGA_MAC_VER_11:
6947         case RTL_GIGA_MAC_VER_12:
6948         case RTL_GIGA_MAC_VER_17:
6949                 pci_clear_master(tp->pci_dev);
6950
6951                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6952                 /* PCI commit */
6953                 RTL_R8(tp, ChipCmd);
6954                 break;
6955         default:
6956                 break;
6957         }
6958 }
6959
6960 static void rtl_shutdown(struct pci_dev *pdev)
6961 {
6962         struct net_device *dev = pci_get_drvdata(pdev);
6963         struct rtl8169_private *tp = netdev_priv(dev);
6964
6965         rtl8169_net_suspend(dev);
6966
6967         /* Restore original MAC address */
6968         rtl_rar_set(tp, dev->perm_addr);
6969
6970         rtl8169_hw_reset(tp);
6971
6972         if (system_state == SYSTEM_POWER_OFF) {
6973                 if (tp->saved_wolopts) {
6974                         rtl_wol_suspend_quirk(tp);
6975                         rtl_wol_shutdown_quirk(tp);
6976                 }
6977
6978                 pci_wake_from_d3(pdev, true);
6979                 pci_set_power_state(pdev, PCI_D3hot);
6980         }
6981 }
6982
6983 static void rtl_remove_one(struct pci_dev *pdev)
6984 {
6985         struct net_device *dev = pci_get_drvdata(pdev);
6986         struct rtl8169_private *tp = netdev_priv(dev);
6987
6988         if (r8168_check_dash(tp))
6989                 rtl8168_driver_stop(tp);
6990
6991         netif_napi_del(&tp->napi);
6992
6993         unregister_netdev(dev);
6994         mdiobus_unregister(tp->mii_bus);
6995
6996         rtl_release_firmware(tp);
6997
6998         if (pci_dev_run_wake(pdev))
6999                 pm_runtime_get_noresume(&pdev->dev);
7000
7001         /* restore original MAC address */
7002         rtl_rar_set(tp, dev->perm_addr);
7003 }
7004
7005 static const struct net_device_ops rtl_netdev_ops = {
7006         .ndo_open               = rtl_open,
7007         .ndo_stop               = rtl8169_close,
7008         .ndo_get_stats64        = rtl8169_get_stats64,
7009         .ndo_start_xmit         = rtl8169_start_xmit,
7010         .ndo_tx_timeout         = rtl8169_tx_timeout,
7011         .ndo_validate_addr      = eth_validate_addr,
7012         .ndo_change_mtu         = rtl8169_change_mtu,
7013         .ndo_fix_features       = rtl8169_fix_features,
7014         .ndo_set_features       = rtl8169_set_features,
7015         .ndo_set_mac_address    = rtl_set_mac_address,
7016         .ndo_do_ioctl           = rtl8169_ioctl,
7017         .ndo_set_rx_mode        = rtl_set_rx_mode,
7018 #ifdef CONFIG_NET_POLL_CONTROLLER
7019         .ndo_poll_controller    = rtl8169_netpoll,
7020 #endif
7021
7022 };
7023
7024 static const struct rtl_cfg_info {
7025         void (*hw_start)(struct rtl8169_private *tp);
7026         u16 event_slow;
7027         unsigned int has_gmii:1;
7028         const struct rtl_coalesce_info *coalesce_info;
7029         u8 default_ver;
7030 } rtl_cfg_infos [] = {
7031         [RTL_CFG_0] = {
7032                 .hw_start       = rtl_hw_start_8169,
7033                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7034                 .has_gmii       = 1,
7035                 .coalesce_info  = rtl_coalesce_info_8169,
7036                 .default_ver    = RTL_GIGA_MAC_VER_01,
7037         },
7038         [RTL_CFG_1] = {
7039                 .hw_start       = rtl_hw_start_8168,
7040                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7041                 .has_gmii       = 1,
7042                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7043                 .default_ver    = RTL_GIGA_MAC_VER_11,
7044         },
7045         [RTL_CFG_2] = {
7046                 .hw_start       = rtl_hw_start_8101,
7047                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7048                                   PCSTimeout,
7049                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7050                 .default_ver    = RTL_GIGA_MAC_VER_13,
7051         }
7052 };
7053
7054 static int rtl_alloc_irq(struct rtl8169_private *tp)
7055 {
7056         unsigned int flags;
7057
7058         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7059                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7060                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7061                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7062                 flags = PCI_IRQ_LEGACY;
7063         } else {
7064                 flags = PCI_IRQ_ALL_TYPES;
7065         }
7066
7067         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7068 }
7069
7070 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7071 {
7072         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7073 }
7074
7075 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7076 {
7077         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7078 }
7079
7080 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7081 {
7082         struct rtl8169_private *tp = mii_bus->priv;
7083
7084         if (phyaddr > 0)
7085                 return -ENODEV;
7086
7087         return rtl_readphy(tp, phyreg);
7088 }
7089
7090 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7091                                 int phyreg, u16 val)
7092 {
7093         struct rtl8169_private *tp = mii_bus->priv;
7094
7095         if (phyaddr > 0)
7096                 return -ENODEV;
7097
7098         rtl_writephy(tp, phyreg, val);
7099
7100         return 0;
7101 }
7102
7103 static int r8169_mdio_register(struct rtl8169_private *tp)
7104 {
7105         struct pci_dev *pdev = tp->pci_dev;
7106         struct phy_device *phydev;
7107         struct mii_bus *new_bus;
7108         int ret;
7109
7110         new_bus = devm_mdiobus_alloc(&pdev->dev);
7111         if (!new_bus)
7112                 return -ENOMEM;
7113
7114         new_bus->name = "r8169";
7115         new_bus->priv = tp;
7116         new_bus->parent = &pdev->dev;
7117         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7118         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7119                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7120
7121         new_bus->read = r8169_mdio_read_reg;
7122         new_bus->write = r8169_mdio_write_reg;
7123
7124         ret = mdiobus_register(new_bus);
7125         if (ret)
7126                 return ret;
7127
7128         phydev = mdiobus_get_phy(new_bus, 0);
7129         if (!phydev) {
7130                 mdiobus_unregister(new_bus);
7131                 return -ENODEV;
7132         }
7133
7134         /* PHY will be woken up in rtl_open() */
7135         phy_suspend(phydev);
7136
7137         tp->mii_bus = new_bus;
7138
7139         return 0;
7140 }
7141
7142 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7143 {
7144         u32 data;
7145
7146         tp->ocp_base = OCP_STD_PHY_BASE;
7147
7148         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7149
7150         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7151                 return;
7152
7153         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7154                 return;
7155
7156         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7157         msleep(1);
7158         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7159
7160         data = r8168_mac_ocp_read(tp, 0xe8de);
7161         data &= ~(1 << 14);
7162         r8168_mac_ocp_write(tp, 0xe8de, data);
7163
7164         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7165                 return;
7166
7167         data = r8168_mac_ocp_read(tp, 0xe8de);
7168         data |= (1 << 15);
7169         r8168_mac_ocp_write(tp, 0xe8de, data);
7170
7171         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7172                 return;
7173 }
7174
7175 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7176 {
7177         rtl8168ep_stop_cmac(tp);
7178         rtl_hw_init_8168g(tp);
7179 }
7180
7181 static void rtl_hw_initialize(struct rtl8169_private *tp)
7182 {
7183         switch (tp->mac_version) {
7184         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7185                 rtl_hw_init_8168g(tp);
7186                 break;
7187         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7188                 rtl_hw_init_8168ep(tp);
7189                 break;
7190         default:
7191                 break;
7192         }
7193 }
7194
7195 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7196 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7197 {
7198         switch (tp->mac_version) {
7199         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7200         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7201                 return false;
7202         default:
7203                 return true;
7204         }
7205 }
7206
7207 static int rtl_jumbo_max(struct rtl8169_private *tp)
7208 {
7209         /* Non-GBit versions don't support jumbo frames */
7210         if (!tp->supports_gmii)
7211                 return JUMBO_1K;
7212
7213         switch (tp->mac_version) {
7214         /* RTL8169 */
7215         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7216                 return JUMBO_7K;
7217         /* RTL8168b */
7218         case RTL_GIGA_MAC_VER_11:
7219         case RTL_GIGA_MAC_VER_12:
7220         case RTL_GIGA_MAC_VER_17:
7221                 return JUMBO_4K;
7222         /* RTL8168c */
7223         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7224                 return JUMBO_6K;
7225         default:
7226                 return JUMBO_9K;
7227         }
7228 }
7229
7230 static void rtl_disable_clk(void *data)
7231 {
7232         clk_disable_unprepare(data);
7233 }
7234
7235 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7236 {
7237         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7238         struct rtl8169_private *tp;
7239         struct net_device *dev;
7240         int chipset, region, i;
7241         int jumbo_max, rc;
7242
7243         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7244         if (!dev)
7245                 return -ENOMEM;
7246
7247         SET_NETDEV_DEV(dev, &pdev->dev);
7248         dev->netdev_ops = &rtl_netdev_ops;
7249         tp = netdev_priv(dev);
7250         tp->dev = dev;
7251         tp->pci_dev = pdev;
7252         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7253         tp->supports_gmii = cfg->has_gmii;
7254
7255         /* Get the *optional* external "ether_clk" used on some boards */
7256         tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7257         if (IS_ERR(tp->clk)) {
7258                 rc = PTR_ERR(tp->clk);
7259                 if (rc == -ENOENT) {
7260                         /* clk-core allows NULL (for suspend / resume) */
7261                         tp->clk = NULL;
7262                 } else if (rc == -EPROBE_DEFER) {
7263                         return rc;
7264                 } else {
7265                         dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7266                         return rc;
7267                 }
7268         } else {
7269                 rc = clk_prepare_enable(tp->clk);
7270                 if (rc) {
7271                         dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7272                         return rc;
7273                 }
7274
7275                 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7276                                               tp->clk);
7277                 if (rc)
7278                         return rc;
7279         }
7280
7281         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7282         rc = pcim_enable_device(pdev);
7283         if (rc < 0) {
7284                 dev_err(&pdev->dev, "enable failure\n");
7285                 return rc;
7286         }
7287
7288         if (pcim_set_mwi(pdev) < 0)
7289                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7290
7291         /* use first MMIO region */
7292         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7293         if (region < 0) {
7294                 dev_err(&pdev->dev, "no MMIO resource found\n");
7295                 return -ENODEV;
7296         }
7297
7298         /* check for weird/broken PCI region reporting */
7299         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7300                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7301                 return -ENODEV;
7302         }
7303
7304         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7305         if (rc < 0) {
7306                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7307                 return rc;
7308         }
7309
7310         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7311
7312         if (!pci_is_pcie(pdev))
7313                 dev_info(&pdev->dev, "not PCI Express\n");
7314
7315         /* Identify chip attached to board */
7316         rtl8169_get_mac_version(tp, cfg->default_ver);
7317
7318         if (rtl_tbi_enabled(tp)) {
7319                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7320                 return -ENODEV;
7321         }
7322
7323         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7324
7325         if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7326             tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7327             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7328
7329                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7330                 if (!pci_is_pcie(pdev))
7331                         tp->cp_cmd |= PCIDAC;
7332                 dev->features |= NETIF_F_HIGHDMA;
7333         } else {
7334                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7335                 if (rc < 0) {
7336                         dev_err(&pdev->dev, "DMA configuration failed\n");
7337                         return rc;
7338                 }
7339         }
7340
7341         rtl_init_rxcfg(tp);
7342
7343         rtl8169_irq_mask_and_ack(tp);
7344
7345         rtl_hw_initialize(tp);
7346
7347         rtl_hw_reset(tp);
7348
7349         pci_set_master(pdev);
7350
7351         rtl_init_mdio_ops(tp);
7352         rtl_init_jumbo_ops(tp);
7353
7354         rtl8169_print_mac_version(tp);
7355
7356         chipset = tp->mac_version;
7357
7358         rc = rtl_alloc_irq(tp);
7359         if (rc < 0) {
7360                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7361                 return rc;
7362         }
7363
7364         tp->saved_wolopts = __rtl8169_get_wol(tp);
7365
7366         mutex_init(&tp->wk.mutex);
7367         u64_stats_init(&tp->rx_stats.syncp);
7368         u64_stats_init(&tp->tx_stats.syncp);
7369
7370         /* Get MAC address */
7371         switch (tp->mac_version) {
7372                 u8 mac_addr[ETH_ALEN] __aligned(4);
7373         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7374         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7375                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7376                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7377
7378                 if (is_valid_ether_addr(mac_addr))
7379                         rtl_rar_set(tp, mac_addr);
7380                 break;
7381         default:
7382                 break;
7383         }
7384         for (i = 0; i < ETH_ALEN; i++)
7385                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7386
7387         dev->ethtool_ops = &rtl8169_ethtool_ops;
7388
7389         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7390
7391         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7392          * properly for all devices */
7393         dev->features |= NETIF_F_RXCSUM |
7394                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7395
7396         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7397                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7398                 NETIF_F_HW_VLAN_CTAG_RX;
7399         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7400                 NETIF_F_HIGHDMA;
7401         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7402
7403         tp->cp_cmd |= RxChkSum | RxVlan;
7404
7405         /*
7406          * Pretend we are using VLANs; This bypasses a nasty bug where
7407          * Interrupts stop flowing on high load on 8110SCd controllers.
7408          */
7409         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7410                 /* Disallow toggling */
7411                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7412
7413         if (rtl_chip_supports_csum_v2(tp)) {
7414                 tp->tso_csum = rtl8169_tso_csum_v2;
7415                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7416         } else {
7417                 tp->tso_csum = rtl8169_tso_csum_v1;
7418         }
7419
7420         dev->hw_features |= NETIF_F_RXALL;
7421         dev->hw_features |= NETIF_F_RXFCS;
7422
7423         /* MTU range: 60 - hw-specific max */
7424         dev->min_mtu = ETH_ZLEN;
7425         jumbo_max = rtl_jumbo_max(tp);
7426         dev->max_mtu = jumbo_max;
7427
7428         tp->hw_start = cfg->hw_start;
7429         tp->event_slow = cfg->event_slow;
7430         tp->coalesce_info = cfg->coalesce_info;
7431
7432         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7433
7434         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7435                                             &tp->counters_phys_addr,
7436                                             GFP_KERNEL);
7437         if (!tp->counters)
7438                 return -ENOMEM;
7439
7440         pci_set_drvdata(pdev, dev);
7441
7442         rc = r8169_mdio_register(tp);
7443         if (rc)
7444                 return rc;
7445
7446         /* chip gets powered up in rtl_open() */
7447         rtl_pll_power_down(tp);
7448
7449         rc = register_netdev(dev);
7450         if (rc)
7451                 goto err_mdio_unregister;
7452
7453         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7454                    rtl_chip_infos[chipset].name, dev->dev_addr,
7455                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7456                    pci_irq_vector(pdev, 0));
7457
7458         if (jumbo_max > JUMBO_1K)
7459                 netif_info(tp, probe, dev,
7460                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7461                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7462                            "ok" : "ko");
7463
7464         if (r8168_check_dash(tp))
7465                 rtl8168_driver_start(tp);
7466
7467         if (pci_dev_run_wake(pdev))
7468                 pm_runtime_put_sync(&pdev->dev);
7469
7470         return 0;
7471
7472 err_mdio_unregister:
7473         mdiobus_unregister(tp->mii_bus);
7474         return rc;
7475 }
7476
7477 static struct pci_driver rtl8169_pci_driver = {
7478         .name           = MODULENAME,
7479         .id_table       = rtl8169_pci_tbl,
7480         .probe          = rtl_init_one,
7481         .remove         = rtl_remove_one,
7482         .shutdown       = rtl_shutdown,
7483         .driver.pm      = RTL8169_PM_OPS,
7484 };
7485
7486 module_pci_driver(rtl8169_pci_driver);