drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/phy.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/prefetch.h>
  29 #include <linux/ipv6.h>
  30 #include <net/ip6_checksum.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 #define TX_SLOTS_AVAIL(tp) \
  62         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  63
  64 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  65 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  66         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  73 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  74
  75 #define R8169_REGS_SIZE         256
  76 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  77 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  78 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  79 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  80 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  81
  82 #define RTL8169_TX_TIMEOUT      (6*HZ)
  83
  84 /* write/read MMIO register */
  85 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  86 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  87 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  88 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  89 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  90 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  91
  92 enum mac_version {
  93         RTL_GIGA_MAC_VER_01 = 0,
  94         RTL_GIGA_MAC_VER_02,
  95         RTL_GIGA_MAC_VER_03,
  96         RTL_GIGA_MAC_VER_04,
  97         RTL_GIGA_MAC_VER_05,
  98         RTL_GIGA_MAC_VER_06,
  99         RTL_GIGA_MAC_VER_07,
 100         RTL_GIGA_MAC_VER_08,
 101         RTL_GIGA_MAC_VER_09,
 102         RTL_GIGA_MAC_VER_10,
 103         RTL_GIGA_MAC_VER_11,
 104         RTL_GIGA_MAC_VER_12,
 105         RTL_GIGA_MAC_VER_13,
 106         RTL_GIGA_MAC_VER_14,
 107         RTL_GIGA_MAC_VER_15,
 108         RTL_GIGA_MAC_VER_16,
 109         RTL_GIGA_MAC_VER_17,
 110         RTL_GIGA_MAC_VER_18,
 111         RTL_GIGA_MAC_VER_19,
 112         RTL_GIGA_MAC_VER_20,
 113         RTL_GIGA_MAC_VER_21,
 114         RTL_GIGA_MAC_VER_22,
 115         RTL_GIGA_MAC_VER_23,
 116         RTL_GIGA_MAC_VER_24,
 117         RTL_GIGA_MAC_VER_25,
 118         RTL_GIGA_MAC_VER_26,
 119         RTL_GIGA_MAC_VER_27,
 120         RTL_GIGA_MAC_VER_28,
 121         RTL_GIGA_MAC_VER_29,
 122         RTL_GIGA_MAC_VER_30,
 123         RTL_GIGA_MAC_VER_31,
 124         RTL_GIGA_MAC_VER_32,
 125         RTL_GIGA_MAC_VER_33,
 126         RTL_GIGA_MAC_VER_34,
 127         RTL_GIGA_MAC_VER_35,
 128         RTL_GIGA_MAC_VER_36,
 129         RTL_GIGA_MAC_VER_37,
 130         RTL_GIGA_MAC_VER_38,
 131         RTL_GIGA_MAC_VER_39,
 132         RTL_GIGA_MAC_VER_40,
 133         RTL_GIGA_MAC_VER_41,
 134         RTL_GIGA_MAC_VER_42,
 135         RTL_GIGA_MAC_VER_43,
 136         RTL_GIGA_MAC_VER_44,
 137         RTL_GIGA_MAC_VER_45,
 138         RTL_GIGA_MAC_VER_46,
 139         RTL_GIGA_MAC_VER_47,
 140         RTL_GIGA_MAC_VER_48,
 141         RTL_GIGA_MAC_VER_49,
 142         RTL_GIGA_MAC_VER_50,
 143         RTL_GIGA_MAC_VER_51,
 144         RTL_GIGA_MAC_NONE   = 0xff,
 145 };
 146
 147 enum rtl_tx_desc_version {
 148         RTL_TD_0        = 0,
 149         RTL_TD_1        = 1,
 150 };
 151
 152 #define JUMBO_1K        ETH_DATA_LEN
 153 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 154 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 155 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 156 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 157
 158 #define _R(NAME,TD,FW,SZ) {     \
 159         .name = NAME,           \
 160         .txd_version = TD,      \
 161         .fw_name = FW,          \
 162         .jumbo_max = SZ,        \
 163 }
 164
 165 static const struct {
 166         const char *name;
 167         enum rtl_tx_desc_version txd_version;
 168         const char *fw_name;
 169         u16 jumbo_max;
 170 } rtl_chip_infos[] = {
 171         /* PCI devices. */
 172         [RTL_GIGA_MAC_VER_01] =
 173                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K),
 174         [RTL_GIGA_MAC_VER_02] =
 175                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K),
 176         [RTL_GIGA_MAC_VER_03] =
 177                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K),
 178         [RTL_GIGA_MAC_VER_04] =
 179                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K),
 180         [RTL_GIGA_MAC_VER_05] =
 181                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 182         [RTL_GIGA_MAC_VER_06] =
 183                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 184         /* PCI-E devices. */
 185         [RTL_GIGA_MAC_VER_07] =
 186                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 187         [RTL_GIGA_MAC_VER_08] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 189         [RTL_GIGA_MAC_VER_09] =
 190                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 191         [RTL_GIGA_MAC_VER_10] =
 192                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 193         [RTL_GIGA_MAC_VER_11] =
 194                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 195         [RTL_GIGA_MAC_VER_12] =
 196                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 197         [RTL_GIGA_MAC_VER_13] =
 198                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 199         [RTL_GIGA_MAC_VER_14] =
 200                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 201         [RTL_GIGA_MAC_VER_15] =
 202                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 203         [RTL_GIGA_MAC_VER_16] =
 204                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 205         [RTL_GIGA_MAC_VER_17] =
 206                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 207         [RTL_GIGA_MAC_VER_18] =
 208                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 209         [RTL_GIGA_MAC_VER_19] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 211         [RTL_GIGA_MAC_VER_20] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 213         [RTL_GIGA_MAC_VER_21] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 215         [RTL_GIGA_MAC_VER_22] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 217         [RTL_GIGA_MAC_VER_23] =
 218                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 219         [RTL_GIGA_MAC_VER_24] =
 220                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 221         [RTL_GIGA_MAC_VER_25] =
 222                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
 223         [RTL_GIGA_MAC_VER_26] =
 224                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
 225         [RTL_GIGA_MAC_VER_27] =
 226                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 227         [RTL_GIGA_MAC_VER_28] =
 228                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 229         [RTL_GIGA_MAC_VER_29] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 231         [RTL_GIGA_MAC_VER_30] =
 232                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 233         [RTL_GIGA_MAC_VER_31] =
 234                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 235         [RTL_GIGA_MAC_VER_32] =
 236                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
 237         [RTL_GIGA_MAC_VER_33] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
 239         [RTL_GIGA_MAC_VER_34] =
 240                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
 241         [RTL_GIGA_MAC_VER_35] =
 242                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
 243         [RTL_GIGA_MAC_VER_36] =
 244                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
 245         [RTL_GIGA_MAC_VER_37] =
 246                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,  JUMBO_1K),
 247         [RTL_GIGA_MAC_VER_38] =
 248                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,  JUMBO_9K),
 249         [RTL_GIGA_MAC_VER_39] =
 250                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
 251         [RTL_GIGA_MAC_VER_40] =
 252                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
 253         [RTL_GIGA_MAC_VER_41] =
 254                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K),
 255         [RTL_GIGA_MAC_VER_42] =
 256                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
 257         [RTL_GIGA_MAC_VER_43] =
 258                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
 259         [RTL_GIGA_MAC_VER_44] =
 260                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,  JUMBO_9K),
 261         [RTL_GIGA_MAC_VER_45] =
 262                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
 263         [RTL_GIGA_MAC_VER_46] =
 264                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
 265         [RTL_GIGA_MAC_VER_47] =
 266                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
 267         [RTL_GIGA_MAC_VER_48] =
 268                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
 269         [RTL_GIGA_MAC_VER_49] =
 270                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 271         [RTL_GIGA_MAC_VER_50] =
 272                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 273         [RTL_GIGA_MAC_VER_51] =
 274                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 275 };
 276 #undef _R
 277
 278 enum cfg_version {
 279         RTL_CFG_0 = 0x00,
 280         RTL_CFG_1,
 281         RTL_CFG_2
 282 };
 283
 284 static const struct pci_device_id rtl8169_pci_tbl[] = {
 285         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 286         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 287         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 288         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 289         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 290         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 291         { PCI_VENDOR_ID_DLINK,                  0x4300,
 292                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 293         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 294         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 295         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 296         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 297         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 298                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 299         { 0x0001,                               0x8168,
 300                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 301         {0,},
 302 };
 303
 304 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 305
 306 static int use_dac = -1;
 307 static struct {
 308         u32 msg_enable;
 309 } debug = { -1 };
 310
 311 enum rtl_registers {
 312         MAC0            = 0,    /* Ethernet hardware address. */
 313         MAC4            = 4,
 314         MAR0            = 8,    /* Multicast filter. */
 315         CounterAddrLow          = 0x10,
 316         CounterAddrHigh         = 0x14,
 317         TxDescStartAddrLow      = 0x20,
 318         TxDescStartAddrHigh     = 0x24,
 319         TxHDescStartAddrLow     = 0x28,
 320         TxHDescStartAddrHigh    = 0x2c,
 321         FLASH           = 0x30,
 322         ERSR            = 0x36,
 323         ChipCmd         = 0x37,
 324         TxPoll          = 0x38,
 325         IntrMask        = 0x3c,
 326         IntrStatus      = 0x3e,
 327
 328         TxConfig        = 0x40,
 329 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 330 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 331
 332         RxConfig        = 0x44,
 333 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 334 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 335 #define RXCFG_FIFO_SHIFT                13
 336                                         /* No threshold before first PCI xfer */
 337 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 338 #define RX_EARLY_OFF                    (1 << 11)
 339 #define RXCFG_DMA_SHIFT                 8
 340                                         /* Unlimited maximum PCI burst. */
 341 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 342
 343         RxMissed        = 0x4c,
 344         Cfg9346         = 0x50,
 345         Config0         = 0x51,
 346         Config1         = 0x52,
 347         Config2         = 0x53,
 348 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 349
 350         Config3         = 0x54,
 351         Config4         = 0x55,
 352         Config5         = 0x56,
 353         MultiIntr       = 0x5c,
 354         PHYAR           = 0x60,
 355         PHYstatus       = 0x6c,
 356         RxMaxSize       = 0xda,
 357         CPlusCmd        = 0xe0,
 358         IntrMitigate    = 0xe2,
 359
 360 #define RTL_COALESCE_MASK       0x0f
 361 #define RTL_COALESCE_SHIFT      4
 362 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 363 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 364
 365         RxDescAddrLow   = 0xe4,
 366         RxDescAddrHigh  = 0xe8,
 367         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 368
 369 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 370
 371         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 372
 373 #define TxPacketMax     (8064 >> 7)
 374 #define EarlySize       0x27
 375
 376         FuncEvent       = 0xf0,
 377         FuncEventMask   = 0xf4,
 378         FuncPresetState = 0xf8,
 379         IBCR0           = 0xf8,
 380         IBCR2           = 0xf9,
 381         IBIMR0          = 0xfa,
 382         IBISR0          = 0xfb,
 383         FuncForceEvent  = 0xfc,
 384 };
 385
 386 enum rtl8168_8101_registers {
 387         CSIDR                   = 0x64,
 388         CSIAR                   = 0x68,
 389 #define CSIAR_FLAG                      0x80000000
 390 #define CSIAR_WRITE_CMD                 0x80000000
 391 #define CSIAR_BYTE_ENABLE               0x0000f000
 392 #define CSIAR_ADDR_MASK                 0x00000fff
 393         PMCH                    = 0x6f,
 394         EPHYAR                  = 0x80,
 395 #define EPHYAR_FLAG                     0x80000000
 396 #define EPHYAR_WRITE_CMD                0x80000000
 397 #define EPHYAR_REG_MASK                 0x1f
 398 #define EPHYAR_REG_SHIFT                16
 399 #define EPHYAR_DATA_MASK                0xffff
 400         DLLPR                   = 0xd0,
 401 #define PFM_EN                          (1 << 6)
 402 #define TX_10M_PS_EN                    (1 << 7)
 403         DBG_REG                 = 0xd1,
 404 #define FIX_NAK_1                       (1 << 4)
 405 #define FIX_NAK_2                       (1 << 3)
 406         TWSI                    = 0xd2,
 407         MCU                     = 0xd3,
 408 #define NOW_IS_OOB                      (1 << 7)
 409 #define TX_EMPTY                        (1 << 5)
 410 #define RX_EMPTY                        (1 << 4)
 411 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 412 #define EN_NDP                          (1 << 3)
 413 #define EN_OOB_RESET                    (1 << 2)
 414 #define LINK_LIST_RDY                   (1 << 1)
 415         EFUSEAR                 = 0xdc,
 416 #define EFUSEAR_FLAG                    0x80000000
 417 #define EFUSEAR_WRITE_CMD               0x80000000
 418 #define EFUSEAR_READ_CMD                0x00000000
 419 #define EFUSEAR_REG_MASK                0x03ff
 420 #define EFUSEAR_REG_SHIFT               8
 421 #define EFUSEAR_DATA_MASK               0xff
 422         MISC_1                  = 0xf2,
 423 #define PFM_D3COLD_EN                   (1 << 6)
 424 };
 425
 426 enum rtl8168_registers {
 427         LED_FREQ                = 0x1a,
 428         EEE_LED                 = 0x1b,
 429         ERIDR                   = 0x70,
 430         ERIAR                   = 0x74,
 431 #define ERIAR_FLAG                      0x80000000
 432 #define ERIAR_WRITE_CMD                 0x80000000
 433 #define ERIAR_READ_CMD                  0x00000000
 434 #define ERIAR_ADDR_BYTE_ALIGN           4
 435 #define ERIAR_TYPE_SHIFT                16
 436 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 437 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 438 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 439 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 440 #define ERIAR_MASK_SHIFT                12
 441 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 442 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 443 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 444 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 445 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 446         EPHY_RXER_NUM           = 0x7c,
 447         OCPDR                   = 0xb0, /* OCP GPHY access */
 448 #define OCPDR_WRITE_CMD                 0x80000000
 449 #define OCPDR_READ_CMD                  0x00000000
 450 #define OCPDR_REG_MASK                  0x7f
 451 #define OCPDR_GPHY_REG_SHIFT            16
 452 #define OCPDR_DATA_MASK                 0xffff
 453         OCPAR                   = 0xb4,
 454 #define OCPAR_FLAG                      0x80000000
 455 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 456 #define OCPAR_GPHY_READ_CMD             0x0000f060
 457         GPHY_OCP                = 0xb8,
 458         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 459         MISC                    = 0xf0, /* 8168e only. */
 460 #define TXPLA_RST                       (1 << 29)
 461 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 462 #define PWM_EN                          (1 << 22)
 463 #define RXDV_GATED_EN                   (1 << 19)
 464 #define EARLY_TALLY_EN                  (1 << 16)
 465 };
 466
 467 enum rtl_register_content {
 468         /* InterruptStatusBits */
 469         SYSErr          = 0x8000,
 470         PCSTimeout      = 0x4000,
 471         SWInt           = 0x0100,
 472         TxDescUnavail   = 0x0080,
 473         RxFIFOOver      = 0x0040,
 474         LinkChg         = 0x0020,
 475         RxOverflow      = 0x0010,
 476         TxErr           = 0x0008,
 477         TxOK            = 0x0004,
 478         RxErr           = 0x0002,
 479         RxOK            = 0x0001,
 480
 481         /* RxStatusDesc */
 482         RxBOVF  = (1 << 24),
 483         RxFOVF  = (1 << 23),
 484         RxRWT   = (1 << 22),
 485         RxRES   = (1 << 21),
 486         RxRUNT  = (1 << 20),
 487         RxCRC   = (1 << 19),
 488
 489         /* ChipCmdBits */
 490         StopReq         = 0x80,
 491         CmdReset        = 0x10,
 492         CmdRxEnb        = 0x08,
 493         CmdTxEnb        = 0x04,
 494         RxBufEmpty      = 0x01,
 495
 496         /* TXPoll register p.5 */
 497         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 498         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 499         FSWInt          = 0x01,         /* Forced software interrupt */
 500
 501         /* Cfg9346Bits */
 502         Cfg9346_Lock    = 0x00,
 503         Cfg9346_Unlock  = 0xc0,
 504
 505         /* rx_mode_bits */
 506         AcceptErr       = 0x20,
 507         AcceptRunt      = 0x10,
 508         AcceptBroadcast = 0x08,
 509         AcceptMulticast = 0x04,
 510         AcceptMyPhys    = 0x02,
 511         AcceptAllPhys   = 0x01,
 512 #define RX_CONFIG_ACCEPT_MASK           0x3f
 513
 514         /* TxConfigBits */
 515         TxInterFrameGapShift = 24,
 516         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 517
 518         /* Config1 register p.24 */
 519         LEDS1           = (1 << 7),
 520         LEDS0           = (1 << 6),
 521         Speed_down      = (1 << 4),
 522         MEMMAP          = (1 << 3),
 523         IOMAP           = (1 << 2),
 524         VPD             = (1 << 1),
 525         PMEnable        = (1 << 0),     /* Power Management Enable */
 526
 527         /* Config2 register p. 25 */
 528         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 529         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 530         PCI_Clock_66MHz = 0x01,
 531         PCI_Clock_33MHz = 0x00,
 532
 533         /* Config3 register p.25 */
 534         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 535         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 536         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 537         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 538         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 539
 540         /* Config4 register */
 541         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 542
 543         /* Config5 register p.27 */
 544         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 545         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 546         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 547         Spi_en          = (1 << 3),
 548         LanWake         = (1 << 1),     /* LanWake enable/disable */
 549         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 550         ASPM_en         = (1 << 0),     /* ASPM enable */
 551
 552         /* CPlusCmd p.31 */
 553         EnableBist      = (1 << 15),    // 8168 8101
 554         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 555         Normal_mode     = (1 << 13),    // unused
 556         Force_half_dup  = (1 << 12),    // 8168 8101
 557         Force_rxflow_en = (1 << 11),    // 8168 8101
 558         Force_txflow_en = (1 << 10),    // 8168 8101
 559         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 560         ASF             = (1 << 8),     // 8168 8101
 561         PktCntrDisable  = (1 << 7),     // 8168 8101
 562         Mac_dbgo_sel    = 0x001c,       // 8168
 563         RxVlan          = (1 << 6),
 564         RxChkSum        = (1 << 5),
 565         PCIDAC          = (1 << 4),
 566         PCIMulRW        = (1 << 3),
 567 #define INTT_MASK       GENMASK(1, 0)
 568         INTT_0          = 0x0000,       // 8168
 569         INTT_1          = 0x0001,       // 8168
 570         INTT_2          = 0x0002,       // 8168
 571         INTT_3          = 0x0003,       // 8168
 572
 573         /* rtl8169_PHYstatus */
 574         TBI_Enable      = 0x80,
 575         TxFlowCtrl      = 0x40,
 576         RxFlowCtrl      = 0x20,
 577         _1000bpsF       = 0x10,
 578         _100bps         = 0x08,
 579         _10bps          = 0x04,
 580         LinkStatus      = 0x02,
 581         FullDup         = 0x01,
 582
 583         /* _TBICSRBit */
 584         TBILinkOK       = 0x02000000,
 585
 586         /* ResetCounterCommand */
 587         CounterReset    = 0x1,
 588
 589         /* DumpCounterCommand */
 590         CounterDump     = 0x8,
 591
 592         /* magic enable v2 */
 593         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 594 };
 595
 596 enum rtl_desc_bit {
 597         /* First doubleword. */
 598         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 599         RingEnd         = (1 << 30), /* End of descriptor ring */
 600         FirstFrag       = (1 << 29), /* First segment of a packet */
 601         LastFrag        = (1 << 28), /* Final segment of a packet */
 602 };
 603
 604 /* Generic case. */
 605 enum rtl_tx_desc_bit {
 606         /* First doubleword. */
 607         TD_LSO          = (1 << 27),            /* Large Send Offload */
 608 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 609
 610         /* Second doubleword. */
 611         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 612 };
 613
 614 /* 8169, 8168b and 810x except 8102e. */
 615 enum rtl_tx_desc_bit_0 {
 616         /* First doubleword. */
 617 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 618         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 619         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 620         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 621 };
 622
 623 /* 8102e, 8168c and beyond. */
 624 enum rtl_tx_desc_bit_1 {
 625         /* First doubleword. */
 626         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 627         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 628 #define GTTCPHO_SHIFT                   18
 629 #define GTTCPHO_MAX                     0x7fU
 630
 631         /* Second doubleword. */
 632 #define TCPHO_SHIFT                     18
 633 #define TCPHO_MAX                       0x3ffU
 634 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 635         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 636         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 637         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 638         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 639 };
 640
 641 enum rtl_rx_desc_bit {
 642         /* Rx private */
 643         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 644         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 645
 646 #define RxProtoUDP      (PID1)
 647 #define RxProtoTCP      (PID0)
 648 #define RxProtoIP       (PID1 | PID0)
 649 #define RxProtoMask     RxProtoIP
 650
 651         IPFail          = (1 << 16), /* IP checksum failed */
 652         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 653         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 654         RxVlanTag       = (1 << 16), /* VLAN tag available */
 655 };
 656
 657 #define RsvdMask        0x3fffc000
 658 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 659
 660 struct TxDesc {
 661         __le32 opts1;
 662         __le32 opts2;
 663         __le64 addr;
 664 };
 665
 666 struct RxDesc {
 667         __le32 opts1;
 668         __le32 opts2;
 669         __le64 addr;
 670 };
 671
 672 struct ring_info {
 673         struct sk_buff  *skb;
 674         u32             len;
 675         u8              __pad[sizeof(void *) - sizeof(u32)];
 676 };
 677
 678 struct rtl8169_counters {
 679         __le64  tx_packets;
 680         __le64  rx_packets;
 681         __le64  tx_errors;
 682         __le32  rx_errors;
 683         __le16  rx_missed;
 684         __le16  align_errors;
 685         __le32  tx_one_collision;
 686         __le32  tx_multi_collision;
 687         __le64  rx_unicast;
 688         __le64  rx_broadcast;
 689         __le32  rx_multicast;
 690         __le16  tx_aborted;
 691         __le16  tx_underun;
 692 };
 693
 694 struct rtl8169_tc_offsets {
 695         bool    inited;
 696         __le64  tx_errors;
 697         __le32  tx_multi_collision;
 698         __le16  tx_aborted;
 699 };
 700
 701 enum rtl_flag {
 702         RTL_FLAG_TASK_ENABLED,
 703         RTL_FLAG_TASK_SLOW_PENDING,
 704         RTL_FLAG_TASK_RESET_PENDING,
 705         RTL_FLAG_MAX
 706 };
 707
 708 struct rtl8169_stats {
 709         u64                     packets;
 710         u64                     bytes;
 711         struct u64_stats_sync   syncp;
 712 };
 713
 714 struct rtl8169_private {
 715         void __iomem *mmio_addr;        /* memory map physical address */
 716         struct pci_dev *pci_dev;
 717         struct net_device *dev;
 718         struct napi_struct napi;
 719         u32 msg_enable;
 720         u16 mac_version;
 721         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 722         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 723         u32 dirty_tx;
 724         struct rtl8169_stats rx_stats;
 725         struct rtl8169_stats tx_stats;
 726         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 727         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 728         dma_addr_t TxPhyAddr;
 729         dma_addr_t RxPhyAddr;
 730         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 731         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 732         u16 cp_cmd;
 733
 734         u16 event_slow;
 735         const struct rtl_coalesce_info *coalesce_info;
 736
 737         struct mdio_ops {
 738                 void (*write)(struct rtl8169_private *, int, int);
 739                 int (*read)(struct rtl8169_private *, int);
 740         } mdio_ops;
 741
 742         struct jumbo_ops {
 743                 void (*enable)(struct rtl8169_private *);
 744                 void (*disable)(struct rtl8169_private *);
 745         } jumbo_ops;
 746
 747         void (*hw_start)(struct rtl8169_private *tp);
 748         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 749
 750         struct {
 751                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 752                 struct mutex mutex;
 753                 struct work_struct work;
 754         } wk;
 755
 756         unsigned supports_gmii:1;
 757         struct mii_bus *mii_bus;
 758         dma_addr_t counters_phys_addr;
 759         struct rtl8169_counters *counters;
 760         struct rtl8169_tc_offsets tc_offset;
 761         u32 saved_wolopts;
 762
 763         struct rtl_fw {
 764                 const struct firmware *fw;
 765
 766 #define RTL_VER_SIZE            32
 767
 768                 char version[RTL_VER_SIZE];
 769
 770                 struct rtl_fw_phy_action {
 771                         __le32 *code;
 772                         size_t size;
 773                 } phy_action;
 774         } *rtl_fw;
 775 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 776
 777         u32 ocp_base;
 778 };
 779
 780 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 781 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 782 module_param(use_dac, int, 0);
 783 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 784 module_param_named(debug, debug.msg_enable, int, 0);
 785 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 786 MODULE_LICENSE("GPL");
 787 MODULE_VERSION(RTL8169_VERSION);
 788 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 789 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 790 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 791 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 792 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 793 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 794 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 795 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 796 MODULE_FIRMWARE(FIRMWARE_8402_1);
 797 MODULE_FIRMWARE(FIRMWARE_8411_1);
 798 MODULE_FIRMWARE(FIRMWARE_8411_2);
 799 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 800 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 801 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 802 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 803 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 804 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 805 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 806 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 807
 808 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 809 {
 810         return &tp->pci_dev->dev;
 811 }
 812
 813 static void rtl_lock_work(struct rtl8169_private *tp)
 814 {
 815         mutex_lock(&tp->wk.mutex);
 816 }
 817
 818 static void rtl_unlock_work(struct rtl8169_private *tp)
 819 {
 820         mutex_unlock(&tp->wk.mutex);
 821 }
 822
 823 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 824 {
 825         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 826                                            PCI_EXP_DEVCTL_READRQ, force);
 827 }
 828
 829 struct rtl_cond {
 830         bool (*check)(struct rtl8169_private *);
 831         const char *msg;
 832 };
 833
 834 static void rtl_udelay(unsigned int d)
 835 {
 836         udelay(d);
 837 }
 838
 839 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 840                           void (*delay)(unsigned int), unsigned int d, int n,
 841                           bool high)
 842 {
 843         int i;
 844
 845         for (i = 0; i < n; i++) {
 846                 delay(d);
 847                 if (c->check(tp) == high)
 848                         return true;
 849         }
 850         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 851                   c->msg, !high, n, d);
 852         return false;
 853 }
 854
 855 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 856                                       const struct rtl_cond *c,
 857                                       unsigned int d, int n)
 858 {
 859         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 860 }
 861
 862 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 863                                      const struct rtl_cond *c,
 864                                      unsigned int d, int n)
 865 {
 866         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 867 }
 868
 869 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 870                                       const struct rtl_cond *c,
 871                                       unsigned int d, int n)
 872 {
 873         return rtl_loop_wait(tp, c, msleep, d, n, true);
 874 }
 875
 876 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 877                                      const struct rtl_cond *c,
 878                                      unsigned int d, int n)
 879 {
 880         return rtl_loop_wait(tp, c, msleep, d, n, false);
 881 }
 882
 883 #define DECLARE_RTL_COND(name)                          \
 884 static bool name ## _check(struct rtl8169_private *);   \
 885                                                         \
 886 static const struct rtl_cond name = {                   \
 887         .check  = name ## _check,                       \
 888         .msg    = #name                                 \
 889 };                                                      \
 890                                                         \
 891 static bool name ## _check(struct rtl8169_private *tp)
 892
 893 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 894 {
 895         if (reg & 0xffff0001) {
 896                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 897                 return true;
 898         }
 899         return false;
 900 }
 901
 902 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 903 {
 904         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 905 }
 906
 907 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 908 {
 909         if (rtl_ocp_reg_failure(tp, reg))
 910                 return;
 911
 912         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 913
 914         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 915 }
 916
 917 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 918 {
 919         if (rtl_ocp_reg_failure(tp, reg))
 920                 return 0;
 921
 922         RTL_W32(tp, GPHY_OCP, reg << 15);
 923
 924         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 925                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 926 }
 927
 928 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 929 {
 930         if (rtl_ocp_reg_failure(tp, reg))
 931                 return;
 932
 933         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 934 }
 935
 936 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 937 {
 938         if (rtl_ocp_reg_failure(tp, reg))
 939                 return 0;
 940
 941         RTL_W32(tp, OCPDR, reg << 15);
 942
 943         return RTL_R32(tp, OCPDR);
 944 }
 945
 946 #define OCP_STD_PHY_BASE        0xa400
 947
 948 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 949 {
 950         if (reg == 0x1f) {
 951                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 952                 return;
 953         }
 954
 955         if (tp->ocp_base != OCP_STD_PHY_BASE)
 956                 reg -= 0x10;
 957
 958         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 959 }
 960
 961 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 962 {
 963         if (tp->ocp_base != OCP_STD_PHY_BASE)
 964                 reg -= 0x10;
 965
 966         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 967 }
 968
 969 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 970 {
 971         if (reg == 0x1f) {
 972                 tp->ocp_base = value << 4;
 973                 return;
 974         }
 975
 976         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 977 }
 978
 979 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 980 {
 981         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 982 }
 983
 984 DECLARE_RTL_COND(rtl_phyar_cond)
 985 {
 986         return RTL_R32(tp, PHYAR) & 0x80000000;
 987 }
 988
 989 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 990 {
 991         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 992
 993         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 994         /*
 995          * According to hardware specs a 20us delay is required after write
 996          * complete indication, but before sending next command.
 997          */
 998         udelay(20);
 999 }
1000
1001 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1002 {
1003         int value;
1004
1005         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1006
1007         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1008                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1009
1010         /*
1011          * According to hardware specs a 20us delay is required after read
1012          * complete indication, but before sending next command.
1013          */
1014         udelay(20);
1015
1016         return value;
1017 }
1018
1019 DECLARE_RTL_COND(rtl_ocpar_cond)
1020 {
1021         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1022 }
1023
1024 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1025 {
1026         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1027         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1028         RTL_W32(tp, EPHY_RXER_NUM, 0);
1029
1030         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1031 }
1032
1033 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1034 {
1035         r8168dp_1_mdio_access(tp, reg,
1036                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1037 }
1038
1039 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1040 {
1041         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1042
1043         mdelay(1);
1044         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1045         RTL_W32(tp, EPHY_RXER_NUM, 0);
1046
1047         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1048                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1049 }
1050
1051 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1052
1053 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1054 {
1055         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1056 }
1057
1058 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1059 {
1060         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1061 }
1062
1063 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1064 {
1065         r8168dp_2_mdio_start(tp);
1066
1067         r8169_mdio_write(tp, reg, value);
1068
1069         r8168dp_2_mdio_stop(tp);
1070 }
1071
1072 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1073 {
1074         int value;
1075
1076         r8168dp_2_mdio_start(tp);
1077
1078         value = r8169_mdio_read(tp, reg);
1079
1080         r8168dp_2_mdio_stop(tp);
1081
1082         return value;
1083 }
1084
1085 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1086 {
1087         tp->mdio_ops.write(tp, location, val);
1088 }
1089
1090 static int rtl_readphy(struct rtl8169_private *tp, int location)
1091 {
1092         return tp->mdio_ops.read(tp, location);
1093 }
1094
1095 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1096 {
1097         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1098 }
1099
1100 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1101 {
1102         int val;
1103
1104         val = rtl_readphy(tp, reg_addr);
1105         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1106 }
1107
1108 DECLARE_RTL_COND(rtl_ephyar_cond)
1109 {
1110         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1111 }
1112
1113 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1114 {
1115         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1116                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1117
1118         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1119
1120         udelay(10);
1121 }
1122
1123 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1124 {
1125         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1126
1127         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1128                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1129 }
1130
1131 DECLARE_RTL_COND(rtl_eriar_cond)
1132 {
1133         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1134 }
1135
1136 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1137                           u32 val, int type)
1138 {
1139         BUG_ON((addr & 3) || (mask == 0));
1140         RTL_W32(tp, ERIDR, val);
1141         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1142
1143         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1144 }
1145
1146 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1147 {
1148         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1149
1150         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1151                 RTL_R32(tp, ERIDR) : ~0;
1152 }
1153
1154 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1155                          u32 m, int type)
1156 {
1157         u32 val;
1158
1159         val = rtl_eri_read(tp, addr, type);
1160         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1161 }
1162
1163 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1164 {
1165         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1166         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1167                 RTL_R32(tp, OCPDR) : ~0;
1168 }
1169
1170 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1171 {
1172         return rtl_eri_read(tp, reg, ERIAR_OOB);
1173 }
1174
1175 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1176 {
1177         switch (tp->mac_version) {
1178         case RTL_GIGA_MAC_VER_27:
1179         case RTL_GIGA_MAC_VER_28:
1180         case RTL_GIGA_MAC_VER_31:
1181                 return r8168dp_ocp_read(tp, mask, reg);
1182         case RTL_GIGA_MAC_VER_49:
1183         case RTL_GIGA_MAC_VER_50:
1184         case RTL_GIGA_MAC_VER_51:
1185                 return r8168ep_ocp_read(tp, mask, reg);
1186         default:
1187                 BUG();
1188                 return ~0;
1189         }
1190 }
1191
1192 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1193                               u32 data)
1194 {
1195         RTL_W32(tp, OCPDR, data);
1196         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1197         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1198 }
1199
1200 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1201                               u32 data)
1202 {
1203         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1204                       data, ERIAR_OOB);
1205 }
1206
1207 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1208 {
1209         switch (tp->mac_version) {
1210         case RTL_GIGA_MAC_VER_27:
1211         case RTL_GIGA_MAC_VER_28:
1212         case RTL_GIGA_MAC_VER_31:
1213                 r8168dp_ocp_write(tp, mask, reg, data);
1214                 break;
1215         case RTL_GIGA_MAC_VER_49:
1216         case RTL_GIGA_MAC_VER_50:
1217         case RTL_GIGA_MAC_VER_51:
1218                 r8168ep_ocp_write(tp, mask, reg, data);
1219                 break;
1220         default:
1221                 BUG();
1222                 break;
1223         }
1224 }
1225
1226 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1227 {
1228         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1229
1230         ocp_write(tp, 0x1, 0x30, 0x00000001);
1231 }
1232
1233 #define OOB_CMD_RESET           0x00
1234 #define OOB_CMD_DRIVER_START    0x05
1235 #define OOB_CMD_DRIVER_STOP     0x06
1236
1237 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1238 {
1239         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1240 }
1241
1242 DECLARE_RTL_COND(rtl_ocp_read_cond)
1243 {
1244         u16 reg;
1245
1246         reg = rtl8168_get_ocp_reg(tp);
1247
1248         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1249 }
1250
1251 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1252 {
1253         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1254 }
1255
1256 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1257 {
1258         return RTL_R8(tp, IBISR0) & 0x20;
1259 }
1260
1261 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1262 {
1263         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1264         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1265         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1266         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1267 }
1268
1269 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1270 {
1271         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1272         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1273 }
1274
1275 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1276 {
1277         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1278         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1279         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1280 }
1281
1282 static void rtl8168_driver_start(struct rtl8169_private *tp)
1283 {
1284         switch (tp->mac_version) {
1285         case RTL_GIGA_MAC_VER_27:
1286         case RTL_GIGA_MAC_VER_28:
1287         case RTL_GIGA_MAC_VER_31:
1288                 rtl8168dp_driver_start(tp);
1289                 break;
1290         case RTL_GIGA_MAC_VER_49:
1291         case RTL_GIGA_MAC_VER_50:
1292         case RTL_GIGA_MAC_VER_51:
1293                 rtl8168ep_driver_start(tp);
1294                 break;
1295         default:
1296                 BUG();
1297                 break;
1298         }
1299 }
1300
1301 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1302 {
1303         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1304         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1305 }
1306
1307 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1308 {
1309         rtl8168ep_stop_cmac(tp);
1310         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1311         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1312         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1313 }
1314
1315 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1316 {
1317         switch (tp->mac_version) {
1318         case RTL_GIGA_MAC_VER_27:
1319         case RTL_GIGA_MAC_VER_28:
1320         case RTL_GIGA_MAC_VER_31:
1321                 rtl8168dp_driver_stop(tp);
1322                 break;
1323         case RTL_GIGA_MAC_VER_49:
1324         case RTL_GIGA_MAC_VER_50:
1325         case RTL_GIGA_MAC_VER_51:
1326                 rtl8168ep_driver_stop(tp);
1327                 break;
1328         default:
1329                 BUG();
1330                 break;
1331         }
1332 }
1333
1334 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1335 {
1336         u16 reg = rtl8168_get_ocp_reg(tp);
1337
1338         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1339 }
1340
1341 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1342 {
1343         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1344 }
1345
1346 static bool r8168_check_dash(struct rtl8169_private *tp)
1347 {
1348         switch (tp->mac_version) {
1349         case RTL_GIGA_MAC_VER_27:
1350         case RTL_GIGA_MAC_VER_28:
1351         case RTL_GIGA_MAC_VER_31:
1352                 return r8168dp_check_dash(tp);
1353         case RTL_GIGA_MAC_VER_49:
1354         case RTL_GIGA_MAC_VER_50:
1355         case RTL_GIGA_MAC_VER_51:
1356                 return r8168ep_check_dash(tp);
1357         default:
1358                 return false;
1359         }
1360 }
1361
1362 struct exgmac_reg {
1363         u16 addr;
1364         u16 mask;
1365         u32 val;
1366 };
1367
1368 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1369                                    const struct exgmac_reg *r, int len)
1370 {
1371         while (len-- > 0) {
1372                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1373                 r++;
1374         }
1375 }
1376
1377 DECLARE_RTL_COND(rtl_efusear_cond)
1378 {
1379         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1380 }
1381
1382 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1383 {
1384         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1385
1386         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1387                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1388 }
1389
1390 static u16 rtl_get_events(struct rtl8169_private *tp)
1391 {
1392         return RTL_R16(tp, IntrStatus);
1393 }
1394
1395 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1396 {
1397         RTL_W16(tp, IntrStatus, bits);
1398         mmiowb();
1399 }
1400
1401 static void rtl_irq_disable(struct rtl8169_private *tp)
1402 {
1403         RTL_W16(tp, IntrMask, 0);
1404         mmiowb();
1405 }
1406
1407 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1408 {
1409         RTL_W16(tp, IntrMask, bits);
1410 }
1411
1412 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1413 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1414 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1415
1416 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1417 {
1418         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1419 }
1420
1421 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1422 {
1423         rtl_irq_disable(tp);
1424         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1425         RTL_R8(tp, ChipCmd);
1426 }
1427
1428 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1429 {
1430         struct net_device *dev = tp->dev;
1431         struct phy_device *phydev = dev->phydev;
1432
1433         if (!netif_running(dev))
1434                 return;
1435
1436         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1437             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1438                 if (phydev->speed == SPEED_1000) {
1439                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1440                                       ERIAR_EXGMAC);
1441                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1442                                       ERIAR_EXGMAC);
1443                 } else if (phydev->speed == SPEED_100) {
1444                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1445                                       ERIAR_EXGMAC);
1446                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1447                                       ERIAR_EXGMAC);
1448                 } else {
1449                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1450                                       ERIAR_EXGMAC);
1451                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1452                                       ERIAR_EXGMAC);
1453                 }
1454                 /* Reset packet filter */
1455                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1456                              ERIAR_EXGMAC);
1457                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1458                              ERIAR_EXGMAC);
1459         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1460                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1461                 if (phydev->speed == SPEED_1000) {
1462                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1463                                       ERIAR_EXGMAC);
1464                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1465                                       ERIAR_EXGMAC);
1466                 } else {
1467                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1468                                       ERIAR_EXGMAC);
1469                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1470                                       ERIAR_EXGMAC);
1471                 }
1472         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1473                 if (phydev->speed == SPEED_10) {
1474                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1475                                       ERIAR_EXGMAC);
1476                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1477                                       ERIAR_EXGMAC);
1478                 } else {
1479                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1480                                       ERIAR_EXGMAC);
1481                 }
1482         }
1483 }
1484
1485 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1486
1487 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1488 {
1489         u8 options;
1490         u32 wolopts = 0;
1491
1492         options = RTL_R8(tp, Config1);
1493         if (!(options & PMEnable))
1494                 return 0;
1495
1496         options = RTL_R8(tp, Config3);
1497         if (options & LinkUp)
1498                 wolopts |= WAKE_PHY;
1499         switch (tp->mac_version) {
1500         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1501         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1502                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1503                         wolopts |= WAKE_MAGIC;
1504                 break;
1505         default:
1506                 if (options & MagicPacket)
1507                         wolopts |= WAKE_MAGIC;
1508                 break;
1509         }
1510
1511         options = RTL_R8(tp, Config5);
1512         if (options & UWF)
1513                 wolopts |= WAKE_UCAST;
1514         if (options & BWF)
1515                 wolopts |= WAKE_BCAST;
1516         if (options & MWF)
1517                 wolopts |= WAKE_MCAST;
1518
1519         return wolopts;
1520 }
1521
1522 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1523 {
1524         struct rtl8169_private *tp = netdev_priv(dev);
1525
1526         rtl_lock_work(tp);
1527         wol->supported = WAKE_ANY;
1528         wol->wolopts = tp->saved_wolopts;
1529         rtl_unlock_work(tp);
1530 }
1531
1532 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1533 {
1534         unsigned int i, tmp;
1535         static const struct {
1536                 u32 opt;
1537                 u16 reg;
1538                 u8  mask;
1539         } cfg[] = {
1540                 { WAKE_PHY,   Config3, LinkUp },
1541                 { WAKE_UCAST, Config5, UWF },
1542                 { WAKE_BCAST, Config5, BWF },
1543                 { WAKE_MCAST, Config5, MWF },
1544                 { WAKE_ANY,   Config5, LanWake },
1545                 { WAKE_MAGIC, Config3, MagicPacket }
1546         };
1547         u8 options;
1548
1549         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1550
1551         switch (tp->mac_version) {
1552         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1553         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1554                 tmp = ARRAY_SIZE(cfg) - 1;
1555                 if (wolopts & WAKE_MAGIC)
1556                         rtl_w0w1_eri(tp,
1557                                      0x0dc,
1558                                      ERIAR_MASK_0100,
1559                                      MagicPacket_v2,
1560                                      0x0000,
1561                                      ERIAR_EXGMAC);
1562                 else
1563                         rtl_w0w1_eri(tp,
1564                                      0x0dc,
1565                                      ERIAR_MASK_0100,
1566                                      0x0000,
1567                                      MagicPacket_v2,
1568                                      ERIAR_EXGMAC);
1569                 break;
1570         default:
1571                 tmp = ARRAY_SIZE(cfg);
1572                 break;
1573         }
1574
1575         for (i = 0; i < tmp; i++) {
1576                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1577                 if (wolopts & cfg[i].opt)
1578                         options |= cfg[i].mask;
1579                 RTL_W8(tp, cfg[i].reg, options);
1580         }
1581
1582         switch (tp->mac_version) {
1583         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1584                 options = RTL_R8(tp, Config1) & ~PMEnable;
1585                 if (wolopts)
1586                         options |= PMEnable;
1587                 RTL_W8(tp, Config1, options);
1588                 break;
1589         default:
1590                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1591                 if (wolopts)
1592                         options |= PME_SIGNAL;
1593                 RTL_W8(tp, Config2, options);
1594                 break;
1595         }
1596
1597         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1598 }
1599
1600 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1601 {
1602         struct rtl8169_private *tp = netdev_priv(dev);
1603         struct device *d = tp_to_dev(tp);
1604
1605         if (wol->wolopts & ~WAKE_ANY)
1606                 return -EINVAL;
1607
1608         pm_runtime_get_noresume(d);
1609
1610         rtl_lock_work(tp);
1611
1612         tp->saved_wolopts = wol->wolopts;
1613
1614         if (pm_runtime_active(d))
1615                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1616
1617         rtl_unlock_work(tp);
1618
1619         device_set_wakeup_enable(d, tp->saved_wolopts);
1620
1621         pm_runtime_put_noidle(d);
1622
1623         return 0;
1624 }
1625
1626 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1627 {
1628         return rtl_chip_infos[tp->mac_version].fw_name;
1629 }
1630
1631 static void rtl8169_get_drvinfo(struct net_device *dev,
1632                                 struct ethtool_drvinfo *info)
1633 {
1634         struct rtl8169_private *tp = netdev_priv(dev);
1635         struct rtl_fw *rtl_fw = tp->rtl_fw;
1636
1637         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1638         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1639         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1640         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1641         if (!IS_ERR_OR_NULL(rtl_fw))
1642                 strlcpy(info->fw_version, rtl_fw->version,
1643                         sizeof(info->fw_version));
1644 }
1645
1646 static int rtl8169_get_regs_len(struct net_device *dev)
1647 {
1648         return R8169_REGS_SIZE;
1649 }
1650
1651 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1652         netdev_features_t features)
1653 {
1654         struct rtl8169_private *tp = netdev_priv(dev);
1655
1656         if (dev->mtu > TD_MSS_MAX)
1657                 features &= ~NETIF_F_ALL_TSO;
1658
1659         if (dev->mtu > JUMBO_1K &&
1660             tp->mac_version > RTL_GIGA_MAC_VER_06)
1661                 features &= ~NETIF_F_IP_CSUM;
1662
1663         return features;
1664 }
1665
1666 static int rtl8169_set_features(struct net_device *dev,
1667                                 netdev_features_t features)
1668 {
1669         struct rtl8169_private *tp = netdev_priv(dev);
1670         u32 rx_config;
1671
1672         rtl_lock_work(tp);
1673
1674         rx_config = RTL_R32(tp, RxConfig);
1675         if (features & NETIF_F_RXALL)
1676                 rx_config |= (AcceptErr | AcceptRunt);
1677         else
1678                 rx_config &= ~(AcceptErr | AcceptRunt);
1679
1680         RTL_W32(tp, RxConfig, rx_config);
1681
1682         if (features & NETIF_F_RXCSUM)
1683                 tp->cp_cmd |= RxChkSum;
1684         else
1685                 tp->cp_cmd &= ~RxChkSum;
1686
1687         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1688                 tp->cp_cmd |= RxVlan;
1689         else
1690                 tp->cp_cmd &= ~RxVlan;
1691
1692         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1693         RTL_R16(tp, CPlusCmd);
1694
1695         rtl_unlock_work(tp);
1696
1697         return 0;
1698 }
1699
1700 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1701 {
1702         return (skb_vlan_tag_present(skb)) ?
1703                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1704 }
1705
1706 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1707 {
1708         u32 opts2 = le32_to_cpu(desc->opts2);
1709
1710         if (opts2 & RxVlanTag)
1711                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1712 }
1713
1714 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1715                              void *p)
1716 {
1717         struct rtl8169_private *tp = netdev_priv(dev);
1718         u32 __iomem *data = tp->mmio_addr;
1719         u32 *dw = p;
1720         int i;
1721
1722         rtl_lock_work(tp);
1723         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1724                 memcpy_fromio(dw++, data++, 4);
1725         rtl_unlock_work(tp);
1726 }
1727
1728 static u32 rtl8169_get_msglevel(struct net_device *dev)
1729 {
1730         struct rtl8169_private *tp = netdev_priv(dev);
1731
1732         return tp->msg_enable;
1733 }
1734
1735 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1736 {
1737         struct rtl8169_private *tp = netdev_priv(dev);
1738
1739         tp->msg_enable = value;
1740 }
1741
1742 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1743         "tx_packets",
1744         "rx_packets",
1745         "tx_errors",
1746         "rx_errors",
1747         "rx_missed",
1748         "align_errors",
1749         "tx_single_collisions",
1750         "tx_multi_collisions",
1751         "unicast",
1752         "broadcast",
1753         "multicast",
1754         "tx_aborted",
1755         "tx_underrun",
1756 };
1757
1758 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1759 {
1760         switch (sset) {
1761         case ETH_SS_STATS:
1762                 return ARRAY_SIZE(rtl8169_gstrings);
1763         default:
1764                 return -EOPNOTSUPP;
1765         }
1766 }
1767
1768 DECLARE_RTL_COND(rtl_counters_cond)
1769 {
1770         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1771 }
1772
1773 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1774 {
1775         dma_addr_t paddr = tp->counters_phys_addr;
1776         u32 cmd;
1777
1778         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1779         RTL_R32(tp, CounterAddrHigh);
1780         cmd = (u64)paddr & DMA_BIT_MASK(32);
1781         RTL_W32(tp, CounterAddrLow, cmd);
1782         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1783
1784         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1785 }
1786
1787 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1788 {
1789         /*
1790          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1791          * tally counters.
1792          */
1793         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1794                 return true;
1795
1796         return rtl8169_do_counters(tp, CounterReset);
1797 }
1798
1799 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1800 {
1801         /*
1802          * Some chips are unable to dump tally counters when the receiver
1803          * is disabled.
1804          */
1805         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1806                 return true;
1807
1808         return rtl8169_do_counters(tp, CounterDump);
1809 }
1810
1811 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1812 {
1813         struct rtl8169_counters *counters = tp->counters;
1814         bool ret = false;
1815
1816         /*
1817          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1818          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1819          * reset by a power cycle, while the counter values collected by the
1820          * driver are reset at every driver unload/load cycle.
1821          *
1822          * To make sure the HW values returned by @get_stats64 match the SW
1823          * values, we collect the initial values at first open(*) and use them
1824          * as offsets to normalize the values returned by @get_stats64.
1825          *
1826          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1827          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1828          * set at open time by rtl_hw_start.
1829          */
1830
1831         if (tp->tc_offset.inited)
1832                 return true;
1833
1834         /* If both, reset and update fail, propagate to caller. */
1835         if (rtl8169_reset_counters(tp))
1836                 ret = true;
1837
1838         if (rtl8169_update_counters(tp))
1839                 ret = true;
1840
1841         tp->tc_offset.tx_errors = counters->tx_errors;
1842         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1843         tp->tc_offset.tx_aborted = counters->tx_aborted;
1844         tp->tc_offset.inited = true;
1845
1846         return ret;
1847 }
1848
1849 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1850                                       struct ethtool_stats *stats, u64 *data)
1851 {
1852         struct rtl8169_private *tp = netdev_priv(dev);
1853         struct device *d = tp_to_dev(tp);
1854         struct rtl8169_counters *counters = tp->counters;
1855
1856         ASSERT_RTNL();
1857
1858         pm_runtime_get_noresume(d);
1859
1860         if (pm_runtime_active(d))
1861                 rtl8169_update_counters(tp);
1862
1863         pm_runtime_put_noidle(d);
1864
1865         data[0] = le64_to_cpu(counters->tx_packets);
1866         data[1] = le64_to_cpu(counters->rx_packets);
1867         data[2] = le64_to_cpu(counters->tx_errors);
1868         data[3] = le32_to_cpu(counters->rx_errors);
1869         data[4] = le16_to_cpu(counters->rx_missed);
1870         data[5] = le16_to_cpu(counters->align_errors);
1871         data[6] = le32_to_cpu(counters->tx_one_collision);
1872         data[7] = le32_to_cpu(counters->tx_multi_collision);
1873         data[8] = le64_to_cpu(counters->rx_unicast);
1874         data[9] = le64_to_cpu(counters->rx_broadcast);
1875         data[10] = le32_to_cpu(counters->rx_multicast);
1876         data[11] = le16_to_cpu(counters->tx_aborted);
1877         data[12] = le16_to_cpu(counters->tx_underun);
1878 }
1879
1880 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1881 {
1882         switch(stringset) {
1883         case ETH_SS_STATS:
1884                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1885                 break;
1886         }
1887 }
1888
1889 /*
1890  * Interrupt coalescing
1891  *
1892  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1893  * >     8169, 8168 and 810x line of chipsets
1894  *
1895  * 8169, 8168, and 8136(810x) serial chipsets support it.
1896  *
1897  * > 2 - the Tx timer unit at gigabit speed
1898  *
1899  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1900  * (0xe0) bit 1 and bit 0.
1901  *
1902  * For 8169
1903  * bit[1:0] \ speed        1000M           100M            10M
1904  * 0 0                     320ns           2.56us          40.96us
1905  * 0 1                     2.56us          20.48us         327.7us
1906  * 1 0                     5.12us          40.96us         655.4us
1907  * 1 1                     10.24us         81.92us         1.31ms
1908  *
1909  * For the other
1910  * bit[1:0] \ speed        1000M           100M            10M
1911  * 0 0                     5us             2.56us          40.96us
1912  * 0 1                     40us            20.48us         327.7us
1913  * 1 0                     80us            40.96us         655.4us
1914  * 1 1                     160us           81.92us         1.31ms
1915  */
1916
1917 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1918 struct rtl_coalesce_scale {
1919         /* Rx / Tx */
1920         u32 nsecs[2];
1921 };
1922
1923 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1924 struct rtl_coalesce_info {
1925         u32 speed;
1926         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1927 };
1928
1929 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1930 #define rxtx_x1822(r, t) {              \
1931         {{(r),          (t)}},          \
1932         {{(r)*8,        (t)*8}},        \
1933         {{(r)*8*2,      (t)*8*2}},      \
1934         {{(r)*8*2*2,    (t)*8*2*2}},    \
1935 }
1936 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1937         /* speed        delays:     rx00   tx00 */
1938         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1939         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1940         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1941         { 0 },
1942 };
1943
1944 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1945         /* speed        delays:     rx00   tx00 */
1946         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1947         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1948         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1949         { 0 },
1950 };
1951 #undef rxtx_x1822
1952
1953 /* get rx/tx scale vector corresponding to current speed */
1954 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1955 {
1956         struct rtl8169_private *tp = netdev_priv(dev);
1957         struct ethtool_link_ksettings ecmd;
1958         const struct rtl_coalesce_info *ci;
1959         int rc;
1960
1961         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1962         if (rc < 0)
1963                 return ERR_PTR(rc);
1964
1965         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1966                 if (ecmd.base.speed == ci->speed) {
1967                         return ci;
1968                 }
1969         }
1970
1971         return ERR_PTR(-ELNRNG);
1972 }
1973
1974 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1975 {
1976         struct rtl8169_private *tp = netdev_priv(dev);
1977         const struct rtl_coalesce_info *ci;
1978         const struct rtl_coalesce_scale *scale;
1979         struct {
1980                 u32 *max_frames;
1981                 u32 *usecs;
1982         } coal_settings [] = {
1983                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1984                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1985         }, *p = coal_settings;
1986         int i;
1987         u16 w;
1988
1989         memset(ec, 0, sizeof(*ec));
1990
1991         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1992         ci = rtl_coalesce_info(dev);
1993         if (IS_ERR(ci))
1994                 return PTR_ERR(ci);
1995
1996         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1997
1998         /* read IntrMitigate and adjust according to scale */
1999         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2000                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2001                 w >>= RTL_COALESCE_SHIFT;
2002                 *p->usecs = w & RTL_COALESCE_MASK;
2003         }
2004
2005         for (i = 0; i < 2; i++) {
2006                 p = coal_settings + i;
2007                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2008
2009                 /*
2010                  * ethtool_coalesce says it is illegal to set both usecs and
2011                  * max_frames to 0.
2012                  */
2013                 if (!*p->usecs && !*p->max_frames)
2014                         *p->max_frames = 1;
2015         }
2016
2017         return 0;
2018 }
2019
2020 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2021 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2022                         struct net_device *dev, u32 nsec, u16 *cp01)
2023 {
2024         const struct rtl_coalesce_info *ci;
2025         u16 i;
2026
2027         ci = rtl_coalesce_info(dev);
2028         if (IS_ERR(ci))
2029                 return ERR_CAST(ci);
2030
2031         for (i = 0; i < 4; i++) {
2032                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2033                                         ci->scalev[i].nsecs[1]);
2034                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2035                         *cp01 = i;
2036                         return &ci->scalev[i];
2037                 }
2038         }
2039
2040         return ERR_PTR(-EINVAL);
2041 }
2042
2043 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2044 {
2045         struct rtl8169_private *tp = netdev_priv(dev);
2046         const struct rtl_coalesce_scale *scale;
2047         struct {
2048                 u32 frames;
2049                 u32 usecs;
2050         } coal_settings [] = {
2051                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2052                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2053         }, *p = coal_settings;
2054         u16 w = 0, cp01;
2055         int i;
2056
2057         scale = rtl_coalesce_choose_scale(dev,
2058                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2059         if (IS_ERR(scale))
2060                 return PTR_ERR(scale);
2061
2062         for (i = 0; i < 2; i++, p++) {
2063                 u32 units;
2064
2065                 /*
2066                  * accept max_frames=1 we returned in rtl_get_coalesce.
2067                  * accept it not only when usecs=0 because of e.g. the following scenario:
2068                  *
2069                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2070                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2071                  * - then user does `ethtool -C eth0 rx-usecs 100`
2072                  *
2073                  * since ethtool sends to kernel whole ethtool_coalesce
2074                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2075                  * we'll reject it below in `frames % 4 != 0`.
2076                  */
2077                 if (p->frames == 1) {
2078                         p->frames = 0;
2079                 }
2080
2081                 units = p->usecs * 1000 / scale->nsecs[i];
2082                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2083                         return -EINVAL;
2084
2085                 w <<= RTL_COALESCE_SHIFT;
2086                 w |= units;
2087                 w <<= RTL_COALESCE_SHIFT;
2088                 w |= p->frames >> 2;
2089         }
2090
2091         rtl_lock_work(tp);
2092
2093         RTL_W16(tp, IntrMitigate, swab16(w));
2094
2095         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2096         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2097         RTL_R16(tp, CPlusCmd);
2098
2099         rtl_unlock_work(tp);
2100
2101         return 0;
2102 }
2103
2104 static const struct ethtool_ops rtl8169_ethtool_ops = {
2105         .get_drvinfo            = rtl8169_get_drvinfo,
2106         .get_regs_len           = rtl8169_get_regs_len,
2107         .get_link               = ethtool_op_get_link,
2108         .get_coalesce           = rtl_get_coalesce,
2109         .set_coalesce           = rtl_set_coalesce,
2110         .get_msglevel           = rtl8169_get_msglevel,
2111         .set_msglevel           = rtl8169_set_msglevel,
2112         .get_regs               = rtl8169_get_regs,
2113         .get_wol                = rtl8169_get_wol,
2114         .set_wol                = rtl8169_set_wol,
2115         .get_strings            = rtl8169_get_strings,
2116         .get_sset_count         = rtl8169_get_sset_count,
2117         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2118         .get_ts_info            = ethtool_op_get_ts_info,
2119         .nway_reset             = phy_ethtool_nway_reset,
2120         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2121         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2122 };
2123
2124 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2125                                     u8 default_version)
2126 {
2127         /*
2128          * The driver currently handles the 8168Bf and the 8168Be identically
2129          * but they can be identified more specifically through the test below
2130          * if needed:
2131          *
2132          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2133          *
2134          * Same thing for the 8101Eb and the 8101Ec:
2135          *
2136          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2137          */
2138         static const struct rtl_mac_info {
2139                 u32 mask;
2140                 u32 val;
2141                 int mac_version;
2142         } mac_info[] = {
2143                 /* 8168EP family. */
2144                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2145                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2146                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2147
2148                 /* 8168H family. */
2149                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2150                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2151
2152                 /* 8168G family. */
2153                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2154                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2155                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2156                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2157
2158                 /* 8168F family. */
2159                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2160                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2161                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2162
2163                 /* 8168E family. */
2164                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2165                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2166                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2167
2168                 /* 8168D family. */
2169                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2170                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2171
2172                 /* 8168DP family. */
2173                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2174                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2175                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2176
2177                 /* 8168C family. */
2178                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2179                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2180                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2181                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2182                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2183                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2184                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2185
2186                 /* 8168B family. */
2187                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2188                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2189                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2190
2191                 /* 8101 family. */
2192                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2193                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2194                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2195                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2196                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2197                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2198                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2199                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2200                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2201                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2202                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2203                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2204                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2205                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2206                 /* FIXME: where did these entries come from ? -- FR */
2207                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2208                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2209
2210                 /* 8110 family. */
2211                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2212                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2213                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2214                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2215                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2216                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2217
2218                 /* Catch-all */
2219                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2220         };
2221         const struct rtl_mac_info *p = mac_info;
2222         u32 reg;
2223
2224         reg = RTL_R32(tp, TxConfig);
2225         while ((reg & p->mask) != p->val)
2226                 p++;
2227         tp->mac_version = p->mac_version;
2228
2229         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2230                 dev_notice(tp_to_dev(tp),
2231                            "unknown MAC, using family default\n");
2232                 tp->mac_version = default_version;
2233         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2234                 tp->mac_version = tp->supports_gmii ?
2235                                   RTL_GIGA_MAC_VER_42 :
2236                                   RTL_GIGA_MAC_VER_43;
2237         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2238                 tp->mac_version = tp->supports_gmii ?
2239                                   RTL_GIGA_MAC_VER_45 :
2240                                   RTL_GIGA_MAC_VER_47;
2241         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2242                 tp->mac_version = tp->supports_gmii ?
2243                                   RTL_GIGA_MAC_VER_46 :
2244                                   RTL_GIGA_MAC_VER_48;
2245         }
2246 }
2247
2248 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2249 {
2250         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2251 }
2252
2253 struct phy_reg {
2254         u16 reg;
2255         u16 val;
2256 };
2257
2258 static void rtl_writephy_batch(struct rtl8169_private *tp,
2259                                const struct phy_reg *regs, int len)
2260 {
2261         while (len-- > 0) {
2262                 rtl_writephy(tp, regs->reg, regs->val);
2263                 regs++;
2264         }
2265 }
2266
2267 #define PHY_READ                0x00000000
2268 #define PHY_DATA_OR             0x10000000
2269 #define PHY_DATA_AND            0x20000000
2270 #define PHY_BJMPN               0x30000000
2271 #define PHY_MDIO_CHG            0x40000000
2272 #define PHY_CLEAR_READCOUNT     0x70000000
2273 #define PHY_WRITE               0x80000000
2274 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2275 #define PHY_COMP_EQ_SKIPN       0xa0000000
2276 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2277 #define PHY_WRITE_PREVIOUS      0xc0000000
2278 #define PHY_SKIPN               0xd0000000
2279 #define PHY_DELAY_MS            0xe0000000
2280
2281 struct fw_info {
2282         u32     magic;
2283         char    version[RTL_VER_SIZE];
2284         __le32  fw_start;
2285         __le32  fw_len;
2286         u8      chksum;
2287 } __packed;
2288
2289 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2290
2291 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2292 {
2293         const struct firmware *fw = rtl_fw->fw;
2294         struct fw_info *fw_info = (struct fw_info *)fw->data;
2295         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2296         char *version = rtl_fw->version;
2297         bool rc = false;
2298
2299         if (fw->size < FW_OPCODE_SIZE)
2300                 goto out;
2301
2302         if (!fw_info->magic) {
2303                 size_t i, size, start;
2304                 u8 checksum = 0;
2305
2306                 if (fw->size < sizeof(*fw_info))
2307                         goto out;
2308
2309                 for (i = 0; i < fw->size; i++)
2310                         checksum += fw->data[i];
2311                 if (checksum != 0)
2312                         goto out;
2313
2314                 start = le32_to_cpu(fw_info->fw_start);
2315                 if (start > fw->size)
2316                         goto out;
2317
2318                 size = le32_to_cpu(fw_info->fw_len);
2319                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2320                         goto out;
2321
2322                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2323
2324                 pa->code = (__le32 *)(fw->data + start);
2325                 pa->size = size;
2326         } else {
2327                 if (fw->size % FW_OPCODE_SIZE)
2328                         goto out;
2329
2330                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2331
2332                 pa->code = (__le32 *)fw->data;
2333                 pa->size = fw->size / FW_OPCODE_SIZE;
2334         }
2335         version[RTL_VER_SIZE - 1] = 0;
2336
2337         rc = true;
2338 out:
2339         return rc;
2340 }
2341
2342 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2343                            struct rtl_fw_phy_action *pa)
2344 {
2345         bool rc = false;
2346         size_t index;
2347
2348         for (index = 0; index < pa->size; index++) {
2349                 u32 action = le32_to_cpu(pa->code[index]);
2350                 u32 regno = (action & 0x0fff0000) >> 16;
2351
2352                 switch(action & 0xf0000000) {
2353                 case PHY_READ:
2354                 case PHY_DATA_OR:
2355                 case PHY_DATA_AND:
2356                 case PHY_MDIO_CHG:
2357                 case PHY_CLEAR_READCOUNT:
2358                 case PHY_WRITE:
2359                 case PHY_WRITE_PREVIOUS:
2360                 case PHY_DELAY_MS:
2361                         break;
2362
2363                 case PHY_BJMPN:
2364                         if (regno > index) {
2365                                 netif_err(tp, ifup, tp->dev,
2366                                           "Out of range of firmware\n");
2367                                 goto out;
2368                         }
2369                         break;
2370                 case PHY_READCOUNT_EQ_SKIP:
2371                         if (index + 2 >= pa->size) {
2372                                 netif_err(tp, ifup, tp->dev,
2373                                           "Out of range of firmware\n");
2374                                 goto out;
2375                         }
2376                         break;
2377                 case PHY_COMP_EQ_SKIPN:
2378                 case PHY_COMP_NEQ_SKIPN:
2379                 case PHY_SKIPN:
2380                         if (index + 1 + regno >= pa->size) {
2381                                 netif_err(tp, ifup, tp->dev,
2382                                           "Out of range of firmware\n");
2383                                 goto out;
2384                         }
2385                         break;
2386
2387                 default:
2388                         netif_err(tp, ifup, tp->dev,
2389                                   "Invalid action 0x%08x\n", action);
2390                         goto out;
2391                 }
2392         }
2393         rc = true;
2394 out:
2395         return rc;
2396 }
2397
2398 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2399 {
2400         struct net_device *dev = tp->dev;
2401         int rc = -EINVAL;
2402
2403         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2404                 netif_err(tp, ifup, dev, "invalid firmware\n");
2405                 goto out;
2406         }
2407
2408         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2409                 rc = 0;
2410 out:
2411         return rc;
2412 }
2413
2414 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2415 {
2416         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2417         struct mdio_ops org, *ops = &tp->mdio_ops;
2418         u32 predata, count;
2419         size_t index;
2420
2421         predata = count = 0;
2422         org.write = ops->write;
2423         org.read = ops->read;
2424
2425         for (index = 0; index < pa->size; ) {
2426                 u32 action = le32_to_cpu(pa->code[index]);
2427                 u32 data = action & 0x0000ffff;
2428                 u32 regno = (action & 0x0fff0000) >> 16;
2429
2430                 if (!action)
2431                         break;
2432
2433                 switch(action & 0xf0000000) {
2434                 case PHY_READ:
2435                         predata = rtl_readphy(tp, regno);
2436                         count++;
2437                         index++;
2438                         break;
2439                 case PHY_DATA_OR:
2440                         predata |= data;
2441                         index++;
2442                         break;
2443                 case PHY_DATA_AND:
2444                         predata &= data;
2445                         index++;
2446                         break;
2447                 case PHY_BJMPN:
2448                         index -= regno;
2449                         break;
2450                 case PHY_MDIO_CHG:
2451                         if (data == 0) {
2452                                 ops->write = org.write;
2453                                 ops->read = org.read;
2454                         } else if (data == 1) {
2455                                 ops->write = mac_mcu_write;
2456                                 ops->read = mac_mcu_read;
2457                         }
2458
2459                         index++;
2460                         break;
2461                 case PHY_CLEAR_READCOUNT:
2462                         count = 0;
2463                         index++;
2464                         break;
2465                 case PHY_WRITE:
2466                         rtl_writephy(tp, regno, data);
2467                         index++;
2468                         break;
2469                 case PHY_READCOUNT_EQ_SKIP:
2470                         index += (count == data) ? 2 : 1;
2471                         break;
2472                 case PHY_COMP_EQ_SKIPN:
2473                         if (predata == data)
2474                                 index += regno;
2475                         index++;
2476                         break;
2477                 case PHY_COMP_NEQ_SKIPN:
2478                         if (predata != data)
2479                                 index += regno;
2480                         index++;
2481                         break;
2482                 case PHY_WRITE_PREVIOUS:
2483                         rtl_writephy(tp, regno, predata);
2484                         index++;
2485                         break;
2486                 case PHY_SKIPN:
2487                         index += regno + 1;
2488                         break;
2489                 case PHY_DELAY_MS:
2490                         mdelay(data);
2491                         index++;
2492                         break;
2493
2494                 default:
2495                         BUG();
2496                 }
2497         }
2498
2499         ops->write = org.write;
2500         ops->read = org.read;
2501 }
2502
2503 static void rtl_release_firmware(struct rtl8169_private *tp)
2504 {
2505         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2506                 release_firmware(tp->rtl_fw->fw);
2507                 kfree(tp->rtl_fw);
2508         }
2509         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2510 }
2511
2512 static void rtl_apply_firmware(struct rtl8169_private *tp)
2513 {
2514         struct rtl_fw *rtl_fw = tp->rtl_fw;
2515
2516         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2517         if (!IS_ERR_OR_NULL(rtl_fw))
2518                 rtl_phy_write_fw(tp, rtl_fw);
2519 }
2520
2521 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2522 {
2523         if (rtl_readphy(tp, reg) != val)
2524                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2525         else
2526                 rtl_apply_firmware(tp);
2527 }
2528
2529 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2530 {
2531         static const struct phy_reg phy_reg_init[] = {
2532                 { 0x1f, 0x0001 },
2533                 { 0x06, 0x006e },
2534                 { 0x08, 0x0708 },
2535                 { 0x15, 0x4000 },
2536                 { 0x18, 0x65c7 },
2537
2538                 { 0x1f, 0x0001 },
2539                 { 0x03, 0x00a1 },
2540                 { 0x02, 0x0008 },
2541                 { 0x01, 0x0120 },
2542                 { 0x00, 0x1000 },
2543                 { 0x04, 0x0800 },
2544                 { 0x04, 0x0000 },
2545
2546                 { 0x03, 0xff41 },
2547                 { 0x02, 0xdf60 },
2548                 { 0x01, 0x0140 },
2549                 { 0x00, 0x0077 },
2550                 { 0x04, 0x7800 },
2551                 { 0x04, 0x7000 },
2552
2553                 { 0x03, 0x802f },
2554                 { 0x02, 0x4f02 },
2555                 { 0x01, 0x0409 },
2556                 { 0x00, 0xf0f9 },
2557                 { 0x04, 0x9800 },
2558                 { 0x04, 0x9000 },
2559
2560                 { 0x03, 0xdf01 },
2561                 { 0x02, 0xdf20 },
2562                 { 0x01, 0xff95 },
2563                 { 0x00, 0xba00 },
2564                 { 0x04, 0xa800 },
2565                 { 0x04, 0xa000 },
2566
2567                 { 0x03, 0xff41 },
2568                 { 0x02, 0xdf20 },
2569                 { 0x01, 0x0140 },
2570                 { 0x00, 0x00bb },
2571                 { 0x04, 0xb800 },
2572                 { 0x04, 0xb000 },
2573
2574                 { 0x03, 0xdf41 },
2575                 { 0x02, 0xdc60 },
2576                 { 0x01, 0x6340 },
2577                 { 0x00, 0x007d },
2578                 { 0x04, 0xd800 },
2579                 { 0x04, 0xd000 },
2580
2581                 { 0x03, 0xdf01 },
2582                 { 0x02, 0xdf20 },
2583                 { 0x01, 0x100a },
2584                 { 0x00, 0xa0ff },
2585                 { 0x04, 0xf800 },
2586                 { 0x04, 0xf000 },
2587
2588                 { 0x1f, 0x0000 },
2589                 { 0x0b, 0x0000 },
2590                 { 0x00, 0x9200 }
2591         };
2592
2593         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2594 }
2595
2596 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2597 {
2598         static const struct phy_reg phy_reg_init[] = {
2599                 { 0x1f, 0x0002 },
2600                 { 0x01, 0x90d0 },
2601                 { 0x1f, 0x0000 }
2602         };
2603
2604         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2605 }
2606
2607 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2608 {
2609         struct pci_dev *pdev = tp->pci_dev;
2610
2611         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2612             (pdev->subsystem_device != 0xe000))
2613                 return;
2614
2615         rtl_writephy(tp, 0x1f, 0x0001);
2616         rtl_writephy(tp, 0x10, 0xf01b);
2617         rtl_writephy(tp, 0x1f, 0x0000);
2618 }
2619
2620 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2621 {
2622         static const struct phy_reg phy_reg_init[] = {
2623                 { 0x1f, 0x0001 },
2624                 { 0x04, 0x0000 },
2625                 { 0x03, 0x00a1 },
2626                 { 0x02, 0x0008 },
2627                 { 0x01, 0x0120 },
2628                 { 0x00, 0x1000 },
2629                 { 0x04, 0x0800 },
2630                 { 0x04, 0x9000 },
2631                 { 0x03, 0x802f },
2632                 { 0x02, 0x4f02 },
2633                 { 0x01, 0x0409 },
2634                 { 0x00, 0xf099 },
2635                 { 0x04, 0x9800 },
2636                 { 0x04, 0xa000 },
2637                 { 0x03, 0xdf01 },
2638                 { 0x02, 0xdf20 },
2639                 { 0x01, 0xff95 },
2640                 { 0x00, 0xba00 },
2641                 { 0x04, 0xa800 },
2642                 { 0x04, 0xf000 },
2643                 { 0x03, 0xdf01 },
2644                 { 0x02, 0xdf20 },
2645                 { 0x01, 0x101a },
2646                 { 0x00, 0xa0ff },
2647                 { 0x04, 0xf800 },
2648                 { 0x04, 0x0000 },
2649                 { 0x1f, 0x0000 },
2650
2651                 { 0x1f, 0x0001 },
2652                 { 0x10, 0xf41b },
2653                 { 0x14, 0xfb54 },
2654                 { 0x18, 0xf5c7 },
2655                 { 0x1f, 0x0000 },
2656
2657                 { 0x1f, 0x0001 },
2658                 { 0x17, 0x0cc0 },
2659                 { 0x1f, 0x0000 }
2660         };
2661
2662         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2663
2664         rtl8169scd_hw_phy_config_quirk(tp);
2665 }
2666
2667 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2668 {
2669         static const struct phy_reg phy_reg_init[] = {
2670                 { 0x1f, 0x0001 },
2671                 { 0x04, 0x0000 },
2672                 { 0x03, 0x00a1 },
2673                 { 0x02, 0x0008 },
2674                 { 0x01, 0x0120 },
2675                 { 0x00, 0x1000 },
2676                 { 0x04, 0x0800 },
2677                 { 0x04, 0x9000 },
2678                 { 0x03, 0x802f },
2679                 { 0x02, 0x4f02 },
2680                 { 0x01, 0x0409 },
2681                 { 0x00, 0xf099 },
2682                 { 0x04, 0x9800 },
2683                 { 0x04, 0xa000 },
2684                 { 0x03, 0xdf01 },
2685                 { 0x02, 0xdf20 },
2686                 { 0x01, 0xff95 },
2687                 { 0x00, 0xba00 },
2688                 { 0x04, 0xa800 },
2689                 { 0x04, 0xf000 },
2690                 { 0x03, 0xdf01 },
2691                 { 0x02, 0xdf20 },
2692                 { 0x01, 0x101a },
2693                 { 0x00, 0xa0ff },
2694                 { 0x04, 0xf800 },
2695                 { 0x04, 0x0000 },
2696                 { 0x1f, 0x0000 },
2697
2698                 { 0x1f, 0x0001 },
2699                 { 0x0b, 0x8480 },
2700                 { 0x1f, 0x0000 },
2701
2702                 { 0x1f, 0x0001 },
2703                 { 0x18, 0x67c7 },
2704                 { 0x04, 0x2000 },
2705                 { 0x03, 0x002f },
2706                 { 0x02, 0x4360 },
2707                 { 0x01, 0x0109 },
2708                 { 0x00, 0x3022 },
2709                 { 0x04, 0x2800 },
2710                 { 0x1f, 0x0000 },
2711
2712                 { 0x1f, 0x0001 },
2713                 { 0x17, 0x0cc0 },
2714                 { 0x1f, 0x0000 }
2715         };
2716
2717         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2718 }
2719
2720 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2721 {
2722         static const struct phy_reg phy_reg_init[] = {
2723                 { 0x10, 0xf41b },
2724                 { 0x1f, 0x0000 }
2725         };
2726
2727         rtl_writephy(tp, 0x1f, 0x0001);
2728         rtl_patchphy(tp, 0x16, 1 << 0);
2729
2730         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2731 }
2732
2733 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2734 {
2735         static const struct phy_reg phy_reg_init[] = {
2736                 { 0x1f, 0x0001 },
2737                 { 0x10, 0xf41b },
2738                 { 0x1f, 0x0000 }
2739         };
2740
2741         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2742 }
2743
2744 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2745 {
2746         static const struct phy_reg phy_reg_init[] = {
2747                 { 0x1f, 0x0000 },
2748                 { 0x1d, 0x0f00 },
2749                 { 0x1f, 0x0002 },
2750                 { 0x0c, 0x1ec8 },
2751                 { 0x1f, 0x0000 }
2752         };
2753
2754         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2755 }
2756
2757 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2758 {
2759         static const struct phy_reg phy_reg_init[] = {
2760                 { 0x1f, 0x0001 },
2761                 { 0x1d, 0x3d98 },
2762                 { 0x1f, 0x0000 }
2763         };
2764
2765         rtl_writephy(tp, 0x1f, 0x0000);
2766         rtl_patchphy(tp, 0x14, 1 << 5);
2767         rtl_patchphy(tp, 0x0d, 1 << 5);
2768
2769         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2770 }
2771
2772 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2773 {
2774         static const struct phy_reg phy_reg_init[] = {
2775                 { 0x1f, 0x0001 },
2776                 { 0x12, 0x2300 },
2777                 { 0x1f, 0x0002 },
2778                 { 0x00, 0x88d4 },
2779                 { 0x01, 0x82b1 },
2780                 { 0x03, 0x7002 },
2781                 { 0x08, 0x9e30 },
2782                 { 0x09, 0x01f0 },
2783                 { 0x0a, 0x5500 },
2784                 { 0x0c, 0x00c8 },
2785                 { 0x1f, 0x0003 },
2786                 { 0x12, 0xc096 },
2787                 { 0x16, 0x000a },
2788                 { 0x1f, 0x0000 },
2789                 { 0x1f, 0x0000 },
2790                 { 0x09, 0x2000 },
2791                 { 0x09, 0x0000 }
2792         };
2793
2794         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2795
2796         rtl_patchphy(tp, 0x14, 1 << 5);
2797         rtl_patchphy(tp, 0x0d, 1 << 5);
2798         rtl_writephy(tp, 0x1f, 0x0000);
2799 }
2800
2801 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2802 {
2803         static const struct phy_reg phy_reg_init[] = {
2804                 { 0x1f, 0x0001 },
2805                 { 0x12, 0x2300 },
2806                 { 0x03, 0x802f },
2807                 { 0x02, 0x4f02 },
2808                 { 0x01, 0x0409 },
2809                 { 0x00, 0xf099 },
2810                 { 0x04, 0x9800 },
2811                 { 0x04, 0x9000 },
2812                 { 0x1d, 0x3d98 },
2813                 { 0x1f, 0x0002 },
2814                 { 0x0c, 0x7eb8 },
2815                 { 0x06, 0x0761 },
2816                 { 0x1f, 0x0003 },
2817                 { 0x16, 0x0f0a },
2818                 { 0x1f, 0x0000 }
2819         };
2820
2821         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2822
2823         rtl_patchphy(tp, 0x16, 1 << 0);
2824         rtl_patchphy(tp, 0x14, 1 << 5);
2825         rtl_patchphy(tp, 0x0d, 1 << 5);
2826         rtl_writephy(tp, 0x1f, 0x0000);
2827 }
2828
2829 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2830 {
2831         static const struct phy_reg phy_reg_init[] = {
2832                 { 0x1f, 0x0001 },
2833                 { 0x12, 0x2300 },
2834                 { 0x1d, 0x3d98 },
2835                 { 0x1f, 0x0002 },
2836                 { 0x0c, 0x7eb8 },
2837                 { 0x06, 0x5461 },
2838                 { 0x1f, 0x0003 },
2839                 { 0x16, 0x0f0a },
2840                 { 0x1f, 0x0000 }
2841         };
2842
2843         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2844
2845         rtl_patchphy(tp, 0x16, 1 << 0);
2846         rtl_patchphy(tp, 0x14, 1 << 5);
2847         rtl_patchphy(tp, 0x0d, 1 << 5);
2848         rtl_writephy(tp, 0x1f, 0x0000);
2849 }
2850
2851 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2852 {
2853         rtl8168c_3_hw_phy_config(tp);
2854 }
2855
2856 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2857 {
2858         static const struct phy_reg phy_reg_init_0[] = {
2859                 /* Channel Estimation */
2860                 { 0x1f, 0x0001 },
2861                 { 0x06, 0x4064 },
2862                 { 0x07, 0x2863 },
2863                 { 0x08, 0x059c },
2864                 { 0x09, 0x26b4 },
2865                 { 0x0a, 0x6a19 },
2866                 { 0x0b, 0xdcc8 },
2867                 { 0x10, 0xf06d },
2868                 { 0x14, 0x7f68 },
2869                 { 0x18, 0x7fd9 },
2870                 { 0x1c, 0xf0ff },
2871                 { 0x1d, 0x3d9c },
2872                 { 0x1f, 0x0003 },
2873                 { 0x12, 0xf49f },
2874                 { 0x13, 0x070b },
2875                 { 0x1a, 0x05ad },
2876                 { 0x14, 0x94c0 },
2877
2878                 /*
2879                  * Tx Error Issue
2880                  * Enhance line driver power
2881                  */
2882                 { 0x1f, 0x0002 },
2883                 { 0x06, 0x5561 },
2884                 { 0x1f, 0x0005 },
2885                 { 0x05, 0x8332 },
2886                 { 0x06, 0x5561 },
2887
2888                 /*
2889                  * Can not link to 1Gbps with bad cable
2890                  * Decrease SNR threshold form 21.07dB to 19.04dB
2891                  */
2892                 { 0x1f, 0x0001 },
2893                 { 0x17, 0x0cc0 },
2894
2895                 { 0x1f, 0x0000 },
2896                 { 0x0d, 0xf880 }
2897         };
2898
2899         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2900
2901         /*
2902          * Rx Error Issue
2903          * Fine Tune Switching regulator parameter
2904          */
2905         rtl_writephy(tp, 0x1f, 0x0002);
2906         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2907         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2908
2909         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2910                 static const struct phy_reg phy_reg_init[] = {
2911                         { 0x1f, 0x0002 },
2912                         { 0x05, 0x669a },
2913                         { 0x1f, 0x0005 },
2914                         { 0x05, 0x8330 },
2915                         { 0x06, 0x669a },
2916                         { 0x1f, 0x0002 }
2917                 };
2918                 int val;
2919
2920                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2921
2922                 val = rtl_readphy(tp, 0x0d);
2923
2924                 if ((val & 0x00ff) != 0x006c) {
2925                         static const u32 set[] = {
2926                                 0x0065, 0x0066, 0x0067, 0x0068,
2927                                 0x0069, 0x006a, 0x006b, 0x006c
2928                         };
2929                         int i;
2930
2931                         rtl_writephy(tp, 0x1f, 0x0002);
2932
2933                         val &= 0xff00;
2934                         for (i = 0; i < ARRAY_SIZE(set); i++)
2935                                 rtl_writephy(tp, 0x0d, val | set[i]);
2936                 }
2937         } else {
2938                 static const struct phy_reg phy_reg_init[] = {
2939                         { 0x1f, 0x0002 },
2940                         { 0x05, 0x6662 },
2941                         { 0x1f, 0x0005 },
2942                         { 0x05, 0x8330 },
2943                         { 0x06, 0x6662 }
2944                 };
2945
2946                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2947         }
2948
2949         /* RSET couple improve */
2950         rtl_writephy(tp, 0x1f, 0x0002);
2951         rtl_patchphy(tp, 0x0d, 0x0300);
2952         rtl_patchphy(tp, 0x0f, 0x0010);
2953
2954         /* Fine tune PLL performance */
2955         rtl_writephy(tp, 0x1f, 0x0002);
2956         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2957         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2958
2959         rtl_writephy(tp, 0x1f, 0x0005);
2960         rtl_writephy(tp, 0x05, 0x001b);
2961
2962         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2963
2964         rtl_writephy(tp, 0x1f, 0x0000);
2965 }
2966
2967 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2968 {
2969         static const struct phy_reg phy_reg_init_0[] = {
2970                 /* Channel Estimation */
2971                 { 0x1f, 0x0001 },
2972                 { 0x06, 0x4064 },
2973                 { 0x07, 0x2863 },
2974                 { 0x08, 0x059c },
2975                 { 0x09, 0x26b4 },
2976                 { 0x0a, 0x6a19 },
2977                 { 0x0b, 0xdcc8 },
2978                 { 0x10, 0xf06d },
2979                 { 0x14, 0x7f68 },
2980                 { 0x18, 0x7fd9 },
2981                 { 0x1c, 0xf0ff },
2982                 { 0x1d, 0x3d9c },
2983                 { 0x1f, 0x0003 },
2984                 { 0x12, 0xf49f },
2985                 { 0x13, 0x070b },
2986                 { 0x1a, 0x05ad },
2987                 { 0x14, 0x94c0 },
2988
2989                 /*
2990                  * Tx Error Issue
2991                  * Enhance line driver power
2992                  */
2993                 { 0x1f, 0x0002 },
2994                 { 0x06, 0x5561 },
2995                 { 0x1f, 0x0005 },
2996                 { 0x05, 0x8332 },
2997                 { 0x06, 0x5561 },
2998
2999                 /*
3000                  * Can not link to 1Gbps with bad cable
3001                  * Decrease SNR threshold form 21.07dB to 19.04dB
3002                  */
3003                 { 0x1f, 0x0001 },
3004                 { 0x17, 0x0cc0 },
3005
3006                 { 0x1f, 0x0000 },
3007                 { 0x0d, 0xf880 }
3008         };
3009
3010         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3011
3012         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3013                 static const struct phy_reg phy_reg_init[] = {
3014                         { 0x1f, 0x0002 },
3015                         { 0x05, 0x669a },
3016                         { 0x1f, 0x0005 },
3017                         { 0x05, 0x8330 },
3018                         { 0x06, 0x669a },
3019
3020                         { 0x1f, 0x0002 }
3021                 };
3022                 int val;
3023
3024                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3025
3026                 val = rtl_readphy(tp, 0x0d);
3027                 if ((val & 0x00ff) != 0x006c) {
3028                         static const u32 set[] = {
3029                                 0x0065, 0x0066, 0x0067, 0x0068,
3030                                 0x0069, 0x006a, 0x006b, 0x006c
3031                         };
3032                         int i;
3033
3034                         rtl_writephy(tp, 0x1f, 0x0002);
3035
3036                         val &= 0xff00;
3037                         for (i = 0; i < ARRAY_SIZE(set); i++)
3038                                 rtl_writephy(tp, 0x0d, val | set[i]);
3039                 }
3040         } else {
3041                 static const struct phy_reg phy_reg_init[] = {
3042                         { 0x1f, 0x0002 },
3043                         { 0x05, 0x2642 },
3044                         { 0x1f, 0x0005 },
3045                         { 0x05, 0x8330 },
3046                         { 0x06, 0x2642 }
3047                 };
3048
3049                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3050         }
3051
3052         /* Fine tune PLL performance */
3053         rtl_writephy(tp, 0x1f, 0x0002);
3054         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3055         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3056
3057         /* Switching regulator Slew rate */
3058         rtl_writephy(tp, 0x1f, 0x0002);
3059         rtl_patchphy(tp, 0x0f, 0x0017);
3060
3061         rtl_writephy(tp, 0x1f, 0x0005);
3062         rtl_writephy(tp, 0x05, 0x001b);
3063
3064         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3065
3066         rtl_writephy(tp, 0x1f, 0x0000);
3067 }
3068
3069 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3070 {
3071         static const struct phy_reg phy_reg_init[] = {
3072                 { 0x1f, 0x0002 },
3073                 { 0x10, 0x0008 },
3074                 { 0x0d, 0x006c },
3075
3076                 { 0x1f, 0x0000 },
3077                 { 0x0d, 0xf880 },
3078
3079                 { 0x1f, 0x0001 },
3080                 { 0x17, 0x0cc0 },
3081
3082                 { 0x1f, 0x0001 },
3083                 { 0x0b, 0xa4d8 },
3084                 { 0x09, 0x281c },
3085                 { 0x07, 0x2883 },
3086                 { 0x0a, 0x6b35 },
3087                 { 0x1d, 0x3da4 },
3088                 { 0x1c, 0xeffd },
3089                 { 0x14, 0x7f52 },
3090                 { 0x18, 0x7fc6 },
3091                 { 0x08, 0x0601 },
3092                 { 0x06, 0x4063 },
3093                 { 0x10, 0xf074 },
3094                 { 0x1f, 0x0003 },
3095                 { 0x13, 0x0789 },
3096                 { 0x12, 0xf4bd },
3097                 { 0x1a, 0x04fd },
3098                 { 0x14, 0x84b0 },
3099                 { 0x1f, 0x0000 },
3100                 { 0x00, 0x9200 },
3101
3102                 { 0x1f, 0x0005 },
3103                 { 0x01, 0x0340 },
3104                 { 0x1f, 0x0001 },
3105                 { 0x04, 0x4000 },
3106                 { 0x03, 0x1d21 },
3107                 { 0x02, 0x0c32 },
3108                 { 0x01, 0x0200 },
3109                 { 0x00, 0x5554 },
3110                 { 0x04, 0x4800 },
3111                 { 0x04, 0x4000 },
3112                 { 0x04, 0xf000 },
3113                 { 0x03, 0xdf01 },
3114                 { 0x02, 0xdf20 },
3115                 { 0x01, 0x101a },
3116                 { 0x00, 0xa0ff },
3117                 { 0x04, 0xf800 },
3118                 { 0x04, 0xf000 },
3119                 { 0x1f, 0x0000 },
3120
3121                 { 0x1f, 0x0007 },
3122                 { 0x1e, 0x0023 },
3123                 { 0x16, 0x0000 },
3124                 { 0x1f, 0x0000 }
3125         };
3126
3127         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3128 }
3129
3130 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3131 {
3132         static const struct phy_reg phy_reg_init[] = {
3133                 { 0x1f, 0x0001 },
3134                 { 0x17, 0x0cc0 },
3135
3136                 { 0x1f, 0x0007 },
3137                 { 0x1e, 0x002d },
3138                 { 0x18, 0x0040 },
3139                 { 0x1f, 0x0000 }
3140         };
3141
3142         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3143         rtl_patchphy(tp, 0x0d, 1 << 5);
3144 }
3145
3146 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3147 {
3148         static const struct phy_reg phy_reg_init[] = {
3149                 /* Enable Delay cap */
3150                 { 0x1f, 0x0005 },
3151                 { 0x05, 0x8b80 },
3152                 { 0x06, 0xc896 },
3153                 { 0x1f, 0x0000 },
3154
3155                 /* Channel estimation fine tune */
3156                 { 0x1f, 0x0001 },
3157                 { 0x0b, 0x6c20 },
3158                 { 0x07, 0x2872 },
3159                 { 0x1c, 0xefff },
3160                 { 0x1f, 0x0003 },
3161                 { 0x14, 0x6420 },
3162                 { 0x1f, 0x0000 },
3163
3164                 /* Update PFM & 10M TX idle timer */
3165                 { 0x1f, 0x0007 },
3166                 { 0x1e, 0x002f },
3167                 { 0x15, 0x1919 },
3168                 { 0x1f, 0x0000 },
3169
3170                 { 0x1f, 0x0007 },
3171                 { 0x1e, 0x00ac },
3172                 { 0x18, 0x0006 },
3173                 { 0x1f, 0x0000 }
3174         };
3175
3176         rtl_apply_firmware(tp);
3177
3178         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3179
3180         /* DCO enable for 10M IDLE Power */
3181         rtl_writephy(tp, 0x1f, 0x0007);
3182         rtl_writephy(tp, 0x1e, 0x0023);
3183         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3184         rtl_writephy(tp, 0x1f, 0x0000);
3185
3186         /* For impedance matching */
3187         rtl_writephy(tp, 0x1f, 0x0002);
3188         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3189         rtl_writephy(tp, 0x1f, 0x0000);
3190
3191         /* PHY auto speed down */
3192         rtl_writephy(tp, 0x1f, 0x0007);
3193         rtl_writephy(tp, 0x1e, 0x002d);
3194         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3195         rtl_writephy(tp, 0x1f, 0x0000);
3196         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3197
3198         rtl_writephy(tp, 0x1f, 0x0005);
3199         rtl_writephy(tp, 0x05, 0x8b86);
3200         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3201         rtl_writephy(tp, 0x1f, 0x0000);
3202
3203         rtl_writephy(tp, 0x1f, 0x0005);
3204         rtl_writephy(tp, 0x05, 0x8b85);
3205         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3206         rtl_writephy(tp, 0x1f, 0x0007);
3207         rtl_writephy(tp, 0x1e, 0x0020);
3208         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3209         rtl_writephy(tp, 0x1f, 0x0006);
3210         rtl_writephy(tp, 0x00, 0x5a00);
3211         rtl_writephy(tp, 0x1f, 0x0000);
3212         rtl_writephy(tp, 0x0d, 0x0007);
3213         rtl_writephy(tp, 0x0e, 0x003c);
3214         rtl_writephy(tp, 0x0d, 0x4007);
3215         rtl_writephy(tp, 0x0e, 0x0000);
3216         rtl_writephy(tp, 0x0d, 0x0000);
3217 }
3218
3219 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3220 {
3221         const u16 w[] = {
3222                 addr[0] | (addr[1] << 8),
3223                 addr[2] | (addr[3] << 8),
3224                 addr[4] | (addr[5] << 8)
3225         };
3226         const struct exgmac_reg e[] = {
3227                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3228                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3229                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3230                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3231         };
3232
3233         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3234 }
3235
3236 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3237 {
3238         static const struct phy_reg phy_reg_init[] = {
3239                 /* Enable Delay cap */
3240                 { 0x1f, 0x0004 },
3241                 { 0x1f, 0x0007 },
3242                 { 0x1e, 0x00ac },
3243                 { 0x18, 0x0006 },
3244                 { 0x1f, 0x0002 },
3245                 { 0x1f, 0x0000 },
3246                 { 0x1f, 0x0000 },
3247
3248                 /* Channel estimation fine tune */
3249                 { 0x1f, 0x0003 },
3250                 { 0x09, 0xa20f },
3251                 { 0x1f, 0x0000 },
3252                 { 0x1f, 0x0000 },
3253
3254                 /* Green Setting */
3255                 { 0x1f, 0x0005 },
3256                 { 0x05, 0x8b5b },
3257                 { 0x06, 0x9222 },
3258                 { 0x05, 0x8b6d },
3259                 { 0x06, 0x8000 },
3260                 { 0x05, 0x8b76 },
3261                 { 0x06, 0x8000 },
3262                 { 0x1f, 0x0000 }
3263         };
3264
3265         rtl_apply_firmware(tp);
3266
3267         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3268
3269         /* For 4-corner performance improve */
3270         rtl_writephy(tp, 0x1f, 0x0005);
3271         rtl_writephy(tp, 0x05, 0x8b80);
3272         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3273         rtl_writephy(tp, 0x1f, 0x0000);
3274
3275         /* PHY auto speed down */
3276         rtl_writephy(tp, 0x1f, 0x0004);
3277         rtl_writephy(tp, 0x1f, 0x0007);
3278         rtl_writephy(tp, 0x1e, 0x002d);
3279         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3280         rtl_writephy(tp, 0x1f, 0x0002);
3281         rtl_writephy(tp, 0x1f, 0x0000);
3282         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3283
3284         /* improve 10M EEE waveform */
3285         rtl_writephy(tp, 0x1f, 0x0005);
3286         rtl_writephy(tp, 0x05, 0x8b86);
3287         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3288         rtl_writephy(tp, 0x1f, 0x0000);
3289
3290         /* Improve 2-pair detection performance */
3291         rtl_writephy(tp, 0x1f, 0x0005);
3292         rtl_writephy(tp, 0x05, 0x8b85);
3293         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3294         rtl_writephy(tp, 0x1f, 0x0000);
3295
3296         /* EEE setting */
3297         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3298         rtl_writephy(tp, 0x1f, 0x0005);
3299         rtl_writephy(tp, 0x05, 0x8b85);
3300         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3301         rtl_writephy(tp, 0x1f, 0x0004);
3302         rtl_writephy(tp, 0x1f, 0x0007);
3303         rtl_writephy(tp, 0x1e, 0x0020);
3304         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3305         rtl_writephy(tp, 0x1f, 0x0002);
3306         rtl_writephy(tp, 0x1f, 0x0000);
3307         rtl_writephy(tp, 0x0d, 0x0007);
3308         rtl_writephy(tp, 0x0e, 0x003c);
3309         rtl_writephy(tp, 0x0d, 0x4007);
3310         rtl_writephy(tp, 0x0e, 0x0006);
3311         rtl_writephy(tp, 0x0d, 0x0000);
3312
3313         /* Green feature */
3314         rtl_writephy(tp, 0x1f, 0x0003);
3315         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3316         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3317         rtl_writephy(tp, 0x1f, 0x0000);
3318         rtl_writephy(tp, 0x1f, 0x0005);
3319         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3320         rtl_writephy(tp, 0x1f, 0x0000);
3321
3322         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3323         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3324 }
3325
3326 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3327 {
3328         /* For 4-corner performance improve */
3329         rtl_writephy(tp, 0x1f, 0x0005);
3330         rtl_writephy(tp, 0x05, 0x8b80);
3331         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3332         rtl_writephy(tp, 0x1f, 0x0000);
3333
3334         /* PHY auto speed down */
3335         rtl_writephy(tp, 0x1f, 0x0007);
3336         rtl_writephy(tp, 0x1e, 0x002d);
3337         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3338         rtl_writephy(tp, 0x1f, 0x0000);
3339         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3340
3341         /* Improve 10M EEE waveform */
3342         rtl_writephy(tp, 0x1f, 0x0005);
3343         rtl_writephy(tp, 0x05, 0x8b86);
3344         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3345         rtl_writephy(tp, 0x1f, 0x0000);
3346 }
3347
3348 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3349 {
3350         static const struct phy_reg phy_reg_init[] = {
3351                 /* Channel estimation fine tune */
3352                 { 0x1f, 0x0003 },
3353                 { 0x09, 0xa20f },
3354                 { 0x1f, 0x0000 },
3355
3356                 /* Modify green table for giga & fnet */
3357                 { 0x1f, 0x0005 },
3358                 { 0x05, 0x8b55 },
3359                 { 0x06, 0x0000 },
3360                 { 0x05, 0x8b5e },
3361                 { 0x06, 0x0000 },
3362                 { 0x05, 0x8b67 },
3363                 { 0x06, 0x0000 },
3364                 { 0x05, 0x8b70 },
3365                 { 0x06, 0x0000 },
3366                 { 0x1f, 0x0000 },
3367                 { 0x1f, 0x0007 },
3368                 { 0x1e, 0x0078 },
3369                 { 0x17, 0x0000 },
3370                 { 0x19, 0x00fb },
3371                 { 0x1f, 0x0000 },
3372
3373                 /* Modify green table for 10M */
3374                 { 0x1f, 0x0005 },
3375                 { 0x05, 0x8b79 },
3376                 { 0x06, 0xaa00 },
3377                 { 0x1f, 0x0000 },
3378
3379                 /* Disable hiimpedance detection (RTCT) */
3380                 { 0x1f, 0x0003 },
3381                 { 0x01, 0x328a },
3382                 { 0x1f, 0x0000 }
3383         };
3384
3385         rtl_apply_firmware(tp);
3386
3387         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3388
3389         rtl8168f_hw_phy_config(tp);
3390
3391         /* Improve 2-pair detection performance */
3392         rtl_writephy(tp, 0x1f, 0x0005);
3393         rtl_writephy(tp, 0x05, 0x8b85);
3394         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3395         rtl_writephy(tp, 0x1f, 0x0000);
3396 }
3397
3398 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3399 {
3400         rtl_apply_firmware(tp);
3401
3402         rtl8168f_hw_phy_config(tp);
3403 }
3404
3405 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3406 {
3407         static const struct phy_reg phy_reg_init[] = {
3408                 /* Channel estimation fine tune */
3409                 { 0x1f, 0x0003 },
3410                 { 0x09, 0xa20f },
3411                 { 0x1f, 0x0000 },
3412
3413                 /* Modify green table for giga & fnet */
3414                 { 0x1f, 0x0005 },
3415                 { 0x05, 0x8b55 },
3416                 { 0x06, 0x0000 },
3417                 { 0x05, 0x8b5e },
3418                 { 0x06, 0x0000 },
3419                 { 0x05, 0x8b67 },
3420                 { 0x06, 0x0000 },
3421                 { 0x05, 0x8b70 },
3422                 { 0x06, 0x0000 },
3423                 { 0x1f, 0x0000 },
3424                 { 0x1f, 0x0007 },
3425                 { 0x1e, 0x0078 },
3426                 { 0x17, 0x0000 },
3427                 { 0x19, 0x00aa },
3428                 { 0x1f, 0x0000 },
3429
3430                 /* Modify green table for 10M */
3431                 { 0x1f, 0x0005 },
3432                 { 0x05, 0x8b79 },
3433                 { 0x06, 0xaa00 },
3434                 { 0x1f, 0x0000 },
3435
3436                 /* Disable hiimpedance detection (RTCT) */
3437                 { 0x1f, 0x0003 },
3438                 { 0x01, 0x328a },
3439                 { 0x1f, 0x0000 }
3440         };
3441
3442
3443         rtl_apply_firmware(tp);
3444
3445         rtl8168f_hw_phy_config(tp);
3446
3447         /* Improve 2-pair detection performance */
3448         rtl_writephy(tp, 0x1f, 0x0005);
3449         rtl_writephy(tp, 0x05, 0x8b85);
3450         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3451         rtl_writephy(tp, 0x1f, 0x0000);
3452
3453         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3454
3455         /* Modify green table for giga */
3456         rtl_writephy(tp, 0x1f, 0x0005);
3457         rtl_writephy(tp, 0x05, 0x8b54);
3458         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3459         rtl_writephy(tp, 0x05, 0x8b5d);
3460         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3461         rtl_writephy(tp, 0x05, 0x8a7c);
3462         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3463         rtl_writephy(tp, 0x05, 0x8a7f);
3464         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3465         rtl_writephy(tp, 0x05, 0x8a82);
3466         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3467         rtl_writephy(tp, 0x05, 0x8a85);
3468         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3469         rtl_writephy(tp, 0x05, 0x8a88);
3470         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3471         rtl_writephy(tp, 0x1f, 0x0000);
3472
3473         /* uc same-seed solution */
3474         rtl_writephy(tp, 0x1f, 0x0005);
3475         rtl_writephy(tp, 0x05, 0x8b85);
3476         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3477         rtl_writephy(tp, 0x1f, 0x0000);
3478
3479         /* eee setting */
3480         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3481         rtl_writephy(tp, 0x1f, 0x0005);
3482         rtl_writephy(tp, 0x05, 0x8b85);
3483         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3484         rtl_writephy(tp, 0x1f, 0x0004);
3485         rtl_writephy(tp, 0x1f, 0x0007);
3486         rtl_writephy(tp, 0x1e, 0x0020);
3487         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3488         rtl_writephy(tp, 0x1f, 0x0000);
3489         rtl_writephy(tp, 0x0d, 0x0007);
3490         rtl_writephy(tp, 0x0e, 0x003c);
3491         rtl_writephy(tp, 0x0d, 0x4007);
3492         rtl_writephy(tp, 0x0e, 0x0000);
3493         rtl_writephy(tp, 0x0d, 0x0000);
3494
3495         /* Green feature */
3496         rtl_writephy(tp, 0x1f, 0x0003);
3497         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3498         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3499         rtl_writephy(tp, 0x1f, 0x0000);
3500 }
3501
3502 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3503 {
3504         rtl_apply_firmware(tp);
3505
3506         rtl_writephy(tp, 0x1f, 0x0a46);
3507         if (rtl_readphy(tp, 0x10) & 0x0100) {
3508                 rtl_writephy(tp, 0x1f, 0x0bcc);
3509                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3510         } else {
3511                 rtl_writephy(tp, 0x1f, 0x0bcc);
3512                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3513         }
3514
3515         rtl_writephy(tp, 0x1f, 0x0a46);
3516         if (rtl_readphy(tp, 0x13) & 0x0100) {
3517                 rtl_writephy(tp, 0x1f, 0x0c41);
3518                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3519         } else {
3520                 rtl_writephy(tp, 0x1f, 0x0c41);
3521                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3522         }
3523
3524         /* Enable PHY auto speed down */
3525         rtl_writephy(tp, 0x1f, 0x0a44);
3526         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3527
3528         rtl_writephy(tp, 0x1f, 0x0bcc);
3529         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3530         rtl_writephy(tp, 0x1f, 0x0a44);
3531         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3532         rtl_writephy(tp, 0x1f, 0x0a43);
3533         rtl_writephy(tp, 0x13, 0x8084);
3534         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3535         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3536
3537         /* EEE auto-fallback function */
3538         rtl_writephy(tp, 0x1f, 0x0a4b);
3539         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3540
3541         /* Enable UC LPF tune function */
3542         rtl_writephy(tp, 0x1f, 0x0a43);
3543         rtl_writephy(tp, 0x13, 0x8012);
3544         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3545
3546         rtl_writephy(tp, 0x1f, 0x0c42);
3547         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3548
3549         /* Improve SWR Efficiency */
3550         rtl_writephy(tp, 0x1f, 0x0bcd);
3551         rtl_writephy(tp, 0x14, 0x5065);
3552         rtl_writephy(tp, 0x14, 0xd065);
3553         rtl_writephy(tp, 0x1f, 0x0bc8);
3554         rtl_writephy(tp, 0x11, 0x5655);
3555         rtl_writephy(tp, 0x1f, 0x0bcd);
3556         rtl_writephy(tp, 0x14, 0x1065);
3557         rtl_writephy(tp, 0x14, 0x9065);
3558         rtl_writephy(tp, 0x14, 0x1065);
3559
3560         /* Check ALDPS bit, disable it if enabled */
3561         rtl_writephy(tp, 0x1f, 0x0a43);
3562         if (rtl_readphy(tp, 0x10) & 0x0004)
3563                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3564
3565         rtl_writephy(tp, 0x1f, 0x0000);
3566 }
3567
3568 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3569 {
3570         rtl_apply_firmware(tp);
3571 }
3572
3573 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3574 {
3575         u16 dout_tapbin;
3576         u32 data;
3577
3578         rtl_apply_firmware(tp);
3579
3580         /* CHN EST parameters adjust - giga master */
3581         rtl_writephy(tp, 0x1f, 0x0a43);
3582         rtl_writephy(tp, 0x13, 0x809b);
3583         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3584         rtl_writephy(tp, 0x13, 0x80a2);
3585         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3586         rtl_writephy(tp, 0x13, 0x80a4);
3587         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3588         rtl_writephy(tp, 0x13, 0x809c);
3589         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3590         rtl_writephy(tp, 0x1f, 0x0000);
3591
3592         /* CHN EST parameters adjust - giga slave */
3593         rtl_writephy(tp, 0x1f, 0x0a43);
3594         rtl_writephy(tp, 0x13, 0x80ad);
3595         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3596         rtl_writephy(tp, 0x13, 0x80b4);
3597         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3598         rtl_writephy(tp, 0x13, 0x80ac);
3599         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3600         rtl_writephy(tp, 0x1f, 0x0000);
3601
3602         /* CHN EST parameters adjust - fnet */
3603         rtl_writephy(tp, 0x1f, 0x0a43);
3604         rtl_writephy(tp, 0x13, 0x808e);
3605         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3606         rtl_writephy(tp, 0x13, 0x8090);
3607         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3608         rtl_writephy(tp, 0x13, 0x8092);
3609         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3610         rtl_writephy(tp, 0x1f, 0x0000);
3611
3612         /* enable R-tune & PGA-retune function */
3613         dout_tapbin = 0;
3614         rtl_writephy(tp, 0x1f, 0x0a46);
3615         data = rtl_readphy(tp, 0x13);
3616         data &= 3;
3617         data <<= 2;
3618         dout_tapbin |= data;
3619         data = rtl_readphy(tp, 0x12);
3620         data &= 0xc000;
3621         data >>= 14;
3622         dout_tapbin |= data;
3623         dout_tapbin = ~(dout_tapbin^0x08);
3624         dout_tapbin <<= 12;
3625         dout_tapbin &= 0xf000;
3626         rtl_writephy(tp, 0x1f, 0x0a43);
3627         rtl_writephy(tp, 0x13, 0x827a);
3628         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3629         rtl_writephy(tp, 0x13, 0x827b);
3630         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3631         rtl_writephy(tp, 0x13, 0x827c);
3632         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3633         rtl_writephy(tp, 0x13, 0x827d);
3634         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3635
3636         rtl_writephy(tp, 0x1f, 0x0a43);
3637         rtl_writephy(tp, 0x13, 0x0811);
3638         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3639         rtl_writephy(tp, 0x1f, 0x0a42);
3640         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3641         rtl_writephy(tp, 0x1f, 0x0000);
3642
3643         /* enable GPHY 10M */
3644         rtl_writephy(tp, 0x1f, 0x0a44);
3645         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3646         rtl_writephy(tp, 0x1f, 0x0000);
3647
3648         /* SAR ADC performance */
3649         rtl_writephy(tp, 0x1f, 0x0bca);
3650         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3651         rtl_writephy(tp, 0x1f, 0x0000);
3652
3653         rtl_writephy(tp, 0x1f, 0x0a43);
3654         rtl_writephy(tp, 0x13, 0x803f);
3655         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3656         rtl_writephy(tp, 0x13, 0x8047);
3657         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3658         rtl_writephy(tp, 0x13, 0x804f);
3659         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3660         rtl_writephy(tp, 0x13, 0x8057);
3661         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3662         rtl_writephy(tp, 0x13, 0x805f);
3663         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3664         rtl_writephy(tp, 0x13, 0x8067);
3665         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3666         rtl_writephy(tp, 0x13, 0x806f);
3667         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3668         rtl_writephy(tp, 0x1f, 0x0000);
3669
3670         /* disable phy pfm mode */
3671         rtl_writephy(tp, 0x1f, 0x0a44);
3672         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3673         rtl_writephy(tp, 0x1f, 0x0000);
3674
3675         /* Check ALDPS bit, disable it if enabled */
3676         rtl_writephy(tp, 0x1f, 0x0a43);
3677         if (rtl_readphy(tp, 0x10) & 0x0004)
3678                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3679
3680         rtl_writephy(tp, 0x1f, 0x0000);
3681 }
3682
3683 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3684 {
3685         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3686         u16 rlen;
3687         u32 data;
3688
3689         rtl_apply_firmware(tp);
3690
3691         /* CHIN EST parameter update */
3692         rtl_writephy(tp, 0x1f, 0x0a43);
3693         rtl_writephy(tp, 0x13, 0x808a);
3694         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3695         rtl_writephy(tp, 0x1f, 0x0000);
3696
3697         /* enable R-tune & PGA-retune function */
3698         rtl_writephy(tp, 0x1f, 0x0a43);
3699         rtl_writephy(tp, 0x13, 0x0811);
3700         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3701         rtl_writephy(tp, 0x1f, 0x0a42);
3702         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3703         rtl_writephy(tp, 0x1f, 0x0000);
3704
3705         /* enable GPHY 10M */
3706         rtl_writephy(tp, 0x1f, 0x0a44);
3707         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3708         rtl_writephy(tp, 0x1f, 0x0000);
3709
3710         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3711         data = r8168_mac_ocp_read(tp, 0xdd02);
3712         ioffset_p3 = ((data & 0x80)>>7);
3713         ioffset_p3 <<= 3;
3714
3715         data = r8168_mac_ocp_read(tp, 0xdd00);
3716         ioffset_p3 |= ((data & (0xe000))>>13);
3717         ioffset_p2 = ((data & (0x1e00))>>9);
3718         ioffset_p1 = ((data & (0x01e0))>>5);
3719         ioffset_p0 = ((data & 0x0010)>>4);
3720         ioffset_p0 <<= 3;
3721         ioffset_p0 |= (data & (0x07));
3722         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3723
3724         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3725             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3726                 rtl_writephy(tp, 0x1f, 0x0bcf);
3727                 rtl_writephy(tp, 0x16, data);
3728                 rtl_writephy(tp, 0x1f, 0x0000);
3729         }
3730
3731         /* Modify rlen (TX LPF corner frequency) level */
3732         rtl_writephy(tp, 0x1f, 0x0bcd);
3733         data = rtl_readphy(tp, 0x16);
3734         data &= 0x000f;
3735         rlen = 0;
3736         if (data > 3)
3737                 rlen = data - 3;
3738         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3739         rtl_writephy(tp, 0x17, data);
3740         rtl_writephy(tp, 0x1f, 0x0bcd);
3741         rtl_writephy(tp, 0x1f, 0x0000);
3742
3743         /* disable phy pfm mode */
3744         rtl_writephy(tp, 0x1f, 0x0a44);
3745         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3746         rtl_writephy(tp, 0x1f, 0x0000);
3747
3748         /* Check ALDPS bit, disable it if enabled */
3749         rtl_writephy(tp, 0x1f, 0x0a43);
3750         if (rtl_readphy(tp, 0x10) & 0x0004)
3751                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3752
3753         rtl_writephy(tp, 0x1f, 0x0000);
3754 }
3755
3756 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3757 {
3758         /* Enable PHY auto speed down */
3759         rtl_writephy(tp, 0x1f, 0x0a44);
3760         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3761         rtl_writephy(tp, 0x1f, 0x0000);
3762
3763         /* patch 10M & ALDPS */
3764         rtl_writephy(tp, 0x1f, 0x0bcc);
3765         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3766         rtl_writephy(tp, 0x1f, 0x0a44);
3767         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3768         rtl_writephy(tp, 0x1f, 0x0a43);
3769         rtl_writephy(tp, 0x13, 0x8084);
3770         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3771         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3772         rtl_writephy(tp, 0x1f, 0x0000);
3773
3774         /* Enable EEE auto-fallback function */
3775         rtl_writephy(tp, 0x1f, 0x0a4b);
3776         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3777         rtl_writephy(tp, 0x1f, 0x0000);
3778
3779         /* Enable UC LPF tune function */
3780         rtl_writephy(tp, 0x1f, 0x0a43);
3781         rtl_writephy(tp, 0x13, 0x8012);
3782         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3783         rtl_writephy(tp, 0x1f, 0x0000);
3784
3785         /* set rg_sel_sdm_rate */
3786         rtl_writephy(tp, 0x1f, 0x0c42);
3787         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3788         rtl_writephy(tp, 0x1f, 0x0000);
3789
3790         /* Check ALDPS bit, disable it if enabled */
3791         rtl_writephy(tp, 0x1f, 0x0a43);
3792         if (rtl_readphy(tp, 0x10) & 0x0004)
3793                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3794
3795         rtl_writephy(tp, 0x1f, 0x0000);
3796 }
3797
3798 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3799 {
3800         /* patch 10M & ALDPS */
3801         rtl_writephy(tp, 0x1f, 0x0bcc);
3802         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3803         rtl_writephy(tp, 0x1f, 0x0a44);
3804         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3805         rtl_writephy(tp, 0x1f, 0x0a43);
3806         rtl_writephy(tp, 0x13, 0x8084);
3807         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3808         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3809         rtl_writephy(tp, 0x1f, 0x0000);
3810
3811         /* Enable UC LPF tune function */
3812         rtl_writephy(tp, 0x1f, 0x0a43);
3813         rtl_writephy(tp, 0x13, 0x8012);
3814         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3815         rtl_writephy(tp, 0x1f, 0x0000);
3816
3817         /* Set rg_sel_sdm_rate */
3818         rtl_writephy(tp, 0x1f, 0x0c42);
3819         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3820         rtl_writephy(tp, 0x1f, 0x0000);
3821
3822         /* Channel estimation parameters */
3823         rtl_writephy(tp, 0x1f, 0x0a43);
3824         rtl_writephy(tp, 0x13, 0x80f3);
3825         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3826         rtl_writephy(tp, 0x13, 0x80f0);
3827         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3828         rtl_writephy(tp, 0x13, 0x80ef);
3829         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3830         rtl_writephy(tp, 0x13, 0x80f6);
3831         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3832         rtl_writephy(tp, 0x13, 0x80ec);
3833         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3834         rtl_writephy(tp, 0x13, 0x80ed);
3835         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3836         rtl_writephy(tp, 0x13, 0x80f2);
3837         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3838         rtl_writephy(tp, 0x13, 0x80f4);
3839         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3840         rtl_writephy(tp, 0x1f, 0x0a43);
3841         rtl_writephy(tp, 0x13, 0x8110);
3842         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3843         rtl_writephy(tp, 0x13, 0x810f);
3844         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3845         rtl_writephy(tp, 0x13, 0x8111);
3846         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3847         rtl_writephy(tp, 0x13, 0x8113);
3848         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3849         rtl_writephy(tp, 0x13, 0x8115);
3850         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3851         rtl_writephy(tp, 0x13, 0x810e);
3852         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3853         rtl_writephy(tp, 0x13, 0x810c);
3854         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3855         rtl_writephy(tp, 0x13, 0x810b);
3856         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3857         rtl_writephy(tp, 0x1f, 0x0a43);
3858         rtl_writephy(tp, 0x13, 0x80d1);
3859         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3860         rtl_writephy(tp, 0x13, 0x80cd);
3861         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3862         rtl_writephy(tp, 0x13, 0x80d3);
3863         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3864         rtl_writephy(tp, 0x13, 0x80d5);
3865         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3866         rtl_writephy(tp, 0x13, 0x80d7);
3867         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3868
3869         /* Force PWM-mode */
3870         rtl_writephy(tp, 0x1f, 0x0bcd);
3871         rtl_writephy(tp, 0x14, 0x5065);
3872         rtl_writephy(tp, 0x14, 0xd065);
3873         rtl_writephy(tp, 0x1f, 0x0bc8);
3874         rtl_writephy(tp, 0x12, 0x00ed);
3875         rtl_writephy(tp, 0x1f, 0x0bcd);
3876         rtl_writephy(tp, 0x14, 0x1065);
3877         rtl_writephy(tp, 0x14, 0x9065);
3878         rtl_writephy(tp, 0x14, 0x1065);
3879         rtl_writephy(tp, 0x1f, 0x0000);
3880
3881         /* Check ALDPS bit, disable it if enabled */
3882         rtl_writephy(tp, 0x1f, 0x0a43);
3883         if (rtl_readphy(tp, 0x10) & 0x0004)
3884                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3885
3886         rtl_writephy(tp, 0x1f, 0x0000);
3887 }
3888
3889 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3890 {
3891         static const struct phy_reg phy_reg_init[] = {
3892                 { 0x1f, 0x0003 },
3893                 { 0x08, 0x441d },
3894                 { 0x01, 0x9100 },
3895                 { 0x1f, 0x0000 }
3896         };
3897
3898         rtl_writephy(tp, 0x1f, 0x0000);
3899         rtl_patchphy(tp, 0x11, 1 << 12);
3900         rtl_patchphy(tp, 0x19, 1 << 13);
3901         rtl_patchphy(tp, 0x10, 1 << 15);
3902
3903         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3904 }
3905
3906 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3907 {
3908         static const struct phy_reg phy_reg_init[] = {
3909                 { 0x1f, 0x0005 },
3910                 { 0x1a, 0x0000 },
3911                 { 0x1f, 0x0000 },
3912
3913                 { 0x1f, 0x0004 },
3914                 { 0x1c, 0x0000 },
3915                 { 0x1f, 0x0000 },
3916
3917                 { 0x1f, 0x0001 },
3918                 { 0x15, 0x7701 },
3919                 { 0x1f, 0x0000 }
3920         };
3921
3922         /* Disable ALDPS before ram code */
3923         rtl_writephy(tp, 0x1f, 0x0000);
3924         rtl_writephy(tp, 0x18, 0x0310);
3925         msleep(100);
3926
3927         rtl_apply_firmware(tp);
3928
3929         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3930 }
3931
3932 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3933 {
3934         /* Disable ALDPS before setting firmware */
3935         rtl_writephy(tp, 0x1f, 0x0000);
3936         rtl_writephy(tp, 0x18, 0x0310);
3937         msleep(20);
3938
3939         rtl_apply_firmware(tp);
3940
3941         /* EEE setting */
3942         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3943         rtl_writephy(tp, 0x1f, 0x0004);
3944         rtl_writephy(tp, 0x10, 0x401f);
3945         rtl_writephy(tp, 0x19, 0x7030);
3946         rtl_writephy(tp, 0x1f, 0x0000);
3947 }
3948
3949 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3950 {
3951         static const struct phy_reg phy_reg_init[] = {
3952                 { 0x1f, 0x0004 },
3953                 { 0x10, 0xc07f },
3954                 { 0x19, 0x7030 },
3955                 { 0x1f, 0x0000 }
3956         };
3957
3958         /* Disable ALDPS before ram code */
3959         rtl_writephy(tp, 0x1f, 0x0000);
3960         rtl_writephy(tp, 0x18, 0x0310);
3961         msleep(100);
3962
3963         rtl_apply_firmware(tp);
3964
3965         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3966         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3967
3968         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3969 }
3970
3971 static void rtl_hw_phy_config(struct net_device *dev)
3972 {
3973         struct rtl8169_private *tp = netdev_priv(dev);
3974
3975         rtl8169_print_mac_version(tp);
3976
3977         switch (tp->mac_version) {
3978         case RTL_GIGA_MAC_VER_01:
3979                 break;
3980         case RTL_GIGA_MAC_VER_02:
3981         case RTL_GIGA_MAC_VER_03:
3982                 rtl8169s_hw_phy_config(tp);
3983                 break;
3984         case RTL_GIGA_MAC_VER_04:
3985                 rtl8169sb_hw_phy_config(tp);
3986                 break;
3987         case RTL_GIGA_MAC_VER_05:
3988                 rtl8169scd_hw_phy_config(tp);
3989                 break;
3990         case RTL_GIGA_MAC_VER_06:
3991                 rtl8169sce_hw_phy_config(tp);
3992                 break;
3993         case RTL_GIGA_MAC_VER_07:
3994         case RTL_GIGA_MAC_VER_08:
3995         case RTL_GIGA_MAC_VER_09:
3996                 rtl8102e_hw_phy_config(tp);
3997                 break;
3998         case RTL_GIGA_MAC_VER_11:
3999                 rtl8168bb_hw_phy_config(tp);
4000                 break;
4001         case RTL_GIGA_MAC_VER_12:
4002                 rtl8168bef_hw_phy_config(tp);
4003                 break;
4004         case RTL_GIGA_MAC_VER_17:
4005                 rtl8168bef_hw_phy_config(tp);
4006                 break;
4007         case RTL_GIGA_MAC_VER_18:
4008                 rtl8168cp_1_hw_phy_config(tp);
4009                 break;
4010         case RTL_GIGA_MAC_VER_19:
4011                 rtl8168c_1_hw_phy_config(tp);
4012                 break;
4013         case RTL_GIGA_MAC_VER_20:
4014                 rtl8168c_2_hw_phy_config(tp);
4015                 break;
4016         case RTL_GIGA_MAC_VER_21:
4017                 rtl8168c_3_hw_phy_config(tp);
4018                 break;
4019         case RTL_GIGA_MAC_VER_22:
4020                 rtl8168c_4_hw_phy_config(tp);
4021                 break;
4022         case RTL_GIGA_MAC_VER_23:
4023         case RTL_GIGA_MAC_VER_24:
4024                 rtl8168cp_2_hw_phy_config(tp);
4025                 break;
4026         case RTL_GIGA_MAC_VER_25:
4027                 rtl8168d_1_hw_phy_config(tp);
4028                 break;
4029         case RTL_GIGA_MAC_VER_26:
4030                 rtl8168d_2_hw_phy_config(tp);
4031                 break;
4032         case RTL_GIGA_MAC_VER_27:
4033                 rtl8168d_3_hw_phy_config(tp);
4034                 break;
4035         case RTL_GIGA_MAC_VER_28:
4036                 rtl8168d_4_hw_phy_config(tp);
4037                 break;
4038         case RTL_GIGA_MAC_VER_29:
4039         case RTL_GIGA_MAC_VER_30:
4040                 rtl8105e_hw_phy_config(tp);
4041                 break;
4042         case RTL_GIGA_MAC_VER_31:
4043                 /* None. */
4044                 break;
4045         case RTL_GIGA_MAC_VER_32:
4046         case RTL_GIGA_MAC_VER_33:
4047                 rtl8168e_1_hw_phy_config(tp);
4048                 break;
4049         case RTL_GIGA_MAC_VER_34:
4050                 rtl8168e_2_hw_phy_config(tp);
4051                 break;
4052         case RTL_GIGA_MAC_VER_35:
4053                 rtl8168f_1_hw_phy_config(tp);
4054                 break;
4055         case RTL_GIGA_MAC_VER_36:
4056                 rtl8168f_2_hw_phy_config(tp);
4057                 break;
4058
4059         case RTL_GIGA_MAC_VER_37:
4060                 rtl8402_hw_phy_config(tp);
4061                 break;
4062
4063         case RTL_GIGA_MAC_VER_38:
4064                 rtl8411_hw_phy_config(tp);
4065                 break;
4066
4067         case RTL_GIGA_MAC_VER_39:
4068                 rtl8106e_hw_phy_config(tp);
4069                 break;
4070
4071         case RTL_GIGA_MAC_VER_40:
4072                 rtl8168g_1_hw_phy_config(tp);
4073                 break;
4074         case RTL_GIGA_MAC_VER_42:
4075         case RTL_GIGA_MAC_VER_43:
4076         case RTL_GIGA_MAC_VER_44:
4077                 rtl8168g_2_hw_phy_config(tp);
4078                 break;
4079         case RTL_GIGA_MAC_VER_45:
4080         case RTL_GIGA_MAC_VER_47:
4081                 rtl8168h_1_hw_phy_config(tp);
4082                 break;
4083         case RTL_GIGA_MAC_VER_46:
4084         case RTL_GIGA_MAC_VER_48:
4085                 rtl8168h_2_hw_phy_config(tp);
4086                 break;
4087
4088         case RTL_GIGA_MAC_VER_49:
4089                 rtl8168ep_1_hw_phy_config(tp);
4090                 break;
4091         case RTL_GIGA_MAC_VER_50:
4092         case RTL_GIGA_MAC_VER_51:
4093                 rtl8168ep_2_hw_phy_config(tp);
4094                 break;
4095
4096         case RTL_GIGA_MAC_VER_41:
4097         default:
4098                 break;
4099         }
4100 }
4101
4102 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4103 {
4104         if (!test_and_set_bit(flag, tp->wk.flags))
4105                 schedule_work(&tp->wk.work);
4106 }
4107
4108 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4109 {
4110         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4111                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4112 }
4113
4114 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4115 {
4116         rtl_hw_phy_config(dev);
4117
4118         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4119                 netif_dbg(tp, drv, dev,
4120                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4121                 RTL_W8(tp, 0x82, 0x01);
4122         }
4123
4124         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4125
4126         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4127                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4128
4129         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4130                 netif_dbg(tp, drv, dev,
4131                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4132                 RTL_W8(tp, 0x82, 0x01);
4133                 netif_dbg(tp, drv, dev,
4134                           "Set PHY Reg 0x0bh = 0x00h\n");
4135                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4136         }
4137
4138         /* We may have called phy_speed_down before */
4139         phy_speed_up(dev->phydev);
4140
4141         genphy_soft_reset(dev->phydev);
4142 }
4143
4144 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4145 {
4146         rtl_lock_work(tp);
4147
4148         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4149
4150         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4151         RTL_R32(tp, MAC4);
4152
4153         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4154         RTL_R32(tp, MAC0);
4155
4156         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4157                 rtl_rar_exgmac_set(tp, addr);
4158
4159         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4160
4161         rtl_unlock_work(tp);
4162 }
4163
4164 static int rtl_set_mac_address(struct net_device *dev, void *p)
4165 {
4166         struct rtl8169_private *tp = netdev_priv(dev);
4167         struct device *d = tp_to_dev(tp);
4168         int ret;
4169
4170         ret = eth_mac_addr(dev, p);
4171         if (ret)
4172                 return ret;
4173
4174         pm_runtime_get_noresume(d);
4175
4176         if (pm_runtime_active(d))
4177                 rtl_rar_set(tp, dev->dev_addr);
4178
4179         pm_runtime_put_noidle(d);
4180
4181         return 0;
4182 }
4183
4184 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4185 {
4186         if (!netif_running(dev))
4187                 return -ENODEV;
4188
4189         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4190 }
4191
4192 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4193 {
4194         struct mdio_ops *ops = &tp->mdio_ops;
4195
4196         switch (tp->mac_version) {
4197         case RTL_GIGA_MAC_VER_27:
4198                 ops->write      = r8168dp_1_mdio_write;
4199                 ops->read       = r8168dp_1_mdio_read;
4200                 break;
4201         case RTL_GIGA_MAC_VER_28:
4202         case RTL_GIGA_MAC_VER_31:
4203                 ops->write      = r8168dp_2_mdio_write;
4204                 ops->read       = r8168dp_2_mdio_read;
4205                 break;
4206         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4207                 ops->write      = r8168g_mdio_write;
4208                 ops->read       = r8168g_mdio_read;
4209                 break;
4210         default:
4211                 ops->write      = r8169_mdio_write;
4212                 ops->read       = r8169_mdio_read;
4213                 break;
4214         }
4215 }
4216
4217 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4218 {
4219         switch (tp->mac_version) {
4220         case RTL_GIGA_MAC_VER_25:
4221         case RTL_GIGA_MAC_VER_26:
4222         case RTL_GIGA_MAC_VER_29:
4223         case RTL_GIGA_MAC_VER_30:
4224         case RTL_GIGA_MAC_VER_32:
4225         case RTL_GIGA_MAC_VER_33:
4226         case RTL_GIGA_MAC_VER_34:
4227         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4228                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4229                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4230                 break;
4231         default:
4232                 break;
4233         }
4234 }
4235
4236 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4237 {
4238         if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4239                 return false;
4240
4241         phy_speed_down(tp->dev->phydev, false);
4242         rtl_wol_suspend_quirk(tp);
4243
4244         return true;
4245 }
4246
4247 static void r8168_pll_power_down(struct rtl8169_private *tp)
4248 {
4249         if (r8168_check_dash(tp))
4250                 return;
4251
4252         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4253             tp->mac_version == RTL_GIGA_MAC_VER_33)
4254                 rtl_ephy_write(tp, 0x19, 0xff64);
4255
4256         if (rtl_wol_pll_power_down(tp))
4257                 return;
4258
4259         switch (tp->mac_version) {
4260         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4261         case RTL_GIGA_MAC_VER_37:
4262         case RTL_GIGA_MAC_VER_39:
4263         case RTL_GIGA_MAC_VER_43:
4264         case RTL_GIGA_MAC_VER_44:
4265         case RTL_GIGA_MAC_VER_45:
4266         case RTL_GIGA_MAC_VER_46:
4267         case RTL_GIGA_MAC_VER_47:
4268         case RTL_GIGA_MAC_VER_48:
4269         case RTL_GIGA_MAC_VER_50:
4270         case RTL_GIGA_MAC_VER_51:
4271                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4272                 break;
4273         case RTL_GIGA_MAC_VER_40:
4274         case RTL_GIGA_MAC_VER_41:
4275         case RTL_GIGA_MAC_VER_49:
4276                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4277                              0xfc000000, ERIAR_EXGMAC);
4278                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4279                 break;
4280         }
4281 }
4282
4283 static void r8168_pll_power_up(struct rtl8169_private *tp)
4284 {
4285         switch (tp->mac_version) {
4286         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4287         case RTL_GIGA_MAC_VER_37:
4288         case RTL_GIGA_MAC_VER_39:
4289         case RTL_GIGA_MAC_VER_43:
4290                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4291                 break;
4292         case RTL_GIGA_MAC_VER_44:
4293         case RTL_GIGA_MAC_VER_45:
4294         case RTL_GIGA_MAC_VER_46:
4295         case RTL_GIGA_MAC_VER_47:
4296         case RTL_GIGA_MAC_VER_48:
4297         case RTL_GIGA_MAC_VER_50:
4298         case RTL_GIGA_MAC_VER_51:
4299                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4300                 break;
4301         case RTL_GIGA_MAC_VER_40:
4302         case RTL_GIGA_MAC_VER_41:
4303         case RTL_GIGA_MAC_VER_49:
4304                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4305                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4306                              0x00000000, ERIAR_EXGMAC);
4307                 break;
4308         }
4309
4310         phy_resume(tp->dev->phydev);
4311         /* give MAC/PHY some time to resume */
4312         msleep(20);
4313 }
4314
4315 static void rtl_pll_power_down(struct rtl8169_private *tp)
4316 {
4317         switch (tp->mac_version) {
4318         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4319         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4320                 break;
4321         default:
4322                 r8168_pll_power_down(tp);
4323         }
4324 }
4325
4326 static void rtl_pll_power_up(struct rtl8169_private *tp)
4327 {
4328         switch (tp->mac_version) {
4329         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4330         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4331                 break;
4332         default:
4333                 r8168_pll_power_up(tp);
4334         }
4335 }
4336
4337 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4338 {
4339         switch (tp->mac_version) {
4340         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4341         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4342                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4343                 break;
4344         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4345         case RTL_GIGA_MAC_VER_34:
4346         case RTL_GIGA_MAC_VER_35:
4347                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4348                 break;
4349         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4350                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4351                 break;
4352         default:
4353                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4354                 break;
4355         }
4356 }
4357
4358 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4359 {
4360         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4361 }
4362
4363 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4364 {
4365         if (tp->jumbo_ops.enable) {
4366                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4367                 tp->jumbo_ops.enable(tp);
4368                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4369         }
4370 }
4371
4372 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4373 {
4374         if (tp->jumbo_ops.disable) {
4375                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4376                 tp->jumbo_ops.disable(tp);
4377                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4378         }
4379 }
4380
4381 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4382 {
4383         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4384         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4385         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4386 }
4387
4388 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4389 {
4390         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4391         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4392         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4393 }
4394
4395 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4396 {
4397         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4398 }
4399
4400 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4401 {
4402         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4403 }
4404
4405 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4406 {
4407         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4408         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4409         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4410         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4411 }
4412
4413 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4414 {
4415         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4416         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4417         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4418         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4419 }
4420
4421 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4422 {
4423         rtl_tx_performance_tweak(tp,
4424                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4425 }
4426
4427 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4428 {
4429         rtl_tx_performance_tweak(tp,
4430                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4431 }
4432
4433 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4434 {
4435         r8168b_0_hw_jumbo_enable(tp);
4436
4437         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4438 }
4439
4440 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4441 {
4442         r8168b_0_hw_jumbo_disable(tp);
4443
4444         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4445 }
4446
4447 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4448 {
4449         struct jumbo_ops *ops = &tp->jumbo_ops;
4450
4451         switch (tp->mac_version) {
4452         case RTL_GIGA_MAC_VER_11:
4453                 ops->disable    = r8168b_0_hw_jumbo_disable;
4454                 ops->enable     = r8168b_0_hw_jumbo_enable;
4455                 break;
4456         case RTL_GIGA_MAC_VER_12:
4457         case RTL_GIGA_MAC_VER_17:
4458                 ops->disable    = r8168b_1_hw_jumbo_disable;
4459                 ops->enable     = r8168b_1_hw_jumbo_enable;
4460                 break;
4461         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4462         case RTL_GIGA_MAC_VER_19:
4463         case RTL_GIGA_MAC_VER_20:
4464         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4465         case RTL_GIGA_MAC_VER_22:
4466         case RTL_GIGA_MAC_VER_23:
4467         case RTL_GIGA_MAC_VER_24:
4468         case RTL_GIGA_MAC_VER_25:
4469         case RTL_GIGA_MAC_VER_26:
4470                 ops->disable    = r8168c_hw_jumbo_disable;
4471                 ops->enable     = r8168c_hw_jumbo_enable;
4472                 break;
4473         case RTL_GIGA_MAC_VER_27:
4474         case RTL_GIGA_MAC_VER_28:
4475                 ops->disable    = r8168dp_hw_jumbo_disable;
4476                 ops->enable     = r8168dp_hw_jumbo_enable;
4477                 break;
4478         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4479         case RTL_GIGA_MAC_VER_32:
4480         case RTL_GIGA_MAC_VER_33:
4481         case RTL_GIGA_MAC_VER_34:
4482                 ops->disable    = r8168e_hw_jumbo_disable;
4483                 ops->enable     = r8168e_hw_jumbo_enable;
4484                 break;
4485
4486         /*
4487          * No action needed for jumbo frames with 8169.
4488          * No jumbo for 810x at all.
4489          */
4490         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4491         default:
4492                 ops->disable    = NULL;
4493                 ops->enable     = NULL;
4494                 break;
4495         }
4496 }
4497
4498 DECLARE_RTL_COND(rtl_chipcmd_cond)
4499 {
4500         return RTL_R8(tp, ChipCmd) & CmdReset;
4501 }
4502
4503 static void rtl_hw_reset(struct rtl8169_private *tp)
4504 {
4505         RTL_W8(tp, ChipCmd, CmdReset);
4506
4507         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4508 }
4509
4510 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4511 {
4512         struct rtl_fw *rtl_fw;
4513         const char *name;
4514         int rc = -ENOMEM;
4515
4516         name = rtl_lookup_firmware_name(tp);
4517         if (!name)
4518                 goto out_no_firmware;
4519
4520         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4521         if (!rtl_fw)
4522                 goto err_warn;
4523
4524         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4525         if (rc < 0)
4526                 goto err_free;
4527
4528         rc = rtl_check_firmware(tp, rtl_fw);
4529         if (rc < 0)
4530                 goto err_release_firmware;
4531
4532         tp->rtl_fw = rtl_fw;
4533 out:
4534         return;
4535
4536 err_release_firmware:
4537         release_firmware(rtl_fw->fw);
4538 err_free:
4539         kfree(rtl_fw);
4540 err_warn:
4541         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4542                    name, rc);
4543 out_no_firmware:
4544         tp->rtl_fw = NULL;
4545         goto out;
4546 }
4547
4548 static void rtl_request_firmware(struct rtl8169_private *tp)
4549 {
4550         if (IS_ERR(tp->rtl_fw))
4551                 rtl_request_uncached_firmware(tp);
4552 }
4553
4554 static void rtl_rx_close(struct rtl8169_private *tp)
4555 {
4556         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4557 }
4558
4559 DECLARE_RTL_COND(rtl_npq_cond)
4560 {
4561         return RTL_R8(tp, TxPoll) & NPQ;
4562 }
4563
4564 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4565 {
4566         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4567 }
4568
4569 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4570 {
4571         /* Disable interrupts */
4572         rtl8169_irq_mask_and_ack(tp);
4573
4574         rtl_rx_close(tp);
4575
4576         switch (tp->mac_version) {
4577         case RTL_GIGA_MAC_VER_27:
4578         case RTL_GIGA_MAC_VER_28:
4579         case RTL_GIGA_MAC_VER_31:
4580                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4581                 break;
4582         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4583         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4584                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4585                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4586                 break;
4587         default:
4588                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4589                 udelay(100);
4590                 break;
4591         }
4592
4593         rtl_hw_reset(tp);
4594 }
4595
4596 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4597 {
4598         /* Set DMA burst size and Interframe Gap Time */
4599         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
4600                 (InterFrameGap << TxInterFrameGapShift));
4601 }
4602
4603 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4604 {
4605         /* Low hurts. Let's disable the filtering. */
4606         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4607 }
4608
4609 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4610 {
4611         /*
4612          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4613          * register to be written before TxDescAddrLow to work.
4614          * Switching from MMIO to I/O access fixes the issue as well.
4615          */
4616         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4617         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4618         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4619         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4620 }
4621
4622 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4623 {
4624         static const struct rtl_cfg2_info {
4625                 u32 mac_version;
4626                 u32 clk;
4627                 u32 val;
4628         } cfg2_info [] = {
4629                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4630                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4631                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4632                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4633         };
4634         const struct rtl_cfg2_info *p = cfg2_info;
4635         unsigned int i;
4636         u32 clk;
4637
4638         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4639         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4640                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4641                         RTL_W32(tp, 0x7c, p->val);
4642                         break;
4643                 }
4644         }
4645 }
4646
4647 static void rtl_set_rx_mode(struct net_device *dev)
4648 {
4649         struct rtl8169_private *tp = netdev_priv(dev);
4650         u32 mc_filter[2];       /* Multicast hash filter */
4651         int rx_mode;
4652         u32 tmp = 0;
4653
4654         if (dev->flags & IFF_PROMISC) {
4655                 /* Unconditionally log net taps. */
4656                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4657                 rx_mode =
4658                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4659                     AcceptAllPhys;
4660                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4661         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4662                    (dev->flags & IFF_ALLMULTI)) {
4663                 /* Too many to filter perfectly -- accept all multicasts. */
4664                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4665                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4666         } else {
4667                 struct netdev_hw_addr *ha;
4668
4669                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4670                 mc_filter[1] = mc_filter[0] = 0;
4671                 netdev_for_each_mc_addr(ha, dev) {
4672                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4673                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4674                         rx_mode |= AcceptMulticast;
4675                 }
4676         }
4677
4678         if (dev->features & NETIF_F_RXALL)
4679                 rx_mode |= (AcceptErr | AcceptRunt);
4680
4681         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4682
4683         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4684                 u32 data = mc_filter[0];
4685
4686                 mc_filter[0] = swab32(mc_filter[1]);
4687                 mc_filter[1] = swab32(data);
4688         }
4689
4690         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4691                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4692
4693         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4694         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4695
4696         RTL_W32(tp, RxConfig, tmp);
4697 }
4698
4699 static void rtl_hw_start(struct  rtl8169_private *tp)
4700 {
4701         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4702
4703         tp->hw_start(tp);
4704
4705         rtl_set_rx_max_size(tp);
4706         rtl_set_rx_tx_desc_registers(tp);
4707         rtl_set_rx_tx_config_registers(tp);
4708         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4709
4710         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4711         RTL_R8(tp, IntrMask);
4712         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4713         rtl_set_rx_mode(tp->dev);
4714         /* no early-rx interrupts */
4715         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4716         rtl_irq_enable_all(tp);
4717 }
4718
4719 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4720 {
4721         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4722                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4723
4724         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4725
4726         tp->cp_cmd |= PCIMulRW;
4727
4728         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4729             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4730                 netif_dbg(tp, drv, tp->dev,
4731                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4732                 tp->cp_cmd |= (1 << 14);
4733         }
4734
4735         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4736
4737         rtl8169_set_magic_reg(tp, tp->mac_version);
4738
4739         /*
4740          * Undocumented corner. Supposedly:
4741          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4742          */
4743         RTL_W16(tp, IntrMitigate, 0x0000);
4744
4745         RTL_W32(tp, RxMissed, 0);
4746 }
4747
4748 DECLARE_RTL_COND(rtl_csiar_cond)
4749 {
4750         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4751 }
4752
4753 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4754 {
4755         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4756
4757         RTL_W32(tp, CSIDR, value);
4758         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4759                 CSIAR_BYTE_ENABLE | func << 16);
4760
4761         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4762 }
4763
4764 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4765 {
4766         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4767
4768         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4769                 CSIAR_BYTE_ENABLE);
4770
4771         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4772                 RTL_R32(tp, CSIDR) : ~0;
4773 }
4774
4775 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4776 {
4777         struct pci_dev *pdev = tp->pci_dev;
4778         u32 csi;
4779
4780         /* According to Realtek the value at config space address 0x070f
4781          * controls the L0s/L1 entrance latency. We try standard ECAM access
4782          * first and if it fails fall back to CSI.
4783          */
4784         if (pdev->cfg_size > 0x070f &&
4785             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4786                 return;
4787
4788         netdev_notice_once(tp->dev,
4789                 "No native access to PCI extended config space, falling back to CSI\n");
4790         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4791         rtl_csi_write(tp, 0x070c, csi | val << 24);
4792 }
4793
4794 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4795 {
4796         rtl_csi_access_enable(tp, 0x27);
4797 }
4798
4799 struct ephy_info {
4800         unsigned int offset;
4801         u16 mask;
4802         u16 bits;
4803 };
4804
4805 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4806                           int len)
4807 {
4808         u16 w;
4809
4810         while (len-- > 0) {
4811                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4812                 rtl_ephy_write(tp, e->offset, w);
4813                 e++;
4814         }
4815 }
4816
4817 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4818 {
4819         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4820                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4821 }
4822
4823 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4824 {
4825         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4826                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4827 }
4828
4829 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4830 {
4831         u8 data;
4832
4833         data = RTL_R8(tp, Config3);
4834
4835         if (enable)
4836                 data |= Rdy_to_L23;
4837         else
4838                 data &= ~Rdy_to_L23;
4839
4840         RTL_W8(tp, Config3, data);
4841 }
4842
4843 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4844 {
4845         if (enable) {
4846                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4847                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4848         } else {
4849                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4850                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4851         }
4852 }
4853
4854 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4855 {
4856         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4857
4858         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4859         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4860
4861         if (tp->dev->mtu <= ETH_DATA_LEN) {
4862                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4863                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4864         }
4865 }
4866
4867 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4868 {
4869         rtl_hw_start_8168bb(tp);
4870
4871         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4872
4873         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4874 }
4875
4876 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4877 {
4878         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4879
4880         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4881
4882         if (tp->dev->mtu <= ETH_DATA_LEN)
4883                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4884
4885         rtl_disable_clock_request(tp);
4886
4887         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4888         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4889 }
4890
4891 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4892 {
4893         static const struct ephy_info e_info_8168cp[] = {
4894                 { 0x01, 0,      0x0001 },
4895                 { 0x02, 0x0800, 0x1000 },
4896                 { 0x03, 0,      0x0042 },
4897                 { 0x06, 0x0080, 0x0000 },
4898                 { 0x07, 0,      0x2000 }
4899         };
4900
4901         rtl_set_def_aspm_entry_latency(tp);
4902
4903         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4904
4905         __rtl_hw_start_8168cp(tp);
4906 }
4907
4908 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4909 {
4910         rtl_set_def_aspm_entry_latency(tp);
4911
4912         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4913
4914         if (tp->dev->mtu <= ETH_DATA_LEN)
4915                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4916
4917         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4918         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4919 }
4920
4921 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4922 {
4923         rtl_set_def_aspm_entry_latency(tp);
4924
4925         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4926
4927         /* Magic. */
4928         RTL_W8(tp, DBG_REG, 0x20);
4929
4930         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4931
4932         if (tp->dev->mtu <= ETH_DATA_LEN)
4933                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4934
4935         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4936         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4937 }
4938
4939 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4940 {
4941         static const struct ephy_info e_info_8168c_1[] = {
4942                 { 0x02, 0x0800, 0x1000 },
4943                 { 0x03, 0,      0x0002 },
4944                 { 0x06, 0x0080, 0x0000 }
4945         };
4946
4947         rtl_set_def_aspm_entry_latency(tp);
4948
4949         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4950
4951         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4952
4953         __rtl_hw_start_8168cp(tp);
4954 }
4955
4956 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4957 {
4958         static const struct ephy_info e_info_8168c_2[] = {
4959                 { 0x01, 0,      0x0001 },
4960                 { 0x03, 0x0400, 0x0220 }
4961         };
4962
4963         rtl_set_def_aspm_entry_latency(tp);
4964
4965         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4966
4967         __rtl_hw_start_8168cp(tp);
4968 }
4969
4970 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4971 {
4972         rtl_hw_start_8168c_2(tp);
4973 }
4974
4975 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4976 {
4977         rtl_set_def_aspm_entry_latency(tp);
4978
4979         __rtl_hw_start_8168cp(tp);
4980 }
4981
4982 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4983 {
4984         rtl_set_def_aspm_entry_latency(tp);
4985
4986         rtl_disable_clock_request(tp);
4987
4988         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4989
4990         if (tp->dev->mtu <= ETH_DATA_LEN)
4991                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4992
4993         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4994         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4995 }
4996
4997 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4998 {
4999         rtl_set_def_aspm_entry_latency(tp);
5000
5001         if (tp->dev->mtu <= ETH_DATA_LEN)
5002                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5003
5004         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5005
5006         rtl_disable_clock_request(tp);
5007 }
5008
5009 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5010 {
5011         static const struct ephy_info e_info_8168d_4[] = {
5012                 { 0x0b, 0x0000, 0x0048 },
5013                 { 0x19, 0x0020, 0x0050 },
5014                 { 0x0c, 0x0100, 0x0020 }
5015         };
5016
5017         rtl_set_def_aspm_entry_latency(tp);
5018
5019         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5020
5021         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5022
5023         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5024
5025         rtl_enable_clock_request(tp);
5026 }
5027
5028 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5029 {
5030         static const struct ephy_info e_info_8168e_1[] = {
5031                 { 0x00, 0x0200, 0x0100 },
5032                 { 0x00, 0x0000, 0x0004 },
5033                 { 0x06, 0x0002, 0x0001 },
5034                 { 0x06, 0x0000, 0x0030 },
5035                 { 0x07, 0x0000, 0x2000 },
5036                 { 0x00, 0x0000, 0x0020 },
5037                 { 0x03, 0x5800, 0x2000 },
5038                 { 0x03, 0x0000, 0x0001 },
5039                 { 0x01, 0x0800, 0x1000 },
5040                 { 0x07, 0x0000, 0x4000 },
5041                 { 0x1e, 0x0000, 0x2000 },
5042                 { 0x19, 0xffff, 0xfe6c },
5043                 { 0x0a, 0x0000, 0x0040 }
5044         };
5045
5046         rtl_set_def_aspm_entry_latency(tp);
5047
5048         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5049
5050         if (tp->dev->mtu <= ETH_DATA_LEN)
5051                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5052
5053         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5054
5055         rtl_disable_clock_request(tp);
5056
5057         /* Reset tx FIFO pointer */
5058         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5059         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5060
5061         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5062 }
5063
5064 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5065 {
5066         static const struct ephy_info e_info_8168e_2[] = {
5067                 { 0x09, 0x0000, 0x0080 },
5068                 { 0x19, 0x0000, 0x0224 }
5069         };
5070
5071         rtl_set_def_aspm_entry_latency(tp);
5072
5073         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5074
5075         if (tp->dev->mtu <= ETH_DATA_LEN)
5076                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5077
5078         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5079         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5080         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5081         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5082         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5083         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5084         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5085         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5086
5087         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5088
5089         rtl_disable_clock_request(tp);
5090
5091         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5092         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5093
5094         /* Adjust EEE LED frequency */
5095         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5096
5097         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5098         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5099         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5100
5101         rtl_hw_aspm_clkreq_enable(tp, true);
5102 }
5103
5104 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5105 {
5106         rtl_set_def_aspm_entry_latency(tp);
5107
5108         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5109
5110         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5111         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5112         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5113         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5114         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5115         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5116         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5117         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5118         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5119         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5120
5121         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5122
5123         rtl_disable_clock_request(tp);
5124
5125         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5126         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5127         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5128         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5129         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5130 }
5131
5132 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5133 {
5134         static const struct ephy_info e_info_8168f_1[] = {
5135                 { 0x06, 0x00c0, 0x0020 },
5136                 { 0x08, 0x0001, 0x0002 },
5137                 { 0x09, 0x0000, 0x0080 },
5138                 { 0x19, 0x0000, 0x0224 }
5139         };
5140
5141         rtl_hw_start_8168f(tp);
5142
5143         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5144
5145         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5146
5147         /* Adjust EEE LED frequency */
5148         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5149 }
5150
5151 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5152 {
5153         static const struct ephy_info e_info_8168f_1[] = {
5154                 { 0x06, 0x00c0, 0x0020 },
5155                 { 0x0f, 0xffff, 0x5200 },
5156                 { 0x1e, 0x0000, 0x4000 },
5157                 { 0x19, 0x0000, 0x0224 }
5158         };
5159
5160         rtl_hw_start_8168f(tp);
5161         rtl_pcie_state_l2l3_enable(tp, false);
5162
5163         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5164
5165         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5166 }
5167
5168 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5169 {
5170         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5171
5172         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5173         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5174         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5175         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5176
5177         rtl_set_def_aspm_entry_latency(tp);
5178
5179         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5180
5181         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5182         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5183         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5184
5185         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5186         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5187
5188         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5189         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5190
5191         /* Adjust EEE LED frequency */
5192         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5193
5194         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5195         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5196
5197         rtl_pcie_state_l2l3_enable(tp, false);
5198 }
5199
5200 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5201 {
5202         static const struct ephy_info e_info_8168g_1[] = {
5203                 { 0x00, 0x0000, 0x0008 },
5204                 { 0x0c, 0x37d0, 0x0820 },
5205                 { 0x1e, 0x0000, 0x0001 },
5206                 { 0x19, 0x8000, 0x0000 }
5207         };
5208
5209         rtl_hw_start_8168g(tp);
5210
5211         /* disable aspm and clock request before access ephy */
5212         rtl_hw_aspm_clkreq_enable(tp, false);
5213         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5214         rtl_hw_aspm_clkreq_enable(tp, true);
5215 }
5216
5217 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5218 {
5219         static const struct ephy_info e_info_8168g_2[] = {
5220                 { 0x00, 0x0000, 0x0008 },
5221                 { 0x0c, 0x3df0, 0x0200 },
5222                 { 0x19, 0xffff, 0xfc00 },
5223                 { 0x1e, 0xffff, 0x20eb }
5224         };
5225
5226         rtl_hw_start_8168g(tp);
5227
5228         /* disable aspm and clock request before access ephy */
5229         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5230         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5231         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5232 }
5233
5234 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5235 {
5236         static const struct ephy_info e_info_8411_2[] = {
5237                 { 0x00, 0x0000, 0x0008 },
5238                 { 0x0c, 0x3df0, 0x0200 },
5239                 { 0x0f, 0xffff, 0x5200 },
5240                 { 0x19, 0x0020, 0x0000 },
5241                 { 0x1e, 0x0000, 0x2000 }
5242         };
5243
5244         rtl_hw_start_8168g(tp);
5245
5246         /* disable aspm and clock request before access ephy */
5247         rtl_hw_aspm_clkreq_enable(tp, false);
5248         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5249         rtl_hw_aspm_clkreq_enable(tp, true);
5250 }
5251
5252 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5253 {
5254         int rg_saw_cnt;
5255         u32 data;
5256         static const struct ephy_info e_info_8168h_1[] = {
5257                 { 0x1e, 0x0800, 0x0001 },
5258                 { 0x1d, 0x0000, 0x0800 },
5259                 { 0x05, 0xffff, 0x2089 },
5260                 { 0x06, 0xffff, 0x5881 },
5261                 { 0x04, 0xffff, 0x154a },
5262                 { 0x01, 0xffff, 0x068b }
5263         };
5264
5265         /* disable aspm and clock request before access ephy */
5266         rtl_hw_aspm_clkreq_enable(tp, false);
5267         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5268
5269         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5270
5271         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5272         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5273         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5274         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5275
5276         rtl_set_def_aspm_entry_latency(tp);
5277
5278         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5279
5280         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5281         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5282
5283         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5284
5285         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5286
5287         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5288
5289         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5290         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5291
5292         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5293         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5294
5295         /* Adjust EEE LED frequency */
5296         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5297
5298         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5299         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5300
5301         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5302
5303         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5304
5305         rtl_pcie_state_l2l3_enable(tp, false);
5306
5307         rtl_writephy(tp, 0x1f, 0x0c42);
5308         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5309         rtl_writephy(tp, 0x1f, 0x0000);
5310         if (rg_saw_cnt > 0) {
5311                 u16 sw_cnt_1ms_ini;
5312
5313                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5314                 sw_cnt_1ms_ini &= 0x0fff;
5315                 data = r8168_mac_ocp_read(tp, 0xd412);
5316                 data &= ~0x0fff;
5317                 data |= sw_cnt_1ms_ini;
5318                 r8168_mac_ocp_write(tp, 0xd412, data);
5319         }
5320
5321         data = r8168_mac_ocp_read(tp, 0xe056);
5322         data &= ~0xf0;
5323         data |= 0x70;
5324         r8168_mac_ocp_write(tp, 0xe056, data);
5325
5326         data = r8168_mac_ocp_read(tp, 0xe052);
5327         data &= ~0x6000;
5328         data |= 0x8008;
5329         r8168_mac_ocp_write(tp, 0xe052, data);
5330
5331         data = r8168_mac_ocp_read(tp, 0xe0d6);
5332         data &= ~0x01ff;
5333         data |= 0x017f;
5334         r8168_mac_ocp_write(tp, 0xe0d6, data);
5335
5336         data = r8168_mac_ocp_read(tp, 0xd420);
5337         data &= ~0x0fff;
5338         data |= 0x047f;
5339         r8168_mac_ocp_write(tp, 0xd420, data);
5340
5341         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5342         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5343         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5344         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5345
5346         rtl_hw_aspm_clkreq_enable(tp, true);
5347 }
5348
5349 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5350 {
5351         rtl8168ep_stop_cmac(tp);
5352
5353         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5354
5355         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5356         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5357         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5358         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5359
5360         rtl_set_def_aspm_entry_latency(tp);
5361
5362         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5363
5364         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5365         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5366
5367         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5368
5369         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5370
5371         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5372         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5373
5374         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5375         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5376
5377         /* Adjust EEE LED frequency */
5378         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5379
5380         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5381
5382         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5383
5384         rtl_pcie_state_l2l3_enable(tp, false);
5385 }
5386
5387 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5388 {
5389         static const struct ephy_info e_info_8168ep_1[] = {
5390                 { 0x00, 0xffff, 0x10ab },
5391                 { 0x06, 0xffff, 0xf030 },
5392                 { 0x08, 0xffff, 0x2006 },
5393                 { 0x0d, 0xffff, 0x1666 },
5394                 { 0x0c, 0x3ff0, 0x0000 }
5395         };
5396
5397         /* disable aspm and clock request before access ephy */
5398         rtl_hw_aspm_clkreq_enable(tp, false);
5399         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5400
5401         rtl_hw_start_8168ep(tp);
5402
5403         rtl_hw_aspm_clkreq_enable(tp, true);
5404 }
5405
5406 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5407 {
5408         static const struct ephy_info e_info_8168ep_2[] = {
5409                 { 0x00, 0xffff, 0x10a3 },
5410                 { 0x19, 0xffff, 0xfc00 },
5411                 { 0x1e, 0xffff, 0x20ea }
5412         };
5413
5414         /* disable aspm and clock request before access ephy */
5415         rtl_hw_aspm_clkreq_enable(tp, false);
5416         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5417
5418         rtl_hw_start_8168ep(tp);
5419
5420         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5421         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5422
5423         rtl_hw_aspm_clkreq_enable(tp, true);
5424 }
5425
5426 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5427 {
5428         u32 data;
5429         static const struct ephy_info e_info_8168ep_3[] = {
5430                 { 0x00, 0xffff, 0x10a3 },
5431                 { 0x19, 0xffff, 0x7c00 },
5432                 { 0x1e, 0xffff, 0x20eb },
5433                 { 0x0d, 0xffff, 0x1666 }
5434         };
5435
5436         /* disable aspm and clock request before access ephy */
5437         rtl_hw_aspm_clkreq_enable(tp, false);
5438         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5439
5440         rtl_hw_start_8168ep(tp);
5441
5442         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5443         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5444
5445         data = r8168_mac_ocp_read(tp, 0xd3e2);
5446         data &= 0xf000;
5447         data |= 0x0271;
5448         r8168_mac_ocp_write(tp, 0xd3e2, data);
5449
5450         data = r8168_mac_ocp_read(tp, 0xd3e4);
5451         data &= 0xff00;
5452         r8168_mac_ocp_write(tp, 0xd3e4, data);
5453
5454         data = r8168_mac_ocp_read(tp, 0xe860);
5455         data |= 0x0080;
5456         r8168_mac_ocp_write(tp, 0xe860, data);
5457
5458         rtl_hw_aspm_clkreq_enable(tp, true);
5459 }
5460
5461 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5462 {
5463         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5464
5465         tp->cp_cmd &= ~INTT_MASK;
5466         tp->cp_cmd |= PktCntrDisable | INTT_1;
5467         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5468
5469         RTL_W16(tp, IntrMitigate, 0x5151);
5470
5471         /* Work around for RxFIFO overflow. */
5472         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5473                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5474                 tp->event_slow &= ~RxOverflow;
5475         }
5476
5477         switch (tp->mac_version) {
5478         case RTL_GIGA_MAC_VER_11:
5479                 rtl_hw_start_8168bb(tp);
5480                 break;
5481
5482         case RTL_GIGA_MAC_VER_12:
5483         case RTL_GIGA_MAC_VER_17:
5484                 rtl_hw_start_8168bef(tp);
5485                 break;
5486
5487         case RTL_GIGA_MAC_VER_18:
5488                 rtl_hw_start_8168cp_1(tp);
5489                 break;
5490
5491         case RTL_GIGA_MAC_VER_19:
5492                 rtl_hw_start_8168c_1(tp);
5493                 break;
5494
5495         case RTL_GIGA_MAC_VER_20:
5496                 rtl_hw_start_8168c_2(tp);
5497                 break;
5498
5499         case RTL_GIGA_MAC_VER_21:
5500                 rtl_hw_start_8168c_3(tp);
5501                 break;
5502
5503         case RTL_GIGA_MAC_VER_22:
5504                 rtl_hw_start_8168c_4(tp);
5505                 break;
5506
5507         case RTL_GIGA_MAC_VER_23:
5508                 rtl_hw_start_8168cp_2(tp);
5509                 break;
5510
5511         case RTL_GIGA_MAC_VER_24:
5512                 rtl_hw_start_8168cp_3(tp);
5513                 break;
5514
5515         case RTL_GIGA_MAC_VER_25:
5516         case RTL_GIGA_MAC_VER_26:
5517         case RTL_GIGA_MAC_VER_27:
5518                 rtl_hw_start_8168d(tp);
5519                 break;
5520
5521         case RTL_GIGA_MAC_VER_28:
5522                 rtl_hw_start_8168d_4(tp);
5523                 break;
5524
5525         case RTL_GIGA_MAC_VER_31:
5526                 rtl_hw_start_8168dp(tp);
5527                 break;
5528
5529         case RTL_GIGA_MAC_VER_32:
5530         case RTL_GIGA_MAC_VER_33:
5531                 rtl_hw_start_8168e_1(tp);
5532                 break;
5533         case RTL_GIGA_MAC_VER_34:
5534                 rtl_hw_start_8168e_2(tp);
5535                 break;
5536
5537         case RTL_GIGA_MAC_VER_35:
5538         case RTL_GIGA_MAC_VER_36:
5539                 rtl_hw_start_8168f_1(tp);
5540                 break;
5541
5542         case RTL_GIGA_MAC_VER_38:
5543                 rtl_hw_start_8411(tp);
5544                 break;
5545
5546         case RTL_GIGA_MAC_VER_40:
5547         case RTL_GIGA_MAC_VER_41:
5548                 rtl_hw_start_8168g_1(tp);
5549                 break;
5550         case RTL_GIGA_MAC_VER_42:
5551                 rtl_hw_start_8168g_2(tp);
5552                 break;
5553
5554         case RTL_GIGA_MAC_VER_44:
5555                 rtl_hw_start_8411_2(tp);
5556                 break;
5557
5558         case RTL_GIGA_MAC_VER_45:
5559         case RTL_GIGA_MAC_VER_46:
5560                 rtl_hw_start_8168h_1(tp);
5561                 break;
5562
5563         case RTL_GIGA_MAC_VER_49:
5564                 rtl_hw_start_8168ep_1(tp);
5565                 break;
5566
5567         case RTL_GIGA_MAC_VER_50:
5568                 rtl_hw_start_8168ep_2(tp);
5569                 break;
5570
5571         case RTL_GIGA_MAC_VER_51:
5572                 rtl_hw_start_8168ep_3(tp);
5573                 break;
5574
5575         default:
5576                 netif_err(tp, drv, tp->dev,
5577                           "unknown chipset (mac_version = %d)\n",
5578                           tp->mac_version);
5579                 break;
5580         }
5581 }
5582
5583 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5584 {
5585         static const struct ephy_info e_info_8102e_1[] = {
5586                 { 0x01, 0, 0x6e65 },
5587                 { 0x02, 0, 0x091f },
5588                 { 0x03, 0, 0xc2f9 },
5589                 { 0x06, 0, 0xafb5 },
5590                 { 0x07, 0, 0x0e00 },
5591                 { 0x19, 0, 0xec80 },
5592                 { 0x01, 0, 0x2e65 },
5593                 { 0x01, 0, 0x6e65 }
5594         };
5595         u8 cfg1;
5596
5597         rtl_set_def_aspm_entry_latency(tp);
5598
5599         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5600
5601         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5602
5603         RTL_W8(tp, Config1,
5604                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5605         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5606
5607         cfg1 = RTL_R8(tp, Config1);
5608         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5609                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5610
5611         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5612 }
5613
5614 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5615 {
5616         rtl_set_def_aspm_entry_latency(tp);
5617
5618         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5619
5620         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5621         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5622 }
5623
5624 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5625 {
5626         rtl_hw_start_8102e_2(tp);
5627
5628         rtl_ephy_write(tp, 0x03, 0xc2f9);
5629 }
5630
5631 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5632 {
5633         static const struct ephy_info e_info_8105e_1[] = {
5634                 { 0x07, 0, 0x4000 },
5635                 { 0x19, 0, 0x0200 },
5636                 { 0x19, 0, 0x0020 },
5637                 { 0x1e, 0, 0x2000 },
5638                 { 0x03, 0, 0x0001 },
5639                 { 0x19, 0, 0x0100 },
5640                 { 0x19, 0, 0x0004 },
5641                 { 0x0a, 0, 0x0020 }
5642         };
5643
5644         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5645         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5646
5647         /* Disable Early Tally Counter */
5648         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5649
5650         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5651         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5652
5653         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5654
5655         rtl_pcie_state_l2l3_enable(tp, false);
5656 }
5657
5658 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5659 {
5660         rtl_hw_start_8105e_1(tp);
5661         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5662 }
5663
5664 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5665 {
5666         static const struct ephy_info e_info_8402[] = {
5667                 { 0x19, 0xffff, 0xff64 },
5668                 { 0x1e, 0, 0x4000 }
5669         };
5670
5671         rtl_set_def_aspm_entry_latency(tp);
5672
5673         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5674         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5675
5676         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5677         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5678
5679         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5680
5681         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5682
5683         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5684         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5685         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5686         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5687         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5688         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5689         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5690
5691         rtl_pcie_state_l2l3_enable(tp, false);
5692 }
5693
5694 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5695 {
5696         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5697         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5698
5699         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5700         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5701         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5702
5703         rtl_pcie_state_l2l3_enable(tp, false);
5704 }
5705
5706 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5707 {
5708         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5709                 tp->event_slow &= ~RxFIFOOver;
5710
5711         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5712             tp->mac_version == RTL_GIGA_MAC_VER_16)
5713                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5714                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5715
5716         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5717
5718         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5719         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5720
5721         switch (tp->mac_version) {
5722         case RTL_GIGA_MAC_VER_07:
5723                 rtl_hw_start_8102e_1(tp);
5724                 break;
5725
5726         case RTL_GIGA_MAC_VER_08:
5727                 rtl_hw_start_8102e_3(tp);
5728                 break;
5729
5730         case RTL_GIGA_MAC_VER_09:
5731                 rtl_hw_start_8102e_2(tp);
5732                 break;
5733
5734         case RTL_GIGA_MAC_VER_29:
5735                 rtl_hw_start_8105e_1(tp);
5736                 break;
5737         case RTL_GIGA_MAC_VER_30:
5738                 rtl_hw_start_8105e_2(tp);
5739                 break;
5740
5741         case RTL_GIGA_MAC_VER_37:
5742                 rtl_hw_start_8402(tp);
5743                 break;
5744
5745         case RTL_GIGA_MAC_VER_39:
5746                 rtl_hw_start_8106(tp);
5747                 break;
5748         case RTL_GIGA_MAC_VER_43:
5749                 rtl_hw_start_8168g_2(tp);
5750                 break;
5751         case RTL_GIGA_MAC_VER_47:
5752         case RTL_GIGA_MAC_VER_48:
5753                 rtl_hw_start_8168h_1(tp);
5754                 break;
5755         }
5756
5757         RTL_W16(tp, IntrMitigate, 0x0000);
5758 }
5759
5760 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5761 {
5762         struct rtl8169_private *tp = netdev_priv(dev);
5763
5764         if (new_mtu > ETH_DATA_LEN)
5765                 rtl_hw_jumbo_enable(tp);
5766         else
5767                 rtl_hw_jumbo_disable(tp);
5768
5769         dev->mtu = new_mtu;
5770         netdev_update_features(dev);
5771
5772         return 0;
5773 }
5774
5775 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5776 {
5777         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5778         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5779 }
5780
5781 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5782                                      void **data_buff, struct RxDesc *desc)
5783 {
5784         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5785                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5786
5787         kfree(*data_buff);
5788         *data_buff = NULL;
5789         rtl8169_make_unusable_by_asic(desc);
5790 }
5791
5792 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5793 {
5794         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5795
5796         /* Force memory writes to complete before releasing descriptor */
5797         dma_wmb();
5798
5799         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5800 }
5801
5802 static inline void *rtl8169_align(void *data)
5803 {
5804         return (void *)ALIGN((long)data, 16);
5805 }
5806
5807 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5808                                              struct RxDesc *desc)
5809 {
5810         void *data;
5811         dma_addr_t mapping;
5812         struct device *d = tp_to_dev(tp);
5813         int node = dev_to_node(d);
5814
5815         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5816         if (!data)
5817                 return NULL;
5818
5819         if (rtl8169_align(data) != data) {
5820                 kfree(data);
5821                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5822                 if (!data)
5823                         return NULL;
5824         }
5825
5826         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5827                                  DMA_FROM_DEVICE);
5828         if (unlikely(dma_mapping_error(d, mapping))) {
5829                 if (net_ratelimit())
5830                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5831                 goto err_out;
5832         }
5833
5834         desc->addr = cpu_to_le64(mapping);
5835         rtl8169_mark_to_asic(desc);
5836         return data;
5837
5838 err_out:
5839         kfree(data);
5840         return NULL;
5841 }
5842
5843 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5844 {
5845         unsigned int i;
5846
5847         for (i = 0; i < NUM_RX_DESC; i++) {
5848                 if (tp->Rx_databuff[i]) {
5849                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5850                                             tp->RxDescArray + i);
5851                 }
5852         }
5853 }
5854
5855 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5856 {
5857         desc->opts1 |= cpu_to_le32(RingEnd);
5858 }
5859
5860 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5861 {
5862         unsigned int i;
5863
5864         for (i = 0; i < NUM_RX_DESC; i++) {
5865                 void *data;
5866
5867                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5868                 if (!data) {
5869                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5870                         goto err_out;
5871                 }
5872                 tp->Rx_databuff[i] = data;
5873         }
5874
5875         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5876         return 0;
5877
5878 err_out:
5879         rtl8169_rx_clear(tp);
5880         return -ENOMEM;
5881 }
5882
5883 static int rtl8169_init_ring(struct rtl8169_private *tp)
5884 {
5885         rtl8169_init_ring_indexes(tp);
5886
5887         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5888         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5889
5890         return rtl8169_rx_fill(tp);
5891 }
5892
5893 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5894                                  struct TxDesc *desc)
5895 {
5896         unsigned int len = tx_skb->len;
5897
5898         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5899
5900         desc->opts1 = 0x00;
5901         desc->opts2 = 0x00;
5902         desc->addr = 0x00;
5903         tx_skb->len = 0;
5904 }
5905
5906 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5907                                    unsigned int n)
5908 {
5909         unsigned int i;
5910
5911         for (i = 0; i < n; i++) {
5912                 unsigned int entry = (start + i) % NUM_TX_DESC;
5913                 struct ring_info *tx_skb = tp->tx_skb + entry;
5914                 unsigned int len = tx_skb->len;
5915
5916                 if (len) {
5917                         struct sk_buff *skb = tx_skb->skb;
5918
5919                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5920                                              tp->TxDescArray + entry);
5921                         if (skb) {
5922                                 dev_consume_skb_any(skb);
5923                                 tx_skb->skb = NULL;
5924                         }
5925                 }
5926         }
5927 }
5928
5929 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5930 {
5931         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5932         tp->cur_tx = tp->dirty_tx = 0;
5933 }
5934
5935 static void rtl_reset_work(struct rtl8169_private *tp)
5936 {
5937         struct net_device *dev = tp->dev;
5938         int i;
5939
5940         napi_disable(&tp->napi);
5941         netif_stop_queue(dev);
5942         synchronize_sched();
5943
5944         rtl8169_hw_reset(tp);
5945
5946         for (i = 0; i < NUM_RX_DESC; i++)
5947                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5948
5949         rtl8169_tx_clear(tp);
5950         rtl8169_init_ring_indexes(tp);
5951
5952         napi_enable(&tp->napi);
5953         rtl_hw_start(tp);
5954         netif_wake_queue(dev);
5955 }
5956
5957 static void rtl8169_tx_timeout(struct net_device *dev)
5958 {
5959         struct rtl8169_private *tp = netdev_priv(dev);
5960
5961         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5962 }
5963
5964 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5965                               u32 *opts)
5966 {
5967         struct skb_shared_info *info = skb_shinfo(skb);
5968         unsigned int cur_frag, entry;
5969         struct TxDesc *uninitialized_var(txd);
5970         struct device *d = tp_to_dev(tp);
5971
5972         entry = tp->cur_tx;
5973         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5974                 const skb_frag_t *frag = info->frags + cur_frag;
5975                 dma_addr_t mapping;
5976                 u32 status, len;
5977                 void *addr;
5978
5979                 entry = (entry + 1) % NUM_TX_DESC;
5980
5981                 txd = tp->TxDescArray + entry;
5982                 len = skb_frag_size(frag);
5983                 addr = skb_frag_address(frag);
5984                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5985                 if (unlikely(dma_mapping_error(d, mapping))) {
5986                         if (net_ratelimit())
5987                                 netif_err(tp, drv, tp->dev,
5988                                           "Failed to map TX fragments DMA!\n");
5989                         goto err_out;
5990                 }
5991
5992                 /* Anti gcc 2.95.3 bugware (sic) */
5993                 status = opts[0] | len |
5994                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5995
5996                 txd->opts1 = cpu_to_le32(status);
5997                 txd->opts2 = cpu_to_le32(opts[1]);
5998                 txd->addr = cpu_to_le64(mapping);
5999
6000                 tp->tx_skb[entry].len = len;
6001         }
6002
6003         if (cur_frag) {
6004                 tp->tx_skb[entry].skb = skb;
6005                 txd->opts1 |= cpu_to_le32(LastFrag);
6006         }
6007
6008         return cur_frag;
6009
6010 err_out:
6011         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6012         return -EIO;
6013 }
6014
6015 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6016 {
6017         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6018 }
6019
6020 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6021                                       struct net_device *dev);
6022 /* r8169_csum_workaround()
6023  * The hw limites the value the transport offset. When the offset is out of the
6024  * range, calculate the checksum by sw.
6025  */
6026 static void r8169_csum_workaround(struct rtl8169_private *tp,
6027                                   struct sk_buff *skb)
6028 {
6029         if (skb_shinfo(skb)->gso_size) {
6030                 netdev_features_t features = tp->dev->features;
6031                 struct sk_buff *segs, *nskb;
6032
6033                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6034                 segs = skb_gso_segment(skb, features);
6035                 if (IS_ERR(segs) || !segs)
6036                         goto drop;
6037
6038                 do {
6039                         nskb = segs;
6040                         segs = segs->next;
6041                         nskb->next = NULL;
6042                         rtl8169_start_xmit(nskb, tp->dev);
6043                 } while (segs);
6044
6045                 dev_consume_skb_any(skb);
6046         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6047                 if (skb_checksum_help(skb) < 0)
6048                         goto drop;
6049
6050                 rtl8169_start_xmit(skb, tp->dev);
6051         } else {
6052                 struct net_device_stats *stats;
6053
6054 drop:
6055                 stats = &tp->dev->stats;
6056                 stats->tx_dropped++;
6057                 dev_kfree_skb_any(skb);
6058         }
6059 }
6060
6061 /* msdn_giant_send_check()
6062  * According to the document of microsoft, the TCP Pseudo Header excludes the
6063  * packet length for IPv6 TCP large packets.
6064  */
6065 static int msdn_giant_send_check(struct sk_buff *skb)
6066 {
6067         const struct ipv6hdr *ipv6h;
6068         struct tcphdr *th;
6069         int ret;
6070
6071         ret = skb_cow_head(skb, 0);
6072         if (ret)
6073                 return ret;
6074
6075         ipv6h = ipv6_hdr(skb);
6076         th = tcp_hdr(skb);
6077
6078         th->check = 0;
6079         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6080
6081         return ret;
6082 }
6083
6084 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6085                                 struct sk_buff *skb, u32 *opts)
6086 {
6087         u32 mss = skb_shinfo(skb)->gso_size;
6088
6089         if (mss) {
6090                 opts[0] |= TD_LSO;
6091                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6092         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6093                 const struct iphdr *ip = ip_hdr(skb);
6094
6095                 if (ip->protocol == IPPROTO_TCP)
6096                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6097                 else if (ip->protocol == IPPROTO_UDP)
6098                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6099                 else
6100                         WARN_ON_ONCE(1);
6101         }
6102
6103         return true;
6104 }
6105
6106 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6107                                 struct sk_buff *skb, u32 *opts)
6108 {
6109         u32 transport_offset = (u32)skb_transport_offset(skb);
6110         u32 mss = skb_shinfo(skb)->gso_size;
6111
6112         if (mss) {
6113                 if (transport_offset > GTTCPHO_MAX) {
6114                         netif_warn(tp, tx_err, tp->dev,
6115                                    "Invalid transport offset 0x%x for TSO\n",
6116                                    transport_offset);
6117                         return false;
6118                 }
6119
6120                 switch (vlan_get_protocol(skb)) {
6121                 case htons(ETH_P_IP):
6122                         opts[0] |= TD1_GTSENV4;
6123                         break;
6124
6125                 case htons(ETH_P_IPV6):
6126                         if (msdn_giant_send_check(skb))
6127                                 return false;
6128
6129                         opts[0] |= TD1_GTSENV6;
6130                         break;
6131
6132                 default:
6133                         WARN_ON_ONCE(1);
6134                         break;
6135                 }
6136
6137                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6138                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6139         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6140                 u8 ip_protocol;
6141
6142                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6143                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6144
6145                 if (transport_offset > TCPHO_MAX) {
6146                         netif_warn(tp, tx_err, tp->dev,
6147                                    "Invalid transport offset 0x%x\n",
6148                                    transport_offset);
6149                         return false;
6150                 }
6151
6152                 switch (vlan_get_protocol(skb)) {
6153                 case htons(ETH_P_IP):
6154                         opts[1] |= TD1_IPv4_CS;
6155                         ip_protocol = ip_hdr(skb)->protocol;
6156                         break;
6157
6158                 case htons(ETH_P_IPV6):
6159                         opts[1] |= TD1_IPv6_CS;
6160                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6161                         break;
6162
6163                 default:
6164                         ip_protocol = IPPROTO_RAW;
6165                         break;
6166                 }
6167
6168                 if (ip_protocol == IPPROTO_TCP)
6169                         opts[1] |= TD1_TCP_CS;
6170                 else if (ip_protocol == IPPROTO_UDP)
6171                         opts[1] |= TD1_UDP_CS;
6172                 else
6173                         WARN_ON_ONCE(1);
6174
6175                 opts[1] |= transport_offset << TCPHO_SHIFT;
6176         } else {
6177                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6178                         return !eth_skb_pad(skb);
6179         }
6180
6181         return true;
6182 }
6183
6184 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6185                                       struct net_device *dev)
6186 {
6187         struct rtl8169_private *tp = netdev_priv(dev);
6188         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6189         struct TxDesc *txd = tp->TxDescArray + entry;
6190         struct device *d = tp_to_dev(tp);
6191         dma_addr_t mapping;
6192         u32 status, len;
6193         u32 opts[2];
6194         int frags;
6195
6196         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6197                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6198                 goto err_stop_0;
6199         }
6200
6201         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6202                 goto err_stop_0;
6203
6204         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6205         opts[0] = DescOwn;
6206
6207         if (!tp->tso_csum(tp, skb, opts)) {
6208                 r8169_csum_workaround(tp, skb);
6209                 return NETDEV_TX_OK;
6210         }
6211
6212         len = skb_headlen(skb);
6213         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6214         if (unlikely(dma_mapping_error(d, mapping))) {
6215                 if (net_ratelimit())
6216                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6217                 goto err_dma_0;
6218         }
6219
6220         tp->tx_skb[entry].len = len;
6221         txd->addr = cpu_to_le64(mapping);
6222
6223         frags = rtl8169_xmit_frags(tp, skb, opts);
6224         if (frags < 0)
6225                 goto err_dma_1;
6226         else if (frags)
6227                 opts[0] |= FirstFrag;
6228         else {
6229                 opts[0] |= FirstFrag | LastFrag;
6230                 tp->tx_skb[entry].skb = skb;
6231         }
6232
6233         txd->opts2 = cpu_to_le32(opts[1]);
6234
6235         skb_tx_timestamp(skb);
6236
6237         /* Force memory writes to complete before releasing descriptor */
6238         dma_wmb();
6239
6240         /* Anti gcc 2.95.3 bugware (sic) */
6241         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6242         txd->opts1 = cpu_to_le32(status);
6243
6244         /* Force all memory writes to complete before notifying device */
6245         wmb();
6246
6247         tp->cur_tx += frags + 1;
6248
6249         RTL_W8(tp, TxPoll, NPQ);
6250
6251         mmiowb();
6252
6253         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6254                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6255                  * not miss a ring update when it notices a stopped queue.
6256                  */
6257                 smp_wmb();
6258                 netif_stop_queue(dev);
6259                 /* Sync with rtl_tx:
6260                  * - publish queue status and cur_tx ring index (write barrier)
6261                  * - refresh dirty_tx ring index (read barrier).
6262                  * May the current thread have a pessimistic view of the ring
6263                  * status and forget to wake up queue, a racing rtl_tx thread
6264                  * can't.
6265                  */
6266                 smp_mb();
6267                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6268                         netif_wake_queue(dev);
6269         }
6270
6271         return NETDEV_TX_OK;
6272
6273 err_dma_1:
6274         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6275 err_dma_0:
6276         dev_kfree_skb_any(skb);
6277         dev->stats.tx_dropped++;
6278         return NETDEV_TX_OK;
6279
6280 err_stop_0:
6281         netif_stop_queue(dev);
6282         dev->stats.tx_dropped++;
6283         return NETDEV_TX_BUSY;
6284 }
6285
6286 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6287 {
6288         struct rtl8169_private *tp = netdev_priv(dev);
6289         struct pci_dev *pdev = tp->pci_dev;
6290         u16 pci_status, pci_cmd;
6291
6292         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6293         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6294
6295         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6296                   pci_cmd, pci_status);
6297
6298         /*
6299          * The recovery sequence below admits a very elaborated explanation:
6300          * - it seems to work;
6301          * - I did not see what else could be done;
6302          * - it makes iop3xx happy.
6303          *
6304          * Feel free to adjust to your needs.
6305          */
6306         if (pdev->broken_parity_status)
6307                 pci_cmd &= ~PCI_COMMAND_PARITY;
6308         else
6309                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6310
6311         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6312
6313         pci_write_config_word(pdev, PCI_STATUS,
6314                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6315                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6316                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6317
6318         /* The infamous DAC f*ckup only happens at boot time */
6319         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6320                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6321                 tp->cp_cmd &= ~PCIDAC;
6322                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6323                 dev->features &= ~NETIF_F_HIGHDMA;
6324         }
6325
6326         rtl8169_hw_reset(tp);
6327
6328         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6329 }
6330
6331 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6332 {
6333         unsigned int dirty_tx, tx_left;
6334
6335         dirty_tx = tp->dirty_tx;
6336         smp_rmb();
6337         tx_left = tp->cur_tx - dirty_tx;
6338
6339         while (tx_left > 0) {
6340                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6341                 struct ring_info *tx_skb = tp->tx_skb + entry;
6342                 u32 status;
6343
6344                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6345                 if (status & DescOwn)
6346                         break;
6347
6348                 /* This barrier is needed to keep us from reading
6349                  * any other fields out of the Tx descriptor until
6350                  * we know the status of DescOwn
6351                  */
6352                 dma_rmb();
6353
6354                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6355                                      tp->TxDescArray + entry);
6356                 if (status & LastFrag) {
6357                         u64_stats_update_begin(&tp->tx_stats.syncp);
6358                         tp->tx_stats.packets++;
6359                         tp->tx_stats.bytes += tx_skb->skb->len;
6360                         u64_stats_update_end(&tp->tx_stats.syncp);
6361                         dev_consume_skb_any(tx_skb->skb);
6362                         tx_skb->skb = NULL;
6363                 }
6364                 dirty_tx++;
6365                 tx_left--;
6366         }
6367
6368         if (tp->dirty_tx != dirty_tx) {
6369                 tp->dirty_tx = dirty_tx;
6370                 /* Sync with rtl8169_start_xmit:
6371                  * - publish dirty_tx ring index (write barrier)
6372                  * - refresh cur_tx ring index and queue status (read barrier)
6373                  * May the current thread miss the stopped queue condition,
6374                  * a racing xmit thread can only have a right view of the
6375                  * ring status.
6376                  */
6377                 smp_mb();
6378                 if (netif_queue_stopped(dev) &&
6379                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6380                         netif_wake_queue(dev);
6381                 }
6382                 /*
6383                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6384                  * too close. Let's kick an extra TxPoll request when a burst
6385                  * of start_xmit activity is detected (if it is not detected,
6386                  * it is slow enough). -- FR
6387                  */
6388                 if (tp->cur_tx != dirty_tx)
6389                         RTL_W8(tp, TxPoll, NPQ);
6390         }
6391 }
6392
6393 static inline int rtl8169_fragmented_frame(u32 status)
6394 {
6395         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6396 }
6397
6398 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6399 {
6400         u32 status = opts1 & RxProtoMask;
6401
6402         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6403             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6404                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6405         else
6406                 skb_checksum_none_assert(skb);
6407 }
6408
6409 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6410                                            struct rtl8169_private *tp,
6411                                            int pkt_size,
6412                                            dma_addr_t addr)
6413 {
6414         struct sk_buff *skb;
6415         struct device *d = tp_to_dev(tp);
6416
6417         data = rtl8169_align(data);
6418         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6419         prefetch(data);
6420         skb = napi_alloc_skb(&tp->napi, pkt_size);
6421         if (skb)
6422                 skb_copy_to_linear_data(skb, data, pkt_size);
6423         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6424
6425         return skb;
6426 }
6427
6428 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6429 {
6430         unsigned int cur_rx, rx_left;
6431         unsigned int count;
6432
6433         cur_rx = tp->cur_rx;
6434
6435         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6436                 unsigned int entry = cur_rx % NUM_RX_DESC;
6437                 struct RxDesc *desc = tp->RxDescArray + entry;
6438                 u32 status;
6439
6440                 status = le32_to_cpu(desc->opts1);
6441                 if (status & DescOwn)
6442                         break;
6443
6444                 /* This barrier is needed to keep us from reading
6445                  * any other fields out of the Rx descriptor until
6446                  * we know the status of DescOwn
6447                  */
6448                 dma_rmb();
6449
6450                 if (unlikely(status & RxRES)) {
6451                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6452                                    status);
6453                         dev->stats.rx_errors++;
6454                         if (status & (RxRWT | RxRUNT))
6455                                 dev->stats.rx_length_errors++;
6456                         if (status & RxCRC)
6457                                 dev->stats.rx_crc_errors++;
6458                         /* RxFOVF is a reserved bit on later chip versions */
6459                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6460                             status & RxFOVF) {
6461                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6462                                 dev->stats.rx_fifo_errors++;
6463                         } else if (status & (RxRUNT | RxCRC) &&
6464                                    !(status & RxRWT) &&
6465                                    dev->features & NETIF_F_RXALL) {
6466                                 goto process_pkt;
6467                         }
6468                 } else {
6469                         struct sk_buff *skb;
6470                         dma_addr_t addr;
6471                         int pkt_size;
6472
6473 process_pkt:
6474                         addr = le64_to_cpu(desc->addr);
6475                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6476                                 pkt_size = (status & 0x00003fff) - 4;
6477                         else
6478                                 pkt_size = status & 0x00003fff;
6479
6480                         /*
6481                          * The driver does not support incoming fragmented
6482                          * frames. They are seen as a symptom of over-mtu
6483                          * sized frames.
6484                          */
6485                         if (unlikely(rtl8169_fragmented_frame(status))) {
6486                                 dev->stats.rx_dropped++;
6487                                 dev->stats.rx_length_errors++;
6488                                 goto release_descriptor;
6489                         }
6490
6491                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6492                                                   tp, pkt_size, addr);
6493                         if (!skb) {
6494                                 dev->stats.rx_dropped++;
6495                                 goto release_descriptor;
6496                         }
6497
6498                         rtl8169_rx_csum(skb, status);
6499                         skb_put(skb, pkt_size);
6500                         skb->protocol = eth_type_trans(skb, dev);
6501
6502                         rtl8169_rx_vlan_tag(desc, skb);
6503
6504                         if (skb->pkt_type == PACKET_MULTICAST)
6505                                 dev->stats.multicast++;
6506
6507                         napi_gro_receive(&tp->napi, skb);
6508
6509                         u64_stats_update_begin(&tp->rx_stats.syncp);
6510                         tp->rx_stats.packets++;
6511                         tp->rx_stats.bytes += pkt_size;
6512                         u64_stats_update_end(&tp->rx_stats.syncp);
6513                 }
6514 release_descriptor:
6515                 desc->opts2 = 0;
6516                 rtl8169_mark_to_asic(desc);
6517         }
6518
6519         count = cur_rx - tp->cur_rx;
6520         tp->cur_rx = cur_rx;
6521
6522         return count;
6523 }
6524
6525 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6526 {
6527         struct rtl8169_private *tp = dev_instance;
6528         int handled = 0;
6529         u16 status;
6530
6531         status = rtl_get_events(tp);
6532         if (status && status != 0xffff) {
6533                 status &= RTL_EVENT_NAPI | tp->event_slow;
6534                 if (status) {
6535                         handled = 1;
6536
6537                         rtl_irq_disable(tp);
6538                         napi_schedule_irqoff(&tp->napi);
6539                 }
6540         }
6541         return IRQ_RETVAL(handled);
6542 }
6543
6544 /*
6545  * Workqueue context.
6546  */
6547 static void rtl_slow_event_work(struct rtl8169_private *tp)
6548 {
6549         struct net_device *dev = tp->dev;
6550         u16 status;
6551
6552         status = rtl_get_events(tp) & tp->event_slow;
6553         rtl_ack_events(tp, status);
6554
6555         if (unlikely(status & RxFIFOOver)) {
6556                 switch (tp->mac_version) {
6557                 /* Work around for rx fifo overflow */
6558                 case RTL_GIGA_MAC_VER_11:
6559                         netif_stop_queue(dev);
6560                         /* XXX - Hack alert. See rtl_task(). */
6561                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6562                 default:
6563                         break;
6564                 }
6565         }
6566
6567         if (unlikely(status & SYSErr))
6568                 rtl8169_pcierr_interrupt(dev);
6569
6570         if (status & LinkChg)
6571                 phy_mac_interrupt(dev->phydev);
6572
6573         rtl_irq_enable_all(tp);
6574 }
6575
6576 static void rtl_task(struct work_struct *work)
6577 {
6578         static const struct {
6579                 int bitnr;
6580                 void (*action)(struct rtl8169_private *);
6581         } rtl_work[] = {
6582                 /* XXX - keep rtl_slow_event_work() as first element. */
6583                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6584                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6585         };
6586         struct rtl8169_private *tp =
6587                 container_of(work, struct rtl8169_private, wk.work);
6588         struct net_device *dev = tp->dev;
6589         int i;
6590
6591         rtl_lock_work(tp);
6592
6593         if (!netif_running(dev) ||
6594             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6595                 goto out_unlock;
6596
6597         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6598                 bool pending;
6599
6600                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6601                 if (pending)
6602                         rtl_work[i].action(tp);
6603         }
6604
6605 out_unlock:
6606         rtl_unlock_work(tp);
6607 }
6608
6609 static int rtl8169_poll(struct napi_struct *napi, int budget)
6610 {
6611         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6612         struct net_device *dev = tp->dev;
6613         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6614         int work_done= 0;
6615         u16 status;
6616
6617         status = rtl_get_events(tp);
6618         rtl_ack_events(tp, status & ~tp->event_slow);
6619
6620         if (status & RTL_EVENT_NAPI_RX)
6621                 work_done = rtl_rx(dev, tp, (u32) budget);
6622
6623         if (status & RTL_EVENT_NAPI_TX)
6624                 rtl_tx(dev, tp);
6625
6626         if (status & tp->event_slow) {
6627                 enable_mask &= ~tp->event_slow;
6628
6629                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6630         }
6631
6632         if (work_done < budget) {
6633                 napi_complete_done(napi, work_done);
6634
6635                 rtl_irq_enable(tp, enable_mask);
6636                 mmiowb();
6637         }
6638
6639         return work_done;
6640 }
6641
6642 static void rtl8169_rx_missed(struct net_device *dev)
6643 {
6644         struct rtl8169_private *tp = netdev_priv(dev);
6645
6646         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6647                 return;
6648
6649         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6650         RTL_W32(tp, RxMissed, 0);
6651 }
6652
6653 static void r8169_phylink_handler(struct net_device *ndev)
6654 {
6655         struct rtl8169_private *tp = netdev_priv(ndev);
6656
6657         if (netif_carrier_ok(ndev)) {
6658                 rtl_link_chg_patch(tp);
6659                 pm_request_resume(&tp->pci_dev->dev);
6660         } else {
6661                 pm_runtime_idle(&tp->pci_dev->dev);
6662         }
6663
6664         if (net_ratelimit())
6665                 phy_print_status(ndev->phydev);
6666 }
6667
6668 static int r8169_phy_connect(struct rtl8169_private *tp)
6669 {
6670         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6671         phy_interface_t phy_mode;
6672         int ret;
6673
6674         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6675                    PHY_INTERFACE_MODE_MII;
6676
6677         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6678                                  phy_mode);
6679         if (ret)
6680                 return ret;
6681
6682         if (!tp->supports_gmii)
6683                 phy_set_max_speed(phydev, SPEED_100);
6684
6685         /* Ensure to advertise everything, incl. pause */
6686         phydev->advertising = phydev->supported;
6687
6688         phy_attached_info(phydev);
6689
6690         return 0;
6691 }
6692
6693 static void rtl8169_down(struct net_device *dev)
6694 {
6695         struct rtl8169_private *tp = netdev_priv(dev);
6696
6697         phy_stop(dev->phydev);
6698
6699         napi_disable(&tp->napi);
6700         netif_stop_queue(dev);
6701
6702         rtl8169_hw_reset(tp);
6703         /*
6704          * At this point device interrupts can not be enabled in any function,
6705          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6706          * and napi is disabled (rtl8169_poll).
6707          */
6708         rtl8169_rx_missed(dev);
6709
6710         /* Give a racing hard_start_xmit a few cycles to complete. */
6711         synchronize_sched();
6712
6713         rtl8169_tx_clear(tp);
6714
6715         rtl8169_rx_clear(tp);
6716
6717         rtl_pll_power_down(tp);
6718 }
6719
6720 static int rtl8169_close(struct net_device *dev)
6721 {
6722         struct rtl8169_private *tp = netdev_priv(dev);
6723         struct pci_dev *pdev = tp->pci_dev;
6724
6725         pm_runtime_get_sync(&pdev->dev);
6726
6727         /* Update counters before going down */
6728         rtl8169_update_counters(tp);
6729
6730         rtl_lock_work(tp);
6731         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6732
6733         rtl8169_down(dev);
6734         rtl_unlock_work(tp);
6735
6736         cancel_work_sync(&tp->wk.work);
6737
6738         phy_disconnect(dev->phydev);
6739
6740         pci_free_irq(pdev, 0, tp);
6741
6742         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6743                           tp->RxPhyAddr);
6744         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6745                           tp->TxPhyAddr);
6746         tp->TxDescArray = NULL;
6747         tp->RxDescArray = NULL;
6748
6749         pm_runtime_put_sync(&pdev->dev);
6750
6751         return 0;
6752 }
6753
6754 #ifdef CONFIG_NET_POLL_CONTROLLER
6755 static void rtl8169_netpoll(struct net_device *dev)
6756 {
6757         struct rtl8169_private *tp = netdev_priv(dev);
6758
6759         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6760 }
6761 #endif
6762
6763 static int rtl_open(struct net_device *dev)
6764 {
6765         struct rtl8169_private *tp = netdev_priv(dev);
6766         struct pci_dev *pdev = tp->pci_dev;
6767         int retval = -ENOMEM;
6768
6769         pm_runtime_get_sync(&pdev->dev);
6770
6771         /*
6772          * Rx and Tx descriptors needs 256 bytes alignment.
6773          * dma_alloc_coherent provides more.
6774          */
6775         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6776                                              &tp->TxPhyAddr, GFP_KERNEL);
6777         if (!tp->TxDescArray)
6778                 goto err_pm_runtime_put;
6779
6780         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6781                                              &tp->RxPhyAddr, GFP_KERNEL);
6782         if (!tp->RxDescArray)
6783                 goto err_free_tx_0;
6784
6785         retval = rtl8169_init_ring(tp);
6786         if (retval < 0)
6787                 goto err_free_rx_1;
6788
6789         INIT_WORK(&tp->wk.work, rtl_task);
6790
6791         smp_mb();
6792
6793         rtl_request_firmware(tp);
6794
6795         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6796                                  dev->name);
6797         if (retval < 0)
6798                 goto err_release_fw_2;
6799
6800         retval = r8169_phy_connect(tp);
6801         if (retval)
6802                 goto err_free_irq;
6803
6804         rtl_lock_work(tp);
6805
6806         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6807
6808         napi_enable(&tp->napi);
6809
6810         rtl8169_init_phy(dev, tp);
6811
6812         rtl_pll_power_up(tp);
6813
6814         rtl_hw_start(tp);
6815
6816         if (!rtl8169_init_counter_offsets(tp))
6817                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6818
6819         phy_start(dev->phydev);
6820         netif_start_queue(dev);
6821
6822         rtl_unlock_work(tp);
6823
6824         pm_runtime_put_sync(&pdev->dev);
6825 out:
6826         return retval;
6827
6828 err_free_irq:
6829         pci_free_irq(pdev, 0, tp);
6830 err_release_fw_2:
6831         rtl_release_firmware(tp);
6832         rtl8169_rx_clear(tp);
6833 err_free_rx_1:
6834         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6835                           tp->RxPhyAddr);
6836         tp->RxDescArray = NULL;
6837 err_free_tx_0:
6838         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6839                           tp->TxPhyAddr);
6840         tp->TxDescArray = NULL;
6841 err_pm_runtime_put:
6842         pm_runtime_put_noidle(&pdev->dev);
6843         goto out;
6844 }
6845
6846 static void
6847 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6848 {
6849         struct rtl8169_private *tp = netdev_priv(dev);
6850         struct pci_dev *pdev = tp->pci_dev;
6851         struct rtl8169_counters *counters = tp->counters;
6852         unsigned int start;
6853
6854         pm_runtime_get_noresume(&pdev->dev);
6855
6856         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6857                 rtl8169_rx_missed(dev);
6858
6859         do {
6860                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6861                 stats->rx_packets = tp->rx_stats.packets;
6862                 stats->rx_bytes = tp->rx_stats.bytes;
6863         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6864
6865         do {
6866                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6867                 stats->tx_packets = tp->tx_stats.packets;
6868                 stats->tx_bytes = tp->tx_stats.bytes;
6869         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6870
6871         stats->rx_dropped       = dev->stats.rx_dropped;
6872         stats->tx_dropped       = dev->stats.tx_dropped;
6873         stats->rx_length_errors = dev->stats.rx_length_errors;
6874         stats->rx_errors        = dev->stats.rx_errors;
6875         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6876         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6877         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6878         stats->multicast        = dev->stats.multicast;
6879
6880         /*
6881          * Fetch additonal counter values missing in stats collected by driver
6882          * from tally counters.
6883          */
6884         if (pm_runtime_active(&pdev->dev))
6885                 rtl8169_update_counters(tp);
6886
6887         /*
6888          * Subtract values fetched during initalization.
6889          * See rtl8169_init_counter_offsets for a description why we do that.
6890          */
6891         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6892                 le64_to_cpu(tp->tc_offset.tx_errors);
6893         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6894                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6895         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6896                 le16_to_cpu(tp->tc_offset.tx_aborted);
6897
6898         pm_runtime_put_noidle(&pdev->dev);
6899 }
6900
6901 static void rtl8169_net_suspend(struct net_device *dev)
6902 {
6903         struct rtl8169_private *tp = netdev_priv(dev);
6904
6905         if (!netif_running(dev))
6906                 return;
6907
6908         phy_stop(dev->phydev);
6909         netif_device_detach(dev);
6910         netif_stop_queue(dev);
6911
6912         rtl_lock_work(tp);
6913         napi_disable(&tp->napi);
6914         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6915         rtl_unlock_work(tp);
6916
6917         rtl_pll_power_down(tp);
6918 }
6919
6920 #ifdef CONFIG_PM
6921
6922 static int rtl8169_suspend(struct device *device)
6923 {
6924         struct pci_dev *pdev = to_pci_dev(device);
6925         struct net_device *dev = pci_get_drvdata(pdev);
6926
6927         rtl8169_net_suspend(dev);
6928
6929         return 0;
6930 }
6931
6932 static void __rtl8169_resume(struct net_device *dev)
6933 {
6934         struct rtl8169_private *tp = netdev_priv(dev);
6935
6936         netif_device_attach(dev);
6937
6938         rtl_pll_power_up(tp);
6939         rtl8169_init_phy(dev, tp);
6940
6941         phy_start(tp->dev->phydev);
6942
6943         rtl_lock_work(tp);
6944         napi_enable(&tp->napi);
6945         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6946         rtl_unlock_work(tp);
6947
6948         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6949 }
6950
6951 static int rtl8169_resume(struct device *device)
6952 {
6953         struct pci_dev *pdev = to_pci_dev(device);
6954         struct net_device *dev = pci_get_drvdata(pdev);
6955
6956         if (netif_running(dev))
6957                 __rtl8169_resume(dev);
6958
6959         return 0;
6960 }
6961
6962 static int rtl8169_runtime_suspend(struct device *device)
6963 {
6964         struct pci_dev *pdev = to_pci_dev(device);
6965         struct net_device *dev = pci_get_drvdata(pdev);
6966         struct rtl8169_private *tp = netdev_priv(dev);
6967
6968         if (!tp->TxDescArray) {
6969                 rtl_pll_power_down(tp);
6970                 return 0;
6971         }
6972
6973         rtl_lock_work(tp);
6974         __rtl8169_set_wol(tp, WAKE_ANY);
6975         rtl_unlock_work(tp);
6976
6977         rtl8169_net_suspend(dev);
6978
6979         /* Update counters before going runtime suspend */
6980         rtl8169_rx_missed(dev);
6981         rtl8169_update_counters(tp);
6982
6983         return 0;
6984 }
6985
6986 static int rtl8169_runtime_resume(struct device *device)
6987 {
6988         struct pci_dev *pdev = to_pci_dev(device);
6989         struct net_device *dev = pci_get_drvdata(pdev);
6990         struct rtl8169_private *tp = netdev_priv(dev);
6991         rtl_rar_set(tp, dev->dev_addr);
6992
6993         if (!tp->TxDescArray)
6994                 return 0;
6995
6996         rtl_lock_work(tp);
6997         __rtl8169_set_wol(tp, tp->saved_wolopts);
6998         rtl_unlock_work(tp);
6999
7000         __rtl8169_resume(dev);
7001
7002         return 0;
7003 }
7004
7005 static int rtl8169_runtime_idle(struct device *device)
7006 {
7007         struct pci_dev *pdev = to_pci_dev(device);
7008         struct net_device *dev = pci_get_drvdata(pdev);
7009
7010         if (!netif_running(dev) || !netif_carrier_ok(dev))
7011                 pm_schedule_suspend(device, 10000);
7012
7013         return -EBUSY;
7014 }
7015
7016 static const struct dev_pm_ops rtl8169_pm_ops = {
7017         .suspend                = rtl8169_suspend,
7018         .resume                 = rtl8169_resume,
7019         .freeze                 = rtl8169_suspend,
7020         .thaw                   = rtl8169_resume,
7021         .poweroff               = rtl8169_suspend,
7022         .restore                = rtl8169_resume,
7023         .runtime_suspend        = rtl8169_runtime_suspend,
7024         .runtime_resume         = rtl8169_runtime_resume,
7025         .runtime_idle           = rtl8169_runtime_idle,
7026 };
7027
7028 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7029
7030 #else /* !CONFIG_PM */
7031
7032 #define RTL8169_PM_OPS  NULL
7033
7034 #endif /* !CONFIG_PM */
7035
7036 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7037 {
7038         /* WoL fails with 8168b when the receiver is disabled. */
7039         switch (tp->mac_version) {
7040         case RTL_GIGA_MAC_VER_11:
7041         case RTL_GIGA_MAC_VER_12:
7042         case RTL_GIGA_MAC_VER_17:
7043                 pci_clear_master(tp->pci_dev);
7044
7045                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7046                 /* PCI commit */
7047                 RTL_R8(tp, ChipCmd);
7048                 break;
7049         default:
7050                 break;
7051         }
7052 }
7053
7054 static void rtl_shutdown(struct pci_dev *pdev)
7055 {
7056         struct net_device *dev = pci_get_drvdata(pdev);
7057         struct rtl8169_private *tp = netdev_priv(dev);
7058
7059         rtl8169_net_suspend(dev);
7060
7061         /* Restore original MAC address */
7062         rtl_rar_set(tp, dev->perm_addr);
7063
7064         rtl8169_hw_reset(tp);
7065
7066         if (system_state == SYSTEM_POWER_OFF) {
7067                 if (tp->saved_wolopts) {
7068                         rtl_wol_suspend_quirk(tp);
7069                         rtl_wol_shutdown_quirk(tp);
7070                 }
7071
7072                 pci_wake_from_d3(pdev, true);
7073                 pci_set_power_state(pdev, PCI_D3hot);
7074         }
7075 }
7076
7077 static void rtl_remove_one(struct pci_dev *pdev)
7078 {
7079         struct net_device *dev = pci_get_drvdata(pdev);
7080         struct rtl8169_private *tp = netdev_priv(dev);
7081
7082         if (r8168_check_dash(tp))
7083                 rtl8168_driver_stop(tp);
7084
7085         netif_napi_del(&tp->napi);
7086
7087         unregister_netdev(dev);
7088         mdiobus_unregister(tp->mii_bus);
7089
7090         rtl_release_firmware(tp);
7091
7092         if (pci_dev_run_wake(pdev))
7093                 pm_runtime_get_noresume(&pdev->dev);
7094
7095         /* restore original MAC address */
7096         rtl_rar_set(tp, dev->perm_addr);
7097 }
7098
7099 static const struct net_device_ops rtl_netdev_ops = {
7100         .ndo_open               = rtl_open,
7101         .ndo_stop               = rtl8169_close,
7102         .ndo_get_stats64        = rtl8169_get_stats64,
7103         .ndo_start_xmit         = rtl8169_start_xmit,
7104         .ndo_tx_timeout         = rtl8169_tx_timeout,
7105         .ndo_validate_addr      = eth_validate_addr,
7106         .ndo_change_mtu         = rtl8169_change_mtu,
7107         .ndo_fix_features       = rtl8169_fix_features,
7108         .ndo_set_features       = rtl8169_set_features,
7109         .ndo_set_mac_address    = rtl_set_mac_address,
7110         .ndo_do_ioctl           = rtl8169_ioctl,
7111         .ndo_set_rx_mode        = rtl_set_rx_mode,
7112 #ifdef CONFIG_NET_POLL_CONTROLLER
7113         .ndo_poll_controller    = rtl8169_netpoll,
7114 #endif
7115
7116 };
7117
7118 static const struct rtl_cfg_info {
7119         void (*hw_start)(struct rtl8169_private *tp);
7120         u16 event_slow;
7121         unsigned int has_gmii:1;
7122         const struct rtl_coalesce_info *coalesce_info;
7123         u8 default_ver;
7124 } rtl_cfg_infos [] = {
7125         [RTL_CFG_0] = {
7126                 .hw_start       = rtl_hw_start_8169,
7127                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7128                 .has_gmii       = 1,
7129                 .coalesce_info  = rtl_coalesce_info_8169,
7130                 .default_ver    = RTL_GIGA_MAC_VER_01,
7131         },
7132         [RTL_CFG_1] = {
7133                 .hw_start       = rtl_hw_start_8168,
7134                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7135                 .has_gmii       = 1,
7136                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7137                 .default_ver    = RTL_GIGA_MAC_VER_11,
7138         },
7139         [RTL_CFG_2] = {
7140                 .hw_start       = rtl_hw_start_8101,
7141                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7142                                   PCSTimeout,
7143                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7144                 .default_ver    = RTL_GIGA_MAC_VER_13,
7145         }
7146 };
7147
7148 static int rtl_alloc_irq(struct rtl8169_private *tp)
7149 {
7150         unsigned int flags;
7151
7152         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7153                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7154                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7155                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7156                 flags = PCI_IRQ_LEGACY;
7157         } else {
7158                 flags = PCI_IRQ_ALL_TYPES;
7159         }
7160
7161         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7162 }
7163
7164 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7165 {
7166         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7167 }
7168
7169 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7170 {
7171         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7172 }
7173
7174 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7175 {
7176         struct rtl8169_private *tp = mii_bus->priv;
7177
7178         if (phyaddr > 0)
7179                 return -ENODEV;
7180
7181         return rtl_readphy(tp, phyreg);
7182 }
7183
7184 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7185                                 int phyreg, u16 val)
7186 {
7187         struct rtl8169_private *tp = mii_bus->priv;
7188
7189         if (phyaddr > 0)
7190                 return -ENODEV;
7191
7192         rtl_writephy(tp, phyreg, val);
7193
7194         return 0;
7195 }
7196
7197 static int r8169_mdio_register(struct rtl8169_private *tp)
7198 {
7199         struct pci_dev *pdev = tp->pci_dev;
7200         struct phy_device *phydev;
7201         struct mii_bus *new_bus;
7202         int ret;
7203
7204         new_bus = devm_mdiobus_alloc(&pdev->dev);
7205         if (!new_bus)
7206                 return -ENOMEM;
7207
7208         new_bus->name = "r8169";
7209         new_bus->priv = tp;
7210         new_bus->parent = &pdev->dev;
7211         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7212         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7213                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7214
7215         new_bus->read = r8169_mdio_read_reg;
7216         new_bus->write = r8169_mdio_write_reg;
7217
7218         ret = mdiobus_register(new_bus);
7219         if (ret)
7220                 return ret;
7221
7222         phydev = mdiobus_get_phy(new_bus, 0);
7223         if (!phydev) {
7224                 mdiobus_unregister(new_bus);
7225                 return -ENODEV;
7226         }
7227
7228         /* PHY will be woken up in rtl_open() */
7229         phy_suspend(phydev);
7230
7231         tp->mii_bus = new_bus;
7232
7233         return 0;
7234 }
7235
7236 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7237 {
7238         u32 data;
7239
7240         tp->ocp_base = OCP_STD_PHY_BASE;
7241
7242         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7243
7244         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7245                 return;
7246
7247         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7248                 return;
7249
7250         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7251         msleep(1);
7252         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7253
7254         data = r8168_mac_ocp_read(tp, 0xe8de);
7255         data &= ~(1 << 14);
7256         r8168_mac_ocp_write(tp, 0xe8de, data);
7257
7258         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7259                 return;
7260
7261         data = r8168_mac_ocp_read(tp, 0xe8de);
7262         data |= (1 << 15);
7263         r8168_mac_ocp_write(tp, 0xe8de, data);
7264
7265         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7266                 return;
7267 }
7268
7269 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7270 {
7271         rtl8168ep_stop_cmac(tp);
7272         rtl_hw_init_8168g(tp);
7273 }
7274
7275 static void rtl_hw_initialize(struct rtl8169_private *tp)
7276 {
7277         switch (tp->mac_version) {
7278         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7279                 rtl_hw_init_8168g(tp);
7280                 break;
7281         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7282                 rtl_hw_init_8168ep(tp);
7283                 break;
7284         default:
7285                 break;
7286         }
7287 }
7288
7289 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7290 {
7291         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7292         struct rtl8169_private *tp;
7293         struct net_device *dev;
7294         int chipset, region, i;
7295         int rc;
7296
7297         if (netif_msg_drv(&debug)) {
7298                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7299                        MODULENAME, RTL8169_VERSION);
7300         }
7301
7302         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7303         if (!dev)
7304                 return -ENOMEM;
7305
7306         SET_NETDEV_DEV(dev, &pdev->dev);
7307         dev->netdev_ops = &rtl_netdev_ops;
7308         tp = netdev_priv(dev);
7309         tp->dev = dev;
7310         tp->pci_dev = pdev;
7311         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7312         tp->supports_gmii = cfg->has_gmii;
7313
7314         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7315         rc = pcim_enable_device(pdev);
7316         if (rc < 0) {
7317                 dev_err(&pdev->dev, "enable failure\n");
7318                 return rc;
7319         }
7320
7321         if (pcim_set_mwi(pdev) < 0)
7322                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7323
7324         /* use first MMIO region */
7325         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7326         if (region < 0) {
7327                 dev_err(&pdev->dev, "no MMIO resource found\n");
7328                 return -ENODEV;
7329         }
7330
7331         /* check for weird/broken PCI region reporting */
7332         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7333                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7334                 return -ENODEV;
7335         }
7336
7337         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7338         if (rc < 0) {
7339                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7340                 return rc;
7341         }
7342
7343         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7344
7345         if (!pci_is_pcie(pdev))
7346                 dev_info(&pdev->dev, "not PCI Express\n");
7347
7348         /* Identify chip attached to board */
7349         rtl8169_get_mac_version(tp, cfg->default_ver);
7350
7351         if (rtl_tbi_enabled(tp)) {
7352                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7353                 return -ENODEV;
7354         }
7355
7356         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7357
7358         if ((sizeof(dma_addr_t) > 4) &&
7359             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7360                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7361             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7362             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7363
7364                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7365                 if (!pci_is_pcie(pdev))
7366                         tp->cp_cmd |= PCIDAC;
7367                 dev->features |= NETIF_F_HIGHDMA;
7368         } else {
7369                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7370                 if (rc < 0) {
7371                         dev_err(&pdev->dev, "DMA configuration failed\n");
7372                         return rc;
7373                 }
7374         }
7375
7376         rtl_init_rxcfg(tp);
7377
7378         rtl_irq_disable(tp);
7379
7380         rtl_hw_initialize(tp);
7381
7382         rtl_hw_reset(tp);
7383
7384         rtl_ack_events(tp, 0xffff);
7385
7386         pci_set_master(pdev);
7387
7388         rtl_init_mdio_ops(tp);
7389         rtl_init_jumbo_ops(tp);
7390
7391         rtl8169_print_mac_version(tp);
7392
7393         chipset = tp->mac_version;
7394
7395         rc = rtl_alloc_irq(tp);
7396         if (rc < 0) {
7397                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7398                 return rc;
7399         }
7400
7401         /* override BIOS settings, use userspace tools to enable WOL */
7402         __rtl8169_set_wol(tp, 0);
7403
7404         mutex_init(&tp->wk.mutex);
7405         u64_stats_init(&tp->rx_stats.syncp);
7406         u64_stats_init(&tp->tx_stats.syncp);
7407
7408         /* Get MAC address */
7409         switch (tp->mac_version) {
7410                 u8 mac_addr[ETH_ALEN] __aligned(4);
7411         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7412         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7413                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7414                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7415
7416                 if (is_valid_ether_addr(mac_addr))
7417                         rtl_rar_set(tp, mac_addr);
7418                 break;
7419         default:
7420                 break;
7421         }
7422         for (i = 0; i < ETH_ALEN; i++)
7423                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7424
7425         dev->ethtool_ops = &rtl8169_ethtool_ops;
7426         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7427
7428         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7429
7430         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7431          * properly for all devices */
7432         dev->features |= NETIF_F_RXCSUM |
7433                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7434
7435         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7436                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7437                 NETIF_F_HW_VLAN_CTAG_RX;
7438         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7439                 NETIF_F_HIGHDMA;
7440
7441         tp->cp_cmd |= RxChkSum | RxVlan;
7442
7443         /*
7444          * Pretend we are using VLANs; This bypasses a nasty bug where
7445          * Interrupts stop flowing on high load on 8110SCd controllers.
7446          */
7447         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7448                 /* Disallow toggling */
7449                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7450
7451         switch (rtl_chip_infos[chipset].txd_version) {
7452         case RTL_TD_0:
7453                 tp->tso_csum = rtl8169_tso_csum_v1;
7454                 break;
7455         case RTL_TD_1:
7456                 tp->tso_csum = rtl8169_tso_csum_v2;
7457                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7458                 break;
7459         default:
7460                 WARN_ON_ONCE(1);
7461         }
7462
7463         dev->hw_features |= NETIF_F_RXALL;
7464         dev->hw_features |= NETIF_F_RXFCS;
7465
7466         /* MTU range: 60 - hw-specific max */
7467         dev->min_mtu = ETH_ZLEN;
7468         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7469
7470         tp->hw_start = cfg->hw_start;
7471         tp->event_slow = cfg->event_slow;
7472         tp->coalesce_info = cfg->coalesce_info;
7473
7474         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7475
7476         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7477                                             &tp->counters_phys_addr,
7478                                             GFP_KERNEL);
7479         if (!tp->counters)
7480                 return -ENOMEM;
7481
7482         pci_set_drvdata(pdev, dev);
7483
7484         rc = r8169_mdio_register(tp);
7485         if (rc)
7486                 return rc;
7487
7488         rc = register_netdev(dev);
7489         if (rc)
7490                 goto err_mdio_unregister;
7491
7492         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7493                    rtl_chip_infos[chipset].name, dev->dev_addr,
7494                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7495                    pci_irq_vector(pdev, 0));
7496         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7497                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7498                            "tx checksumming: %s]\n",
7499                            rtl_chip_infos[chipset].jumbo_max,
7500                           tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
7501         }
7502
7503         if (r8168_check_dash(tp))
7504                 rtl8168_driver_start(tp);
7505
7506         if (pci_dev_run_wake(pdev))
7507                 pm_runtime_put_sync(&pdev->dev);
7508
7509         return 0;
7510
7511 err_mdio_unregister:
7512         mdiobus_unregister(tp->mii_bus);
7513         return rc;
7514 }
7515
7516 static struct pci_driver rtl8169_pci_driver = {
7517         .name           = MODULENAME,
7518         .id_table       = rtl8169_pci_tbl,
7519         .probe          = rtl_init_one,
7520         .remove         = rtl_remove_one,
7521         .shutdown       = rtl_shutdown,
7522         .driver.pm      = RTL8169_PM_OPS,
7523 };
7524
7525 module_pci_driver(rtl8169_pci_driver);