drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492
 493         /* rtl8169_PHYstatus */
 494         TBI_Enable      = 0x80,
 495         TxFlowCtrl      = 0x40,
 496         RxFlowCtrl      = 0x20,
 497         _1000bpsF       = 0x10,
 498         _100bps         = 0x08,
 499         _10bps          = 0x04,
 500         LinkStatus      = 0x02,
 501         FullDup         = 0x01,
 502
 503         /* ResetCounterCommand */
 504         CounterReset    = 0x1,
 505
 506         /* DumpCounterCommand */
 507         CounterDump     = 0x8,
 508
 509         /* magic enable v2 */
 510         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 511 };
 512
 513 enum rtl_desc_bit {
 514         /* First doubleword. */
 515         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 516         RingEnd         = (1 << 30), /* End of descriptor ring */
 517         FirstFrag       = (1 << 29), /* First segment of a packet */
 518         LastFrag        = (1 << 28), /* Final segment of a packet */
 519 };
 520
 521 /* Generic case. */
 522 enum rtl_tx_desc_bit {
 523         /* First doubleword. */
 524         TD_LSO          = (1 << 27),            /* Large Send Offload */
 525 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 526
 527         /* Second doubleword. */
 528         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 529 };
 530
 531 /* 8169, 8168b and 810x except 8102e. */
 532 enum rtl_tx_desc_bit_0 {
 533         /* First doubleword. */
 534 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 535         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 536         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 537         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 538 };
 539
 540 /* 8102e, 8168c and beyond. */
 541 enum rtl_tx_desc_bit_1 {
 542         /* First doubleword. */
 543         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 544         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 545 #define GTTCPHO_SHIFT                   18
 546 #define GTTCPHO_MAX                     0x7fU
 547
 548         /* Second doubleword. */
 549 #define TCPHO_SHIFT                     18
 550 #define TCPHO_MAX                       0x3ffU
 551 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 552         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 553         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 554         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 555         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 556 };
 557
 558 enum rtl_rx_desc_bit {
 559         /* Rx private */
 560         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 561         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 562
 563 #define RxProtoUDP      (PID1)
 564 #define RxProtoTCP      (PID0)
 565 #define RxProtoIP       (PID1 | PID0)
 566 #define RxProtoMask     RxProtoIP
 567
 568         IPFail          = (1 << 16), /* IP checksum failed */
 569         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 570         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 571         RxVlanTag       = (1 << 16), /* VLAN tag available */
 572 };
 573
 574 #define RsvdMask        0x3fffc000
 575 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 576
 577 struct TxDesc {
 578         __le32 opts1;
 579         __le32 opts2;
 580         __le64 addr;
 581 };
 582
 583 struct RxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct ring_info {
 590         struct sk_buff  *skb;
 591         u32             len;
 592 };
 593
 594 struct rtl8169_counters {
 595         __le64  tx_packets;
 596         __le64  rx_packets;
 597         __le64  tx_errors;
 598         __le32  rx_errors;
 599         __le16  rx_missed;
 600         __le16  align_errors;
 601         __le32  tx_one_collision;
 602         __le32  tx_multi_collision;
 603         __le64  rx_unicast;
 604         __le64  rx_broadcast;
 605         __le32  rx_multicast;
 606         __le16  tx_aborted;
 607         __le16  tx_underun;
 608 };
 609
 610 struct rtl8169_tc_offsets {
 611         bool    inited;
 612         __le64  tx_errors;
 613         __le32  tx_multi_collision;
 614         __le16  tx_aborted;
 615 };
 616
 617 enum rtl_flag {
 618         RTL_FLAG_TASK_ENABLED = 0,
 619         RTL_FLAG_TASK_RESET_PENDING,
 620         RTL_FLAG_MAX
 621 };
 622
 623 struct rtl8169_stats {
 624         u64                     packets;
 625         u64                     bytes;
 626         struct u64_stats_sync   syncp;
 627 };
 628
 629 struct rtl8169_private;
 630 typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val);
 631 typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg);
 632
 633 struct rtl8169_private {
 634         void __iomem *mmio_addr;        /* memory map physical address */
 635         struct pci_dev *pci_dev;
 636         struct net_device *dev;
 637         struct phy_device *phydev;
 638         struct napi_struct napi;
 639         u32 msg_enable;
 640         enum mac_version mac_version;
 641         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 642         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 643         u32 dirty_tx;
 644         struct rtl8169_stats rx_stats;
 645         struct rtl8169_stats tx_stats;
 646         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 647         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 648         dma_addr_t TxPhyAddr;
 649         dma_addr_t RxPhyAddr;
 650         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 651         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 652         u16 cp_cmd;
 653
 654         u16 irq_mask;
 655         const struct rtl_coalesce_info *coalesce_info;
 656         struct clk *clk;
 657
 658         void (*hw_start)(struct rtl8169_private *tp);
 659
 660         struct {
 661                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 662                 struct mutex mutex;
 663                 struct work_struct work;
 664         } wk;
 665
 666         unsigned irq_enabled:1;
 667         unsigned supports_gmii:1;
 668         dma_addr_t counters_phys_addr;
 669         struct rtl8169_counters *counters;
 670         struct rtl8169_tc_offsets tc_offset;
 671         u32 saved_wolopts;
 672
 673         const char *fw_name;
 674         struct rtl_fw {
 675                 rtl_fw_write_t phy_write;
 676                 rtl_fw_read_t phy_read;
 677                 rtl_fw_write_t mac_mcu_write;
 678                 rtl_fw_read_t mac_mcu_read;
 679                 const struct firmware *fw;
 680
 681 #define RTL_VER_SIZE            32
 682
 683                 char version[RTL_VER_SIZE];
 684
 685                 struct rtl_fw_phy_action {
 686                         __le32 *code;
 687                         size_t size;
 688                 } phy_action;
 689         } *rtl_fw;
 690
 691         u32 ocp_base;
 692 };
 693
 694 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 695
 696 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 697 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 698 module_param_named(debug, debug.msg_enable, int, 0);
 699 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 700 MODULE_SOFTDEP("pre: realtek");
 701 MODULE_LICENSE("GPL");
 702 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 703 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 704 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 705 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 706 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 707 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 708 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 709 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 710 MODULE_FIRMWARE(FIRMWARE_8402_1);
 711 MODULE_FIRMWARE(FIRMWARE_8411_1);
 712 MODULE_FIRMWARE(FIRMWARE_8411_2);
 713 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 714 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 715 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 716 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 717 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 719 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 720 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 721
 722 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 723 {
 724         return &tp->pci_dev->dev;
 725 }
 726
 727 static void rtl_lock_work(struct rtl8169_private *tp)
 728 {
 729         mutex_lock(&tp->wk.mutex);
 730 }
 731
 732 static void rtl_unlock_work(struct rtl8169_private *tp)
 733 {
 734         mutex_unlock(&tp->wk.mutex);
 735 }
 736
 737 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 738 {
 739         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 740 }
 741
 742 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 743 {
 744         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 745 }
 746
 747 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 748 {
 749         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 750                                            PCI_EXP_DEVCTL_READRQ, force);
 751 }
 752
 753 struct rtl_cond {
 754         bool (*check)(struct rtl8169_private *);
 755         const char *msg;
 756 };
 757
 758 static void rtl_udelay(unsigned int d)
 759 {
 760         udelay(d);
 761 }
 762
 763 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 764                           void (*delay)(unsigned int), unsigned int d, int n,
 765                           bool high)
 766 {
 767         int i;
 768
 769         for (i = 0; i < n; i++) {
 770                 if (c->check(tp) == high)
 771                         return true;
 772                 delay(d);
 773         }
 774         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 775                   c->msg, !high, n, d);
 776         return false;
 777 }
 778
 779 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 780                                       const struct rtl_cond *c,
 781                                       unsigned int d, int n)
 782 {
 783         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 784 }
 785
 786 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 787                                      const struct rtl_cond *c,
 788                                      unsigned int d, int n)
 789 {
 790         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 791 }
 792
 793 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 794                                       const struct rtl_cond *c,
 795                                       unsigned int d, int n)
 796 {
 797         return rtl_loop_wait(tp, c, msleep, d, n, true);
 798 }
 799
 800 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 801                                      const struct rtl_cond *c,
 802                                      unsigned int d, int n)
 803 {
 804         return rtl_loop_wait(tp, c, msleep, d, n, false);
 805 }
 806
 807 #define DECLARE_RTL_COND(name)                          \
 808 static bool name ## _check(struct rtl8169_private *);   \
 809                                                         \
 810 static const struct rtl_cond name = {                   \
 811         .check  = name ## _check,                       \
 812         .msg    = #name                                 \
 813 };                                                      \
 814                                                         \
 815 static bool name ## _check(struct rtl8169_private *tp)
 816
 817 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 818 {
 819         if (reg & 0xffff0001) {
 820                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 821                 return true;
 822         }
 823         return false;
 824 }
 825
 826 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 827 {
 828         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 829 }
 830
 831 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 832 {
 833         if (rtl_ocp_reg_failure(tp, reg))
 834                 return;
 835
 836         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 837
 838         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 839 }
 840
 841 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 842 {
 843         if (rtl_ocp_reg_failure(tp, reg))
 844                 return 0;
 845
 846         RTL_W32(tp, GPHY_OCP, reg << 15);
 847
 848         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 849                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 850 }
 851
 852 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 853 {
 854         if (rtl_ocp_reg_failure(tp, reg))
 855                 return;
 856
 857         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 858 }
 859
 860 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 861 {
 862         if (rtl_ocp_reg_failure(tp, reg))
 863                 return 0;
 864
 865         RTL_W32(tp, OCPDR, reg << 15);
 866
 867         return RTL_R32(tp, OCPDR);
 868 }
 869
 870 #define OCP_STD_PHY_BASE        0xa400
 871
 872 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 873 {
 874         if (reg == 0x1f) {
 875                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 876                 return;
 877         }
 878
 879         if (tp->ocp_base != OCP_STD_PHY_BASE)
 880                 reg -= 0x10;
 881
 882         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 883 }
 884
 885 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 886 {
 887         if (tp->ocp_base != OCP_STD_PHY_BASE)
 888                 reg -= 0x10;
 889
 890         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 891 }
 892
 893 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 894 {
 895         if (reg == 0x1f) {
 896                 tp->ocp_base = value << 4;
 897                 return;
 898         }
 899
 900         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 901 }
 902
 903 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 904 {
 905         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 906 }
 907
 908 DECLARE_RTL_COND(rtl_phyar_cond)
 909 {
 910         return RTL_R32(tp, PHYAR) & 0x80000000;
 911 }
 912
 913 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 914 {
 915         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 916
 917         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 918         /*
 919          * According to hardware specs a 20us delay is required after write
 920          * complete indication, but before sending next command.
 921          */
 922         udelay(20);
 923 }
 924
 925 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 926 {
 927         int value;
 928
 929         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 930
 931         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 932                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 933
 934         /*
 935          * According to hardware specs a 20us delay is required after read
 936          * complete indication, but before sending next command.
 937          */
 938         udelay(20);
 939
 940         return value;
 941 }
 942
 943 DECLARE_RTL_COND(rtl_ocpar_cond)
 944 {
 945         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 946 }
 947
 948 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 949 {
 950         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 951         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 952         RTL_W32(tp, EPHY_RXER_NUM, 0);
 953
 954         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 955 }
 956
 957 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 958 {
 959         r8168dp_1_mdio_access(tp, reg,
 960                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 961 }
 962
 963 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 964 {
 965         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 966
 967         mdelay(1);
 968         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 969         RTL_W32(tp, EPHY_RXER_NUM, 0);
 970
 971         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 972                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 973 }
 974
 975 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 976
 977 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 978 {
 979         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 980 }
 981
 982 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 983 {
 984         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 985 }
 986
 987 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 988 {
 989         r8168dp_2_mdio_start(tp);
 990
 991         r8169_mdio_write(tp, reg, value);
 992
 993         r8168dp_2_mdio_stop(tp);
 994 }
 995
 996 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 997 {
 998         int value;
 999
1000         r8168dp_2_mdio_start(tp);
1001
1002         value = r8169_mdio_read(tp, reg);
1003
1004         r8168dp_2_mdio_stop(tp);
1005
1006         return value;
1007 }
1008
1009 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1010 {
1011         switch (tp->mac_version) {
1012         case RTL_GIGA_MAC_VER_27:
1013                 r8168dp_1_mdio_write(tp, location, val);
1014                 break;
1015         case RTL_GIGA_MAC_VER_28:
1016         case RTL_GIGA_MAC_VER_31:
1017                 r8168dp_2_mdio_write(tp, location, val);
1018                 break;
1019         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1020                 r8168g_mdio_write(tp, location, val);
1021                 break;
1022         default:
1023                 r8169_mdio_write(tp, location, val);
1024                 break;
1025         }
1026 }
1027
1028 static int rtl_readphy(struct rtl8169_private *tp, int location)
1029 {
1030         switch (tp->mac_version) {
1031         case RTL_GIGA_MAC_VER_27:
1032                 return r8168dp_1_mdio_read(tp, location);
1033         case RTL_GIGA_MAC_VER_28:
1034         case RTL_GIGA_MAC_VER_31:
1035                 return r8168dp_2_mdio_read(tp, location);
1036         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1037                 return r8168g_mdio_read(tp, location);
1038         default:
1039                 return r8169_mdio_read(tp, location);
1040         }
1041 }
1042
1043 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1044 {
1045         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1046 }
1047
1048 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1049 {
1050         int val;
1051
1052         val = rtl_readphy(tp, reg_addr);
1053         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1054 }
1055
1056 DECLARE_RTL_COND(rtl_ephyar_cond)
1057 {
1058         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1059 }
1060
1061 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1062 {
1063         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1064                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1065
1066         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1067
1068         udelay(10);
1069 }
1070
1071 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1072 {
1073         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1074
1075         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1076                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1077 }
1078
1079 DECLARE_RTL_COND(rtl_eriar_cond)
1080 {
1081         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1082 }
1083
1084 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1085                            u32 val, int type)
1086 {
1087         BUG_ON((addr & 3) || (mask == 0));
1088         RTL_W32(tp, ERIDR, val);
1089         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1090
1091         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1092 }
1093
1094 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1095                           u32 val)
1096 {
1097         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1098 }
1099
1100 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1101 {
1102         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1103
1104         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1105                 RTL_R32(tp, ERIDR) : ~0;
1106 }
1107
1108 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1109 {
1110         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1111 }
1112
1113 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1114                          u32 m)
1115 {
1116         u32 val;
1117
1118         val = rtl_eri_read(tp, addr);
1119         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1120 }
1121
1122 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1123                              u32 p)
1124 {
1125         rtl_w0w1_eri(tp, addr, mask, p, 0);
1126 }
1127
1128 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1129                                u32 m)
1130 {
1131         rtl_w0w1_eri(tp, addr, mask, 0, m);
1132 }
1133
1134 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1135 {
1136         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1137         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1138                 RTL_R32(tp, OCPDR) : ~0;
1139 }
1140
1141 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1142 {
1143         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1144 }
1145
1146 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1147                               u32 data)
1148 {
1149         RTL_W32(tp, OCPDR, data);
1150         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1151         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1152 }
1153
1154 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1155                               u32 data)
1156 {
1157         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1158                        data, ERIAR_OOB);
1159 }
1160
1161 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1162 {
1163         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1164
1165         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1166 }
1167
1168 #define OOB_CMD_RESET           0x00
1169 #define OOB_CMD_DRIVER_START    0x05
1170 #define OOB_CMD_DRIVER_STOP     0x06
1171
1172 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1173 {
1174         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1175 }
1176
1177 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1178 {
1179         u16 reg;
1180
1181         reg = rtl8168_get_ocp_reg(tp);
1182
1183         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1184 }
1185
1186 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1187 {
1188         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1189 }
1190
1191 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1192 {
1193         return RTL_R8(tp, IBISR0) & 0x20;
1194 }
1195
1196 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1197 {
1198         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1199         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1200         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1201         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1202 }
1203
1204 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1205 {
1206         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1207         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1208 }
1209
1210 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1211 {
1212         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1213         r8168ep_ocp_write(tp, 0x01, 0x30,
1214                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1215         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1216 }
1217
1218 static void rtl8168_driver_start(struct rtl8169_private *tp)
1219 {
1220         switch (tp->mac_version) {
1221         case RTL_GIGA_MAC_VER_27:
1222         case RTL_GIGA_MAC_VER_28:
1223         case RTL_GIGA_MAC_VER_31:
1224                 rtl8168dp_driver_start(tp);
1225                 break;
1226         case RTL_GIGA_MAC_VER_49:
1227         case RTL_GIGA_MAC_VER_50:
1228         case RTL_GIGA_MAC_VER_51:
1229                 rtl8168ep_driver_start(tp);
1230                 break;
1231         default:
1232                 BUG();
1233                 break;
1234         }
1235 }
1236
1237 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1238 {
1239         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1240         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1241 }
1242
1243 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1244 {
1245         rtl8168ep_stop_cmac(tp);
1246         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1247         r8168ep_ocp_write(tp, 0x01, 0x30,
1248                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1249         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1250 }
1251
1252 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1253 {
1254         switch (tp->mac_version) {
1255         case RTL_GIGA_MAC_VER_27:
1256         case RTL_GIGA_MAC_VER_28:
1257         case RTL_GIGA_MAC_VER_31:
1258                 rtl8168dp_driver_stop(tp);
1259                 break;
1260         case RTL_GIGA_MAC_VER_49:
1261         case RTL_GIGA_MAC_VER_50:
1262         case RTL_GIGA_MAC_VER_51:
1263                 rtl8168ep_driver_stop(tp);
1264                 break;
1265         default:
1266                 BUG();
1267                 break;
1268         }
1269 }
1270
1271 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1272 {
1273         u16 reg = rtl8168_get_ocp_reg(tp);
1274
1275         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1276 }
1277
1278 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1279 {
1280         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1281 }
1282
1283 static bool r8168_check_dash(struct rtl8169_private *tp)
1284 {
1285         switch (tp->mac_version) {
1286         case RTL_GIGA_MAC_VER_27:
1287         case RTL_GIGA_MAC_VER_28:
1288         case RTL_GIGA_MAC_VER_31:
1289                 return r8168dp_check_dash(tp);
1290         case RTL_GIGA_MAC_VER_49:
1291         case RTL_GIGA_MAC_VER_50:
1292         case RTL_GIGA_MAC_VER_51:
1293                 return r8168ep_check_dash(tp);
1294         default:
1295                 return false;
1296         }
1297 }
1298
1299 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1300 {
1301         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1302         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1303 }
1304
1305 DECLARE_RTL_COND(rtl_efusear_cond)
1306 {
1307         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1308 }
1309
1310 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1311 {
1312         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1313
1314         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1315                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1316 }
1317
1318 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1319 {
1320         RTL_W16(tp, IntrStatus, bits);
1321 }
1322
1323 static void rtl_irq_disable(struct rtl8169_private *tp)
1324 {
1325         RTL_W16(tp, IntrMask, 0);
1326         tp->irq_enabled = 0;
1327 }
1328
1329 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1330 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1331 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1332
1333 static void rtl_irq_enable(struct rtl8169_private *tp)
1334 {
1335         tp->irq_enabled = 1;
1336         RTL_W16(tp, IntrMask, tp->irq_mask);
1337 }
1338
1339 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1340 {
1341         rtl_irq_disable(tp);
1342         rtl_ack_events(tp, 0xffff);
1343         /* PCI commit */
1344         RTL_R8(tp, ChipCmd);
1345 }
1346
1347 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1348 {
1349         struct net_device *dev = tp->dev;
1350         struct phy_device *phydev = tp->phydev;
1351
1352         if (!netif_running(dev))
1353                 return;
1354
1355         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1356             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1357                 if (phydev->speed == SPEED_1000) {
1358                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1360                 } else if (phydev->speed == SPEED_100) {
1361                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1362                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1363                 } else {
1364                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1365                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1366                 }
1367                 rtl_reset_packet_filter(tp);
1368         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1369                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1370                 if (phydev->speed == SPEED_1000) {
1371                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1372                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1373                 } else {
1374                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1375                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1376                 }
1377         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1378                 if (phydev->speed == SPEED_10) {
1379                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1380                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1381                 } else {
1382                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1383                 }
1384         }
1385 }
1386
1387 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1388
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1390 {
1391         struct rtl8169_private *tp = netdev_priv(dev);
1392
1393         rtl_lock_work(tp);
1394         wol->supported = WAKE_ANY;
1395         wol->wolopts = tp->saved_wolopts;
1396         rtl_unlock_work(tp);
1397 }
1398
1399 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1400 {
1401         unsigned int i, tmp;
1402         static const struct {
1403                 u32 opt;
1404                 u16 reg;
1405                 u8  mask;
1406         } cfg[] = {
1407                 { WAKE_PHY,   Config3, LinkUp },
1408                 { WAKE_UCAST, Config5, UWF },
1409                 { WAKE_BCAST, Config5, BWF },
1410                 { WAKE_MCAST, Config5, MWF },
1411                 { WAKE_ANY,   Config5, LanWake },
1412                 { WAKE_MAGIC, Config3, MagicPacket }
1413         };
1414         u8 options;
1415
1416         rtl_unlock_config_regs(tp);
1417
1418         switch (tp->mac_version) {
1419         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1420         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1421                 tmp = ARRAY_SIZE(cfg) - 1;
1422                 if (wolopts & WAKE_MAGIC)
1423                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1424                                          MagicPacket_v2);
1425                 else
1426                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1427                                            MagicPacket_v2);
1428                 break;
1429         default:
1430                 tmp = ARRAY_SIZE(cfg);
1431                 break;
1432         }
1433
1434         for (i = 0; i < tmp; i++) {
1435                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1436                 if (wolopts & cfg[i].opt)
1437                         options |= cfg[i].mask;
1438                 RTL_W8(tp, cfg[i].reg, options);
1439         }
1440
1441         switch (tp->mac_version) {
1442         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1443                 options = RTL_R8(tp, Config1) & ~PMEnable;
1444                 if (wolopts)
1445                         options |= PMEnable;
1446                 RTL_W8(tp, Config1, options);
1447                 break;
1448         default:
1449                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1450                 if (wolopts)
1451                         options |= PME_SIGNAL;
1452                 RTL_W8(tp, Config2, options);
1453                 break;
1454         }
1455
1456         rtl_lock_config_regs(tp);
1457
1458         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1459 }
1460
1461 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1462 {
1463         struct rtl8169_private *tp = netdev_priv(dev);
1464         struct device *d = tp_to_dev(tp);
1465
1466         if (wol->wolopts & ~WAKE_ANY)
1467                 return -EINVAL;
1468
1469         pm_runtime_get_noresume(d);
1470
1471         rtl_lock_work(tp);
1472
1473         tp->saved_wolopts = wol->wolopts;
1474
1475         if (pm_runtime_active(d))
1476                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1477
1478         rtl_unlock_work(tp);
1479
1480         pm_runtime_put_noidle(d);
1481
1482         return 0;
1483 }
1484
1485 static void rtl8169_get_drvinfo(struct net_device *dev,
1486                                 struct ethtool_drvinfo *info)
1487 {
1488         struct rtl8169_private *tp = netdev_priv(dev);
1489         struct rtl_fw *rtl_fw = tp->rtl_fw;
1490
1491         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1492         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1493         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1494         if (rtl_fw)
1495                 strlcpy(info->fw_version, rtl_fw->version,
1496                         sizeof(info->fw_version));
1497 }
1498
1499 static int rtl8169_get_regs_len(struct net_device *dev)
1500 {
1501         return R8169_REGS_SIZE;
1502 }
1503
1504 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1505         netdev_features_t features)
1506 {
1507         struct rtl8169_private *tp = netdev_priv(dev);
1508
1509         if (dev->mtu > TD_MSS_MAX)
1510                 features &= ~NETIF_F_ALL_TSO;
1511
1512         if (dev->mtu > JUMBO_1K &&
1513             tp->mac_version > RTL_GIGA_MAC_VER_06)
1514                 features &= ~NETIF_F_IP_CSUM;
1515
1516         return features;
1517 }
1518
1519 static int rtl8169_set_features(struct net_device *dev,
1520                                 netdev_features_t features)
1521 {
1522         struct rtl8169_private *tp = netdev_priv(dev);
1523         u32 rx_config;
1524
1525         rtl_lock_work(tp);
1526
1527         rx_config = RTL_R32(tp, RxConfig);
1528         if (features & NETIF_F_RXALL)
1529                 rx_config |= (AcceptErr | AcceptRunt);
1530         else
1531                 rx_config &= ~(AcceptErr | AcceptRunt);
1532
1533         RTL_W32(tp, RxConfig, rx_config);
1534
1535         if (features & NETIF_F_RXCSUM)
1536                 tp->cp_cmd |= RxChkSum;
1537         else
1538                 tp->cp_cmd &= ~RxChkSum;
1539
1540         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1541                 tp->cp_cmd |= RxVlan;
1542         else
1543                 tp->cp_cmd &= ~RxVlan;
1544
1545         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1546         RTL_R16(tp, CPlusCmd);
1547
1548         rtl_unlock_work(tp);
1549
1550         return 0;
1551 }
1552
1553 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1554 {
1555         return (skb_vlan_tag_present(skb)) ?
1556                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1557 }
1558
1559 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1560 {
1561         u32 opts2 = le32_to_cpu(desc->opts2);
1562
1563         if (opts2 & RxVlanTag)
1564                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1565 }
1566
1567 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1568                              void *p)
1569 {
1570         struct rtl8169_private *tp = netdev_priv(dev);
1571         u32 __iomem *data = tp->mmio_addr;
1572         u32 *dw = p;
1573         int i;
1574
1575         rtl_lock_work(tp);
1576         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1577                 memcpy_fromio(dw++, data++, 4);
1578         rtl_unlock_work(tp);
1579 }
1580
1581 static u32 rtl8169_get_msglevel(struct net_device *dev)
1582 {
1583         struct rtl8169_private *tp = netdev_priv(dev);
1584
1585         return tp->msg_enable;
1586 }
1587
1588 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1589 {
1590         struct rtl8169_private *tp = netdev_priv(dev);
1591
1592         tp->msg_enable = value;
1593 }
1594
1595 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1596         "tx_packets",
1597         "rx_packets",
1598         "tx_errors",
1599         "rx_errors",
1600         "rx_missed",
1601         "align_errors",
1602         "tx_single_collisions",
1603         "tx_multi_collisions",
1604         "unicast",
1605         "broadcast",
1606         "multicast",
1607         "tx_aborted",
1608         "tx_underrun",
1609 };
1610
1611 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1612 {
1613         switch (sset) {
1614         case ETH_SS_STATS:
1615                 return ARRAY_SIZE(rtl8169_gstrings);
1616         default:
1617                 return -EOPNOTSUPP;
1618         }
1619 }
1620
1621 DECLARE_RTL_COND(rtl_counters_cond)
1622 {
1623         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1624 }
1625
1626 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1627 {
1628         dma_addr_t paddr = tp->counters_phys_addr;
1629         u32 cmd;
1630
1631         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1632         RTL_R32(tp, CounterAddrHigh);
1633         cmd = (u64)paddr & DMA_BIT_MASK(32);
1634         RTL_W32(tp, CounterAddrLow, cmd);
1635         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1636
1637         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1638 }
1639
1640 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1641 {
1642         /*
1643          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1644          * tally counters.
1645          */
1646         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1647                 return true;
1648
1649         return rtl8169_do_counters(tp, CounterReset);
1650 }
1651
1652 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1653 {
1654         u8 val = RTL_R8(tp, ChipCmd);
1655
1656         /*
1657          * Some chips are unable to dump tally counters when the receiver
1658          * is disabled. If 0xff chip may be in a PCI power-save state.
1659          */
1660         if (!(val & CmdRxEnb) || val == 0xff)
1661                 return true;
1662
1663         return rtl8169_do_counters(tp, CounterDump);
1664 }
1665
1666 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1667 {
1668         struct rtl8169_counters *counters = tp->counters;
1669         bool ret = false;
1670
1671         /*
1672          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1673          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1674          * reset by a power cycle, while the counter values collected by the
1675          * driver are reset at every driver unload/load cycle.
1676          *
1677          * To make sure the HW values returned by @get_stats64 match the SW
1678          * values, we collect the initial values at first open(*) and use them
1679          * as offsets to normalize the values returned by @get_stats64.
1680          *
1681          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1682          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1683          * set at open time by rtl_hw_start.
1684          */
1685
1686         if (tp->tc_offset.inited)
1687                 return true;
1688
1689         /* If both, reset and update fail, propagate to caller. */
1690         if (rtl8169_reset_counters(tp))
1691                 ret = true;
1692
1693         if (rtl8169_update_counters(tp))
1694                 ret = true;
1695
1696         tp->tc_offset.tx_errors = counters->tx_errors;
1697         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1698         tp->tc_offset.tx_aborted = counters->tx_aborted;
1699         tp->tc_offset.inited = true;
1700
1701         return ret;
1702 }
1703
1704 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1705                                       struct ethtool_stats *stats, u64 *data)
1706 {
1707         struct rtl8169_private *tp = netdev_priv(dev);
1708         struct device *d = tp_to_dev(tp);
1709         struct rtl8169_counters *counters = tp->counters;
1710
1711         ASSERT_RTNL();
1712
1713         pm_runtime_get_noresume(d);
1714
1715         if (pm_runtime_active(d))
1716                 rtl8169_update_counters(tp);
1717
1718         pm_runtime_put_noidle(d);
1719
1720         data[0] = le64_to_cpu(counters->tx_packets);
1721         data[1] = le64_to_cpu(counters->rx_packets);
1722         data[2] = le64_to_cpu(counters->tx_errors);
1723         data[3] = le32_to_cpu(counters->rx_errors);
1724         data[4] = le16_to_cpu(counters->rx_missed);
1725         data[5] = le16_to_cpu(counters->align_errors);
1726         data[6] = le32_to_cpu(counters->tx_one_collision);
1727         data[7] = le32_to_cpu(counters->tx_multi_collision);
1728         data[8] = le64_to_cpu(counters->rx_unicast);
1729         data[9] = le64_to_cpu(counters->rx_broadcast);
1730         data[10] = le32_to_cpu(counters->rx_multicast);
1731         data[11] = le16_to_cpu(counters->tx_aborted);
1732         data[12] = le16_to_cpu(counters->tx_underun);
1733 }
1734
1735 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1736 {
1737         switch(stringset) {
1738         case ETH_SS_STATS:
1739                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1740                 break;
1741         }
1742 }
1743
1744 /*
1745  * Interrupt coalescing
1746  *
1747  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1748  * >     8169, 8168 and 810x line of chipsets
1749  *
1750  * 8169, 8168, and 8136(810x) serial chipsets support it.
1751  *
1752  * > 2 - the Tx timer unit at gigabit speed
1753  *
1754  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1755  * (0xe0) bit 1 and bit 0.
1756  *
1757  * For 8169
1758  * bit[1:0] \ speed        1000M           100M            10M
1759  * 0 0                     320ns           2.56us          40.96us
1760  * 0 1                     2.56us          20.48us         327.7us
1761  * 1 0                     5.12us          40.96us         655.4us
1762  * 1 1                     10.24us         81.92us         1.31ms
1763  *
1764  * For the other
1765  * bit[1:0] \ speed        1000M           100M            10M
1766  * 0 0                     5us             2.56us          40.96us
1767  * 0 1                     40us            20.48us         327.7us
1768  * 1 0                     80us            40.96us         655.4us
1769  * 1 1                     160us           81.92us         1.31ms
1770  */
1771
1772 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1773 struct rtl_coalesce_scale {
1774         /* Rx / Tx */
1775         u32 nsecs[2];
1776 };
1777
1778 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1779 struct rtl_coalesce_info {
1780         u32 speed;
1781         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1782 };
1783
1784 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1785 #define rxtx_x1822(r, t) {              \
1786         {{(r),          (t)}},          \
1787         {{(r)*8,        (t)*8}},        \
1788         {{(r)*8*2,      (t)*8*2}},      \
1789         {{(r)*8*2*2,    (t)*8*2*2}},    \
1790 }
1791 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1792         /* speed        delays:     rx00   tx00 */
1793         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1794         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1795         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1796         { 0 },
1797 };
1798
1799 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1800         /* speed        delays:     rx00   tx00 */
1801         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1802         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1803         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1804         { 0 },
1805 };
1806 #undef rxtx_x1822
1807
1808 /* get rx/tx scale vector corresponding to current speed */
1809 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1810 {
1811         struct rtl8169_private *tp = netdev_priv(dev);
1812         struct ethtool_link_ksettings ecmd;
1813         const struct rtl_coalesce_info *ci;
1814         int rc;
1815
1816         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1817         if (rc < 0)
1818                 return ERR_PTR(rc);
1819
1820         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1821                 if (ecmd.base.speed == ci->speed) {
1822                         return ci;
1823                 }
1824         }
1825
1826         return ERR_PTR(-ELNRNG);
1827 }
1828
1829 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1830 {
1831         struct rtl8169_private *tp = netdev_priv(dev);
1832         const struct rtl_coalesce_info *ci;
1833         const struct rtl_coalesce_scale *scale;
1834         struct {
1835                 u32 *max_frames;
1836                 u32 *usecs;
1837         } coal_settings [] = {
1838                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1839                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1840         }, *p = coal_settings;
1841         int i;
1842         u16 w;
1843
1844         memset(ec, 0, sizeof(*ec));
1845
1846         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1847         ci = rtl_coalesce_info(dev);
1848         if (IS_ERR(ci))
1849                 return PTR_ERR(ci);
1850
1851         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1852
1853         /* read IntrMitigate and adjust according to scale */
1854         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1855                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1856                 w >>= RTL_COALESCE_SHIFT;
1857                 *p->usecs = w & RTL_COALESCE_MASK;
1858         }
1859
1860         for (i = 0; i < 2; i++) {
1861                 p = coal_settings + i;
1862                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1863
1864                 /*
1865                  * ethtool_coalesce says it is illegal to set both usecs and
1866                  * max_frames to 0.
1867                  */
1868                 if (!*p->usecs && !*p->max_frames)
1869                         *p->max_frames = 1;
1870         }
1871
1872         return 0;
1873 }
1874
1875 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1876 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1877                         struct net_device *dev, u32 nsec, u16 *cp01)
1878 {
1879         const struct rtl_coalesce_info *ci;
1880         u16 i;
1881
1882         ci = rtl_coalesce_info(dev);
1883         if (IS_ERR(ci))
1884                 return ERR_CAST(ci);
1885
1886         for (i = 0; i < 4; i++) {
1887                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1888                                         ci->scalev[i].nsecs[1]);
1889                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1890                         *cp01 = i;
1891                         return &ci->scalev[i];
1892                 }
1893         }
1894
1895         return ERR_PTR(-EINVAL);
1896 }
1897
1898 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1899 {
1900         struct rtl8169_private *tp = netdev_priv(dev);
1901         const struct rtl_coalesce_scale *scale;
1902         struct {
1903                 u32 frames;
1904                 u32 usecs;
1905         } coal_settings [] = {
1906                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1907                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1908         }, *p = coal_settings;
1909         u16 w = 0, cp01;
1910         int i;
1911
1912         scale = rtl_coalesce_choose_scale(dev,
1913                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1914         if (IS_ERR(scale))
1915                 return PTR_ERR(scale);
1916
1917         for (i = 0; i < 2; i++, p++) {
1918                 u32 units;
1919
1920                 /*
1921                  * accept max_frames=1 we returned in rtl_get_coalesce.
1922                  * accept it not only when usecs=0 because of e.g. the following scenario:
1923                  *
1924                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1925                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1926                  * - then user does `ethtool -C eth0 rx-usecs 100`
1927                  *
1928                  * since ethtool sends to kernel whole ethtool_coalesce
1929                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1930                  * we'll reject it below in `frames % 4 != 0`.
1931                  */
1932                 if (p->frames == 1) {
1933                         p->frames = 0;
1934                 }
1935
1936                 units = p->usecs * 1000 / scale->nsecs[i];
1937                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1938                         return -EINVAL;
1939
1940                 w <<= RTL_COALESCE_SHIFT;
1941                 w |= units;
1942                 w <<= RTL_COALESCE_SHIFT;
1943                 w |= p->frames >> 2;
1944         }
1945
1946         rtl_lock_work(tp);
1947
1948         RTL_W16(tp, IntrMitigate, swab16(w));
1949
1950         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1951         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1952         RTL_R16(tp, CPlusCmd);
1953
1954         rtl_unlock_work(tp);
1955
1956         return 0;
1957 }
1958
1959 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1960 {
1961         struct phy_device *phydev = tp->phydev;
1962         int ret;
1963
1964         switch (tp->mac_version) {
1965         case RTL_GIGA_MAC_VER_34:
1966         case RTL_GIGA_MAC_VER_35:
1967         case RTL_GIGA_MAC_VER_36:
1968         case RTL_GIGA_MAC_VER_38:
1969                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1970                 break;
1971         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1972                 phy_write(phydev, 0x1f, 0x0a5c);
1973                 ret = phy_read(phydev, 0x12);
1974                 phy_write(phydev, 0x1f, 0x0000);
1975                 break;
1976         default:
1977                 ret = -EPROTONOSUPPORT;
1978                 break;
1979         }
1980
1981         return ret;
1982 }
1983
1984 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1985 {
1986         struct phy_device *phydev = tp->phydev;
1987         int ret;
1988
1989         switch (tp->mac_version) {
1990         case RTL_GIGA_MAC_VER_34:
1991         case RTL_GIGA_MAC_VER_35:
1992         case RTL_GIGA_MAC_VER_36:
1993         case RTL_GIGA_MAC_VER_38:
1994                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1995                 break;
1996         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1997                 phy_write(phydev, 0x1f, 0x0a5d);
1998                 ret = phy_read(phydev, 0x11);
1999                 phy_write(phydev, 0x1f, 0x0000);
2000                 break;
2001         default:
2002                 ret = -EPROTONOSUPPORT;
2003                 break;
2004         }
2005
2006         return ret;
2007 }
2008
2009 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2010 {
2011         struct phy_device *phydev = tp->phydev;
2012         int ret;
2013
2014         switch (tp->mac_version) {
2015         case RTL_GIGA_MAC_VER_34:
2016         case RTL_GIGA_MAC_VER_35:
2017         case RTL_GIGA_MAC_VER_36:
2018         case RTL_GIGA_MAC_VER_38:
2019                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2020                 break;
2021         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2022                 phy_write(phydev, 0x1f, 0x0a5d);
2023                 ret = phy_read(phydev, 0x10);
2024                 phy_write(phydev, 0x1f, 0x0000);
2025                 break;
2026         default:
2027                 ret = -EPROTONOSUPPORT;
2028                 break;
2029         }
2030
2031         return ret;
2032 }
2033
2034 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2035 {
2036         struct phy_device *phydev = tp->phydev;
2037         int ret = 0;
2038
2039         switch (tp->mac_version) {
2040         case RTL_GIGA_MAC_VER_34:
2041         case RTL_GIGA_MAC_VER_35:
2042         case RTL_GIGA_MAC_VER_36:
2043         case RTL_GIGA_MAC_VER_38:
2044                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2045                 break;
2046         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2047                 phy_write(phydev, 0x1f, 0x0a5d);
2048                 phy_write(phydev, 0x10, val);
2049                 phy_write(phydev, 0x1f, 0x0000);
2050                 break;
2051         default:
2052                 ret = -EPROTONOSUPPORT;
2053                 break;
2054         }
2055
2056         return ret;
2057 }
2058
2059 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2060 {
2061         struct rtl8169_private *tp = netdev_priv(dev);
2062         struct device *d = tp_to_dev(tp);
2063         int ret;
2064
2065         pm_runtime_get_noresume(d);
2066
2067         if (!pm_runtime_active(d)) {
2068                 ret = -EOPNOTSUPP;
2069                 goto out;
2070         }
2071
2072         /* Get Supported EEE */
2073         ret = rtl_get_eee_supp(tp);
2074         if (ret < 0)
2075                 goto out;
2076         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2077
2078         /* Get advertisement EEE */
2079         ret = rtl_get_eee_adv(tp);
2080         if (ret < 0)
2081                 goto out;
2082         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2083         data->eee_enabled = !!data->advertised;
2084
2085         /* Get LP advertisement EEE */
2086         ret = rtl_get_eee_lpadv(tp);
2087         if (ret < 0)
2088                 goto out;
2089         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2090         data->eee_active = !!(data->advertised & data->lp_advertised);
2091 out:
2092         pm_runtime_put_noidle(d);
2093         return ret < 0 ? ret : 0;
2094 }
2095
2096 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2097 {
2098         struct rtl8169_private *tp = netdev_priv(dev);
2099         struct device *d = tp_to_dev(tp);
2100         int old_adv, adv = 0, cap, ret;
2101
2102         pm_runtime_get_noresume(d);
2103
2104         if (!dev->phydev || !pm_runtime_active(d)) {
2105                 ret = -EOPNOTSUPP;
2106                 goto out;
2107         }
2108
2109         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2110             dev->phydev->duplex != DUPLEX_FULL) {
2111                 ret = -EPROTONOSUPPORT;
2112                 goto out;
2113         }
2114
2115         /* Get Supported EEE */
2116         ret = rtl_get_eee_supp(tp);
2117         if (ret < 0)
2118                 goto out;
2119         cap = ret;
2120
2121         ret = rtl_get_eee_adv(tp);
2122         if (ret < 0)
2123                 goto out;
2124         old_adv = ret;
2125
2126         if (data->eee_enabled) {
2127                 adv = !data->advertised ? cap :
2128                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2129                 /* Mask prohibited EEE modes */
2130                 adv &= ~dev->phydev->eee_broken_modes;
2131         }
2132
2133         if (old_adv != adv) {
2134                 ret = rtl_set_eee_adv(tp, adv);
2135                 if (ret < 0)
2136                         goto out;
2137
2138                 /* Restart autonegotiation so the new modes get sent to the
2139                  * link partner.
2140                  */
2141                 ret = phy_restart_aneg(dev->phydev);
2142         }
2143
2144 out:
2145         pm_runtime_put_noidle(d);
2146         return ret < 0 ? ret : 0;
2147 }
2148
2149 static const struct ethtool_ops rtl8169_ethtool_ops = {
2150         .get_drvinfo            = rtl8169_get_drvinfo,
2151         .get_regs_len           = rtl8169_get_regs_len,
2152         .get_link               = ethtool_op_get_link,
2153         .get_coalesce           = rtl_get_coalesce,
2154         .set_coalesce           = rtl_set_coalesce,
2155         .get_msglevel           = rtl8169_get_msglevel,
2156         .set_msglevel           = rtl8169_set_msglevel,
2157         .get_regs               = rtl8169_get_regs,
2158         .get_wol                = rtl8169_get_wol,
2159         .set_wol                = rtl8169_set_wol,
2160         .get_strings            = rtl8169_get_strings,
2161         .get_sset_count         = rtl8169_get_sset_count,
2162         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2163         .get_ts_info            = ethtool_op_get_ts_info,
2164         .nway_reset             = phy_ethtool_nway_reset,
2165         .get_eee                = rtl8169_get_eee,
2166         .set_eee                = rtl8169_set_eee,
2167         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2168         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2169 };
2170
2171 static void rtl_enable_eee(struct rtl8169_private *tp)
2172 {
2173         int supported = rtl_get_eee_supp(tp);
2174
2175         if (supported > 0)
2176                 rtl_set_eee_adv(tp, supported);
2177 }
2178
2179 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2180 {
2181         /*
2182          * The driver currently handles the 8168Bf and the 8168Be identically
2183          * but they can be identified more specifically through the test below
2184          * if needed:
2185          *
2186          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2187          *
2188          * Same thing for the 8101Eb and the 8101Ec:
2189          *
2190          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2191          */
2192         static const struct rtl_mac_info {
2193                 u16 mask;
2194                 u16 val;
2195                 u16 mac_version;
2196         } mac_info[] = {
2197                 /* 8168EP family. */
2198                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2199                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2200                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2201
2202                 /* 8168H family. */
2203                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2204                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2205
2206                 /* 8168G family. */
2207                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2208                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2209                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2210                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2211
2212                 /* 8168F family. */
2213                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2214                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2215                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2216
2217                 /* 8168E family. */
2218                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2219                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2220                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2221
2222                 /* 8168D family. */
2223                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2224                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2225
2226                 /* 8168DP family. */
2227                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2228                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2229                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2230
2231                 /* 8168C family. */
2232                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2233                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2234                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2235                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2236                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2237                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2238                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2239
2240                 /* 8168B family. */
2241                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2242                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2243                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2244
2245                 /* 8101 family. */
2246                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2247                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2248                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2249                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2250                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2251                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2252                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2253                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2254                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2255                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2256                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2257                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2258                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2259                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2260                 /* FIXME: where did these entries come from ? -- FR */
2261                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2262                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2263
2264                 /* 8110 family. */
2265                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2266                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2267                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2268                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2269                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2270
2271                 /* Catch-all */
2272                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2273         };
2274         const struct rtl_mac_info *p = mac_info;
2275         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2276
2277         while ((reg & p->mask) != p->val)
2278                 p++;
2279         tp->mac_version = p->mac_version;
2280
2281         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2282                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2283         } else if (!tp->supports_gmii) {
2284                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2285                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2286                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2287                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2288                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2289                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2290         }
2291 }
2292
2293 struct phy_reg {
2294         u16 reg;
2295         u16 val;
2296 };
2297
2298 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2299                                  const struct phy_reg *regs, int len)
2300 {
2301         while (len-- > 0) {
2302                 rtl_writephy(tp, regs->reg, regs->val);
2303                 regs++;
2304         }
2305 }
2306
2307 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2308
2309 #define PHY_READ                0x00000000
2310 #define PHY_DATA_OR             0x10000000
2311 #define PHY_DATA_AND            0x20000000
2312 #define PHY_BJMPN               0x30000000
2313 #define PHY_MDIO_CHG            0x40000000
2314 #define PHY_CLEAR_READCOUNT     0x70000000
2315 #define PHY_WRITE               0x80000000
2316 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2317 #define PHY_COMP_EQ_SKIPN       0xa0000000
2318 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2319 #define PHY_WRITE_PREVIOUS      0xc0000000
2320 #define PHY_SKIPN               0xd0000000
2321 #define PHY_DELAY_MS            0xe0000000
2322
2323 struct fw_info {
2324         u32     magic;
2325         char    version[RTL_VER_SIZE];
2326         __le32  fw_start;
2327         __le32  fw_len;
2328         u8      chksum;
2329 } __packed;
2330
2331 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2332
2333 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2334 {
2335         const struct firmware *fw = rtl_fw->fw;
2336         struct fw_info *fw_info = (struct fw_info *)fw->data;
2337         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2338
2339         if (fw->size < FW_OPCODE_SIZE)
2340                 return false;
2341
2342         if (!fw_info->magic) {
2343                 size_t i, size, start;
2344                 u8 checksum = 0;
2345
2346                 if (fw->size < sizeof(*fw_info))
2347                         return false;
2348
2349                 for (i = 0; i < fw->size; i++)
2350                         checksum += fw->data[i];
2351                 if (checksum != 0)
2352                         return false;
2353
2354                 start = le32_to_cpu(fw_info->fw_start);
2355                 if (start > fw->size)
2356                         return false;
2357
2358                 size = le32_to_cpu(fw_info->fw_len);
2359                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2360                         return false;
2361
2362                 strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
2363
2364                 pa->code = (__le32 *)(fw->data + start);
2365                 pa->size = size;
2366         } else {
2367                 if (fw->size % FW_OPCODE_SIZE)
2368                         return false;
2369
2370                 strscpy(rtl_fw->version, tp->fw_name, RTL_VER_SIZE);
2371
2372                 pa->code = (__le32 *)fw->data;
2373                 pa->size = fw->size / FW_OPCODE_SIZE;
2374         }
2375
2376         return true;
2377 }
2378
2379 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2380                            struct rtl_fw_phy_action *pa)
2381 {
2382         bool rc = false;
2383         size_t index;
2384
2385         for (index = 0; index < pa->size; index++) {
2386                 u32 action = le32_to_cpu(pa->code[index]);
2387                 u32 regno = (action & 0x0fff0000) >> 16;
2388
2389                 switch(action & 0xf0000000) {
2390                 case PHY_READ:
2391                 case PHY_DATA_OR:
2392                 case PHY_DATA_AND:
2393                 case PHY_MDIO_CHG:
2394                 case PHY_CLEAR_READCOUNT:
2395                 case PHY_WRITE:
2396                 case PHY_WRITE_PREVIOUS:
2397                 case PHY_DELAY_MS:
2398                         break;
2399
2400                 case PHY_BJMPN:
2401                         if (regno > index) {
2402                                 netif_err(tp, ifup, tp->dev,
2403                                           "Out of range of firmware\n");
2404                                 goto out;
2405                         }
2406                         break;
2407                 case PHY_READCOUNT_EQ_SKIP:
2408                         if (index + 2 >= pa->size) {
2409                                 netif_err(tp, ifup, tp->dev,
2410                                           "Out of range of firmware\n");
2411                                 goto out;
2412                         }
2413                         break;
2414                 case PHY_COMP_EQ_SKIPN:
2415                 case PHY_COMP_NEQ_SKIPN:
2416                 case PHY_SKIPN:
2417                         if (index + 1 + regno >= pa->size) {
2418                                 netif_err(tp, ifup, tp->dev,
2419                                           "Out of range of firmware\n");
2420                                 goto out;
2421                         }
2422                         break;
2423
2424                 default:
2425                         netif_err(tp, ifup, tp->dev,
2426                                   "Invalid action 0x%08x\n", action);
2427                         goto out;
2428                 }
2429         }
2430         rc = true;
2431 out:
2432         return rc;
2433 }
2434
2435 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2436 {
2437         struct net_device *dev = tp->dev;
2438         int rc = -EINVAL;
2439
2440         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2441                 netif_err(tp, ifup, dev, "invalid firmware\n");
2442                 goto out;
2443         }
2444
2445         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2446                 rc = 0;
2447 out:
2448         return rc;
2449 }
2450
2451 static void rtl_fw_write_firmware(struct rtl8169_private *tp,
2452                                   struct rtl_fw *rtl_fw)
2453 {
2454         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2455         rtl_fw_write_t fw_write = rtl_fw->phy_write;
2456         rtl_fw_read_t fw_read = rtl_fw->phy_read;
2457         int predata = 0, count = 0;
2458         size_t index;
2459
2460         for (index = 0; index < pa->size; ) {
2461                 u32 action = le32_to_cpu(pa->code[index]);
2462                 u32 data = action & 0x0000ffff;
2463                 u32 regno = (action & 0x0fff0000) >> 16;
2464
2465                 if (!action)
2466                         break;
2467
2468                 switch(action & 0xf0000000) {
2469                 case PHY_READ:
2470                         predata = fw_read(tp, regno);
2471                         count++;
2472                         index++;
2473                         break;
2474                 case PHY_DATA_OR:
2475                         predata |= data;
2476                         index++;
2477                         break;
2478                 case PHY_DATA_AND:
2479                         predata &= data;
2480                         index++;
2481                         break;
2482                 case PHY_BJMPN:
2483                         index -= regno;
2484                         break;
2485                 case PHY_MDIO_CHG:
2486                         if (data == 0) {
2487                                 fw_write = rtl_fw->phy_write;
2488                                 fw_read = rtl_fw->phy_read;
2489                         } else if (data == 1) {
2490                                 fw_write = rtl_fw->mac_mcu_write;
2491                                 fw_read = rtl_fw->mac_mcu_read;
2492                         }
2493
2494                         index++;
2495                         break;
2496                 case PHY_CLEAR_READCOUNT:
2497                         count = 0;
2498                         index++;
2499                         break;
2500                 case PHY_WRITE:
2501                         fw_write(tp, regno, data);
2502                         index++;
2503                         break;
2504                 case PHY_READCOUNT_EQ_SKIP:
2505                         index += (count == data) ? 2 : 1;
2506                         break;
2507                 case PHY_COMP_EQ_SKIPN:
2508                         if (predata == data)
2509                                 index += regno;
2510                         index++;
2511                         break;
2512                 case PHY_COMP_NEQ_SKIPN:
2513                         if (predata != data)
2514                                 index += regno;
2515                         index++;
2516                         break;
2517                 case PHY_WRITE_PREVIOUS:
2518                         fw_write(tp, regno, predata);
2519                         index++;
2520                         break;
2521                 case PHY_SKIPN:
2522                         index += regno + 1;
2523                         break;
2524                 case PHY_DELAY_MS:
2525                         mdelay(data);
2526                         index++;
2527                         break;
2528
2529                 default:
2530                         BUG();
2531                 }
2532         }
2533 }
2534
2535 static void rtl_release_firmware(struct rtl8169_private *tp)
2536 {
2537         if (tp->rtl_fw) {
2538                 release_firmware(tp->rtl_fw->fw);
2539                 kfree(tp->rtl_fw);
2540                 tp->rtl_fw = NULL;
2541         }
2542 }
2543
2544 static void rtl_apply_firmware(struct rtl8169_private *tp)
2545 {
2546         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2547         if (tp->rtl_fw)
2548                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2549 }
2550
2551 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2552 {
2553         if (rtl_readphy(tp, reg) != val)
2554                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2555         else
2556                 rtl_apply_firmware(tp);
2557 }
2558
2559 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2560 {
2561         /* Adjust EEE LED frequency */
2562         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2563                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2564
2565         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2566 }
2567
2568 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2569 {
2570         struct phy_device *phydev = tp->phydev;
2571
2572         phy_write(phydev, 0x1f, 0x0007);
2573         phy_write(phydev, 0x1e, 0x0020);
2574         phy_set_bits(phydev, 0x15, BIT(8));
2575
2576         phy_write(phydev, 0x1f, 0x0005);
2577         phy_write(phydev, 0x05, 0x8b85);
2578         phy_set_bits(phydev, 0x06, BIT(13));
2579
2580         phy_write(phydev, 0x1f, 0x0000);
2581 }
2582
2583 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2584 {
2585         phy_write(tp->phydev, 0x1f, 0x0a43);
2586         phy_set_bits(tp->phydev, 0x11, BIT(4));
2587         phy_write(tp->phydev, 0x1f, 0x0000);
2588 }
2589
2590 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2591 {
2592         static const struct phy_reg phy_reg_init[] = {
2593                 { 0x1f, 0x0001 },
2594                 { 0x06, 0x006e },
2595                 { 0x08, 0x0708 },
2596                 { 0x15, 0x4000 },
2597                 { 0x18, 0x65c7 },
2598
2599                 { 0x1f, 0x0001 },
2600                 { 0x03, 0x00a1 },
2601                 { 0x02, 0x0008 },
2602                 { 0x01, 0x0120 },
2603                 { 0x00, 0x1000 },
2604                 { 0x04, 0x0800 },
2605                 { 0x04, 0x0000 },
2606
2607                 { 0x03, 0xff41 },
2608                 { 0x02, 0xdf60 },
2609                 { 0x01, 0x0140 },
2610                 { 0x00, 0x0077 },
2611                 { 0x04, 0x7800 },
2612                 { 0x04, 0x7000 },
2613
2614                 { 0x03, 0x802f },
2615                 { 0x02, 0x4f02 },
2616                 { 0x01, 0x0409 },
2617                 { 0x00, 0xf0f9 },
2618                 { 0x04, 0x9800 },
2619                 { 0x04, 0x9000 },
2620
2621                 { 0x03, 0xdf01 },
2622                 { 0x02, 0xdf20 },
2623                 { 0x01, 0xff95 },
2624                 { 0x00, 0xba00 },
2625                 { 0x04, 0xa800 },
2626                 { 0x04, 0xa000 },
2627
2628                 { 0x03, 0xff41 },
2629                 { 0x02, 0xdf20 },
2630                 { 0x01, 0x0140 },
2631                 { 0x00, 0x00bb },
2632                 { 0x04, 0xb800 },
2633                 { 0x04, 0xb000 },
2634
2635                 { 0x03, 0xdf41 },
2636                 { 0x02, 0xdc60 },
2637                 { 0x01, 0x6340 },
2638                 { 0x00, 0x007d },
2639                 { 0x04, 0xd800 },
2640                 { 0x04, 0xd000 },
2641
2642                 { 0x03, 0xdf01 },
2643                 { 0x02, 0xdf20 },
2644                 { 0x01, 0x100a },
2645                 { 0x00, 0xa0ff },
2646                 { 0x04, 0xf800 },
2647                 { 0x04, 0xf000 },
2648
2649                 { 0x1f, 0x0000 },
2650                 { 0x0b, 0x0000 },
2651                 { 0x00, 0x9200 }
2652         };
2653
2654         rtl_writephy_batch(tp, phy_reg_init);
2655 }
2656
2657 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2658 {
2659         static const struct phy_reg phy_reg_init[] = {
2660                 { 0x1f, 0x0002 },
2661                 { 0x01, 0x90d0 },
2662                 { 0x1f, 0x0000 }
2663         };
2664
2665         rtl_writephy_batch(tp, phy_reg_init);
2666 }
2667
2668 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2669 {
2670         struct pci_dev *pdev = tp->pci_dev;
2671
2672         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2673             (pdev->subsystem_device != 0xe000))
2674                 return;
2675
2676         rtl_writephy(tp, 0x1f, 0x0001);
2677         rtl_writephy(tp, 0x10, 0xf01b);
2678         rtl_writephy(tp, 0x1f, 0x0000);
2679 }
2680
2681 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2682 {
2683         static const struct phy_reg phy_reg_init[] = {
2684                 { 0x1f, 0x0001 },
2685                 { 0x04, 0x0000 },
2686                 { 0x03, 0x00a1 },
2687                 { 0x02, 0x0008 },
2688                 { 0x01, 0x0120 },
2689                 { 0x00, 0x1000 },
2690                 { 0x04, 0x0800 },
2691                 { 0x04, 0x9000 },
2692                 { 0x03, 0x802f },
2693                 { 0x02, 0x4f02 },
2694                 { 0x01, 0x0409 },
2695                 { 0x00, 0xf099 },
2696                 { 0x04, 0x9800 },
2697                 { 0x04, 0xa000 },
2698                 { 0x03, 0xdf01 },
2699                 { 0x02, 0xdf20 },
2700                 { 0x01, 0xff95 },
2701                 { 0x00, 0xba00 },
2702                 { 0x04, 0xa800 },
2703                 { 0x04, 0xf000 },
2704                 { 0x03, 0xdf01 },
2705                 { 0x02, 0xdf20 },
2706                 { 0x01, 0x101a },
2707                 { 0x00, 0xa0ff },
2708                 { 0x04, 0xf800 },
2709                 { 0x04, 0x0000 },
2710                 { 0x1f, 0x0000 },
2711
2712                 { 0x1f, 0x0001 },
2713                 { 0x10, 0xf41b },
2714                 { 0x14, 0xfb54 },
2715                 { 0x18, 0xf5c7 },
2716                 { 0x1f, 0x0000 },
2717
2718                 { 0x1f, 0x0001 },
2719                 { 0x17, 0x0cc0 },
2720                 { 0x1f, 0x0000 }
2721         };
2722
2723         rtl_writephy_batch(tp, phy_reg_init);
2724
2725         rtl8169scd_hw_phy_config_quirk(tp);
2726 }
2727
2728 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2729 {
2730         static const struct phy_reg phy_reg_init[] = {
2731                 { 0x1f, 0x0001 },
2732                 { 0x04, 0x0000 },
2733                 { 0x03, 0x00a1 },
2734                 { 0x02, 0x0008 },
2735                 { 0x01, 0x0120 },
2736                 { 0x00, 0x1000 },
2737                 { 0x04, 0x0800 },
2738                 { 0x04, 0x9000 },
2739                 { 0x03, 0x802f },
2740                 { 0x02, 0x4f02 },
2741                 { 0x01, 0x0409 },
2742                 { 0x00, 0xf099 },
2743                 { 0x04, 0x9800 },
2744                 { 0x04, 0xa000 },
2745                 { 0x03, 0xdf01 },
2746                 { 0x02, 0xdf20 },
2747                 { 0x01, 0xff95 },
2748                 { 0x00, 0xba00 },
2749                 { 0x04, 0xa800 },
2750                 { 0x04, 0xf000 },
2751                 { 0x03, 0xdf01 },
2752                 { 0x02, 0xdf20 },
2753                 { 0x01, 0x101a },
2754                 { 0x00, 0xa0ff },
2755                 { 0x04, 0xf800 },
2756                 { 0x04, 0x0000 },
2757                 { 0x1f, 0x0000 },
2758
2759                 { 0x1f, 0x0001 },
2760                 { 0x0b, 0x8480 },
2761                 { 0x1f, 0x0000 },
2762
2763                 { 0x1f, 0x0001 },
2764                 { 0x18, 0x67c7 },
2765                 { 0x04, 0x2000 },
2766                 { 0x03, 0x002f },
2767                 { 0x02, 0x4360 },
2768                 { 0x01, 0x0109 },
2769                 { 0x00, 0x3022 },
2770                 { 0x04, 0x2800 },
2771                 { 0x1f, 0x0000 },
2772
2773                 { 0x1f, 0x0001 },
2774                 { 0x17, 0x0cc0 },
2775                 { 0x1f, 0x0000 }
2776         };
2777
2778         rtl_writephy_batch(tp, phy_reg_init);
2779 }
2780
2781 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2782 {
2783         static const struct phy_reg phy_reg_init[] = {
2784                 { 0x10, 0xf41b },
2785                 { 0x1f, 0x0000 }
2786         };
2787
2788         rtl_writephy(tp, 0x1f, 0x0001);
2789         rtl_patchphy(tp, 0x16, 1 << 0);
2790
2791         rtl_writephy_batch(tp, phy_reg_init);
2792 }
2793
2794 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2795 {
2796         static const struct phy_reg phy_reg_init[] = {
2797                 { 0x1f, 0x0001 },
2798                 { 0x10, 0xf41b },
2799                 { 0x1f, 0x0000 }
2800         };
2801
2802         rtl_writephy_batch(tp, phy_reg_init);
2803 }
2804
2805 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2806 {
2807         static const struct phy_reg phy_reg_init[] = {
2808                 { 0x1f, 0x0000 },
2809                 { 0x1d, 0x0f00 },
2810                 { 0x1f, 0x0002 },
2811                 { 0x0c, 0x1ec8 },
2812                 { 0x1f, 0x0000 }
2813         };
2814
2815         rtl_writephy_batch(tp, phy_reg_init);
2816 }
2817
2818 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2819 {
2820         static const struct phy_reg phy_reg_init[] = {
2821                 { 0x1f, 0x0001 },
2822                 { 0x1d, 0x3d98 },
2823                 { 0x1f, 0x0000 }
2824         };
2825
2826         rtl_writephy(tp, 0x1f, 0x0000);
2827         rtl_patchphy(tp, 0x14, 1 << 5);
2828         rtl_patchphy(tp, 0x0d, 1 << 5);
2829
2830         rtl_writephy_batch(tp, phy_reg_init);
2831 }
2832
2833 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2834 {
2835         static const struct phy_reg phy_reg_init[] = {
2836                 { 0x1f, 0x0001 },
2837                 { 0x12, 0x2300 },
2838                 { 0x1f, 0x0002 },
2839                 { 0x00, 0x88d4 },
2840                 { 0x01, 0x82b1 },
2841                 { 0x03, 0x7002 },
2842                 { 0x08, 0x9e30 },
2843                 { 0x09, 0x01f0 },
2844                 { 0x0a, 0x5500 },
2845                 { 0x0c, 0x00c8 },
2846                 { 0x1f, 0x0003 },
2847                 { 0x12, 0xc096 },
2848                 { 0x16, 0x000a },
2849                 { 0x1f, 0x0000 },
2850                 { 0x1f, 0x0000 },
2851                 { 0x09, 0x2000 },
2852                 { 0x09, 0x0000 }
2853         };
2854
2855         rtl_writephy_batch(tp, phy_reg_init);
2856
2857         rtl_patchphy(tp, 0x14, 1 << 5);
2858         rtl_patchphy(tp, 0x0d, 1 << 5);
2859         rtl_writephy(tp, 0x1f, 0x0000);
2860 }
2861
2862 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2863 {
2864         static const struct phy_reg phy_reg_init[] = {
2865                 { 0x1f, 0x0001 },
2866                 { 0x12, 0x2300 },
2867                 { 0x03, 0x802f },
2868                 { 0x02, 0x4f02 },
2869                 { 0x01, 0x0409 },
2870                 { 0x00, 0xf099 },
2871                 { 0x04, 0x9800 },
2872                 { 0x04, 0x9000 },
2873                 { 0x1d, 0x3d98 },
2874                 { 0x1f, 0x0002 },
2875                 { 0x0c, 0x7eb8 },
2876                 { 0x06, 0x0761 },
2877                 { 0x1f, 0x0003 },
2878                 { 0x16, 0x0f0a },
2879                 { 0x1f, 0x0000 }
2880         };
2881
2882         rtl_writephy_batch(tp, phy_reg_init);
2883
2884         rtl_patchphy(tp, 0x16, 1 << 0);
2885         rtl_patchphy(tp, 0x14, 1 << 5);
2886         rtl_patchphy(tp, 0x0d, 1 << 5);
2887         rtl_writephy(tp, 0x1f, 0x0000);
2888 }
2889
2890 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2891 {
2892         static const struct phy_reg phy_reg_init[] = {
2893                 { 0x1f, 0x0001 },
2894                 { 0x12, 0x2300 },
2895                 { 0x1d, 0x3d98 },
2896                 { 0x1f, 0x0002 },
2897                 { 0x0c, 0x7eb8 },
2898                 { 0x06, 0x5461 },
2899                 { 0x1f, 0x0003 },
2900                 { 0x16, 0x0f0a },
2901                 { 0x1f, 0x0000 }
2902         };
2903
2904         rtl_writephy_batch(tp, phy_reg_init);
2905
2906         rtl_patchphy(tp, 0x16, 1 << 0);
2907         rtl_patchphy(tp, 0x14, 1 << 5);
2908         rtl_patchphy(tp, 0x0d, 1 << 5);
2909         rtl_writephy(tp, 0x1f, 0x0000);
2910 }
2911
2912 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2913 {
2914         rtl8168c_3_hw_phy_config(tp);
2915 }
2916
2917 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2918         /* Channel Estimation */
2919         { 0x1f, 0x0001 },
2920         { 0x06, 0x4064 },
2921         { 0x07, 0x2863 },
2922         { 0x08, 0x059c },
2923         { 0x09, 0x26b4 },
2924         { 0x0a, 0x6a19 },
2925         { 0x0b, 0xdcc8 },
2926         { 0x10, 0xf06d },
2927         { 0x14, 0x7f68 },
2928         { 0x18, 0x7fd9 },
2929         { 0x1c, 0xf0ff },
2930         { 0x1d, 0x3d9c },
2931         { 0x1f, 0x0003 },
2932         { 0x12, 0xf49f },
2933         { 0x13, 0x070b },
2934         { 0x1a, 0x05ad },
2935         { 0x14, 0x94c0 },
2936
2937         /*
2938          * Tx Error Issue
2939          * Enhance line driver power
2940          */
2941         { 0x1f, 0x0002 },
2942         { 0x06, 0x5561 },
2943         { 0x1f, 0x0005 },
2944         { 0x05, 0x8332 },
2945         { 0x06, 0x5561 },
2946
2947         /*
2948          * Can not link to 1Gbps with bad cable
2949          * Decrease SNR threshold form 21.07dB to 19.04dB
2950          */
2951         { 0x1f, 0x0001 },
2952         { 0x17, 0x0cc0 },
2953
2954         { 0x1f, 0x0000 },
2955         { 0x0d, 0xf880 }
2956 };
2957
2958 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2959         { 0x1f, 0x0002 },
2960         { 0x05, 0x669a },
2961         { 0x1f, 0x0005 },
2962         { 0x05, 0x8330 },
2963         { 0x06, 0x669a },
2964         { 0x1f, 0x0002 }
2965 };
2966
2967 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2968 {
2969         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2970
2971         /*
2972          * Rx Error Issue
2973          * Fine Tune Switching regulator parameter
2974          */
2975         rtl_writephy(tp, 0x1f, 0x0002);
2976         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2977         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2978
2979         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2980                 int val;
2981
2982                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2983
2984                 val = rtl_readphy(tp, 0x0d);
2985
2986                 if ((val & 0x00ff) != 0x006c) {
2987                         static const u32 set[] = {
2988                                 0x0065, 0x0066, 0x0067, 0x0068,
2989                                 0x0069, 0x006a, 0x006b, 0x006c
2990                         };
2991                         int i;
2992
2993                         rtl_writephy(tp, 0x1f, 0x0002);
2994
2995                         val &= 0xff00;
2996                         for (i = 0; i < ARRAY_SIZE(set); i++)
2997                                 rtl_writephy(tp, 0x0d, val | set[i]);
2998                 }
2999         } else {
3000                 static const struct phy_reg phy_reg_init[] = {
3001                         { 0x1f, 0x0002 },
3002                         { 0x05, 0x6662 },
3003                         { 0x1f, 0x0005 },
3004                         { 0x05, 0x8330 },
3005                         { 0x06, 0x6662 }
3006                 };
3007
3008                 rtl_writephy_batch(tp, phy_reg_init);
3009         }
3010
3011         /* RSET couple improve */
3012         rtl_writephy(tp, 0x1f, 0x0002);
3013         rtl_patchphy(tp, 0x0d, 0x0300);
3014         rtl_patchphy(tp, 0x0f, 0x0010);
3015
3016         /* Fine tune PLL performance */
3017         rtl_writephy(tp, 0x1f, 0x0002);
3018         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3019         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3020
3021         rtl_writephy(tp, 0x1f, 0x0005);
3022         rtl_writephy(tp, 0x05, 0x001b);
3023
3024         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3025
3026         rtl_writephy(tp, 0x1f, 0x0000);
3027 }
3028
3029 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3030 {
3031         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
3032
3033         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3034                 int val;
3035
3036                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3037
3038                 val = rtl_readphy(tp, 0x0d);
3039                 if ((val & 0x00ff) != 0x006c) {
3040                         static const u32 set[] = {
3041                                 0x0065, 0x0066, 0x0067, 0x0068,
3042                                 0x0069, 0x006a, 0x006b, 0x006c
3043                         };
3044                         int i;
3045
3046                         rtl_writephy(tp, 0x1f, 0x0002);
3047
3048                         val &= 0xff00;
3049                         for (i = 0; i < ARRAY_SIZE(set); i++)
3050                                 rtl_writephy(tp, 0x0d, val | set[i]);
3051                 }
3052         } else {
3053                 static const struct phy_reg phy_reg_init[] = {
3054                         { 0x1f, 0x0002 },
3055                         { 0x05, 0x2642 },
3056                         { 0x1f, 0x0005 },
3057                         { 0x05, 0x8330 },
3058                         { 0x06, 0x2642 }
3059                 };
3060
3061                 rtl_writephy_batch(tp, phy_reg_init);
3062         }
3063
3064         /* Fine tune PLL performance */
3065         rtl_writephy(tp, 0x1f, 0x0002);
3066         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3067         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3068
3069         /* Switching regulator Slew rate */
3070         rtl_writephy(tp, 0x1f, 0x0002);
3071         rtl_patchphy(tp, 0x0f, 0x0017);
3072
3073         rtl_writephy(tp, 0x1f, 0x0005);
3074         rtl_writephy(tp, 0x05, 0x001b);
3075
3076         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3077
3078         rtl_writephy(tp, 0x1f, 0x0000);
3079 }
3080
3081 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3082 {
3083         static const struct phy_reg phy_reg_init[] = {
3084                 { 0x1f, 0x0002 },
3085                 { 0x10, 0x0008 },
3086                 { 0x0d, 0x006c },
3087
3088                 { 0x1f, 0x0000 },
3089                 { 0x0d, 0xf880 },
3090
3091                 { 0x1f, 0x0001 },
3092                 { 0x17, 0x0cc0 },
3093
3094                 { 0x1f, 0x0001 },
3095                 { 0x0b, 0xa4d8 },
3096                 { 0x09, 0x281c },
3097                 { 0x07, 0x2883 },
3098                 { 0x0a, 0x6b35 },
3099                 { 0x1d, 0x3da4 },
3100                 { 0x1c, 0xeffd },
3101                 { 0x14, 0x7f52 },
3102                 { 0x18, 0x7fc6 },
3103                 { 0x08, 0x0601 },
3104                 { 0x06, 0x4063 },
3105                 { 0x10, 0xf074 },
3106                 { 0x1f, 0x0003 },
3107                 { 0x13, 0x0789 },
3108                 { 0x12, 0xf4bd },
3109                 { 0x1a, 0x04fd },
3110                 { 0x14, 0x84b0 },
3111                 { 0x1f, 0x0000 },
3112                 { 0x00, 0x9200 },
3113
3114                 { 0x1f, 0x0005 },
3115                 { 0x01, 0x0340 },
3116                 { 0x1f, 0x0001 },
3117                 { 0x04, 0x4000 },
3118                 { 0x03, 0x1d21 },
3119                 { 0x02, 0x0c32 },
3120                 { 0x01, 0x0200 },
3121                 { 0x00, 0x5554 },
3122                 { 0x04, 0x4800 },
3123                 { 0x04, 0x4000 },
3124                 { 0x04, 0xf000 },
3125                 { 0x03, 0xdf01 },
3126                 { 0x02, 0xdf20 },
3127                 { 0x01, 0x101a },
3128                 { 0x00, 0xa0ff },
3129                 { 0x04, 0xf800 },
3130                 { 0x04, 0xf000 },
3131                 { 0x1f, 0x0000 },
3132
3133                 { 0x1f, 0x0007 },
3134                 { 0x1e, 0x0023 },
3135                 { 0x16, 0x0000 },
3136                 { 0x1f, 0x0000 }
3137         };
3138
3139         rtl_writephy_batch(tp, phy_reg_init);
3140 }
3141
3142 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3143 {
3144         static const struct phy_reg phy_reg_init[] = {
3145                 { 0x1f, 0x0001 },
3146                 { 0x17, 0x0cc0 },
3147
3148                 { 0x1f, 0x0007 },
3149                 { 0x1e, 0x002d },
3150                 { 0x18, 0x0040 },
3151                 { 0x1f, 0x0000 }
3152         };
3153
3154         rtl_writephy_batch(tp, phy_reg_init);
3155         rtl_patchphy(tp, 0x0d, 1 << 5);
3156 }
3157
3158 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3159 {
3160         static const struct phy_reg phy_reg_init[] = {
3161                 /* Enable Delay cap */
3162                 { 0x1f, 0x0005 },
3163                 { 0x05, 0x8b80 },
3164                 { 0x06, 0xc896 },
3165                 { 0x1f, 0x0000 },
3166
3167                 /* Channel estimation fine tune */
3168                 { 0x1f, 0x0001 },
3169                 { 0x0b, 0x6c20 },
3170                 { 0x07, 0x2872 },
3171                 { 0x1c, 0xefff },
3172                 { 0x1f, 0x0003 },
3173                 { 0x14, 0x6420 },
3174                 { 0x1f, 0x0000 },
3175
3176                 /* Update PFM & 10M TX idle timer */
3177                 { 0x1f, 0x0007 },
3178                 { 0x1e, 0x002f },
3179                 { 0x15, 0x1919 },
3180                 { 0x1f, 0x0000 },
3181
3182                 { 0x1f, 0x0007 },
3183                 { 0x1e, 0x00ac },
3184                 { 0x18, 0x0006 },
3185                 { 0x1f, 0x0000 }
3186         };
3187
3188         rtl_apply_firmware(tp);
3189
3190         rtl_writephy_batch(tp, phy_reg_init);
3191
3192         /* DCO enable for 10M IDLE Power */
3193         rtl_writephy(tp, 0x1f, 0x0007);
3194         rtl_writephy(tp, 0x1e, 0x0023);
3195         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3196         rtl_writephy(tp, 0x1f, 0x0000);
3197
3198         /* For impedance matching */
3199         rtl_writephy(tp, 0x1f, 0x0002);
3200         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3201         rtl_writephy(tp, 0x1f, 0x0000);
3202
3203         /* PHY auto speed down */
3204         rtl_writephy(tp, 0x1f, 0x0007);
3205         rtl_writephy(tp, 0x1e, 0x002d);
3206         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3207         rtl_writephy(tp, 0x1f, 0x0000);
3208         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3209
3210         rtl_writephy(tp, 0x1f, 0x0005);
3211         rtl_writephy(tp, 0x05, 0x8b86);
3212         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3213         rtl_writephy(tp, 0x1f, 0x0000);
3214
3215         rtl_writephy(tp, 0x1f, 0x0005);
3216         rtl_writephy(tp, 0x05, 0x8b85);
3217         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3218         rtl_writephy(tp, 0x1f, 0x0007);
3219         rtl_writephy(tp, 0x1e, 0x0020);
3220         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3221         rtl_writephy(tp, 0x1f, 0x0006);
3222         rtl_writephy(tp, 0x00, 0x5a00);
3223         rtl_writephy(tp, 0x1f, 0x0000);
3224         rtl_writephy(tp, 0x0d, 0x0007);
3225         rtl_writephy(tp, 0x0e, 0x003c);
3226         rtl_writephy(tp, 0x0d, 0x4007);
3227         rtl_writephy(tp, 0x0e, 0x0000);
3228         rtl_writephy(tp, 0x0d, 0x0000);
3229 }
3230
3231 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3232 {
3233         const u16 w[] = {
3234                 addr[0] | (addr[1] << 8),
3235                 addr[2] | (addr[3] << 8),
3236                 addr[4] | (addr[5] << 8)
3237         };
3238
3239         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3240         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3241         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3242         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3243 }
3244
3245 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3246 {
3247         static const struct phy_reg phy_reg_init[] = {
3248                 /* Enable Delay cap */
3249                 { 0x1f, 0x0004 },
3250                 { 0x1f, 0x0007 },
3251                 { 0x1e, 0x00ac },
3252                 { 0x18, 0x0006 },
3253                 { 0x1f, 0x0002 },
3254                 { 0x1f, 0x0000 },
3255                 { 0x1f, 0x0000 },
3256
3257                 /* Channel estimation fine tune */
3258                 { 0x1f, 0x0003 },
3259                 { 0x09, 0xa20f },
3260                 { 0x1f, 0x0000 },
3261                 { 0x1f, 0x0000 },
3262
3263                 /* Green Setting */
3264                 { 0x1f, 0x0005 },
3265                 { 0x05, 0x8b5b },
3266                 { 0x06, 0x9222 },
3267                 { 0x05, 0x8b6d },
3268                 { 0x06, 0x8000 },
3269                 { 0x05, 0x8b76 },
3270                 { 0x06, 0x8000 },
3271                 { 0x1f, 0x0000 }
3272         };
3273
3274         rtl_apply_firmware(tp);
3275
3276         rtl_writephy_batch(tp, phy_reg_init);
3277
3278         /* For 4-corner performance improve */
3279         rtl_writephy(tp, 0x1f, 0x0005);
3280         rtl_writephy(tp, 0x05, 0x8b80);
3281         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3282         rtl_writephy(tp, 0x1f, 0x0000);
3283
3284         /* PHY auto speed down */
3285         rtl_writephy(tp, 0x1f, 0x0004);
3286         rtl_writephy(tp, 0x1f, 0x0007);
3287         rtl_writephy(tp, 0x1e, 0x002d);
3288         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3289         rtl_writephy(tp, 0x1f, 0x0002);
3290         rtl_writephy(tp, 0x1f, 0x0000);
3291         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3292
3293         /* improve 10M EEE waveform */
3294         rtl_writephy(tp, 0x1f, 0x0005);
3295         rtl_writephy(tp, 0x05, 0x8b86);
3296         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3297         rtl_writephy(tp, 0x1f, 0x0000);
3298
3299         /* Improve 2-pair detection performance */
3300         rtl_writephy(tp, 0x1f, 0x0005);
3301         rtl_writephy(tp, 0x05, 0x8b85);
3302         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3303         rtl_writephy(tp, 0x1f, 0x0000);
3304
3305         rtl8168f_config_eee_phy(tp);
3306         rtl_enable_eee(tp);
3307
3308         /* Green feature */
3309         rtl_writephy(tp, 0x1f, 0x0003);
3310         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3311         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3312         rtl_writephy(tp, 0x1f, 0x0000);
3313         rtl_writephy(tp, 0x1f, 0x0005);
3314         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3315         rtl_writephy(tp, 0x1f, 0x0000);
3316
3317         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3318         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3319 }
3320
3321 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3322 {
3323         /* For 4-corner performance improve */
3324         rtl_writephy(tp, 0x1f, 0x0005);
3325         rtl_writephy(tp, 0x05, 0x8b80);
3326         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3327         rtl_writephy(tp, 0x1f, 0x0000);
3328
3329         /* PHY auto speed down */
3330         rtl_writephy(tp, 0x1f, 0x0007);
3331         rtl_writephy(tp, 0x1e, 0x002d);
3332         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3333         rtl_writephy(tp, 0x1f, 0x0000);
3334         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3335
3336         /* Improve 10M EEE waveform */
3337         rtl_writephy(tp, 0x1f, 0x0005);
3338         rtl_writephy(tp, 0x05, 0x8b86);
3339         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3340         rtl_writephy(tp, 0x1f, 0x0000);
3341
3342         rtl8168f_config_eee_phy(tp);
3343         rtl_enable_eee(tp);
3344 }
3345
3346 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3347 {
3348         static const struct phy_reg phy_reg_init[] = {
3349                 /* Channel estimation fine tune */
3350                 { 0x1f, 0x0003 },
3351                 { 0x09, 0xa20f },
3352                 { 0x1f, 0x0000 },
3353
3354                 /* Modify green table for giga & fnet */
3355                 { 0x1f, 0x0005 },
3356                 { 0x05, 0x8b55 },
3357                 { 0x06, 0x0000 },
3358                 { 0x05, 0x8b5e },
3359                 { 0x06, 0x0000 },
3360                 { 0x05, 0x8b67 },
3361                 { 0x06, 0x0000 },
3362                 { 0x05, 0x8b70 },
3363                 { 0x06, 0x0000 },
3364                 { 0x1f, 0x0000 },
3365                 { 0x1f, 0x0007 },
3366                 { 0x1e, 0x0078 },
3367                 { 0x17, 0x0000 },
3368                 { 0x19, 0x00fb },
3369                 { 0x1f, 0x0000 },
3370
3371                 /* Modify green table for 10M */
3372                 { 0x1f, 0x0005 },
3373                 { 0x05, 0x8b79 },
3374                 { 0x06, 0xaa00 },
3375                 { 0x1f, 0x0000 },
3376
3377                 /* Disable hiimpedance detection (RTCT) */
3378                 { 0x1f, 0x0003 },
3379                 { 0x01, 0x328a },
3380                 { 0x1f, 0x0000 }
3381         };
3382
3383         rtl_apply_firmware(tp);
3384
3385         rtl_writephy_batch(tp, phy_reg_init);
3386
3387         rtl8168f_hw_phy_config(tp);
3388
3389         /* Improve 2-pair detection performance */
3390         rtl_writephy(tp, 0x1f, 0x0005);
3391         rtl_writephy(tp, 0x05, 0x8b85);
3392         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3393         rtl_writephy(tp, 0x1f, 0x0000);
3394 }
3395
3396 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3397 {
3398         rtl_apply_firmware(tp);
3399
3400         rtl8168f_hw_phy_config(tp);
3401 }
3402
3403 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3404 {
3405         static const struct phy_reg phy_reg_init[] = {
3406                 /* Channel estimation fine tune */
3407                 { 0x1f, 0x0003 },
3408                 { 0x09, 0xa20f },
3409                 { 0x1f, 0x0000 },
3410
3411                 /* Modify green table for giga & fnet */
3412                 { 0x1f, 0x0005 },
3413                 { 0x05, 0x8b55 },
3414                 { 0x06, 0x0000 },
3415                 { 0x05, 0x8b5e },
3416                 { 0x06, 0x0000 },
3417                 { 0x05, 0x8b67 },
3418                 { 0x06, 0x0000 },
3419                 { 0x05, 0x8b70 },
3420                 { 0x06, 0x0000 },
3421                 { 0x1f, 0x0000 },
3422                 { 0x1f, 0x0007 },
3423                 { 0x1e, 0x0078 },
3424                 { 0x17, 0x0000 },
3425                 { 0x19, 0x00aa },
3426                 { 0x1f, 0x0000 },
3427
3428                 /* Modify green table for 10M */
3429                 { 0x1f, 0x0005 },
3430                 { 0x05, 0x8b79 },
3431                 { 0x06, 0xaa00 },
3432                 { 0x1f, 0x0000 },
3433
3434                 /* Disable hiimpedance detection (RTCT) */
3435                 { 0x1f, 0x0003 },
3436                 { 0x01, 0x328a },
3437                 { 0x1f, 0x0000 }
3438         };
3439
3440
3441         rtl_apply_firmware(tp);
3442
3443         rtl8168f_hw_phy_config(tp);
3444
3445         /* Improve 2-pair detection performance */
3446         rtl_writephy(tp, 0x1f, 0x0005);
3447         rtl_writephy(tp, 0x05, 0x8b85);
3448         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3449         rtl_writephy(tp, 0x1f, 0x0000);
3450
3451         rtl_writephy_batch(tp, phy_reg_init);
3452
3453         /* Modify green table for giga */
3454         rtl_writephy(tp, 0x1f, 0x0005);
3455         rtl_writephy(tp, 0x05, 0x8b54);
3456         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3457         rtl_writephy(tp, 0x05, 0x8b5d);
3458         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3459         rtl_writephy(tp, 0x05, 0x8a7c);
3460         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3461         rtl_writephy(tp, 0x05, 0x8a7f);
3462         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3463         rtl_writephy(tp, 0x05, 0x8a82);
3464         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3465         rtl_writephy(tp, 0x05, 0x8a85);
3466         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3467         rtl_writephy(tp, 0x05, 0x8a88);
3468         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3469         rtl_writephy(tp, 0x1f, 0x0000);
3470
3471         /* uc same-seed solution */
3472         rtl_writephy(tp, 0x1f, 0x0005);
3473         rtl_writephy(tp, 0x05, 0x8b85);
3474         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3475         rtl_writephy(tp, 0x1f, 0x0000);
3476
3477         /* Green feature */
3478         rtl_writephy(tp, 0x1f, 0x0003);
3479         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3480         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3481         rtl_writephy(tp, 0x1f, 0x0000);
3482 }
3483
3484 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3485 {
3486         phy_write(tp->phydev, 0x1f, 0x0a43);
3487         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3488 }
3489
3490 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3491 {
3492         struct phy_device *phydev = tp->phydev;
3493
3494         phy_write(phydev, 0x1f, 0x0bcc);
3495         phy_clear_bits(phydev, 0x14, BIT(8));
3496
3497         phy_write(phydev, 0x1f, 0x0a44);
3498         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3499
3500         phy_write(phydev, 0x1f, 0x0a43);
3501         phy_write(phydev, 0x13, 0x8084);
3502         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3503         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3504
3505         phy_write(phydev, 0x1f, 0x0000);
3506 }
3507
3508 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3509 {
3510         rtl_apply_firmware(tp);
3511
3512         rtl_writephy(tp, 0x1f, 0x0a46);
3513         if (rtl_readphy(tp, 0x10) & 0x0100) {
3514                 rtl_writephy(tp, 0x1f, 0x0bcc);
3515                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3516         } else {
3517                 rtl_writephy(tp, 0x1f, 0x0bcc);
3518                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3519         }
3520
3521         rtl_writephy(tp, 0x1f, 0x0a46);
3522         if (rtl_readphy(tp, 0x13) & 0x0100) {
3523                 rtl_writephy(tp, 0x1f, 0x0c41);
3524                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3525         } else {
3526                 rtl_writephy(tp, 0x1f, 0x0c41);
3527                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3528         }
3529
3530         /* Enable PHY auto speed down */
3531         rtl_writephy(tp, 0x1f, 0x0a44);
3532         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3533
3534         rtl8168g_phy_adjust_10m_aldps(tp);
3535
3536         /* EEE auto-fallback function */
3537         rtl_writephy(tp, 0x1f, 0x0a4b);
3538         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3539
3540         /* Enable UC LPF tune function */
3541         rtl_writephy(tp, 0x1f, 0x0a43);
3542         rtl_writephy(tp, 0x13, 0x8012);
3543         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3544
3545         rtl_writephy(tp, 0x1f, 0x0c42);
3546         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3547
3548         /* Improve SWR Efficiency */
3549         rtl_writephy(tp, 0x1f, 0x0bcd);
3550         rtl_writephy(tp, 0x14, 0x5065);
3551         rtl_writephy(tp, 0x14, 0xd065);
3552         rtl_writephy(tp, 0x1f, 0x0bc8);
3553         rtl_writephy(tp, 0x11, 0x5655);
3554         rtl_writephy(tp, 0x1f, 0x0bcd);
3555         rtl_writephy(tp, 0x14, 0x1065);
3556         rtl_writephy(tp, 0x14, 0x9065);
3557         rtl_writephy(tp, 0x14, 0x1065);
3558
3559         rtl8168g_disable_aldps(tp);
3560         rtl8168g_config_eee_phy(tp);
3561         rtl_enable_eee(tp);
3562 }
3563
3564 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3565 {
3566         rtl_apply_firmware(tp);
3567         rtl8168g_config_eee_phy(tp);
3568         rtl_enable_eee(tp);
3569 }
3570
3571 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3572 {
3573         u16 dout_tapbin;
3574         u32 data;
3575
3576         rtl_apply_firmware(tp);
3577
3578         /* CHN EST parameters adjust - giga master */
3579         rtl_writephy(tp, 0x1f, 0x0a43);
3580         rtl_writephy(tp, 0x13, 0x809b);
3581         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3582         rtl_writephy(tp, 0x13, 0x80a2);
3583         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3584         rtl_writephy(tp, 0x13, 0x80a4);
3585         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3586         rtl_writephy(tp, 0x13, 0x809c);
3587         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3588         rtl_writephy(tp, 0x1f, 0x0000);
3589
3590         /* CHN EST parameters adjust - giga slave */
3591         rtl_writephy(tp, 0x1f, 0x0a43);
3592         rtl_writephy(tp, 0x13, 0x80ad);
3593         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3594         rtl_writephy(tp, 0x13, 0x80b4);
3595         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3596         rtl_writephy(tp, 0x13, 0x80ac);
3597         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3598         rtl_writephy(tp, 0x1f, 0x0000);
3599
3600         /* CHN EST parameters adjust - fnet */
3601         rtl_writephy(tp, 0x1f, 0x0a43);
3602         rtl_writephy(tp, 0x13, 0x808e);
3603         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3604         rtl_writephy(tp, 0x13, 0x8090);
3605         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3606         rtl_writephy(tp, 0x13, 0x8092);
3607         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3608         rtl_writephy(tp, 0x1f, 0x0000);
3609
3610         /* enable R-tune & PGA-retune function */
3611         dout_tapbin = 0;
3612         rtl_writephy(tp, 0x1f, 0x0a46);
3613         data = rtl_readphy(tp, 0x13);
3614         data &= 3;
3615         data <<= 2;
3616         dout_tapbin |= data;
3617         data = rtl_readphy(tp, 0x12);
3618         data &= 0xc000;
3619         data >>= 14;
3620         dout_tapbin |= data;
3621         dout_tapbin = ~(dout_tapbin^0x08);
3622         dout_tapbin <<= 12;
3623         dout_tapbin &= 0xf000;
3624         rtl_writephy(tp, 0x1f, 0x0a43);
3625         rtl_writephy(tp, 0x13, 0x827a);
3626         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3627         rtl_writephy(tp, 0x13, 0x827b);
3628         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3629         rtl_writephy(tp, 0x13, 0x827c);
3630         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3631         rtl_writephy(tp, 0x13, 0x827d);
3632         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3633
3634         rtl_writephy(tp, 0x1f, 0x0a43);
3635         rtl_writephy(tp, 0x13, 0x0811);
3636         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3637         rtl_writephy(tp, 0x1f, 0x0a42);
3638         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3639         rtl_writephy(tp, 0x1f, 0x0000);
3640
3641         /* enable GPHY 10M */
3642         rtl_writephy(tp, 0x1f, 0x0a44);
3643         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3644         rtl_writephy(tp, 0x1f, 0x0000);
3645
3646         /* SAR ADC performance */
3647         rtl_writephy(tp, 0x1f, 0x0bca);
3648         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3649         rtl_writephy(tp, 0x1f, 0x0000);
3650
3651         rtl_writephy(tp, 0x1f, 0x0a43);
3652         rtl_writephy(tp, 0x13, 0x803f);
3653         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3654         rtl_writephy(tp, 0x13, 0x8047);
3655         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3656         rtl_writephy(tp, 0x13, 0x804f);
3657         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3658         rtl_writephy(tp, 0x13, 0x8057);
3659         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3660         rtl_writephy(tp, 0x13, 0x805f);
3661         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3662         rtl_writephy(tp, 0x13, 0x8067);
3663         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3664         rtl_writephy(tp, 0x13, 0x806f);
3665         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3666         rtl_writephy(tp, 0x1f, 0x0000);
3667
3668         /* disable phy pfm mode */
3669         rtl_writephy(tp, 0x1f, 0x0a44);
3670         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3671         rtl_writephy(tp, 0x1f, 0x0000);
3672
3673         rtl8168g_disable_aldps(tp);
3674         rtl8168g_config_eee_phy(tp);
3675         rtl_enable_eee(tp);
3676 }
3677
3678 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3679 {
3680         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3681         u16 rlen;
3682         u32 data;
3683
3684         rtl_apply_firmware(tp);
3685
3686         /* CHIN EST parameter update */
3687         rtl_writephy(tp, 0x1f, 0x0a43);
3688         rtl_writephy(tp, 0x13, 0x808a);
3689         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3690         rtl_writephy(tp, 0x1f, 0x0000);
3691
3692         /* enable R-tune & PGA-retune function */
3693         rtl_writephy(tp, 0x1f, 0x0a43);
3694         rtl_writephy(tp, 0x13, 0x0811);
3695         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3696         rtl_writephy(tp, 0x1f, 0x0a42);
3697         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3698         rtl_writephy(tp, 0x1f, 0x0000);
3699
3700         /* enable GPHY 10M */
3701         rtl_writephy(tp, 0x1f, 0x0a44);
3702         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3703         rtl_writephy(tp, 0x1f, 0x0000);
3704
3705         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3706         data = r8168_mac_ocp_read(tp, 0xdd02);
3707         ioffset_p3 = ((data & 0x80)>>7);
3708         ioffset_p3 <<= 3;
3709
3710         data = r8168_mac_ocp_read(tp, 0xdd00);
3711         ioffset_p3 |= ((data & (0xe000))>>13);
3712         ioffset_p2 = ((data & (0x1e00))>>9);
3713         ioffset_p1 = ((data & (0x01e0))>>5);
3714         ioffset_p0 = ((data & 0x0010)>>4);
3715         ioffset_p0 <<= 3;
3716         ioffset_p0 |= (data & (0x07));
3717         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3718
3719         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3720             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3721                 rtl_writephy(tp, 0x1f, 0x0bcf);
3722                 rtl_writephy(tp, 0x16, data);
3723                 rtl_writephy(tp, 0x1f, 0x0000);
3724         }
3725
3726         /* Modify rlen (TX LPF corner frequency) level */
3727         rtl_writephy(tp, 0x1f, 0x0bcd);
3728         data = rtl_readphy(tp, 0x16);
3729         data &= 0x000f;
3730         rlen = 0;
3731         if (data > 3)
3732                 rlen = data - 3;
3733         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3734         rtl_writephy(tp, 0x17, data);
3735         rtl_writephy(tp, 0x1f, 0x0bcd);
3736         rtl_writephy(tp, 0x1f, 0x0000);
3737
3738         /* disable phy pfm mode */
3739         rtl_writephy(tp, 0x1f, 0x0a44);
3740         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3741         rtl_writephy(tp, 0x1f, 0x0000);
3742
3743         rtl8168g_disable_aldps(tp);
3744         rtl8168g_config_eee_phy(tp);
3745         rtl_enable_eee(tp);
3746 }
3747
3748 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3749 {
3750         /* Enable PHY auto speed down */
3751         rtl_writephy(tp, 0x1f, 0x0a44);
3752         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3753         rtl_writephy(tp, 0x1f, 0x0000);
3754
3755         rtl8168g_phy_adjust_10m_aldps(tp);
3756
3757         /* Enable EEE auto-fallback function */
3758         rtl_writephy(tp, 0x1f, 0x0a4b);
3759         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3760         rtl_writephy(tp, 0x1f, 0x0000);
3761
3762         /* Enable UC LPF tune function */
3763         rtl_writephy(tp, 0x1f, 0x0a43);
3764         rtl_writephy(tp, 0x13, 0x8012);
3765         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3766         rtl_writephy(tp, 0x1f, 0x0000);
3767
3768         /* set rg_sel_sdm_rate */
3769         rtl_writephy(tp, 0x1f, 0x0c42);
3770         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3771         rtl_writephy(tp, 0x1f, 0x0000);
3772
3773         rtl8168g_disable_aldps(tp);
3774         rtl8168g_config_eee_phy(tp);
3775         rtl_enable_eee(tp);
3776 }
3777
3778 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3779 {
3780         rtl8168g_phy_adjust_10m_aldps(tp);
3781
3782         /* Enable UC LPF tune function */
3783         rtl_writephy(tp, 0x1f, 0x0a43);
3784         rtl_writephy(tp, 0x13, 0x8012);
3785         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3786         rtl_writephy(tp, 0x1f, 0x0000);
3787
3788         /* Set rg_sel_sdm_rate */
3789         rtl_writephy(tp, 0x1f, 0x0c42);
3790         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3791         rtl_writephy(tp, 0x1f, 0x0000);
3792
3793         /* Channel estimation parameters */
3794         rtl_writephy(tp, 0x1f, 0x0a43);
3795         rtl_writephy(tp, 0x13, 0x80f3);
3796         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3797         rtl_writephy(tp, 0x13, 0x80f0);
3798         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3799         rtl_writephy(tp, 0x13, 0x80ef);
3800         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3801         rtl_writephy(tp, 0x13, 0x80f6);
3802         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3803         rtl_writephy(tp, 0x13, 0x80ec);
3804         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3805         rtl_writephy(tp, 0x13, 0x80ed);
3806         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3807         rtl_writephy(tp, 0x13, 0x80f2);
3808         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3809         rtl_writephy(tp, 0x13, 0x80f4);
3810         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3811         rtl_writephy(tp, 0x1f, 0x0a43);
3812         rtl_writephy(tp, 0x13, 0x8110);
3813         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3814         rtl_writephy(tp, 0x13, 0x810f);
3815         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3816         rtl_writephy(tp, 0x13, 0x8111);
3817         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3818         rtl_writephy(tp, 0x13, 0x8113);
3819         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3820         rtl_writephy(tp, 0x13, 0x8115);
3821         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3822         rtl_writephy(tp, 0x13, 0x810e);
3823         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3824         rtl_writephy(tp, 0x13, 0x810c);
3825         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3826         rtl_writephy(tp, 0x13, 0x810b);
3827         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3828         rtl_writephy(tp, 0x1f, 0x0a43);
3829         rtl_writephy(tp, 0x13, 0x80d1);
3830         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3831         rtl_writephy(tp, 0x13, 0x80cd);
3832         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3833         rtl_writephy(tp, 0x13, 0x80d3);
3834         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3835         rtl_writephy(tp, 0x13, 0x80d5);
3836         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3837         rtl_writephy(tp, 0x13, 0x80d7);
3838         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3839
3840         /* Force PWM-mode */
3841         rtl_writephy(tp, 0x1f, 0x0bcd);
3842         rtl_writephy(tp, 0x14, 0x5065);
3843         rtl_writephy(tp, 0x14, 0xd065);
3844         rtl_writephy(tp, 0x1f, 0x0bc8);
3845         rtl_writephy(tp, 0x12, 0x00ed);
3846         rtl_writephy(tp, 0x1f, 0x0bcd);
3847         rtl_writephy(tp, 0x14, 0x1065);
3848         rtl_writephy(tp, 0x14, 0x9065);
3849         rtl_writephy(tp, 0x14, 0x1065);
3850         rtl_writephy(tp, 0x1f, 0x0000);
3851
3852         rtl8168g_disable_aldps(tp);
3853         rtl8168g_config_eee_phy(tp);
3854         rtl_enable_eee(tp);
3855 }
3856
3857 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3858 {
3859         static const struct phy_reg phy_reg_init[] = {
3860                 { 0x1f, 0x0003 },
3861                 { 0x08, 0x441d },
3862                 { 0x01, 0x9100 },
3863                 { 0x1f, 0x0000 }
3864         };
3865
3866         rtl_writephy(tp, 0x1f, 0x0000);
3867         rtl_patchphy(tp, 0x11, 1 << 12);
3868         rtl_patchphy(tp, 0x19, 1 << 13);
3869         rtl_patchphy(tp, 0x10, 1 << 15);
3870
3871         rtl_writephy_batch(tp, phy_reg_init);
3872 }
3873
3874 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3875 {
3876         static const struct phy_reg phy_reg_init[] = {
3877                 { 0x1f, 0x0005 },
3878                 { 0x1a, 0x0000 },
3879                 { 0x1f, 0x0000 },
3880
3881                 { 0x1f, 0x0004 },
3882                 { 0x1c, 0x0000 },
3883                 { 0x1f, 0x0000 },
3884
3885                 { 0x1f, 0x0001 },
3886                 { 0x15, 0x7701 },
3887                 { 0x1f, 0x0000 }
3888         };
3889
3890         /* Disable ALDPS before ram code */
3891         rtl_writephy(tp, 0x1f, 0x0000);
3892         rtl_writephy(tp, 0x18, 0x0310);
3893         msleep(100);
3894
3895         rtl_apply_firmware(tp);
3896
3897         rtl_writephy_batch(tp, phy_reg_init);
3898 }
3899
3900 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3901 {
3902         /* Disable ALDPS before setting firmware */
3903         rtl_writephy(tp, 0x1f, 0x0000);
3904         rtl_writephy(tp, 0x18, 0x0310);
3905         msleep(20);
3906
3907         rtl_apply_firmware(tp);
3908
3909         /* EEE setting */
3910         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3911         rtl_writephy(tp, 0x1f, 0x0004);
3912         rtl_writephy(tp, 0x10, 0x401f);
3913         rtl_writephy(tp, 0x19, 0x7030);
3914         rtl_writephy(tp, 0x1f, 0x0000);
3915 }
3916
3917 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3918 {
3919         static const struct phy_reg phy_reg_init[] = {
3920                 { 0x1f, 0x0004 },
3921                 { 0x10, 0xc07f },
3922                 { 0x19, 0x7030 },
3923                 { 0x1f, 0x0000 }
3924         };
3925
3926         /* Disable ALDPS before ram code */
3927         rtl_writephy(tp, 0x1f, 0x0000);
3928         rtl_writephy(tp, 0x18, 0x0310);
3929         msleep(100);
3930
3931         rtl_apply_firmware(tp);
3932
3933         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3934         rtl_writephy_batch(tp, phy_reg_init);
3935
3936         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3937 }
3938
3939 static void rtl_hw_phy_config(struct net_device *dev)
3940 {
3941         static const rtl_generic_fct phy_configs[] = {
3942                 /* PCI devices. */
3943                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3944                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3945                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3946                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3947                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3948                 /* PCI-E devices. */
3949                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3950                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3951                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3952                 [RTL_GIGA_MAC_VER_10] = NULL,
3953                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3954                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3955                 [RTL_GIGA_MAC_VER_13] = NULL,
3956                 [RTL_GIGA_MAC_VER_14] = NULL,
3957                 [RTL_GIGA_MAC_VER_15] = NULL,
3958                 [RTL_GIGA_MAC_VER_16] = NULL,
3959                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3960                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3961                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3962                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3963                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3964                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3965                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3966                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3967                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3968                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3969                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3970                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3971                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3972                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3973                 [RTL_GIGA_MAC_VER_31] = NULL,
3974                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3975                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3976                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3977                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3978                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3979                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3980                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3981                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3982                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3983                 [RTL_GIGA_MAC_VER_41] = NULL,
3984                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3985                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3986                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3987                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3988                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3989                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3990                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3991                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3992                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3993                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3994         };
3995         struct rtl8169_private *tp = netdev_priv(dev);
3996
3997         if (phy_configs[tp->mac_version])
3998                 phy_configs[tp->mac_version](tp);
3999 }
4000
4001 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4002 {
4003         if (!test_and_set_bit(flag, tp->wk.flags))
4004                 schedule_work(&tp->wk.work);
4005 }
4006
4007 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4008 {
4009         rtl_hw_phy_config(dev);
4010
4011         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4012                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4013                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4014                 netif_dbg(tp, drv, dev,
4015                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4016                 RTL_W8(tp, 0x82, 0x01);
4017         }
4018
4019         /* We may have called phy_speed_down before */
4020         phy_speed_up(tp->phydev);
4021
4022         genphy_soft_reset(tp->phydev);
4023 }
4024
4025 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4026 {
4027         rtl_lock_work(tp);
4028
4029         rtl_unlock_config_regs(tp);
4030
4031         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4032         RTL_R32(tp, MAC4);
4033
4034         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4035         RTL_R32(tp, MAC0);
4036
4037         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4038                 rtl_rar_exgmac_set(tp, addr);
4039
4040         rtl_lock_config_regs(tp);
4041
4042         rtl_unlock_work(tp);
4043 }
4044
4045 static int rtl_set_mac_address(struct net_device *dev, void *p)
4046 {
4047         struct rtl8169_private *tp = netdev_priv(dev);
4048         struct device *d = tp_to_dev(tp);
4049         int ret;
4050
4051         ret = eth_mac_addr(dev, p);
4052         if (ret)
4053                 return ret;
4054
4055         pm_runtime_get_noresume(d);
4056
4057         if (pm_runtime_active(d))
4058                 rtl_rar_set(tp, dev->dev_addr);
4059
4060         pm_runtime_put_noidle(d);
4061
4062         return 0;
4063 }
4064
4065 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4066 {
4067         struct rtl8169_private *tp = netdev_priv(dev);
4068
4069         if (!netif_running(dev))
4070                 return -ENODEV;
4071
4072         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4073 }
4074
4075 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4076 {
4077         switch (tp->mac_version) {
4078         case RTL_GIGA_MAC_VER_25:
4079         case RTL_GIGA_MAC_VER_26:
4080         case RTL_GIGA_MAC_VER_29:
4081         case RTL_GIGA_MAC_VER_30:
4082         case RTL_GIGA_MAC_VER_32:
4083         case RTL_GIGA_MAC_VER_33:
4084         case RTL_GIGA_MAC_VER_34:
4085         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4086                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4087                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4088                 break;
4089         default:
4090                 break;
4091         }
4092 }
4093
4094 static void rtl_pll_power_down(struct rtl8169_private *tp)
4095 {
4096         if (r8168_check_dash(tp))
4097                 return;
4098
4099         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4100             tp->mac_version == RTL_GIGA_MAC_VER_33)
4101                 rtl_ephy_write(tp, 0x19, 0xff64);
4102
4103         if (device_may_wakeup(tp_to_dev(tp))) {
4104                 phy_speed_down(tp->phydev, false);
4105                 rtl_wol_suspend_quirk(tp);
4106                 return;
4107         }
4108
4109         switch (tp->mac_version) {
4110         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4111         case RTL_GIGA_MAC_VER_37:
4112         case RTL_GIGA_MAC_VER_39:
4113         case RTL_GIGA_MAC_VER_43:
4114         case RTL_GIGA_MAC_VER_44:
4115         case RTL_GIGA_MAC_VER_45:
4116         case RTL_GIGA_MAC_VER_46:
4117         case RTL_GIGA_MAC_VER_47:
4118         case RTL_GIGA_MAC_VER_48:
4119         case RTL_GIGA_MAC_VER_50:
4120         case RTL_GIGA_MAC_VER_51:
4121                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4122                 break;
4123         case RTL_GIGA_MAC_VER_40:
4124         case RTL_GIGA_MAC_VER_41:
4125         case RTL_GIGA_MAC_VER_49:
4126                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4127                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4128                 break;
4129         default:
4130                 break;
4131         }
4132 }
4133
4134 static void rtl_pll_power_up(struct rtl8169_private *tp)
4135 {
4136         switch (tp->mac_version) {
4137         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4138         case RTL_GIGA_MAC_VER_37:
4139         case RTL_GIGA_MAC_VER_39:
4140         case RTL_GIGA_MAC_VER_43:
4141                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4142                 break;
4143         case RTL_GIGA_MAC_VER_44:
4144         case RTL_GIGA_MAC_VER_45:
4145         case RTL_GIGA_MAC_VER_46:
4146         case RTL_GIGA_MAC_VER_47:
4147         case RTL_GIGA_MAC_VER_48:
4148         case RTL_GIGA_MAC_VER_50:
4149         case RTL_GIGA_MAC_VER_51:
4150                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4151                 break;
4152         case RTL_GIGA_MAC_VER_40:
4153         case RTL_GIGA_MAC_VER_41:
4154         case RTL_GIGA_MAC_VER_49:
4155                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4156                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4157                 break;
4158         default:
4159                 break;
4160         }
4161
4162         phy_resume(tp->phydev);
4163         /* give MAC/PHY some time to resume */
4164         msleep(20);
4165 }
4166
4167 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4168 {
4169         switch (tp->mac_version) {
4170         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4171         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4172                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4173                 break;
4174         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4175         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4176         case RTL_GIGA_MAC_VER_38:
4177                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4178                 break;
4179         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4180                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4181                 break;
4182         default:
4183                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4184                 break;
4185         }
4186 }
4187
4188 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4189 {
4190         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4191 }
4192
4193 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4194 {
4195         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4196         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4197         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4198 }
4199
4200 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4201 {
4202         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4203         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4204         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4205 }
4206
4207 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4208 {
4209         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4210 }
4211
4212 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4213 {
4214         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4215 }
4216
4217 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4218 {
4219         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4220         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4221         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4222         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4223 }
4224
4225 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4226 {
4227         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4228         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4229         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4230         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4231 }
4232
4233 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4234 {
4235         rtl_tx_performance_tweak(tp,
4236                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4237 }
4238
4239 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4240 {
4241         rtl_tx_performance_tweak(tp,
4242                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4243 }
4244
4245 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4246 {
4247         r8168b_0_hw_jumbo_enable(tp);
4248
4249         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4250 }
4251
4252 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4253 {
4254         r8168b_0_hw_jumbo_disable(tp);
4255
4256         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4257 }
4258
4259 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4260 {
4261         rtl_unlock_config_regs(tp);
4262         switch (tp->mac_version) {
4263         case RTL_GIGA_MAC_VER_11:
4264                 r8168b_0_hw_jumbo_enable(tp);
4265                 break;
4266         case RTL_GIGA_MAC_VER_12:
4267         case RTL_GIGA_MAC_VER_17:
4268                 r8168b_1_hw_jumbo_enable(tp);
4269                 break;
4270         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4271                 r8168c_hw_jumbo_enable(tp);
4272                 break;
4273         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4274                 r8168dp_hw_jumbo_enable(tp);
4275                 break;
4276         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4277                 r8168e_hw_jumbo_enable(tp);
4278                 break;
4279         default:
4280                 break;
4281         }
4282         rtl_lock_config_regs(tp);
4283 }
4284
4285 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4286 {
4287         rtl_unlock_config_regs(tp);
4288         switch (tp->mac_version) {
4289         case RTL_GIGA_MAC_VER_11:
4290                 r8168b_0_hw_jumbo_disable(tp);
4291                 break;
4292         case RTL_GIGA_MAC_VER_12:
4293         case RTL_GIGA_MAC_VER_17:
4294                 r8168b_1_hw_jumbo_disable(tp);
4295                 break;
4296         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4297                 r8168c_hw_jumbo_disable(tp);
4298                 break;
4299         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4300                 r8168dp_hw_jumbo_disable(tp);
4301                 break;
4302         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4303                 r8168e_hw_jumbo_disable(tp);
4304                 break;
4305         default:
4306                 break;
4307         }
4308         rtl_lock_config_regs(tp);
4309 }
4310
4311 DECLARE_RTL_COND(rtl_chipcmd_cond)
4312 {
4313         return RTL_R8(tp, ChipCmd) & CmdReset;
4314 }
4315
4316 static void rtl_hw_reset(struct rtl8169_private *tp)
4317 {
4318         RTL_W8(tp, ChipCmd, CmdReset);
4319
4320         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4321 }
4322
4323 static void rtl_request_firmware(struct rtl8169_private *tp)
4324 {
4325         struct rtl_fw *rtl_fw;
4326         int rc = -ENOMEM;
4327
4328         /* firmware loaded already or no firmware available */
4329         if (tp->rtl_fw || !tp->fw_name)
4330                 return;
4331
4332         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4333         if (!rtl_fw)
4334                 goto err_warn;
4335
4336         rtl_fw->phy_write = rtl_writephy;
4337         rtl_fw->phy_read = rtl_readphy;
4338         rtl_fw->mac_mcu_write = mac_mcu_write;
4339         rtl_fw->mac_mcu_read = mac_mcu_read;
4340
4341         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4342         if (rc < 0)
4343                 goto err_free;
4344
4345         rc = rtl_check_firmware(tp, rtl_fw);
4346         if (rc < 0)
4347                 goto err_release_firmware;
4348
4349         tp->rtl_fw = rtl_fw;
4350
4351         return;
4352
4353 err_release_firmware:
4354         release_firmware(rtl_fw->fw);
4355 err_free:
4356         kfree(rtl_fw);
4357 err_warn:
4358         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4359                    tp->fw_name, rc);
4360 }
4361
4362 static void rtl_rx_close(struct rtl8169_private *tp)
4363 {
4364         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4365 }
4366
4367 DECLARE_RTL_COND(rtl_npq_cond)
4368 {
4369         return RTL_R8(tp, TxPoll) & NPQ;
4370 }
4371
4372 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4373 {
4374         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4375 }
4376
4377 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4378 {
4379         /* Disable interrupts */
4380         rtl8169_irq_mask_and_ack(tp);
4381
4382         rtl_rx_close(tp);
4383
4384         switch (tp->mac_version) {
4385         case RTL_GIGA_MAC_VER_27:
4386         case RTL_GIGA_MAC_VER_28:
4387         case RTL_GIGA_MAC_VER_31:
4388                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4389                 break;
4390         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4391         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4392                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4393                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4394                 break;
4395         default:
4396                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4397                 udelay(100);
4398                 break;
4399         }
4400
4401         rtl_hw_reset(tp);
4402 }
4403
4404 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4405 {
4406         u32 val = TX_DMA_BURST << TxDMAShift |
4407                   InterFrameGap << TxInterFrameGapShift;
4408
4409         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4410             tp->mac_version != RTL_GIGA_MAC_VER_39)
4411                 val |= TXCFG_AUTO_FIFO;
4412
4413         RTL_W32(tp, TxConfig, val);
4414 }
4415
4416 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4417 {
4418         /* Low hurts. Let's disable the filtering. */
4419         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4420 }
4421
4422 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4423 {
4424         /*
4425          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4426          * register to be written before TxDescAddrLow to work.
4427          * Switching from MMIO to I/O access fixes the issue as well.
4428          */
4429         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4430         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4431         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4432         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4433 }
4434
4435 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4436 {
4437         u32 val;
4438
4439         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4440                 val = 0x000fff00;
4441         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4442                 val = 0x00ffff00;
4443         else
4444                 return;
4445
4446         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4447                 val |= 0xff;
4448
4449         RTL_W32(tp, 0x7c, val);
4450 }
4451
4452 static void rtl_set_rx_mode(struct net_device *dev)
4453 {
4454         struct rtl8169_private *tp = netdev_priv(dev);
4455         u32 mc_filter[2];       /* Multicast hash filter */
4456         int rx_mode;
4457         u32 tmp = 0;
4458
4459         if (dev->flags & IFF_PROMISC) {
4460                 /* Unconditionally log net taps. */
4461                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4462                 rx_mode =
4463                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4464                     AcceptAllPhys;
4465                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4466         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4467                    (dev->flags & IFF_ALLMULTI)) {
4468                 /* Too many to filter perfectly -- accept all multicasts. */
4469                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4470                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4471         } else {
4472                 struct netdev_hw_addr *ha;
4473
4474                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4475                 mc_filter[1] = mc_filter[0] = 0;
4476                 netdev_for_each_mc_addr(ha, dev) {
4477                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4478                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4479                         rx_mode |= AcceptMulticast;
4480                 }
4481         }
4482
4483         if (dev->features & NETIF_F_RXALL)
4484                 rx_mode |= (AcceptErr | AcceptRunt);
4485
4486         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4487
4488         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4489                 u32 data = mc_filter[0];
4490
4491                 mc_filter[0] = swab32(mc_filter[1]);
4492                 mc_filter[1] = swab32(data);
4493         }
4494
4495         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4496                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4497
4498         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4499         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4500
4501         RTL_W32(tp, RxConfig, tmp);
4502 }
4503
4504 static void rtl_hw_start(struct  rtl8169_private *tp)
4505 {
4506         rtl_unlock_config_regs(tp);
4507
4508         tp->hw_start(tp);
4509
4510         rtl_set_rx_max_size(tp);
4511         rtl_set_rx_tx_desc_registers(tp);
4512         rtl_lock_config_regs(tp);
4513
4514         /* disable interrupt coalescing */
4515         RTL_W16(tp, IntrMitigate, 0x0000);
4516         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4517         RTL_R8(tp, IntrMask);
4518         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4519         rtl_init_rxcfg(tp);
4520         rtl_set_tx_config_registers(tp);
4521
4522         rtl_set_rx_mode(tp->dev);
4523         /* no early-rx interrupts */
4524         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4525         rtl_irq_enable(tp);
4526 }
4527
4528 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4529 {
4530         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4531                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4532
4533         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4534
4535         tp->cp_cmd |= PCIMulRW;
4536
4537         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4538             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4539                 netif_dbg(tp, drv, tp->dev,
4540                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4541                 tp->cp_cmd |= (1 << 14);
4542         }
4543
4544         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4545
4546         rtl8169_set_magic_reg(tp, tp->mac_version);
4547
4548         RTL_W32(tp, RxMissed, 0);
4549 }
4550
4551 DECLARE_RTL_COND(rtl_csiar_cond)
4552 {
4553         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4554 }
4555
4556 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4557 {
4558         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4559
4560         RTL_W32(tp, CSIDR, value);
4561         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4562                 CSIAR_BYTE_ENABLE | func << 16);
4563
4564         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4565 }
4566
4567 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4568 {
4569         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4570
4571         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4572                 CSIAR_BYTE_ENABLE);
4573
4574         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4575                 RTL_R32(tp, CSIDR) : ~0;
4576 }
4577
4578 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4579 {
4580         struct pci_dev *pdev = tp->pci_dev;
4581         u32 csi;
4582
4583         /* According to Realtek the value at config space address 0x070f
4584          * controls the L0s/L1 entrance latency. We try standard ECAM access
4585          * first and if it fails fall back to CSI.
4586          */
4587         if (pdev->cfg_size > 0x070f &&
4588             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4589                 return;
4590
4591         netdev_notice_once(tp->dev,
4592                 "No native access to PCI extended config space, falling back to CSI\n");
4593         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4594         rtl_csi_write(tp, 0x070c, csi | val << 24);
4595 }
4596
4597 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4598 {
4599         rtl_csi_access_enable(tp, 0x27);
4600 }
4601
4602 struct ephy_info {
4603         unsigned int offset;
4604         u16 mask;
4605         u16 bits;
4606 };
4607
4608 static void __rtl_ephy_init(struct rtl8169_private *tp,
4609                             const struct ephy_info *e, int len)
4610 {
4611         u16 w;
4612
4613         while (len-- > 0) {
4614                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4615                 rtl_ephy_write(tp, e->offset, w);
4616                 e++;
4617         }
4618 }
4619
4620 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4621
4622 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4623 {
4624         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4625                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4626 }
4627
4628 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4629 {
4630         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4631                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4632 }
4633
4634 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4635 {
4636         /* work around an issue when PCI reset occurs during L2/L3 state */
4637         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4638 }
4639
4640 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4641 {
4642         if (enable) {
4643                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4644                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4645         } else {
4646                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4647                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4648         }
4649
4650         udelay(10);
4651 }
4652
4653 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4654                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4655 {
4656         /* Usage of dynamic vs. static FIFO is controlled by bit
4657          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4658          */
4659         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4660         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4661 }
4662
4663 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4664                                           u8 low, u8 high)
4665 {
4666         /* FIFO thresholds for pause flow control */
4667         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4668         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4669 }
4670
4671 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4672 {
4673         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4674
4675         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4676         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4677
4678         if (tp->dev->mtu <= ETH_DATA_LEN) {
4679                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4680                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4681         }
4682 }
4683
4684 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4685 {
4686         rtl_hw_start_8168bb(tp);
4687
4688         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4689
4690         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4691 }
4692
4693 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4694 {
4695         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4696
4697         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4698
4699         if (tp->dev->mtu <= ETH_DATA_LEN)
4700                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4701
4702         rtl_disable_clock_request(tp);
4703
4704         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4705         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4706 }
4707
4708 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4709 {
4710         static const struct ephy_info e_info_8168cp[] = {
4711                 { 0x01, 0,      0x0001 },
4712                 { 0x02, 0x0800, 0x1000 },
4713                 { 0x03, 0,      0x0042 },
4714                 { 0x06, 0x0080, 0x0000 },
4715                 { 0x07, 0,      0x2000 }
4716         };
4717
4718         rtl_set_def_aspm_entry_latency(tp);
4719
4720         rtl_ephy_init(tp, e_info_8168cp);
4721
4722         __rtl_hw_start_8168cp(tp);
4723 }
4724
4725 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4726 {
4727         rtl_set_def_aspm_entry_latency(tp);
4728
4729         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4730
4731         if (tp->dev->mtu <= ETH_DATA_LEN)
4732                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4733
4734         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4735         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4736 }
4737
4738 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4739 {
4740         rtl_set_def_aspm_entry_latency(tp);
4741
4742         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4743
4744         /* Magic. */
4745         RTL_W8(tp, DBG_REG, 0x20);
4746
4747         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4748
4749         if (tp->dev->mtu <= ETH_DATA_LEN)
4750                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4751
4752         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4753         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4754 }
4755
4756 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4757 {
4758         static const struct ephy_info e_info_8168c_1[] = {
4759                 { 0x02, 0x0800, 0x1000 },
4760                 { 0x03, 0,      0x0002 },
4761                 { 0x06, 0x0080, 0x0000 }
4762         };
4763
4764         rtl_set_def_aspm_entry_latency(tp);
4765
4766         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4767
4768         rtl_ephy_init(tp, e_info_8168c_1);
4769
4770         __rtl_hw_start_8168cp(tp);
4771 }
4772
4773 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4774 {
4775         static const struct ephy_info e_info_8168c_2[] = {
4776                 { 0x01, 0,      0x0001 },
4777                 { 0x03, 0x0400, 0x0220 }
4778         };
4779
4780         rtl_set_def_aspm_entry_latency(tp);
4781
4782         rtl_ephy_init(tp, e_info_8168c_2);
4783
4784         __rtl_hw_start_8168cp(tp);
4785 }
4786
4787 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4788 {
4789         rtl_hw_start_8168c_2(tp);
4790 }
4791
4792 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4793 {
4794         rtl_set_def_aspm_entry_latency(tp);
4795
4796         __rtl_hw_start_8168cp(tp);
4797 }
4798
4799 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4800 {
4801         rtl_set_def_aspm_entry_latency(tp);
4802
4803         rtl_disable_clock_request(tp);
4804
4805         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4806
4807         if (tp->dev->mtu <= ETH_DATA_LEN)
4808                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4809
4810         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4811         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4812 }
4813
4814 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4815 {
4816         rtl_set_def_aspm_entry_latency(tp);
4817
4818         if (tp->dev->mtu <= ETH_DATA_LEN)
4819                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4820
4821         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4822
4823         rtl_disable_clock_request(tp);
4824 }
4825
4826 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4827 {
4828         static const struct ephy_info e_info_8168d_4[] = {
4829                 { 0x0b, 0x0000, 0x0048 },
4830                 { 0x19, 0x0020, 0x0050 },
4831                 { 0x0c, 0x0100, 0x0020 }
4832         };
4833
4834         rtl_set_def_aspm_entry_latency(tp);
4835
4836         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4837
4838         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4839
4840         rtl_ephy_init(tp, e_info_8168d_4);
4841
4842         rtl_enable_clock_request(tp);
4843 }
4844
4845 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4846 {
4847         static const struct ephy_info e_info_8168e_1[] = {
4848                 { 0x00, 0x0200, 0x0100 },
4849                 { 0x00, 0x0000, 0x0004 },
4850                 { 0x06, 0x0002, 0x0001 },
4851                 { 0x06, 0x0000, 0x0030 },
4852                 { 0x07, 0x0000, 0x2000 },
4853                 { 0x00, 0x0000, 0x0020 },
4854                 { 0x03, 0x5800, 0x2000 },
4855                 { 0x03, 0x0000, 0x0001 },
4856                 { 0x01, 0x0800, 0x1000 },
4857                 { 0x07, 0x0000, 0x4000 },
4858                 { 0x1e, 0x0000, 0x2000 },
4859                 { 0x19, 0xffff, 0xfe6c },
4860                 { 0x0a, 0x0000, 0x0040 }
4861         };
4862
4863         rtl_set_def_aspm_entry_latency(tp);
4864
4865         rtl_ephy_init(tp, e_info_8168e_1);
4866
4867         if (tp->dev->mtu <= ETH_DATA_LEN)
4868                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4869
4870         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4871
4872         rtl_disable_clock_request(tp);
4873
4874         /* Reset tx FIFO pointer */
4875         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4876         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4877
4878         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4879 }
4880
4881 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4882 {
4883         static const struct ephy_info e_info_8168e_2[] = {
4884                 { 0x09, 0x0000, 0x0080 },
4885                 { 0x19, 0x0000, 0x0224 }
4886         };
4887
4888         rtl_set_def_aspm_entry_latency(tp);
4889
4890         rtl_ephy_init(tp, e_info_8168e_2);
4891
4892         if (tp->dev->mtu <= ETH_DATA_LEN)
4893                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4894
4895         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4896         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4897         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4898         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4899         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4900         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4901         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4902
4903         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4904
4905         rtl_disable_clock_request(tp);
4906
4907         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4908
4909         rtl8168_config_eee_mac(tp);
4910
4911         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4912         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4913         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4914
4915         rtl_hw_aspm_clkreq_enable(tp, true);
4916 }
4917
4918 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4919 {
4920         rtl_set_def_aspm_entry_latency(tp);
4921
4922         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4923
4924         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4925         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4926         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4927         rtl_reset_packet_filter(tp);
4928         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4929         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4930         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4931         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4932
4933         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4934
4935         rtl_disable_clock_request(tp);
4936
4937         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4938         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4939         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4940         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4941
4942         rtl8168_config_eee_mac(tp);
4943 }
4944
4945 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4946 {
4947         static const struct ephy_info e_info_8168f_1[] = {
4948                 { 0x06, 0x00c0, 0x0020 },
4949                 { 0x08, 0x0001, 0x0002 },
4950                 { 0x09, 0x0000, 0x0080 },
4951                 { 0x19, 0x0000, 0x0224 }
4952         };
4953
4954         rtl_hw_start_8168f(tp);
4955
4956         rtl_ephy_init(tp, e_info_8168f_1);
4957
4958         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4959 }
4960
4961 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4962 {
4963         static const struct ephy_info e_info_8168f_1[] = {
4964                 { 0x06, 0x00c0, 0x0020 },
4965                 { 0x0f, 0xffff, 0x5200 },
4966                 { 0x1e, 0x0000, 0x4000 },
4967                 { 0x19, 0x0000, 0x0224 }
4968         };
4969
4970         rtl_hw_start_8168f(tp);
4971         rtl_pcie_state_l2l3_disable(tp);
4972
4973         rtl_ephy_init(tp, e_info_8168f_1);
4974
4975         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4976 }
4977
4978 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4979 {
4980         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4981         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4982
4983         rtl_set_def_aspm_entry_latency(tp);
4984
4985         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4986
4987         rtl_reset_packet_filter(tp);
4988         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4989
4990         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4991         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4992
4993         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4994         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4995
4996         rtl8168_config_eee_mac(tp);
4997
4998         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4999         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5000
5001         rtl_pcie_state_l2l3_disable(tp);
5002 }
5003
5004 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5005 {
5006         static const struct ephy_info e_info_8168g_1[] = {
5007                 { 0x00, 0x0000, 0x0008 },
5008                 { 0x0c, 0x37d0, 0x0820 },
5009                 { 0x1e, 0x0000, 0x0001 },
5010                 { 0x19, 0x8000, 0x0000 }
5011         };
5012
5013         rtl_hw_start_8168g(tp);
5014
5015         /* disable aspm and clock request before access ephy */
5016         rtl_hw_aspm_clkreq_enable(tp, false);
5017         rtl_ephy_init(tp, e_info_8168g_1);
5018         rtl_hw_aspm_clkreq_enable(tp, true);
5019 }
5020
5021 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5022 {
5023         static const struct ephy_info e_info_8168g_2[] = {
5024                 { 0x00, 0x0000, 0x0008 },
5025                 { 0x0c, 0x3df0, 0x0200 },
5026                 { 0x19, 0xffff, 0xfc00 },
5027                 { 0x1e, 0xffff, 0x20eb }
5028         };
5029
5030         rtl_hw_start_8168g(tp);
5031
5032         /* disable aspm and clock request before access ephy */
5033         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5034         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5035         rtl_ephy_init(tp, e_info_8168g_2);
5036 }
5037
5038 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5039 {
5040         static const struct ephy_info e_info_8411_2[] = {
5041                 { 0x00, 0x0000, 0x0008 },
5042                 { 0x0c, 0x3df0, 0x0200 },
5043                 { 0x0f, 0xffff, 0x5200 },
5044                 { 0x19, 0x0020, 0x0000 },
5045                 { 0x1e, 0x0000, 0x2000 }
5046         };
5047
5048         rtl_hw_start_8168g(tp);
5049
5050         /* disable aspm and clock request before access ephy */
5051         rtl_hw_aspm_clkreq_enable(tp, false);
5052         rtl_ephy_init(tp, e_info_8411_2);
5053         rtl_hw_aspm_clkreq_enable(tp, true);
5054 }
5055
5056 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5057 {
5058         int rg_saw_cnt;
5059         u32 data;
5060         static const struct ephy_info e_info_8168h_1[] = {
5061                 { 0x1e, 0x0800, 0x0001 },
5062                 { 0x1d, 0x0000, 0x0800 },
5063                 { 0x05, 0xffff, 0x2089 },
5064                 { 0x06, 0xffff, 0x5881 },
5065                 { 0x04, 0xffff, 0x154a },
5066                 { 0x01, 0xffff, 0x068b }
5067         };
5068
5069         /* disable aspm and clock request before access ephy */
5070         rtl_hw_aspm_clkreq_enable(tp, false);
5071         rtl_ephy_init(tp, e_info_8168h_1);
5072
5073         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5074         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5075
5076         rtl_set_def_aspm_entry_latency(tp);
5077
5078         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5079
5080         rtl_reset_packet_filter(tp);
5081
5082         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5083
5084         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5085
5086         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5087
5088         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5089         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5090
5091         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5092         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5093
5094         rtl8168_config_eee_mac(tp);
5095
5096         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5097         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5098
5099         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5100
5101         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5102
5103         rtl_pcie_state_l2l3_disable(tp);
5104
5105         rtl_writephy(tp, 0x1f, 0x0c42);
5106         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5107         rtl_writephy(tp, 0x1f, 0x0000);
5108         if (rg_saw_cnt > 0) {
5109                 u16 sw_cnt_1ms_ini;
5110
5111                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5112                 sw_cnt_1ms_ini &= 0x0fff;
5113                 data = r8168_mac_ocp_read(tp, 0xd412);
5114                 data &= ~0x0fff;
5115                 data |= sw_cnt_1ms_ini;
5116                 r8168_mac_ocp_write(tp, 0xd412, data);
5117         }
5118
5119         data = r8168_mac_ocp_read(tp, 0xe056);
5120         data &= ~0xf0;
5121         data |= 0x70;
5122         r8168_mac_ocp_write(tp, 0xe056, data);
5123
5124         data = r8168_mac_ocp_read(tp, 0xe052);
5125         data &= ~0x6000;
5126         data |= 0x8008;
5127         r8168_mac_ocp_write(tp, 0xe052, data);
5128
5129         data = r8168_mac_ocp_read(tp, 0xe0d6);
5130         data &= ~0x01ff;
5131         data |= 0x017f;
5132         r8168_mac_ocp_write(tp, 0xe0d6, data);
5133
5134         data = r8168_mac_ocp_read(tp, 0xd420);
5135         data &= ~0x0fff;
5136         data |= 0x047f;
5137         r8168_mac_ocp_write(tp, 0xd420, data);
5138
5139         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5140         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5141         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5142         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5143
5144         rtl_hw_aspm_clkreq_enable(tp, true);
5145 }
5146
5147 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5148 {
5149         rtl8168ep_stop_cmac(tp);
5150
5151         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5152         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5153
5154         rtl_set_def_aspm_entry_latency(tp);
5155
5156         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5157
5158         rtl_reset_packet_filter(tp);
5159
5160         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5161
5162         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5163
5164         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5165         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5166
5167         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5168         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5169
5170         rtl8168_config_eee_mac(tp);
5171
5172         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5173
5174         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5175
5176         rtl_pcie_state_l2l3_disable(tp);
5177 }
5178
5179 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5180 {
5181         static const struct ephy_info e_info_8168ep_1[] = {
5182                 { 0x00, 0xffff, 0x10ab },
5183                 { 0x06, 0xffff, 0xf030 },
5184                 { 0x08, 0xffff, 0x2006 },
5185                 { 0x0d, 0xffff, 0x1666 },
5186                 { 0x0c, 0x3ff0, 0x0000 }
5187         };
5188
5189         /* disable aspm and clock request before access ephy */
5190         rtl_hw_aspm_clkreq_enable(tp, false);
5191         rtl_ephy_init(tp, e_info_8168ep_1);
5192
5193         rtl_hw_start_8168ep(tp);
5194
5195         rtl_hw_aspm_clkreq_enable(tp, true);
5196 }
5197
5198 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5199 {
5200         static const struct ephy_info e_info_8168ep_2[] = {
5201                 { 0x00, 0xffff, 0x10a3 },
5202                 { 0x19, 0xffff, 0xfc00 },
5203                 { 0x1e, 0xffff, 0x20ea }
5204         };
5205
5206         /* disable aspm and clock request before access ephy */
5207         rtl_hw_aspm_clkreq_enable(tp, false);
5208         rtl_ephy_init(tp, e_info_8168ep_2);
5209
5210         rtl_hw_start_8168ep(tp);
5211
5212         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5213         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5214
5215         rtl_hw_aspm_clkreq_enable(tp, true);
5216 }
5217
5218 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5219 {
5220         u32 data;
5221         static const struct ephy_info e_info_8168ep_3[] = {
5222                 { 0x00, 0xffff, 0x10a3 },
5223                 { 0x19, 0xffff, 0x7c00 },
5224                 { 0x1e, 0xffff, 0x20eb },
5225                 { 0x0d, 0xffff, 0x1666 }
5226         };
5227
5228         /* disable aspm and clock request before access ephy */
5229         rtl_hw_aspm_clkreq_enable(tp, false);
5230         rtl_ephy_init(tp, e_info_8168ep_3);
5231
5232         rtl_hw_start_8168ep(tp);
5233
5234         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5235         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5236
5237         data = r8168_mac_ocp_read(tp, 0xd3e2);
5238         data &= 0xf000;
5239         data |= 0x0271;
5240         r8168_mac_ocp_write(tp, 0xd3e2, data);
5241
5242         data = r8168_mac_ocp_read(tp, 0xd3e4);
5243         data &= 0xff00;
5244         r8168_mac_ocp_write(tp, 0xd3e4, data);
5245
5246         data = r8168_mac_ocp_read(tp, 0xe860);
5247         data |= 0x0080;
5248         r8168_mac_ocp_write(tp, 0xe860, data);
5249
5250         rtl_hw_aspm_clkreq_enable(tp, true);
5251 }
5252
5253 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5254 {
5255         static const struct ephy_info e_info_8102e_1[] = {
5256                 { 0x01, 0, 0x6e65 },
5257                 { 0x02, 0, 0x091f },
5258                 { 0x03, 0, 0xc2f9 },
5259                 { 0x06, 0, 0xafb5 },
5260                 { 0x07, 0, 0x0e00 },
5261                 { 0x19, 0, 0xec80 },
5262                 { 0x01, 0, 0x2e65 },
5263                 { 0x01, 0, 0x6e65 }
5264         };
5265         u8 cfg1;
5266
5267         rtl_set_def_aspm_entry_latency(tp);
5268
5269         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5270
5271         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5272
5273         RTL_W8(tp, Config1,
5274                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5275         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5276
5277         cfg1 = RTL_R8(tp, Config1);
5278         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5279                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5280
5281         rtl_ephy_init(tp, e_info_8102e_1);
5282 }
5283
5284 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5285 {
5286         rtl_set_def_aspm_entry_latency(tp);
5287
5288         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5289
5290         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5291         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5292 }
5293
5294 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5295 {
5296         rtl_hw_start_8102e_2(tp);
5297
5298         rtl_ephy_write(tp, 0x03, 0xc2f9);
5299 }
5300
5301 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5302 {
5303         static const struct ephy_info e_info_8105e_1[] = {
5304                 { 0x07, 0, 0x4000 },
5305                 { 0x19, 0, 0x0200 },
5306                 { 0x19, 0, 0x0020 },
5307                 { 0x1e, 0, 0x2000 },
5308                 { 0x03, 0, 0x0001 },
5309                 { 0x19, 0, 0x0100 },
5310                 { 0x19, 0, 0x0004 },
5311                 { 0x0a, 0, 0x0020 }
5312         };
5313
5314         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5315         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5316
5317         /* Disable Early Tally Counter */
5318         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5319
5320         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5321         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5322
5323         rtl_ephy_init(tp, e_info_8105e_1);
5324
5325         rtl_pcie_state_l2l3_disable(tp);
5326 }
5327
5328 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5329 {
5330         rtl_hw_start_8105e_1(tp);
5331         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5332 }
5333
5334 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5335 {
5336         static const struct ephy_info e_info_8402[] = {
5337                 { 0x19, 0xffff, 0xff64 },
5338                 { 0x1e, 0, 0x4000 }
5339         };
5340
5341         rtl_set_def_aspm_entry_latency(tp);
5342
5343         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5344         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5345
5346         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5347
5348         rtl_ephy_init(tp, e_info_8402);
5349
5350         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5351
5352         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5353         rtl_reset_packet_filter(tp);
5354         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5355         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5356         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5357
5358         rtl_pcie_state_l2l3_disable(tp);
5359 }
5360
5361 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5362 {
5363         rtl_hw_aspm_clkreq_enable(tp, false);
5364
5365         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5366         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5367
5368         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5369         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5370         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5371
5372         rtl_pcie_state_l2l3_disable(tp);
5373         rtl_hw_aspm_clkreq_enable(tp, true);
5374 }
5375
5376 static void rtl_hw_config(struct rtl8169_private *tp)
5377 {
5378         static const rtl_generic_fct hw_configs[] = {
5379                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5380                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5381                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5382                 [RTL_GIGA_MAC_VER_10] = NULL,
5383                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5384                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5385                 [RTL_GIGA_MAC_VER_13] = NULL,
5386                 [RTL_GIGA_MAC_VER_14] = NULL,
5387                 [RTL_GIGA_MAC_VER_15] = NULL,
5388                 [RTL_GIGA_MAC_VER_16] = NULL,
5389                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5390                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5391                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5392                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5393                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5394                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5395                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5396                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5397                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5398                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5399                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5400                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5401                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5402                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5403                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5404                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5405                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5406                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5407                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5408                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5409                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5410                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5411                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5412                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5413                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5414                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5415                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5416                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5417                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5418                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5419                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5420                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5421                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5422                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5423                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5424         };
5425
5426         if (hw_configs[tp->mac_version])
5427                 hw_configs[tp->mac_version](tp);
5428 }
5429
5430 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5431 {
5432         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5433
5434         /* Workaround for RxFIFO overflow. */
5435         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5436                 tp->irq_mask |= RxFIFOOver;
5437                 tp->irq_mask &= ~RxOverflow;
5438         }
5439
5440         rtl_hw_config(tp);
5441 }
5442
5443 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5444 {
5445         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5446                 tp->irq_mask &= ~RxFIFOOver;
5447
5448         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5449             tp->mac_version == RTL_GIGA_MAC_VER_16)
5450                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5451                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5452
5453         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5454
5455         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5456         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5457
5458         rtl_hw_config(tp);
5459 }
5460
5461 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5462 {
5463         struct rtl8169_private *tp = netdev_priv(dev);
5464
5465         if (new_mtu > ETH_DATA_LEN)
5466                 rtl_hw_jumbo_enable(tp);
5467         else
5468                 rtl_hw_jumbo_disable(tp);
5469
5470         dev->mtu = new_mtu;
5471         netdev_update_features(dev);
5472
5473         return 0;
5474 }
5475
5476 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5477 {
5478         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5479         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5480 }
5481
5482 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5483                                      void **data_buff, struct RxDesc *desc)
5484 {
5485         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5486                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5487
5488         kfree(*data_buff);
5489         *data_buff = NULL;
5490         rtl8169_make_unusable_by_asic(desc);
5491 }
5492
5493 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5494 {
5495         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5496
5497         /* Force memory writes to complete before releasing descriptor */
5498         dma_wmb();
5499
5500         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5501 }
5502
5503 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5504                                              struct RxDesc *desc)
5505 {
5506         void *data;
5507         dma_addr_t mapping;
5508         struct device *d = tp_to_dev(tp);
5509         int node = dev_to_node(d);
5510
5511         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5512         if (!data)
5513                 return NULL;
5514
5515         /* Memory should be properly aligned, but better check. */
5516         if (!IS_ALIGNED((unsigned long)data, 8)) {
5517                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5518                 goto err_out;
5519         }
5520
5521         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5522         if (unlikely(dma_mapping_error(d, mapping))) {
5523                 if (net_ratelimit())
5524                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5525                 goto err_out;
5526         }
5527
5528         desc->addr = cpu_to_le64(mapping);
5529         rtl8169_mark_to_asic(desc);
5530         return data;
5531
5532 err_out:
5533         kfree(data);
5534         return NULL;
5535 }
5536
5537 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5538 {
5539         unsigned int i;
5540
5541         for (i = 0; i < NUM_RX_DESC; i++) {
5542                 if (tp->Rx_databuff[i]) {
5543                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5544                                             tp->RxDescArray + i);
5545                 }
5546         }
5547 }
5548
5549 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5550 {
5551         desc->opts1 |= cpu_to_le32(RingEnd);
5552 }
5553
5554 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5555 {
5556         unsigned int i;
5557
5558         for (i = 0; i < NUM_RX_DESC; i++) {
5559                 void *data;
5560
5561                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5562                 if (!data) {
5563                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5564                         goto err_out;
5565                 }
5566                 tp->Rx_databuff[i] = data;
5567         }
5568
5569         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5570         return 0;
5571
5572 err_out:
5573         rtl8169_rx_clear(tp);
5574         return -ENOMEM;
5575 }
5576
5577 static int rtl8169_init_ring(struct rtl8169_private *tp)
5578 {
5579         rtl8169_init_ring_indexes(tp);
5580
5581         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5582         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5583
5584         return rtl8169_rx_fill(tp);
5585 }
5586
5587 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5588                                  struct TxDesc *desc)
5589 {
5590         unsigned int len = tx_skb->len;
5591
5592         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5593
5594         desc->opts1 = 0x00;
5595         desc->opts2 = 0x00;
5596         desc->addr = 0x00;
5597         tx_skb->len = 0;
5598 }
5599
5600 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5601                                    unsigned int n)
5602 {
5603         unsigned int i;
5604
5605         for (i = 0; i < n; i++) {
5606                 unsigned int entry = (start + i) % NUM_TX_DESC;
5607                 struct ring_info *tx_skb = tp->tx_skb + entry;
5608                 unsigned int len = tx_skb->len;
5609
5610                 if (len) {
5611                         struct sk_buff *skb = tx_skb->skb;
5612
5613                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5614                                              tp->TxDescArray + entry);
5615                         if (skb) {
5616                                 dev_consume_skb_any(skb);
5617                                 tx_skb->skb = NULL;
5618                         }
5619                 }
5620         }
5621 }
5622
5623 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5624 {
5625         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5626         tp->cur_tx = tp->dirty_tx = 0;
5627         netdev_reset_queue(tp->dev);
5628 }
5629
5630 static void rtl_reset_work(struct rtl8169_private *tp)
5631 {
5632         struct net_device *dev = tp->dev;
5633         int i;
5634
5635         napi_disable(&tp->napi);
5636         netif_stop_queue(dev);
5637         synchronize_rcu();
5638
5639         rtl8169_hw_reset(tp);
5640
5641         for (i = 0; i < NUM_RX_DESC; i++)
5642                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5643
5644         rtl8169_tx_clear(tp);
5645         rtl8169_init_ring_indexes(tp);
5646
5647         napi_enable(&tp->napi);
5648         rtl_hw_start(tp);
5649         netif_wake_queue(dev);
5650 }
5651
5652 static void rtl8169_tx_timeout(struct net_device *dev)
5653 {
5654         struct rtl8169_private *tp = netdev_priv(dev);
5655
5656         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5657 }
5658
5659 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5660 {
5661         u32 status = opts0 | len;
5662
5663         if (entry == NUM_TX_DESC - 1)
5664                 status |= RingEnd;
5665
5666         return cpu_to_le32(status);
5667 }
5668
5669 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5670                               u32 *opts)
5671 {
5672         struct skb_shared_info *info = skb_shinfo(skb);
5673         unsigned int cur_frag, entry;
5674         struct TxDesc *uninitialized_var(txd);
5675         struct device *d = tp_to_dev(tp);
5676
5677         entry = tp->cur_tx;
5678         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5679                 const skb_frag_t *frag = info->frags + cur_frag;
5680                 dma_addr_t mapping;
5681                 u32 len;
5682                 void *addr;
5683
5684                 entry = (entry + 1) % NUM_TX_DESC;
5685
5686                 txd = tp->TxDescArray + entry;
5687                 len = skb_frag_size(frag);
5688                 addr = skb_frag_address(frag);
5689                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5690                 if (unlikely(dma_mapping_error(d, mapping))) {
5691                         if (net_ratelimit())
5692                                 netif_err(tp, drv, tp->dev,
5693                                           "Failed to map TX fragments DMA!\n");
5694                         goto err_out;
5695                 }
5696
5697                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5698                 txd->opts2 = cpu_to_le32(opts[1]);
5699                 txd->addr = cpu_to_le64(mapping);
5700
5701                 tp->tx_skb[entry].len = len;
5702         }
5703
5704         if (cur_frag) {
5705                 tp->tx_skb[entry].skb = skb;
5706                 txd->opts1 |= cpu_to_le32(LastFrag);
5707         }
5708
5709         return cur_frag;
5710
5711 err_out:
5712         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5713         return -EIO;
5714 }
5715
5716 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5717 {
5718         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5719 }
5720
5721 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5722                                       struct net_device *dev);
5723 /* r8169_csum_workaround()
5724  * The hw limites the value the transport offset. When the offset is out of the
5725  * range, calculate the checksum by sw.
5726  */
5727 static void r8169_csum_workaround(struct rtl8169_private *tp,
5728                                   struct sk_buff *skb)
5729 {
5730         if (skb_is_gso(skb)) {
5731                 netdev_features_t features = tp->dev->features;
5732                 struct sk_buff *segs, *nskb;
5733
5734                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5735                 segs = skb_gso_segment(skb, features);
5736                 if (IS_ERR(segs) || !segs)
5737                         goto drop;
5738
5739                 do {
5740                         nskb = segs;
5741                         segs = segs->next;
5742                         nskb->next = NULL;
5743                         rtl8169_start_xmit(nskb, tp->dev);
5744                 } while (segs);
5745
5746                 dev_consume_skb_any(skb);
5747         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5748                 if (skb_checksum_help(skb) < 0)
5749                         goto drop;
5750
5751                 rtl8169_start_xmit(skb, tp->dev);
5752         } else {
5753 drop:
5754                 tp->dev->stats.tx_dropped++;
5755                 dev_kfree_skb_any(skb);
5756         }
5757 }
5758
5759 /* msdn_giant_send_check()
5760  * According to the document of microsoft, the TCP Pseudo Header excludes the
5761  * packet length for IPv6 TCP large packets.
5762  */
5763 static int msdn_giant_send_check(struct sk_buff *skb)
5764 {
5765         const struct ipv6hdr *ipv6h;
5766         struct tcphdr *th;
5767         int ret;
5768
5769         ret = skb_cow_head(skb, 0);
5770         if (ret)
5771                 return ret;
5772
5773         ipv6h = ipv6_hdr(skb);
5774         th = tcp_hdr(skb);
5775
5776         th->check = 0;
5777         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5778
5779         return ret;
5780 }
5781
5782 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5783 {
5784         u32 mss = skb_shinfo(skb)->gso_size;
5785
5786         if (mss) {
5787                 opts[0] |= TD_LSO;
5788                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5789         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5790                 const struct iphdr *ip = ip_hdr(skb);
5791
5792                 if (ip->protocol == IPPROTO_TCP)
5793                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5794                 else if (ip->protocol == IPPROTO_UDP)
5795                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5796                 else
5797                         WARN_ON_ONCE(1);
5798         }
5799 }
5800
5801 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5802                                 struct sk_buff *skb, u32 *opts)
5803 {
5804         u32 transport_offset = (u32)skb_transport_offset(skb);
5805         u32 mss = skb_shinfo(skb)->gso_size;
5806
5807         if (mss) {
5808                 if (transport_offset > GTTCPHO_MAX) {
5809                         netif_warn(tp, tx_err, tp->dev,
5810                                    "Invalid transport offset 0x%x for TSO\n",
5811                                    transport_offset);
5812                         return false;
5813                 }
5814
5815                 switch (vlan_get_protocol(skb)) {
5816                 case htons(ETH_P_IP):
5817                         opts[0] |= TD1_GTSENV4;
5818                         break;
5819
5820                 case htons(ETH_P_IPV6):
5821                         if (msdn_giant_send_check(skb))
5822                                 return false;
5823
5824                         opts[0] |= TD1_GTSENV6;
5825                         break;
5826
5827                 default:
5828                         WARN_ON_ONCE(1);
5829                         break;
5830                 }
5831
5832                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5833                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5834         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5835                 u8 ip_protocol;
5836
5837                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5838                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5839
5840                 if (transport_offset > TCPHO_MAX) {
5841                         netif_warn(tp, tx_err, tp->dev,
5842                                    "Invalid transport offset 0x%x\n",
5843                                    transport_offset);
5844                         return false;
5845                 }
5846
5847                 switch (vlan_get_protocol(skb)) {
5848                 case htons(ETH_P_IP):
5849                         opts[1] |= TD1_IPv4_CS;
5850                         ip_protocol = ip_hdr(skb)->protocol;
5851                         break;
5852
5853                 case htons(ETH_P_IPV6):
5854                         opts[1] |= TD1_IPv6_CS;
5855                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5856                         break;
5857
5858                 default:
5859                         ip_protocol = IPPROTO_RAW;
5860                         break;
5861                 }
5862
5863                 if (ip_protocol == IPPROTO_TCP)
5864                         opts[1] |= TD1_TCP_CS;
5865                 else if (ip_protocol == IPPROTO_UDP)
5866                         opts[1] |= TD1_UDP_CS;
5867                 else
5868                         WARN_ON_ONCE(1);
5869
5870                 opts[1] |= transport_offset << TCPHO_SHIFT;
5871         } else {
5872                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5873                         return !eth_skb_pad(skb);
5874         }
5875
5876         return true;
5877 }
5878
5879 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5880                                unsigned int nr_frags)
5881 {
5882         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5883
5884         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5885         return slots_avail > nr_frags;
5886 }
5887
5888 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5889 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5890 {
5891         switch (tp->mac_version) {
5892         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5893         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5894                 return false;
5895         default:
5896                 return true;
5897         }
5898 }
5899
5900 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5901                                       struct net_device *dev)
5902 {
5903         struct rtl8169_private *tp = netdev_priv(dev);
5904         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5905         struct TxDesc *txd = tp->TxDescArray + entry;
5906         struct device *d = tp_to_dev(tp);
5907         dma_addr_t mapping;
5908         u32 opts[2], len;
5909         int frags;
5910
5911         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5912                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5913                 goto err_stop_0;
5914         }
5915
5916         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5917                 goto err_stop_0;
5918
5919         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5920         opts[0] = DescOwn;
5921
5922         if (rtl_chip_supports_csum_v2(tp)) {
5923                 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5924                         r8169_csum_workaround(tp, skb);
5925                         return NETDEV_TX_OK;
5926                 }
5927         } else {
5928                 rtl8169_tso_csum_v1(skb, opts);
5929         }
5930
5931         len = skb_headlen(skb);
5932         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5933         if (unlikely(dma_mapping_error(d, mapping))) {
5934                 if (net_ratelimit())
5935                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5936                 goto err_dma_0;
5937         }
5938
5939         tp->tx_skb[entry].len = len;
5940         txd->addr = cpu_to_le64(mapping);
5941
5942         frags = rtl8169_xmit_frags(tp, skb, opts);
5943         if (frags < 0)
5944                 goto err_dma_1;
5945         else if (frags)
5946                 opts[0] |= FirstFrag;
5947         else {
5948                 opts[0] |= FirstFrag | LastFrag;
5949                 tp->tx_skb[entry].skb = skb;
5950         }
5951
5952         txd->opts2 = cpu_to_le32(opts[1]);
5953
5954         netdev_sent_queue(dev, skb->len);
5955
5956         skb_tx_timestamp(skb);
5957
5958         /* Force memory writes to complete before releasing descriptor */
5959         dma_wmb();
5960
5961         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5962
5963         /* Force all memory writes to complete before notifying device */
5964         wmb();
5965
5966         tp->cur_tx += frags + 1;
5967
5968         RTL_W8(tp, TxPoll, NPQ);
5969
5970         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5971                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5972                  * not miss a ring update when it notices a stopped queue.
5973                  */
5974                 smp_wmb();
5975                 netif_stop_queue(dev);
5976                 /* Sync with rtl_tx:
5977                  * - publish queue status and cur_tx ring index (write barrier)
5978                  * - refresh dirty_tx ring index (read barrier).
5979                  * May the current thread have a pessimistic view of the ring
5980                  * status and forget to wake up queue, a racing rtl_tx thread
5981                  * can't.
5982                  */
5983                 smp_mb();
5984                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5985                         netif_start_queue(dev);
5986         }
5987
5988         return NETDEV_TX_OK;
5989
5990 err_dma_1:
5991         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5992 err_dma_0:
5993         dev_kfree_skb_any(skb);
5994         dev->stats.tx_dropped++;
5995         return NETDEV_TX_OK;
5996
5997 err_stop_0:
5998         netif_stop_queue(dev);
5999         dev->stats.tx_dropped++;
6000         return NETDEV_TX_BUSY;
6001 }
6002
6003 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6004 {
6005         struct rtl8169_private *tp = netdev_priv(dev);
6006         struct pci_dev *pdev = tp->pci_dev;
6007         u16 pci_status, pci_cmd;
6008
6009         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6010         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6011
6012         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6013                   pci_cmd, pci_status);
6014
6015         /*
6016          * The recovery sequence below admits a very elaborated explanation:
6017          * - it seems to work;
6018          * - I did not see what else could be done;
6019          * - it makes iop3xx happy.
6020          *
6021          * Feel free to adjust to your needs.
6022          */
6023         if (pdev->broken_parity_status)
6024                 pci_cmd &= ~PCI_COMMAND_PARITY;
6025         else
6026                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6027
6028         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6029
6030         pci_write_config_word(pdev, PCI_STATUS,
6031                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6032                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6033                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6034
6035         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6036 }
6037
6038 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6039                    int budget)
6040 {
6041         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6042
6043         dirty_tx = tp->dirty_tx;
6044         smp_rmb();
6045         tx_left = tp->cur_tx - dirty_tx;
6046
6047         while (tx_left > 0) {
6048                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6049                 struct ring_info *tx_skb = tp->tx_skb + entry;
6050                 u32 status;
6051
6052                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6053                 if (status & DescOwn)
6054                         break;
6055
6056                 /* This barrier is needed to keep us from reading
6057                  * any other fields out of the Tx descriptor until
6058                  * we know the status of DescOwn
6059                  */
6060                 dma_rmb();
6061
6062                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6063                                      tp->TxDescArray + entry);
6064                 if (status & LastFrag) {
6065                         pkts_compl++;
6066                         bytes_compl += tx_skb->skb->len;
6067                         napi_consume_skb(tx_skb->skb, budget);
6068                         tx_skb->skb = NULL;
6069                 }
6070                 dirty_tx++;
6071                 tx_left--;
6072         }
6073
6074         if (tp->dirty_tx != dirty_tx) {
6075                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6076
6077                 u64_stats_update_begin(&tp->tx_stats.syncp);
6078                 tp->tx_stats.packets += pkts_compl;
6079                 tp->tx_stats.bytes += bytes_compl;
6080                 u64_stats_update_end(&tp->tx_stats.syncp);
6081
6082                 tp->dirty_tx = dirty_tx;
6083                 /* Sync with rtl8169_start_xmit:
6084                  * - publish dirty_tx ring index (write barrier)
6085                  * - refresh cur_tx ring index and queue status (read barrier)
6086                  * May the current thread miss the stopped queue condition,
6087                  * a racing xmit thread can only have a right view of the
6088                  * ring status.
6089                  */
6090                 smp_mb();
6091                 if (netif_queue_stopped(dev) &&
6092                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6093                         netif_wake_queue(dev);
6094                 }
6095                 /*
6096                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6097                  * too close. Let's kick an extra TxPoll request when a burst
6098                  * of start_xmit activity is detected (if it is not detected,
6099                  * it is slow enough). -- FR
6100                  */
6101                 if (tp->cur_tx != dirty_tx)
6102                         RTL_W8(tp, TxPoll, NPQ);
6103         }
6104 }
6105
6106 static inline int rtl8169_fragmented_frame(u32 status)
6107 {
6108         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6109 }
6110
6111 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6112 {
6113         u32 status = opts1 & RxProtoMask;
6114
6115         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6116             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6117                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6118         else
6119                 skb_checksum_none_assert(skb);
6120 }
6121
6122 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6123                                            struct rtl8169_private *tp,
6124                                            int pkt_size,
6125                                            dma_addr_t addr)
6126 {
6127         struct sk_buff *skb;
6128         struct device *d = tp_to_dev(tp);
6129
6130         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6131         prefetch(data);
6132         skb = napi_alloc_skb(&tp->napi, pkt_size);
6133         if (skb)
6134                 skb_copy_to_linear_data(skb, data, pkt_size);
6135         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6136
6137         return skb;
6138 }
6139
6140 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6141 {
6142         unsigned int cur_rx, rx_left;
6143         unsigned int count;
6144
6145         cur_rx = tp->cur_rx;
6146
6147         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6148                 unsigned int entry = cur_rx % NUM_RX_DESC;
6149                 struct RxDesc *desc = tp->RxDescArray + entry;
6150                 u32 status;
6151
6152                 status = le32_to_cpu(desc->opts1);
6153                 if (status & DescOwn)
6154                         break;
6155
6156                 /* This barrier is needed to keep us from reading
6157                  * any other fields out of the Rx descriptor until
6158                  * we know the status of DescOwn
6159                  */
6160                 dma_rmb();
6161
6162                 if (unlikely(status & RxRES)) {
6163                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6164                                    status);
6165                         dev->stats.rx_errors++;
6166                         if (status & (RxRWT | RxRUNT))
6167                                 dev->stats.rx_length_errors++;
6168                         if (status & RxCRC)
6169                                 dev->stats.rx_crc_errors++;
6170                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6171                             dev->features & NETIF_F_RXALL) {
6172                                 goto process_pkt;
6173                         }
6174                 } else {
6175                         struct sk_buff *skb;
6176                         dma_addr_t addr;
6177                         int pkt_size;
6178
6179 process_pkt:
6180                         addr = le64_to_cpu(desc->addr);
6181                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6182                                 pkt_size = (status & 0x00003fff) - 4;
6183                         else
6184                                 pkt_size = status & 0x00003fff;
6185
6186                         /*
6187                          * The driver does not support incoming fragmented
6188                          * frames. They are seen as a symptom of over-mtu
6189                          * sized frames.
6190                          */
6191                         if (unlikely(rtl8169_fragmented_frame(status))) {
6192                                 dev->stats.rx_dropped++;
6193                                 dev->stats.rx_length_errors++;
6194                                 goto release_descriptor;
6195                         }
6196
6197                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6198                                                   tp, pkt_size, addr);
6199                         if (!skb) {
6200                                 dev->stats.rx_dropped++;
6201                                 goto release_descriptor;
6202                         }
6203
6204                         rtl8169_rx_csum(skb, status);
6205                         skb_put(skb, pkt_size);
6206                         skb->protocol = eth_type_trans(skb, dev);
6207
6208                         rtl8169_rx_vlan_tag(desc, skb);
6209
6210                         if (skb->pkt_type == PACKET_MULTICAST)
6211                                 dev->stats.multicast++;
6212
6213                         napi_gro_receive(&tp->napi, skb);
6214
6215                         u64_stats_update_begin(&tp->rx_stats.syncp);
6216                         tp->rx_stats.packets++;
6217                         tp->rx_stats.bytes += pkt_size;
6218                         u64_stats_update_end(&tp->rx_stats.syncp);
6219                 }
6220 release_descriptor:
6221                 desc->opts2 = 0;
6222                 rtl8169_mark_to_asic(desc);
6223         }
6224
6225         count = cur_rx - tp->cur_rx;
6226         tp->cur_rx = cur_rx;
6227
6228         return count;
6229 }
6230
6231 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6232 {
6233         struct rtl8169_private *tp = dev_instance;
6234         u16 status = RTL_R16(tp, IntrStatus);
6235
6236         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6237                 return IRQ_NONE;
6238
6239         if (unlikely(status & SYSErr)) {
6240                 rtl8169_pcierr_interrupt(tp->dev);
6241                 goto out;
6242         }
6243
6244         if (status & LinkChg)
6245                 phy_mac_interrupt(tp->phydev);
6246
6247         if (unlikely(status & RxFIFOOver &&
6248             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6249                 netif_stop_queue(tp->dev);
6250                 /* XXX - Hack alert. See rtl_task(). */
6251                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6252         }
6253
6254         rtl_irq_disable(tp);
6255         napi_schedule_irqoff(&tp->napi);
6256 out:
6257         rtl_ack_events(tp, status);
6258
6259         return IRQ_HANDLED;
6260 }
6261
6262 static void rtl_task(struct work_struct *work)
6263 {
6264         static const struct {
6265                 int bitnr;
6266                 void (*action)(struct rtl8169_private *);
6267         } rtl_work[] = {
6268                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6269         };
6270         struct rtl8169_private *tp =
6271                 container_of(work, struct rtl8169_private, wk.work);
6272         struct net_device *dev = tp->dev;
6273         int i;
6274
6275         rtl_lock_work(tp);
6276
6277         if (!netif_running(dev) ||
6278             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6279                 goto out_unlock;
6280
6281         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6282                 bool pending;
6283
6284                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6285                 if (pending)
6286                         rtl_work[i].action(tp);
6287         }
6288
6289 out_unlock:
6290         rtl_unlock_work(tp);
6291 }
6292
6293 static int rtl8169_poll(struct napi_struct *napi, int budget)
6294 {
6295         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6296         struct net_device *dev = tp->dev;
6297         int work_done;
6298
6299         work_done = rtl_rx(dev, tp, (u32) budget);
6300
6301         rtl_tx(dev, tp, budget);
6302
6303         if (work_done < budget) {
6304                 napi_complete_done(napi, work_done);
6305                 rtl_irq_enable(tp);
6306         }
6307
6308         return work_done;
6309 }
6310
6311 static void rtl8169_rx_missed(struct net_device *dev)
6312 {
6313         struct rtl8169_private *tp = netdev_priv(dev);
6314
6315         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6316                 return;
6317
6318         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6319         RTL_W32(tp, RxMissed, 0);
6320 }
6321
6322 static void r8169_phylink_handler(struct net_device *ndev)
6323 {
6324         struct rtl8169_private *tp = netdev_priv(ndev);
6325
6326         if (netif_carrier_ok(ndev)) {
6327                 rtl_link_chg_patch(tp);
6328                 pm_request_resume(&tp->pci_dev->dev);
6329         } else {
6330                 pm_runtime_idle(&tp->pci_dev->dev);
6331         }
6332
6333         if (net_ratelimit())
6334                 phy_print_status(tp->phydev);
6335 }
6336
6337 static int r8169_phy_connect(struct rtl8169_private *tp)
6338 {
6339         struct phy_device *phydev = tp->phydev;
6340         phy_interface_t phy_mode;
6341         int ret;
6342
6343         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6344                    PHY_INTERFACE_MODE_MII;
6345
6346         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6347                                  phy_mode);
6348         if (ret)
6349                 return ret;
6350
6351         if (tp->supports_gmii)
6352                 phy_remove_link_mode(phydev,
6353                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6354         else
6355                 phy_set_max_speed(phydev, SPEED_100);
6356
6357         phy_support_asym_pause(phydev);
6358
6359         phy_attached_info(phydev);
6360
6361         return 0;
6362 }
6363
6364 static void rtl8169_down(struct net_device *dev)
6365 {
6366         struct rtl8169_private *tp = netdev_priv(dev);
6367
6368         phy_stop(tp->phydev);
6369
6370         napi_disable(&tp->napi);
6371         netif_stop_queue(dev);
6372
6373         rtl8169_hw_reset(tp);
6374         /*
6375          * At this point device interrupts can not be enabled in any function,
6376          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6377          * and napi is disabled (rtl8169_poll).
6378          */
6379         rtl8169_rx_missed(dev);
6380
6381         /* Give a racing hard_start_xmit a few cycles to complete. */
6382         synchronize_rcu();
6383
6384         rtl8169_tx_clear(tp);
6385
6386         rtl8169_rx_clear(tp);
6387
6388         rtl_pll_power_down(tp);
6389 }
6390
6391 static int rtl8169_close(struct net_device *dev)
6392 {
6393         struct rtl8169_private *tp = netdev_priv(dev);
6394         struct pci_dev *pdev = tp->pci_dev;
6395
6396         pm_runtime_get_sync(&pdev->dev);
6397
6398         /* Update counters before going down */
6399         rtl8169_update_counters(tp);
6400
6401         rtl_lock_work(tp);
6402         /* Clear all task flags */
6403         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6404
6405         rtl8169_down(dev);
6406         rtl_unlock_work(tp);
6407
6408         cancel_work_sync(&tp->wk.work);
6409
6410         phy_disconnect(tp->phydev);
6411
6412         pci_free_irq(pdev, 0, tp);
6413
6414         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6415                           tp->RxPhyAddr);
6416         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6417                           tp->TxPhyAddr);
6418         tp->TxDescArray = NULL;
6419         tp->RxDescArray = NULL;
6420
6421         pm_runtime_put_sync(&pdev->dev);
6422
6423         return 0;
6424 }
6425
6426 #ifdef CONFIG_NET_POLL_CONTROLLER
6427 static void rtl8169_netpoll(struct net_device *dev)
6428 {
6429         struct rtl8169_private *tp = netdev_priv(dev);
6430
6431         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6432 }
6433 #endif
6434
6435 static int rtl_open(struct net_device *dev)
6436 {
6437         struct rtl8169_private *tp = netdev_priv(dev);
6438         struct pci_dev *pdev = tp->pci_dev;
6439         int retval = -ENOMEM;
6440
6441         pm_runtime_get_sync(&pdev->dev);
6442
6443         /*
6444          * Rx and Tx descriptors needs 256 bytes alignment.
6445          * dma_alloc_coherent provides more.
6446          */
6447         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6448                                              &tp->TxPhyAddr, GFP_KERNEL);
6449         if (!tp->TxDescArray)
6450                 goto err_pm_runtime_put;
6451
6452         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6453                                              &tp->RxPhyAddr, GFP_KERNEL);
6454         if (!tp->RxDescArray)
6455                 goto err_free_tx_0;
6456
6457         retval = rtl8169_init_ring(tp);
6458         if (retval < 0)
6459                 goto err_free_rx_1;
6460
6461         rtl_request_firmware(tp);
6462
6463         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6464                                  dev->name);
6465         if (retval < 0)
6466                 goto err_release_fw_2;
6467
6468         retval = r8169_phy_connect(tp);
6469         if (retval)
6470                 goto err_free_irq;
6471
6472         rtl_lock_work(tp);
6473
6474         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6475
6476         napi_enable(&tp->napi);
6477
6478         rtl8169_init_phy(dev, tp);
6479
6480         rtl_pll_power_up(tp);
6481
6482         rtl_hw_start(tp);
6483
6484         if (!rtl8169_init_counter_offsets(tp))
6485                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6486
6487         phy_start(tp->phydev);
6488         netif_start_queue(dev);
6489
6490         rtl_unlock_work(tp);
6491
6492         pm_runtime_put_sync(&pdev->dev);
6493 out:
6494         return retval;
6495
6496 err_free_irq:
6497         pci_free_irq(pdev, 0, tp);
6498 err_release_fw_2:
6499         rtl_release_firmware(tp);
6500         rtl8169_rx_clear(tp);
6501 err_free_rx_1:
6502         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6503                           tp->RxPhyAddr);
6504         tp->RxDescArray = NULL;
6505 err_free_tx_0:
6506         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6507                           tp->TxPhyAddr);
6508         tp->TxDescArray = NULL;
6509 err_pm_runtime_put:
6510         pm_runtime_put_noidle(&pdev->dev);
6511         goto out;
6512 }
6513
6514 static void
6515 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6516 {
6517         struct rtl8169_private *tp = netdev_priv(dev);
6518         struct pci_dev *pdev = tp->pci_dev;
6519         struct rtl8169_counters *counters = tp->counters;
6520         unsigned int start;
6521
6522         pm_runtime_get_noresume(&pdev->dev);
6523
6524         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6525                 rtl8169_rx_missed(dev);
6526
6527         do {
6528                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6529                 stats->rx_packets = tp->rx_stats.packets;
6530                 stats->rx_bytes = tp->rx_stats.bytes;
6531         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6532
6533         do {
6534                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6535                 stats->tx_packets = tp->tx_stats.packets;
6536                 stats->tx_bytes = tp->tx_stats.bytes;
6537         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6538
6539         stats->rx_dropped       = dev->stats.rx_dropped;
6540         stats->tx_dropped       = dev->stats.tx_dropped;
6541         stats->rx_length_errors = dev->stats.rx_length_errors;
6542         stats->rx_errors        = dev->stats.rx_errors;
6543         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6544         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6545         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6546         stats->multicast        = dev->stats.multicast;
6547
6548         /*
6549          * Fetch additonal counter values missing in stats collected by driver
6550          * from tally counters.
6551          */
6552         if (pm_runtime_active(&pdev->dev))
6553                 rtl8169_update_counters(tp);
6554
6555         /*
6556          * Subtract values fetched during initalization.
6557          * See rtl8169_init_counter_offsets for a description why we do that.
6558          */
6559         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6560                 le64_to_cpu(tp->tc_offset.tx_errors);
6561         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6562                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6563         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6564                 le16_to_cpu(tp->tc_offset.tx_aborted);
6565
6566         pm_runtime_put_noidle(&pdev->dev);
6567 }
6568
6569 static void rtl8169_net_suspend(struct net_device *dev)
6570 {
6571         struct rtl8169_private *tp = netdev_priv(dev);
6572
6573         if (!netif_running(dev))
6574                 return;
6575
6576         phy_stop(tp->phydev);
6577         netif_device_detach(dev);
6578
6579         rtl_lock_work(tp);
6580         napi_disable(&tp->napi);
6581         /* Clear all task flags */
6582         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6583
6584         rtl_unlock_work(tp);
6585
6586         rtl_pll_power_down(tp);
6587 }
6588
6589 #ifdef CONFIG_PM
6590
6591 static int rtl8169_suspend(struct device *device)
6592 {
6593         struct net_device *dev = dev_get_drvdata(device);
6594         struct rtl8169_private *tp = netdev_priv(dev);
6595
6596         rtl8169_net_suspend(dev);
6597         clk_disable_unprepare(tp->clk);
6598
6599         return 0;
6600 }
6601
6602 static void __rtl8169_resume(struct net_device *dev)
6603 {
6604         struct rtl8169_private *tp = netdev_priv(dev);
6605
6606         netif_device_attach(dev);
6607
6608         rtl_pll_power_up(tp);
6609         rtl8169_init_phy(dev, tp);
6610
6611         phy_start(tp->phydev);
6612
6613         rtl_lock_work(tp);
6614         napi_enable(&tp->napi);
6615         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6616         rtl_reset_work(tp);
6617         rtl_unlock_work(tp);
6618 }
6619
6620 static int rtl8169_resume(struct device *device)
6621 {
6622         struct net_device *dev = dev_get_drvdata(device);
6623         struct rtl8169_private *tp = netdev_priv(dev);
6624
6625         rtl_rar_set(tp, dev->dev_addr);
6626
6627         clk_prepare_enable(tp->clk);
6628
6629         if (netif_running(dev))
6630                 __rtl8169_resume(dev);
6631
6632         return 0;
6633 }
6634
6635 static int rtl8169_runtime_suspend(struct device *device)
6636 {
6637         struct net_device *dev = dev_get_drvdata(device);
6638         struct rtl8169_private *tp = netdev_priv(dev);
6639
6640         if (!tp->TxDescArray)
6641                 return 0;
6642
6643         rtl_lock_work(tp);
6644         __rtl8169_set_wol(tp, WAKE_ANY);
6645         rtl_unlock_work(tp);
6646
6647         rtl8169_net_suspend(dev);
6648
6649         /* Update counters before going runtime suspend */
6650         rtl8169_rx_missed(dev);
6651         rtl8169_update_counters(tp);
6652
6653         return 0;
6654 }
6655
6656 static int rtl8169_runtime_resume(struct device *device)
6657 {
6658         struct net_device *dev = dev_get_drvdata(device);
6659         struct rtl8169_private *tp = netdev_priv(dev);
6660
6661         rtl_rar_set(tp, dev->dev_addr);
6662
6663         if (!tp->TxDescArray)
6664                 return 0;
6665
6666         rtl_lock_work(tp);
6667         __rtl8169_set_wol(tp, tp->saved_wolopts);
6668         rtl_unlock_work(tp);
6669
6670         __rtl8169_resume(dev);
6671
6672         return 0;
6673 }
6674
6675 static int rtl8169_runtime_idle(struct device *device)
6676 {
6677         struct net_device *dev = dev_get_drvdata(device);
6678
6679         if (!netif_running(dev) || !netif_carrier_ok(dev))
6680                 pm_schedule_suspend(device, 10000);
6681
6682         return -EBUSY;
6683 }
6684
6685 static const struct dev_pm_ops rtl8169_pm_ops = {
6686         .suspend                = rtl8169_suspend,
6687         .resume                 = rtl8169_resume,
6688         .freeze                 = rtl8169_suspend,
6689         .thaw                   = rtl8169_resume,
6690         .poweroff               = rtl8169_suspend,
6691         .restore                = rtl8169_resume,
6692         .runtime_suspend        = rtl8169_runtime_suspend,
6693         .runtime_resume         = rtl8169_runtime_resume,
6694         .runtime_idle           = rtl8169_runtime_idle,
6695 };
6696
6697 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6698
6699 #else /* !CONFIG_PM */
6700
6701 #define RTL8169_PM_OPS  NULL
6702
6703 #endif /* !CONFIG_PM */
6704
6705 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6706 {
6707         /* WoL fails with 8168b when the receiver is disabled. */
6708         switch (tp->mac_version) {
6709         case RTL_GIGA_MAC_VER_11:
6710         case RTL_GIGA_MAC_VER_12:
6711         case RTL_GIGA_MAC_VER_17:
6712                 pci_clear_master(tp->pci_dev);
6713
6714                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6715                 /* PCI commit */
6716                 RTL_R8(tp, ChipCmd);
6717                 break;
6718         default:
6719                 break;
6720         }
6721 }
6722
6723 static void rtl_shutdown(struct pci_dev *pdev)
6724 {
6725         struct net_device *dev = pci_get_drvdata(pdev);
6726         struct rtl8169_private *tp = netdev_priv(dev);
6727
6728         rtl8169_net_suspend(dev);
6729
6730         /* Restore original MAC address */
6731         rtl_rar_set(tp, dev->perm_addr);
6732
6733         rtl8169_hw_reset(tp);
6734
6735         if (system_state == SYSTEM_POWER_OFF) {
6736                 if (tp->saved_wolopts) {
6737                         rtl_wol_suspend_quirk(tp);
6738                         rtl_wol_shutdown_quirk(tp);
6739                 }
6740
6741                 pci_wake_from_d3(pdev, true);
6742                 pci_set_power_state(pdev, PCI_D3hot);
6743         }
6744 }
6745
6746 static void rtl_remove_one(struct pci_dev *pdev)
6747 {
6748         struct net_device *dev = pci_get_drvdata(pdev);
6749         struct rtl8169_private *tp = netdev_priv(dev);
6750
6751         if (r8168_check_dash(tp))
6752                 rtl8168_driver_stop(tp);
6753
6754         netif_napi_del(&tp->napi);
6755
6756         unregister_netdev(dev);
6757         mdiobus_unregister(tp->phydev->mdio.bus);
6758
6759         rtl_release_firmware(tp);
6760
6761         if (pci_dev_run_wake(pdev))
6762                 pm_runtime_get_noresume(&pdev->dev);
6763
6764         /* restore original MAC address */
6765         rtl_rar_set(tp, dev->perm_addr);
6766 }
6767
6768 static const struct net_device_ops rtl_netdev_ops = {
6769         .ndo_open               = rtl_open,
6770         .ndo_stop               = rtl8169_close,
6771         .ndo_get_stats64        = rtl8169_get_stats64,
6772         .ndo_start_xmit         = rtl8169_start_xmit,
6773         .ndo_tx_timeout         = rtl8169_tx_timeout,
6774         .ndo_validate_addr      = eth_validate_addr,
6775         .ndo_change_mtu         = rtl8169_change_mtu,
6776         .ndo_fix_features       = rtl8169_fix_features,
6777         .ndo_set_features       = rtl8169_set_features,
6778         .ndo_set_mac_address    = rtl_set_mac_address,
6779         .ndo_do_ioctl           = rtl8169_ioctl,
6780         .ndo_set_rx_mode        = rtl_set_rx_mode,
6781 #ifdef CONFIG_NET_POLL_CONTROLLER
6782         .ndo_poll_controller    = rtl8169_netpoll,
6783 #endif
6784
6785 };
6786
6787 static const struct rtl_cfg_info {
6788         void (*hw_start)(struct rtl8169_private *tp);
6789         u16 irq_mask;
6790         unsigned int has_gmii:1;
6791         const struct rtl_coalesce_info *coalesce_info;
6792 } rtl_cfg_infos [] = {
6793         [RTL_CFG_0] = {
6794                 .hw_start       = rtl_hw_start_8169,
6795                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6796                 .has_gmii       = 1,
6797                 .coalesce_info  = rtl_coalesce_info_8169,
6798         },
6799         [RTL_CFG_1] = {
6800                 .hw_start       = rtl_hw_start_8168,
6801                 .irq_mask       = LinkChg | RxOverflow,
6802                 .has_gmii       = 1,
6803                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6804         },
6805         [RTL_CFG_2] = {
6806                 .hw_start       = rtl_hw_start_8101,
6807                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6808                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6809         }
6810 };
6811
6812 static int rtl_alloc_irq(struct rtl8169_private *tp)
6813 {
6814         unsigned int flags;
6815
6816         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6817                 rtl_unlock_config_regs(tp);
6818                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6819                 rtl_lock_config_regs(tp);
6820                 flags = PCI_IRQ_LEGACY;
6821         } else {
6822                 flags = PCI_IRQ_ALL_TYPES;
6823         }
6824
6825         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6826 }
6827
6828 static void rtl_read_mac_address(struct rtl8169_private *tp,
6829                                  u8 mac_addr[ETH_ALEN])
6830 {
6831         u32 value;
6832
6833         /* Get MAC address */
6834         switch (tp->mac_version) {
6835         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6836         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6837                 value = rtl_eri_read(tp, 0xe0);
6838                 mac_addr[0] = (value >>  0) & 0xff;
6839                 mac_addr[1] = (value >>  8) & 0xff;
6840                 mac_addr[2] = (value >> 16) & 0xff;
6841                 mac_addr[3] = (value >> 24) & 0xff;
6842
6843                 value = rtl_eri_read(tp, 0xe4);
6844                 mac_addr[4] = (value >>  0) & 0xff;
6845                 mac_addr[5] = (value >>  8) & 0xff;
6846                 break;
6847         default:
6848                 break;
6849         }
6850 }
6851
6852 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6853 {
6854         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6855 }
6856
6857 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6858 {
6859         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6860 }
6861
6862 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6863 {
6864         struct rtl8169_private *tp = mii_bus->priv;
6865
6866         if (phyaddr > 0)
6867                 return -ENODEV;
6868
6869         return rtl_readphy(tp, phyreg);
6870 }
6871
6872 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6873                                 int phyreg, u16 val)
6874 {
6875         struct rtl8169_private *tp = mii_bus->priv;
6876
6877         if (phyaddr > 0)
6878                 return -ENODEV;
6879
6880         rtl_writephy(tp, phyreg, val);
6881
6882         return 0;
6883 }
6884
6885 static int r8169_mdio_register(struct rtl8169_private *tp)
6886 {
6887         struct pci_dev *pdev = tp->pci_dev;
6888         struct mii_bus *new_bus;
6889         int ret;
6890
6891         new_bus = devm_mdiobus_alloc(&pdev->dev);
6892         if (!new_bus)
6893                 return -ENOMEM;
6894
6895         new_bus->name = "r8169";
6896         new_bus->priv = tp;
6897         new_bus->parent = &pdev->dev;
6898         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6899         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6900
6901         new_bus->read = r8169_mdio_read_reg;
6902         new_bus->write = r8169_mdio_write_reg;
6903
6904         ret = mdiobus_register(new_bus);
6905         if (ret)
6906                 return ret;
6907
6908         tp->phydev = mdiobus_get_phy(new_bus, 0);
6909         if (!tp->phydev) {
6910                 mdiobus_unregister(new_bus);
6911                 return -ENODEV;
6912         }
6913
6914         /* PHY will be woken up in rtl_open() */
6915         phy_suspend(tp->phydev);
6916
6917         return 0;
6918 }
6919
6920 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6921 {
6922         u32 data;
6923
6924         tp->ocp_base = OCP_STD_PHY_BASE;
6925
6926         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6927
6928         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6929                 return;
6930
6931         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6932                 return;
6933
6934         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6935         msleep(1);
6936         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6937
6938         data = r8168_mac_ocp_read(tp, 0xe8de);
6939         data &= ~(1 << 14);
6940         r8168_mac_ocp_write(tp, 0xe8de, data);
6941
6942         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6943                 return;
6944
6945         data = r8168_mac_ocp_read(tp, 0xe8de);
6946         data |= (1 << 15);
6947         r8168_mac_ocp_write(tp, 0xe8de, data);
6948
6949         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6950 }
6951
6952 static void rtl_hw_initialize(struct rtl8169_private *tp)
6953 {
6954         switch (tp->mac_version) {
6955         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6956                 rtl8168ep_stop_cmac(tp);
6957                 /* fall through */
6958         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6959                 rtl_hw_init_8168g(tp);
6960                 break;
6961         default:
6962                 break;
6963         }
6964 }
6965
6966 static int rtl_jumbo_max(struct rtl8169_private *tp)
6967 {
6968         /* Non-GBit versions don't support jumbo frames */
6969         if (!tp->supports_gmii)
6970                 return JUMBO_1K;
6971
6972         switch (tp->mac_version) {
6973         /* RTL8169 */
6974         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6975                 return JUMBO_7K;
6976         /* RTL8168b */
6977         case RTL_GIGA_MAC_VER_11:
6978         case RTL_GIGA_MAC_VER_12:
6979         case RTL_GIGA_MAC_VER_17:
6980                 return JUMBO_4K;
6981         /* RTL8168c */
6982         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6983                 return JUMBO_6K;
6984         default:
6985                 return JUMBO_9K;
6986         }
6987 }
6988
6989 static void rtl_disable_clk(void *data)
6990 {
6991         clk_disable_unprepare(data);
6992 }
6993
6994 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6995 {
6996         struct device *d = tp_to_dev(tp);
6997         struct clk *clk;
6998         int rc;
6999
7000         clk = devm_clk_get(d, "ether_clk");
7001         if (IS_ERR(clk)) {
7002                 rc = PTR_ERR(clk);
7003                 if (rc == -ENOENT)
7004                         /* clk-core allows NULL (for suspend / resume) */
7005                         rc = 0;
7006                 else if (rc != -EPROBE_DEFER)
7007                         dev_err(d, "failed to get clk: %d\n", rc);
7008         } else {
7009                 tp->clk = clk;
7010                 rc = clk_prepare_enable(clk);
7011                 if (rc)
7012                         dev_err(d, "failed to enable clk: %d\n", rc);
7013                 else
7014                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7015         }
7016
7017         return rc;
7018 }
7019
7020 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7021 {
7022         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7023         /* align to u16 for is_valid_ether_addr() */
7024         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7025         struct rtl8169_private *tp;
7026         struct net_device *dev;
7027         int chipset, region, i;
7028         int jumbo_max, rc;
7029
7030         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7031         if (!dev)
7032                 return -ENOMEM;
7033
7034         SET_NETDEV_DEV(dev, &pdev->dev);
7035         dev->netdev_ops = &rtl_netdev_ops;
7036         tp = netdev_priv(dev);
7037         tp->dev = dev;
7038         tp->pci_dev = pdev;
7039         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7040         tp->supports_gmii = cfg->has_gmii;
7041
7042         /* Get the *optional* external "ether_clk" used on some boards */
7043         rc = rtl_get_ether_clk(tp);
7044         if (rc)
7045                 return rc;
7046
7047         /* Disable ASPM completely as that cause random device stop working
7048          * problems as well as full system hangs for some PCIe devices users.
7049          */
7050         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7051
7052         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7053         rc = pcim_enable_device(pdev);
7054         if (rc < 0) {
7055                 dev_err(&pdev->dev, "enable failure\n");
7056                 return rc;
7057         }
7058
7059         if (pcim_set_mwi(pdev) < 0)
7060                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7061
7062         /* use first MMIO region */
7063         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7064         if (region < 0) {
7065                 dev_err(&pdev->dev, "no MMIO resource found\n");
7066                 return -ENODEV;
7067         }
7068
7069         /* check for weird/broken PCI region reporting */
7070         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7071                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7072                 return -ENODEV;
7073         }
7074
7075         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7076         if (rc < 0) {
7077                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7078                 return rc;
7079         }
7080
7081         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7082
7083         /* Identify chip attached to board */
7084         rtl8169_get_mac_version(tp);
7085         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7086                 return -ENODEV;
7087
7088         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7089
7090         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7091             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7092                 dev->features |= NETIF_F_HIGHDMA;
7093         } else {
7094                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7095                 if (rc < 0) {
7096                         dev_err(&pdev->dev, "DMA configuration failed\n");
7097                         return rc;
7098                 }
7099         }
7100
7101         rtl_init_rxcfg(tp);
7102
7103         rtl8169_irq_mask_and_ack(tp);
7104
7105         rtl_hw_initialize(tp);
7106
7107         rtl_hw_reset(tp);
7108
7109         pci_set_master(pdev);
7110
7111         chipset = tp->mac_version;
7112
7113         rc = rtl_alloc_irq(tp);
7114         if (rc < 0) {
7115                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7116                 return rc;
7117         }
7118
7119         mutex_init(&tp->wk.mutex);
7120         INIT_WORK(&tp->wk.work, rtl_task);
7121         u64_stats_init(&tp->rx_stats.syncp);
7122         u64_stats_init(&tp->tx_stats.syncp);
7123
7124         /* get MAC address */
7125         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7126         if (rc)
7127                 rtl_read_mac_address(tp, mac_addr);
7128
7129         if (is_valid_ether_addr(mac_addr))
7130                 rtl_rar_set(tp, mac_addr);
7131
7132         for (i = 0; i < ETH_ALEN; i++)
7133                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7134
7135         dev->ethtool_ops = &rtl8169_ethtool_ops;
7136
7137         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7138
7139         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7140          * properly for all devices */
7141         dev->features |= NETIF_F_RXCSUM |
7142                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7143
7144         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7145                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7146                 NETIF_F_HW_VLAN_CTAG_RX;
7147         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7148                 NETIF_F_HIGHDMA;
7149         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7150
7151         tp->cp_cmd |= RxChkSum | RxVlan;
7152
7153         /*
7154          * Pretend we are using VLANs; This bypasses a nasty bug where
7155          * Interrupts stop flowing on high load on 8110SCd controllers.
7156          */
7157         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7158                 /* Disallow toggling */
7159                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7160
7161         if (rtl_chip_supports_csum_v2(tp))
7162                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7163
7164         dev->hw_features |= NETIF_F_RXALL;
7165         dev->hw_features |= NETIF_F_RXFCS;
7166
7167         /* MTU range: 60 - hw-specific max */
7168         dev->min_mtu = ETH_ZLEN;
7169         jumbo_max = rtl_jumbo_max(tp);
7170         dev->max_mtu = jumbo_max;
7171
7172         tp->hw_start = cfg->hw_start;
7173         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7174         tp->coalesce_info = cfg->coalesce_info;
7175
7176         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7177
7178         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7179                                             &tp->counters_phys_addr,
7180                                             GFP_KERNEL);
7181         if (!tp->counters)
7182                 return -ENOMEM;
7183
7184         pci_set_drvdata(pdev, dev);
7185
7186         rc = r8169_mdio_register(tp);
7187         if (rc)
7188                 return rc;
7189
7190         /* chip gets powered up in rtl_open() */
7191         rtl_pll_power_down(tp);
7192
7193         rc = register_netdev(dev);
7194         if (rc)
7195                 goto err_mdio_unregister;
7196
7197         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7198                    rtl_chip_infos[chipset].name, dev->dev_addr,
7199                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7200                    pci_irq_vector(pdev, 0));
7201
7202         if (jumbo_max > JUMBO_1K)
7203                 netif_info(tp, probe, dev,
7204                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7205                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7206                            "ok" : "ko");
7207
7208         if (r8168_check_dash(tp))
7209                 rtl8168_driver_start(tp);
7210
7211         if (pci_dev_run_wake(pdev))
7212                 pm_runtime_put_sync(&pdev->dev);
7213
7214         return 0;
7215
7216 err_mdio_unregister:
7217         mdiobus_unregister(tp->phydev->mdio.bus);
7218         return rc;
7219 }
7220
7221 static struct pci_driver rtl8169_pci_driver = {
7222         .name           = MODULENAME,
7223         .id_table       = rtl8169_pci_tbl,
7224         .probe          = rtl_init_one,
7225         .remove         = rtl_remove_one,
7226         .shutdown       = rtl_shutdown,
7227         .driver.pm      = RTL8169_PM_OPS,
7228 };
7229
7230 module_pci_driver(rtl8169_pci_driver);