drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define MAX_READ_REQUEST_SHIFT  12
  88 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  89 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  90
  91 #define R8169_REGS_SIZE         256
  92 #define R8169_NAPI_WEIGHT       64
  93 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  94 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  95 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  96 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  97
  98 #define RTL8169_TX_TIMEOUT      (6*HZ)
  99 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 100
 101 /* write/read MMIO register */
 102 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 103 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 104 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 105 #define RTL_R8(reg)             readb (ioaddr + (reg))
 106 #define RTL_R16(reg)            readw (ioaddr + (reg))
 107 #define RTL_R32(reg)            readl (ioaddr + (reg))
 108
 109 enum mac_version {
 110         RTL_GIGA_MAC_VER_01 = 0,
 111         RTL_GIGA_MAC_VER_02,
 112         RTL_GIGA_MAC_VER_03,
 113         RTL_GIGA_MAC_VER_04,
 114         RTL_GIGA_MAC_VER_05,
 115         RTL_GIGA_MAC_VER_06,
 116         RTL_GIGA_MAC_VER_07,
 117         RTL_GIGA_MAC_VER_08,
 118         RTL_GIGA_MAC_VER_09,
 119         RTL_GIGA_MAC_VER_10,
 120         RTL_GIGA_MAC_VER_11,
 121         RTL_GIGA_MAC_VER_12,
 122         RTL_GIGA_MAC_VER_13,
 123         RTL_GIGA_MAC_VER_14,
 124         RTL_GIGA_MAC_VER_15,
 125         RTL_GIGA_MAC_VER_16,
 126         RTL_GIGA_MAC_VER_17,
 127         RTL_GIGA_MAC_VER_18,
 128         RTL_GIGA_MAC_VER_19,
 129         RTL_GIGA_MAC_VER_20,
 130         RTL_GIGA_MAC_VER_21,
 131         RTL_GIGA_MAC_VER_22,
 132         RTL_GIGA_MAC_VER_23,
 133         RTL_GIGA_MAC_VER_24,
 134         RTL_GIGA_MAC_VER_25,
 135         RTL_GIGA_MAC_VER_26,
 136         RTL_GIGA_MAC_VER_27,
 137         RTL_GIGA_MAC_VER_28,
 138         RTL_GIGA_MAC_VER_29,
 139         RTL_GIGA_MAC_VER_30,
 140         RTL_GIGA_MAC_VER_31,
 141         RTL_GIGA_MAC_VER_32,
 142         RTL_GIGA_MAC_VER_33,
 143         RTL_GIGA_MAC_VER_34,
 144         RTL_GIGA_MAC_VER_35,
 145         RTL_GIGA_MAC_VER_36,
 146         RTL_GIGA_MAC_VER_37,
 147         RTL_GIGA_MAC_VER_38,
 148         RTL_GIGA_MAC_VER_39,
 149         RTL_GIGA_MAC_VER_40,
 150         RTL_GIGA_MAC_VER_41,
 151         RTL_GIGA_MAC_VER_42,
 152         RTL_GIGA_MAC_VER_43,
 153         RTL_GIGA_MAC_VER_44,
 154         RTL_GIGA_MAC_VER_45,
 155         RTL_GIGA_MAC_VER_46,
 156         RTL_GIGA_MAC_VER_47,
 157         RTL_GIGA_MAC_VER_48,
 158         RTL_GIGA_MAC_VER_49,
 159         RTL_GIGA_MAC_VER_50,
 160         RTL_GIGA_MAC_VER_51,
 161         RTL_GIGA_MAC_NONE   = 0xff,
 162 };
 163
 164 enum rtl_tx_desc_version {
 165         RTL_TD_0        = 0,
 166         RTL_TD_1        = 1,
 167 };
 168
 169 #define JUMBO_1K        ETH_DATA_LEN
 170 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 171 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 172 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 173 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 174
 175 #define _R(NAME,TD,FW,SZ,B) {   \
 176         .name = NAME,           \
 177         .txd_version = TD,      \
 178         .fw_name = FW,          \
 179         .jumbo_max = SZ,        \
 180         .jumbo_tx_csum = B      \
 181 }
 182
 183 static const struct {
 184         const char *name;
 185         enum rtl_tx_desc_version txd_version;
 186         const char *fw_name;
 187         u16 jumbo_max;
 188         bool jumbo_tx_csum;
 189 } rtl_chip_infos[] = {
 190         /* PCI devices. */
 191         [RTL_GIGA_MAC_VER_01] =
 192                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 193         [RTL_GIGA_MAC_VER_02] =
 194                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 195         [RTL_GIGA_MAC_VER_03] =
 196                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 197         [RTL_GIGA_MAC_VER_04] =
 198                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 199         [RTL_GIGA_MAC_VER_05] =
 200                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 201         [RTL_GIGA_MAC_VER_06] =
 202                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 203         /* PCI-E devices. */
 204         [RTL_GIGA_MAC_VER_07] =
 205                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 206         [RTL_GIGA_MAC_VER_08] =
 207                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 208         [RTL_GIGA_MAC_VER_09] =
 209                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 210         [RTL_GIGA_MAC_VER_10] =
 211                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 212         [RTL_GIGA_MAC_VER_11] =
 213                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 214         [RTL_GIGA_MAC_VER_12] =
 215                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 216         [RTL_GIGA_MAC_VER_13] =
 217                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 218         [RTL_GIGA_MAC_VER_14] =
 219                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 220         [RTL_GIGA_MAC_VER_15] =
 221                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 222         [RTL_GIGA_MAC_VER_16] =
 223                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 224         [RTL_GIGA_MAC_VER_17] =
 225                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 226         [RTL_GIGA_MAC_VER_18] =
 227                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 228         [RTL_GIGA_MAC_VER_19] =
 229                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 230         [RTL_GIGA_MAC_VER_20] =
 231                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 232         [RTL_GIGA_MAC_VER_21] =
 233                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 234         [RTL_GIGA_MAC_VER_22] =
 235                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 236         [RTL_GIGA_MAC_VER_23] =
 237                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 238         [RTL_GIGA_MAC_VER_24] =
 239                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 240         [RTL_GIGA_MAC_VER_25] =
 241                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_26] =
 244                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_27] =
 247                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 248         [RTL_GIGA_MAC_VER_28] =
 249                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 250         [RTL_GIGA_MAC_VER_29] =
 251                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 252                                                         JUMBO_1K, true),
 253         [RTL_GIGA_MAC_VER_30] =
 254                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 255                                                         JUMBO_1K, true),
 256         [RTL_GIGA_MAC_VER_31] =
 257                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 258         [RTL_GIGA_MAC_VER_32] =
 259                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 260                                                         JUMBO_9K, false),
 261         [RTL_GIGA_MAC_VER_33] =
 262                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 263                                                         JUMBO_9K, false),
 264         [RTL_GIGA_MAC_VER_34] =
 265                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 266                                                         JUMBO_9K, false),
 267         [RTL_GIGA_MAC_VER_35] =
 268                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 269                                                         JUMBO_9K, false),
 270         [RTL_GIGA_MAC_VER_36] =
 271                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 272                                                         JUMBO_9K, false),
 273         [RTL_GIGA_MAC_VER_37] =
 274                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 275                                                         JUMBO_1K, true),
 276         [RTL_GIGA_MAC_VER_38] =
 277                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 278                                                         JUMBO_9K, false),
 279         [RTL_GIGA_MAC_VER_39] =
 280                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 281                                                         JUMBO_1K, true),
 282         [RTL_GIGA_MAC_VER_40] =
 283                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 284                                                         JUMBO_9K, false),
 285         [RTL_GIGA_MAC_VER_41] =
 286                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 287         [RTL_GIGA_MAC_VER_42] =
 288                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 289                                                         JUMBO_9K, false),
 290         [RTL_GIGA_MAC_VER_43] =
 291                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 292                                                         JUMBO_1K, true),
 293         [RTL_GIGA_MAC_VER_44] =
 294                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 295                                                         JUMBO_9K, false),
 296         [RTL_GIGA_MAC_VER_45] =
 297                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 298                                                         JUMBO_9K, false),
 299         [RTL_GIGA_MAC_VER_46] =
 300                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 301                                                         JUMBO_9K, false),
 302         [RTL_GIGA_MAC_VER_47] =
 303                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 304                                                         JUMBO_1K, false),
 305         [RTL_GIGA_MAC_VER_48] =
 306                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 307                                                         JUMBO_1K, false),
 308         [RTL_GIGA_MAC_VER_49] =
 309                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 310                                                         JUMBO_9K, false),
 311         [RTL_GIGA_MAC_VER_50] =
 312                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 313                                                         JUMBO_9K, false),
 314         [RTL_GIGA_MAC_VER_51] =
 315                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 316                                                         JUMBO_9K, false),
 317 };
 318 #undef _R
 319
 320 enum cfg_version {
 321         RTL_CFG_0 = 0x00,
 322         RTL_CFG_1,
 323         RTL_CFG_2
 324 };
 325
 326 static const struct pci_device_id rtl8169_pci_tbl[] = {
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 332         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 333         { PCI_VENDOR_ID_DLINK,                  0x4300,
 334                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 338         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 339         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 340                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 341         { 0x0001,                               0x8168,
 342                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 343         {0,},
 344 };
 345
 346 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 347
 348 static int rx_buf_sz = 16383;
 349 static int use_dac = -1;
 350 static struct {
 351         u32 msg_enable;
 352 } debug = { -1 };
 353
 354 enum rtl_registers {
 355         MAC0            = 0,    /* Ethernet hardware address. */
 356         MAC4            = 4,
 357         MAR0            = 8,    /* Multicast filter. */
 358         CounterAddrLow          = 0x10,
 359         CounterAddrHigh         = 0x14,
 360         TxDescStartAddrLow      = 0x20,
 361         TxDescStartAddrHigh     = 0x24,
 362         TxHDescStartAddrLow     = 0x28,
 363         TxHDescStartAddrHigh    = 0x2c,
 364         FLASH           = 0x30,
 365         ERSR            = 0x36,
 366         ChipCmd         = 0x37,
 367         TxPoll          = 0x38,
 368         IntrMask        = 0x3c,
 369         IntrStatus      = 0x3e,
 370
 371         TxConfig        = 0x40,
 372 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 373 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 374
 375         RxConfig        = 0x44,
 376 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 377 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 378 #define RXCFG_FIFO_SHIFT                13
 379                                         /* No threshold before first PCI xfer */
 380 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 381 #define RX_EARLY_OFF                    (1 << 11)
 382 #define RXCFG_DMA_SHIFT                 8
 383                                         /* Unlimited maximum PCI burst. */
 384 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 385
 386         RxMissed        = 0x4c,
 387         Cfg9346         = 0x50,
 388         Config0         = 0x51,
 389         Config1         = 0x52,
 390         Config2         = 0x53,
 391 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 392
 393         Config3         = 0x54,
 394         Config4         = 0x55,
 395         Config5         = 0x56,
 396         MultiIntr       = 0x5c,
 397         PHYAR           = 0x60,
 398         PHYstatus       = 0x6c,
 399         RxMaxSize       = 0xda,
 400         CPlusCmd        = 0xe0,
 401         IntrMitigate    = 0xe2,
 402
 403 #define RTL_COALESCE_MASK       0x0f
 404 #define RTL_COALESCE_SHIFT      4
 405 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 406 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 407
 408         RxDescAddrLow   = 0xe4,
 409         RxDescAddrHigh  = 0xe8,
 410         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 411
 412 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 413
 414         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 415
 416 #define TxPacketMax     (8064 >> 7)
 417 #define EarlySize       0x27
 418
 419         FuncEvent       = 0xf0,
 420         FuncEventMask   = 0xf4,
 421         FuncPresetState = 0xf8,
 422         IBCR0           = 0xf8,
 423         IBCR2           = 0xf9,
 424         IBIMR0          = 0xfa,
 425         IBISR0          = 0xfb,
 426         FuncForceEvent  = 0xfc,
 427 };
 428
 429 enum rtl8110_registers {
 430         TBICSR                  = 0x64,
 431         TBI_ANAR                = 0x68,
 432         TBI_LPAR                = 0x6a,
 433 };
 434
 435 enum rtl8168_8101_registers {
 436         CSIDR                   = 0x64,
 437         CSIAR                   = 0x68,
 438 #define CSIAR_FLAG                      0x80000000
 439 #define CSIAR_WRITE_CMD                 0x80000000
 440 #define CSIAR_BYTE_ENABLE               0x0f
 441 #define CSIAR_BYTE_ENABLE_SHIFT         12
 442 #define CSIAR_ADDR_MASK                 0x0fff
 443 #define CSIAR_FUNC_CARD                 0x00000000
 444 #define CSIAR_FUNC_SDIO                 0x00010000
 445 #define CSIAR_FUNC_NIC                  0x00020000
 446 #define CSIAR_FUNC_NIC2                 0x00010000
 447         PMCH                    = 0x6f,
 448         EPHYAR                  = 0x80,
 449 #define EPHYAR_FLAG                     0x80000000
 450 #define EPHYAR_WRITE_CMD                0x80000000
 451 #define EPHYAR_REG_MASK                 0x1f
 452 #define EPHYAR_REG_SHIFT                16
 453 #define EPHYAR_DATA_MASK                0xffff
 454         DLLPR                   = 0xd0,
 455 #define PFM_EN                          (1 << 6)
 456 #define TX_10M_PS_EN                    (1 << 7)
 457         DBG_REG                 = 0xd1,
 458 #define FIX_NAK_1                       (1 << 4)
 459 #define FIX_NAK_2                       (1 << 3)
 460         TWSI                    = 0xd2,
 461         MCU                     = 0xd3,
 462 #define NOW_IS_OOB                      (1 << 7)
 463 #define TX_EMPTY                        (1 << 5)
 464 #define RX_EMPTY                        (1 << 4)
 465 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 466 #define EN_NDP                          (1 << 3)
 467 #define EN_OOB_RESET                    (1 << 2)
 468 #define LINK_LIST_RDY                   (1 << 1)
 469         EFUSEAR                 = 0xdc,
 470 #define EFUSEAR_FLAG                    0x80000000
 471 #define EFUSEAR_WRITE_CMD               0x80000000
 472 #define EFUSEAR_READ_CMD                0x00000000
 473 #define EFUSEAR_REG_MASK                0x03ff
 474 #define EFUSEAR_REG_SHIFT               8
 475 #define EFUSEAR_DATA_MASK               0xff
 476         MISC_1                  = 0xf2,
 477 #define PFM_D3COLD_EN                   (1 << 6)
 478 };
 479
 480 enum rtl8168_registers {
 481         LED_FREQ                = 0x1a,
 482         EEE_LED                 = 0x1b,
 483         ERIDR                   = 0x70,
 484         ERIAR                   = 0x74,
 485 #define ERIAR_FLAG                      0x80000000
 486 #define ERIAR_WRITE_CMD                 0x80000000
 487 #define ERIAR_READ_CMD                  0x00000000
 488 #define ERIAR_ADDR_BYTE_ALIGN           4
 489 #define ERIAR_TYPE_SHIFT                16
 490 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 491 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 492 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 493 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 494 #define ERIAR_MASK_SHIFT                12
 495 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 496 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 497 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 498 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 499 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 500         EPHY_RXER_NUM           = 0x7c,
 501         OCPDR                   = 0xb0, /* OCP GPHY access */
 502 #define OCPDR_WRITE_CMD                 0x80000000
 503 #define OCPDR_READ_CMD                  0x00000000
 504 #define OCPDR_REG_MASK                  0x7f
 505 #define OCPDR_GPHY_REG_SHIFT            16
 506 #define OCPDR_DATA_MASK                 0xffff
 507         OCPAR                   = 0xb4,
 508 #define OCPAR_FLAG                      0x80000000
 509 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 510 #define OCPAR_GPHY_READ_CMD             0x0000f060
 511         GPHY_OCP                = 0xb8,
 512         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 513         MISC                    = 0xf0, /* 8168e only. */
 514 #define TXPLA_RST                       (1 << 29)
 515 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 516 #define PWM_EN                          (1 << 22)
 517 #define RXDV_GATED_EN                   (1 << 19)
 518 #define EARLY_TALLY_EN                  (1 << 16)
 519 };
 520
 521 enum rtl_register_content {
 522         /* InterruptStatusBits */
 523         SYSErr          = 0x8000,
 524         PCSTimeout      = 0x4000,
 525         SWInt           = 0x0100,
 526         TxDescUnavail   = 0x0080,
 527         RxFIFOOver      = 0x0040,
 528         LinkChg         = 0x0020,
 529         RxOverflow      = 0x0010,
 530         TxErr           = 0x0008,
 531         TxOK            = 0x0004,
 532         RxErr           = 0x0002,
 533         RxOK            = 0x0001,
 534
 535         /* RxStatusDesc */
 536         RxBOVF  = (1 << 24),
 537         RxFOVF  = (1 << 23),
 538         RxRWT   = (1 << 22),
 539         RxRES   = (1 << 21),
 540         RxRUNT  = (1 << 20),
 541         RxCRC   = (1 << 19),
 542
 543         /* ChipCmdBits */
 544         StopReq         = 0x80,
 545         CmdReset        = 0x10,
 546         CmdRxEnb        = 0x08,
 547         CmdTxEnb        = 0x04,
 548         RxBufEmpty      = 0x01,
 549
 550         /* TXPoll register p.5 */
 551         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 552         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 553         FSWInt          = 0x01,         /* Forced software interrupt */
 554
 555         /* Cfg9346Bits */
 556         Cfg9346_Lock    = 0x00,
 557         Cfg9346_Unlock  = 0xc0,
 558
 559         /* rx_mode_bits */
 560         AcceptErr       = 0x20,
 561         AcceptRunt      = 0x10,
 562         AcceptBroadcast = 0x08,
 563         AcceptMulticast = 0x04,
 564         AcceptMyPhys    = 0x02,
 565         AcceptAllPhys   = 0x01,
 566 #define RX_CONFIG_ACCEPT_MASK           0x3f
 567
 568         /* TxConfigBits */
 569         TxInterFrameGapShift = 24,
 570         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 571
 572         /* Config1 register p.24 */
 573         LEDS1           = (1 << 7),
 574         LEDS0           = (1 << 6),
 575         Speed_down      = (1 << 4),
 576         MEMMAP          = (1 << 3),
 577         IOMAP           = (1 << 2),
 578         VPD             = (1 << 1),
 579         PMEnable        = (1 << 0),     /* Power Management Enable */
 580
 581         /* Config2 register p. 25 */
 582         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 583         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 584         PCI_Clock_66MHz = 0x01,
 585         PCI_Clock_33MHz = 0x00,
 586
 587         /* Config3 register p.25 */
 588         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 589         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 590         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 591         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 592         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 593
 594         /* Config4 register */
 595         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 596
 597         /* Config5 register p.27 */
 598         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 599         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 600         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 601         Spi_en          = (1 << 3),
 602         LanWake         = (1 << 1),     /* LanWake enable/disable */
 603         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 604         ASPM_en         = (1 << 0),     /* ASPM enable */
 605
 606         /* TBICSR p.28 */
 607         TBIReset        = 0x80000000,
 608         TBILoopback     = 0x40000000,
 609         TBINwEnable     = 0x20000000,
 610         TBINwRestart    = 0x10000000,
 611         TBILinkOk       = 0x02000000,
 612         TBINwComplete   = 0x01000000,
 613
 614         /* CPlusCmd p.31 */
 615         EnableBist      = (1 << 15),    // 8168 8101
 616         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 617         Normal_mode     = (1 << 13),    // unused
 618         Force_half_dup  = (1 << 12),    // 8168 8101
 619         Force_rxflow_en = (1 << 11),    // 8168 8101
 620         Force_txflow_en = (1 << 10),    // 8168 8101
 621         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 622         ASF             = (1 << 8),     // 8168 8101
 623         PktCntrDisable  = (1 << 7),     // 8168 8101
 624         Mac_dbgo_sel    = 0x001c,       // 8168
 625         RxVlan          = (1 << 6),
 626         RxChkSum        = (1 << 5),
 627         PCIDAC          = (1 << 4),
 628         PCIMulRW        = (1 << 3),
 629         INTT_0          = 0x0000,       // 8168
 630         INTT_1          = 0x0001,       // 8168
 631         INTT_2          = 0x0002,       // 8168
 632         INTT_3          = 0x0003,       // 8168
 633
 634         /* rtl8169_PHYstatus */
 635         TBI_Enable      = 0x80,
 636         TxFlowCtrl      = 0x40,
 637         RxFlowCtrl      = 0x20,
 638         _1000bpsF       = 0x10,
 639         _100bps         = 0x08,
 640         _10bps          = 0x04,
 641         LinkStatus      = 0x02,
 642         FullDup         = 0x01,
 643
 644         /* _TBICSRBit */
 645         TBILinkOK       = 0x02000000,
 646
 647         /* ResetCounterCommand */
 648         CounterReset    = 0x1,
 649
 650         /* DumpCounterCommand */
 651         CounterDump     = 0x8,
 652
 653         /* magic enable v2 */
 654         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 655 };
 656
 657 enum rtl_desc_bit {
 658         /* First doubleword. */
 659         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 660         RingEnd         = (1 << 30), /* End of descriptor ring */
 661         FirstFrag       = (1 << 29), /* First segment of a packet */
 662         LastFrag        = (1 << 28), /* Final segment of a packet */
 663 };
 664
 665 /* Generic case. */
 666 enum rtl_tx_desc_bit {
 667         /* First doubleword. */
 668         TD_LSO          = (1 << 27),            /* Large Send Offload */
 669 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 670
 671         /* Second doubleword. */
 672         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 673 };
 674
 675 /* 8169, 8168b and 810x except 8102e. */
 676 enum rtl_tx_desc_bit_0 {
 677         /* First doubleword. */
 678 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 679         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 680         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 681         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 682 };
 683
 684 /* 8102e, 8168c and beyond. */
 685 enum rtl_tx_desc_bit_1 {
 686         /* First doubleword. */
 687         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 688         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 689 #define GTTCPHO_SHIFT                   18
 690 #define GTTCPHO_MAX                     0x7fU
 691
 692         /* Second doubleword. */
 693 #define TCPHO_SHIFT                     18
 694 #define TCPHO_MAX                       0x3ffU
 695 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 696         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 697         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 698         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 699         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 700 };
 701
 702 enum rtl_rx_desc_bit {
 703         /* Rx private */
 704         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 705         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 706
 707 #define RxProtoUDP      (PID1)
 708 #define RxProtoTCP      (PID0)
 709 #define RxProtoIP       (PID1 | PID0)
 710 #define RxProtoMask     RxProtoIP
 711
 712         IPFail          = (1 << 16), /* IP checksum failed */
 713         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 714         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 715         RxVlanTag       = (1 << 16), /* VLAN tag available */
 716 };
 717
 718 #define RsvdMask        0x3fffc000
 719
 720 struct TxDesc {
 721         __le32 opts1;
 722         __le32 opts2;
 723         __le64 addr;
 724 };
 725
 726 struct RxDesc {
 727         __le32 opts1;
 728         __le32 opts2;
 729         __le64 addr;
 730 };
 731
 732 struct ring_info {
 733         struct sk_buff  *skb;
 734         u32             len;
 735         u8              __pad[sizeof(void *) - sizeof(u32)];
 736 };
 737
 738 enum features {
 739         RTL_FEATURE_WOL         = (1 << 0),
 740         RTL_FEATURE_MSI         = (1 << 1),
 741         RTL_FEATURE_GMII        = (1 << 2),
 742 };
 743
 744 struct rtl8169_counters {
 745         __le64  tx_packets;
 746         __le64  rx_packets;
 747         __le64  tx_errors;
 748         __le32  rx_errors;
 749         __le16  rx_missed;
 750         __le16  align_errors;
 751         __le32  tx_one_collision;
 752         __le32  tx_multi_collision;
 753         __le64  rx_unicast;
 754         __le64  rx_broadcast;
 755         __le32  rx_multicast;
 756         __le16  tx_aborted;
 757         __le16  tx_underun;
 758 };
 759
 760 struct rtl8169_tc_offsets {
 761         bool    inited;
 762         __le64  tx_errors;
 763         __le32  tx_multi_collision;
 764         __le16  tx_aborted;
 765 };
 766
 767 enum rtl_flag {
 768         RTL_FLAG_TASK_ENABLED,
 769         RTL_FLAG_TASK_SLOW_PENDING,
 770         RTL_FLAG_TASK_RESET_PENDING,
 771         RTL_FLAG_TASK_PHY_PENDING,
 772         RTL_FLAG_MAX
 773 };
 774
 775 struct rtl8169_stats {
 776         u64                     packets;
 777         u64                     bytes;
 778         struct u64_stats_sync   syncp;
 779 };
 780
 781 struct rtl8169_private {
 782         void __iomem *mmio_addr;        /* memory map physical address */
 783         struct pci_dev *pci_dev;
 784         struct net_device *dev;
 785         struct napi_struct napi;
 786         u32 msg_enable;
 787         u16 txd_version;
 788         u16 mac_version;
 789         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 790         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 791         u32 dirty_tx;
 792         struct rtl8169_stats rx_stats;
 793         struct rtl8169_stats tx_stats;
 794         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 795         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 796         dma_addr_t TxPhyAddr;
 797         dma_addr_t RxPhyAddr;
 798         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 799         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 800         struct timer_list timer;
 801         u16 cp_cmd;
 802
 803         u16 event_slow;
 804         const struct rtl_coalesce_info *coalesce_info;
 805
 806         struct mdio_ops {
 807                 void (*write)(struct rtl8169_private *, int, int);
 808                 int (*read)(struct rtl8169_private *, int);
 809         } mdio_ops;
 810
 811         struct pll_power_ops {
 812                 void (*down)(struct rtl8169_private *);
 813                 void (*up)(struct rtl8169_private *);
 814         } pll_power_ops;
 815
 816         struct jumbo_ops {
 817                 void (*enable)(struct rtl8169_private *);
 818                 void (*disable)(struct rtl8169_private *);
 819         } jumbo_ops;
 820
 821         struct csi_ops {
 822                 void (*write)(struct rtl8169_private *, int, int);
 823                 u32 (*read)(struct rtl8169_private *, int);
 824         } csi_ops;
 825
 826         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 827         int (*get_link_ksettings)(struct net_device *,
 828                                   struct ethtool_link_ksettings *);
 829         void (*phy_reset_enable)(struct rtl8169_private *tp);
 830         void (*hw_start)(struct net_device *);
 831         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 832         unsigned int (*link_ok)(void __iomem *);
 833         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 834         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 835
 836         struct {
 837                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 838                 struct mutex mutex;
 839                 struct work_struct work;
 840         } wk;
 841
 842         unsigned features;
 843
 844         struct mii_if_info mii;
 845         dma_addr_t counters_phys_addr;
 846         struct rtl8169_counters *counters;
 847         struct rtl8169_tc_offsets tc_offset;
 848         u32 saved_wolopts;
 849         u32 opts1_mask;
 850
 851         struct rtl_fw {
 852                 const struct firmware *fw;
 853
 854 #define RTL_VER_SIZE            32
 855
 856                 char version[RTL_VER_SIZE];
 857
 858                 struct rtl_fw_phy_action {
 859                         __le32 *code;
 860                         size_t size;
 861                 } phy_action;
 862         } *rtl_fw;
 863 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 864
 865         u32 ocp_base;
 866 };
 867
 868 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 869 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 870 module_param(use_dac, int, 0);
 871 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 872 module_param_named(debug, debug.msg_enable, int, 0);
 873 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 874 MODULE_LICENSE("GPL");
 875 MODULE_VERSION(RTL8169_VERSION);
 876 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 877 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 878 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 879 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 880 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 881 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 882 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 883 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 884 MODULE_FIRMWARE(FIRMWARE_8402_1);
 885 MODULE_FIRMWARE(FIRMWARE_8411_1);
 886 MODULE_FIRMWARE(FIRMWARE_8411_2);
 887 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 888 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 889 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 890 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 891 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 892 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 893 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 894 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 895
 896 static void rtl_lock_work(struct rtl8169_private *tp)
 897 {
 898         mutex_lock(&tp->wk.mutex);
 899 }
 900
 901 static void rtl_unlock_work(struct rtl8169_private *tp)
 902 {
 903         mutex_unlock(&tp->wk.mutex);
 904 }
 905
 906 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 907 {
 908         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
 909                                            PCI_EXP_DEVCTL_READRQ, force);
 910 }
 911
 912 struct rtl_cond {
 913         bool (*check)(struct rtl8169_private *);
 914         const char *msg;
 915 };
 916
 917 static void rtl_udelay(unsigned int d)
 918 {
 919         udelay(d);
 920 }
 921
 922 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 923                           void (*delay)(unsigned int), unsigned int d, int n,
 924                           bool high)
 925 {
 926         int i;
 927
 928         for (i = 0; i < n; i++) {
 929                 delay(d);
 930                 if (c->check(tp) == high)
 931                         return true;
 932         }
 933         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 934                   c->msg, !high, n, d);
 935         return false;
 936 }
 937
 938 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 939                                       const struct rtl_cond *c,
 940                                       unsigned int d, int n)
 941 {
 942         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 943 }
 944
 945 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 946                                      const struct rtl_cond *c,
 947                                      unsigned int d, int n)
 948 {
 949         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 950 }
 951
 952 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 953                                       const struct rtl_cond *c,
 954                                       unsigned int d, int n)
 955 {
 956         return rtl_loop_wait(tp, c, msleep, d, n, true);
 957 }
 958
 959 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 960                                      const struct rtl_cond *c,
 961                                      unsigned int d, int n)
 962 {
 963         return rtl_loop_wait(tp, c, msleep, d, n, false);
 964 }
 965
 966 #define DECLARE_RTL_COND(name)                          \
 967 static bool name ## _check(struct rtl8169_private *);   \
 968                                                         \
 969 static const struct rtl_cond name = {                   \
 970         .check  = name ## _check,                       \
 971         .msg    = #name                                 \
 972 };                                                      \
 973                                                         \
 974 static bool name ## _check(struct rtl8169_private *tp)
 975
 976 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 977 {
 978         if (reg & 0xffff0001) {
 979                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 980                 return true;
 981         }
 982         return false;
 983 }
 984
 985 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 986 {
 987         void __iomem *ioaddr = tp->mmio_addr;
 988
 989         return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
 990 }
 991
 992 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 993 {
 994         void __iomem *ioaddr = tp->mmio_addr;
 995
 996         if (rtl_ocp_reg_failure(tp, reg))
 997                 return;
 998
 999         RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1000
1001         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1002 }
1003
1004 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1005 {
1006         void __iomem *ioaddr = tp->mmio_addr;
1007
1008         if (rtl_ocp_reg_failure(tp, reg))
1009                 return 0;
1010
1011         RTL_W32(GPHY_OCP, reg << 15);
1012
1013         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1014                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1015 }
1016
1017 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1018 {
1019         void __iomem *ioaddr = tp->mmio_addr;
1020
1021         if (rtl_ocp_reg_failure(tp, reg))
1022                 return;
1023
1024         RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1025 }
1026
1027 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1028 {
1029         void __iomem *ioaddr = tp->mmio_addr;
1030
1031         if (rtl_ocp_reg_failure(tp, reg))
1032                 return 0;
1033
1034         RTL_W32(OCPDR, reg << 15);
1035
1036         return RTL_R32(OCPDR);
1037 }
1038
1039 #define OCP_STD_PHY_BASE        0xa400
1040
1041 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1042 {
1043         if (reg == 0x1f) {
1044                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1045                 return;
1046         }
1047
1048         if (tp->ocp_base != OCP_STD_PHY_BASE)
1049                 reg -= 0x10;
1050
1051         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1052 }
1053
1054 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1055 {
1056         if (tp->ocp_base != OCP_STD_PHY_BASE)
1057                 reg -= 0x10;
1058
1059         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1060 }
1061
1062 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1063 {
1064         if (reg == 0x1f) {
1065                 tp->ocp_base = value << 4;
1066                 return;
1067         }
1068
1069         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1070 }
1071
1072 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1073 {
1074         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1075 }
1076
1077 DECLARE_RTL_COND(rtl_phyar_cond)
1078 {
1079         void __iomem *ioaddr = tp->mmio_addr;
1080
1081         return RTL_R32(PHYAR) & 0x80000000;
1082 }
1083
1084 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1085 {
1086         void __iomem *ioaddr = tp->mmio_addr;
1087
1088         RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1089
1090         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1091         /*
1092          * According to hardware specs a 20us delay is required after write
1093          * complete indication, but before sending next command.
1094          */
1095         udelay(20);
1096 }
1097
1098 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1099 {
1100         void __iomem *ioaddr = tp->mmio_addr;
1101         int value;
1102
1103         RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1104
1105         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1106                 RTL_R32(PHYAR) & 0xffff : ~0;
1107
1108         /*
1109          * According to hardware specs a 20us delay is required after read
1110          * complete indication, but before sending next command.
1111          */
1112         udelay(20);
1113
1114         return value;
1115 }
1116
1117 DECLARE_RTL_COND(rtl_ocpar_cond)
1118 {
1119         void __iomem *ioaddr = tp->mmio_addr;
1120
1121         return RTL_R32(OCPAR) & OCPAR_FLAG;
1122 }
1123
1124 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1125 {
1126         void __iomem *ioaddr = tp->mmio_addr;
1127
1128         RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1129         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1130         RTL_W32(EPHY_RXER_NUM, 0);
1131
1132         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1133 }
1134
1135 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1136 {
1137         r8168dp_1_mdio_access(tp, reg,
1138                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1139 }
1140
1141 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1142 {
1143         void __iomem *ioaddr = tp->mmio_addr;
1144
1145         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1146
1147         mdelay(1);
1148         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1149         RTL_W32(EPHY_RXER_NUM, 0);
1150
1151         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1152                 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1153 }
1154
1155 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1156
1157 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1158 {
1159         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1160 }
1161
1162 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1163 {
1164         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1165 }
1166
1167 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1168 {
1169         void __iomem *ioaddr = tp->mmio_addr;
1170
1171         r8168dp_2_mdio_start(ioaddr);
1172
1173         r8169_mdio_write(tp, reg, value);
1174
1175         r8168dp_2_mdio_stop(ioaddr);
1176 }
1177
1178 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1179 {
1180         void __iomem *ioaddr = tp->mmio_addr;
1181         int value;
1182
1183         r8168dp_2_mdio_start(ioaddr);
1184
1185         value = r8169_mdio_read(tp, reg);
1186
1187         r8168dp_2_mdio_stop(ioaddr);
1188
1189         return value;
1190 }
1191
1192 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1193 {
1194         tp->mdio_ops.write(tp, location, val);
1195 }
1196
1197 static int rtl_readphy(struct rtl8169_private *tp, int location)
1198 {
1199         return tp->mdio_ops.read(tp, location);
1200 }
1201
1202 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1203 {
1204         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1205 }
1206
1207 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1208 {
1209         int val;
1210
1211         val = rtl_readphy(tp, reg_addr);
1212         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1213 }
1214
1215 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1216                            int val)
1217 {
1218         struct rtl8169_private *tp = netdev_priv(dev);
1219
1220         rtl_writephy(tp, location, val);
1221 }
1222
1223 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1224 {
1225         struct rtl8169_private *tp = netdev_priv(dev);
1226
1227         return rtl_readphy(tp, location);
1228 }
1229
1230 DECLARE_RTL_COND(rtl_ephyar_cond)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233
1234         return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1235 }
1236
1237 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1238 {
1239         void __iomem *ioaddr = tp->mmio_addr;
1240
1241         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1242                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1243
1244         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1245
1246         udelay(10);
1247 }
1248
1249 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1250 {
1251         void __iomem *ioaddr = tp->mmio_addr;
1252
1253         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1254
1255         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1256                 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1257 }
1258
1259 DECLARE_RTL_COND(rtl_eriar_cond)
1260 {
1261         void __iomem *ioaddr = tp->mmio_addr;
1262
1263         return RTL_R32(ERIAR) & ERIAR_FLAG;
1264 }
1265
1266 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1267                           u32 val, int type)
1268 {
1269         void __iomem *ioaddr = tp->mmio_addr;
1270
1271         BUG_ON((addr & 3) || (mask == 0));
1272         RTL_W32(ERIDR, val);
1273         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1274
1275         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1276 }
1277
1278 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1279 {
1280         void __iomem *ioaddr = tp->mmio_addr;
1281
1282         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1283
1284         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1285                 RTL_R32(ERIDR) : ~0;
1286 }
1287
1288 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1289                          u32 m, int type)
1290 {
1291         u32 val;
1292
1293         val = rtl_eri_read(tp, addr, type);
1294         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1295 }
1296
1297 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298 {
1299         void __iomem *ioaddr = tp->mmio_addr;
1300
1301         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1302         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1303                 RTL_R32(OCPDR) : ~0;
1304 }
1305
1306 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1307 {
1308         return rtl_eri_read(tp, reg, ERIAR_OOB);
1309 }
1310
1311 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1312 {
1313         switch (tp->mac_version) {
1314         case RTL_GIGA_MAC_VER_27:
1315         case RTL_GIGA_MAC_VER_28:
1316         case RTL_GIGA_MAC_VER_31:
1317                 return r8168dp_ocp_read(tp, mask, reg);
1318         case RTL_GIGA_MAC_VER_49:
1319         case RTL_GIGA_MAC_VER_50:
1320         case RTL_GIGA_MAC_VER_51:
1321                 return r8168ep_ocp_read(tp, mask, reg);
1322         default:
1323                 BUG();
1324                 return ~0;
1325         }
1326 }
1327
1328 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1329                               u32 data)
1330 {
1331         void __iomem *ioaddr = tp->mmio_addr;
1332
1333         RTL_W32(OCPDR, data);
1334         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1335         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1336 }
1337
1338 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1339                               u32 data)
1340 {
1341         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1342                       data, ERIAR_OOB);
1343 }
1344
1345 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1346 {
1347         switch (tp->mac_version) {
1348         case RTL_GIGA_MAC_VER_27:
1349         case RTL_GIGA_MAC_VER_28:
1350         case RTL_GIGA_MAC_VER_31:
1351                 r8168dp_ocp_write(tp, mask, reg, data);
1352                 break;
1353         case RTL_GIGA_MAC_VER_49:
1354         case RTL_GIGA_MAC_VER_50:
1355         case RTL_GIGA_MAC_VER_51:
1356                 r8168ep_ocp_write(tp, mask, reg, data);
1357                 break;
1358         default:
1359                 BUG();
1360                 break;
1361         }
1362 }
1363
1364 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1365 {
1366         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1367
1368         ocp_write(tp, 0x1, 0x30, 0x00000001);
1369 }
1370
1371 #define OOB_CMD_RESET           0x00
1372 #define OOB_CMD_DRIVER_START    0x05
1373 #define OOB_CMD_DRIVER_STOP     0x06
1374
1375 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1376 {
1377         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1378 }
1379
1380 DECLARE_RTL_COND(rtl_ocp_read_cond)
1381 {
1382         u16 reg;
1383
1384         reg = rtl8168_get_ocp_reg(tp);
1385
1386         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1387 }
1388
1389 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1390 {
1391         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1392 }
1393
1394 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1395 {
1396         void __iomem *ioaddr = tp->mmio_addr;
1397
1398         return RTL_R8(IBISR0) & 0x02;
1399 }
1400
1401 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1402 {
1403         void __iomem *ioaddr = tp->mmio_addr;
1404
1405         RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1406         rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1407         RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1408         RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1409 }
1410
1411 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1412 {
1413         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1414         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1415 }
1416
1417 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1418 {
1419         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1420         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1421         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1422 }
1423
1424 static void rtl8168_driver_start(struct rtl8169_private *tp)
1425 {
1426         switch (tp->mac_version) {
1427         case RTL_GIGA_MAC_VER_27:
1428         case RTL_GIGA_MAC_VER_28:
1429         case RTL_GIGA_MAC_VER_31:
1430                 rtl8168dp_driver_start(tp);
1431                 break;
1432         case RTL_GIGA_MAC_VER_49:
1433         case RTL_GIGA_MAC_VER_50:
1434         case RTL_GIGA_MAC_VER_51:
1435                 rtl8168ep_driver_start(tp);
1436                 break;
1437         default:
1438                 BUG();
1439                 break;
1440         }
1441 }
1442
1443 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1444 {
1445         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1446         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1447 }
1448
1449 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1450 {
1451         rtl8168ep_stop_cmac(tp);
1452         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1453         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1454         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1455 }
1456
1457 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1458 {
1459         switch (tp->mac_version) {
1460         case RTL_GIGA_MAC_VER_27:
1461         case RTL_GIGA_MAC_VER_28:
1462         case RTL_GIGA_MAC_VER_31:
1463                 rtl8168dp_driver_stop(tp);
1464                 break;
1465         case RTL_GIGA_MAC_VER_49:
1466         case RTL_GIGA_MAC_VER_50:
1467         case RTL_GIGA_MAC_VER_51:
1468                 rtl8168ep_driver_stop(tp);
1469                 break;
1470         default:
1471                 BUG();
1472                 break;
1473         }
1474 }
1475
1476 static int r8168dp_check_dash(struct rtl8169_private *tp)
1477 {
1478         u16 reg = rtl8168_get_ocp_reg(tp);
1479
1480         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1481 }
1482
1483 static int r8168ep_check_dash(struct rtl8169_private *tp)
1484 {
1485         return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1486 }
1487
1488 static int r8168_check_dash(struct rtl8169_private *tp)
1489 {
1490         switch (tp->mac_version) {
1491         case RTL_GIGA_MAC_VER_27:
1492         case RTL_GIGA_MAC_VER_28:
1493         case RTL_GIGA_MAC_VER_31:
1494                 return r8168dp_check_dash(tp);
1495         case RTL_GIGA_MAC_VER_49:
1496         case RTL_GIGA_MAC_VER_50:
1497         case RTL_GIGA_MAC_VER_51:
1498                 return r8168ep_check_dash(tp);
1499         default:
1500                 return 0;
1501         }
1502 }
1503
1504 struct exgmac_reg {
1505         u16 addr;
1506         u16 mask;
1507         u32 val;
1508 };
1509
1510 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1511                                    const struct exgmac_reg *r, int len)
1512 {
1513         while (len-- > 0) {
1514                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1515                 r++;
1516         }
1517 }
1518
1519 DECLARE_RTL_COND(rtl_efusear_cond)
1520 {
1521         void __iomem *ioaddr = tp->mmio_addr;
1522
1523         return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1524 }
1525
1526 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1527 {
1528         void __iomem *ioaddr = tp->mmio_addr;
1529
1530         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1531
1532         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1533                 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1534 }
1535
1536 static u16 rtl_get_events(struct rtl8169_private *tp)
1537 {
1538         void __iomem *ioaddr = tp->mmio_addr;
1539
1540         return RTL_R16(IntrStatus);
1541 }
1542
1543 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1544 {
1545         void __iomem *ioaddr = tp->mmio_addr;
1546
1547         RTL_W16(IntrStatus, bits);
1548         mmiowb();
1549 }
1550
1551 static void rtl_irq_disable(struct rtl8169_private *tp)
1552 {
1553         void __iomem *ioaddr = tp->mmio_addr;
1554
1555         RTL_W16(IntrMask, 0);
1556         mmiowb();
1557 }
1558
1559 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1560 {
1561         void __iomem *ioaddr = tp->mmio_addr;
1562
1563         RTL_W16(IntrMask, bits);
1564 }
1565
1566 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1567 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1568 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1569
1570 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1571 {
1572         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1573 }
1574
1575 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1576 {
1577         void __iomem *ioaddr = tp->mmio_addr;
1578
1579         rtl_irq_disable(tp);
1580         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1581         RTL_R8(ChipCmd);
1582 }
1583
1584 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1585 {
1586         void __iomem *ioaddr = tp->mmio_addr;
1587
1588         return RTL_R32(TBICSR) & TBIReset;
1589 }
1590
1591 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1592 {
1593         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1594 }
1595
1596 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1597 {
1598         return RTL_R32(TBICSR) & TBILinkOk;
1599 }
1600
1601 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1602 {
1603         return RTL_R8(PHYstatus) & LinkStatus;
1604 }
1605
1606 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1607 {
1608         void __iomem *ioaddr = tp->mmio_addr;
1609
1610         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1611 }
1612
1613 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1614 {
1615         unsigned int val;
1616
1617         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1618         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1619 }
1620
1621 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1622 {
1623         void __iomem *ioaddr = tp->mmio_addr;
1624         struct net_device *dev = tp->dev;
1625
1626         if (!netif_running(dev))
1627                 return;
1628
1629         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1630             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1631                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1632                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1633                                       ERIAR_EXGMAC);
1634                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1635                                       ERIAR_EXGMAC);
1636                 } else if (RTL_R8(PHYstatus) & _100bps) {
1637                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1638                                       ERIAR_EXGMAC);
1639                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1640                                       ERIAR_EXGMAC);
1641                 } else {
1642                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1643                                       ERIAR_EXGMAC);
1644                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1645                                       ERIAR_EXGMAC);
1646                 }
1647                 /* Reset packet filter */
1648                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1649                              ERIAR_EXGMAC);
1650                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1651                              ERIAR_EXGMAC);
1652         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1653                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1654                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1655                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1656                                       ERIAR_EXGMAC);
1657                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1658                                       ERIAR_EXGMAC);
1659                 } else {
1660                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1661                                       ERIAR_EXGMAC);
1662                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1663                                       ERIAR_EXGMAC);
1664                 }
1665         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1666                 if (RTL_R8(PHYstatus) & _10bps) {
1667                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1668                                       ERIAR_EXGMAC);
1669                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1670                                       ERIAR_EXGMAC);
1671                 } else {
1672                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1673                                       ERIAR_EXGMAC);
1674                 }
1675         }
1676 }
1677
1678 static void rtl8169_check_link_status(struct net_device *dev,
1679                                       struct rtl8169_private *tp,
1680                                       void __iomem *ioaddr)
1681 {
1682         if (tp->link_ok(ioaddr)) {
1683                 rtl_link_chg_patch(tp);
1684                 /* This is to cancel a scheduled suspend if there's one. */
1685                 pm_request_resume(&tp->pci_dev->dev);
1686                 netif_carrier_on(dev);
1687                 if (net_ratelimit())
1688                         netif_info(tp, ifup, dev, "link up\n");
1689         } else {
1690                 netif_carrier_off(dev);
1691                 netif_info(tp, ifdown, dev, "link down\n");
1692                 pm_runtime_idle(&tp->pci_dev->dev);
1693         }
1694 }
1695
1696 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1699 {
1700         void __iomem *ioaddr = tp->mmio_addr;
1701         u8 options;
1702         u32 wolopts = 0;
1703
1704         options = RTL_R8(Config1);
1705         if (!(options & PMEnable))
1706                 return 0;
1707
1708         options = RTL_R8(Config3);
1709         if (options & LinkUp)
1710                 wolopts |= WAKE_PHY;
1711         switch (tp->mac_version) {
1712         case RTL_GIGA_MAC_VER_34:
1713         case RTL_GIGA_MAC_VER_35:
1714         case RTL_GIGA_MAC_VER_36:
1715         case RTL_GIGA_MAC_VER_37:
1716         case RTL_GIGA_MAC_VER_38:
1717         case RTL_GIGA_MAC_VER_40:
1718         case RTL_GIGA_MAC_VER_41:
1719         case RTL_GIGA_MAC_VER_42:
1720         case RTL_GIGA_MAC_VER_43:
1721         case RTL_GIGA_MAC_VER_44:
1722         case RTL_GIGA_MAC_VER_45:
1723         case RTL_GIGA_MAC_VER_46:
1724         case RTL_GIGA_MAC_VER_47:
1725         case RTL_GIGA_MAC_VER_48:
1726         case RTL_GIGA_MAC_VER_49:
1727         case RTL_GIGA_MAC_VER_50:
1728         case RTL_GIGA_MAC_VER_51:
1729                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730                         wolopts |= WAKE_MAGIC;
1731                 break;
1732         default:
1733                 if (options & MagicPacket)
1734                         wolopts |= WAKE_MAGIC;
1735                 break;
1736         }
1737
1738         options = RTL_R8(Config5);
1739         if (options & UWF)
1740                 wolopts |= WAKE_UCAST;
1741         if (options & BWF)
1742                 wolopts |= WAKE_BCAST;
1743         if (options & MWF)
1744                 wolopts |= WAKE_MCAST;
1745
1746         return wolopts;
1747 }
1748
1749 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1750 {
1751         struct rtl8169_private *tp = netdev_priv(dev);
1752         struct device *d = &tp->pci_dev->dev;
1753
1754         pm_runtime_get_noresume(d);
1755
1756         rtl_lock_work(tp);
1757
1758         wol->supported = WAKE_ANY;
1759         if (pm_runtime_active(d))
1760                 wol->wolopts = __rtl8169_get_wol(tp);
1761         else
1762                 wol->wolopts = tp->saved_wolopts;
1763
1764         rtl_unlock_work(tp);
1765
1766         pm_runtime_put_noidle(d);
1767 }
1768
1769 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1770 {
1771         void __iomem *ioaddr = tp->mmio_addr;
1772         unsigned int i, tmp;
1773         static const struct {
1774                 u32 opt;
1775                 u16 reg;
1776                 u8  mask;
1777         } cfg[] = {
1778                 { WAKE_PHY,   Config3, LinkUp },
1779                 { WAKE_UCAST, Config5, UWF },
1780                 { WAKE_BCAST, Config5, BWF },
1781                 { WAKE_MCAST, Config5, MWF },
1782                 { WAKE_ANY,   Config5, LanWake },
1783                 { WAKE_MAGIC, Config3, MagicPacket }
1784         };
1785         u8 options;
1786
1787         RTL_W8(Cfg9346, Cfg9346_Unlock);
1788
1789         switch (tp->mac_version) {
1790         case RTL_GIGA_MAC_VER_34:
1791         case RTL_GIGA_MAC_VER_35:
1792         case RTL_GIGA_MAC_VER_36:
1793         case RTL_GIGA_MAC_VER_37:
1794         case RTL_GIGA_MAC_VER_38:
1795         case RTL_GIGA_MAC_VER_40:
1796         case RTL_GIGA_MAC_VER_41:
1797         case RTL_GIGA_MAC_VER_42:
1798         case RTL_GIGA_MAC_VER_43:
1799         case RTL_GIGA_MAC_VER_44:
1800         case RTL_GIGA_MAC_VER_45:
1801         case RTL_GIGA_MAC_VER_46:
1802         case RTL_GIGA_MAC_VER_47:
1803         case RTL_GIGA_MAC_VER_48:
1804         case RTL_GIGA_MAC_VER_49:
1805         case RTL_GIGA_MAC_VER_50:
1806         case RTL_GIGA_MAC_VER_51:
1807                 tmp = ARRAY_SIZE(cfg) - 1;
1808                 if (wolopts & WAKE_MAGIC)
1809                         rtl_w0w1_eri(tp,
1810                                      0x0dc,
1811                                      ERIAR_MASK_0100,
1812                                      MagicPacket_v2,
1813                                      0x0000,
1814                                      ERIAR_EXGMAC);
1815                 else
1816                         rtl_w0w1_eri(tp,
1817                                      0x0dc,
1818                                      ERIAR_MASK_0100,
1819                                      0x0000,
1820                                      MagicPacket_v2,
1821                                      ERIAR_EXGMAC);
1822                 break;
1823         default:
1824                 tmp = ARRAY_SIZE(cfg);
1825                 break;
1826         }
1827
1828         for (i = 0; i < tmp; i++) {
1829                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1830                 if (wolopts & cfg[i].opt)
1831                         options |= cfg[i].mask;
1832                 RTL_W8(cfg[i].reg, options);
1833         }
1834
1835         switch (tp->mac_version) {
1836         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1837                 options = RTL_R8(Config1) & ~PMEnable;
1838                 if (wolopts)
1839                         options |= PMEnable;
1840                 RTL_W8(Config1, options);
1841                 break;
1842         default:
1843                 options = RTL_R8(Config2) & ~PME_SIGNAL;
1844                 if (wolopts)
1845                         options |= PME_SIGNAL;
1846                 RTL_W8(Config2, options);
1847                 break;
1848         }
1849
1850         RTL_W8(Cfg9346, Cfg9346_Lock);
1851 }
1852
1853 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1854 {
1855         struct rtl8169_private *tp = netdev_priv(dev);
1856         struct device *d = &tp->pci_dev->dev;
1857
1858         pm_runtime_get_noresume(d);
1859
1860         rtl_lock_work(tp);
1861
1862         if (wol->wolopts)
1863                 tp->features |= RTL_FEATURE_WOL;
1864         else
1865                 tp->features &= ~RTL_FEATURE_WOL;
1866         if (pm_runtime_active(d))
1867                 __rtl8169_set_wol(tp, wol->wolopts);
1868         else
1869                 tp->saved_wolopts = wol->wolopts;
1870
1871         rtl_unlock_work(tp);
1872
1873         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1874
1875         pm_runtime_put_noidle(d);
1876
1877         return 0;
1878 }
1879
1880 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1881 {
1882         return rtl_chip_infos[tp->mac_version].fw_name;
1883 }
1884
1885 static void rtl8169_get_drvinfo(struct net_device *dev,
1886                                 struct ethtool_drvinfo *info)
1887 {
1888         struct rtl8169_private *tp = netdev_priv(dev);
1889         struct rtl_fw *rtl_fw = tp->rtl_fw;
1890
1891         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1892         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1893         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1894         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1895         if (!IS_ERR_OR_NULL(rtl_fw))
1896                 strlcpy(info->fw_version, rtl_fw->version,
1897                         sizeof(info->fw_version));
1898 }
1899
1900 static int rtl8169_get_regs_len(struct net_device *dev)
1901 {
1902         return R8169_REGS_SIZE;
1903 }
1904
1905 static int rtl8169_set_speed_tbi(struct net_device *dev,
1906                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1907 {
1908         struct rtl8169_private *tp = netdev_priv(dev);
1909         void __iomem *ioaddr = tp->mmio_addr;
1910         int ret = 0;
1911         u32 reg;
1912
1913         reg = RTL_R32(TBICSR);
1914         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1915             (duplex == DUPLEX_FULL)) {
1916                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1917         } else if (autoneg == AUTONEG_ENABLE)
1918                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1919         else {
1920                 netif_warn(tp, link, dev,
1921                            "incorrect speed setting refused in TBI mode\n");
1922                 ret = -EOPNOTSUPP;
1923         }
1924
1925         return ret;
1926 }
1927
1928 static int rtl8169_set_speed_xmii(struct net_device *dev,
1929                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1930 {
1931         struct rtl8169_private *tp = netdev_priv(dev);
1932         int giga_ctrl, bmcr;
1933         int rc = -EINVAL;
1934
1935         rtl_writephy(tp, 0x1f, 0x0000);
1936
1937         if (autoneg == AUTONEG_ENABLE) {
1938                 int auto_nego;
1939
1940                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1941                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1942                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1943
1944                 if (adv & ADVERTISED_10baseT_Half)
1945                         auto_nego |= ADVERTISE_10HALF;
1946                 if (adv & ADVERTISED_10baseT_Full)
1947                         auto_nego |= ADVERTISE_10FULL;
1948                 if (adv & ADVERTISED_100baseT_Half)
1949                         auto_nego |= ADVERTISE_100HALF;
1950                 if (adv & ADVERTISED_100baseT_Full)
1951                         auto_nego |= ADVERTISE_100FULL;
1952
1953                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1954
1955                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1956                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1957
1958                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1959                 if (tp->mii.supports_gmii) {
1960                         if (adv & ADVERTISED_1000baseT_Half)
1961                                 giga_ctrl |= ADVERTISE_1000HALF;
1962                         if (adv & ADVERTISED_1000baseT_Full)
1963                                 giga_ctrl |= ADVERTISE_1000FULL;
1964                 } else if (adv & (ADVERTISED_1000baseT_Half |
1965                                   ADVERTISED_1000baseT_Full)) {
1966                         netif_info(tp, link, dev,
1967                                    "PHY does not support 1000Mbps\n");
1968                         goto out;
1969                 }
1970
1971                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1972
1973                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1974                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1975         } else {
1976                 if (speed == SPEED_10)
1977                         bmcr = 0;
1978                 else if (speed == SPEED_100)
1979                         bmcr = BMCR_SPEED100;
1980                 else
1981                         goto out;
1982
1983                 if (duplex == DUPLEX_FULL)
1984                         bmcr |= BMCR_FULLDPLX;
1985         }
1986
1987         rtl_writephy(tp, MII_BMCR, bmcr);
1988
1989         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1990             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1991                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1992                         rtl_writephy(tp, 0x17, 0x2138);
1993                         rtl_writephy(tp, 0x0e, 0x0260);
1994                 } else {
1995                         rtl_writephy(tp, 0x17, 0x2108);
1996                         rtl_writephy(tp, 0x0e, 0x0000);
1997                 }
1998         }
1999
2000         rc = 0;
2001 out:
2002         return rc;
2003 }
2004
2005 static int rtl8169_set_speed(struct net_device *dev,
2006                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2007 {
2008         struct rtl8169_private *tp = netdev_priv(dev);
2009         int ret;
2010
2011         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2012         if (ret < 0)
2013                 goto out;
2014
2015         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2016             (advertising & ADVERTISED_1000baseT_Full) &&
2017             !pci_is_pcie(tp->pci_dev)) {
2018                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2019         }
2020 out:
2021         return ret;
2022 }
2023
2024 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2025         netdev_features_t features)
2026 {
2027         struct rtl8169_private *tp = netdev_priv(dev);
2028
2029         if (dev->mtu > TD_MSS_MAX)
2030                 features &= ~NETIF_F_ALL_TSO;
2031
2032         if (dev->mtu > JUMBO_1K &&
2033             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2034                 features &= ~NETIF_F_IP_CSUM;
2035
2036         return features;
2037 }
2038
2039 static void __rtl8169_set_features(struct net_device *dev,
2040                                    netdev_features_t features)
2041 {
2042         struct rtl8169_private *tp = netdev_priv(dev);
2043         void __iomem *ioaddr = tp->mmio_addr;
2044         u32 rx_config;
2045
2046         rx_config = RTL_R32(RxConfig);
2047         if (features & NETIF_F_RXALL)
2048                 rx_config |= (AcceptErr | AcceptRunt);
2049         else
2050                 rx_config &= ~(AcceptErr | AcceptRunt);
2051
2052         RTL_W32(RxConfig, rx_config);
2053
2054         if (features & NETIF_F_RXCSUM)
2055                 tp->cp_cmd |= RxChkSum;
2056         else
2057                 tp->cp_cmd &= ~RxChkSum;
2058
2059         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2060                 tp->cp_cmd |= RxVlan;
2061         else
2062                 tp->cp_cmd &= ~RxVlan;
2063
2064         tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2065
2066         RTL_W16(CPlusCmd, tp->cp_cmd);
2067         RTL_R16(CPlusCmd);
2068 }
2069
2070 static int rtl8169_set_features(struct net_device *dev,
2071                                 netdev_features_t features)
2072 {
2073         struct rtl8169_private *tp = netdev_priv(dev);
2074
2075         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2076
2077         rtl_lock_work(tp);
2078         if (features ^ dev->features)
2079                 __rtl8169_set_features(dev, features);
2080         rtl_unlock_work(tp);
2081
2082         return 0;
2083 }
2084
2085
2086 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2087 {
2088         return (skb_vlan_tag_present(skb)) ?
2089                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2090 }
2091
2092 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2093 {
2094         u32 opts2 = le32_to_cpu(desc->opts2);
2095
2096         if (opts2 & RxVlanTag)
2097                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2098 }
2099
2100 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2101                                           struct ethtool_link_ksettings *cmd)
2102 {
2103         struct rtl8169_private *tp = netdev_priv(dev);
2104         void __iomem *ioaddr = tp->mmio_addr;
2105         u32 status;
2106         u32 supported, advertising;
2107
2108         supported =
2109                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2110         cmd->base.port = PORT_FIBRE;
2111
2112         status = RTL_R32(TBICSR);
2113         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2114         cmd->base.autoneg = !!(status & TBINwEnable);
2115
2116         cmd->base.speed = SPEED_1000;
2117         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2118
2119         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2120                                                 supported);
2121         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2122                                                 advertising);
2123
2124         return 0;
2125 }
2126
2127 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2128                                            struct ethtool_link_ksettings *cmd)
2129 {
2130         struct rtl8169_private *tp = netdev_priv(dev);
2131
2132         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2133
2134         return 0;
2135 }
2136
2137 static int rtl8169_get_link_ksettings(struct net_device *dev,
2138                                       struct ethtool_link_ksettings *cmd)
2139 {
2140         struct rtl8169_private *tp = netdev_priv(dev);
2141         int rc;
2142
2143         rtl_lock_work(tp);
2144         rc = tp->get_link_ksettings(dev, cmd);
2145         rtl_unlock_work(tp);
2146
2147         return rc;
2148 }
2149
2150 static int rtl8169_set_link_ksettings(struct net_device *dev,
2151                                       const struct ethtool_link_ksettings *cmd)
2152 {
2153         struct rtl8169_private *tp = netdev_priv(dev);
2154         int rc;
2155         u32 advertising;
2156
2157         if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2158             cmd->link_modes.advertising))
2159                 return -EINVAL;
2160
2161         del_timer_sync(&tp->timer);
2162
2163         rtl_lock_work(tp);
2164         rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2165                                cmd->base.duplex, advertising);
2166         rtl_unlock_work(tp);
2167
2168         return rc;
2169 }
2170
2171 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2172                              void *p)
2173 {
2174         struct rtl8169_private *tp = netdev_priv(dev);
2175         u32 __iomem *data = tp->mmio_addr;
2176         u32 *dw = p;
2177         int i;
2178
2179         rtl_lock_work(tp);
2180         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2181                 memcpy_fromio(dw++, data++, 4);
2182         rtl_unlock_work(tp);
2183 }
2184
2185 static u32 rtl8169_get_msglevel(struct net_device *dev)
2186 {
2187         struct rtl8169_private *tp = netdev_priv(dev);
2188
2189         return tp->msg_enable;
2190 }
2191
2192 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2193 {
2194         struct rtl8169_private *tp = netdev_priv(dev);
2195
2196         tp->msg_enable = value;
2197 }
2198
2199 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2200         "tx_packets",
2201         "rx_packets",
2202         "tx_errors",
2203         "rx_errors",
2204         "rx_missed",
2205         "align_errors",
2206         "tx_single_collisions",
2207         "tx_multi_collisions",
2208         "unicast",
2209         "broadcast",
2210         "multicast",
2211         "tx_aborted",
2212         "tx_underrun",
2213 };
2214
2215 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2216 {
2217         switch (sset) {
2218         case ETH_SS_STATS:
2219                 return ARRAY_SIZE(rtl8169_gstrings);
2220         default:
2221                 return -EOPNOTSUPP;
2222         }
2223 }
2224
2225 DECLARE_RTL_COND(rtl_counters_cond)
2226 {
2227         void __iomem *ioaddr = tp->mmio_addr;
2228
2229         return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2230 }
2231
2232 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2233 {
2234         struct rtl8169_private *tp = netdev_priv(dev);
2235         void __iomem *ioaddr = tp->mmio_addr;
2236         dma_addr_t paddr = tp->counters_phys_addr;
2237         u32 cmd;
2238         bool ret;
2239
2240         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2241         cmd = (u64)paddr & DMA_BIT_MASK(32);
2242         RTL_W32(CounterAddrLow, cmd);
2243         RTL_W32(CounterAddrLow, cmd | counter_cmd);
2244
2245         ret = rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2246
2247         RTL_W32(CounterAddrLow, 0);
2248         RTL_W32(CounterAddrHigh, 0);
2249
2250         return ret;
2251 }
2252
2253 static bool rtl8169_reset_counters(struct net_device *dev)
2254 {
2255         struct rtl8169_private *tp = netdev_priv(dev);
2256
2257         /*
2258          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2259          * tally counters.
2260          */
2261         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2262                 return true;
2263
2264         return rtl8169_do_counters(dev, CounterReset);
2265 }
2266
2267 static bool rtl8169_update_counters(struct net_device *dev)
2268 {
2269         struct rtl8169_private *tp = netdev_priv(dev);
2270         void __iomem *ioaddr = tp->mmio_addr;
2271
2272         /*
2273          * Some chips are unable to dump tally counters when the receiver
2274          * is disabled.
2275          */
2276         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2277                 return true;
2278
2279         return rtl8169_do_counters(dev, CounterDump);
2280 }
2281
2282 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2283 {
2284         struct rtl8169_private *tp = netdev_priv(dev);
2285         struct rtl8169_counters *counters = tp->counters;
2286         bool ret = false;
2287
2288         /*
2289          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2290          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2291          * reset by a power cycle, while the counter values collected by the
2292          * driver are reset at every driver unload/load cycle.
2293          *
2294          * To make sure the HW values returned by @get_stats64 match the SW
2295          * values, we collect the initial values at first open(*) and use them
2296          * as offsets to normalize the values returned by @get_stats64.
2297          *
2298          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2299          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2300          * set at open time by rtl_hw_start.
2301          */
2302
2303         if (tp->tc_offset.inited)
2304                 return true;
2305
2306         /* If both, reset and update fail, propagate to caller. */
2307         if (rtl8169_reset_counters(dev))
2308                 ret = true;
2309
2310         if (rtl8169_update_counters(dev))
2311                 ret = true;
2312
2313         tp->tc_offset.tx_errors = counters->tx_errors;
2314         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2315         tp->tc_offset.tx_aborted = counters->tx_aborted;
2316         tp->tc_offset.inited = true;
2317
2318         return ret;
2319 }
2320
2321 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2322                                       struct ethtool_stats *stats, u64 *data)
2323 {
2324         struct rtl8169_private *tp = netdev_priv(dev);
2325         struct device *d = &tp->pci_dev->dev;
2326         struct rtl8169_counters *counters = tp->counters;
2327
2328         ASSERT_RTNL();
2329
2330         pm_runtime_get_noresume(d);
2331
2332         if (pm_runtime_active(d))
2333                 rtl8169_update_counters(dev);
2334
2335         pm_runtime_put_noidle(d);
2336
2337         data[0] = le64_to_cpu(counters->tx_packets);
2338         data[1] = le64_to_cpu(counters->rx_packets);
2339         data[2] = le64_to_cpu(counters->tx_errors);
2340         data[3] = le32_to_cpu(counters->rx_errors);
2341         data[4] = le16_to_cpu(counters->rx_missed);
2342         data[5] = le16_to_cpu(counters->align_errors);
2343         data[6] = le32_to_cpu(counters->tx_one_collision);
2344         data[7] = le32_to_cpu(counters->tx_multi_collision);
2345         data[8] = le64_to_cpu(counters->rx_unicast);
2346         data[9] = le64_to_cpu(counters->rx_broadcast);
2347         data[10] = le32_to_cpu(counters->rx_multicast);
2348         data[11] = le16_to_cpu(counters->tx_aborted);
2349         data[12] = le16_to_cpu(counters->tx_underun);
2350 }
2351
2352 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2353 {
2354         switch(stringset) {
2355         case ETH_SS_STATS:
2356                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2357                 break;
2358         }
2359 }
2360
2361 static int rtl8169_nway_reset(struct net_device *dev)
2362 {
2363         struct rtl8169_private *tp = netdev_priv(dev);
2364
2365         return mii_nway_restart(&tp->mii);
2366 }
2367
2368 /*
2369  * Interrupt coalescing
2370  *
2371  * > 1 - the availability of the IntrMitigate (0xe2) register through the
2372  * >     8169, 8168 and 810x line of chipsets
2373  *
2374  * 8169, 8168, and 8136(810x) serial chipsets support it.
2375  *
2376  * > 2 - the Tx timer unit at gigabit speed
2377  *
2378  * The unit of the timer depends on both the speed and the setting of CPlusCmd
2379  * (0xe0) bit 1 and bit 0.
2380  *
2381  * For 8169
2382  * bit[1:0] \ speed        1000M           100M            10M
2383  * 0 0                     320ns           2.56us          40.96us
2384  * 0 1                     2.56us          20.48us         327.7us
2385  * 1 0                     5.12us          40.96us         655.4us
2386  * 1 1                     10.24us         81.92us         1.31ms
2387  *
2388  * For the other
2389  * bit[1:0] \ speed        1000M           100M            10M
2390  * 0 0                     5us             2.56us          40.96us
2391  * 0 1                     40us            20.48us         327.7us
2392  * 1 0                     80us            40.96us         655.4us
2393  * 1 1                     160us           81.92us         1.31ms
2394  */
2395
2396 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2397 struct rtl_coalesce_scale {
2398         /* Rx / Tx */
2399         u32 nsecs[2];
2400 };
2401
2402 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2403 struct rtl_coalesce_info {
2404         u32 speed;
2405         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
2406 };
2407
2408 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2409 #define rxtx_x1822(r, t) {              \
2410         {{(r),          (t)}},          \
2411         {{(r)*8,        (t)*8}},        \
2412         {{(r)*8*2,      (t)*8*2}},      \
2413         {{(r)*8*2*2,    (t)*8*2*2}},    \
2414 }
2415 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2416         /* speed        delays:     rx00   tx00 */
2417         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2418         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2419         { SPEED_1000,   rxtx_x1822(  320,   320)        },
2420         { 0 },
2421 };
2422
2423 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2424         /* speed        delays:     rx00   tx00 */
2425         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2426         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2427         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
2428         { 0 },
2429 };
2430 #undef rxtx_x1822
2431
2432 /* get rx/tx scale vector corresponding to current speed */
2433 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2434 {
2435         struct rtl8169_private *tp = netdev_priv(dev);
2436         struct ethtool_link_ksettings ecmd;
2437         const struct rtl_coalesce_info *ci;
2438         int rc;
2439
2440         rc = rtl8169_get_link_ksettings(dev, &ecmd);
2441         if (rc < 0)
2442                 return ERR_PTR(rc);
2443
2444         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2445                 if (ecmd.base.speed == ci->speed) {
2446                         return ci;
2447                 }
2448         }
2449
2450         return ERR_PTR(-ELNRNG);
2451 }
2452
2453 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2454 {
2455         struct rtl8169_private *tp = netdev_priv(dev);
2456         void __iomem *ioaddr = tp->mmio_addr;
2457         const struct rtl_coalesce_info *ci;
2458         const struct rtl_coalesce_scale *scale;
2459         struct {
2460                 u32 *max_frames;
2461                 u32 *usecs;
2462         } coal_settings [] = {
2463                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2464                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2465         }, *p = coal_settings;
2466         int i;
2467         u16 w;
2468
2469         memset(ec, 0, sizeof(*ec));
2470
2471         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2472         ci = rtl_coalesce_info(dev);
2473         if (IS_ERR(ci))
2474                 return PTR_ERR(ci);
2475
2476         scale = &ci->scalev[RTL_R16(CPlusCmd) & 3];
2477
2478         /* read IntrMitigate and adjust according to scale */
2479         for (w = RTL_R16(IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2480                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2481                 w >>= RTL_COALESCE_SHIFT;
2482                 *p->usecs = w & RTL_COALESCE_MASK;
2483         }
2484
2485         for (i = 0; i < 2; i++) {
2486                 p = coal_settings + i;
2487                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2488
2489                 /*
2490                  * ethtool_coalesce says it is illegal to set both usecs and
2491                  * max_frames to 0.
2492                  */
2493                 if (!*p->usecs && !*p->max_frames)
2494                         *p->max_frames = 1;
2495         }
2496
2497         return 0;
2498 }
2499
2500 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2501 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2502                         struct net_device *dev, u32 nsec, u16 *cp01)
2503 {
2504         const struct rtl_coalesce_info *ci;
2505         u16 i;
2506
2507         ci = rtl_coalesce_info(dev);
2508         if (IS_ERR(ci))
2509                 return ERR_CAST(ci);
2510
2511         for (i = 0; i < 4; i++) {
2512                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2513                                         ci->scalev[i].nsecs[1]);
2514                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2515                         *cp01 = i;
2516                         return &ci->scalev[i];
2517                 }
2518         }
2519
2520         return ERR_PTR(-EINVAL);
2521 }
2522
2523 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2524 {
2525         struct rtl8169_private *tp = netdev_priv(dev);
2526         void __iomem *ioaddr = tp->mmio_addr;
2527         const struct rtl_coalesce_scale *scale;
2528         struct {
2529                 u32 frames;
2530                 u32 usecs;
2531         } coal_settings [] = {
2532                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2533                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2534         }, *p = coal_settings;
2535         u16 w = 0, cp01;
2536         int i;
2537
2538         scale = rtl_coalesce_choose_scale(dev,
2539                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2540         if (IS_ERR(scale))
2541                 return PTR_ERR(scale);
2542
2543         for (i = 0; i < 2; i++, p++) {
2544                 u32 units;
2545
2546                 /*
2547                  * accept max_frames=1 we returned in rtl_get_coalesce.
2548                  * accept it not only when usecs=0 because of e.g. the following scenario:
2549                  *
2550                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2551                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2552                  * - then user does `ethtool -C eth0 rx-usecs 100`
2553                  *
2554                  * since ethtool sends to kernel whole ethtool_coalesce
2555                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2556                  * we'll reject it below in `frames % 4 != 0`.
2557                  */
2558                 if (p->frames == 1) {
2559                         p->frames = 0;
2560                 }
2561
2562                 units = p->usecs * 1000 / scale->nsecs[i];
2563                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2564                         return -EINVAL;
2565
2566                 w <<= RTL_COALESCE_SHIFT;
2567                 w |= units;
2568                 w <<= RTL_COALESCE_SHIFT;
2569                 w |= p->frames >> 2;
2570         }
2571
2572         rtl_lock_work(tp);
2573
2574         RTL_W16(IntrMitigate, swab16(w));
2575
2576         tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2577         RTL_W16(CPlusCmd, tp->cp_cmd);
2578         RTL_R16(CPlusCmd);
2579
2580         rtl_unlock_work(tp);
2581
2582         return 0;
2583 }
2584
2585 static const struct ethtool_ops rtl8169_ethtool_ops = {
2586         .get_drvinfo            = rtl8169_get_drvinfo,
2587         .get_regs_len           = rtl8169_get_regs_len,
2588         .get_link               = ethtool_op_get_link,
2589         .get_coalesce           = rtl_get_coalesce,
2590         .set_coalesce           = rtl_set_coalesce,
2591         .get_msglevel           = rtl8169_get_msglevel,
2592         .set_msglevel           = rtl8169_set_msglevel,
2593         .get_regs               = rtl8169_get_regs,
2594         .get_wol                = rtl8169_get_wol,
2595         .set_wol                = rtl8169_set_wol,
2596         .get_strings            = rtl8169_get_strings,
2597         .get_sset_count         = rtl8169_get_sset_count,
2598         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2599         .get_ts_info            = ethtool_op_get_ts_info,
2600         .nway_reset             = rtl8169_nway_reset,
2601         .get_link_ksettings     = rtl8169_get_link_ksettings,
2602         .set_link_ksettings     = rtl8169_set_link_ksettings,
2603 };
2604
2605 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2606                                     struct net_device *dev, u8 default_version)
2607 {
2608         void __iomem *ioaddr = tp->mmio_addr;
2609         /*
2610          * The driver currently handles the 8168Bf and the 8168Be identically
2611          * but they can be identified more specifically through the test below
2612          * if needed:
2613          *
2614          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2615          *
2616          * Same thing for the 8101Eb and the 8101Ec:
2617          *
2618          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2619          */
2620         static const struct rtl_mac_info {
2621                 u32 mask;
2622                 u32 val;
2623                 int mac_version;
2624         } mac_info[] = {
2625                 /* 8168EP family. */
2626                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2627                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2628                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2629
2630                 /* 8168H family. */
2631                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2632                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2633
2634                 /* 8168G family. */
2635                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2636                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2637                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2638                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2639
2640                 /* 8168F family. */
2641                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2642                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2643                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2644
2645                 /* 8168E family. */
2646                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2647                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2648                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2649                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2650
2651                 /* 8168D family. */
2652                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2653                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2654                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2655
2656                 /* 8168DP family. */
2657                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2658                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2659                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2660
2661                 /* 8168C family. */
2662                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2663                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2664                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2665                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2666                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2667                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2668                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2669                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2670                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2671
2672                 /* 8168B family. */
2673                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2674                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2675                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2676                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2677
2678                 /* 8101 family. */
2679                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2680                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2681                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2682                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2683                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2684                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2685                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2686                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2687                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2688                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2689                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2690                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2691                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2692                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2693                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2694                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2695                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2696                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2697                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2698                 /* FIXME: where did these entries come from ? -- FR */
2699                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2700                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2701
2702                 /* 8110 family. */
2703                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2704                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2705                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2706                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2707                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2708                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2709
2710                 /* Catch-all */
2711                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2712         };
2713         const struct rtl_mac_info *p = mac_info;
2714         u32 reg;
2715
2716         reg = RTL_R32(TxConfig);
2717         while ((reg & p->mask) != p->val)
2718                 p++;
2719         tp->mac_version = p->mac_version;
2720
2721         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2722                 netif_notice(tp, probe, dev,
2723                              "unknown MAC, using family default\n");
2724                 tp->mac_version = default_version;
2725         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2726                 tp->mac_version = tp->mii.supports_gmii ?
2727                                   RTL_GIGA_MAC_VER_42 :
2728                                   RTL_GIGA_MAC_VER_43;
2729         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2730                 tp->mac_version = tp->mii.supports_gmii ?
2731                                   RTL_GIGA_MAC_VER_45 :
2732                                   RTL_GIGA_MAC_VER_47;
2733         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2734                 tp->mac_version = tp->mii.supports_gmii ?
2735                                   RTL_GIGA_MAC_VER_46 :
2736                                   RTL_GIGA_MAC_VER_48;
2737         }
2738 }
2739
2740 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2741 {
2742         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2743 }
2744
2745 struct phy_reg {
2746         u16 reg;
2747         u16 val;
2748 };
2749
2750 static void rtl_writephy_batch(struct rtl8169_private *tp,
2751                                const struct phy_reg *regs, int len)
2752 {
2753         while (len-- > 0) {
2754                 rtl_writephy(tp, regs->reg, regs->val);
2755                 regs++;
2756         }
2757 }
2758
2759 #define PHY_READ                0x00000000
2760 #define PHY_DATA_OR             0x10000000
2761 #define PHY_DATA_AND            0x20000000
2762 #define PHY_BJMPN               0x30000000
2763 #define PHY_MDIO_CHG            0x40000000
2764 #define PHY_CLEAR_READCOUNT     0x70000000
2765 #define PHY_WRITE               0x80000000
2766 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2767 #define PHY_COMP_EQ_SKIPN       0xa0000000
2768 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2769 #define PHY_WRITE_PREVIOUS      0xc0000000
2770 #define PHY_SKIPN               0xd0000000
2771 #define PHY_DELAY_MS            0xe0000000
2772
2773 struct fw_info {
2774         u32     magic;
2775         char    version[RTL_VER_SIZE];
2776         __le32  fw_start;
2777         __le32  fw_len;
2778         u8      chksum;
2779 } __packed;
2780
2781 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2782
2783 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2784 {
2785         const struct firmware *fw = rtl_fw->fw;
2786         struct fw_info *fw_info = (struct fw_info *)fw->data;
2787         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2788         char *version = rtl_fw->version;
2789         bool rc = false;
2790
2791         if (fw->size < FW_OPCODE_SIZE)
2792                 goto out;
2793
2794         if (!fw_info->magic) {
2795                 size_t i, size, start;
2796                 u8 checksum = 0;
2797
2798                 if (fw->size < sizeof(*fw_info))
2799                         goto out;
2800
2801                 for (i = 0; i < fw->size; i++)
2802                         checksum += fw->data[i];
2803                 if (checksum != 0)
2804                         goto out;
2805
2806                 start = le32_to_cpu(fw_info->fw_start);
2807                 if (start > fw->size)
2808                         goto out;
2809
2810                 size = le32_to_cpu(fw_info->fw_len);
2811                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2812                         goto out;
2813
2814                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2815
2816                 pa->code = (__le32 *)(fw->data + start);
2817                 pa->size = size;
2818         } else {
2819                 if (fw->size % FW_OPCODE_SIZE)
2820                         goto out;
2821
2822                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2823
2824                 pa->code = (__le32 *)fw->data;
2825                 pa->size = fw->size / FW_OPCODE_SIZE;
2826         }
2827         version[RTL_VER_SIZE - 1] = 0;
2828
2829         rc = true;
2830 out:
2831         return rc;
2832 }
2833
2834 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2835                            struct rtl_fw_phy_action *pa)
2836 {
2837         bool rc = false;
2838         size_t index;
2839
2840         for (index = 0; index < pa->size; index++) {
2841                 u32 action = le32_to_cpu(pa->code[index]);
2842                 u32 regno = (action & 0x0fff0000) >> 16;
2843
2844                 switch(action & 0xf0000000) {
2845                 case PHY_READ:
2846                 case PHY_DATA_OR:
2847                 case PHY_DATA_AND:
2848                 case PHY_MDIO_CHG:
2849                 case PHY_CLEAR_READCOUNT:
2850                 case PHY_WRITE:
2851                 case PHY_WRITE_PREVIOUS:
2852                 case PHY_DELAY_MS:
2853                         break;
2854
2855                 case PHY_BJMPN:
2856                         if (regno > index) {
2857                                 netif_err(tp, ifup, tp->dev,
2858                                           "Out of range of firmware\n");
2859                                 goto out;
2860                         }
2861                         break;
2862                 case PHY_READCOUNT_EQ_SKIP:
2863                         if (index + 2 >= pa->size) {
2864                                 netif_err(tp, ifup, tp->dev,
2865                                           "Out of range of firmware\n");
2866                                 goto out;
2867                         }
2868                         break;
2869                 case PHY_COMP_EQ_SKIPN:
2870                 case PHY_COMP_NEQ_SKIPN:
2871                 case PHY_SKIPN:
2872                         if (index + 1 + regno >= pa->size) {
2873                                 netif_err(tp, ifup, tp->dev,
2874                                           "Out of range of firmware\n");
2875                                 goto out;
2876                         }
2877                         break;
2878
2879                 default:
2880                         netif_err(tp, ifup, tp->dev,
2881                                   "Invalid action 0x%08x\n", action);
2882                         goto out;
2883                 }
2884         }
2885         rc = true;
2886 out:
2887         return rc;
2888 }
2889
2890 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2891 {
2892         struct net_device *dev = tp->dev;
2893         int rc = -EINVAL;
2894
2895         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2896                 netif_err(tp, ifup, dev, "invalid firmware\n");
2897                 goto out;
2898         }
2899
2900         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2901                 rc = 0;
2902 out:
2903         return rc;
2904 }
2905
2906 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2907 {
2908         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2909         struct mdio_ops org, *ops = &tp->mdio_ops;
2910         u32 predata, count;
2911         size_t index;
2912
2913         predata = count = 0;
2914         org.write = ops->write;
2915         org.read = ops->read;
2916
2917         for (index = 0; index < pa->size; ) {
2918                 u32 action = le32_to_cpu(pa->code[index]);
2919                 u32 data = action & 0x0000ffff;
2920                 u32 regno = (action & 0x0fff0000) >> 16;
2921
2922                 if (!action)
2923                         break;
2924
2925                 switch(action & 0xf0000000) {
2926                 case PHY_READ:
2927                         predata = rtl_readphy(tp, regno);
2928                         count++;
2929                         index++;
2930                         break;
2931                 case PHY_DATA_OR:
2932                         predata |= data;
2933                         index++;
2934                         break;
2935                 case PHY_DATA_AND:
2936                         predata &= data;
2937                         index++;
2938                         break;
2939                 case PHY_BJMPN:
2940                         index -= regno;
2941                         break;
2942                 case PHY_MDIO_CHG:
2943                         if (data == 0) {
2944                                 ops->write = org.write;
2945                                 ops->read = org.read;
2946                         } else if (data == 1) {
2947                                 ops->write = mac_mcu_write;
2948                                 ops->read = mac_mcu_read;
2949                         }
2950
2951                         index++;
2952                         break;
2953                 case PHY_CLEAR_READCOUNT:
2954                         count = 0;
2955                         index++;
2956                         break;
2957                 case PHY_WRITE:
2958                         rtl_writephy(tp, regno, data);
2959                         index++;
2960                         break;
2961                 case PHY_READCOUNT_EQ_SKIP:
2962                         index += (count == data) ? 2 : 1;
2963                         break;
2964                 case PHY_COMP_EQ_SKIPN:
2965                         if (predata == data)
2966                                 index += regno;
2967                         index++;
2968                         break;
2969                 case PHY_COMP_NEQ_SKIPN:
2970                         if (predata != data)
2971                                 index += regno;
2972                         index++;
2973                         break;
2974                 case PHY_WRITE_PREVIOUS:
2975                         rtl_writephy(tp, regno, predata);
2976                         index++;
2977                         break;
2978                 case PHY_SKIPN:
2979                         index += regno + 1;
2980                         break;
2981                 case PHY_DELAY_MS:
2982                         mdelay(data);
2983                         index++;
2984                         break;
2985
2986                 default:
2987                         BUG();
2988                 }
2989         }
2990
2991         ops->write = org.write;
2992         ops->read = org.read;
2993 }
2994
2995 static void rtl_release_firmware(struct rtl8169_private *tp)
2996 {
2997         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2998                 release_firmware(tp->rtl_fw->fw);
2999                 kfree(tp->rtl_fw);
3000         }
3001         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3002 }
3003
3004 static void rtl_apply_firmware(struct rtl8169_private *tp)
3005 {
3006         struct rtl_fw *rtl_fw = tp->rtl_fw;
3007
3008         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
3009         if (!IS_ERR_OR_NULL(rtl_fw))
3010                 rtl_phy_write_fw(tp, rtl_fw);
3011 }
3012
3013 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
3014 {
3015         if (rtl_readphy(tp, reg) != val)
3016                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
3017         else
3018                 rtl_apply_firmware(tp);
3019 }
3020
3021 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
3022 {
3023         static const struct phy_reg phy_reg_init[] = {
3024                 { 0x1f, 0x0001 },
3025                 { 0x06, 0x006e },
3026                 { 0x08, 0x0708 },
3027                 { 0x15, 0x4000 },
3028                 { 0x18, 0x65c7 },
3029
3030                 { 0x1f, 0x0001 },
3031                 { 0x03, 0x00a1 },
3032                 { 0x02, 0x0008 },
3033                 { 0x01, 0x0120 },
3034                 { 0x00, 0x1000 },
3035                 { 0x04, 0x0800 },
3036                 { 0x04, 0x0000 },
3037
3038                 { 0x03, 0xff41 },
3039                 { 0x02, 0xdf60 },
3040                 { 0x01, 0x0140 },
3041                 { 0x00, 0x0077 },
3042                 { 0x04, 0x7800 },
3043                 { 0x04, 0x7000 },
3044
3045                 { 0x03, 0x802f },
3046                 { 0x02, 0x4f02 },
3047                 { 0x01, 0x0409 },
3048                 { 0x00, 0xf0f9 },
3049                 { 0x04, 0x9800 },
3050                 { 0x04, 0x9000 },
3051
3052                 { 0x03, 0xdf01 },
3053                 { 0x02, 0xdf20 },
3054                 { 0x01, 0xff95 },
3055                 { 0x00, 0xba00 },
3056                 { 0x04, 0xa800 },
3057                 { 0x04, 0xa000 },
3058
3059                 { 0x03, 0xff41 },
3060                 { 0x02, 0xdf20 },
3061                 { 0x01, 0x0140 },
3062                 { 0x00, 0x00bb },
3063                 { 0x04, 0xb800 },
3064                 { 0x04, 0xb000 },
3065
3066                 { 0x03, 0xdf41 },
3067                 { 0x02, 0xdc60 },
3068                 { 0x01, 0x6340 },
3069                 { 0x00, 0x007d },
3070                 { 0x04, 0xd800 },
3071                 { 0x04, 0xd000 },
3072
3073                 { 0x03, 0xdf01 },
3074                 { 0x02, 0xdf20 },
3075                 { 0x01, 0x100a },
3076                 { 0x00, 0xa0ff },
3077                 { 0x04, 0xf800 },
3078                 { 0x04, 0xf000 },
3079
3080                 { 0x1f, 0x0000 },
3081                 { 0x0b, 0x0000 },
3082                 { 0x00, 0x9200 }
3083         };
3084
3085         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3086 }
3087
3088 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
3089 {
3090         static const struct phy_reg phy_reg_init[] = {
3091                 { 0x1f, 0x0002 },
3092                 { 0x01, 0x90d0 },
3093                 { 0x1f, 0x0000 }
3094         };
3095
3096         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3097 }
3098
3099 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
3100 {
3101         struct pci_dev *pdev = tp->pci_dev;
3102
3103         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3104             (pdev->subsystem_device != 0xe000))
3105                 return;
3106
3107         rtl_writephy(tp, 0x1f, 0x0001);
3108         rtl_writephy(tp, 0x10, 0xf01b);
3109         rtl_writephy(tp, 0x1f, 0x0000);
3110 }
3111
3112 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
3113 {
3114         static const struct phy_reg phy_reg_init[] = {
3115                 { 0x1f, 0x0001 },
3116                 { 0x04, 0x0000 },
3117                 { 0x03, 0x00a1 },
3118                 { 0x02, 0x0008 },
3119                 { 0x01, 0x0120 },
3120                 { 0x00, 0x1000 },
3121                 { 0x04, 0x0800 },
3122                 { 0x04, 0x9000 },
3123                 { 0x03, 0x802f },
3124                 { 0x02, 0x4f02 },
3125                 { 0x01, 0x0409 },
3126                 { 0x00, 0xf099 },
3127                 { 0x04, 0x9800 },
3128                 { 0x04, 0xa000 },
3129                 { 0x03, 0xdf01 },
3130                 { 0x02, 0xdf20 },
3131                 { 0x01, 0xff95 },
3132                 { 0x00, 0xba00 },
3133                 { 0x04, 0xa800 },
3134                 { 0x04, 0xf000 },
3135                 { 0x03, 0xdf01 },
3136                 { 0x02, 0xdf20 },
3137                 { 0x01, 0x101a },
3138                 { 0x00, 0xa0ff },
3139                 { 0x04, 0xf800 },
3140                 { 0x04, 0x0000 },
3141                 { 0x1f, 0x0000 },
3142
3143                 { 0x1f, 0x0001 },
3144                 { 0x10, 0xf41b },
3145                 { 0x14, 0xfb54 },
3146                 { 0x18, 0xf5c7 },
3147                 { 0x1f, 0x0000 },
3148
3149                 { 0x1f, 0x0001 },
3150                 { 0x17, 0x0cc0 },
3151                 { 0x1f, 0x0000 }
3152         };
3153
3154         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3155
3156         rtl8169scd_hw_phy_config_quirk(tp);
3157 }
3158
3159 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
3160 {
3161         static const struct phy_reg phy_reg_init[] = {
3162                 { 0x1f, 0x0001 },
3163                 { 0x04, 0x0000 },
3164                 { 0x03, 0x00a1 },
3165                 { 0x02, 0x0008 },
3166                 { 0x01, 0x0120 },
3167                 { 0x00, 0x1000 },
3168                 { 0x04, 0x0800 },
3169                 { 0x04, 0x9000 },
3170                 { 0x03, 0x802f },
3171                 { 0x02, 0x4f02 },
3172                 { 0x01, 0x0409 },
3173                 { 0x00, 0xf099 },
3174                 { 0x04, 0x9800 },
3175                 { 0x04, 0xa000 },
3176                 { 0x03, 0xdf01 },
3177                 { 0x02, 0xdf20 },
3178                 { 0x01, 0xff95 },
3179                 { 0x00, 0xba00 },
3180                 { 0x04, 0xa800 },
3181                 { 0x04, 0xf000 },
3182                 { 0x03, 0xdf01 },
3183                 { 0x02, 0xdf20 },
3184                 { 0x01, 0x101a },
3185                 { 0x00, 0xa0ff },
3186                 { 0x04, 0xf800 },
3187                 { 0x04, 0x0000 },
3188                 { 0x1f, 0x0000 },
3189
3190                 { 0x1f, 0x0001 },
3191                 { 0x0b, 0x8480 },
3192                 { 0x1f, 0x0000 },
3193
3194                 { 0x1f, 0x0001 },
3195                 { 0x18, 0x67c7 },
3196                 { 0x04, 0x2000 },
3197                 { 0x03, 0x002f },
3198                 { 0x02, 0x4360 },
3199                 { 0x01, 0x0109 },
3200                 { 0x00, 0x3022 },
3201                 { 0x04, 0x2800 },
3202                 { 0x1f, 0x0000 },
3203
3204                 { 0x1f, 0x0001 },
3205                 { 0x17, 0x0cc0 },
3206                 { 0x1f, 0x0000 }
3207         };
3208
3209         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3210 }
3211
3212 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3213 {
3214         static const struct phy_reg phy_reg_init[] = {
3215                 { 0x10, 0xf41b },
3216                 { 0x1f, 0x0000 }
3217         };
3218
3219         rtl_writephy(tp, 0x1f, 0x0001);
3220         rtl_patchphy(tp, 0x16, 1 << 0);
3221
3222         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3223 }
3224
3225 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3226 {
3227         static const struct phy_reg phy_reg_init[] = {
3228                 { 0x1f, 0x0001 },
3229                 { 0x10, 0xf41b },
3230                 { 0x1f, 0x0000 }
3231         };
3232
3233         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3234 }
3235
3236 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3237 {
3238         static const struct phy_reg phy_reg_init[] = {
3239                 { 0x1f, 0x0000 },
3240                 { 0x1d, 0x0f00 },
3241                 { 0x1f, 0x0002 },
3242                 { 0x0c, 0x1ec8 },
3243                 { 0x1f, 0x0000 }
3244         };
3245
3246         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3247 }
3248
3249 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3250 {
3251         static const struct phy_reg phy_reg_init[] = {
3252                 { 0x1f, 0x0001 },
3253                 { 0x1d, 0x3d98 },
3254                 { 0x1f, 0x0000 }
3255         };
3256
3257         rtl_writephy(tp, 0x1f, 0x0000);
3258         rtl_patchphy(tp, 0x14, 1 << 5);
3259         rtl_patchphy(tp, 0x0d, 1 << 5);
3260
3261         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3262 }
3263
3264 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3265 {
3266         static const struct phy_reg phy_reg_init[] = {
3267                 { 0x1f, 0x0001 },
3268                 { 0x12, 0x2300 },
3269                 { 0x1f, 0x0002 },
3270                 { 0x00, 0x88d4 },
3271                 { 0x01, 0x82b1 },
3272                 { 0x03, 0x7002 },
3273                 { 0x08, 0x9e30 },
3274                 { 0x09, 0x01f0 },
3275                 { 0x0a, 0x5500 },
3276                 { 0x0c, 0x00c8 },
3277                 { 0x1f, 0x0003 },
3278                 { 0x12, 0xc096 },
3279                 { 0x16, 0x000a },
3280                 { 0x1f, 0x0000 },
3281                 { 0x1f, 0x0000 },
3282                 { 0x09, 0x2000 },
3283                 { 0x09, 0x0000 }
3284         };
3285
3286         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3287
3288         rtl_patchphy(tp, 0x14, 1 << 5);
3289         rtl_patchphy(tp, 0x0d, 1 << 5);
3290         rtl_writephy(tp, 0x1f, 0x0000);
3291 }
3292
3293 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3294 {
3295         static const struct phy_reg phy_reg_init[] = {
3296                 { 0x1f, 0x0001 },
3297                 { 0x12, 0x2300 },
3298                 { 0x03, 0x802f },
3299                 { 0x02, 0x4f02 },
3300                 { 0x01, 0x0409 },
3301                 { 0x00, 0xf099 },
3302                 { 0x04, 0x9800 },
3303                 { 0x04, 0x9000 },
3304                 { 0x1d, 0x3d98 },
3305                 { 0x1f, 0x0002 },
3306                 { 0x0c, 0x7eb8 },
3307                 { 0x06, 0x0761 },
3308                 { 0x1f, 0x0003 },
3309                 { 0x16, 0x0f0a },
3310                 { 0x1f, 0x0000 }
3311         };
3312
3313         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3314
3315         rtl_patchphy(tp, 0x16, 1 << 0);
3316         rtl_patchphy(tp, 0x14, 1 << 5);
3317         rtl_patchphy(tp, 0x0d, 1 << 5);
3318         rtl_writephy(tp, 0x1f, 0x0000);
3319 }
3320
3321 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3322 {
3323         static const struct phy_reg phy_reg_init[] = {
3324                 { 0x1f, 0x0001 },
3325                 { 0x12, 0x2300 },
3326                 { 0x1d, 0x3d98 },
3327                 { 0x1f, 0x0002 },
3328                 { 0x0c, 0x7eb8 },
3329                 { 0x06, 0x5461 },
3330                 { 0x1f, 0x0003 },
3331                 { 0x16, 0x0f0a },
3332                 { 0x1f, 0x0000 }
3333         };
3334
3335         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3336
3337         rtl_patchphy(tp, 0x16, 1 << 0);
3338         rtl_patchphy(tp, 0x14, 1 << 5);
3339         rtl_patchphy(tp, 0x0d, 1 << 5);
3340         rtl_writephy(tp, 0x1f, 0x0000);
3341 }
3342
3343 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3344 {
3345         rtl8168c_3_hw_phy_config(tp);
3346 }
3347
3348 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3349 {
3350         static const struct phy_reg phy_reg_init_0[] = {
3351                 /* Channel Estimation */
3352                 { 0x1f, 0x0001 },
3353                 { 0x06, 0x4064 },
3354                 { 0x07, 0x2863 },
3355                 { 0x08, 0x059c },
3356                 { 0x09, 0x26b4 },
3357                 { 0x0a, 0x6a19 },
3358                 { 0x0b, 0xdcc8 },
3359                 { 0x10, 0xf06d },
3360                 { 0x14, 0x7f68 },
3361                 { 0x18, 0x7fd9 },
3362                 { 0x1c, 0xf0ff },
3363                 { 0x1d, 0x3d9c },
3364                 { 0x1f, 0x0003 },
3365                 { 0x12, 0xf49f },
3366                 { 0x13, 0x070b },
3367                 { 0x1a, 0x05ad },
3368                 { 0x14, 0x94c0 },
3369
3370                 /*
3371                  * Tx Error Issue
3372                  * Enhance line driver power
3373                  */
3374                 { 0x1f, 0x0002 },
3375                 { 0x06, 0x5561 },
3376                 { 0x1f, 0x0005 },
3377                 { 0x05, 0x8332 },
3378                 { 0x06, 0x5561 },
3379
3380                 /*
3381                  * Can not link to 1Gbps with bad cable
3382                  * Decrease SNR threshold form 21.07dB to 19.04dB
3383                  */
3384                 { 0x1f, 0x0001 },
3385                 { 0x17, 0x0cc0 },
3386
3387                 { 0x1f, 0x0000 },
3388                 { 0x0d, 0xf880 }
3389         };
3390
3391         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3392
3393         /*
3394          * Rx Error Issue
3395          * Fine Tune Switching regulator parameter
3396          */
3397         rtl_writephy(tp, 0x1f, 0x0002);
3398         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3399         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3400
3401         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3402                 static const struct phy_reg phy_reg_init[] = {
3403                         { 0x1f, 0x0002 },
3404                         { 0x05, 0x669a },
3405                         { 0x1f, 0x0005 },
3406                         { 0x05, 0x8330 },
3407                         { 0x06, 0x669a },
3408                         { 0x1f, 0x0002 }
3409                 };
3410                 int val;
3411
3412                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3413
3414                 val = rtl_readphy(tp, 0x0d);
3415
3416                 if ((val & 0x00ff) != 0x006c) {
3417                         static const u32 set[] = {
3418                                 0x0065, 0x0066, 0x0067, 0x0068,
3419                                 0x0069, 0x006a, 0x006b, 0x006c
3420                         };
3421                         int i;
3422
3423                         rtl_writephy(tp, 0x1f, 0x0002);
3424
3425                         val &= 0xff00;
3426                         for (i = 0; i < ARRAY_SIZE(set); i++)
3427                                 rtl_writephy(tp, 0x0d, val | set[i]);
3428                 }
3429         } else {
3430                 static const struct phy_reg phy_reg_init[] = {
3431                         { 0x1f, 0x0002 },
3432                         { 0x05, 0x6662 },
3433                         { 0x1f, 0x0005 },
3434                         { 0x05, 0x8330 },
3435                         { 0x06, 0x6662 }
3436                 };
3437
3438                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3439         }
3440
3441         /* RSET couple improve */
3442         rtl_writephy(tp, 0x1f, 0x0002);
3443         rtl_patchphy(tp, 0x0d, 0x0300);
3444         rtl_patchphy(tp, 0x0f, 0x0010);
3445
3446         /* Fine tune PLL performance */
3447         rtl_writephy(tp, 0x1f, 0x0002);
3448         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3449         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3450
3451         rtl_writephy(tp, 0x1f, 0x0005);
3452         rtl_writephy(tp, 0x05, 0x001b);
3453
3454         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3455
3456         rtl_writephy(tp, 0x1f, 0x0000);
3457 }
3458
3459 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3460 {
3461         static const struct phy_reg phy_reg_init_0[] = {
3462                 /* Channel Estimation */
3463                 { 0x1f, 0x0001 },
3464                 { 0x06, 0x4064 },
3465                 { 0x07, 0x2863 },
3466                 { 0x08, 0x059c },
3467                 { 0x09, 0x26b4 },
3468                 { 0x0a, 0x6a19 },
3469                 { 0x0b, 0xdcc8 },
3470                 { 0x10, 0xf06d },
3471                 { 0x14, 0x7f68 },
3472                 { 0x18, 0x7fd9 },
3473                 { 0x1c, 0xf0ff },
3474                 { 0x1d, 0x3d9c },
3475                 { 0x1f, 0x0003 },
3476                 { 0x12, 0xf49f },
3477                 { 0x13, 0x070b },
3478                 { 0x1a, 0x05ad },
3479                 { 0x14, 0x94c0 },
3480
3481                 /*
3482                  * Tx Error Issue
3483                  * Enhance line driver power
3484                  */
3485                 { 0x1f, 0x0002 },
3486                 { 0x06, 0x5561 },
3487                 { 0x1f, 0x0005 },
3488                 { 0x05, 0x8332 },
3489                 { 0x06, 0x5561 },
3490
3491                 /*
3492                  * Can not link to 1Gbps with bad cable
3493                  * Decrease SNR threshold form 21.07dB to 19.04dB
3494                  */
3495                 { 0x1f, 0x0001 },
3496                 { 0x17, 0x0cc0 },
3497
3498                 { 0x1f, 0x0000 },
3499                 { 0x0d, 0xf880 }
3500         };
3501
3502         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3503
3504         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3505                 static const struct phy_reg phy_reg_init[] = {
3506                         { 0x1f, 0x0002 },
3507                         { 0x05, 0x669a },
3508                         { 0x1f, 0x0005 },
3509                         { 0x05, 0x8330 },
3510                         { 0x06, 0x669a },
3511
3512                         { 0x1f, 0x0002 }
3513                 };
3514                 int val;
3515
3516                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3517
3518                 val = rtl_readphy(tp, 0x0d);
3519                 if ((val & 0x00ff) != 0x006c) {
3520                         static const u32 set[] = {
3521                                 0x0065, 0x0066, 0x0067, 0x0068,
3522                                 0x0069, 0x006a, 0x006b, 0x006c
3523                         };
3524                         int i;
3525
3526                         rtl_writephy(tp, 0x1f, 0x0002);
3527
3528                         val &= 0xff00;
3529                         for (i = 0; i < ARRAY_SIZE(set); i++)
3530                                 rtl_writephy(tp, 0x0d, val | set[i]);
3531                 }
3532         } else {
3533                 static const struct phy_reg phy_reg_init[] = {
3534                         { 0x1f, 0x0002 },
3535                         { 0x05, 0x2642 },
3536                         { 0x1f, 0x0005 },
3537                         { 0x05, 0x8330 },
3538                         { 0x06, 0x2642 }
3539                 };
3540
3541                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3542         }
3543
3544         /* Fine tune PLL performance */
3545         rtl_writephy(tp, 0x1f, 0x0002);
3546         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3547         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3548
3549         /* Switching regulator Slew rate */
3550         rtl_writephy(tp, 0x1f, 0x0002);
3551         rtl_patchphy(tp, 0x0f, 0x0017);
3552
3553         rtl_writephy(tp, 0x1f, 0x0005);
3554         rtl_writephy(tp, 0x05, 0x001b);
3555
3556         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3557
3558         rtl_writephy(tp, 0x1f, 0x0000);
3559 }
3560
3561 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3562 {
3563         static const struct phy_reg phy_reg_init[] = {
3564                 { 0x1f, 0x0002 },
3565                 { 0x10, 0x0008 },
3566                 { 0x0d, 0x006c },
3567
3568                 { 0x1f, 0x0000 },
3569                 { 0x0d, 0xf880 },
3570
3571                 { 0x1f, 0x0001 },
3572                 { 0x17, 0x0cc0 },
3573
3574                 { 0x1f, 0x0001 },
3575                 { 0x0b, 0xa4d8 },
3576                 { 0x09, 0x281c },
3577                 { 0x07, 0x2883 },
3578                 { 0x0a, 0x6b35 },
3579                 { 0x1d, 0x3da4 },
3580                 { 0x1c, 0xeffd },
3581                 { 0x14, 0x7f52 },
3582                 { 0x18, 0x7fc6 },
3583                 { 0x08, 0x0601 },
3584                 { 0x06, 0x4063 },
3585                 { 0x10, 0xf074 },
3586                 { 0x1f, 0x0003 },
3587                 { 0x13, 0x0789 },
3588                 { 0x12, 0xf4bd },
3589                 { 0x1a, 0x04fd },
3590                 { 0x14, 0x84b0 },
3591                 { 0x1f, 0x0000 },
3592                 { 0x00, 0x9200 },
3593
3594                 { 0x1f, 0x0005 },
3595                 { 0x01, 0x0340 },
3596                 { 0x1f, 0x0001 },
3597                 { 0x04, 0x4000 },
3598                 { 0x03, 0x1d21 },
3599                 { 0x02, 0x0c32 },
3600                 { 0x01, 0x0200 },
3601                 { 0x00, 0x5554 },
3602                 { 0x04, 0x4800 },
3603                 { 0x04, 0x4000 },
3604                 { 0x04, 0xf000 },
3605                 { 0x03, 0xdf01 },
3606                 { 0x02, 0xdf20 },
3607                 { 0x01, 0x101a },
3608                 { 0x00, 0xa0ff },
3609                 { 0x04, 0xf800 },
3610                 { 0x04, 0xf000 },
3611                 { 0x1f, 0x0000 },
3612
3613                 { 0x1f, 0x0007 },
3614                 { 0x1e, 0x0023 },
3615                 { 0x16, 0x0000 },
3616                 { 0x1f, 0x0000 }
3617         };
3618
3619         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3620 }
3621
3622 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3623 {
3624         static const struct phy_reg phy_reg_init[] = {
3625                 { 0x1f, 0x0001 },
3626                 { 0x17, 0x0cc0 },
3627
3628                 { 0x1f, 0x0007 },
3629                 { 0x1e, 0x002d },
3630                 { 0x18, 0x0040 },
3631                 { 0x1f, 0x0000 }
3632         };
3633
3634         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3635         rtl_patchphy(tp, 0x0d, 1 << 5);
3636 }
3637
3638 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3639 {
3640         static const struct phy_reg phy_reg_init[] = {
3641                 /* Enable Delay cap */
3642                 { 0x1f, 0x0005 },
3643                 { 0x05, 0x8b80 },
3644                 { 0x06, 0xc896 },
3645                 { 0x1f, 0x0000 },
3646
3647                 /* Channel estimation fine tune */
3648                 { 0x1f, 0x0001 },
3649                 { 0x0b, 0x6c20 },
3650                 { 0x07, 0x2872 },
3651                 { 0x1c, 0xefff },
3652                 { 0x1f, 0x0003 },
3653                 { 0x14, 0x6420 },
3654                 { 0x1f, 0x0000 },
3655
3656                 /* Update PFM & 10M TX idle timer */
3657                 { 0x1f, 0x0007 },
3658                 { 0x1e, 0x002f },
3659                 { 0x15, 0x1919 },
3660                 { 0x1f, 0x0000 },
3661
3662                 { 0x1f, 0x0007 },
3663                 { 0x1e, 0x00ac },
3664                 { 0x18, 0x0006 },
3665                 { 0x1f, 0x0000 }
3666         };
3667
3668         rtl_apply_firmware(tp);
3669
3670         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3671
3672         /* DCO enable for 10M IDLE Power */
3673         rtl_writephy(tp, 0x1f, 0x0007);
3674         rtl_writephy(tp, 0x1e, 0x0023);
3675         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3676         rtl_writephy(tp, 0x1f, 0x0000);
3677
3678         /* For impedance matching */
3679         rtl_writephy(tp, 0x1f, 0x0002);
3680         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3681         rtl_writephy(tp, 0x1f, 0x0000);
3682
3683         /* PHY auto speed down */
3684         rtl_writephy(tp, 0x1f, 0x0007);
3685         rtl_writephy(tp, 0x1e, 0x002d);
3686         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3687         rtl_writephy(tp, 0x1f, 0x0000);
3688         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3689
3690         rtl_writephy(tp, 0x1f, 0x0005);
3691         rtl_writephy(tp, 0x05, 0x8b86);
3692         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3693         rtl_writephy(tp, 0x1f, 0x0000);
3694
3695         rtl_writephy(tp, 0x1f, 0x0005);
3696         rtl_writephy(tp, 0x05, 0x8b85);
3697         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3698         rtl_writephy(tp, 0x1f, 0x0007);
3699         rtl_writephy(tp, 0x1e, 0x0020);
3700         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3701         rtl_writephy(tp, 0x1f, 0x0006);
3702         rtl_writephy(tp, 0x00, 0x5a00);
3703         rtl_writephy(tp, 0x1f, 0x0000);
3704         rtl_writephy(tp, 0x0d, 0x0007);
3705         rtl_writephy(tp, 0x0e, 0x003c);
3706         rtl_writephy(tp, 0x0d, 0x4007);
3707         rtl_writephy(tp, 0x0e, 0x0000);
3708         rtl_writephy(tp, 0x0d, 0x0000);
3709 }
3710
3711 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3712 {
3713         const u16 w[] = {
3714                 addr[0] | (addr[1] << 8),
3715                 addr[2] | (addr[3] << 8),
3716                 addr[4] | (addr[5] << 8)
3717         };
3718         const struct exgmac_reg e[] = {
3719                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3720                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3721                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3722                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3723         };
3724
3725         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3726 }
3727
3728 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3729 {
3730         static const struct phy_reg phy_reg_init[] = {
3731                 /* Enable Delay cap */
3732                 { 0x1f, 0x0004 },
3733                 { 0x1f, 0x0007 },
3734                 { 0x1e, 0x00ac },
3735                 { 0x18, 0x0006 },
3736                 { 0x1f, 0x0002 },
3737                 { 0x1f, 0x0000 },
3738                 { 0x1f, 0x0000 },
3739
3740                 /* Channel estimation fine tune */
3741                 { 0x1f, 0x0003 },
3742                 { 0x09, 0xa20f },
3743                 { 0x1f, 0x0000 },
3744                 { 0x1f, 0x0000 },
3745
3746                 /* Green Setting */
3747                 { 0x1f, 0x0005 },
3748                 { 0x05, 0x8b5b },
3749                 { 0x06, 0x9222 },
3750                 { 0x05, 0x8b6d },
3751                 { 0x06, 0x8000 },
3752                 { 0x05, 0x8b76 },
3753                 { 0x06, 0x8000 },
3754                 { 0x1f, 0x0000 }
3755         };
3756
3757         rtl_apply_firmware(tp);
3758
3759         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3760
3761         /* For 4-corner performance improve */
3762         rtl_writephy(tp, 0x1f, 0x0005);
3763         rtl_writephy(tp, 0x05, 0x8b80);
3764         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3765         rtl_writephy(tp, 0x1f, 0x0000);
3766
3767         /* PHY auto speed down */
3768         rtl_writephy(tp, 0x1f, 0x0004);
3769         rtl_writephy(tp, 0x1f, 0x0007);
3770         rtl_writephy(tp, 0x1e, 0x002d);
3771         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3772         rtl_writephy(tp, 0x1f, 0x0002);
3773         rtl_writephy(tp, 0x1f, 0x0000);
3774         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3775
3776         /* improve 10M EEE waveform */
3777         rtl_writephy(tp, 0x1f, 0x0005);
3778         rtl_writephy(tp, 0x05, 0x8b86);
3779         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3780         rtl_writephy(tp, 0x1f, 0x0000);
3781
3782         /* Improve 2-pair detection performance */
3783         rtl_writephy(tp, 0x1f, 0x0005);
3784         rtl_writephy(tp, 0x05, 0x8b85);
3785         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3786         rtl_writephy(tp, 0x1f, 0x0000);
3787
3788         /* EEE setting */
3789         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3790         rtl_writephy(tp, 0x1f, 0x0005);
3791         rtl_writephy(tp, 0x05, 0x8b85);
3792         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3793         rtl_writephy(tp, 0x1f, 0x0004);
3794         rtl_writephy(tp, 0x1f, 0x0007);
3795         rtl_writephy(tp, 0x1e, 0x0020);
3796         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3797         rtl_writephy(tp, 0x1f, 0x0002);
3798         rtl_writephy(tp, 0x1f, 0x0000);
3799         rtl_writephy(tp, 0x0d, 0x0007);
3800         rtl_writephy(tp, 0x0e, 0x003c);
3801         rtl_writephy(tp, 0x0d, 0x4007);
3802         rtl_writephy(tp, 0x0e, 0x0006);
3803         rtl_writephy(tp, 0x0d, 0x0000);
3804
3805         /* Green feature */
3806         rtl_writephy(tp, 0x1f, 0x0003);
3807         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3808         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3809         rtl_writephy(tp, 0x1f, 0x0000);
3810         rtl_writephy(tp, 0x1f, 0x0005);
3811         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3812         rtl_writephy(tp, 0x1f, 0x0000);
3813         /* soft-reset phy */
3814         rtl_writephy(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
3815
3816         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3817         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3818 }
3819
3820 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3821 {
3822         /* For 4-corner performance improve */
3823         rtl_writephy(tp, 0x1f, 0x0005);
3824         rtl_writephy(tp, 0x05, 0x8b80);
3825         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3826         rtl_writephy(tp, 0x1f, 0x0000);
3827
3828         /* PHY auto speed down */
3829         rtl_writephy(tp, 0x1f, 0x0007);
3830         rtl_writephy(tp, 0x1e, 0x002d);
3831         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3832         rtl_writephy(tp, 0x1f, 0x0000);
3833         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3834
3835         /* Improve 10M EEE waveform */
3836         rtl_writephy(tp, 0x1f, 0x0005);
3837         rtl_writephy(tp, 0x05, 0x8b86);
3838         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3839         rtl_writephy(tp, 0x1f, 0x0000);
3840 }
3841
3842 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3843 {
3844         static const struct phy_reg phy_reg_init[] = {
3845                 /* Channel estimation fine tune */
3846                 { 0x1f, 0x0003 },
3847                 { 0x09, 0xa20f },
3848                 { 0x1f, 0x0000 },
3849
3850                 /* Modify green table for giga & fnet */
3851                 { 0x1f, 0x0005 },
3852                 { 0x05, 0x8b55 },
3853                 { 0x06, 0x0000 },
3854                 { 0x05, 0x8b5e },
3855                 { 0x06, 0x0000 },
3856                 { 0x05, 0x8b67 },
3857                 { 0x06, 0x0000 },
3858                 { 0x05, 0x8b70 },
3859                 { 0x06, 0x0000 },
3860                 { 0x1f, 0x0000 },
3861                 { 0x1f, 0x0007 },
3862                 { 0x1e, 0x0078 },
3863                 { 0x17, 0x0000 },
3864                 { 0x19, 0x00fb },
3865                 { 0x1f, 0x0000 },
3866
3867                 /* Modify green table for 10M */
3868                 { 0x1f, 0x0005 },
3869                 { 0x05, 0x8b79 },
3870                 { 0x06, 0xaa00 },
3871                 { 0x1f, 0x0000 },
3872
3873                 /* Disable hiimpedance detection (RTCT) */
3874                 { 0x1f, 0x0003 },
3875                 { 0x01, 0x328a },
3876                 { 0x1f, 0x0000 }
3877         };
3878
3879         rtl_apply_firmware(tp);
3880
3881         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3882
3883         rtl8168f_hw_phy_config(tp);
3884
3885         /* Improve 2-pair detection performance */
3886         rtl_writephy(tp, 0x1f, 0x0005);
3887         rtl_writephy(tp, 0x05, 0x8b85);
3888         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3889         rtl_writephy(tp, 0x1f, 0x0000);
3890 }
3891
3892 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3893 {
3894         rtl_apply_firmware(tp);
3895
3896         rtl8168f_hw_phy_config(tp);
3897 }
3898
3899 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3900 {
3901         static const struct phy_reg phy_reg_init[] = {
3902                 /* Channel estimation fine tune */
3903                 { 0x1f, 0x0003 },
3904                 { 0x09, 0xa20f },
3905                 { 0x1f, 0x0000 },
3906
3907                 /* Modify green table for giga & fnet */
3908                 { 0x1f, 0x0005 },
3909                 { 0x05, 0x8b55 },
3910                 { 0x06, 0x0000 },
3911                 { 0x05, 0x8b5e },
3912                 { 0x06, 0x0000 },
3913                 { 0x05, 0x8b67 },
3914                 { 0x06, 0x0000 },
3915                 { 0x05, 0x8b70 },
3916                 { 0x06, 0x0000 },
3917                 { 0x1f, 0x0000 },
3918                 { 0x1f, 0x0007 },
3919                 { 0x1e, 0x0078 },
3920                 { 0x17, 0x0000 },
3921                 { 0x19, 0x00aa },
3922                 { 0x1f, 0x0000 },
3923
3924                 /* Modify green table for 10M */
3925                 { 0x1f, 0x0005 },
3926                 { 0x05, 0x8b79 },
3927                 { 0x06, 0xaa00 },
3928                 { 0x1f, 0x0000 },
3929
3930                 /* Disable hiimpedance detection (RTCT) */
3931                 { 0x1f, 0x0003 },
3932                 { 0x01, 0x328a },
3933                 { 0x1f, 0x0000 }
3934         };
3935
3936
3937         rtl_apply_firmware(tp);
3938
3939         rtl8168f_hw_phy_config(tp);
3940
3941         /* Improve 2-pair detection performance */
3942         rtl_writephy(tp, 0x1f, 0x0005);
3943         rtl_writephy(tp, 0x05, 0x8b85);
3944         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3945         rtl_writephy(tp, 0x1f, 0x0000);
3946
3947         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3948
3949         /* Modify green table for giga */
3950         rtl_writephy(tp, 0x1f, 0x0005);
3951         rtl_writephy(tp, 0x05, 0x8b54);
3952         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3953         rtl_writephy(tp, 0x05, 0x8b5d);
3954         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3955         rtl_writephy(tp, 0x05, 0x8a7c);
3956         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3957         rtl_writephy(tp, 0x05, 0x8a7f);
3958         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3959         rtl_writephy(tp, 0x05, 0x8a82);
3960         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3961         rtl_writephy(tp, 0x05, 0x8a85);
3962         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3963         rtl_writephy(tp, 0x05, 0x8a88);
3964         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3965         rtl_writephy(tp, 0x1f, 0x0000);
3966
3967         /* uc same-seed solution */
3968         rtl_writephy(tp, 0x1f, 0x0005);
3969         rtl_writephy(tp, 0x05, 0x8b85);
3970         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3971         rtl_writephy(tp, 0x1f, 0x0000);
3972
3973         /* eee setting */
3974         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3975         rtl_writephy(tp, 0x1f, 0x0005);
3976         rtl_writephy(tp, 0x05, 0x8b85);
3977         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3978         rtl_writephy(tp, 0x1f, 0x0004);
3979         rtl_writephy(tp, 0x1f, 0x0007);
3980         rtl_writephy(tp, 0x1e, 0x0020);
3981         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3982         rtl_writephy(tp, 0x1f, 0x0000);
3983         rtl_writephy(tp, 0x0d, 0x0007);
3984         rtl_writephy(tp, 0x0e, 0x003c);
3985         rtl_writephy(tp, 0x0d, 0x4007);
3986         rtl_writephy(tp, 0x0e, 0x0000);
3987         rtl_writephy(tp, 0x0d, 0x0000);
3988
3989         /* Green feature */
3990         rtl_writephy(tp, 0x1f, 0x0003);
3991         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3992         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3993         rtl_writephy(tp, 0x1f, 0x0000);
3994 }
3995
3996 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3997 {
3998         rtl_apply_firmware(tp);
3999
4000         rtl_writephy(tp, 0x1f, 0x0a46);
4001         if (rtl_readphy(tp, 0x10) & 0x0100) {
4002                 rtl_writephy(tp, 0x1f, 0x0bcc);
4003                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
4004         } else {
4005                 rtl_writephy(tp, 0x1f, 0x0bcc);
4006                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
4007         }
4008
4009         rtl_writephy(tp, 0x1f, 0x0a46);
4010         if (rtl_readphy(tp, 0x13) & 0x0100) {
4011                 rtl_writephy(tp, 0x1f, 0x0c41);
4012                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
4013         } else {
4014                 rtl_writephy(tp, 0x1f, 0x0c41);
4015                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
4016         }
4017
4018         /* Enable PHY auto speed down */
4019         rtl_writephy(tp, 0x1f, 0x0a44);
4020         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4021
4022         rtl_writephy(tp, 0x1f, 0x0bcc);
4023         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
4024         rtl_writephy(tp, 0x1f, 0x0a44);
4025         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4026         rtl_writephy(tp, 0x1f, 0x0a43);
4027         rtl_writephy(tp, 0x13, 0x8084);
4028         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4029         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4030
4031         /* EEE auto-fallback function */
4032         rtl_writephy(tp, 0x1f, 0x0a4b);
4033         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4034
4035         /* Enable UC LPF tune function */
4036         rtl_writephy(tp, 0x1f, 0x0a43);
4037         rtl_writephy(tp, 0x13, 0x8012);
4038         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4039
4040         rtl_writephy(tp, 0x1f, 0x0c42);
4041         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4042
4043         /* Improve SWR Efficiency */
4044         rtl_writephy(tp, 0x1f, 0x0bcd);
4045         rtl_writephy(tp, 0x14, 0x5065);
4046         rtl_writephy(tp, 0x14, 0xd065);
4047         rtl_writephy(tp, 0x1f, 0x0bc8);
4048         rtl_writephy(tp, 0x11, 0x5655);
4049         rtl_writephy(tp, 0x1f, 0x0bcd);
4050         rtl_writephy(tp, 0x14, 0x1065);
4051         rtl_writephy(tp, 0x14, 0x9065);
4052         rtl_writephy(tp, 0x14, 0x1065);
4053
4054         /* Check ALDPS bit, disable it if enabled */
4055         rtl_writephy(tp, 0x1f, 0x0a43);
4056         if (rtl_readphy(tp, 0x10) & 0x0004)
4057                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4058
4059         rtl_writephy(tp, 0x1f, 0x0000);
4060 }
4061
4062 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
4063 {
4064         rtl_apply_firmware(tp);
4065 }
4066
4067 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
4068 {
4069         u16 dout_tapbin;
4070         u32 data;
4071
4072         rtl_apply_firmware(tp);
4073
4074         /* CHN EST parameters adjust - giga master */
4075         rtl_writephy(tp, 0x1f, 0x0a43);
4076         rtl_writephy(tp, 0x13, 0x809b);
4077         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
4078         rtl_writephy(tp, 0x13, 0x80a2);
4079         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
4080         rtl_writephy(tp, 0x13, 0x80a4);
4081         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
4082         rtl_writephy(tp, 0x13, 0x809c);
4083         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
4084         rtl_writephy(tp, 0x1f, 0x0000);
4085
4086         /* CHN EST parameters adjust - giga slave */
4087         rtl_writephy(tp, 0x1f, 0x0a43);
4088         rtl_writephy(tp, 0x13, 0x80ad);
4089         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
4090         rtl_writephy(tp, 0x13, 0x80b4);
4091         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
4092         rtl_writephy(tp, 0x13, 0x80ac);
4093         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
4094         rtl_writephy(tp, 0x1f, 0x0000);
4095
4096         /* CHN EST parameters adjust - fnet */
4097         rtl_writephy(tp, 0x1f, 0x0a43);
4098         rtl_writephy(tp, 0x13, 0x808e);
4099         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
4100         rtl_writephy(tp, 0x13, 0x8090);
4101         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
4102         rtl_writephy(tp, 0x13, 0x8092);
4103         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
4104         rtl_writephy(tp, 0x1f, 0x0000);
4105
4106         /* enable R-tune & PGA-retune function */
4107         dout_tapbin = 0;
4108         rtl_writephy(tp, 0x1f, 0x0a46);
4109         data = rtl_readphy(tp, 0x13);
4110         data &= 3;
4111         data <<= 2;
4112         dout_tapbin |= data;
4113         data = rtl_readphy(tp, 0x12);
4114         data &= 0xc000;
4115         data >>= 14;
4116         dout_tapbin |= data;
4117         dout_tapbin = ~(dout_tapbin^0x08);
4118         dout_tapbin <<= 12;
4119         dout_tapbin &= 0xf000;
4120         rtl_writephy(tp, 0x1f, 0x0a43);
4121         rtl_writephy(tp, 0x13, 0x827a);
4122         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4123         rtl_writephy(tp, 0x13, 0x827b);
4124         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4125         rtl_writephy(tp, 0x13, 0x827c);
4126         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4127         rtl_writephy(tp, 0x13, 0x827d);
4128         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4129
4130         rtl_writephy(tp, 0x1f, 0x0a43);
4131         rtl_writephy(tp, 0x13, 0x0811);
4132         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4133         rtl_writephy(tp, 0x1f, 0x0a42);
4134         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4135         rtl_writephy(tp, 0x1f, 0x0000);
4136
4137         /* enable GPHY 10M */
4138         rtl_writephy(tp, 0x1f, 0x0a44);
4139         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4140         rtl_writephy(tp, 0x1f, 0x0000);
4141
4142         /* SAR ADC performance */
4143         rtl_writephy(tp, 0x1f, 0x0bca);
4144         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
4145         rtl_writephy(tp, 0x1f, 0x0000);
4146
4147         rtl_writephy(tp, 0x1f, 0x0a43);
4148         rtl_writephy(tp, 0x13, 0x803f);
4149         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4150         rtl_writephy(tp, 0x13, 0x8047);
4151         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4152         rtl_writephy(tp, 0x13, 0x804f);
4153         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4154         rtl_writephy(tp, 0x13, 0x8057);
4155         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4156         rtl_writephy(tp, 0x13, 0x805f);
4157         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4158         rtl_writephy(tp, 0x13, 0x8067);
4159         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4160         rtl_writephy(tp, 0x13, 0x806f);
4161         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4162         rtl_writephy(tp, 0x1f, 0x0000);
4163
4164         /* disable phy pfm mode */
4165         rtl_writephy(tp, 0x1f, 0x0a44);
4166         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4167         rtl_writephy(tp, 0x1f, 0x0000);
4168
4169         /* Check ALDPS bit, disable it if enabled */
4170         rtl_writephy(tp, 0x1f, 0x0a43);
4171         if (rtl_readphy(tp, 0x10) & 0x0004)
4172                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4173
4174         rtl_writephy(tp, 0x1f, 0x0000);
4175 }
4176
4177 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4178 {
4179         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4180         u16 rlen;
4181         u32 data;
4182
4183         rtl_apply_firmware(tp);
4184
4185         /* CHIN EST parameter update */
4186         rtl_writephy(tp, 0x1f, 0x0a43);
4187         rtl_writephy(tp, 0x13, 0x808a);
4188         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
4189         rtl_writephy(tp, 0x1f, 0x0000);
4190
4191         /* enable R-tune & PGA-retune function */
4192         rtl_writephy(tp, 0x1f, 0x0a43);
4193         rtl_writephy(tp, 0x13, 0x0811);
4194         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4195         rtl_writephy(tp, 0x1f, 0x0a42);
4196         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4197         rtl_writephy(tp, 0x1f, 0x0000);
4198
4199         /* enable GPHY 10M */
4200         rtl_writephy(tp, 0x1f, 0x0a44);
4201         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4202         rtl_writephy(tp, 0x1f, 0x0000);
4203
4204         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4205         data = r8168_mac_ocp_read(tp, 0xdd02);
4206         ioffset_p3 = ((data & 0x80)>>7);
4207         ioffset_p3 <<= 3;
4208
4209         data = r8168_mac_ocp_read(tp, 0xdd00);
4210         ioffset_p3 |= ((data & (0xe000))>>13);
4211         ioffset_p2 = ((data & (0x1e00))>>9);
4212         ioffset_p1 = ((data & (0x01e0))>>5);
4213         ioffset_p0 = ((data & 0x0010)>>4);
4214         ioffset_p0 <<= 3;
4215         ioffset_p0 |= (data & (0x07));
4216         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4217
4218         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
4219             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
4220                 rtl_writephy(tp, 0x1f, 0x0bcf);
4221                 rtl_writephy(tp, 0x16, data);
4222                 rtl_writephy(tp, 0x1f, 0x0000);
4223         }
4224
4225         /* Modify rlen (TX LPF corner frequency) level */
4226         rtl_writephy(tp, 0x1f, 0x0bcd);
4227         data = rtl_readphy(tp, 0x16);
4228         data &= 0x000f;
4229         rlen = 0;
4230         if (data > 3)
4231                 rlen = data - 3;
4232         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4233         rtl_writephy(tp, 0x17, data);
4234         rtl_writephy(tp, 0x1f, 0x0bcd);
4235         rtl_writephy(tp, 0x1f, 0x0000);
4236
4237         /* disable phy pfm mode */
4238         rtl_writephy(tp, 0x1f, 0x0a44);
4239         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4240         rtl_writephy(tp, 0x1f, 0x0000);
4241
4242         /* Check ALDPS bit, disable it if enabled */
4243         rtl_writephy(tp, 0x1f, 0x0a43);
4244         if (rtl_readphy(tp, 0x10) & 0x0004)
4245                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4246
4247         rtl_writephy(tp, 0x1f, 0x0000);
4248 }
4249
4250 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4251 {
4252         /* Enable PHY auto speed down */
4253         rtl_writephy(tp, 0x1f, 0x0a44);
4254         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4255         rtl_writephy(tp, 0x1f, 0x0000);
4256
4257         /* patch 10M & ALDPS */
4258         rtl_writephy(tp, 0x1f, 0x0bcc);
4259         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4260         rtl_writephy(tp, 0x1f, 0x0a44);
4261         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4262         rtl_writephy(tp, 0x1f, 0x0a43);
4263         rtl_writephy(tp, 0x13, 0x8084);
4264         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4265         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4266         rtl_writephy(tp, 0x1f, 0x0000);
4267
4268         /* Enable EEE auto-fallback function */
4269         rtl_writephy(tp, 0x1f, 0x0a4b);
4270         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4271         rtl_writephy(tp, 0x1f, 0x0000);
4272
4273         /* Enable UC LPF tune function */
4274         rtl_writephy(tp, 0x1f, 0x0a43);
4275         rtl_writephy(tp, 0x13, 0x8012);
4276         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4277         rtl_writephy(tp, 0x1f, 0x0000);
4278
4279         /* set rg_sel_sdm_rate */
4280         rtl_writephy(tp, 0x1f, 0x0c42);
4281         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4282         rtl_writephy(tp, 0x1f, 0x0000);
4283
4284         /* Check ALDPS bit, disable it if enabled */
4285         rtl_writephy(tp, 0x1f, 0x0a43);
4286         if (rtl_readphy(tp, 0x10) & 0x0004)
4287                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4288
4289         rtl_writephy(tp, 0x1f, 0x0000);
4290 }
4291
4292 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4293 {
4294         /* patch 10M & ALDPS */
4295         rtl_writephy(tp, 0x1f, 0x0bcc);
4296         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4297         rtl_writephy(tp, 0x1f, 0x0a44);
4298         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4299         rtl_writephy(tp, 0x1f, 0x0a43);
4300         rtl_writephy(tp, 0x13, 0x8084);
4301         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4302         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4303         rtl_writephy(tp, 0x1f, 0x0000);
4304
4305         /* Enable UC LPF tune function */
4306         rtl_writephy(tp, 0x1f, 0x0a43);
4307         rtl_writephy(tp, 0x13, 0x8012);
4308         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4309         rtl_writephy(tp, 0x1f, 0x0000);
4310
4311         /* Set rg_sel_sdm_rate */
4312         rtl_writephy(tp, 0x1f, 0x0c42);
4313         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4314         rtl_writephy(tp, 0x1f, 0x0000);
4315
4316         /* Channel estimation parameters */
4317         rtl_writephy(tp, 0x1f, 0x0a43);
4318         rtl_writephy(tp, 0x13, 0x80f3);
4319         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4320         rtl_writephy(tp, 0x13, 0x80f0);
4321         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4322         rtl_writephy(tp, 0x13, 0x80ef);
4323         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4324         rtl_writephy(tp, 0x13, 0x80f6);
4325         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4326         rtl_writephy(tp, 0x13, 0x80ec);
4327         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4328         rtl_writephy(tp, 0x13, 0x80ed);
4329         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4330         rtl_writephy(tp, 0x13, 0x80f2);
4331         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4332         rtl_writephy(tp, 0x13, 0x80f4);
4333         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4334         rtl_writephy(tp, 0x1f, 0x0a43);
4335         rtl_writephy(tp, 0x13, 0x8110);
4336         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4337         rtl_writephy(tp, 0x13, 0x810f);
4338         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4339         rtl_writephy(tp, 0x13, 0x8111);
4340         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4341         rtl_writephy(tp, 0x13, 0x8113);
4342         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4343         rtl_writephy(tp, 0x13, 0x8115);
4344         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4345         rtl_writephy(tp, 0x13, 0x810e);
4346         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4347         rtl_writephy(tp, 0x13, 0x810c);
4348         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4349         rtl_writephy(tp, 0x13, 0x810b);
4350         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4351         rtl_writephy(tp, 0x1f, 0x0a43);
4352         rtl_writephy(tp, 0x13, 0x80d1);
4353         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4354         rtl_writephy(tp, 0x13, 0x80cd);
4355         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4356         rtl_writephy(tp, 0x13, 0x80d3);
4357         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4358         rtl_writephy(tp, 0x13, 0x80d5);
4359         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4360         rtl_writephy(tp, 0x13, 0x80d7);
4361         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4362
4363         /* Force PWM-mode */
4364         rtl_writephy(tp, 0x1f, 0x0bcd);
4365         rtl_writephy(tp, 0x14, 0x5065);
4366         rtl_writephy(tp, 0x14, 0xd065);
4367         rtl_writephy(tp, 0x1f, 0x0bc8);
4368         rtl_writephy(tp, 0x12, 0x00ed);
4369         rtl_writephy(tp, 0x1f, 0x0bcd);
4370         rtl_writephy(tp, 0x14, 0x1065);
4371         rtl_writephy(tp, 0x14, 0x9065);
4372         rtl_writephy(tp, 0x14, 0x1065);
4373         rtl_writephy(tp, 0x1f, 0x0000);
4374
4375         /* Check ALDPS bit, disable it if enabled */
4376         rtl_writephy(tp, 0x1f, 0x0a43);
4377         if (rtl_readphy(tp, 0x10) & 0x0004)
4378                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4379
4380         rtl_writephy(tp, 0x1f, 0x0000);
4381 }
4382
4383 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4384 {
4385         static const struct phy_reg phy_reg_init[] = {
4386                 { 0x1f, 0x0003 },
4387                 { 0x08, 0x441d },
4388                 { 0x01, 0x9100 },
4389                 { 0x1f, 0x0000 }
4390         };
4391
4392         rtl_writephy(tp, 0x1f, 0x0000);
4393         rtl_patchphy(tp, 0x11, 1 << 12);
4394         rtl_patchphy(tp, 0x19, 1 << 13);
4395         rtl_patchphy(tp, 0x10, 1 << 15);
4396
4397         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4398 }
4399
4400 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4401 {
4402         static const struct phy_reg phy_reg_init[] = {
4403                 { 0x1f, 0x0005 },
4404                 { 0x1a, 0x0000 },
4405                 { 0x1f, 0x0000 },
4406
4407                 { 0x1f, 0x0004 },
4408                 { 0x1c, 0x0000 },
4409                 { 0x1f, 0x0000 },
4410
4411                 { 0x1f, 0x0001 },
4412                 { 0x15, 0x7701 },
4413                 { 0x1f, 0x0000 }
4414         };
4415
4416         /* Disable ALDPS before ram code */
4417         rtl_writephy(tp, 0x1f, 0x0000);
4418         rtl_writephy(tp, 0x18, 0x0310);
4419         msleep(100);
4420
4421         rtl_apply_firmware(tp);
4422
4423         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4424 }
4425
4426 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4427 {
4428         /* Disable ALDPS before setting firmware */
4429         rtl_writephy(tp, 0x1f, 0x0000);
4430         rtl_writephy(tp, 0x18, 0x0310);
4431         msleep(20);
4432
4433         rtl_apply_firmware(tp);
4434
4435         /* EEE setting */
4436         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4437         rtl_writephy(tp, 0x1f, 0x0004);
4438         rtl_writephy(tp, 0x10, 0x401f);
4439         rtl_writephy(tp, 0x19, 0x7030);
4440         rtl_writephy(tp, 0x1f, 0x0000);
4441 }
4442
4443 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4444 {
4445         static const struct phy_reg phy_reg_init[] = {
4446                 { 0x1f, 0x0004 },
4447                 { 0x10, 0xc07f },
4448                 { 0x19, 0x7030 },
4449                 { 0x1f, 0x0000 }
4450         };
4451
4452         /* Disable ALDPS before ram code */
4453         rtl_writephy(tp, 0x1f, 0x0000);
4454         rtl_writephy(tp, 0x18, 0x0310);
4455         msleep(100);
4456
4457         rtl_apply_firmware(tp);
4458
4459         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4460         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4461
4462         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4463 }
4464
4465 static void rtl_hw_phy_config(struct net_device *dev)
4466 {
4467         struct rtl8169_private *tp = netdev_priv(dev);
4468
4469         rtl8169_print_mac_version(tp);
4470
4471         switch (tp->mac_version) {
4472         case RTL_GIGA_MAC_VER_01:
4473                 break;
4474         case RTL_GIGA_MAC_VER_02:
4475         case RTL_GIGA_MAC_VER_03:
4476                 rtl8169s_hw_phy_config(tp);
4477                 break;
4478         case RTL_GIGA_MAC_VER_04:
4479                 rtl8169sb_hw_phy_config(tp);
4480                 break;
4481         case RTL_GIGA_MAC_VER_05:
4482                 rtl8169scd_hw_phy_config(tp);
4483                 break;
4484         case RTL_GIGA_MAC_VER_06:
4485                 rtl8169sce_hw_phy_config(tp);
4486                 break;
4487         case RTL_GIGA_MAC_VER_07:
4488         case RTL_GIGA_MAC_VER_08:
4489         case RTL_GIGA_MAC_VER_09:
4490                 rtl8102e_hw_phy_config(tp);
4491                 break;
4492         case RTL_GIGA_MAC_VER_11:
4493                 rtl8168bb_hw_phy_config(tp);
4494                 break;
4495         case RTL_GIGA_MAC_VER_12:
4496                 rtl8168bef_hw_phy_config(tp);
4497                 break;
4498         case RTL_GIGA_MAC_VER_17:
4499                 rtl8168bef_hw_phy_config(tp);
4500                 break;
4501         case RTL_GIGA_MAC_VER_18:
4502                 rtl8168cp_1_hw_phy_config(tp);
4503                 break;
4504         case RTL_GIGA_MAC_VER_19:
4505                 rtl8168c_1_hw_phy_config(tp);
4506                 break;
4507         case RTL_GIGA_MAC_VER_20:
4508                 rtl8168c_2_hw_phy_config(tp);
4509                 break;
4510         case RTL_GIGA_MAC_VER_21:
4511                 rtl8168c_3_hw_phy_config(tp);
4512                 break;
4513         case RTL_GIGA_MAC_VER_22:
4514                 rtl8168c_4_hw_phy_config(tp);
4515                 break;
4516         case RTL_GIGA_MAC_VER_23:
4517         case RTL_GIGA_MAC_VER_24:
4518                 rtl8168cp_2_hw_phy_config(tp);
4519                 break;
4520         case RTL_GIGA_MAC_VER_25:
4521                 rtl8168d_1_hw_phy_config(tp);
4522                 break;
4523         case RTL_GIGA_MAC_VER_26:
4524                 rtl8168d_2_hw_phy_config(tp);
4525                 break;
4526         case RTL_GIGA_MAC_VER_27:
4527                 rtl8168d_3_hw_phy_config(tp);
4528                 break;
4529         case RTL_GIGA_MAC_VER_28:
4530                 rtl8168d_4_hw_phy_config(tp);
4531                 break;
4532         case RTL_GIGA_MAC_VER_29:
4533         case RTL_GIGA_MAC_VER_30:
4534                 rtl8105e_hw_phy_config(tp);
4535                 break;
4536         case RTL_GIGA_MAC_VER_31:
4537                 /* None. */
4538                 break;
4539         case RTL_GIGA_MAC_VER_32:
4540         case RTL_GIGA_MAC_VER_33:
4541                 rtl8168e_1_hw_phy_config(tp);
4542                 break;
4543         case RTL_GIGA_MAC_VER_34:
4544                 rtl8168e_2_hw_phy_config(tp);
4545                 break;
4546         case RTL_GIGA_MAC_VER_35:
4547                 rtl8168f_1_hw_phy_config(tp);
4548                 break;
4549         case RTL_GIGA_MAC_VER_36:
4550                 rtl8168f_2_hw_phy_config(tp);
4551                 break;
4552
4553         case RTL_GIGA_MAC_VER_37:
4554                 rtl8402_hw_phy_config(tp);
4555                 break;
4556
4557         case RTL_GIGA_MAC_VER_38:
4558                 rtl8411_hw_phy_config(tp);
4559                 break;
4560
4561         case RTL_GIGA_MAC_VER_39:
4562                 rtl8106e_hw_phy_config(tp);
4563                 break;
4564
4565         case RTL_GIGA_MAC_VER_40:
4566                 rtl8168g_1_hw_phy_config(tp);
4567                 break;
4568         case RTL_GIGA_MAC_VER_42:
4569         case RTL_GIGA_MAC_VER_43:
4570         case RTL_GIGA_MAC_VER_44:
4571                 rtl8168g_2_hw_phy_config(tp);
4572                 break;
4573         case RTL_GIGA_MAC_VER_45:
4574         case RTL_GIGA_MAC_VER_47:
4575                 rtl8168h_1_hw_phy_config(tp);
4576                 break;
4577         case RTL_GIGA_MAC_VER_46:
4578         case RTL_GIGA_MAC_VER_48:
4579                 rtl8168h_2_hw_phy_config(tp);
4580                 break;
4581
4582         case RTL_GIGA_MAC_VER_49:
4583                 rtl8168ep_1_hw_phy_config(tp);
4584                 break;
4585         case RTL_GIGA_MAC_VER_50:
4586         case RTL_GIGA_MAC_VER_51:
4587                 rtl8168ep_2_hw_phy_config(tp);
4588                 break;
4589
4590         case RTL_GIGA_MAC_VER_41:
4591         default:
4592                 break;
4593         }
4594 }
4595
4596 static void rtl_phy_work(struct rtl8169_private *tp)
4597 {
4598         struct timer_list *timer = &tp->timer;
4599         void __iomem *ioaddr = tp->mmio_addr;
4600         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4601
4602         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4603
4604         if (tp->phy_reset_pending(tp)) {
4605                 /*
4606                  * A busy loop could burn quite a few cycles on nowadays CPU.
4607                  * Let's delay the execution of the timer for a few ticks.
4608                  */
4609                 timeout = HZ/10;
4610                 goto out_mod_timer;
4611         }
4612
4613         if (tp->link_ok(ioaddr))
4614                 return;
4615
4616         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4617
4618         tp->phy_reset_enable(tp);
4619
4620 out_mod_timer:
4621         mod_timer(timer, jiffies + timeout);
4622 }
4623
4624 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4625 {
4626         if (!test_and_set_bit(flag, tp->wk.flags))
4627                 schedule_work(&tp->wk.work);
4628 }
4629
4630 static void rtl8169_phy_timer(struct timer_list *t)
4631 {
4632         struct rtl8169_private *tp = from_timer(tp, t, timer);
4633
4634         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4635 }
4636
4637 DECLARE_RTL_COND(rtl_phy_reset_cond)
4638 {
4639         return tp->phy_reset_pending(tp);
4640 }
4641
4642 static void rtl8169_phy_reset(struct net_device *dev,
4643                               struct rtl8169_private *tp)
4644 {
4645         tp->phy_reset_enable(tp);
4646         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4647 }
4648
4649 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4650 {
4651         void __iomem *ioaddr = tp->mmio_addr;
4652
4653         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4654             (RTL_R8(PHYstatus) & TBI_Enable);
4655 }
4656
4657 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4658 {
4659         void __iomem *ioaddr = tp->mmio_addr;
4660
4661         rtl_hw_phy_config(dev);
4662
4663         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4664                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4665                 RTL_W8(0x82, 0x01);
4666         }
4667
4668         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4669
4670         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4671                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4672
4673         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4674                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4675                 RTL_W8(0x82, 0x01);
4676                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4677                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4678         }
4679
4680         rtl8169_phy_reset(dev, tp);
4681
4682         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4683                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4684                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4685                           (tp->mii.supports_gmii ?
4686                            ADVERTISED_1000baseT_Half |
4687                            ADVERTISED_1000baseT_Full : 0));
4688
4689         if (rtl_tbi_enabled(tp))
4690                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4691 }
4692
4693 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4694 {
4695         void __iomem *ioaddr = tp->mmio_addr;
4696
4697         rtl_lock_work(tp);
4698
4699         RTL_W8(Cfg9346, Cfg9346_Unlock);
4700
4701         RTL_W32(MAC4, addr[4] | addr[5] << 8);
4702         RTL_R32(MAC4);
4703
4704         RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4705         RTL_R32(MAC0);
4706
4707         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4708                 rtl_rar_exgmac_set(tp, addr);
4709
4710         RTL_W8(Cfg9346, Cfg9346_Lock);
4711
4712         rtl_unlock_work(tp);
4713 }
4714
4715 static int rtl_set_mac_address(struct net_device *dev, void *p)
4716 {
4717         struct rtl8169_private *tp = netdev_priv(dev);
4718         struct device *d = &tp->pci_dev->dev;
4719         struct sockaddr *addr = p;
4720
4721         if (!is_valid_ether_addr(addr->sa_data))
4722                 return -EADDRNOTAVAIL;
4723
4724         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4725
4726         pm_runtime_get_noresume(d);
4727
4728         if (pm_runtime_active(d))
4729                 rtl_rar_set(tp, dev->dev_addr);
4730
4731         pm_runtime_put_noidle(d);
4732
4733         return 0;
4734 }
4735
4736 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4737 {
4738         struct rtl8169_private *tp = netdev_priv(dev);
4739         struct mii_ioctl_data *data = if_mii(ifr);
4740
4741         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4742 }
4743
4744 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4745                           struct mii_ioctl_data *data, int cmd)
4746 {
4747         switch (cmd) {
4748         case SIOCGMIIPHY:
4749                 data->phy_id = 32; /* Internal PHY */
4750                 return 0;
4751
4752         case SIOCGMIIREG:
4753                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4754                 return 0;
4755
4756         case SIOCSMIIREG:
4757                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4758                 return 0;
4759         }
4760         return -EOPNOTSUPP;
4761 }
4762
4763 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4764 {
4765         return -EOPNOTSUPP;
4766 }
4767
4768 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4769 {
4770         struct mdio_ops *ops = &tp->mdio_ops;
4771
4772         switch (tp->mac_version) {
4773         case RTL_GIGA_MAC_VER_27:
4774                 ops->write      = r8168dp_1_mdio_write;
4775                 ops->read       = r8168dp_1_mdio_read;
4776                 break;
4777         case RTL_GIGA_MAC_VER_28:
4778         case RTL_GIGA_MAC_VER_31:
4779                 ops->write      = r8168dp_2_mdio_write;
4780                 ops->read       = r8168dp_2_mdio_read;
4781                 break;
4782         case RTL_GIGA_MAC_VER_40:
4783         case RTL_GIGA_MAC_VER_41:
4784         case RTL_GIGA_MAC_VER_42:
4785         case RTL_GIGA_MAC_VER_43:
4786         case RTL_GIGA_MAC_VER_44:
4787         case RTL_GIGA_MAC_VER_45:
4788         case RTL_GIGA_MAC_VER_46:
4789         case RTL_GIGA_MAC_VER_47:
4790         case RTL_GIGA_MAC_VER_48:
4791         case RTL_GIGA_MAC_VER_49:
4792         case RTL_GIGA_MAC_VER_50:
4793         case RTL_GIGA_MAC_VER_51:
4794                 ops->write      = r8168g_mdio_write;
4795                 ops->read       = r8168g_mdio_read;
4796                 break;
4797         default:
4798                 ops->write      = r8169_mdio_write;
4799                 ops->read       = r8169_mdio_read;
4800                 break;
4801         }
4802 }
4803
4804 static void rtl_speed_down(struct rtl8169_private *tp)
4805 {
4806         u32 adv;
4807         int lpa;
4808
4809         rtl_writephy(tp, 0x1f, 0x0000);
4810         lpa = rtl_readphy(tp, MII_LPA);
4811
4812         if (lpa & (LPA_10HALF | LPA_10FULL))
4813                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4814         else if (lpa & (LPA_100HALF | LPA_100FULL))
4815                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4816                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4817         else
4818                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4819                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4820                       (tp->mii.supports_gmii ?
4821                        ADVERTISED_1000baseT_Half |
4822                        ADVERTISED_1000baseT_Full : 0);
4823
4824         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4825                           adv);
4826 }
4827
4828 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4829 {
4830         void __iomem *ioaddr = tp->mmio_addr;
4831
4832         switch (tp->mac_version) {
4833         case RTL_GIGA_MAC_VER_25:
4834         case RTL_GIGA_MAC_VER_26:
4835         case RTL_GIGA_MAC_VER_29:
4836         case RTL_GIGA_MAC_VER_30:
4837         case RTL_GIGA_MAC_VER_32:
4838         case RTL_GIGA_MAC_VER_33:
4839         case RTL_GIGA_MAC_VER_34:
4840         case RTL_GIGA_MAC_VER_37:
4841         case RTL_GIGA_MAC_VER_38:
4842         case RTL_GIGA_MAC_VER_39:
4843         case RTL_GIGA_MAC_VER_40:
4844         case RTL_GIGA_MAC_VER_41:
4845         case RTL_GIGA_MAC_VER_42:
4846         case RTL_GIGA_MAC_VER_43:
4847         case RTL_GIGA_MAC_VER_44:
4848         case RTL_GIGA_MAC_VER_45:
4849         case RTL_GIGA_MAC_VER_46:
4850         case RTL_GIGA_MAC_VER_47:
4851         case RTL_GIGA_MAC_VER_48:
4852         case RTL_GIGA_MAC_VER_49:
4853         case RTL_GIGA_MAC_VER_50:
4854         case RTL_GIGA_MAC_VER_51:
4855                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4856                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4857                 break;
4858         default:
4859                 break;
4860         }
4861 }
4862
4863 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4864 {
4865         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4866                 return false;
4867
4868         rtl_speed_down(tp);
4869         rtl_wol_suspend_quirk(tp);
4870
4871         return true;
4872 }
4873
4874 static void r810x_phy_power_down(struct rtl8169_private *tp)
4875 {
4876         rtl_writephy(tp, 0x1f, 0x0000);
4877         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4878 }
4879
4880 static void r810x_phy_power_up(struct rtl8169_private *tp)
4881 {
4882         rtl_writephy(tp, 0x1f, 0x0000);
4883         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4884 }
4885
4886 static void r810x_pll_power_down(struct rtl8169_private *tp)
4887 {
4888         void __iomem *ioaddr = tp->mmio_addr;
4889
4890         if (rtl_wol_pll_power_down(tp))
4891                 return;
4892
4893         r810x_phy_power_down(tp);
4894
4895         switch (tp->mac_version) {
4896         case RTL_GIGA_MAC_VER_07:
4897         case RTL_GIGA_MAC_VER_08:
4898         case RTL_GIGA_MAC_VER_09:
4899         case RTL_GIGA_MAC_VER_10:
4900         case RTL_GIGA_MAC_VER_13:
4901         case RTL_GIGA_MAC_VER_16:
4902                 break;
4903         default:
4904                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4905                 break;
4906         }
4907 }
4908
4909 static void r810x_pll_power_up(struct rtl8169_private *tp)
4910 {
4911         void __iomem *ioaddr = tp->mmio_addr;
4912
4913         r810x_phy_power_up(tp);
4914
4915         switch (tp->mac_version) {
4916         case RTL_GIGA_MAC_VER_07:
4917         case RTL_GIGA_MAC_VER_08:
4918         case RTL_GIGA_MAC_VER_09:
4919         case RTL_GIGA_MAC_VER_10:
4920         case RTL_GIGA_MAC_VER_13:
4921         case RTL_GIGA_MAC_VER_16:
4922                 break;
4923         case RTL_GIGA_MAC_VER_47:
4924         case RTL_GIGA_MAC_VER_48:
4925                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4926                 break;
4927         default:
4928                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4929                 break;
4930         }
4931 }
4932
4933 static void r8168_phy_power_up(struct rtl8169_private *tp)
4934 {
4935         rtl_writephy(tp, 0x1f, 0x0000);
4936         switch (tp->mac_version) {
4937         case RTL_GIGA_MAC_VER_11:
4938         case RTL_GIGA_MAC_VER_12:
4939         case RTL_GIGA_MAC_VER_17:
4940         case RTL_GIGA_MAC_VER_18:
4941         case RTL_GIGA_MAC_VER_19:
4942         case RTL_GIGA_MAC_VER_20:
4943         case RTL_GIGA_MAC_VER_21:
4944         case RTL_GIGA_MAC_VER_22:
4945         case RTL_GIGA_MAC_VER_23:
4946         case RTL_GIGA_MAC_VER_24:
4947         case RTL_GIGA_MAC_VER_25:
4948         case RTL_GIGA_MAC_VER_26:
4949         case RTL_GIGA_MAC_VER_27:
4950         case RTL_GIGA_MAC_VER_28:
4951         case RTL_GIGA_MAC_VER_31:
4952                 rtl_writephy(tp, 0x0e, 0x0000);
4953                 break;
4954         default:
4955                 break;
4956         }
4957         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4958 }
4959
4960 static void r8168_phy_power_down(struct rtl8169_private *tp)
4961 {
4962         rtl_writephy(tp, 0x1f, 0x0000);
4963         switch (tp->mac_version) {
4964         case RTL_GIGA_MAC_VER_32:
4965         case RTL_GIGA_MAC_VER_33:
4966         case RTL_GIGA_MAC_VER_40:
4967         case RTL_GIGA_MAC_VER_41:
4968                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4969                 break;
4970
4971         case RTL_GIGA_MAC_VER_11:
4972         case RTL_GIGA_MAC_VER_12:
4973         case RTL_GIGA_MAC_VER_17:
4974         case RTL_GIGA_MAC_VER_18:
4975         case RTL_GIGA_MAC_VER_19:
4976         case RTL_GIGA_MAC_VER_20:
4977         case RTL_GIGA_MAC_VER_21:
4978         case RTL_GIGA_MAC_VER_22:
4979         case RTL_GIGA_MAC_VER_23:
4980         case RTL_GIGA_MAC_VER_24:
4981         case RTL_GIGA_MAC_VER_25:
4982         case RTL_GIGA_MAC_VER_26:
4983         case RTL_GIGA_MAC_VER_27:
4984         case RTL_GIGA_MAC_VER_28:
4985         case RTL_GIGA_MAC_VER_31:
4986                 rtl_writephy(tp, 0x0e, 0x0200);
4987         default:
4988                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4989                 break;
4990         }
4991 }
4992
4993 static void r8168_pll_power_down(struct rtl8169_private *tp)
4994 {
4995         void __iomem *ioaddr = tp->mmio_addr;
4996
4997         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4998              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4999              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
5000              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5001              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5002              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
5003             r8168_check_dash(tp)) {
5004                 return;
5005         }
5006
5007         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
5008              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
5009             (RTL_R16(CPlusCmd) & ASF)) {
5010                 return;
5011         }
5012
5013         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
5014             tp->mac_version == RTL_GIGA_MAC_VER_33)
5015                 rtl_ephy_write(tp, 0x19, 0xff64);
5016
5017         if (rtl_wol_pll_power_down(tp))
5018                 return;
5019
5020         r8168_phy_power_down(tp);
5021
5022         switch (tp->mac_version) {
5023         case RTL_GIGA_MAC_VER_25:
5024         case RTL_GIGA_MAC_VER_26:
5025         case RTL_GIGA_MAC_VER_27:
5026         case RTL_GIGA_MAC_VER_28:
5027         case RTL_GIGA_MAC_VER_31:
5028         case RTL_GIGA_MAC_VER_32:
5029         case RTL_GIGA_MAC_VER_33:
5030         case RTL_GIGA_MAC_VER_44:
5031         case RTL_GIGA_MAC_VER_45:
5032         case RTL_GIGA_MAC_VER_46:
5033         case RTL_GIGA_MAC_VER_50:
5034         case RTL_GIGA_MAC_VER_51:
5035                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5036                 break;
5037         case RTL_GIGA_MAC_VER_40:
5038         case RTL_GIGA_MAC_VER_41:
5039         case RTL_GIGA_MAC_VER_49:
5040                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
5041                              0xfc000000, ERIAR_EXGMAC);
5042                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5043                 break;
5044         }
5045 }
5046
5047 static void r8168_pll_power_up(struct rtl8169_private *tp)
5048 {
5049         void __iomem *ioaddr = tp->mmio_addr;
5050
5051         switch (tp->mac_version) {
5052         case RTL_GIGA_MAC_VER_25:
5053         case RTL_GIGA_MAC_VER_26:
5054         case RTL_GIGA_MAC_VER_27:
5055         case RTL_GIGA_MAC_VER_28:
5056         case RTL_GIGA_MAC_VER_31:
5057         case RTL_GIGA_MAC_VER_32:
5058         case RTL_GIGA_MAC_VER_33:
5059                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
5060                 break;
5061         case RTL_GIGA_MAC_VER_44:
5062         case RTL_GIGA_MAC_VER_45:
5063         case RTL_GIGA_MAC_VER_46:
5064         case RTL_GIGA_MAC_VER_50:
5065         case RTL_GIGA_MAC_VER_51:
5066                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
5067                 break;
5068         case RTL_GIGA_MAC_VER_40:
5069         case RTL_GIGA_MAC_VER_41:
5070         case RTL_GIGA_MAC_VER_49:
5071                 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
5072                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
5073                              0x00000000, ERIAR_EXGMAC);
5074                 break;
5075         }
5076
5077         r8168_phy_power_up(tp);
5078 }
5079
5080 static void rtl_generic_op(struct rtl8169_private *tp,
5081                            void (*op)(struct rtl8169_private *))
5082 {
5083         if (op)
5084                 op(tp);
5085 }
5086
5087 static void rtl_pll_power_down(struct rtl8169_private *tp)
5088 {
5089         rtl_generic_op(tp, tp->pll_power_ops.down);
5090 }
5091
5092 static void rtl_pll_power_up(struct rtl8169_private *tp)
5093 {
5094         rtl_generic_op(tp, tp->pll_power_ops.up);
5095 }
5096
5097 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
5098 {
5099         struct pll_power_ops *ops = &tp->pll_power_ops;
5100
5101         switch (tp->mac_version) {
5102         case RTL_GIGA_MAC_VER_07:
5103         case RTL_GIGA_MAC_VER_08:
5104         case RTL_GIGA_MAC_VER_09:
5105         case RTL_GIGA_MAC_VER_10:
5106         case RTL_GIGA_MAC_VER_16:
5107         case RTL_GIGA_MAC_VER_29:
5108         case RTL_GIGA_MAC_VER_30:
5109         case RTL_GIGA_MAC_VER_37:
5110         case RTL_GIGA_MAC_VER_39:
5111         case RTL_GIGA_MAC_VER_43:
5112         case RTL_GIGA_MAC_VER_47:
5113         case RTL_GIGA_MAC_VER_48:
5114                 ops->down       = r810x_pll_power_down;
5115                 ops->up         = r810x_pll_power_up;
5116                 break;
5117
5118         case RTL_GIGA_MAC_VER_11:
5119         case RTL_GIGA_MAC_VER_12:
5120         case RTL_GIGA_MAC_VER_17:
5121         case RTL_GIGA_MAC_VER_18:
5122         case RTL_GIGA_MAC_VER_19:
5123         case RTL_GIGA_MAC_VER_20:
5124         case RTL_GIGA_MAC_VER_21:
5125         case RTL_GIGA_MAC_VER_22:
5126         case RTL_GIGA_MAC_VER_23:
5127         case RTL_GIGA_MAC_VER_24:
5128         case RTL_GIGA_MAC_VER_25:
5129         case RTL_GIGA_MAC_VER_26:
5130         case RTL_GIGA_MAC_VER_27:
5131         case RTL_GIGA_MAC_VER_28:
5132         case RTL_GIGA_MAC_VER_31:
5133         case RTL_GIGA_MAC_VER_32:
5134         case RTL_GIGA_MAC_VER_33:
5135         case RTL_GIGA_MAC_VER_34:
5136         case RTL_GIGA_MAC_VER_35:
5137         case RTL_GIGA_MAC_VER_36:
5138         case RTL_GIGA_MAC_VER_38:
5139         case RTL_GIGA_MAC_VER_40:
5140         case RTL_GIGA_MAC_VER_41:
5141         case RTL_GIGA_MAC_VER_42:
5142         case RTL_GIGA_MAC_VER_44:
5143         case RTL_GIGA_MAC_VER_45:
5144         case RTL_GIGA_MAC_VER_46:
5145         case RTL_GIGA_MAC_VER_49:
5146         case RTL_GIGA_MAC_VER_50:
5147         case RTL_GIGA_MAC_VER_51:
5148                 ops->down       = r8168_pll_power_down;
5149                 ops->up         = r8168_pll_power_up;
5150                 break;
5151
5152         default:
5153                 ops->down       = NULL;
5154                 ops->up         = NULL;
5155                 break;
5156         }
5157 }
5158
5159 static void rtl_init_rxcfg(struct rtl8169_private *tp)
5160 {
5161         void __iomem *ioaddr = tp->mmio_addr;
5162
5163         switch (tp->mac_version) {
5164         case RTL_GIGA_MAC_VER_01:
5165         case RTL_GIGA_MAC_VER_02:
5166         case RTL_GIGA_MAC_VER_03:
5167         case RTL_GIGA_MAC_VER_04:
5168         case RTL_GIGA_MAC_VER_05:
5169         case RTL_GIGA_MAC_VER_06:
5170         case RTL_GIGA_MAC_VER_10:
5171         case RTL_GIGA_MAC_VER_11:
5172         case RTL_GIGA_MAC_VER_12:
5173         case RTL_GIGA_MAC_VER_13:
5174         case RTL_GIGA_MAC_VER_14:
5175         case RTL_GIGA_MAC_VER_15:
5176         case RTL_GIGA_MAC_VER_16:
5177         case RTL_GIGA_MAC_VER_17:
5178                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5179                 break;
5180         case RTL_GIGA_MAC_VER_18:
5181         case RTL_GIGA_MAC_VER_19:
5182         case RTL_GIGA_MAC_VER_20:
5183         case RTL_GIGA_MAC_VER_21:
5184         case RTL_GIGA_MAC_VER_22:
5185         case RTL_GIGA_MAC_VER_23:
5186         case RTL_GIGA_MAC_VER_24:
5187         case RTL_GIGA_MAC_VER_34:
5188         case RTL_GIGA_MAC_VER_35:
5189                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5190                 break;
5191         case RTL_GIGA_MAC_VER_40:
5192         case RTL_GIGA_MAC_VER_41:
5193         case RTL_GIGA_MAC_VER_42:
5194         case RTL_GIGA_MAC_VER_43:
5195         case RTL_GIGA_MAC_VER_44:
5196         case RTL_GIGA_MAC_VER_45:
5197         case RTL_GIGA_MAC_VER_46:
5198         case RTL_GIGA_MAC_VER_47:
5199         case RTL_GIGA_MAC_VER_48:
5200         case RTL_GIGA_MAC_VER_49:
5201         case RTL_GIGA_MAC_VER_50:
5202         case RTL_GIGA_MAC_VER_51:
5203                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
5204                 break;
5205         default:
5206                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
5207                 break;
5208         }
5209 }
5210
5211 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5212 {
5213         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5214 }
5215
5216 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5217 {
5218         void __iomem *ioaddr = tp->mmio_addr;
5219
5220         RTL_W8(Cfg9346, Cfg9346_Unlock);
5221         rtl_generic_op(tp, tp->jumbo_ops.enable);
5222         RTL_W8(Cfg9346, Cfg9346_Lock);
5223 }
5224
5225 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5226 {
5227         void __iomem *ioaddr = tp->mmio_addr;
5228
5229         RTL_W8(Cfg9346, Cfg9346_Unlock);
5230         rtl_generic_op(tp, tp->jumbo_ops.disable);
5231         RTL_W8(Cfg9346, Cfg9346_Lock);
5232 }
5233
5234 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5235 {
5236         void __iomem *ioaddr = tp->mmio_addr;
5237
5238         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5239         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5240         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5241 }
5242
5243 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5244 {
5245         void __iomem *ioaddr = tp->mmio_addr;
5246
5247         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5248         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5249         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5250 }
5251
5252 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5253 {
5254         void __iomem *ioaddr = tp->mmio_addr;
5255
5256         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5257 }
5258
5259 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5260 {
5261         void __iomem *ioaddr = tp->mmio_addr;
5262
5263         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5264 }
5265
5266 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5267 {
5268         void __iomem *ioaddr = tp->mmio_addr;
5269
5270         RTL_W8(MaxTxPacketSize, 0x3f);
5271         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5272         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5273         rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5274 }
5275
5276 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5277 {
5278         void __iomem *ioaddr = tp->mmio_addr;
5279
5280         RTL_W8(MaxTxPacketSize, 0x0c);
5281         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5282         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5283         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5284 }
5285
5286 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5287 {
5288         rtl_tx_performance_tweak(tp->pci_dev,
5289                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5290 }
5291
5292 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5293 {
5294         rtl_tx_performance_tweak(tp->pci_dev,
5295                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5296 }
5297
5298 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5299 {
5300         void __iomem *ioaddr = tp->mmio_addr;
5301
5302         r8168b_0_hw_jumbo_enable(tp);
5303
5304         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5305 }
5306
5307 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5308 {
5309         void __iomem *ioaddr = tp->mmio_addr;
5310
5311         r8168b_0_hw_jumbo_disable(tp);
5312
5313         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5314 }
5315
5316 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5317 {
5318         struct jumbo_ops *ops = &tp->jumbo_ops;
5319
5320         switch (tp->mac_version) {
5321         case RTL_GIGA_MAC_VER_11:
5322                 ops->disable    = r8168b_0_hw_jumbo_disable;
5323                 ops->enable     = r8168b_0_hw_jumbo_enable;
5324                 break;
5325         case RTL_GIGA_MAC_VER_12:
5326         case RTL_GIGA_MAC_VER_17:
5327                 ops->disable    = r8168b_1_hw_jumbo_disable;
5328                 ops->enable     = r8168b_1_hw_jumbo_enable;
5329                 break;
5330         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5331         case RTL_GIGA_MAC_VER_19:
5332         case RTL_GIGA_MAC_VER_20:
5333         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5334         case RTL_GIGA_MAC_VER_22:
5335         case RTL_GIGA_MAC_VER_23:
5336         case RTL_GIGA_MAC_VER_24:
5337         case RTL_GIGA_MAC_VER_25:
5338         case RTL_GIGA_MAC_VER_26:
5339                 ops->disable    = r8168c_hw_jumbo_disable;
5340                 ops->enable     = r8168c_hw_jumbo_enable;
5341                 break;
5342         case RTL_GIGA_MAC_VER_27:
5343         case RTL_GIGA_MAC_VER_28:
5344                 ops->disable    = r8168dp_hw_jumbo_disable;
5345                 ops->enable     = r8168dp_hw_jumbo_enable;
5346                 break;
5347         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5348         case RTL_GIGA_MAC_VER_32:
5349         case RTL_GIGA_MAC_VER_33:
5350         case RTL_GIGA_MAC_VER_34:
5351                 ops->disable    = r8168e_hw_jumbo_disable;
5352                 ops->enable     = r8168e_hw_jumbo_enable;
5353                 break;
5354
5355         /*
5356          * No action needed for jumbo frames with 8169.
5357          * No jumbo for 810x at all.
5358          */
5359         case RTL_GIGA_MAC_VER_40:
5360         case RTL_GIGA_MAC_VER_41:
5361         case RTL_GIGA_MAC_VER_42:
5362         case RTL_GIGA_MAC_VER_43:
5363         case RTL_GIGA_MAC_VER_44:
5364         case RTL_GIGA_MAC_VER_45:
5365         case RTL_GIGA_MAC_VER_46:
5366         case RTL_GIGA_MAC_VER_47:
5367         case RTL_GIGA_MAC_VER_48:
5368         case RTL_GIGA_MAC_VER_49:
5369         case RTL_GIGA_MAC_VER_50:
5370         case RTL_GIGA_MAC_VER_51:
5371         default:
5372                 ops->disable    = NULL;
5373                 ops->enable     = NULL;
5374                 break;
5375         }
5376 }
5377
5378 DECLARE_RTL_COND(rtl_chipcmd_cond)
5379 {
5380         void __iomem *ioaddr = tp->mmio_addr;
5381
5382         return RTL_R8(ChipCmd) & CmdReset;
5383 }
5384
5385 static void rtl_hw_reset(struct rtl8169_private *tp)
5386 {
5387         void __iomem *ioaddr = tp->mmio_addr;
5388
5389         RTL_W8(ChipCmd, CmdReset);
5390
5391         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5392 }
5393
5394 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5395 {
5396         struct rtl_fw *rtl_fw;
5397         const char *name;
5398         int rc = -ENOMEM;
5399
5400         name = rtl_lookup_firmware_name(tp);
5401         if (!name)
5402                 goto out_no_firmware;
5403
5404         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5405         if (!rtl_fw)
5406                 goto err_warn;
5407
5408         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5409         if (rc < 0)
5410                 goto err_free;
5411
5412         rc = rtl_check_firmware(tp, rtl_fw);
5413         if (rc < 0)
5414                 goto err_release_firmware;
5415
5416         tp->rtl_fw = rtl_fw;
5417 out:
5418         return;
5419
5420 err_release_firmware:
5421         release_firmware(rtl_fw->fw);
5422 err_free:
5423         kfree(rtl_fw);
5424 err_warn:
5425         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5426                    name, rc);
5427 out_no_firmware:
5428         tp->rtl_fw = NULL;
5429         goto out;
5430 }
5431
5432 static void rtl_request_firmware(struct rtl8169_private *tp)
5433 {
5434         if (IS_ERR(tp->rtl_fw))
5435                 rtl_request_uncached_firmware(tp);
5436 }
5437
5438 static void rtl_rx_close(struct rtl8169_private *tp)
5439 {
5440         void __iomem *ioaddr = tp->mmio_addr;
5441
5442         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5443 }
5444
5445 DECLARE_RTL_COND(rtl_npq_cond)
5446 {
5447         void __iomem *ioaddr = tp->mmio_addr;
5448
5449         return RTL_R8(TxPoll) & NPQ;
5450 }
5451
5452 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5453 {
5454         void __iomem *ioaddr = tp->mmio_addr;
5455
5456         return RTL_R32(TxConfig) & TXCFG_EMPTY;
5457 }
5458
5459 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5460 {
5461         void __iomem *ioaddr = tp->mmio_addr;
5462
5463         /* Disable interrupts */
5464         rtl8169_irq_mask_and_ack(tp);
5465
5466         rtl_rx_close(tp);
5467
5468         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5469             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5470             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5471                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5472         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5473                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5474                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5475                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5476                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5477                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5478                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5479                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5480                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5481                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5482                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5483                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5484                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5485                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5486                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5487                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5488                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5489                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5490                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5491         } else {
5492                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5493                 udelay(100);
5494         }
5495
5496         rtl_hw_reset(tp);
5497 }
5498
5499 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5500 {
5501         void __iomem *ioaddr = tp->mmio_addr;
5502
5503         /* Set DMA burst size and Interframe Gap Time */
5504         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5505                 (InterFrameGap << TxInterFrameGapShift));
5506 }
5507
5508 static void rtl_hw_start(struct net_device *dev)
5509 {
5510         struct rtl8169_private *tp = netdev_priv(dev);
5511
5512         tp->hw_start(dev);
5513
5514         rtl_irq_enable_all(tp);
5515 }
5516
5517 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5518                                          void __iomem *ioaddr)
5519 {
5520         /*
5521          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5522          * register to be written before TxDescAddrLow to work.
5523          * Switching from MMIO to I/O access fixes the issue as well.
5524          */
5525         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5526         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5527         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5528         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5529 }
5530
5531 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5532 {
5533         u16 cmd;
5534
5535         cmd = RTL_R16(CPlusCmd);
5536         RTL_W16(CPlusCmd, cmd);
5537         return cmd;
5538 }
5539
5540 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5541 {
5542         /* Low hurts. Let's disable the filtering. */
5543         RTL_W16(RxMaxSize, rx_buf_sz + 1);
5544 }
5545
5546 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5547 {
5548         static const struct rtl_cfg2_info {
5549                 u32 mac_version;
5550                 u32 clk;
5551                 u32 val;
5552         } cfg2_info [] = {
5553                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5554                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5555                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5556                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5557         };
5558         const struct rtl_cfg2_info *p = cfg2_info;
5559         unsigned int i;
5560         u32 clk;
5561
5562         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5563         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5564                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5565                         RTL_W32(0x7c, p->val);
5566                         break;
5567                 }
5568         }
5569 }
5570
5571 static void rtl_set_rx_mode(struct net_device *dev)
5572 {
5573         struct rtl8169_private *tp = netdev_priv(dev);
5574         void __iomem *ioaddr = tp->mmio_addr;
5575         u32 mc_filter[2];       /* Multicast hash filter */
5576         int rx_mode;
5577         u32 tmp = 0;
5578
5579         if (dev->flags & IFF_PROMISC) {
5580                 /* Unconditionally log net taps. */
5581                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5582                 rx_mode =
5583                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5584                     AcceptAllPhys;
5585                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5586         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5587                    (dev->flags & IFF_ALLMULTI)) {
5588                 /* Too many to filter perfectly -- accept all multicasts. */
5589                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5590                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5591         } else {
5592                 struct netdev_hw_addr *ha;
5593
5594                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5595                 mc_filter[1] = mc_filter[0] = 0;
5596                 netdev_for_each_mc_addr(ha, dev) {
5597                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5598                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5599                         rx_mode |= AcceptMulticast;
5600                 }
5601         }
5602
5603         if (dev->features & NETIF_F_RXALL)
5604                 rx_mode |= (AcceptErr | AcceptRunt);
5605
5606         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5607
5608         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5609                 u32 data = mc_filter[0];
5610
5611                 mc_filter[0] = swab32(mc_filter[1]);
5612                 mc_filter[1] = swab32(data);
5613         }
5614
5615         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5616                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5617
5618         RTL_W32(MAR0 + 4, mc_filter[1]);
5619         RTL_W32(MAR0 + 0, mc_filter[0]);
5620
5621         RTL_W32(RxConfig, tmp);
5622 }
5623
5624 static void rtl_hw_start_8169(struct net_device *dev)
5625 {
5626         struct rtl8169_private *tp = netdev_priv(dev);
5627         void __iomem *ioaddr = tp->mmio_addr;
5628         struct pci_dev *pdev = tp->pci_dev;
5629
5630         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5631                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5632                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5633         }
5634
5635         RTL_W8(Cfg9346, Cfg9346_Unlock);
5636         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5637             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5638             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5639             tp->mac_version == RTL_GIGA_MAC_VER_04)
5640                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5641
5642         rtl_init_rxcfg(tp);
5643
5644         RTL_W8(EarlyTxThres, NoEarlyTx);
5645
5646         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5647
5648         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5649             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5650             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5651             tp->mac_version == RTL_GIGA_MAC_VER_04)
5652                 rtl_set_rx_tx_config_registers(tp);
5653
5654         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5655
5656         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5657             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5658                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5659                         "Bit-3 and bit-14 MUST be 1\n");
5660                 tp->cp_cmd |= (1 << 14);
5661         }
5662
5663         RTL_W16(CPlusCmd, tp->cp_cmd);
5664
5665         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5666
5667         /*
5668          * Undocumented corner. Supposedly:
5669          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5670          */
5671         RTL_W16(IntrMitigate, 0x0000);
5672
5673         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5674
5675         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5676             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5677             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5678             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5679                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5680                 rtl_set_rx_tx_config_registers(tp);
5681         }
5682
5683         RTL_W8(Cfg9346, Cfg9346_Lock);
5684
5685         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5686         RTL_R8(IntrMask);
5687
5688         RTL_W32(RxMissed, 0);
5689
5690         rtl_set_rx_mode(dev);
5691
5692         /* no early-rx interrupts */
5693         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5694 }
5695
5696 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5697 {
5698         if (tp->csi_ops.write)
5699                 tp->csi_ops.write(tp, addr, value);
5700 }
5701
5702 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5703 {
5704         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5705 }
5706
5707 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5708 {
5709         u32 csi;
5710
5711         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5712         rtl_csi_write(tp, 0x070c, csi | bits);
5713 }
5714
5715 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5716 {
5717         rtl_csi_access_enable(tp, 0x17000000);
5718 }
5719
5720 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5721 {
5722         rtl_csi_access_enable(tp, 0x27000000);
5723 }
5724
5725 DECLARE_RTL_COND(rtl_csiar_cond)
5726 {
5727         void __iomem *ioaddr = tp->mmio_addr;
5728
5729         return RTL_R32(CSIAR) & CSIAR_FLAG;
5730 }
5731
5732 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5733 {
5734         void __iomem *ioaddr = tp->mmio_addr;
5735
5736         RTL_W32(CSIDR, value);
5737         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5738                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5739
5740         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5741 }
5742
5743 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5744 {
5745         void __iomem *ioaddr = tp->mmio_addr;
5746
5747         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5748                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5749
5750         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5751                 RTL_R32(CSIDR) : ~0;
5752 }
5753
5754 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5755 {
5756         void __iomem *ioaddr = tp->mmio_addr;
5757
5758         RTL_W32(CSIDR, value);
5759         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5760                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5761                 CSIAR_FUNC_NIC);
5762
5763         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5764 }
5765
5766 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5767 {
5768         void __iomem *ioaddr = tp->mmio_addr;
5769
5770         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5771                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5772
5773         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5774                 RTL_R32(CSIDR) : ~0;
5775 }
5776
5777 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5778 {
5779         void __iomem *ioaddr = tp->mmio_addr;
5780
5781         RTL_W32(CSIDR, value);
5782         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5783                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5784                 CSIAR_FUNC_NIC2);
5785
5786         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5787 }
5788
5789 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5790 {
5791         void __iomem *ioaddr = tp->mmio_addr;
5792
5793         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5794                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5795
5796         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5797                 RTL_R32(CSIDR) : ~0;
5798 }
5799
5800 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5801 {
5802         struct csi_ops *ops = &tp->csi_ops;
5803
5804         switch (tp->mac_version) {
5805         case RTL_GIGA_MAC_VER_01:
5806         case RTL_GIGA_MAC_VER_02:
5807         case RTL_GIGA_MAC_VER_03:
5808         case RTL_GIGA_MAC_VER_04:
5809         case RTL_GIGA_MAC_VER_05:
5810         case RTL_GIGA_MAC_VER_06:
5811         case RTL_GIGA_MAC_VER_10:
5812         case RTL_GIGA_MAC_VER_11:
5813         case RTL_GIGA_MAC_VER_12:
5814         case RTL_GIGA_MAC_VER_13:
5815         case RTL_GIGA_MAC_VER_14:
5816         case RTL_GIGA_MAC_VER_15:
5817         case RTL_GIGA_MAC_VER_16:
5818         case RTL_GIGA_MAC_VER_17:
5819                 ops->write      = NULL;
5820                 ops->read       = NULL;
5821                 break;
5822
5823         case RTL_GIGA_MAC_VER_37:
5824         case RTL_GIGA_MAC_VER_38:
5825                 ops->write      = r8402_csi_write;
5826                 ops->read       = r8402_csi_read;
5827                 break;
5828
5829         case RTL_GIGA_MAC_VER_44:
5830                 ops->write      = r8411_csi_write;
5831                 ops->read       = r8411_csi_read;
5832                 break;
5833
5834         default:
5835                 ops->write      = r8169_csi_write;
5836                 ops->read       = r8169_csi_read;
5837                 break;
5838         }
5839 }
5840
5841 struct ephy_info {
5842         unsigned int offset;
5843         u16 mask;
5844         u16 bits;
5845 };
5846
5847 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5848                           int len)
5849 {
5850         u16 w;
5851
5852         while (len-- > 0) {
5853                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5854                 rtl_ephy_write(tp, e->offset, w);
5855                 e++;
5856         }
5857 }
5858
5859 static void rtl_disable_clock_request(struct pci_dev *pdev)
5860 {
5861         pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5862                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5863 }
5864
5865 static void rtl_enable_clock_request(struct pci_dev *pdev)
5866 {
5867         pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5868                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5869 }
5870
5871 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5872 {
5873         void __iomem *ioaddr = tp->mmio_addr;
5874         u8 data;
5875
5876         data = RTL_R8(Config3);
5877
5878         if (enable)
5879                 data |= Rdy_to_L23;
5880         else
5881                 data &= ~Rdy_to_L23;
5882
5883         RTL_W8(Config3, data);
5884 }
5885
5886 #define R8168_CPCMD_QUIRK_MASK (\
5887         EnableBist | \
5888         Mac_dbgo_oe | \
5889         Force_half_dup | \
5890         Force_rxflow_en | \
5891         Force_txflow_en | \
5892         Cxpl_dbg_sel | \
5893         ASF | \
5894         PktCntrDisable | \
5895         Mac_dbgo_sel)
5896
5897 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5898 {
5899         void __iomem *ioaddr = tp->mmio_addr;
5900         struct pci_dev *pdev = tp->pci_dev;
5901
5902         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5903
5904         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5905
5906         if (tp->dev->mtu <= ETH_DATA_LEN) {
5907                 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5908                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5909         }
5910 }
5911
5912 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5913 {
5914         void __iomem *ioaddr = tp->mmio_addr;
5915
5916         rtl_hw_start_8168bb(tp);
5917
5918         RTL_W8(MaxTxPacketSize, TxPacketMax);
5919
5920         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5921 }
5922
5923 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5924 {
5925         void __iomem *ioaddr = tp->mmio_addr;
5926         struct pci_dev *pdev = tp->pci_dev;
5927
5928         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5929
5930         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5931
5932         if (tp->dev->mtu <= ETH_DATA_LEN)
5933                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5934
5935         rtl_disable_clock_request(pdev);
5936
5937         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5938 }
5939
5940 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5941 {
5942         static const struct ephy_info e_info_8168cp[] = {
5943                 { 0x01, 0,      0x0001 },
5944                 { 0x02, 0x0800, 0x1000 },
5945                 { 0x03, 0,      0x0042 },
5946                 { 0x06, 0x0080, 0x0000 },
5947                 { 0x07, 0,      0x2000 }
5948         };
5949
5950         rtl_csi_access_enable_2(tp);
5951
5952         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5953
5954         __rtl_hw_start_8168cp(tp);
5955 }
5956
5957 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5958 {
5959         void __iomem *ioaddr = tp->mmio_addr;
5960         struct pci_dev *pdev = tp->pci_dev;
5961
5962         rtl_csi_access_enable_2(tp);
5963
5964         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5965
5966         if (tp->dev->mtu <= ETH_DATA_LEN)
5967                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5968
5969         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5970 }
5971
5972 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5973 {
5974         void __iomem *ioaddr = tp->mmio_addr;
5975         struct pci_dev *pdev = tp->pci_dev;
5976
5977         rtl_csi_access_enable_2(tp);
5978
5979         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5980
5981         /* Magic. */
5982         RTL_W8(DBG_REG, 0x20);
5983
5984         RTL_W8(MaxTxPacketSize, TxPacketMax);
5985
5986         if (tp->dev->mtu <= ETH_DATA_LEN)
5987                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5988
5989         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5990 }
5991
5992 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5993 {
5994         void __iomem *ioaddr = tp->mmio_addr;
5995         static const struct ephy_info e_info_8168c_1[] = {
5996                 { 0x02, 0x0800, 0x1000 },
5997                 { 0x03, 0,      0x0002 },
5998                 { 0x06, 0x0080, 0x0000 }
5999         };
6000
6001         rtl_csi_access_enable_2(tp);
6002
6003         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
6004
6005         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
6006
6007         __rtl_hw_start_8168cp(tp);
6008 }
6009
6010 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
6011 {
6012         static const struct ephy_info e_info_8168c_2[] = {
6013                 { 0x01, 0,      0x0001 },
6014                 { 0x03, 0x0400, 0x0220 }
6015         };
6016
6017         rtl_csi_access_enable_2(tp);
6018
6019         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
6020
6021         __rtl_hw_start_8168cp(tp);
6022 }
6023
6024 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
6025 {
6026         rtl_hw_start_8168c_2(tp);
6027 }
6028
6029 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6030 {
6031         rtl_csi_access_enable_2(tp);
6032
6033         __rtl_hw_start_8168cp(tp);
6034 }
6035
6036 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
6037 {
6038         void __iomem *ioaddr = tp->mmio_addr;
6039         struct pci_dev *pdev = tp->pci_dev;
6040
6041         rtl_csi_access_enable_2(tp);
6042
6043         rtl_disable_clock_request(pdev);
6044
6045         RTL_W8(MaxTxPacketSize, TxPacketMax);
6046
6047         if (tp->dev->mtu <= ETH_DATA_LEN)
6048                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6049
6050         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
6051 }
6052
6053 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
6054 {
6055         void __iomem *ioaddr = tp->mmio_addr;
6056         struct pci_dev *pdev = tp->pci_dev;
6057
6058         rtl_csi_access_enable_1(tp);
6059
6060         if (tp->dev->mtu <= ETH_DATA_LEN)
6061                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6062
6063         RTL_W8(MaxTxPacketSize, TxPacketMax);
6064
6065         rtl_disable_clock_request(pdev);
6066 }
6067
6068 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
6069 {
6070         void __iomem *ioaddr = tp->mmio_addr;
6071         struct pci_dev *pdev = tp->pci_dev;
6072         static const struct ephy_info e_info_8168d_4[] = {
6073                 { 0x0b, 0x0000, 0x0048 },
6074                 { 0x19, 0x0020, 0x0050 },
6075                 { 0x0c, 0x0100, 0x0020 }
6076         };
6077
6078         rtl_csi_access_enable_1(tp);
6079
6080         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6081
6082         RTL_W8(MaxTxPacketSize, TxPacketMax);
6083
6084         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
6085
6086         rtl_enable_clock_request(pdev);
6087 }
6088
6089 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
6090 {
6091         void __iomem *ioaddr = tp->mmio_addr;
6092         struct pci_dev *pdev = tp->pci_dev;
6093         static const struct ephy_info e_info_8168e_1[] = {
6094                 { 0x00, 0x0200, 0x0100 },
6095                 { 0x00, 0x0000, 0x0004 },
6096                 { 0x06, 0x0002, 0x0001 },
6097                 { 0x06, 0x0000, 0x0030 },
6098                 { 0x07, 0x0000, 0x2000 },
6099                 { 0x00, 0x0000, 0x0020 },
6100                 { 0x03, 0x5800, 0x2000 },
6101                 { 0x03, 0x0000, 0x0001 },
6102                 { 0x01, 0x0800, 0x1000 },
6103                 { 0x07, 0x0000, 0x4000 },
6104                 { 0x1e, 0x0000, 0x2000 },
6105                 { 0x19, 0xffff, 0xfe6c },
6106                 { 0x0a, 0x0000, 0x0040 }
6107         };
6108
6109         rtl_csi_access_enable_2(tp);
6110
6111         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
6112
6113         if (tp->dev->mtu <= ETH_DATA_LEN)
6114                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6115
6116         RTL_W8(MaxTxPacketSize, TxPacketMax);
6117
6118         rtl_disable_clock_request(pdev);
6119
6120         /* Reset tx FIFO pointer */
6121         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
6122         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
6123
6124         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6125 }
6126
6127 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
6128 {
6129         void __iomem *ioaddr = tp->mmio_addr;
6130         struct pci_dev *pdev = tp->pci_dev;
6131         static const struct ephy_info e_info_8168e_2[] = {
6132                 { 0x09, 0x0000, 0x0080 },
6133                 { 0x19, 0x0000, 0x0224 }
6134         };
6135
6136         rtl_csi_access_enable_1(tp);
6137
6138         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
6139
6140         if (tp->dev->mtu <= ETH_DATA_LEN)
6141                 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6142
6143         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6144         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6145         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6146         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6147         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6148         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
6149         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6150         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6151
6152         RTL_W8(MaxTxPacketSize, EarlySize);
6153
6154         rtl_disable_clock_request(pdev);
6155
6156         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6157         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6158
6159         /* Adjust EEE LED frequency */
6160         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6161
6162         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6163         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6164         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6165 }
6166
6167 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
6168 {
6169         void __iomem *ioaddr = tp->mmio_addr;
6170         struct pci_dev *pdev = tp->pci_dev;
6171
6172         rtl_csi_access_enable_2(tp);
6173
6174         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6175
6176         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6177         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6178         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6179         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6180         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6181         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6182         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6183         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6184         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6185         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
6186
6187         RTL_W8(MaxTxPacketSize, EarlySize);
6188
6189         rtl_disable_clock_request(pdev);
6190
6191         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6192         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6193         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6194         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6195         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6196 }
6197
6198 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
6199 {
6200         void __iomem *ioaddr = tp->mmio_addr;
6201         static const struct ephy_info e_info_8168f_1[] = {
6202                 { 0x06, 0x00c0, 0x0020 },
6203                 { 0x08, 0x0001, 0x0002 },
6204                 { 0x09, 0x0000, 0x0080 },
6205                 { 0x19, 0x0000, 0x0224 }
6206         };
6207
6208         rtl_hw_start_8168f(tp);
6209
6210         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6211
6212         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6213
6214         /* Adjust EEE LED frequency */
6215         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6216 }
6217
6218 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6219 {
6220         static const struct ephy_info e_info_8168f_1[] = {
6221                 { 0x06, 0x00c0, 0x0020 },
6222                 { 0x0f, 0xffff, 0x5200 },
6223                 { 0x1e, 0x0000, 0x4000 },
6224                 { 0x19, 0x0000, 0x0224 }
6225         };
6226
6227         rtl_hw_start_8168f(tp);
6228         rtl_pcie_state_l2l3_enable(tp, false);
6229
6230         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6231
6232         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6233 }
6234
6235 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6236 {
6237         void __iomem *ioaddr = tp->mmio_addr;
6238         struct pci_dev *pdev = tp->pci_dev;
6239
6240         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6241
6242         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6243         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6244         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6245         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6246
6247         rtl_csi_access_enable_1(tp);
6248
6249         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6250
6251         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6252         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6253         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6254
6255         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6256         RTL_W8(MaxTxPacketSize, EarlySize);
6257
6258         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6259         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6260
6261         /* Adjust EEE LED frequency */
6262         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6263
6264         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6265         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6266
6267         rtl_pcie_state_l2l3_enable(tp, false);
6268 }
6269
6270 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6271 {
6272         void __iomem *ioaddr = tp->mmio_addr;
6273         static const struct ephy_info e_info_8168g_1[] = {
6274                 { 0x00, 0x0000, 0x0008 },
6275                 { 0x0c, 0x37d0, 0x0820 },
6276                 { 0x1e, 0x0000, 0x0001 },
6277                 { 0x19, 0x8000, 0x0000 }
6278         };
6279
6280         rtl_hw_start_8168g(tp);
6281
6282         /* disable aspm and clock request before access ephy */
6283         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6284         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6285         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6286 }
6287
6288 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6289 {
6290         void __iomem *ioaddr = tp->mmio_addr;
6291         static const struct ephy_info e_info_8168g_2[] = {
6292                 { 0x00, 0x0000, 0x0008 },
6293                 { 0x0c, 0x3df0, 0x0200 },
6294                 { 0x19, 0xffff, 0xfc00 },
6295                 { 0x1e, 0xffff, 0x20eb }
6296         };
6297
6298         rtl_hw_start_8168g(tp);
6299
6300         /* disable aspm and clock request before access ephy */
6301         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6302         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6303         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6304 }
6305
6306 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6307 {
6308         void __iomem *ioaddr = tp->mmio_addr;
6309         static const struct ephy_info e_info_8411_2[] = {
6310                 { 0x00, 0x0000, 0x0008 },
6311                 { 0x0c, 0x3df0, 0x0200 },
6312                 { 0x0f, 0xffff, 0x5200 },
6313                 { 0x19, 0x0020, 0x0000 },
6314                 { 0x1e, 0x0000, 0x2000 }
6315         };
6316
6317         rtl_hw_start_8168g(tp);
6318
6319         /* disable aspm and clock request before access ephy */
6320         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6321         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6322         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6323 }
6324
6325 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6326 {
6327         void __iomem *ioaddr = tp->mmio_addr;
6328         struct pci_dev *pdev = tp->pci_dev;
6329         int rg_saw_cnt;
6330         u32 data;
6331         static const struct ephy_info e_info_8168h_1[] = {
6332                 { 0x1e, 0x0800, 0x0001 },
6333                 { 0x1d, 0x0000, 0x0800 },
6334                 { 0x05, 0xffff, 0x2089 },
6335                 { 0x06, 0xffff, 0x5881 },
6336                 { 0x04, 0xffff, 0x154a },
6337                 { 0x01, 0xffff, 0x068b }
6338         };
6339
6340         /* disable aspm and clock request before access ephy */
6341         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6342         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6343         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6344
6345         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6346
6347         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6348         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6349         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6350         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6351
6352         rtl_csi_access_enable_1(tp);
6353
6354         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6355
6356         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6357         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6358
6359         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6360
6361         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6362
6363         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6364
6365         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6366         RTL_W8(MaxTxPacketSize, EarlySize);
6367
6368         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6369         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6370
6371         /* Adjust EEE LED frequency */
6372         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6373
6374         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6375         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6376
6377         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6378
6379         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6380
6381         rtl_pcie_state_l2l3_enable(tp, false);
6382
6383         rtl_writephy(tp, 0x1f, 0x0c42);
6384         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6385         rtl_writephy(tp, 0x1f, 0x0000);
6386         if (rg_saw_cnt > 0) {
6387                 u16 sw_cnt_1ms_ini;
6388
6389                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6390                 sw_cnt_1ms_ini &= 0x0fff;
6391                 data = r8168_mac_ocp_read(tp, 0xd412);
6392                 data &= ~0x0fff;
6393                 data |= sw_cnt_1ms_ini;
6394                 r8168_mac_ocp_write(tp, 0xd412, data);
6395         }
6396
6397         data = r8168_mac_ocp_read(tp, 0xe056);
6398         data &= ~0xf0;
6399         data |= 0x70;
6400         r8168_mac_ocp_write(tp, 0xe056, data);
6401
6402         data = r8168_mac_ocp_read(tp, 0xe052);
6403         data &= ~0x6000;
6404         data |= 0x8008;
6405         r8168_mac_ocp_write(tp, 0xe052, data);
6406
6407         data = r8168_mac_ocp_read(tp, 0xe0d6);
6408         data &= ~0x01ff;
6409         data |= 0x017f;
6410         r8168_mac_ocp_write(tp, 0xe0d6, data);
6411
6412         data = r8168_mac_ocp_read(tp, 0xd420);
6413         data &= ~0x0fff;
6414         data |= 0x047f;
6415         r8168_mac_ocp_write(tp, 0xd420, data);
6416
6417         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6418         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6419         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6420         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6421 }
6422
6423 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6424 {
6425         void __iomem *ioaddr = tp->mmio_addr;
6426         struct pci_dev *pdev = tp->pci_dev;
6427
6428         rtl8168ep_stop_cmac(tp);
6429
6430         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6431
6432         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6433         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6434         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6435         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6436
6437         rtl_csi_access_enable_1(tp);
6438
6439         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6440
6441         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6442         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6443
6444         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6445
6446         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6447
6448         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6449         RTL_W8(MaxTxPacketSize, EarlySize);
6450
6451         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6452         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6453
6454         /* Adjust EEE LED frequency */
6455         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6456
6457         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6458
6459         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6460
6461         rtl_pcie_state_l2l3_enable(tp, false);
6462 }
6463
6464 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6465 {
6466         void __iomem *ioaddr = tp->mmio_addr;
6467         static const struct ephy_info e_info_8168ep_1[] = {
6468                 { 0x00, 0xffff, 0x10ab },
6469                 { 0x06, 0xffff, 0xf030 },
6470                 { 0x08, 0xffff, 0x2006 },
6471                 { 0x0d, 0xffff, 0x1666 },
6472                 { 0x0c, 0x3ff0, 0x0000 }
6473         };
6474
6475         /* disable aspm and clock request before access ephy */
6476         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6477         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6478         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6479
6480         rtl_hw_start_8168ep(tp);
6481 }
6482
6483 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6484 {
6485         void __iomem *ioaddr = tp->mmio_addr;
6486         static const struct ephy_info e_info_8168ep_2[] = {
6487                 { 0x00, 0xffff, 0x10a3 },
6488                 { 0x19, 0xffff, 0xfc00 },
6489                 { 0x1e, 0xffff, 0x20ea }
6490         };
6491
6492         /* disable aspm and clock request before access ephy */
6493         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6494         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6495         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6496
6497         rtl_hw_start_8168ep(tp);
6498
6499         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6500         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6501 }
6502
6503 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6504 {
6505         void __iomem *ioaddr = tp->mmio_addr;
6506         u32 data;
6507         static const struct ephy_info e_info_8168ep_3[] = {
6508                 { 0x00, 0xffff, 0x10a3 },
6509                 { 0x19, 0xffff, 0x7c00 },
6510                 { 0x1e, 0xffff, 0x20eb },
6511                 { 0x0d, 0xffff, 0x1666 }
6512         };
6513
6514         /* disable aspm and clock request before access ephy */
6515         RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6516         RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6517         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6518
6519         rtl_hw_start_8168ep(tp);
6520
6521         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6522         RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6523
6524         data = r8168_mac_ocp_read(tp, 0xd3e2);
6525         data &= 0xf000;
6526         data |= 0x0271;
6527         r8168_mac_ocp_write(tp, 0xd3e2, data);
6528
6529         data = r8168_mac_ocp_read(tp, 0xd3e4);
6530         data &= 0xff00;
6531         r8168_mac_ocp_write(tp, 0xd3e4, data);
6532
6533         data = r8168_mac_ocp_read(tp, 0xe860);
6534         data |= 0x0080;
6535         r8168_mac_ocp_write(tp, 0xe860, data);
6536 }
6537
6538 static void rtl_hw_start_8168(struct net_device *dev)
6539 {
6540         struct rtl8169_private *tp = netdev_priv(dev);
6541         void __iomem *ioaddr = tp->mmio_addr;
6542
6543         RTL_W8(Cfg9346, Cfg9346_Unlock);
6544
6545         RTL_W8(MaxTxPacketSize, TxPacketMax);
6546
6547         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6548
6549         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6550
6551         RTL_W16(CPlusCmd, tp->cp_cmd);
6552
6553         RTL_W16(IntrMitigate, 0x5151);
6554
6555         /* Work around for RxFIFO overflow. */
6556         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6557                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6558                 tp->event_slow &= ~RxOverflow;
6559         }
6560
6561         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6562
6563         rtl_set_rx_tx_config_registers(tp);
6564
6565         RTL_R8(IntrMask);
6566
6567         switch (tp->mac_version) {
6568         case RTL_GIGA_MAC_VER_11:
6569                 rtl_hw_start_8168bb(tp);
6570                 break;
6571
6572         case RTL_GIGA_MAC_VER_12:
6573         case RTL_GIGA_MAC_VER_17:
6574                 rtl_hw_start_8168bef(tp);
6575                 break;
6576
6577         case RTL_GIGA_MAC_VER_18:
6578                 rtl_hw_start_8168cp_1(tp);
6579                 break;
6580
6581         case RTL_GIGA_MAC_VER_19:
6582                 rtl_hw_start_8168c_1(tp);
6583                 break;
6584
6585         case RTL_GIGA_MAC_VER_20:
6586                 rtl_hw_start_8168c_2(tp);
6587                 break;
6588
6589         case RTL_GIGA_MAC_VER_21:
6590                 rtl_hw_start_8168c_3(tp);
6591                 break;
6592
6593         case RTL_GIGA_MAC_VER_22:
6594                 rtl_hw_start_8168c_4(tp);
6595                 break;
6596
6597         case RTL_GIGA_MAC_VER_23:
6598                 rtl_hw_start_8168cp_2(tp);
6599                 break;
6600
6601         case RTL_GIGA_MAC_VER_24:
6602                 rtl_hw_start_8168cp_3(tp);
6603                 break;
6604
6605         case RTL_GIGA_MAC_VER_25:
6606         case RTL_GIGA_MAC_VER_26:
6607         case RTL_GIGA_MAC_VER_27:
6608                 rtl_hw_start_8168d(tp);
6609                 break;
6610
6611         case RTL_GIGA_MAC_VER_28:
6612                 rtl_hw_start_8168d_4(tp);
6613                 break;
6614
6615         case RTL_GIGA_MAC_VER_31:
6616                 rtl_hw_start_8168dp(tp);
6617                 break;
6618
6619         case RTL_GIGA_MAC_VER_32:
6620         case RTL_GIGA_MAC_VER_33:
6621                 rtl_hw_start_8168e_1(tp);
6622                 break;
6623         case RTL_GIGA_MAC_VER_34:
6624                 rtl_hw_start_8168e_2(tp);
6625                 break;
6626
6627         case RTL_GIGA_MAC_VER_35:
6628         case RTL_GIGA_MAC_VER_36:
6629                 rtl_hw_start_8168f_1(tp);
6630                 break;
6631
6632         case RTL_GIGA_MAC_VER_38:
6633                 rtl_hw_start_8411(tp);
6634                 break;
6635
6636         case RTL_GIGA_MAC_VER_40:
6637         case RTL_GIGA_MAC_VER_41:
6638                 rtl_hw_start_8168g_1(tp);
6639                 break;
6640         case RTL_GIGA_MAC_VER_42:
6641                 rtl_hw_start_8168g_2(tp);
6642                 break;
6643
6644         case RTL_GIGA_MAC_VER_44:
6645                 rtl_hw_start_8411_2(tp);
6646                 break;
6647
6648         case RTL_GIGA_MAC_VER_45:
6649         case RTL_GIGA_MAC_VER_46:
6650                 rtl_hw_start_8168h_1(tp);
6651                 break;
6652
6653         case RTL_GIGA_MAC_VER_49:
6654                 rtl_hw_start_8168ep_1(tp);
6655                 break;
6656
6657         case RTL_GIGA_MAC_VER_50:
6658                 rtl_hw_start_8168ep_2(tp);
6659                 break;
6660
6661         case RTL_GIGA_MAC_VER_51:
6662                 rtl_hw_start_8168ep_3(tp);
6663                 break;
6664
6665         default:
6666                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6667                         dev->name, tp->mac_version);
6668                 break;
6669         }
6670
6671         RTL_W8(Cfg9346, Cfg9346_Lock);
6672
6673         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6674
6675         rtl_set_rx_mode(dev);
6676
6677         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6678 }
6679
6680 #define R810X_CPCMD_QUIRK_MASK (\
6681         EnableBist | \
6682         Mac_dbgo_oe | \
6683         Force_half_dup | \
6684         Force_rxflow_en | \
6685         Force_txflow_en | \
6686         Cxpl_dbg_sel | \
6687         ASF | \
6688         PktCntrDisable | \
6689         Mac_dbgo_sel)
6690
6691 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6692 {
6693         void __iomem *ioaddr = tp->mmio_addr;
6694         struct pci_dev *pdev = tp->pci_dev;
6695         static const struct ephy_info e_info_8102e_1[] = {
6696                 { 0x01, 0, 0x6e65 },
6697                 { 0x02, 0, 0x091f },
6698                 { 0x03, 0, 0xc2f9 },
6699                 { 0x06, 0, 0xafb5 },
6700                 { 0x07, 0, 0x0e00 },
6701                 { 0x19, 0, 0xec80 },
6702                 { 0x01, 0, 0x2e65 },
6703                 { 0x01, 0, 0x6e65 }
6704         };
6705         u8 cfg1;
6706
6707         rtl_csi_access_enable_2(tp);
6708
6709         RTL_W8(DBG_REG, FIX_NAK_1);
6710
6711         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6712
6713         RTL_W8(Config1,
6714                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6715         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6716
6717         cfg1 = RTL_R8(Config1);
6718         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6719                 RTL_W8(Config1, cfg1 & ~LEDS0);
6720
6721         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6722 }
6723
6724 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6725 {
6726         void __iomem *ioaddr = tp->mmio_addr;
6727         struct pci_dev *pdev = tp->pci_dev;
6728
6729         rtl_csi_access_enable_2(tp);
6730
6731         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6732
6733         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6734         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6735 }
6736
6737 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6738 {
6739         rtl_hw_start_8102e_2(tp);
6740
6741         rtl_ephy_write(tp, 0x03, 0xc2f9);
6742 }
6743
6744 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6745 {
6746         void __iomem *ioaddr = tp->mmio_addr;
6747         static const struct ephy_info e_info_8105e_1[] = {
6748                 { 0x07, 0, 0x4000 },
6749                 { 0x19, 0, 0x0200 },
6750                 { 0x19, 0, 0x0020 },
6751                 { 0x1e, 0, 0x2000 },
6752                 { 0x03, 0, 0x0001 },
6753                 { 0x19, 0, 0x0100 },
6754                 { 0x19, 0, 0x0004 },
6755                 { 0x0a, 0, 0x0020 }
6756         };
6757
6758         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6759         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6760
6761         /* Disable Early Tally Counter */
6762         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6763
6764         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6765         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6766
6767         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6768
6769         rtl_pcie_state_l2l3_enable(tp, false);
6770 }
6771
6772 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6773 {
6774         rtl_hw_start_8105e_1(tp);
6775         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6776 }
6777
6778 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6779 {
6780         void __iomem *ioaddr = tp->mmio_addr;
6781         static const struct ephy_info e_info_8402[] = {
6782                 { 0x19, 0xffff, 0xff64 },
6783                 { 0x1e, 0, 0x4000 }
6784         };
6785
6786         rtl_csi_access_enable_2(tp);
6787
6788         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6789         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6790
6791         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6792         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6793
6794         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6795
6796         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6797
6798         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6799         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6800         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6801         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6802         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6803         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6804         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6805
6806         rtl_pcie_state_l2l3_enable(tp, false);
6807 }
6808
6809 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6810 {
6811         void __iomem *ioaddr = tp->mmio_addr;
6812
6813         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6814         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6815
6816         RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6817         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6818         RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6819
6820         rtl_pcie_state_l2l3_enable(tp, false);
6821 }
6822
6823 static void rtl_hw_start_8101(struct net_device *dev)
6824 {
6825         struct rtl8169_private *tp = netdev_priv(dev);
6826         void __iomem *ioaddr = tp->mmio_addr;
6827         struct pci_dev *pdev = tp->pci_dev;
6828
6829         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6830                 tp->event_slow &= ~RxFIFOOver;
6831
6832         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6833             tp->mac_version == RTL_GIGA_MAC_VER_16)
6834                 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6835                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6836
6837         RTL_W8(Cfg9346, Cfg9346_Unlock);
6838
6839         RTL_W8(MaxTxPacketSize, TxPacketMax);
6840
6841         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6842
6843         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6844         RTL_W16(CPlusCmd, tp->cp_cmd);
6845
6846         rtl_set_rx_tx_desc_registers(tp, ioaddr);
6847
6848         rtl_set_rx_tx_config_registers(tp);
6849
6850         switch (tp->mac_version) {
6851         case RTL_GIGA_MAC_VER_07:
6852                 rtl_hw_start_8102e_1(tp);
6853                 break;
6854
6855         case RTL_GIGA_MAC_VER_08:
6856                 rtl_hw_start_8102e_3(tp);
6857                 break;
6858
6859         case RTL_GIGA_MAC_VER_09:
6860                 rtl_hw_start_8102e_2(tp);
6861                 break;
6862
6863         case RTL_GIGA_MAC_VER_29:
6864                 rtl_hw_start_8105e_1(tp);
6865                 break;
6866         case RTL_GIGA_MAC_VER_30:
6867                 rtl_hw_start_8105e_2(tp);
6868                 break;
6869
6870         case RTL_GIGA_MAC_VER_37:
6871                 rtl_hw_start_8402(tp);
6872                 break;
6873
6874         case RTL_GIGA_MAC_VER_39:
6875                 rtl_hw_start_8106(tp);
6876                 break;
6877         case RTL_GIGA_MAC_VER_43:
6878                 rtl_hw_start_8168g_2(tp);
6879                 break;
6880         case RTL_GIGA_MAC_VER_47:
6881         case RTL_GIGA_MAC_VER_48:
6882                 rtl_hw_start_8168h_1(tp);
6883                 break;
6884         }
6885
6886         RTL_W8(Cfg9346, Cfg9346_Lock);
6887
6888         RTL_W16(IntrMitigate, 0x0000);
6889
6890         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6891
6892         rtl_set_rx_mode(dev);
6893
6894         RTL_R8(IntrMask);
6895
6896         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6897 }
6898
6899 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6900 {
6901         struct rtl8169_private *tp = netdev_priv(dev);
6902
6903         if (new_mtu > ETH_DATA_LEN)
6904                 rtl_hw_jumbo_enable(tp);
6905         else
6906                 rtl_hw_jumbo_disable(tp);
6907
6908         dev->mtu = new_mtu;
6909         netdev_update_features(dev);
6910
6911         return 0;
6912 }
6913
6914 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6915 {
6916         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6917         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6918 }
6919
6920 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6921                                      void **data_buff, struct RxDesc *desc)
6922 {
6923         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6924                          DMA_FROM_DEVICE);
6925
6926         kfree(*data_buff);
6927         *data_buff = NULL;
6928         rtl8169_make_unusable_by_asic(desc);
6929 }
6930
6931 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6932 {
6933         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6934
6935         /* Force memory writes to complete before releasing descriptor */
6936         dma_wmb();
6937
6938         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6939 }
6940
6941 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6942                                        u32 rx_buf_sz)
6943 {
6944         desc->addr = cpu_to_le64(mapping);
6945         rtl8169_mark_to_asic(desc, rx_buf_sz);
6946 }
6947
6948 static inline void *rtl8169_align(void *data)
6949 {
6950         return (void *)ALIGN((long)data, 16);
6951 }
6952
6953 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6954                                              struct RxDesc *desc)
6955 {
6956         void *data;
6957         dma_addr_t mapping;
6958         struct device *d = &tp->pci_dev->dev;
6959         struct net_device *dev = tp->dev;
6960         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6961
6962         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6963         if (!data)
6964                 return NULL;
6965
6966         if (rtl8169_align(data) != data) {
6967                 kfree(data);
6968                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6969                 if (!data)
6970                         return NULL;
6971         }
6972
6973         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6974                                  DMA_FROM_DEVICE);
6975         if (unlikely(dma_mapping_error(d, mapping))) {
6976                 if (net_ratelimit())
6977                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6978                 goto err_out;
6979         }
6980
6981         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6982         return data;
6983
6984 err_out:
6985         kfree(data);
6986         return NULL;
6987 }
6988
6989 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6990 {
6991         unsigned int i;
6992
6993         for (i = 0; i < NUM_RX_DESC; i++) {
6994                 if (tp->Rx_databuff[i]) {
6995                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6996                                             tp->RxDescArray + i);
6997                 }
6998         }
6999 }
7000
7001 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
7002 {
7003         desc->opts1 |= cpu_to_le32(RingEnd);
7004 }
7005
7006 static int rtl8169_rx_fill(struct rtl8169_private *tp)
7007 {
7008         unsigned int i;
7009
7010         for (i = 0; i < NUM_RX_DESC; i++) {
7011                 void *data;
7012
7013                 if (tp->Rx_databuff[i])
7014                         continue;
7015
7016                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
7017                 if (!data) {
7018                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
7019                         goto err_out;
7020                 }
7021                 tp->Rx_databuff[i] = data;
7022         }
7023
7024         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
7025         return 0;
7026
7027 err_out:
7028         rtl8169_rx_clear(tp);
7029         return -ENOMEM;
7030 }
7031
7032 static int rtl8169_init_ring(struct net_device *dev)
7033 {
7034         struct rtl8169_private *tp = netdev_priv(dev);
7035
7036         rtl8169_init_ring_indexes(tp);
7037
7038         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
7039         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
7040
7041         return rtl8169_rx_fill(tp);
7042 }
7043
7044 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
7045                                  struct TxDesc *desc)
7046 {
7047         unsigned int len = tx_skb->len;
7048
7049         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
7050
7051         desc->opts1 = 0x00;
7052         desc->opts2 = 0x00;
7053         desc->addr = 0x00;
7054         tx_skb->len = 0;
7055 }
7056
7057 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
7058                                    unsigned int n)
7059 {
7060         unsigned int i;
7061
7062         for (i = 0; i < n; i++) {
7063                 unsigned int entry = (start + i) % NUM_TX_DESC;
7064                 struct ring_info *tx_skb = tp->tx_skb + entry;
7065                 unsigned int len = tx_skb->len;
7066
7067                 if (len) {
7068                         struct sk_buff *skb = tx_skb->skb;
7069
7070                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7071                                              tp->TxDescArray + entry);
7072                         if (skb) {
7073                                 dev_consume_skb_any(skb);
7074                                 tx_skb->skb = NULL;
7075                         }
7076                 }
7077         }
7078 }
7079
7080 static void rtl8169_tx_clear(struct rtl8169_private *tp)
7081 {
7082         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
7083         tp->cur_tx = tp->dirty_tx = 0;
7084 }
7085
7086 static void rtl_reset_work(struct rtl8169_private *tp)
7087 {
7088         struct net_device *dev = tp->dev;
7089         int i;
7090
7091         napi_disable(&tp->napi);
7092         netif_stop_queue(dev);
7093         synchronize_sched();
7094
7095         rtl8169_hw_reset(tp);
7096
7097         for (i = 0; i < NUM_RX_DESC; i++)
7098                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
7099
7100         rtl8169_tx_clear(tp);
7101         rtl8169_init_ring_indexes(tp);
7102
7103         napi_enable(&tp->napi);
7104         rtl_hw_start(dev);
7105         netif_wake_queue(dev);
7106         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
7107 }
7108
7109 static void rtl8169_tx_timeout(struct net_device *dev)
7110 {
7111         struct rtl8169_private *tp = netdev_priv(dev);
7112
7113         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7114 }
7115
7116 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
7117                               u32 *opts)
7118 {
7119         struct skb_shared_info *info = skb_shinfo(skb);
7120         unsigned int cur_frag, entry;
7121         struct TxDesc *uninitialized_var(txd);
7122         struct device *d = &tp->pci_dev->dev;
7123
7124         entry = tp->cur_tx;
7125         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
7126                 const skb_frag_t *frag = info->frags + cur_frag;
7127                 dma_addr_t mapping;
7128                 u32 status, len;
7129                 void *addr;
7130
7131                 entry = (entry + 1) % NUM_TX_DESC;
7132
7133                 txd = tp->TxDescArray + entry;
7134                 len = skb_frag_size(frag);
7135                 addr = skb_frag_address(frag);
7136                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
7137                 if (unlikely(dma_mapping_error(d, mapping))) {
7138                         if (net_ratelimit())
7139                                 netif_err(tp, drv, tp->dev,
7140                                           "Failed to map TX fragments DMA!\n");
7141                         goto err_out;
7142                 }
7143
7144                 /* Anti gcc 2.95.3 bugware (sic) */
7145                 status = opts[0] | len |
7146                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
7147
7148                 txd->opts1 = cpu_to_le32(status);
7149                 txd->opts2 = cpu_to_le32(opts[1]);
7150                 txd->addr = cpu_to_le64(mapping);
7151
7152                 tp->tx_skb[entry].len = len;
7153         }
7154
7155         if (cur_frag) {
7156                 tp->tx_skb[entry].skb = skb;
7157                 txd->opts1 |= cpu_to_le32(LastFrag);
7158         }
7159
7160         return cur_frag;
7161
7162 err_out:
7163         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
7164         return -EIO;
7165 }
7166
7167 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
7168 {
7169         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
7170 }
7171
7172 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7173                                       struct net_device *dev);
7174 /* r8169_csum_workaround()
7175  * The hw limites the value the transport offset. When the offset is out of the
7176  * range, calculate the checksum by sw.
7177  */
7178 static void r8169_csum_workaround(struct rtl8169_private *tp,
7179                                   struct sk_buff *skb)
7180 {
7181         if (skb_shinfo(skb)->gso_size) {
7182                 netdev_features_t features = tp->dev->features;
7183                 struct sk_buff *segs, *nskb;
7184
7185                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
7186                 segs = skb_gso_segment(skb, features);
7187                 if (IS_ERR(segs) || !segs)
7188                         goto drop;
7189
7190                 do {
7191                         nskb = segs;
7192                         segs = segs->next;
7193                         nskb->next = NULL;
7194                         rtl8169_start_xmit(nskb, tp->dev);
7195                 } while (segs);
7196
7197                 dev_consume_skb_any(skb);
7198         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7199                 if (skb_checksum_help(skb) < 0)
7200                         goto drop;
7201
7202                 rtl8169_start_xmit(skb, tp->dev);
7203         } else {
7204                 struct net_device_stats *stats;
7205
7206 drop:
7207                 stats = &tp->dev->stats;
7208                 stats->tx_dropped++;
7209                 dev_kfree_skb_any(skb);
7210         }
7211 }
7212
7213 /* msdn_giant_send_check()
7214  * According to the document of microsoft, the TCP Pseudo Header excludes the
7215  * packet length for IPv6 TCP large packets.
7216  */
7217 static int msdn_giant_send_check(struct sk_buff *skb)
7218 {
7219         const struct ipv6hdr *ipv6h;
7220         struct tcphdr *th;
7221         int ret;
7222
7223         ret = skb_cow_head(skb, 0);
7224         if (ret)
7225                 return ret;
7226
7227         ipv6h = ipv6_hdr(skb);
7228         th = tcp_hdr(skb);
7229
7230         th->check = 0;
7231         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7232
7233         return ret;
7234 }
7235
7236 static inline __be16 get_protocol(struct sk_buff *skb)
7237 {
7238         __be16 protocol;
7239
7240         if (skb->protocol == htons(ETH_P_8021Q))
7241                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7242         else
7243                 protocol = skb->protocol;
7244
7245         return protocol;
7246 }
7247
7248 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7249                                 struct sk_buff *skb, u32 *opts)
7250 {
7251         u32 mss = skb_shinfo(skb)->gso_size;
7252
7253         if (mss) {
7254                 opts[0] |= TD_LSO;
7255                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7256         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7257                 const struct iphdr *ip = ip_hdr(skb);
7258
7259                 if (ip->protocol == IPPROTO_TCP)
7260                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7261                 else if (ip->protocol == IPPROTO_UDP)
7262                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7263                 else
7264                         WARN_ON_ONCE(1);
7265         }
7266
7267         return true;
7268 }
7269
7270 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7271                                 struct sk_buff *skb, u32 *opts)
7272 {
7273         u32 transport_offset = (u32)skb_transport_offset(skb);
7274         u32 mss = skb_shinfo(skb)->gso_size;
7275
7276         if (mss) {
7277                 if (transport_offset > GTTCPHO_MAX) {
7278                         netif_warn(tp, tx_err, tp->dev,
7279                                    "Invalid transport offset 0x%x for TSO\n",
7280                                    transport_offset);
7281                         return false;
7282                 }
7283
7284                 switch (get_protocol(skb)) {
7285                 case htons(ETH_P_IP):
7286                         opts[0] |= TD1_GTSENV4;
7287                         break;
7288
7289                 case htons(ETH_P_IPV6):
7290                         if (msdn_giant_send_check(skb))
7291                                 return false;
7292
7293                         opts[0] |= TD1_GTSENV6;
7294                         break;
7295
7296                 default:
7297                         WARN_ON_ONCE(1);
7298                         break;
7299                 }
7300
7301                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7302                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7303         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7304                 u8 ip_protocol;
7305
7306                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7307                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7308
7309                 if (transport_offset > TCPHO_MAX) {
7310                         netif_warn(tp, tx_err, tp->dev,
7311                                    "Invalid transport offset 0x%x\n",
7312                                    transport_offset);
7313                         return false;
7314                 }
7315
7316                 switch (get_protocol(skb)) {
7317                 case htons(ETH_P_IP):
7318                         opts[1] |= TD1_IPv4_CS;
7319                         ip_protocol = ip_hdr(skb)->protocol;
7320                         break;
7321
7322                 case htons(ETH_P_IPV6):
7323                         opts[1] |= TD1_IPv6_CS;
7324                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7325                         break;
7326
7327                 default:
7328                         ip_protocol = IPPROTO_RAW;
7329                         break;
7330                 }
7331
7332                 if (ip_protocol == IPPROTO_TCP)
7333                         opts[1] |= TD1_TCP_CS;
7334                 else if (ip_protocol == IPPROTO_UDP)
7335                         opts[1] |= TD1_UDP_CS;
7336                 else
7337                         WARN_ON_ONCE(1);
7338
7339                 opts[1] |= transport_offset << TCPHO_SHIFT;
7340         } else {
7341                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7342                         return !eth_skb_pad(skb);
7343         }
7344
7345         return true;
7346 }
7347
7348 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7349                                       struct net_device *dev)
7350 {
7351         struct rtl8169_private *tp = netdev_priv(dev);
7352         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7353         struct TxDesc *txd = tp->TxDescArray + entry;
7354         void __iomem *ioaddr = tp->mmio_addr;
7355         struct device *d = &tp->pci_dev->dev;
7356         dma_addr_t mapping;
7357         u32 status, len;
7358         u32 opts[2];
7359         int frags;
7360
7361         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7362                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7363                 goto err_stop_0;
7364         }
7365
7366         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7367                 goto err_stop_0;
7368
7369         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7370         opts[0] = DescOwn;
7371
7372         if (!tp->tso_csum(tp, skb, opts)) {
7373                 r8169_csum_workaround(tp, skb);
7374                 return NETDEV_TX_OK;
7375         }
7376
7377         len = skb_headlen(skb);
7378         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7379         if (unlikely(dma_mapping_error(d, mapping))) {
7380                 if (net_ratelimit())
7381                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7382                 goto err_dma_0;
7383         }
7384
7385         tp->tx_skb[entry].len = len;
7386         txd->addr = cpu_to_le64(mapping);
7387
7388         frags = rtl8169_xmit_frags(tp, skb, opts);
7389         if (frags < 0)
7390                 goto err_dma_1;
7391         else if (frags)
7392                 opts[0] |= FirstFrag;
7393         else {
7394                 opts[0] |= FirstFrag | LastFrag;
7395                 tp->tx_skb[entry].skb = skb;
7396         }
7397
7398         txd->opts2 = cpu_to_le32(opts[1]);
7399
7400         skb_tx_timestamp(skb);
7401
7402         /* Force memory writes to complete before releasing descriptor */
7403         dma_wmb();
7404
7405         /* Anti gcc 2.95.3 bugware (sic) */
7406         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7407         txd->opts1 = cpu_to_le32(status);
7408
7409         /* Force all memory writes to complete before notifying device */
7410         wmb();
7411
7412         tp->cur_tx += frags + 1;
7413
7414         RTL_W8(TxPoll, NPQ);
7415
7416         mmiowb();
7417
7418         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7419                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7420                  * not miss a ring update when it notices a stopped queue.
7421                  */
7422                 smp_wmb();
7423                 netif_stop_queue(dev);
7424                 /* Sync with rtl_tx:
7425                  * - publish queue status and cur_tx ring index (write barrier)
7426                  * - refresh dirty_tx ring index (read barrier).
7427                  * May the current thread have a pessimistic view of the ring
7428                  * status and forget to wake up queue, a racing rtl_tx thread
7429                  * can't.
7430                  */
7431                 smp_mb();
7432                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7433                         netif_wake_queue(dev);
7434         }
7435
7436         return NETDEV_TX_OK;
7437
7438 err_dma_1:
7439         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7440 err_dma_0:
7441         dev_kfree_skb_any(skb);
7442         dev->stats.tx_dropped++;
7443         return NETDEV_TX_OK;
7444
7445 err_stop_0:
7446         netif_stop_queue(dev);
7447         dev->stats.tx_dropped++;
7448         return NETDEV_TX_BUSY;
7449 }
7450
7451 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7452 {
7453         struct rtl8169_private *tp = netdev_priv(dev);
7454         struct pci_dev *pdev = tp->pci_dev;
7455         u16 pci_status, pci_cmd;
7456
7457         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7458         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7459
7460         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7461                   pci_cmd, pci_status);
7462
7463         /*
7464          * The recovery sequence below admits a very elaborated explanation:
7465          * - it seems to work;
7466          * - I did not see what else could be done;
7467          * - it makes iop3xx happy.
7468          *
7469          * Feel free to adjust to your needs.
7470          */
7471         if (pdev->broken_parity_status)
7472                 pci_cmd &= ~PCI_COMMAND_PARITY;
7473         else
7474                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7475
7476         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7477
7478         pci_write_config_word(pdev, PCI_STATUS,
7479                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7480                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7481                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7482
7483         /* The infamous DAC f*ckup only happens at boot time */
7484         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7485                 void __iomem *ioaddr = tp->mmio_addr;
7486
7487                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7488                 tp->cp_cmd &= ~PCIDAC;
7489                 RTL_W16(CPlusCmd, tp->cp_cmd);
7490                 dev->features &= ~NETIF_F_HIGHDMA;
7491         }
7492
7493         rtl8169_hw_reset(tp);
7494
7495         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7496 }
7497
7498 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7499 {
7500         unsigned int dirty_tx, tx_left;
7501
7502         dirty_tx = tp->dirty_tx;
7503         smp_rmb();
7504         tx_left = tp->cur_tx - dirty_tx;
7505
7506         while (tx_left > 0) {
7507                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7508                 struct ring_info *tx_skb = tp->tx_skb + entry;
7509                 u32 status;
7510
7511                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7512                 if (status & DescOwn)
7513                         break;
7514
7515                 /* This barrier is needed to keep us from reading
7516                  * any other fields out of the Tx descriptor until
7517                  * we know the status of DescOwn
7518                  */
7519                 dma_rmb();
7520
7521                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7522                                      tp->TxDescArray + entry);
7523                 if (status & LastFrag) {
7524                         u64_stats_update_begin(&tp->tx_stats.syncp);
7525                         tp->tx_stats.packets++;
7526                         tp->tx_stats.bytes += tx_skb->skb->len;
7527                         u64_stats_update_end(&tp->tx_stats.syncp);
7528                         dev_consume_skb_any(tx_skb->skb);
7529                         tx_skb->skb = NULL;
7530                 }
7531                 dirty_tx++;
7532                 tx_left--;
7533         }
7534
7535         if (tp->dirty_tx != dirty_tx) {
7536                 tp->dirty_tx = dirty_tx;
7537                 /* Sync with rtl8169_start_xmit:
7538                  * - publish dirty_tx ring index (write barrier)
7539                  * - refresh cur_tx ring index and queue status (read barrier)
7540                  * May the current thread miss the stopped queue condition,
7541                  * a racing xmit thread can only have a right view of the
7542                  * ring status.
7543                  */
7544                 smp_mb();
7545                 if (netif_queue_stopped(dev) &&
7546                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7547                         netif_wake_queue(dev);
7548                 }
7549                 /*
7550                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7551                  * too close. Let's kick an extra TxPoll request when a burst
7552                  * of start_xmit activity is detected (if it is not detected,
7553                  * it is slow enough). -- FR
7554                  */
7555                 if (tp->cur_tx != dirty_tx) {
7556                         void __iomem *ioaddr = tp->mmio_addr;
7557
7558                         RTL_W8(TxPoll, NPQ);
7559                 }
7560         }
7561 }
7562
7563 static inline int rtl8169_fragmented_frame(u32 status)
7564 {
7565         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7566 }
7567
7568 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7569 {
7570         u32 status = opts1 & RxProtoMask;
7571
7572         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7573             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7574                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7575         else
7576                 skb_checksum_none_assert(skb);
7577 }
7578
7579 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7580                                            struct rtl8169_private *tp,
7581                                            int pkt_size,
7582                                            dma_addr_t addr)
7583 {
7584         struct sk_buff *skb;
7585         struct device *d = &tp->pci_dev->dev;
7586
7587         data = rtl8169_align(data);
7588         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7589         prefetch(data);
7590         skb = napi_alloc_skb(&tp->napi, pkt_size);
7591         if (skb)
7592                 memcpy(skb->data, data, pkt_size);
7593         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7594
7595         return skb;
7596 }
7597
7598 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7599 {
7600         unsigned int cur_rx, rx_left;
7601         unsigned int count;
7602
7603         cur_rx = tp->cur_rx;
7604
7605         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7606                 unsigned int entry = cur_rx % NUM_RX_DESC;
7607                 struct RxDesc *desc = tp->RxDescArray + entry;
7608                 u32 status;
7609
7610                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7611                 if (status & DescOwn)
7612                         break;
7613
7614                 /* This barrier is needed to keep us from reading
7615                  * any other fields out of the Rx descriptor until
7616                  * we know the status of DescOwn
7617                  */
7618                 dma_rmb();
7619
7620                 if (unlikely(status & RxRES)) {
7621                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7622                                    status);
7623                         dev->stats.rx_errors++;
7624                         if (status & (RxRWT | RxRUNT))
7625                                 dev->stats.rx_length_errors++;
7626                         if (status & RxCRC)
7627                                 dev->stats.rx_crc_errors++;
7628                         if (status & RxFOVF) {
7629                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7630                                 dev->stats.rx_fifo_errors++;
7631                         }
7632                         if ((status & (RxRUNT | RxCRC)) &&
7633                             !(status & (RxRWT | RxFOVF)) &&
7634                             (dev->features & NETIF_F_RXALL))
7635                                 goto process_pkt;
7636                 } else {
7637                         struct sk_buff *skb;
7638                         dma_addr_t addr;
7639                         int pkt_size;
7640
7641 process_pkt:
7642                         addr = le64_to_cpu(desc->addr);
7643                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7644                                 pkt_size = (status & 0x00003fff) - 4;
7645                         else
7646                                 pkt_size = status & 0x00003fff;
7647
7648                         /*
7649                          * The driver does not support incoming fragmented
7650                          * frames. They are seen as a symptom of over-mtu
7651                          * sized frames.
7652                          */
7653                         if (unlikely(rtl8169_fragmented_frame(status))) {
7654                                 dev->stats.rx_dropped++;
7655                                 dev->stats.rx_length_errors++;
7656                                 goto release_descriptor;
7657                         }
7658
7659                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7660                                                   tp, pkt_size, addr);
7661                         if (!skb) {
7662                                 dev->stats.rx_dropped++;
7663                                 goto release_descriptor;
7664                         }
7665
7666                         rtl8169_rx_csum(skb, status);
7667                         skb_put(skb, pkt_size);
7668                         skb->protocol = eth_type_trans(skb, dev);
7669
7670                         rtl8169_rx_vlan_tag(desc, skb);
7671
7672                         if (skb->pkt_type == PACKET_MULTICAST)
7673                                 dev->stats.multicast++;
7674
7675                         napi_gro_receive(&tp->napi, skb);
7676
7677                         u64_stats_update_begin(&tp->rx_stats.syncp);
7678                         tp->rx_stats.packets++;
7679                         tp->rx_stats.bytes += pkt_size;
7680                         u64_stats_update_end(&tp->rx_stats.syncp);
7681                 }
7682 release_descriptor:
7683                 desc->opts2 = 0;
7684                 rtl8169_mark_to_asic(desc, rx_buf_sz);
7685         }
7686
7687         count = cur_rx - tp->cur_rx;
7688         tp->cur_rx = cur_rx;
7689
7690         return count;
7691 }
7692
7693 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7694 {
7695         struct net_device *dev = dev_instance;
7696         struct rtl8169_private *tp = netdev_priv(dev);
7697         int handled = 0;
7698         u16 status;
7699
7700         status = rtl_get_events(tp);
7701         if (status && status != 0xffff) {
7702                 status &= RTL_EVENT_NAPI | tp->event_slow;
7703                 if (status) {
7704                         handled = 1;
7705
7706                         rtl_irq_disable(tp);
7707                         napi_schedule(&tp->napi);
7708                 }
7709         }
7710         return IRQ_RETVAL(handled);
7711 }
7712
7713 /*
7714  * Workqueue context.
7715  */
7716 static void rtl_slow_event_work(struct rtl8169_private *tp)
7717 {
7718         struct net_device *dev = tp->dev;
7719         u16 status;
7720
7721         status = rtl_get_events(tp) & tp->event_slow;
7722         rtl_ack_events(tp, status);
7723
7724         if (unlikely(status & RxFIFOOver)) {
7725                 switch (tp->mac_version) {
7726                 /* Work around for rx fifo overflow */
7727                 case RTL_GIGA_MAC_VER_11:
7728                         netif_stop_queue(dev);
7729                         /* XXX - Hack alert. See rtl_task(). */
7730                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7731                 default:
7732                         break;
7733                 }
7734         }
7735
7736         if (unlikely(status & SYSErr))
7737                 rtl8169_pcierr_interrupt(dev);
7738
7739         if (status & LinkChg)
7740                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
7741
7742         rtl_irq_enable_all(tp);
7743 }
7744
7745 static void rtl_task(struct work_struct *work)
7746 {
7747         static const struct {
7748                 int bitnr;
7749                 void (*action)(struct rtl8169_private *);
7750         } rtl_work[] = {
7751                 /* XXX - keep rtl_slow_event_work() as first element. */
7752                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7753                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7754                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7755         };
7756         struct rtl8169_private *tp =
7757                 container_of(work, struct rtl8169_private, wk.work);
7758         struct net_device *dev = tp->dev;
7759         int i;
7760
7761         rtl_lock_work(tp);
7762
7763         if (!netif_running(dev) ||
7764             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7765                 goto out_unlock;
7766
7767         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7768                 bool pending;
7769
7770                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7771                 if (pending)
7772                         rtl_work[i].action(tp);
7773         }
7774
7775 out_unlock:
7776         rtl_unlock_work(tp);
7777 }
7778
7779 static int rtl8169_poll(struct napi_struct *napi, int budget)
7780 {
7781         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7782         struct net_device *dev = tp->dev;
7783         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7784         int work_done= 0;
7785         u16 status;
7786
7787         status = rtl_get_events(tp);
7788         rtl_ack_events(tp, status & ~tp->event_slow);
7789
7790         if (status & RTL_EVENT_NAPI_RX)
7791                 work_done = rtl_rx(dev, tp, (u32) budget);
7792
7793         if (status & RTL_EVENT_NAPI_TX)
7794                 rtl_tx(dev, tp);
7795
7796         if (status & tp->event_slow) {
7797                 enable_mask &= ~tp->event_slow;
7798
7799                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7800         }
7801
7802         if (work_done < budget) {
7803                 napi_complete_done(napi, work_done);
7804
7805                 rtl_irq_enable(tp, enable_mask);
7806                 mmiowb();
7807         }
7808
7809         return work_done;
7810 }
7811
7812 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7813 {
7814         struct rtl8169_private *tp = netdev_priv(dev);
7815
7816         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7817                 return;
7818
7819         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7820         RTL_W32(RxMissed, 0);
7821 }
7822
7823 static void rtl8169_down(struct net_device *dev)
7824 {
7825         struct rtl8169_private *tp = netdev_priv(dev);
7826         void __iomem *ioaddr = tp->mmio_addr;
7827
7828         del_timer_sync(&tp->timer);
7829
7830         napi_disable(&tp->napi);
7831         netif_stop_queue(dev);
7832
7833         rtl8169_hw_reset(tp);
7834         /*
7835          * At this point device interrupts can not be enabled in any function,
7836          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7837          * and napi is disabled (rtl8169_poll).
7838          */
7839         rtl8169_rx_missed(dev, ioaddr);
7840
7841         /* Give a racing hard_start_xmit a few cycles to complete. */
7842         synchronize_sched();
7843
7844         rtl8169_tx_clear(tp);
7845
7846         rtl8169_rx_clear(tp);
7847
7848         rtl_pll_power_down(tp);
7849 }
7850
7851 static int rtl8169_close(struct net_device *dev)
7852 {
7853         struct rtl8169_private *tp = netdev_priv(dev);
7854         struct pci_dev *pdev = tp->pci_dev;
7855
7856         pm_runtime_get_sync(&pdev->dev);
7857
7858         /* Update counters before going down */
7859         rtl8169_update_counters(dev);
7860
7861         rtl_lock_work(tp);
7862         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7863
7864         rtl8169_down(dev);
7865         rtl_unlock_work(tp);
7866
7867         cancel_work_sync(&tp->wk.work);
7868
7869         free_irq(pdev->irq, dev);
7870
7871         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7872                           tp->RxPhyAddr);
7873         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7874                           tp->TxPhyAddr);
7875         tp->TxDescArray = NULL;
7876         tp->RxDescArray = NULL;
7877
7878         pm_runtime_put_sync(&pdev->dev);
7879
7880         return 0;
7881 }
7882
7883 #ifdef CONFIG_NET_POLL_CONTROLLER
7884 static void rtl8169_netpoll(struct net_device *dev)
7885 {
7886         struct rtl8169_private *tp = netdev_priv(dev);
7887
7888         rtl8169_interrupt(tp->pci_dev->irq, dev);
7889 }
7890 #endif
7891
7892 static int rtl_open(struct net_device *dev)
7893 {
7894         struct rtl8169_private *tp = netdev_priv(dev);
7895         void __iomem *ioaddr = tp->mmio_addr;
7896         struct pci_dev *pdev = tp->pci_dev;
7897         int retval = -ENOMEM;
7898
7899         pm_runtime_get_sync(&pdev->dev);
7900
7901         /*
7902          * Rx and Tx descriptors needs 256 bytes alignment.
7903          * dma_alloc_coherent provides more.
7904          */
7905         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7906                                              &tp->TxPhyAddr, GFP_KERNEL);
7907         if (!tp->TxDescArray)
7908                 goto err_pm_runtime_put;
7909
7910         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7911                                              &tp->RxPhyAddr, GFP_KERNEL);
7912         if (!tp->RxDescArray)
7913                 goto err_free_tx_0;
7914
7915         retval = rtl8169_init_ring(dev);
7916         if (retval < 0)
7917                 goto err_free_rx_1;
7918
7919         INIT_WORK(&tp->wk.work, rtl_task);
7920
7921         smp_mb();
7922
7923         rtl_request_firmware(tp);
7924
7925         retval = request_irq(pdev->irq, rtl8169_interrupt,
7926                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7927                              dev->name, dev);
7928         if (retval < 0)
7929                 goto err_release_fw_2;
7930
7931         rtl_lock_work(tp);
7932
7933         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7934
7935         napi_enable(&tp->napi);
7936
7937         rtl8169_init_phy(dev, tp);
7938
7939         __rtl8169_set_features(dev, dev->features);
7940
7941         rtl_pll_power_up(tp);
7942
7943         rtl_hw_start(dev);
7944
7945         if (!rtl8169_init_counter_offsets(dev))
7946                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7947
7948         netif_start_queue(dev);
7949
7950         rtl_unlock_work(tp);
7951
7952         tp->saved_wolopts = 0;
7953         pm_runtime_put_sync(&pdev->dev);
7954
7955         rtl8169_check_link_status(dev, tp, ioaddr);
7956 out:
7957         return retval;
7958
7959 err_release_fw_2:
7960         rtl_release_firmware(tp);
7961         rtl8169_rx_clear(tp);
7962 err_free_rx_1:
7963         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7964                           tp->RxPhyAddr);
7965         tp->RxDescArray = NULL;
7966 err_free_tx_0:
7967         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7968                           tp->TxPhyAddr);
7969         tp->TxDescArray = NULL;
7970 err_pm_runtime_put:
7971         pm_runtime_put_noidle(&pdev->dev);
7972         goto out;
7973 }
7974
7975 static void
7976 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7977 {
7978         struct rtl8169_private *tp = netdev_priv(dev);
7979         void __iomem *ioaddr = tp->mmio_addr;
7980         struct pci_dev *pdev = tp->pci_dev;
7981         struct rtl8169_counters *counters = tp->counters;
7982         unsigned int start;
7983
7984         pm_runtime_get_noresume(&pdev->dev);
7985
7986         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7987                 rtl8169_rx_missed(dev, ioaddr);
7988
7989         do {
7990                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7991                 stats->rx_packets = tp->rx_stats.packets;
7992                 stats->rx_bytes = tp->rx_stats.bytes;
7993         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7994
7995         do {
7996                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7997                 stats->tx_packets = tp->tx_stats.packets;
7998                 stats->tx_bytes = tp->tx_stats.bytes;
7999         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8000
8001         stats->rx_dropped       = dev->stats.rx_dropped;
8002         stats->tx_dropped       = dev->stats.tx_dropped;
8003         stats->rx_length_errors = dev->stats.rx_length_errors;
8004         stats->rx_errors        = dev->stats.rx_errors;
8005         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
8006         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
8007         stats->rx_missed_errors = dev->stats.rx_missed_errors;
8008         stats->multicast        = dev->stats.multicast;
8009
8010         /*
8011          * Fetch additonal counter values missing in stats collected by driver
8012          * from tally counters.
8013          */
8014         if (pm_runtime_active(&pdev->dev))
8015                 rtl8169_update_counters(dev);
8016
8017         /*
8018          * Subtract values fetched during initalization.
8019          * See rtl8169_init_counter_offsets for a description why we do that.
8020          */
8021         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
8022                 le64_to_cpu(tp->tc_offset.tx_errors);
8023         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
8024                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
8025         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
8026                 le16_to_cpu(tp->tc_offset.tx_aborted);
8027
8028         pm_runtime_put_noidle(&pdev->dev);
8029 }
8030
8031 static void rtl8169_net_suspend(struct net_device *dev)
8032 {
8033         struct rtl8169_private *tp = netdev_priv(dev);
8034
8035         if (!netif_running(dev))
8036                 return;
8037
8038         netif_device_detach(dev);
8039         netif_stop_queue(dev);
8040
8041         rtl_lock_work(tp);
8042         napi_disable(&tp->napi);
8043         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
8044         rtl_unlock_work(tp);
8045
8046         rtl_pll_power_down(tp);
8047 }
8048
8049 #ifdef CONFIG_PM
8050
8051 static int rtl8169_suspend(struct device *device)
8052 {
8053         struct pci_dev *pdev = to_pci_dev(device);
8054         struct net_device *dev = pci_get_drvdata(pdev);
8055
8056         rtl8169_net_suspend(dev);
8057
8058         return 0;
8059 }
8060
8061 static void __rtl8169_resume(struct net_device *dev)
8062 {
8063         struct rtl8169_private *tp = netdev_priv(dev);
8064
8065         netif_device_attach(dev);
8066
8067         rtl_pll_power_up(tp);
8068
8069         rtl_lock_work(tp);
8070         napi_enable(&tp->napi);
8071         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
8072         rtl_unlock_work(tp);
8073
8074         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
8075 }
8076
8077 static int rtl8169_resume(struct device *device)
8078 {
8079         struct pci_dev *pdev = to_pci_dev(device);
8080         struct net_device *dev = pci_get_drvdata(pdev);
8081         struct rtl8169_private *tp = netdev_priv(dev);
8082
8083         rtl8169_init_phy(dev, tp);
8084
8085         if (netif_running(dev))
8086                 __rtl8169_resume(dev);
8087
8088         return 0;
8089 }
8090
8091 static int rtl8169_runtime_suspend(struct device *device)
8092 {
8093         struct pci_dev *pdev = to_pci_dev(device);
8094         struct net_device *dev = pci_get_drvdata(pdev);
8095         struct rtl8169_private *tp = netdev_priv(dev);
8096
8097         if (!tp->TxDescArray) {
8098                 rtl_pll_power_down(tp);
8099                 return 0;
8100         }
8101
8102         rtl_lock_work(tp);
8103         tp->saved_wolopts = __rtl8169_get_wol(tp);
8104         __rtl8169_set_wol(tp, WAKE_ANY);
8105         rtl_unlock_work(tp);
8106
8107         rtl8169_net_suspend(dev);
8108
8109         /* Update counters before going runtime suspend */
8110         rtl8169_rx_missed(dev, tp->mmio_addr);
8111         rtl8169_update_counters(dev);
8112
8113         return 0;
8114 }
8115
8116 static int rtl8169_runtime_resume(struct device *device)
8117 {
8118         struct pci_dev *pdev = to_pci_dev(device);
8119         struct net_device *dev = pci_get_drvdata(pdev);
8120         struct rtl8169_private *tp = netdev_priv(dev);
8121         rtl_rar_set(tp, dev->dev_addr);
8122
8123         if (!tp->TxDescArray)
8124                 return 0;
8125
8126         rtl_lock_work(tp);
8127         __rtl8169_set_wol(tp, tp->saved_wolopts);
8128         tp->saved_wolopts = 0;
8129         rtl_unlock_work(tp);
8130
8131         rtl8169_init_phy(dev, tp);
8132
8133         __rtl8169_resume(dev);
8134
8135         return 0;
8136 }
8137
8138 static int rtl8169_runtime_idle(struct device *device)
8139 {
8140         struct pci_dev *pdev = to_pci_dev(device);
8141         struct net_device *dev = pci_get_drvdata(pdev);
8142
8143         if (!netif_running(dev) || !netif_carrier_ok(dev))
8144                 pm_schedule_suspend(device, 10000);
8145
8146         return -EBUSY;
8147 }
8148
8149 static const struct dev_pm_ops rtl8169_pm_ops = {
8150         .suspend                = rtl8169_suspend,
8151         .resume                 = rtl8169_resume,
8152         .freeze                 = rtl8169_suspend,
8153         .thaw                   = rtl8169_resume,
8154         .poweroff               = rtl8169_suspend,
8155         .restore                = rtl8169_resume,
8156         .runtime_suspend        = rtl8169_runtime_suspend,
8157         .runtime_resume         = rtl8169_runtime_resume,
8158         .runtime_idle           = rtl8169_runtime_idle,
8159 };
8160
8161 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
8162
8163 #else /* !CONFIG_PM */
8164
8165 #define RTL8169_PM_OPS  NULL
8166
8167 #endif /* !CONFIG_PM */
8168
8169 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
8170 {
8171         void __iomem *ioaddr = tp->mmio_addr;
8172
8173         /* WoL fails with 8168b when the receiver is disabled. */
8174         switch (tp->mac_version) {
8175         case RTL_GIGA_MAC_VER_11:
8176         case RTL_GIGA_MAC_VER_12:
8177         case RTL_GIGA_MAC_VER_17:
8178                 pci_clear_master(tp->pci_dev);
8179
8180                 RTL_W8(ChipCmd, CmdRxEnb);
8181                 /* PCI commit */
8182                 RTL_R8(ChipCmd);
8183                 break;
8184         default:
8185                 break;
8186         }
8187 }
8188
8189 static void rtl_shutdown(struct pci_dev *pdev)
8190 {
8191         struct net_device *dev = pci_get_drvdata(pdev);
8192         struct rtl8169_private *tp = netdev_priv(dev);
8193
8194         rtl8169_net_suspend(dev);
8195
8196         /* Restore original MAC address */
8197         rtl_rar_set(tp, dev->perm_addr);
8198
8199         rtl8169_hw_reset(tp);
8200
8201         if (system_state == SYSTEM_POWER_OFF) {
8202                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
8203                         rtl_wol_suspend_quirk(tp);
8204                         rtl_wol_shutdown_quirk(tp);
8205                 }
8206
8207                 pci_wake_from_d3(pdev, true);
8208                 pci_set_power_state(pdev, PCI_D3hot);
8209         }
8210 }
8211
8212 static void rtl_remove_one(struct pci_dev *pdev)
8213 {
8214         struct net_device *dev = pci_get_drvdata(pdev);
8215         struct rtl8169_private *tp = netdev_priv(dev);
8216
8217         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8218              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8219              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8220              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8221              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8222              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8223             r8168_check_dash(tp)) {
8224                 rtl8168_driver_stop(tp);
8225         }
8226
8227         netif_napi_del(&tp->napi);
8228
8229         unregister_netdev(dev);
8230
8231         rtl_release_firmware(tp);
8232
8233         if (pci_dev_run_wake(pdev))
8234                 pm_runtime_get_noresume(&pdev->dev);
8235
8236         /* restore original MAC address */
8237         rtl_rar_set(tp, dev->perm_addr);
8238 }
8239
8240 static const struct net_device_ops rtl_netdev_ops = {
8241         .ndo_open               = rtl_open,
8242         .ndo_stop               = rtl8169_close,
8243         .ndo_get_stats64        = rtl8169_get_stats64,
8244         .ndo_start_xmit         = rtl8169_start_xmit,
8245         .ndo_tx_timeout         = rtl8169_tx_timeout,
8246         .ndo_validate_addr      = eth_validate_addr,
8247         .ndo_change_mtu         = rtl8169_change_mtu,
8248         .ndo_fix_features       = rtl8169_fix_features,
8249         .ndo_set_features       = rtl8169_set_features,
8250         .ndo_set_mac_address    = rtl_set_mac_address,
8251         .ndo_do_ioctl           = rtl8169_ioctl,
8252         .ndo_set_rx_mode        = rtl_set_rx_mode,
8253 #ifdef CONFIG_NET_POLL_CONTROLLER
8254         .ndo_poll_controller    = rtl8169_netpoll,
8255 #endif
8256
8257 };
8258
8259 static const struct rtl_cfg_info {
8260         void (*hw_start)(struct net_device *);
8261         unsigned int region;
8262         unsigned int align;
8263         u16 event_slow;
8264         unsigned features;
8265         const struct rtl_coalesce_info *coalesce_info;
8266         u8 default_ver;
8267 } rtl_cfg_infos [] = {
8268         [RTL_CFG_0] = {
8269                 .hw_start       = rtl_hw_start_8169,
8270                 .region         = 1,
8271                 .align          = 0,
8272                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8273                 .features       = RTL_FEATURE_GMII,
8274                 .coalesce_info  = rtl_coalesce_info_8169,
8275                 .default_ver    = RTL_GIGA_MAC_VER_01,
8276         },
8277         [RTL_CFG_1] = {
8278                 .hw_start       = rtl_hw_start_8168,
8279                 .region         = 2,
8280                 .align          = 8,
8281                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8282                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8283                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8284                 .default_ver    = RTL_GIGA_MAC_VER_11,
8285         },
8286         [RTL_CFG_2] = {
8287                 .hw_start       = rtl_hw_start_8101,
8288                 .region         = 2,
8289                 .align          = 8,
8290                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8291                                   PCSTimeout,
8292                 .features       = RTL_FEATURE_MSI,
8293                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8294                 .default_ver    = RTL_GIGA_MAC_VER_13,
8295         }
8296 };
8297
8298 /* Cfg9346_Unlock assumed. */
8299 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8300                             const struct rtl_cfg_info *cfg)
8301 {
8302         void __iomem *ioaddr = tp->mmio_addr;
8303         unsigned msi = 0;
8304         u8 cfg2;
8305
8306         cfg2 = RTL_R8(Config2) & ~MSIEnable;
8307         if (cfg->features & RTL_FEATURE_MSI) {
8308                 if (pci_enable_msi(tp->pci_dev)) {
8309                         netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8310                 } else {
8311                         cfg2 |= MSIEnable;
8312                         msi = RTL_FEATURE_MSI;
8313                 }
8314         }
8315         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8316                 RTL_W8(Config2, cfg2);
8317         return msi;
8318 }
8319
8320 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8321 {
8322         void __iomem *ioaddr = tp->mmio_addr;
8323
8324         return RTL_R8(MCU) & LINK_LIST_RDY;
8325 }
8326
8327 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8328 {
8329         void __iomem *ioaddr = tp->mmio_addr;
8330
8331         return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8332 }
8333
8334 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8335 {
8336         void __iomem *ioaddr = tp->mmio_addr;
8337         u32 data;
8338
8339         tp->ocp_base = OCP_STD_PHY_BASE;
8340
8341         RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8342
8343         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8344                 return;
8345
8346         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8347                 return;
8348
8349         RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8350         msleep(1);
8351         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8352
8353         data = r8168_mac_ocp_read(tp, 0xe8de);
8354         data &= ~(1 << 14);
8355         r8168_mac_ocp_write(tp, 0xe8de, data);
8356
8357         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8358                 return;
8359
8360         data = r8168_mac_ocp_read(tp, 0xe8de);
8361         data |= (1 << 15);
8362         r8168_mac_ocp_write(tp, 0xe8de, data);
8363
8364         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8365                 return;
8366 }
8367
8368 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8369 {
8370         rtl8168ep_stop_cmac(tp);
8371         rtl_hw_init_8168g(tp);
8372 }
8373
8374 static void rtl_hw_initialize(struct rtl8169_private *tp)
8375 {
8376         switch (tp->mac_version) {
8377         case RTL_GIGA_MAC_VER_40:
8378         case RTL_GIGA_MAC_VER_41:
8379         case RTL_GIGA_MAC_VER_42:
8380         case RTL_GIGA_MAC_VER_43:
8381         case RTL_GIGA_MAC_VER_44:
8382         case RTL_GIGA_MAC_VER_45:
8383         case RTL_GIGA_MAC_VER_46:
8384         case RTL_GIGA_MAC_VER_47:
8385         case RTL_GIGA_MAC_VER_48:
8386                 rtl_hw_init_8168g(tp);
8387                 break;
8388         case RTL_GIGA_MAC_VER_49:
8389         case RTL_GIGA_MAC_VER_50:
8390         case RTL_GIGA_MAC_VER_51:
8391                 rtl_hw_init_8168ep(tp);
8392                 break;
8393         default:
8394                 break;
8395         }
8396 }
8397
8398 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8399 {
8400         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8401         const unsigned int region = cfg->region;
8402         struct rtl8169_private *tp;
8403         struct mii_if_info *mii;
8404         struct net_device *dev;
8405         void __iomem *ioaddr;
8406         int chipset, i;
8407         int rc;
8408
8409         if (netif_msg_drv(&debug)) {
8410                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8411                        MODULENAME, RTL8169_VERSION);
8412         }
8413
8414         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8415         if (!dev)
8416                 return -ENOMEM;
8417
8418         SET_NETDEV_DEV(dev, &pdev->dev);
8419         dev->netdev_ops = &rtl_netdev_ops;
8420         tp = netdev_priv(dev);
8421         tp->dev = dev;
8422         tp->pci_dev = pdev;
8423         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8424
8425         mii = &tp->mii;
8426         mii->dev = dev;
8427         mii->mdio_read = rtl_mdio_read;
8428         mii->mdio_write = rtl_mdio_write;
8429         mii->phy_id_mask = 0x1f;
8430         mii->reg_num_mask = 0x1f;
8431         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8432
8433         /* disable ASPM completely as that cause random device stop working
8434          * problems as well as full system hangs for some PCIe devices users */
8435         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8436                                      PCIE_LINK_STATE_CLKPM);
8437
8438         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8439         rc = pcim_enable_device(pdev);
8440         if (rc < 0) {
8441                 netif_err(tp, probe, dev, "enable failure\n");
8442                 return rc;
8443         }
8444
8445         if (pcim_set_mwi(pdev) < 0)
8446                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8447
8448         /* make sure PCI base addr 1 is MMIO */
8449         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8450                 netif_err(tp, probe, dev,
8451                           "region #%d not an MMIO resource, aborting\n",
8452                           region);
8453                 return -ENODEV;
8454         }
8455
8456         /* check for weird/broken PCI region reporting */
8457         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8458                 netif_err(tp, probe, dev,
8459                           "Invalid PCI region size(s), aborting\n");
8460                 return -ENODEV;
8461         }
8462
8463         rc = pci_request_regions(pdev, MODULENAME);
8464         if (rc < 0) {
8465                 netif_err(tp, probe, dev, "could not request regions\n");
8466                 return rc;
8467         }
8468
8469         /* ioremap MMIO region */
8470         ioaddr = devm_ioremap(&pdev->dev, pci_resource_start(pdev, region),
8471                               R8169_REGS_SIZE);
8472         if (!ioaddr) {
8473                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8474                 return -EIO;
8475         }
8476         tp->mmio_addr = ioaddr;
8477
8478         if (!pci_is_pcie(pdev))
8479                 netif_info(tp, probe, dev, "not PCI Express\n");
8480
8481         /* Identify chip attached to board */
8482         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8483
8484         tp->cp_cmd = 0;
8485
8486         if ((sizeof(dma_addr_t) > 4) &&
8487             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8488                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8489             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8490             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8491
8492                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8493                 if (!pci_is_pcie(pdev))
8494                         tp->cp_cmd |= PCIDAC;
8495                 dev->features |= NETIF_F_HIGHDMA;
8496         } else {
8497                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8498                 if (rc < 0) {
8499                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8500                         return rc;
8501                 }
8502         }
8503
8504         rtl_init_rxcfg(tp);
8505
8506         rtl_irq_disable(tp);
8507
8508         rtl_hw_initialize(tp);
8509
8510         rtl_hw_reset(tp);
8511
8512         rtl_ack_events(tp, 0xffff);
8513
8514         pci_set_master(pdev);
8515
8516         rtl_init_mdio_ops(tp);
8517         rtl_init_pll_power_ops(tp);
8518         rtl_init_jumbo_ops(tp);
8519         rtl_init_csi_ops(tp);
8520
8521         rtl8169_print_mac_version(tp);
8522
8523         chipset = tp->mac_version;
8524         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8525
8526         RTL_W8(Cfg9346, Cfg9346_Unlock);
8527         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8528         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8529         switch (tp->mac_version) {
8530         case RTL_GIGA_MAC_VER_34:
8531         case RTL_GIGA_MAC_VER_35:
8532         case RTL_GIGA_MAC_VER_36:
8533         case RTL_GIGA_MAC_VER_37:
8534         case RTL_GIGA_MAC_VER_38:
8535         case RTL_GIGA_MAC_VER_40:
8536         case RTL_GIGA_MAC_VER_41:
8537         case RTL_GIGA_MAC_VER_42:
8538         case RTL_GIGA_MAC_VER_43:
8539         case RTL_GIGA_MAC_VER_44:
8540         case RTL_GIGA_MAC_VER_45:
8541         case RTL_GIGA_MAC_VER_46:
8542         case RTL_GIGA_MAC_VER_47:
8543         case RTL_GIGA_MAC_VER_48:
8544         case RTL_GIGA_MAC_VER_49:
8545         case RTL_GIGA_MAC_VER_50:
8546         case RTL_GIGA_MAC_VER_51:
8547                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8548                         tp->features |= RTL_FEATURE_WOL;
8549                 if ((RTL_R8(Config3) & LinkUp) != 0)
8550                         tp->features |= RTL_FEATURE_WOL;
8551                 break;
8552         default:
8553                 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8554                         tp->features |= RTL_FEATURE_WOL;
8555                 break;
8556         }
8557         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8558                 tp->features |= RTL_FEATURE_WOL;
8559         tp->features |= rtl_try_msi(tp, cfg);
8560         RTL_W8(Cfg9346, Cfg9346_Lock);
8561
8562         if (rtl_tbi_enabled(tp)) {
8563                 tp->set_speed = rtl8169_set_speed_tbi;
8564                 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8565                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8566                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8567                 tp->link_ok = rtl8169_tbi_link_ok;
8568                 tp->do_ioctl = rtl_tbi_ioctl;
8569         } else {
8570                 tp->set_speed = rtl8169_set_speed_xmii;
8571                 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8572                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8573                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8574                 tp->link_ok = rtl8169_xmii_link_ok;
8575                 tp->do_ioctl = rtl_xmii_ioctl;
8576         }
8577
8578         mutex_init(&tp->wk.mutex);
8579         u64_stats_init(&tp->rx_stats.syncp);
8580         u64_stats_init(&tp->tx_stats.syncp);
8581
8582         /* Get MAC address */
8583         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8584             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8585             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8586             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8587             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8588             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8589             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8590             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8591             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8592             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8593             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8594             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8595             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8596             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8597             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8598             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8599                 u16 mac_addr[3];
8600
8601                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8602                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8603
8604                 if (is_valid_ether_addr((u8 *)mac_addr))
8605                         rtl_rar_set(tp, (u8 *)mac_addr);
8606         }
8607         for (i = 0; i < ETH_ALEN; i++)
8608                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8609
8610         dev->ethtool_ops = &rtl8169_ethtool_ops;
8611         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8612
8613         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8614
8615         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8616          * properly for all devices */
8617         dev->features |= NETIF_F_RXCSUM |
8618                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8619
8620         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8621                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8622                 NETIF_F_HW_VLAN_CTAG_RX;
8623         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8624                 NETIF_F_HIGHDMA;
8625
8626         tp->cp_cmd |= RxChkSum | RxVlan;
8627
8628         /*
8629          * Pretend we are using VLANs; This bypasses a nasty bug where
8630          * Interrupts stop flowing on high load on 8110SCd controllers.
8631          */
8632         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8633                 /* Disallow toggling */
8634                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8635
8636         if (tp->txd_version == RTL_TD_0)
8637                 tp->tso_csum = rtl8169_tso_csum_v1;
8638         else if (tp->txd_version == RTL_TD_1) {
8639                 tp->tso_csum = rtl8169_tso_csum_v2;
8640                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8641         } else
8642                 WARN_ON_ONCE(1);
8643
8644         dev->hw_features |= NETIF_F_RXALL;
8645         dev->hw_features |= NETIF_F_RXFCS;
8646
8647         /* MTU range: 60 - hw-specific max */
8648         dev->min_mtu = ETH_ZLEN;
8649         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8650
8651         tp->hw_start = cfg->hw_start;
8652         tp->event_slow = cfg->event_slow;
8653         tp->coalesce_info = cfg->coalesce_info;
8654
8655         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8656                 ~(RxBOVF | RxFOVF) : ~0;
8657
8658         timer_setup(&tp->timer, rtl8169_phy_timer, 0);
8659
8660         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8661
8662         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8663                                             &tp->counters_phys_addr,
8664                                             GFP_KERNEL);
8665         if (!tp->counters)
8666                 return -ENOMEM;
8667
8668         rc = register_netdev(dev);
8669         if (rc < 0)
8670                 return rc;
8671
8672         pci_set_drvdata(pdev, dev);
8673
8674         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8675                    rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8676                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8677         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8678                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8679                            "tx checksumming: %s]\n",
8680                            rtl_chip_infos[chipset].jumbo_max,
8681                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8682         }
8683
8684         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8685              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8686              tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8687              tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8688              tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8689              tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8690             r8168_check_dash(tp)) {
8691                 rtl8168_driver_start(tp);
8692         }
8693
8694         netif_carrier_off(dev);
8695
8696         if (pci_dev_run_wake(pdev))
8697                 pm_runtime_put_sync(&pdev->dev);
8698
8699         return 0;
8700 }
8701
8702 static struct pci_driver rtl8169_pci_driver = {
8703         .name           = MODULENAME,
8704         .id_table       = rtl8169_pci_tbl,
8705         .probe          = rtl_init_one,
8706         .remove         = rtl_remove_one,
8707         .shutdown       = rtl_shutdown,
8708         .driver.pm      = RTL8169_PM_OPS,
8709 };
8710
8711 module_pci_driver(rtl8169_pci_driver);