drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492
 493         /* rtl8169_PHYstatus */
 494         TBI_Enable      = 0x80,
 495         TxFlowCtrl      = 0x40,
 496         RxFlowCtrl      = 0x20,
 497         _1000bpsF       = 0x10,
 498         _100bps         = 0x08,
 499         _10bps          = 0x04,
 500         LinkStatus      = 0x02,
 501         FullDup         = 0x01,
 502
 503         /* ResetCounterCommand */
 504         CounterReset    = 0x1,
 505
 506         /* DumpCounterCommand */
 507         CounterDump     = 0x8,
 508
 509         /* magic enable v2 */
 510         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 511 };
 512
 513 enum rtl_desc_bit {
 514         /* First doubleword. */
 515         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 516         RingEnd         = (1 << 30), /* End of descriptor ring */
 517         FirstFrag       = (1 << 29), /* First segment of a packet */
 518         LastFrag        = (1 << 28), /* Final segment of a packet */
 519 };
 520
 521 /* Generic case. */
 522 enum rtl_tx_desc_bit {
 523         /* First doubleword. */
 524         TD_LSO          = (1 << 27),            /* Large Send Offload */
 525 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 526
 527         /* Second doubleword. */
 528         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 529 };
 530
 531 /* 8169, 8168b and 810x except 8102e. */
 532 enum rtl_tx_desc_bit_0 {
 533         /* First doubleword. */
 534 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 535         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 536         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 537         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 538 };
 539
 540 /* 8102e, 8168c and beyond. */
 541 enum rtl_tx_desc_bit_1 {
 542         /* First doubleword. */
 543         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 544         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 545 #define GTTCPHO_SHIFT                   18
 546 #define GTTCPHO_MAX                     0x7fU
 547
 548         /* Second doubleword. */
 549 #define TCPHO_SHIFT                     18
 550 #define TCPHO_MAX                       0x3ffU
 551 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 552         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 553         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 554         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 555         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 556 };
 557
 558 enum rtl_rx_desc_bit {
 559         /* Rx private */
 560         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 561         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 562
 563 #define RxProtoUDP      (PID1)
 564 #define RxProtoTCP      (PID0)
 565 #define RxProtoIP       (PID1 | PID0)
 566 #define RxProtoMask     RxProtoIP
 567
 568         IPFail          = (1 << 16), /* IP checksum failed */
 569         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 570         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 571         RxVlanTag       = (1 << 16), /* VLAN tag available */
 572 };
 573
 574 #define RsvdMask        0x3fffc000
 575 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 576
 577 struct TxDesc {
 578         __le32 opts1;
 579         __le32 opts2;
 580         __le64 addr;
 581 };
 582
 583 struct RxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct ring_info {
 590         struct sk_buff  *skb;
 591         u32             len;
 592 };
 593
 594 struct rtl8169_counters {
 595         __le64  tx_packets;
 596         __le64  rx_packets;
 597         __le64  tx_errors;
 598         __le32  rx_errors;
 599         __le16  rx_missed;
 600         __le16  align_errors;
 601         __le32  tx_one_collision;
 602         __le32  tx_multi_collision;
 603         __le64  rx_unicast;
 604         __le64  rx_broadcast;
 605         __le32  rx_multicast;
 606         __le16  tx_aborted;
 607         __le16  tx_underun;
 608 };
 609
 610 struct rtl8169_tc_offsets {
 611         bool    inited;
 612         __le64  tx_errors;
 613         __le32  tx_multi_collision;
 614         __le16  tx_aborted;
 615 };
 616
 617 enum rtl_flag {
 618         RTL_FLAG_TASK_ENABLED = 0,
 619         RTL_FLAG_TASK_RESET_PENDING,
 620         RTL_FLAG_MAX
 621 };
 622
 623 struct rtl8169_stats {
 624         u64                     packets;
 625         u64                     bytes;
 626         struct u64_stats_sync   syncp;
 627 };
 628
 629 struct rtl8169_private;
 630 typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val);
 631 typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg);
 632
 633 struct rtl8169_private {
 634         void __iomem *mmio_addr;        /* memory map physical address */
 635         struct pci_dev *pci_dev;
 636         struct net_device *dev;
 637         struct phy_device *phydev;
 638         struct napi_struct napi;
 639         u32 msg_enable;
 640         enum mac_version mac_version;
 641         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 642         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 643         u32 dirty_tx;
 644         struct rtl8169_stats rx_stats;
 645         struct rtl8169_stats tx_stats;
 646         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 647         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 648         dma_addr_t TxPhyAddr;
 649         dma_addr_t RxPhyAddr;
 650         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 651         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 652         u16 cp_cmd;
 653
 654         u16 irq_mask;
 655         const struct rtl_coalesce_info *coalesce_info;
 656         struct clk *clk;
 657
 658         struct jumbo_ops {
 659                 void (*enable)(struct rtl8169_private *);
 660                 void (*disable)(struct rtl8169_private *);
 661         } jumbo_ops;
 662
 663         void (*hw_start)(struct rtl8169_private *tp);
 664         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 665
 666         struct {
 667                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 668                 struct mutex mutex;
 669                 struct work_struct work;
 670         } wk;
 671
 672         unsigned irq_enabled:1;
 673         unsigned supports_gmii:1;
 674         dma_addr_t counters_phys_addr;
 675         struct rtl8169_counters *counters;
 676         struct rtl8169_tc_offsets tc_offset;
 677         u32 saved_wolopts;
 678
 679         const char *fw_name;
 680         struct rtl_fw {
 681                 rtl_fw_write_t phy_write;
 682                 rtl_fw_read_t phy_read;
 683                 rtl_fw_write_t mac_mcu_write;
 684                 rtl_fw_read_t mac_mcu_read;
 685                 const struct firmware *fw;
 686
 687 #define RTL_VER_SIZE            32
 688
 689                 char version[RTL_VER_SIZE];
 690
 691                 struct rtl_fw_phy_action {
 692                         __le32 *code;
 693                         size_t size;
 694                 } phy_action;
 695         } *rtl_fw;
 696
 697         u32 ocp_base;
 698 };
 699
 700 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 701
 702 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 703 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 704 module_param_named(debug, debug.msg_enable, int, 0);
 705 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 706 MODULE_SOFTDEP("pre: realtek");
 707 MODULE_LICENSE("GPL");
 708 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 709 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 710 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 712 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 713 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 714 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 715 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 716 MODULE_FIRMWARE(FIRMWARE_8402_1);
 717 MODULE_FIRMWARE(FIRMWARE_8411_1);
 718 MODULE_FIRMWARE(FIRMWARE_8411_2);
 719 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 720 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 721 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 722 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 723 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 724 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 725 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 726 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 727
 728 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 729 {
 730         return &tp->pci_dev->dev;
 731 }
 732
 733 static void rtl_lock_work(struct rtl8169_private *tp)
 734 {
 735         mutex_lock(&tp->wk.mutex);
 736 }
 737
 738 static void rtl_unlock_work(struct rtl8169_private *tp)
 739 {
 740         mutex_unlock(&tp->wk.mutex);
 741 }
 742
 743 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 744 {
 745         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 746 }
 747
 748 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 749 {
 750         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 751 }
 752
 753 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 754 {
 755         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 756                                            PCI_EXP_DEVCTL_READRQ, force);
 757 }
 758
 759 struct rtl_cond {
 760         bool (*check)(struct rtl8169_private *);
 761         const char *msg;
 762 };
 763
 764 static void rtl_udelay(unsigned int d)
 765 {
 766         udelay(d);
 767 }
 768
 769 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 770                           void (*delay)(unsigned int), unsigned int d, int n,
 771                           bool high)
 772 {
 773         int i;
 774
 775         for (i = 0; i < n; i++) {
 776                 if (c->check(tp) == high)
 777                         return true;
 778                 delay(d);
 779         }
 780         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 781                   c->msg, !high, n, d);
 782         return false;
 783 }
 784
 785 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 786                                       const struct rtl_cond *c,
 787                                       unsigned int d, int n)
 788 {
 789         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 790 }
 791
 792 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 793                                      const struct rtl_cond *c,
 794                                      unsigned int d, int n)
 795 {
 796         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 797 }
 798
 799 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 800                                       const struct rtl_cond *c,
 801                                       unsigned int d, int n)
 802 {
 803         return rtl_loop_wait(tp, c, msleep, d, n, true);
 804 }
 805
 806 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 807                                      const struct rtl_cond *c,
 808                                      unsigned int d, int n)
 809 {
 810         return rtl_loop_wait(tp, c, msleep, d, n, false);
 811 }
 812
 813 #define DECLARE_RTL_COND(name)                          \
 814 static bool name ## _check(struct rtl8169_private *);   \
 815                                                         \
 816 static const struct rtl_cond name = {                   \
 817         .check  = name ## _check,                       \
 818         .msg    = #name                                 \
 819 };                                                      \
 820                                                         \
 821 static bool name ## _check(struct rtl8169_private *tp)
 822
 823 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 824 {
 825         if (reg & 0xffff0001) {
 826                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 827                 return true;
 828         }
 829         return false;
 830 }
 831
 832 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 833 {
 834         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 835 }
 836
 837 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 838 {
 839         if (rtl_ocp_reg_failure(tp, reg))
 840                 return;
 841
 842         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 843
 844         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 845 }
 846
 847 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 848 {
 849         if (rtl_ocp_reg_failure(tp, reg))
 850                 return 0;
 851
 852         RTL_W32(tp, GPHY_OCP, reg << 15);
 853
 854         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 855                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 856 }
 857
 858 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 859 {
 860         if (rtl_ocp_reg_failure(tp, reg))
 861                 return;
 862
 863         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 864 }
 865
 866 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 867 {
 868         if (rtl_ocp_reg_failure(tp, reg))
 869                 return 0;
 870
 871         RTL_W32(tp, OCPDR, reg << 15);
 872
 873         return RTL_R32(tp, OCPDR);
 874 }
 875
 876 #define OCP_STD_PHY_BASE        0xa400
 877
 878 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 879 {
 880         if (reg == 0x1f) {
 881                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 882                 return;
 883         }
 884
 885         if (tp->ocp_base != OCP_STD_PHY_BASE)
 886                 reg -= 0x10;
 887
 888         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 889 }
 890
 891 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 892 {
 893         if (tp->ocp_base != OCP_STD_PHY_BASE)
 894                 reg -= 0x10;
 895
 896         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 897 }
 898
 899 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 900 {
 901         if (reg == 0x1f) {
 902                 tp->ocp_base = value << 4;
 903                 return;
 904         }
 905
 906         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 907 }
 908
 909 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 910 {
 911         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 912 }
 913
 914 DECLARE_RTL_COND(rtl_phyar_cond)
 915 {
 916         return RTL_R32(tp, PHYAR) & 0x80000000;
 917 }
 918
 919 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 920 {
 921         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 922
 923         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 924         /*
 925          * According to hardware specs a 20us delay is required after write
 926          * complete indication, but before sending next command.
 927          */
 928         udelay(20);
 929 }
 930
 931 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 932 {
 933         int value;
 934
 935         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 936
 937         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 938                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 939
 940         /*
 941          * According to hardware specs a 20us delay is required after read
 942          * complete indication, but before sending next command.
 943          */
 944         udelay(20);
 945
 946         return value;
 947 }
 948
 949 DECLARE_RTL_COND(rtl_ocpar_cond)
 950 {
 951         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 952 }
 953
 954 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 955 {
 956         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 957         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 958         RTL_W32(tp, EPHY_RXER_NUM, 0);
 959
 960         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 961 }
 962
 963 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 964 {
 965         r8168dp_1_mdio_access(tp, reg,
 966                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 967 }
 968
 969 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 970 {
 971         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 972
 973         mdelay(1);
 974         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 975         RTL_W32(tp, EPHY_RXER_NUM, 0);
 976
 977         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 978                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 979 }
 980
 981 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 982
 983 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 984 {
 985         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 986 }
 987
 988 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 989 {
 990         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 991 }
 992
 993 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 994 {
 995         r8168dp_2_mdio_start(tp);
 996
 997         r8169_mdio_write(tp, reg, value);
 998
 999         r8168dp_2_mdio_stop(tp);
1000 }
1001
1002 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1003 {
1004         int value;
1005
1006         r8168dp_2_mdio_start(tp);
1007
1008         value = r8169_mdio_read(tp, reg);
1009
1010         r8168dp_2_mdio_stop(tp);
1011
1012         return value;
1013 }
1014
1015 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1016 {
1017         switch (tp->mac_version) {
1018         case RTL_GIGA_MAC_VER_27:
1019                 r8168dp_1_mdio_write(tp, location, val);
1020                 break;
1021         case RTL_GIGA_MAC_VER_28:
1022         case RTL_GIGA_MAC_VER_31:
1023                 r8168dp_2_mdio_write(tp, location, val);
1024                 break;
1025         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1026                 r8168g_mdio_write(tp, location, val);
1027                 break;
1028         default:
1029                 r8169_mdio_write(tp, location, val);
1030                 break;
1031         }
1032 }
1033
1034 static int rtl_readphy(struct rtl8169_private *tp, int location)
1035 {
1036         switch (tp->mac_version) {
1037         case RTL_GIGA_MAC_VER_27:
1038                 return r8168dp_1_mdio_read(tp, location);
1039         case RTL_GIGA_MAC_VER_28:
1040         case RTL_GIGA_MAC_VER_31:
1041                 return r8168dp_2_mdio_read(tp, location);
1042         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1043                 return r8168g_mdio_read(tp, location);
1044         default:
1045                 return r8169_mdio_read(tp, location);
1046         }
1047 }
1048
1049 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1050 {
1051         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1052 }
1053
1054 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1055 {
1056         int val;
1057
1058         val = rtl_readphy(tp, reg_addr);
1059         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1060 }
1061
1062 DECLARE_RTL_COND(rtl_ephyar_cond)
1063 {
1064         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1065 }
1066
1067 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1068 {
1069         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1070                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1071
1072         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1073
1074         udelay(10);
1075 }
1076
1077 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1078 {
1079         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1080
1081         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1082                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1083 }
1084
1085 DECLARE_RTL_COND(rtl_eriar_cond)
1086 {
1087         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1088 }
1089
1090 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1091                            u32 val, int type)
1092 {
1093         BUG_ON((addr & 3) || (mask == 0));
1094         RTL_W32(tp, ERIDR, val);
1095         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1096
1097         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1098 }
1099
1100 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1101                           u32 val)
1102 {
1103         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1104 }
1105
1106 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1107 {
1108         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1109
1110         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1111                 RTL_R32(tp, ERIDR) : ~0;
1112 }
1113
1114 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1115 {
1116         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1117 }
1118
1119 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1120                          u32 m)
1121 {
1122         u32 val;
1123
1124         val = rtl_eri_read(tp, addr);
1125         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1126 }
1127
1128 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1129                              u32 p)
1130 {
1131         rtl_w0w1_eri(tp, addr, mask, p, 0);
1132 }
1133
1134 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1135                                u32 m)
1136 {
1137         rtl_w0w1_eri(tp, addr, mask, 0, m);
1138 }
1139
1140 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1141 {
1142         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1143         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1144                 RTL_R32(tp, OCPDR) : ~0;
1145 }
1146
1147 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1148 {
1149         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1150 }
1151
1152 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1153                               u32 data)
1154 {
1155         RTL_W32(tp, OCPDR, data);
1156         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1157         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1158 }
1159
1160 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1161                               u32 data)
1162 {
1163         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1164                        data, ERIAR_OOB);
1165 }
1166
1167 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1168 {
1169         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1170
1171         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1172 }
1173
1174 #define OOB_CMD_RESET           0x00
1175 #define OOB_CMD_DRIVER_START    0x05
1176 #define OOB_CMD_DRIVER_STOP     0x06
1177
1178 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1179 {
1180         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1181 }
1182
1183 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1184 {
1185         u16 reg;
1186
1187         reg = rtl8168_get_ocp_reg(tp);
1188
1189         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1190 }
1191
1192 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1193 {
1194         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1195 }
1196
1197 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1198 {
1199         return RTL_R8(tp, IBISR0) & 0x20;
1200 }
1201
1202 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1203 {
1204         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1205         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1206         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1207         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1208 }
1209
1210 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1211 {
1212         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1213         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1214 }
1215
1216 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1217 {
1218         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1219         r8168ep_ocp_write(tp, 0x01, 0x30,
1220                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1221         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1222 }
1223
1224 static void rtl8168_driver_start(struct rtl8169_private *tp)
1225 {
1226         switch (tp->mac_version) {
1227         case RTL_GIGA_MAC_VER_27:
1228         case RTL_GIGA_MAC_VER_28:
1229         case RTL_GIGA_MAC_VER_31:
1230                 rtl8168dp_driver_start(tp);
1231                 break;
1232         case RTL_GIGA_MAC_VER_49:
1233         case RTL_GIGA_MAC_VER_50:
1234         case RTL_GIGA_MAC_VER_51:
1235                 rtl8168ep_driver_start(tp);
1236                 break;
1237         default:
1238                 BUG();
1239                 break;
1240         }
1241 }
1242
1243 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1244 {
1245         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1246         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1247 }
1248
1249 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1250 {
1251         rtl8168ep_stop_cmac(tp);
1252         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1253         r8168ep_ocp_write(tp, 0x01, 0x30,
1254                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1255         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1256 }
1257
1258 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1259 {
1260         switch (tp->mac_version) {
1261         case RTL_GIGA_MAC_VER_27:
1262         case RTL_GIGA_MAC_VER_28:
1263         case RTL_GIGA_MAC_VER_31:
1264                 rtl8168dp_driver_stop(tp);
1265                 break;
1266         case RTL_GIGA_MAC_VER_49:
1267         case RTL_GIGA_MAC_VER_50:
1268         case RTL_GIGA_MAC_VER_51:
1269                 rtl8168ep_driver_stop(tp);
1270                 break;
1271         default:
1272                 BUG();
1273                 break;
1274         }
1275 }
1276
1277 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1278 {
1279         u16 reg = rtl8168_get_ocp_reg(tp);
1280
1281         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1282 }
1283
1284 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1285 {
1286         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1287 }
1288
1289 static bool r8168_check_dash(struct rtl8169_private *tp)
1290 {
1291         switch (tp->mac_version) {
1292         case RTL_GIGA_MAC_VER_27:
1293         case RTL_GIGA_MAC_VER_28:
1294         case RTL_GIGA_MAC_VER_31:
1295                 return r8168dp_check_dash(tp);
1296         case RTL_GIGA_MAC_VER_49:
1297         case RTL_GIGA_MAC_VER_50:
1298         case RTL_GIGA_MAC_VER_51:
1299                 return r8168ep_check_dash(tp);
1300         default:
1301                 return false;
1302         }
1303 }
1304
1305 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1306 {
1307         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1308         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1309 }
1310
1311 DECLARE_RTL_COND(rtl_efusear_cond)
1312 {
1313         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1314 }
1315
1316 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1317 {
1318         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1319
1320         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1321                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1322 }
1323
1324 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1325 {
1326         RTL_W16(tp, IntrStatus, bits);
1327 }
1328
1329 static void rtl_irq_disable(struct rtl8169_private *tp)
1330 {
1331         RTL_W16(tp, IntrMask, 0);
1332         tp->irq_enabled = 0;
1333 }
1334
1335 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1336 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1337 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1338
1339 static void rtl_irq_enable(struct rtl8169_private *tp)
1340 {
1341         tp->irq_enabled = 1;
1342         RTL_W16(tp, IntrMask, tp->irq_mask);
1343 }
1344
1345 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1346 {
1347         rtl_irq_disable(tp);
1348         rtl_ack_events(tp, 0xffff);
1349         /* PCI commit */
1350         RTL_R8(tp, ChipCmd);
1351 }
1352
1353 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1354 {
1355         struct net_device *dev = tp->dev;
1356         struct phy_device *phydev = tp->phydev;
1357
1358         if (!netif_running(dev))
1359                 return;
1360
1361         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1362             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1363                 if (phydev->speed == SPEED_1000) {
1364                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1365                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1366                 } else if (phydev->speed == SPEED_100) {
1367                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1368                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1369                 } else {
1370                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1371                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1372                 }
1373                 rtl_reset_packet_filter(tp);
1374         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1375                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1376                 if (phydev->speed == SPEED_1000) {
1377                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1378                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1379                 } else {
1380                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1381                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1382                 }
1383         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1384                 if (phydev->speed == SPEED_10) {
1385                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1386                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1387                 } else {
1388                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1389                 }
1390         }
1391 }
1392
1393 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1394
1395 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1396 {
1397         struct rtl8169_private *tp = netdev_priv(dev);
1398
1399         rtl_lock_work(tp);
1400         wol->supported = WAKE_ANY;
1401         wol->wolopts = tp->saved_wolopts;
1402         rtl_unlock_work(tp);
1403 }
1404
1405 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1406 {
1407         unsigned int i, tmp;
1408         static const struct {
1409                 u32 opt;
1410                 u16 reg;
1411                 u8  mask;
1412         } cfg[] = {
1413                 { WAKE_PHY,   Config3, LinkUp },
1414                 { WAKE_UCAST, Config5, UWF },
1415                 { WAKE_BCAST, Config5, BWF },
1416                 { WAKE_MCAST, Config5, MWF },
1417                 { WAKE_ANY,   Config5, LanWake },
1418                 { WAKE_MAGIC, Config3, MagicPacket }
1419         };
1420         u8 options;
1421
1422         rtl_unlock_config_regs(tp);
1423
1424         switch (tp->mac_version) {
1425         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1426         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1427                 tmp = ARRAY_SIZE(cfg) - 1;
1428                 if (wolopts & WAKE_MAGIC)
1429                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1430                                          MagicPacket_v2);
1431                 else
1432                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1433                                            MagicPacket_v2);
1434                 break;
1435         default:
1436                 tmp = ARRAY_SIZE(cfg);
1437                 break;
1438         }
1439
1440         for (i = 0; i < tmp; i++) {
1441                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1442                 if (wolopts & cfg[i].opt)
1443                         options |= cfg[i].mask;
1444                 RTL_W8(tp, cfg[i].reg, options);
1445         }
1446
1447         switch (tp->mac_version) {
1448         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1449                 options = RTL_R8(tp, Config1) & ~PMEnable;
1450                 if (wolopts)
1451                         options |= PMEnable;
1452                 RTL_W8(tp, Config1, options);
1453                 break;
1454         default:
1455                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1456                 if (wolopts)
1457                         options |= PME_SIGNAL;
1458                 RTL_W8(tp, Config2, options);
1459                 break;
1460         }
1461
1462         rtl_lock_config_regs(tp);
1463
1464         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1465 }
1466
1467 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1468 {
1469         struct rtl8169_private *tp = netdev_priv(dev);
1470         struct device *d = tp_to_dev(tp);
1471
1472         if (wol->wolopts & ~WAKE_ANY)
1473                 return -EINVAL;
1474
1475         pm_runtime_get_noresume(d);
1476
1477         rtl_lock_work(tp);
1478
1479         tp->saved_wolopts = wol->wolopts;
1480
1481         if (pm_runtime_active(d))
1482                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1483
1484         rtl_unlock_work(tp);
1485
1486         pm_runtime_put_noidle(d);
1487
1488         return 0;
1489 }
1490
1491 static void rtl8169_get_drvinfo(struct net_device *dev,
1492                                 struct ethtool_drvinfo *info)
1493 {
1494         struct rtl8169_private *tp = netdev_priv(dev);
1495         struct rtl_fw *rtl_fw = tp->rtl_fw;
1496
1497         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1498         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1499         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1500         if (rtl_fw)
1501                 strlcpy(info->fw_version, rtl_fw->version,
1502                         sizeof(info->fw_version));
1503 }
1504
1505 static int rtl8169_get_regs_len(struct net_device *dev)
1506 {
1507         return R8169_REGS_SIZE;
1508 }
1509
1510 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1511         netdev_features_t features)
1512 {
1513         struct rtl8169_private *tp = netdev_priv(dev);
1514
1515         if (dev->mtu > TD_MSS_MAX)
1516                 features &= ~NETIF_F_ALL_TSO;
1517
1518         if (dev->mtu > JUMBO_1K &&
1519             tp->mac_version > RTL_GIGA_MAC_VER_06)
1520                 features &= ~NETIF_F_IP_CSUM;
1521
1522         return features;
1523 }
1524
1525 static int rtl8169_set_features(struct net_device *dev,
1526                                 netdev_features_t features)
1527 {
1528         struct rtl8169_private *tp = netdev_priv(dev);
1529         u32 rx_config;
1530
1531         rtl_lock_work(tp);
1532
1533         rx_config = RTL_R32(tp, RxConfig);
1534         if (features & NETIF_F_RXALL)
1535                 rx_config |= (AcceptErr | AcceptRunt);
1536         else
1537                 rx_config &= ~(AcceptErr | AcceptRunt);
1538
1539         RTL_W32(tp, RxConfig, rx_config);
1540
1541         if (features & NETIF_F_RXCSUM)
1542                 tp->cp_cmd |= RxChkSum;
1543         else
1544                 tp->cp_cmd &= ~RxChkSum;
1545
1546         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1547                 tp->cp_cmd |= RxVlan;
1548         else
1549                 tp->cp_cmd &= ~RxVlan;
1550
1551         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1552         RTL_R16(tp, CPlusCmd);
1553
1554         rtl_unlock_work(tp);
1555
1556         return 0;
1557 }
1558
1559 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1560 {
1561         return (skb_vlan_tag_present(skb)) ?
1562                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1563 }
1564
1565 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1566 {
1567         u32 opts2 = le32_to_cpu(desc->opts2);
1568
1569         if (opts2 & RxVlanTag)
1570                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1571 }
1572
1573 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1574                              void *p)
1575 {
1576         struct rtl8169_private *tp = netdev_priv(dev);
1577         u32 __iomem *data = tp->mmio_addr;
1578         u32 *dw = p;
1579         int i;
1580
1581         rtl_lock_work(tp);
1582         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1583                 memcpy_fromio(dw++, data++, 4);
1584         rtl_unlock_work(tp);
1585 }
1586
1587 static u32 rtl8169_get_msglevel(struct net_device *dev)
1588 {
1589         struct rtl8169_private *tp = netdev_priv(dev);
1590
1591         return tp->msg_enable;
1592 }
1593
1594 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1595 {
1596         struct rtl8169_private *tp = netdev_priv(dev);
1597
1598         tp->msg_enable = value;
1599 }
1600
1601 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1602         "tx_packets",
1603         "rx_packets",
1604         "tx_errors",
1605         "rx_errors",
1606         "rx_missed",
1607         "align_errors",
1608         "tx_single_collisions",
1609         "tx_multi_collisions",
1610         "unicast",
1611         "broadcast",
1612         "multicast",
1613         "tx_aborted",
1614         "tx_underrun",
1615 };
1616
1617 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1618 {
1619         switch (sset) {
1620         case ETH_SS_STATS:
1621                 return ARRAY_SIZE(rtl8169_gstrings);
1622         default:
1623                 return -EOPNOTSUPP;
1624         }
1625 }
1626
1627 DECLARE_RTL_COND(rtl_counters_cond)
1628 {
1629         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1630 }
1631
1632 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1633 {
1634         dma_addr_t paddr = tp->counters_phys_addr;
1635         u32 cmd;
1636
1637         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1638         RTL_R32(tp, CounterAddrHigh);
1639         cmd = (u64)paddr & DMA_BIT_MASK(32);
1640         RTL_W32(tp, CounterAddrLow, cmd);
1641         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1642
1643         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1644 }
1645
1646 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1647 {
1648         /*
1649          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1650          * tally counters.
1651          */
1652         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1653                 return true;
1654
1655         return rtl8169_do_counters(tp, CounterReset);
1656 }
1657
1658 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1659 {
1660         u8 val = RTL_R8(tp, ChipCmd);
1661
1662         /*
1663          * Some chips are unable to dump tally counters when the receiver
1664          * is disabled. If 0xff chip may be in a PCI power-save state.
1665          */
1666         if (!(val & CmdRxEnb) || val == 0xff)
1667                 return true;
1668
1669         return rtl8169_do_counters(tp, CounterDump);
1670 }
1671
1672 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1673 {
1674         struct rtl8169_counters *counters = tp->counters;
1675         bool ret = false;
1676
1677         /*
1678          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1679          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1680          * reset by a power cycle, while the counter values collected by the
1681          * driver are reset at every driver unload/load cycle.
1682          *
1683          * To make sure the HW values returned by @get_stats64 match the SW
1684          * values, we collect the initial values at first open(*) and use them
1685          * as offsets to normalize the values returned by @get_stats64.
1686          *
1687          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1688          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1689          * set at open time by rtl_hw_start.
1690          */
1691
1692         if (tp->tc_offset.inited)
1693                 return true;
1694
1695         /* If both, reset and update fail, propagate to caller. */
1696         if (rtl8169_reset_counters(tp))
1697                 ret = true;
1698
1699         if (rtl8169_update_counters(tp))
1700                 ret = true;
1701
1702         tp->tc_offset.tx_errors = counters->tx_errors;
1703         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1704         tp->tc_offset.tx_aborted = counters->tx_aborted;
1705         tp->tc_offset.inited = true;
1706
1707         return ret;
1708 }
1709
1710 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1711                                       struct ethtool_stats *stats, u64 *data)
1712 {
1713         struct rtl8169_private *tp = netdev_priv(dev);
1714         struct device *d = tp_to_dev(tp);
1715         struct rtl8169_counters *counters = tp->counters;
1716
1717         ASSERT_RTNL();
1718
1719         pm_runtime_get_noresume(d);
1720
1721         if (pm_runtime_active(d))
1722                 rtl8169_update_counters(tp);
1723
1724         pm_runtime_put_noidle(d);
1725
1726         data[0] = le64_to_cpu(counters->tx_packets);
1727         data[1] = le64_to_cpu(counters->rx_packets);
1728         data[2] = le64_to_cpu(counters->tx_errors);
1729         data[3] = le32_to_cpu(counters->rx_errors);
1730         data[4] = le16_to_cpu(counters->rx_missed);
1731         data[5] = le16_to_cpu(counters->align_errors);
1732         data[6] = le32_to_cpu(counters->tx_one_collision);
1733         data[7] = le32_to_cpu(counters->tx_multi_collision);
1734         data[8] = le64_to_cpu(counters->rx_unicast);
1735         data[9] = le64_to_cpu(counters->rx_broadcast);
1736         data[10] = le32_to_cpu(counters->rx_multicast);
1737         data[11] = le16_to_cpu(counters->tx_aborted);
1738         data[12] = le16_to_cpu(counters->tx_underun);
1739 }
1740
1741 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1742 {
1743         switch(stringset) {
1744         case ETH_SS_STATS:
1745                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1746                 break;
1747         }
1748 }
1749
1750 /*
1751  * Interrupt coalescing
1752  *
1753  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1754  * >     8169, 8168 and 810x line of chipsets
1755  *
1756  * 8169, 8168, and 8136(810x) serial chipsets support it.
1757  *
1758  * > 2 - the Tx timer unit at gigabit speed
1759  *
1760  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1761  * (0xe0) bit 1 and bit 0.
1762  *
1763  * For 8169
1764  * bit[1:0] \ speed        1000M           100M            10M
1765  * 0 0                     320ns           2.56us          40.96us
1766  * 0 1                     2.56us          20.48us         327.7us
1767  * 1 0                     5.12us          40.96us         655.4us
1768  * 1 1                     10.24us         81.92us         1.31ms
1769  *
1770  * For the other
1771  * bit[1:0] \ speed        1000M           100M            10M
1772  * 0 0                     5us             2.56us          40.96us
1773  * 0 1                     40us            20.48us         327.7us
1774  * 1 0                     80us            40.96us         655.4us
1775  * 1 1                     160us           81.92us         1.31ms
1776  */
1777
1778 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1779 struct rtl_coalesce_scale {
1780         /* Rx / Tx */
1781         u32 nsecs[2];
1782 };
1783
1784 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1785 struct rtl_coalesce_info {
1786         u32 speed;
1787         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1788 };
1789
1790 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1791 #define rxtx_x1822(r, t) {              \
1792         {{(r),          (t)}},          \
1793         {{(r)*8,        (t)*8}},        \
1794         {{(r)*8*2,      (t)*8*2}},      \
1795         {{(r)*8*2*2,    (t)*8*2*2}},    \
1796 }
1797 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1798         /* speed        delays:     rx00   tx00 */
1799         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1800         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1801         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1802         { 0 },
1803 };
1804
1805 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1806         /* speed        delays:     rx00   tx00 */
1807         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1808         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1809         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1810         { 0 },
1811 };
1812 #undef rxtx_x1822
1813
1814 /* get rx/tx scale vector corresponding to current speed */
1815 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1816 {
1817         struct rtl8169_private *tp = netdev_priv(dev);
1818         struct ethtool_link_ksettings ecmd;
1819         const struct rtl_coalesce_info *ci;
1820         int rc;
1821
1822         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1823         if (rc < 0)
1824                 return ERR_PTR(rc);
1825
1826         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1827                 if (ecmd.base.speed == ci->speed) {
1828                         return ci;
1829                 }
1830         }
1831
1832         return ERR_PTR(-ELNRNG);
1833 }
1834
1835 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1836 {
1837         struct rtl8169_private *tp = netdev_priv(dev);
1838         const struct rtl_coalesce_info *ci;
1839         const struct rtl_coalesce_scale *scale;
1840         struct {
1841                 u32 *max_frames;
1842                 u32 *usecs;
1843         } coal_settings [] = {
1844                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1845                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1846         }, *p = coal_settings;
1847         int i;
1848         u16 w;
1849
1850         memset(ec, 0, sizeof(*ec));
1851
1852         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1853         ci = rtl_coalesce_info(dev);
1854         if (IS_ERR(ci))
1855                 return PTR_ERR(ci);
1856
1857         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1858
1859         /* read IntrMitigate and adjust according to scale */
1860         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1861                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1862                 w >>= RTL_COALESCE_SHIFT;
1863                 *p->usecs = w & RTL_COALESCE_MASK;
1864         }
1865
1866         for (i = 0; i < 2; i++) {
1867                 p = coal_settings + i;
1868                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1869
1870                 /*
1871                  * ethtool_coalesce says it is illegal to set both usecs and
1872                  * max_frames to 0.
1873                  */
1874                 if (!*p->usecs && !*p->max_frames)
1875                         *p->max_frames = 1;
1876         }
1877
1878         return 0;
1879 }
1880
1881 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1882 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1883                         struct net_device *dev, u32 nsec, u16 *cp01)
1884 {
1885         const struct rtl_coalesce_info *ci;
1886         u16 i;
1887
1888         ci = rtl_coalesce_info(dev);
1889         if (IS_ERR(ci))
1890                 return ERR_CAST(ci);
1891
1892         for (i = 0; i < 4; i++) {
1893                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1894                                         ci->scalev[i].nsecs[1]);
1895                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1896                         *cp01 = i;
1897                         return &ci->scalev[i];
1898                 }
1899         }
1900
1901         return ERR_PTR(-EINVAL);
1902 }
1903
1904 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1905 {
1906         struct rtl8169_private *tp = netdev_priv(dev);
1907         const struct rtl_coalesce_scale *scale;
1908         struct {
1909                 u32 frames;
1910                 u32 usecs;
1911         } coal_settings [] = {
1912                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1913                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1914         }, *p = coal_settings;
1915         u16 w = 0, cp01;
1916         int i;
1917
1918         scale = rtl_coalesce_choose_scale(dev,
1919                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1920         if (IS_ERR(scale))
1921                 return PTR_ERR(scale);
1922
1923         for (i = 0; i < 2; i++, p++) {
1924                 u32 units;
1925
1926                 /*
1927                  * accept max_frames=1 we returned in rtl_get_coalesce.
1928                  * accept it not only when usecs=0 because of e.g. the following scenario:
1929                  *
1930                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1931                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1932                  * - then user does `ethtool -C eth0 rx-usecs 100`
1933                  *
1934                  * since ethtool sends to kernel whole ethtool_coalesce
1935                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1936                  * we'll reject it below in `frames % 4 != 0`.
1937                  */
1938                 if (p->frames == 1) {
1939                         p->frames = 0;
1940                 }
1941
1942                 units = p->usecs * 1000 / scale->nsecs[i];
1943                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1944                         return -EINVAL;
1945
1946                 w <<= RTL_COALESCE_SHIFT;
1947                 w |= units;
1948                 w <<= RTL_COALESCE_SHIFT;
1949                 w |= p->frames >> 2;
1950         }
1951
1952         rtl_lock_work(tp);
1953
1954         RTL_W16(tp, IntrMitigate, swab16(w));
1955
1956         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1957         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1958         RTL_R16(tp, CPlusCmd);
1959
1960         rtl_unlock_work(tp);
1961
1962         return 0;
1963 }
1964
1965 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1966 {
1967         struct phy_device *phydev = tp->phydev;
1968         int ret;
1969
1970         switch (tp->mac_version) {
1971         case RTL_GIGA_MAC_VER_34:
1972         case RTL_GIGA_MAC_VER_35:
1973         case RTL_GIGA_MAC_VER_36:
1974         case RTL_GIGA_MAC_VER_38:
1975                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1976                 break;
1977         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1978                 phy_write(phydev, 0x1f, 0x0a5c);
1979                 ret = phy_read(phydev, 0x12);
1980                 phy_write(phydev, 0x1f, 0x0000);
1981                 break;
1982         default:
1983                 ret = -EPROTONOSUPPORT;
1984                 break;
1985         }
1986
1987         return ret;
1988 }
1989
1990 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1991 {
1992         struct phy_device *phydev = tp->phydev;
1993         int ret;
1994
1995         switch (tp->mac_version) {
1996         case RTL_GIGA_MAC_VER_34:
1997         case RTL_GIGA_MAC_VER_35:
1998         case RTL_GIGA_MAC_VER_36:
1999         case RTL_GIGA_MAC_VER_38:
2000                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
2001                 break;
2002         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2003                 phy_write(phydev, 0x1f, 0x0a5d);
2004                 ret = phy_read(phydev, 0x11);
2005                 phy_write(phydev, 0x1f, 0x0000);
2006                 break;
2007         default:
2008                 ret = -EPROTONOSUPPORT;
2009                 break;
2010         }
2011
2012         return ret;
2013 }
2014
2015 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2016 {
2017         struct phy_device *phydev = tp->phydev;
2018         int ret;
2019
2020         switch (tp->mac_version) {
2021         case RTL_GIGA_MAC_VER_34:
2022         case RTL_GIGA_MAC_VER_35:
2023         case RTL_GIGA_MAC_VER_36:
2024         case RTL_GIGA_MAC_VER_38:
2025                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2026                 break;
2027         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2028                 phy_write(phydev, 0x1f, 0x0a5d);
2029                 ret = phy_read(phydev, 0x10);
2030                 phy_write(phydev, 0x1f, 0x0000);
2031                 break;
2032         default:
2033                 ret = -EPROTONOSUPPORT;
2034                 break;
2035         }
2036
2037         return ret;
2038 }
2039
2040 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2041 {
2042         struct phy_device *phydev = tp->phydev;
2043         int ret = 0;
2044
2045         switch (tp->mac_version) {
2046         case RTL_GIGA_MAC_VER_34:
2047         case RTL_GIGA_MAC_VER_35:
2048         case RTL_GIGA_MAC_VER_36:
2049         case RTL_GIGA_MAC_VER_38:
2050                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2051                 break;
2052         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2053                 phy_write(phydev, 0x1f, 0x0a5d);
2054                 phy_write(phydev, 0x10, val);
2055                 phy_write(phydev, 0x1f, 0x0000);
2056                 break;
2057         default:
2058                 ret = -EPROTONOSUPPORT;
2059                 break;
2060         }
2061
2062         return ret;
2063 }
2064
2065 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2066 {
2067         struct rtl8169_private *tp = netdev_priv(dev);
2068         struct device *d = tp_to_dev(tp);
2069         int ret;
2070
2071         pm_runtime_get_noresume(d);
2072
2073         if (!pm_runtime_active(d)) {
2074                 ret = -EOPNOTSUPP;
2075                 goto out;
2076         }
2077
2078         /* Get Supported EEE */
2079         ret = rtl_get_eee_supp(tp);
2080         if (ret < 0)
2081                 goto out;
2082         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2083
2084         /* Get advertisement EEE */
2085         ret = rtl_get_eee_adv(tp);
2086         if (ret < 0)
2087                 goto out;
2088         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2089         data->eee_enabled = !!data->advertised;
2090
2091         /* Get LP advertisement EEE */
2092         ret = rtl_get_eee_lpadv(tp);
2093         if (ret < 0)
2094                 goto out;
2095         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2096         data->eee_active = !!(data->advertised & data->lp_advertised);
2097 out:
2098         pm_runtime_put_noidle(d);
2099         return ret < 0 ? ret : 0;
2100 }
2101
2102 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2103 {
2104         struct rtl8169_private *tp = netdev_priv(dev);
2105         struct device *d = tp_to_dev(tp);
2106         int old_adv, adv = 0, cap, ret;
2107
2108         pm_runtime_get_noresume(d);
2109
2110         if (!dev->phydev || !pm_runtime_active(d)) {
2111                 ret = -EOPNOTSUPP;
2112                 goto out;
2113         }
2114
2115         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2116             dev->phydev->duplex != DUPLEX_FULL) {
2117                 ret = -EPROTONOSUPPORT;
2118                 goto out;
2119         }
2120
2121         /* Get Supported EEE */
2122         ret = rtl_get_eee_supp(tp);
2123         if (ret < 0)
2124                 goto out;
2125         cap = ret;
2126
2127         ret = rtl_get_eee_adv(tp);
2128         if (ret < 0)
2129                 goto out;
2130         old_adv = ret;
2131
2132         if (data->eee_enabled) {
2133                 adv = !data->advertised ? cap :
2134                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2135                 /* Mask prohibited EEE modes */
2136                 adv &= ~dev->phydev->eee_broken_modes;
2137         }
2138
2139         if (old_adv != adv) {
2140                 ret = rtl_set_eee_adv(tp, adv);
2141                 if (ret < 0)
2142                         goto out;
2143
2144                 /* Restart autonegotiation so the new modes get sent to the
2145                  * link partner.
2146                  */
2147                 ret = phy_restart_aneg(dev->phydev);
2148         }
2149
2150 out:
2151         pm_runtime_put_noidle(d);
2152         return ret < 0 ? ret : 0;
2153 }
2154
2155 static const struct ethtool_ops rtl8169_ethtool_ops = {
2156         .get_drvinfo            = rtl8169_get_drvinfo,
2157         .get_regs_len           = rtl8169_get_regs_len,
2158         .get_link               = ethtool_op_get_link,
2159         .get_coalesce           = rtl_get_coalesce,
2160         .set_coalesce           = rtl_set_coalesce,
2161         .get_msglevel           = rtl8169_get_msglevel,
2162         .set_msglevel           = rtl8169_set_msglevel,
2163         .get_regs               = rtl8169_get_regs,
2164         .get_wol                = rtl8169_get_wol,
2165         .set_wol                = rtl8169_set_wol,
2166         .get_strings            = rtl8169_get_strings,
2167         .get_sset_count         = rtl8169_get_sset_count,
2168         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2169         .get_ts_info            = ethtool_op_get_ts_info,
2170         .nway_reset             = phy_ethtool_nway_reset,
2171         .get_eee                = rtl8169_get_eee,
2172         .set_eee                = rtl8169_set_eee,
2173         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2174         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2175 };
2176
2177 static void rtl_enable_eee(struct rtl8169_private *tp)
2178 {
2179         int supported = rtl_get_eee_supp(tp);
2180
2181         if (supported > 0)
2182                 rtl_set_eee_adv(tp, supported);
2183 }
2184
2185 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2186 {
2187         /*
2188          * The driver currently handles the 8168Bf and the 8168Be identically
2189          * but they can be identified more specifically through the test below
2190          * if needed:
2191          *
2192          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2193          *
2194          * Same thing for the 8101Eb and the 8101Ec:
2195          *
2196          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2197          */
2198         static const struct rtl_mac_info {
2199                 u16 mask;
2200                 u16 val;
2201                 u16 mac_version;
2202         } mac_info[] = {
2203                 /* 8168EP family. */
2204                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2205                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2206                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2207
2208                 /* 8168H family. */
2209                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2210                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2211
2212                 /* 8168G family. */
2213                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2214                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2215                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2216                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2217
2218                 /* 8168F family. */
2219                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2220                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2221                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2222
2223                 /* 8168E family. */
2224                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2225                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2226                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2227
2228                 /* 8168D family. */
2229                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2230                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2231
2232                 /* 8168DP family. */
2233                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2234                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2235                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2236
2237                 /* 8168C family. */
2238                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2239                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2240                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2241                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2242                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2243                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2244                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2245
2246                 /* 8168B family. */
2247                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2248                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2249                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2250
2251                 /* 8101 family. */
2252                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2253                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2254                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2255                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2256                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2257                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2258                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2259                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2260                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2261                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2262                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2263                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2264                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2265                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2266                 /* FIXME: where did these entries come from ? -- FR */
2267                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2268                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2269
2270                 /* 8110 family. */
2271                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2272                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2273                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2274                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2275                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2276
2277                 /* Catch-all */
2278                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2279         };
2280         const struct rtl_mac_info *p = mac_info;
2281         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2282
2283         while ((reg & p->mask) != p->val)
2284                 p++;
2285         tp->mac_version = p->mac_version;
2286
2287         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2288                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2289         } else if (!tp->supports_gmii) {
2290                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2291                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2292                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2293                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2294                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2295                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2296         }
2297 }
2298
2299 struct phy_reg {
2300         u16 reg;
2301         u16 val;
2302 };
2303
2304 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2305                                  const struct phy_reg *regs, int len)
2306 {
2307         while (len-- > 0) {
2308                 rtl_writephy(tp, regs->reg, regs->val);
2309                 regs++;
2310         }
2311 }
2312
2313 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2314
2315 #define PHY_READ                0x00000000
2316 #define PHY_DATA_OR             0x10000000
2317 #define PHY_DATA_AND            0x20000000
2318 #define PHY_BJMPN               0x30000000
2319 #define PHY_MDIO_CHG            0x40000000
2320 #define PHY_CLEAR_READCOUNT     0x70000000
2321 #define PHY_WRITE               0x80000000
2322 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2323 #define PHY_COMP_EQ_SKIPN       0xa0000000
2324 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2325 #define PHY_WRITE_PREVIOUS      0xc0000000
2326 #define PHY_SKIPN               0xd0000000
2327 #define PHY_DELAY_MS            0xe0000000
2328
2329 struct fw_info {
2330         u32     magic;
2331         char    version[RTL_VER_SIZE];
2332         __le32  fw_start;
2333         __le32  fw_len;
2334         u8      chksum;
2335 } __packed;
2336
2337 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2338
2339 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2340 {
2341         const struct firmware *fw = rtl_fw->fw;
2342         struct fw_info *fw_info = (struct fw_info *)fw->data;
2343         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2344
2345         if (fw->size < FW_OPCODE_SIZE)
2346                 return false;
2347
2348         if (!fw_info->magic) {
2349                 size_t i, size, start;
2350                 u8 checksum = 0;
2351
2352                 if (fw->size < sizeof(*fw_info))
2353                         return false;
2354
2355                 for (i = 0; i < fw->size; i++)
2356                         checksum += fw->data[i];
2357                 if (checksum != 0)
2358                         return false;
2359
2360                 start = le32_to_cpu(fw_info->fw_start);
2361                 if (start > fw->size)
2362                         return false;
2363
2364                 size = le32_to_cpu(fw_info->fw_len);
2365                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2366                         return false;
2367
2368                 strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
2369
2370                 pa->code = (__le32 *)(fw->data + start);
2371                 pa->size = size;
2372         } else {
2373                 if (fw->size % FW_OPCODE_SIZE)
2374                         return false;
2375
2376                 strscpy(rtl_fw->version, tp->fw_name, RTL_VER_SIZE);
2377
2378                 pa->code = (__le32 *)fw->data;
2379                 pa->size = fw->size / FW_OPCODE_SIZE;
2380         }
2381
2382         return true;
2383 }
2384
2385 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2386                            struct rtl_fw_phy_action *pa)
2387 {
2388         bool rc = false;
2389         size_t index;
2390
2391         for (index = 0; index < pa->size; index++) {
2392                 u32 action = le32_to_cpu(pa->code[index]);
2393                 u32 regno = (action & 0x0fff0000) >> 16;
2394
2395                 switch(action & 0xf0000000) {
2396                 case PHY_READ:
2397                 case PHY_DATA_OR:
2398                 case PHY_DATA_AND:
2399                 case PHY_MDIO_CHG:
2400                 case PHY_CLEAR_READCOUNT:
2401                 case PHY_WRITE:
2402                 case PHY_WRITE_PREVIOUS:
2403                 case PHY_DELAY_MS:
2404                         break;
2405
2406                 case PHY_BJMPN:
2407                         if (regno > index) {
2408                                 netif_err(tp, ifup, tp->dev,
2409                                           "Out of range of firmware\n");
2410                                 goto out;
2411                         }
2412                         break;
2413                 case PHY_READCOUNT_EQ_SKIP:
2414                         if (index + 2 >= pa->size) {
2415                                 netif_err(tp, ifup, tp->dev,
2416                                           "Out of range of firmware\n");
2417                                 goto out;
2418                         }
2419                         break;
2420                 case PHY_COMP_EQ_SKIPN:
2421                 case PHY_COMP_NEQ_SKIPN:
2422                 case PHY_SKIPN:
2423                         if (index + 1 + regno >= pa->size) {
2424                                 netif_err(tp, ifup, tp->dev,
2425                                           "Out of range of firmware\n");
2426                                 goto out;
2427                         }
2428                         break;
2429
2430                 default:
2431                         netif_err(tp, ifup, tp->dev,
2432                                   "Invalid action 0x%08x\n", action);
2433                         goto out;
2434                 }
2435         }
2436         rc = true;
2437 out:
2438         return rc;
2439 }
2440
2441 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2442 {
2443         struct net_device *dev = tp->dev;
2444         int rc = -EINVAL;
2445
2446         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2447                 netif_err(tp, ifup, dev, "invalid firmware\n");
2448                 goto out;
2449         }
2450
2451         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2452                 rc = 0;
2453 out:
2454         return rc;
2455 }
2456
2457 static void rtl_fw_write_firmware(struct rtl8169_private *tp,
2458                                   struct rtl_fw *rtl_fw)
2459 {
2460         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2461         rtl_fw_write_t fw_write = rtl_fw->phy_write;
2462         rtl_fw_read_t fw_read = rtl_fw->phy_read;
2463         int predata = 0, count = 0;
2464         size_t index;
2465
2466         for (index = 0; index < pa->size; ) {
2467                 u32 action = le32_to_cpu(pa->code[index]);
2468                 u32 data = action & 0x0000ffff;
2469                 u32 regno = (action & 0x0fff0000) >> 16;
2470
2471                 if (!action)
2472                         break;
2473
2474                 switch(action & 0xf0000000) {
2475                 case PHY_READ:
2476                         predata = fw_read(tp, regno);
2477                         count++;
2478                         index++;
2479                         break;
2480                 case PHY_DATA_OR:
2481                         predata |= data;
2482                         index++;
2483                         break;
2484                 case PHY_DATA_AND:
2485                         predata &= data;
2486                         index++;
2487                         break;
2488                 case PHY_BJMPN:
2489                         index -= regno;
2490                         break;
2491                 case PHY_MDIO_CHG:
2492                         if (data == 0) {
2493                                 fw_write = rtl_fw->phy_write;
2494                                 fw_read = rtl_fw->phy_read;
2495                         } else if (data == 1) {
2496                                 fw_write = rtl_fw->mac_mcu_write;
2497                                 fw_read = rtl_fw->mac_mcu_read;
2498                         }
2499
2500                         index++;
2501                         break;
2502                 case PHY_CLEAR_READCOUNT:
2503                         count = 0;
2504                         index++;
2505                         break;
2506                 case PHY_WRITE:
2507                         fw_write(tp, regno, data);
2508                         index++;
2509                         break;
2510                 case PHY_READCOUNT_EQ_SKIP:
2511                         index += (count == data) ? 2 : 1;
2512                         break;
2513                 case PHY_COMP_EQ_SKIPN:
2514                         if (predata == data)
2515                                 index += regno;
2516                         index++;
2517                         break;
2518                 case PHY_COMP_NEQ_SKIPN:
2519                         if (predata != data)
2520                                 index += regno;
2521                         index++;
2522                         break;
2523                 case PHY_WRITE_PREVIOUS:
2524                         fw_write(tp, regno, predata);
2525                         index++;
2526                         break;
2527                 case PHY_SKIPN:
2528                         index += regno + 1;
2529                         break;
2530                 case PHY_DELAY_MS:
2531                         mdelay(data);
2532                         index++;
2533                         break;
2534
2535                 default:
2536                         BUG();
2537                 }
2538         }
2539 }
2540
2541 static void rtl_release_firmware(struct rtl8169_private *tp)
2542 {
2543         if (tp->rtl_fw) {
2544                 release_firmware(tp->rtl_fw->fw);
2545                 kfree(tp->rtl_fw);
2546                 tp->rtl_fw = NULL;
2547         }
2548 }
2549
2550 static void rtl_apply_firmware(struct rtl8169_private *tp)
2551 {
2552         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2553         if (tp->rtl_fw)
2554                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2555 }
2556
2557 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2558 {
2559         if (rtl_readphy(tp, reg) != val)
2560                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2561         else
2562                 rtl_apply_firmware(tp);
2563 }
2564
2565 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2566 {
2567         /* Adjust EEE LED frequency */
2568         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2569                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2570
2571         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2572 }
2573
2574 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2575 {
2576         struct phy_device *phydev = tp->phydev;
2577
2578         phy_write(phydev, 0x1f, 0x0007);
2579         phy_write(phydev, 0x1e, 0x0020);
2580         phy_set_bits(phydev, 0x15, BIT(8));
2581
2582         phy_write(phydev, 0x1f, 0x0005);
2583         phy_write(phydev, 0x05, 0x8b85);
2584         phy_set_bits(phydev, 0x06, BIT(13));
2585
2586         phy_write(phydev, 0x1f, 0x0000);
2587 }
2588
2589 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2590 {
2591         phy_write(tp->phydev, 0x1f, 0x0a43);
2592         phy_set_bits(tp->phydev, 0x11, BIT(4));
2593         phy_write(tp->phydev, 0x1f, 0x0000);
2594 }
2595
2596 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2597 {
2598         static const struct phy_reg phy_reg_init[] = {
2599                 { 0x1f, 0x0001 },
2600                 { 0x06, 0x006e },
2601                 { 0x08, 0x0708 },
2602                 { 0x15, 0x4000 },
2603                 { 0x18, 0x65c7 },
2604
2605                 { 0x1f, 0x0001 },
2606                 { 0x03, 0x00a1 },
2607                 { 0x02, 0x0008 },
2608                 { 0x01, 0x0120 },
2609                 { 0x00, 0x1000 },
2610                 { 0x04, 0x0800 },
2611                 { 0x04, 0x0000 },
2612
2613                 { 0x03, 0xff41 },
2614                 { 0x02, 0xdf60 },
2615                 { 0x01, 0x0140 },
2616                 { 0x00, 0x0077 },
2617                 { 0x04, 0x7800 },
2618                 { 0x04, 0x7000 },
2619
2620                 { 0x03, 0x802f },
2621                 { 0x02, 0x4f02 },
2622                 { 0x01, 0x0409 },
2623                 { 0x00, 0xf0f9 },
2624                 { 0x04, 0x9800 },
2625                 { 0x04, 0x9000 },
2626
2627                 { 0x03, 0xdf01 },
2628                 { 0x02, 0xdf20 },
2629                 { 0x01, 0xff95 },
2630                 { 0x00, 0xba00 },
2631                 { 0x04, 0xa800 },
2632                 { 0x04, 0xa000 },
2633
2634                 { 0x03, 0xff41 },
2635                 { 0x02, 0xdf20 },
2636                 { 0x01, 0x0140 },
2637                 { 0x00, 0x00bb },
2638                 { 0x04, 0xb800 },
2639                 { 0x04, 0xb000 },
2640
2641                 { 0x03, 0xdf41 },
2642                 { 0x02, 0xdc60 },
2643                 { 0x01, 0x6340 },
2644                 { 0x00, 0x007d },
2645                 { 0x04, 0xd800 },
2646                 { 0x04, 0xd000 },
2647
2648                 { 0x03, 0xdf01 },
2649                 { 0x02, 0xdf20 },
2650                 { 0x01, 0x100a },
2651                 { 0x00, 0xa0ff },
2652                 { 0x04, 0xf800 },
2653                 { 0x04, 0xf000 },
2654
2655                 { 0x1f, 0x0000 },
2656                 { 0x0b, 0x0000 },
2657                 { 0x00, 0x9200 }
2658         };
2659
2660         rtl_writephy_batch(tp, phy_reg_init);
2661 }
2662
2663 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2664 {
2665         static const struct phy_reg phy_reg_init[] = {
2666                 { 0x1f, 0x0002 },
2667                 { 0x01, 0x90d0 },
2668                 { 0x1f, 0x0000 }
2669         };
2670
2671         rtl_writephy_batch(tp, phy_reg_init);
2672 }
2673
2674 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2675 {
2676         struct pci_dev *pdev = tp->pci_dev;
2677
2678         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2679             (pdev->subsystem_device != 0xe000))
2680                 return;
2681
2682         rtl_writephy(tp, 0x1f, 0x0001);
2683         rtl_writephy(tp, 0x10, 0xf01b);
2684         rtl_writephy(tp, 0x1f, 0x0000);
2685 }
2686
2687 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2688 {
2689         static const struct phy_reg phy_reg_init[] = {
2690                 { 0x1f, 0x0001 },
2691                 { 0x04, 0x0000 },
2692                 { 0x03, 0x00a1 },
2693                 { 0x02, 0x0008 },
2694                 { 0x01, 0x0120 },
2695                 { 0x00, 0x1000 },
2696                 { 0x04, 0x0800 },
2697                 { 0x04, 0x9000 },
2698                 { 0x03, 0x802f },
2699                 { 0x02, 0x4f02 },
2700                 { 0x01, 0x0409 },
2701                 { 0x00, 0xf099 },
2702                 { 0x04, 0x9800 },
2703                 { 0x04, 0xa000 },
2704                 { 0x03, 0xdf01 },
2705                 { 0x02, 0xdf20 },
2706                 { 0x01, 0xff95 },
2707                 { 0x00, 0xba00 },
2708                 { 0x04, 0xa800 },
2709                 { 0x04, 0xf000 },
2710                 { 0x03, 0xdf01 },
2711                 { 0x02, 0xdf20 },
2712                 { 0x01, 0x101a },
2713                 { 0x00, 0xa0ff },
2714                 { 0x04, 0xf800 },
2715                 { 0x04, 0x0000 },
2716                 { 0x1f, 0x0000 },
2717
2718                 { 0x1f, 0x0001 },
2719                 { 0x10, 0xf41b },
2720                 { 0x14, 0xfb54 },
2721                 { 0x18, 0xf5c7 },
2722                 { 0x1f, 0x0000 },
2723
2724                 { 0x1f, 0x0001 },
2725                 { 0x17, 0x0cc0 },
2726                 { 0x1f, 0x0000 }
2727         };
2728
2729         rtl_writephy_batch(tp, phy_reg_init);
2730
2731         rtl8169scd_hw_phy_config_quirk(tp);
2732 }
2733
2734 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2735 {
2736         static const struct phy_reg phy_reg_init[] = {
2737                 { 0x1f, 0x0001 },
2738                 { 0x04, 0x0000 },
2739                 { 0x03, 0x00a1 },
2740                 { 0x02, 0x0008 },
2741                 { 0x01, 0x0120 },
2742                 { 0x00, 0x1000 },
2743                 { 0x04, 0x0800 },
2744                 { 0x04, 0x9000 },
2745                 { 0x03, 0x802f },
2746                 { 0x02, 0x4f02 },
2747                 { 0x01, 0x0409 },
2748                 { 0x00, 0xf099 },
2749                 { 0x04, 0x9800 },
2750                 { 0x04, 0xa000 },
2751                 { 0x03, 0xdf01 },
2752                 { 0x02, 0xdf20 },
2753                 { 0x01, 0xff95 },
2754                 { 0x00, 0xba00 },
2755                 { 0x04, 0xa800 },
2756                 { 0x04, 0xf000 },
2757                 { 0x03, 0xdf01 },
2758                 { 0x02, 0xdf20 },
2759                 { 0x01, 0x101a },
2760                 { 0x00, 0xa0ff },
2761                 { 0x04, 0xf800 },
2762                 { 0x04, 0x0000 },
2763                 { 0x1f, 0x0000 },
2764
2765                 { 0x1f, 0x0001 },
2766                 { 0x0b, 0x8480 },
2767                 { 0x1f, 0x0000 },
2768
2769                 { 0x1f, 0x0001 },
2770                 { 0x18, 0x67c7 },
2771                 { 0x04, 0x2000 },
2772                 { 0x03, 0x002f },
2773                 { 0x02, 0x4360 },
2774                 { 0x01, 0x0109 },
2775                 { 0x00, 0x3022 },
2776                 { 0x04, 0x2800 },
2777                 { 0x1f, 0x0000 },
2778
2779                 { 0x1f, 0x0001 },
2780                 { 0x17, 0x0cc0 },
2781                 { 0x1f, 0x0000 }
2782         };
2783
2784         rtl_writephy_batch(tp, phy_reg_init);
2785 }
2786
2787 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2788 {
2789         static const struct phy_reg phy_reg_init[] = {
2790                 { 0x10, 0xf41b },
2791                 { 0x1f, 0x0000 }
2792         };
2793
2794         rtl_writephy(tp, 0x1f, 0x0001);
2795         rtl_patchphy(tp, 0x16, 1 << 0);
2796
2797         rtl_writephy_batch(tp, phy_reg_init);
2798 }
2799
2800 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2801 {
2802         static const struct phy_reg phy_reg_init[] = {
2803                 { 0x1f, 0x0001 },
2804                 { 0x10, 0xf41b },
2805                 { 0x1f, 0x0000 }
2806         };
2807
2808         rtl_writephy_batch(tp, phy_reg_init);
2809 }
2810
2811 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2812 {
2813         static const struct phy_reg phy_reg_init[] = {
2814                 { 0x1f, 0x0000 },
2815                 { 0x1d, 0x0f00 },
2816                 { 0x1f, 0x0002 },
2817                 { 0x0c, 0x1ec8 },
2818                 { 0x1f, 0x0000 }
2819         };
2820
2821         rtl_writephy_batch(tp, phy_reg_init);
2822 }
2823
2824 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2825 {
2826         static const struct phy_reg phy_reg_init[] = {
2827                 { 0x1f, 0x0001 },
2828                 { 0x1d, 0x3d98 },
2829                 { 0x1f, 0x0000 }
2830         };
2831
2832         rtl_writephy(tp, 0x1f, 0x0000);
2833         rtl_patchphy(tp, 0x14, 1 << 5);
2834         rtl_patchphy(tp, 0x0d, 1 << 5);
2835
2836         rtl_writephy_batch(tp, phy_reg_init);
2837 }
2838
2839 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2840 {
2841         static const struct phy_reg phy_reg_init[] = {
2842                 { 0x1f, 0x0001 },
2843                 { 0x12, 0x2300 },
2844                 { 0x1f, 0x0002 },
2845                 { 0x00, 0x88d4 },
2846                 { 0x01, 0x82b1 },
2847                 { 0x03, 0x7002 },
2848                 { 0x08, 0x9e30 },
2849                 { 0x09, 0x01f0 },
2850                 { 0x0a, 0x5500 },
2851                 { 0x0c, 0x00c8 },
2852                 { 0x1f, 0x0003 },
2853                 { 0x12, 0xc096 },
2854                 { 0x16, 0x000a },
2855                 { 0x1f, 0x0000 },
2856                 { 0x1f, 0x0000 },
2857                 { 0x09, 0x2000 },
2858                 { 0x09, 0x0000 }
2859         };
2860
2861         rtl_writephy_batch(tp, phy_reg_init);
2862
2863         rtl_patchphy(tp, 0x14, 1 << 5);
2864         rtl_patchphy(tp, 0x0d, 1 << 5);
2865         rtl_writephy(tp, 0x1f, 0x0000);
2866 }
2867
2868 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2869 {
2870         static const struct phy_reg phy_reg_init[] = {
2871                 { 0x1f, 0x0001 },
2872                 { 0x12, 0x2300 },
2873                 { 0x03, 0x802f },
2874                 { 0x02, 0x4f02 },
2875                 { 0x01, 0x0409 },
2876                 { 0x00, 0xf099 },
2877                 { 0x04, 0x9800 },
2878                 { 0x04, 0x9000 },
2879                 { 0x1d, 0x3d98 },
2880                 { 0x1f, 0x0002 },
2881                 { 0x0c, 0x7eb8 },
2882                 { 0x06, 0x0761 },
2883                 { 0x1f, 0x0003 },
2884                 { 0x16, 0x0f0a },
2885                 { 0x1f, 0x0000 }
2886         };
2887
2888         rtl_writephy_batch(tp, phy_reg_init);
2889
2890         rtl_patchphy(tp, 0x16, 1 << 0);
2891         rtl_patchphy(tp, 0x14, 1 << 5);
2892         rtl_patchphy(tp, 0x0d, 1 << 5);
2893         rtl_writephy(tp, 0x1f, 0x0000);
2894 }
2895
2896 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2897 {
2898         static const struct phy_reg phy_reg_init[] = {
2899                 { 0x1f, 0x0001 },
2900                 { 0x12, 0x2300 },
2901                 { 0x1d, 0x3d98 },
2902                 { 0x1f, 0x0002 },
2903                 { 0x0c, 0x7eb8 },
2904                 { 0x06, 0x5461 },
2905                 { 0x1f, 0x0003 },
2906                 { 0x16, 0x0f0a },
2907                 { 0x1f, 0x0000 }
2908         };
2909
2910         rtl_writephy_batch(tp, phy_reg_init);
2911
2912         rtl_patchphy(tp, 0x16, 1 << 0);
2913         rtl_patchphy(tp, 0x14, 1 << 5);
2914         rtl_patchphy(tp, 0x0d, 1 << 5);
2915         rtl_writephy(tp, 0x1f, 0x0000);
2916 }
2917
2918 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2919 {
2920         rtl8168c_3_hw_phy_config(tp);
2921 }
2922
2923 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2924         /* Channel Estimation */
2925         { 0x1f, 0x0001 },
2926         { 0x06, 0x4064 },
2927         { 0x07, 0x2863 },
2928         { 0x08, 0x059c },
2929         { 0x09, 0x26b4 },
2930         { 0x0a, 0x6a19 },
2931         { 0x0b, 0xdcc8 },
2932         { 0x10, 0xf06d },
2933         { 0x14, 0x7f68 },
2934         { 0x18, 0x7fd9 },
2935         { 0x1c, 0xf0ff },
2936         { 0x1d, 0x3d9c },
2937         { 0x1f, 0x0003 },
2938         { 0x12, 0xf49f },
2939         { 0x13, 0x070b },
2940         { 0x1a, 0x05ad },
2941         { 0x14, 0x94c0 },
2942
2943         /*
2944          * Tx Error Issue
2945          * Enhance line driver power
2946          */
2947         { 0x1f, 0x0002 },
2948         { 0x06, 0x5561 },
2949         { 0x1f, 0x0005 },
2950         { 0x05, 0x8332 },
2951         { 0x06, 0x5561 },
2952
2953         /*
2954          * Can not link to 1Gbps with bad cable
2955          * Decrease SNR threshold form 21.07dB to 19.04dB
2956          */
2957         { 0x1f, 0x0001 },
2958         { 0x17, 0x0cc0 },
2959
2960         { 0x1f, 0x0000 },
2961         { 0x0d, 0xf880 }
2962 };
2963
2964 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2965         { 0x1f, 0x0002 },
2966         { 0x05, 0x669a },
2967         { 0x1f, 0x0005 },
2968         { 0x05, 0x8330 },
2969         { 0x06, 0x669a },
2970         { 0x1f, 0x0002 }
2971 };
2972
2973 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2974 {
2975         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2976
2977         /*
2978          * Rx Error Issue
2979          * Fine Tune Switching regulator parameter
2980          */
2981         rtl_writephy(tp, 0x1f, 0x0002);
2982         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2983         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2984
2985         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2986                 int val;
2987
2988                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2989
2990                 val = rtl_readphy(tp, 0x0d);
2991
2992                 if ((val & 0x00ff) != 0x006c) {
2993                         static const u32 set[] = {
2994                                 0x0065, 0x0066, 0x0067, 0x0068,
2995                                 0x0069, 0x006a, 0x006b, 0x006c
2996                         };
2997                         int i;
2998
2999                         rtl_writephy(tp, 0x1f, 0x0002);
3000
3001                         val &= 0xff00;
3002                         for (i = 0; i < ARRAY_SIZE(set); i++)
3003                                 rtl_writephy(tp, 0x0d, val | set[i]);
3004                 }
3005         } else {
3006                 static const struct phy_reg phy_reg_init[] = {
3007                         { 0x1f, 0x0002 },
3008                         { 0x05, 0x6662 },
3009                         { 0x1f, 0x0005 },
3010                         { 0x05, 0x8330 },
3011                         { 0x06, 0x6662 }
3012                 };
3013
3014                 rtl_writephy_batch(tp, phy_reg_init);
3015         }
3016
3017         /* RSET couple improve */
3018         rtl_writephy(tp, 0x1f, 0x0002);
3019         rtl_patchphy(tp, 0x0d, 0x0300);
3020         rtl_patchphy(tp, 0x0f, 0x0010);
3021
3022         /* Fine tune PLL performance */
3023         rtl_writephy(tp, 0x1f, 0x0002);
3024         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3025         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3026
3027         rtl_writephy(tp, 0x1f, 0x0005);
3028         rtl_writephy(tp, 0x05, 0x001b);
3029
3030         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3031
3032         rtl_writephy(tp, 0x1f, 0x0000);
3033 }
3034
3035 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3036 {
3037         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
3038
3039         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3040                 int val;
3041
3042                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3043
3044                 val = rtl_readphy(tp, 0x0d);
3045                 if ((val & 0x00ff) != 0x006c) {
3046                         static const u32 set[] = {
3047                                 0x0065, 0x0066, 0x0067, 0x0068,
3048                                 0x0069, 0x006a, 0x006b, 0x006c
3049                         };
3050                         int i;
3051
3052                         rtl_writephy(tp, 0x1f, 0x0002);
3053
3054                         val &= 0xff00;
3055                         for (i = 0; i < ARRAY_SIZE(set); i++)
3056                                 rtl_writephy(tp, 0x0d, val | set[i]);
3057                 }
3058         } else {
3059                 static const struct phy_reg phy_reg_init[] = {
3060                         { 0x1f, 0x0002 },
3061                         { 0x05, 0x2642 },
3062                         { 0x1f, 0x0005 },
3063                         { 0x05, 0x8330 },
3064                         { 0x06, 0x2642 }
3065                 };
3066
3067                 rtl_writephy_batch(tp, phy_reg_init);
3068         }
3069
3070         /* Fine tune PLL performance */
3071         rtl_writephy(tp, 0x1f, 0x0002);
3072         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3073         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3074
3075         /* Switching regulator Slew rate */
3076         rtl_writephy(tp, 0x1f, 0x0002);
3077         rtl_patchphy(tp, 0x0f, 0x0017);
3078
3079         rtl_writephy(tp, 0x1f, 0x0005);
3080         rtl_writephy(tp, 0x05, 0x001b);
3081
3082         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3083
3084         rtl_writephy(tp, 0x1f, 0x0000);
3085 }
3086
3087 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3088 {
3089         static const struct phy_reg phy_reg_init[] = {
3090                 { 0x1f, 0x0002 },
3091                 { 0x10, 0x0008 },
3092                 { 0x0d, 0x006c },
3093
3094                 { 0x1f, 0x0000 },
3095                 { 0x0d, 0xf880 },
3096
3097                 { 0x1f, 0x0001 },
3098                 { 0x17, 0x0cc0 },
3099
3100                 { 0x1f, 0x0001 },
3101                 { 0x0b, 0xa4d8 },
3102                 { 0x09, 0x281c },
3103                 { 0x07, 0x2883 },
3104                 { 0x0a, 0x6b35 },
3105                 { 0x1d, 0x3da4 },
3106                 { 0x1c, 0xeffd },
3107                 { 0x14, 0x7f52 },
3108                 { 0x18, 0x7fc6 },
3109                 { 0x08, 0x0601 },
3110                 { 0x06, 0x4063 },
3111                 { 0x10, 0xf074 },
3112                 { 0x1f, 0x0003 },
3113                 { 0x13, 0x0789 },
3114                 { 0x12, 0xf4bd },
3115                 { 0x1a, 0x04fd },
3116                 { 0x14, 0x84b0 },
3117                 { 0x1f, 0x0000 },
3118                 { 0x00, 0x9200 },
3119
3120                 { 0x1f, 0x0005 },
3121                 { 0x01, 0x0340 },
3122                 { 0x1f, 0x0001 },
3123                 { 0x04, 0x4000 },
3124                 { 0x03, 0x1d21 },
3125                 { 0x02, 0x0c32 },
3126                 { 0x01, 0x0200 },
3127                 { 0x00, 0x5554 },
3128                 { 0x04, 0x4800 },
3129                 { 0x04, 0x4000 },
3130                 { 0x04, 0xf000 },
3131                 { 0x03, 0xdf01 },
3132                 { 0x02, 0xdf20 },
3133                 { 0x01, 0x101a },
3134                 { 0x00, 0xa0ff },
3135                 { 0x04, 0xf800 },
3136                 { 0x04, 0xf000 },
3137                 { 0x1f, 0x0000 },
3138
3139                 { 0x1f, 0x0007 },
3140                 { 0x1e, 0x0023 },
3141                 { 0x16, 0x0000 },
3142                 { 0x1f, 0x0000 }
3143         };
3144
3145         rtl_writephy_batch(tp, phy_reg_init);
3146 }
3147
3148 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3149 {
3150         static const struct phy_reg phy_reg_init[] = {
3151                 { 0x1f, 0x0001 },
3152                 { 0x17, 0x0cc0 },
3153
3154                 { 0x1f, 0x0007 },
3155                 { 0x1e, 0x002d },
3156                 { 0x18, 0x0040 },
3157                 { 0x1f, 0x0000 }
3158         };
3159
3160         rtl_writephy_batch(tp, phy_reg_init);
3161         rtl_patchphy(tp, 0x0d, 1 << 5);
3162 }
3163
3164 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3165 {
3166         static const struct phy_reg phy_reg_init[] = {
3167                 /* Enable Delay cap */
3168                 { 0x1f, 0x0005 },
3169                 { 0x05, 0x8b80 },
3170                 { 0x06, 0xc896 },
3171                 { 0x1f, 0x0000 },
3172
3173                 /* Channel estimation fine tune */
3174                 { 0x1f, 0x0001 },
3175                 { 0x0b, 0x6c20 },
3176                 { 0x07, 0x2872 },
3177                 { 0x1c, 0xefff },
3178                 { 0x1f, 0x0003 },
3179                 { 0x14, 0x6420 },
3180                 { 0x1f, 0x0000 },
3181
3182                 /* Update PFM & 10M TX idle timer */
3183                 { 0x1f, 0x0007 },
3184                 { 0x1e, 0x002f },
3185                 { 0x15, 0x1919 },
3186                 { 0x1f, 0x0000 },
3187
3188                 { 0x1f, 0x0007 },
3189                 { 0x1e, 0x00ac },
3190                 { 0x18, 0x0006 },
3191                 { 0x1f, 0x0000 }
3192         };
3193
3194         rtl_apply_firmware(tp);
3195
3196         rtl_writephy_batch(tp, phy_reg_init);
3197
3198         /* DCO enable for 10M IDLE Power */
3199         rtl_writephy(tp, 0x1f, 0x0007);
3200         rtl_writephy(tp, 0x1e, 0x0023);
3201         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3202         rtl_writephy(tp, 0x1f, 0x0000);
3203
3204         /* For impedance matching */
3205         rtl_writephy(tp, 0x1f, 0x0002);
3206         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3207         rtl_writephy(tp, 0x1f, 0x0000);
3208
3209         /* PHY auto speed down */
3210         rtl_writephy(tp, 0x1f, 0x0007);
3211         rtl_writephy(tp, 0x1e, 0x002d);
3212         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3213         rtl_writephy(tp, 0x1f, 0x0000);
3214         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3215
3216         rtl_writephy(tp, 0x1f, 0x0005);
3217         rtl_writephy(tp, 0x05, 0x8b86);
3218         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3219         rtl_writephy(tp, 0x1f, 0x0000);
3220
3221         rtl_writephy(tp, 0x1f, 0x0005);
3222         rtl_writephy(tp, 0x05, 0x8b85);
3223         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3224         rtl_writephy(tp, 0x1f, 0x0007);
3225         rtl_writephy(tp, 0x1e, 0x0020);
3226         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3227         rtl_writephy(tp, 0x1f, 0x0006);
3228         rtl_writephy(tp, 0x00, 0x5a00);
3229         rtl_writephy(tp, 0x1f, 0x0000);
3230         rtl_writephy(tp, 0x0d, 0x0007);
3231         rtl_writephy(tp, 0x0e, 0x003c);
3232         rtl_writephy(tp, 0x0d, 0x4007);
3233         rtl_writephy(tp, 0x0e, 0x0000);
3234         rtl_writephy(tp, 0x0d, 0x0000);
3235 }
3236
3237 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3238 {
3239         const u16 w[] = {
3240                 addr[0] | (addr[1] << 8),
3241                 addr[2] | (addr[3] << 8),
3242                 addr[4] | (addr[5] << 8)
3243         };
3244
3245         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3246         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3247         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3248         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3249 }
3250
3251 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3252 {
3253         static const struct phy_reg phy_reg_init[] = {
3254                 /* Enable Delay cap */
3255                 { 0x1f, 0x0004 },
3256                 { 0x1f, 0x0007 },
3257                 { 0x1e, 0x00ac },
3258                 { 0x18, 0x0006 },
3259                 { 0x1f, 0x0002 },
3260                 { 0x1f, 0x0000 },
3261                 { 0x1f, 0x0000 },
3262
3263                 /* Channel estimation fine tune */
3264                 { 0x1f, 0x0003 },
3265                 { 0x09, 0xa20f },
3266                 { 0x1f, 0x0000 },
3267                 { 0x1f, 0x0000 },
3268
3269                 /* Green Setting */
3270                 { 0x1f, 0x0005 },
3271                 { 0x05, 0x8b5b },
3272                 { 0x06, 0x9222 },
3273                 { 0x05, 0x8b6d },
3274                 { 0x06, 0x8000 },
3275                 { 0x05, 0x8b76 },
3276                 { 0x06, 0x8000 },
3277                 { 0x1f, 0x0000 }
3278         };
3279
3280         rtl_apply_firmware(tp);
3281
3282         rtl_writephy_batch(tp, phy_reg_init);
3283
3284         /* For 4-corner performance improve */
3285         rtl_writephy(tp, 0x1f, 0x0005);
3286         rtl_writephy(tp, 0x05, 0x8b80);
3287         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3288         rtl_writephy(tp, 0x1f, 0x0000);
3289
3290         /* PHY auto speed down */
3291         rtl_writephy(tp, 0x1f, 0x0004);
3292         rtl_writephy(tp, 0x1f, 0x0007);
3293         rtl_writephy(tp, 0x1e, 0x002d);
3294         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3295         rtl_writephy(tp, 0x1f, 0x0002);
3296         rtl_writephy(tp, 0x1f, 0x0000);
3297         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3298
3299         /* improve 10M EEE waveform */
3300         rtl_writephy(tp, 0x1f, 0x0005);
3301         rtl_writephy(tp, 0x05, 0x8b86);
3302         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3303         rtl_writephy(tp, 0x1f, 0x0000);
3304
3305         /* Improve 2-pair detection performance */
3306         rtl_writephy(tp, 0x1f, 0x0005);
3307         rtl_writephy(tp, 0x05, 0x8b85);
3308         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3309         rtl_writephy(tp, 0x1f, 0x0000);
3310
3311         rtl8168f_config_eee_phy(tp);
3312         rtl_enable_eee(tp);
3313
3314         /* Green feature */
3315         rtl_writephy(tp, 0x1f, 0x0003);
3316         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3317         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3318         rtl_writephy(tp, 0x1f, 0x0000);
3319         rtl_writephy(tp, 0x1f, 0x0005);
3320         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3321         rtl_writephy(tp, 0x1f, 0x0000);
3322
3323         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3324         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3325 }
3326
3327 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3328 {
3329         /* For 4-corner performance improve */
3330         rtl_writephy(tp, 0x1f, 0x0005);
3331         rtl_writephy(tp, 0x05, 0x8b80);
3332         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3333         rtl_writephy(tp, 0x1f, 0x0000);
3334
3335         /* PHY auto speed down */
3336         rtl_writephy(tp, 0x1f, 0x0007);
3337         rtl_writephy(tp, 0x1e, 0x002d);
3338         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3339         rtl_writephy(tp, 0x1f, 0x0000);
3340         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3341
3342         /* Improve 10M EEE waveform */
3343         rtl_writephy(tp, 0x1f, 0x0005);
3344         rtl_writephy(tp, 0x05, 0x8b86);
3345         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3346         rtl_writephy(tp, 0x1f, 0x0000);
3347
3348         rtl8168f_config_eee_phy(tp);
3349         rtl_enable_eee(tp);
3350 }
3351
3352 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3353 {
3354         static const struct phy_reg phy_reg_init[] = {
3355                 /* Channel estimation fine tune */
3356                 { 0x1f, 0x0003 },
3357                 { 0x09, 0xa20f },
3358                 { 0x1f, 0x0000 },
3359
3360                 /* Modify green table for giga & fnet */
3361                 { 0x1f, 0x0005 },
3362                 { 0x05, 0x8b55 },
3363                 { 0x06, 0x0000 },
3364                 { 0x05, 0x8b5e },
3365                 { 0x06, 0x0000 },
3366                 { 0x05, 0x8b67 },
3367                 { 0x06, 0x0000 },
3368                 { 0x05, 0x8b70 },
3369                 { 0x06, 0x0000 },
3370                 { 0x1f, 0x0000 },
3371                 { 0x1f, 0x0007 },
3372                 { 0x1e, 0x0078 },
3373                 { 0x17, 0x0000 },
3374                 { 0x19, 0x00fb },
3375                 { 0x1f, 0x0000 },
3376
3377                 /* Modify green table for 10M */
3378                 { 0x1f, 0x0005 },
3379                 { 0x05, 0x8b79 },
3380                 { 0x06, 0xaa00 },
3381                 { 0x1f, 0x0000 },
3382
3383                 /* Disable hiimpedance detection (RTCT) */
3384                 { 0x1f, 0x0003 },
3385                 { 0x01, 0x328a },
3386                 { 0x1f, 0x0000 }
3387         };
3388
3389         rtl_apply_firmware(tp);
3390
3391         rtl_writephy_batch(tp, phy_reg_init);
3392
3393         rtl8168f_hw_phy_config(tp);
3394
3395         /* Improve 2-pair detection performance */
3396         rtl_writephy(tp, 0x1f, 0x0005);
3397         rtl_writephy(tp, 0x05, 0x8b85);
3398         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3399         rtl_writephy(tp, 0x1f, 0x0000);
3400 }
3401
3402 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3403 {
3404         rtl_apply_firmware(tp);
3405
3406         rtl8168f_hw_phy_config(tp);
3407 }
3408
3409 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3410 {
3411         static const struct phy_reg phy_reg_init[] = {
3412                 /* Channel estimation fine tune */
3413                 { 0x1f, 0x0003 },
3414                 { 0x09, 0xa20f },
3415                 { 0x1f, 0x0000 },
3416
3417                 /* Modify green table for giga & fnet */
3418                 { 0x1f, 0x0005 },
3419                 { 0x05, 0x8b55 },
3420                 { 0x06, 0x0000 },
3421                 { 0x05, 0x8b5e },
3422                 { 0x06, 0x0000 },
3423                 { 0x05, 0x8b67 },
3424                 { 0x06, 0x0000 },
3425                 { 0x05, 0x8b70 },
3426                 { 0x06, 0x0000 },
3427                 { 0x1f, 0x0000 },
3428                 { 0x1f, 0x0007 },
3429                 { 0x1e, 0x0078 },
3430                 { 0x17, 0x0000 },
3431                 { 0x19, 0x00aa },
3432                 { 0x1f, 0x0000 },
3433
3434                 /* Modify green table for 10M */
3435                 { 0x1f, 0x0005 },
3436                 { 0x05, 0x8b79 },
3437                 { 0x06, 0xaa00 },
3438                 { 0x1f, 0x0000 },
3439
3440                 /* Disable hiimpedance detection (RTCT) */
3441                 { 0x1f, 0x0003 },
3442                 { 0x01, 0x328a },
3443                 { 0x1f, 0x0000 }
3444         };
3445
3446
3447         rtl_apply_firmware(tp);
3448
3449         rtl8168f_hw_phy_config(tp);
3450
3451         /* Improve 2-pair detection performance */
3452         rtl_writephy(tp, 0x1f, 0x0005);
3453         rtl_writephy(tp, 0x05, 0x8b85);
3454         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3455         rtl_writephy(tp, 0x1f, 0x0000);
3456
3457         rtl_writephy_batch(tp, phy_reg_init);
3458
3459         /* Modify green table for giga */
3460         rtl_writephy(tp, 0x1f, 0x0005);
3461         rtl_writephy(tp, 0x05, 0x8b54);
3462         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3463         rtl_writephy(tp, 0x05, 0x8b5d);
3464         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3465         rtl_writephy(tp, 0x05, 0x8a7c);
3466         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3467         rtl_writephy(tp, 0x05, 0x8a7f);
3468         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3469         rtl_writephy(tp, 0x05, 0x8a82);
3470         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3471         rtl_writephy(tp, 0x05, 0x8a85);
3472         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3473         rtl_writephy(tp, 0x05, 0x8a88);
3474         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3475         rtl_writephy(tp, 0x1f, 0x0000);
3476
3477         /* uc same-seed solution */
3478         rtl_writephy(tp, 0x1f, 0x0005);
3479         rtl_writephy(tp, 0x05, 0x8b85);
3480         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3481         rtl_writephy(tp, 0x1f, 0x0000);
3482
3483         /* Green feature */
3484         rtl_writephy(tp, 0x1f, 0x0003);
3485         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3486         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3487         rtl_writephy(tp, 0x1f, 0x0000);
3488 }
3489
3490 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3491 {
3492         phy_write(tp->phydev, 0x1f, 0x0a43);
3493         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3494 }
3495
3496 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3497 {
3498         struct phy_device *phydev = tp->phydev;
3499
3500         phy_write(phydev, 0x1f, 0x0bcc);
3501         phy_clear_bits(phydev, 0x14, BIT(8));
3502
3503         phy_write(phydev, 0x1f, 0x0a44);
3504         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3505
3506         phy_write(phydev, 0x1f, 0x0a43);
3507         phy_write(phydev, 0x13, 0x8084);
3508         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3509         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3510
3511         phy_write(phydev, 0x1f, 0x0000);
3512 }
3513
3514 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3515 {
3516         rtl_apply_firmware(tp);
3517
3518         rtl_writephy(tp, 0x1f, 0x0a46);
3519         if (rtl_readphy(tp, 0x10) & 0x0100) {
3520                 rtl_writephy(tp, 0x1f, 0x0bcc);
3521                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3522         } else {
3523                 rtl_writephy(tp, 0x1f, 0x0bcc);
3524                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3525         }
3526
3527         rtl_writephy(tp, 0x1f, 0x0a46);
3528         if (rtl_readphy(tp, 0x13) & 0x0100) {
3529                 rtl_writephy(tp, 0x1f, 0x0c41);
3530                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3531         } else {
3532                 rtl_writephy(tp, 0x1f, 0x0c41);
3533                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3534         }
3535
3536         /* Enable PHY auto speed down */
3537         rtl_writephy(tp, 0x1f, 0x0a44);
3538         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3539
3540         rtl8168g_phy_adjust_10m_aldps(tp);
3541
3542         /* EEE auto-fallback function */
3543         rtl_writephy(tp, 0x1f, 0x0a4b);
3544         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3545
3546         /* Enable UC LPF tune function */
3547         rtl_writephy(tp, 0x1f, 0x0a43);
3548         rtl_writephy(tp, 0x13, 0x8012);
3549         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3550
3551         rtl_writephy(tp, 0x1f, 0x0c42);
3552         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3553
3554         /* Improve SWR Efficiency */
3555         rtl_writephy(tp, 0x1f, 0x0bcd);
3556         rtl_writephy(tp, 0x14, 0x5065);
3557         rtl_writephy(tp, 0x14, 0xd065);
3558         rtl_writephy(tp, 0x1f, 0x0bc8);
3559         rtl_writephy(tp, 0x11, 0x5655);
3560         rtl_writephy(tp, 0x1f, 0x0bcd);
3561         rtl_writephy(tp, 0x14, 0x1065);
3562         rtl_writephy(tp, 0x14, 0x9065);
3563         rtl_writephy(tp, 0x14, 0x1065);
3564
3565         rtl8168g_disable_aldps(tp);
3566         rtl8168g_config_eee_phy(tp);
3567         rtl_enable_eee(tp);
3568 }
3569
3570 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3571 {
3572         rtl_apply_firmware(tp);
3573         rtl8168g_config_eee_phy(tp);
3574         rtl_enable_eee(tp);
3575 }
3576
3577 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3578 {
3579         u16 dout_tapbin;
3580         u32 data;
3581
3582         rtl_apply_firmware(tp);
3583
3584         /* CHN EST parameters adjust - giga master */
3585         rtl_writephy(tp, 0x1f, 0x0a43);
3586         rtl_writephy(tp, 0x13, 0x809b);
3587         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3588         rtl_writephy(tp, 0x13, 0x80a2);
3589         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3590         rtl_writephy(tp, 0x13, 0x80a4);
3591         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3592         rtl_writephy(tp, 0x13, 0x809c);
3593         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3594         rtl_writephy(tp, 0x1f, 0x0000);
3595
3596         /* CHN EST parameters adjust - giga slave */
3597         rtl_writephy(tp, 0x1f, 0x0a43);
3598         rtl_writephy(tp, 0x13, 0x80ad);
3599         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3600         rtl_writephy(tp, 0x13, 0x80b4);
3601         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3602         rtl_writephy(tp, 0x13, 0x80ac);
3603         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3604         rtl_writephy(tp, 0x1f, 0x0000);
3605
3606         /* CHN EST parameters adjust - fnet */
3607         rtl_writephy(tp, 0x1f, 0x0a43);
3608         rtl_writephy(tp, 0x13, 0x808e);
3609         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3610         rtl_writephy(tp, 0x13, 0x8090);
3611         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3612         rtl_writephy(tp, 0x13, 0x8092);
3613         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3614         rtl_writephy(tp, 0x1f, 0x0000);
3615
3616         /* enable R-tune & PGA-retune function */
3617         dout_tapbin = 0;
3618         rtl_writephy(tp, 0x1f, 0x0a46);
3619         data = rtl_readphy(tp, 0x13);
3620         data &= 3;
3621         data <<= 2;
3622         dout_tapbin |= data;
3623         data = rtl_readphy(tp, 0x12);
3624         data &= 0xc000;
3625         data >>= 14;
3626         dout_tapbin |= data;
3627         dout_tapbin = ~(dout_tapbin^0x08);
3628         dout_tapbin <<= 12;
3629         dout_tapbin &= 0xf000;
3630         rtl_writephy(tp, 0x1f, 0x0a43);
3631         rtl_writephy(tp, 0x13, 0x827a);
3632         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3633         rtl_writephy(tp, 0x13, 0x827b);
3634         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3635         rtl_writephy(tp, 0x13, 0x827c);
3636         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3637         rtl_writephy(tp, 0x13, 0x827d);
3638         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3639
3640         rtl_writephy(tp, 0x1f, 0x0a43);
3641         rtl_writephy(tp, 0x13, 0x0811);
3642         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3643         rtl_writephy(tp, 0x1f, 0x0a42);
3644         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3645         rtl_writephy(tp, 0x1f, 0x0000);
3646
3647         /* enable GPHY 10M */
3648         rtl_writephy(tp, 0x1f, 0x0a44);
3649         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3650         rtl_writephy(tp, 0x1f, 0x0000);
3651
3652         /* SAR ADC performance */
3653         rtl_writephy(tp, 0x1f, 0x0bca);
3654         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3655         rtl_writephy(tp, 0x1f, 0x0000);
3656
3657         rtl_writephy(tp, 0x1f, 0x0a43);
3658         rtl_writephy(tp, 0x13, 0x803f);
3659         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3660         rtl_writephy(tp, 0x13, 0x8047);
3661         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3662         rtl_writephy(tp, 0x13, 0x804f);
3663         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3664         rtl_writephy(tp, 0x13, 0x8057);
3665         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3666         rtl_writephy(tp, 0x13, 0x805f);
3667         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3668         rtl_writephy(tp, 0x13, 0x8067);
3669         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3670         rtl_writephy(tp, 0x13, 0x806f);
3671         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3672         rtl_writephy(tp, 0x1f, 0x0000);
3673
3674         /* disable phy pfm mode */
3675         rtl_writephy(tp, 0x1f, 0x0a44);
3676         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3677         rtl_writephy(tp, 0x1f, 0x0000);
3678
3679         rtl8168g_disable_aldps(tp);
3680         rtl8168g_config_eee_phy(tp);
3681         rtl_enable_eee(tp);
3682 }
3683
3684 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3685 {
3686         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3687         u16 rlen;
3688         u32 data;
3689
3690         rtl_apply_firmware(tp);
3691
3692         /* CHIN EST parameter update */
3693         rtl_writephy(tp, 0x1f, 0x0a43);
3694         rtl_writephy(tp, 0x13, 0x808a);
3695         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3696         rtl_writephy(tp, 0x1f, 0x0000);
3697
3698         /* enable R-tune & PGA-retune function */
3699         rtl_writephy(tp, 0x1f, 0x0a43);
3700         rtl_writephy(tp, 0x13, 0x0811);
3701         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3702         rtl_writephy(tp, 0x1f, 0x0a42);
3703         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3704         rtl_writephy(tp, 0x1f, 0x0000);
3705
3706         /* enable GPHY 10M */
3707         rtl_writephy(tp, 0x1f, 0x0a44);
3708         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3709         rtl_writephy(tp, 0x1f, 0x0000);
3710
3711         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3712         data = r8168_mac_ocp_read(tp, 0xdd02);
3713         ioffset_p3 = ((data & 0x80)>>7);
3714         ioffset_p3 <<= 3;
3715
3716         data = r8168_mac_ocp_read(tp, 0xdd00);
3717         ioffset_p3 |= ((data & (0xe000))>>13);
3718         ioffset_p2 = ((data & (0x1e00))>>9);
3719         ioffset_p1 = ((data & (0x01e0))>>5);
3720         ioffset_p0 = ((data & 0x0010)>>4);
3721         ioffset_p0 <<= 3;
3722         ioffset_p0 |= (data & (0x07));
3723         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3724
3725         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3726             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3727                 rtl_writephy(tp, 0x1f, 0x0bcf);
3728                 rtl_writephy(tp, 0x16, data);
3729                 rtl_writephy(tp, 0x1f, 0x0000);
3730         }
3731
3732         /* Modify rlen (TX LPF corner frequency) level */
3733         rtl_writephy(tp, 0x1f, 0x0bcd);
3734         data = rtl_readphy(tp, 0x16);
3735         data &= 0x000f;
3736         rlen = 0;
3737         if (data > 3)
3738                 rlen = data - 3;
3739         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3740         rtl_writephy(tp, 0x17, data);
3741         rtl_writephy(tp, 0x1f, 0x0bcd);
3742         rtl_writephy(tp, 0x1f, 0x0000);
3743
3744         /* disable phy pfm mode */
3745         rtl_writephy(tp, 0x1f, 0x0a44);
3746         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3747         rtl_writephy(tp, 0x1f, 0x0000);
3748
3749         rtl8168g_disable_aldps(tp);
3750         rtl8168g_config_eee_phy(tp);
3751         rtl_enable_eee(tp);
3752 }
3753
3754 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3755 {
3756         /* Enable PHY auto speed down */
3757         rtl_writephy(tp, 0x1f, 0x0a44);
3758         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3759         rtl_writephy(tp, 0x1f, 0x0000);
3760
3761         rtl8168g_phy_adjust_10m_aldps(tp);
3762
3763         /* Enable EEE auto-fallback function */
3764         rtl_writephy(tp, 0x1f, 0x0a4b);
3765         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3766         rtl_writephy(tp, 0x1f, 0x0000);
3767
3768         /* Enable UC LPF tune function */
3769         rtl_writephy(tp, 0x1f, 0x0a43);
3770         rtl_writephy(tp, 0x13, 0x8012);
3771         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3772         rtl_writephy(tp, 0x1f, 0x0000);
3773
3774         /* set rg_sel_sdm_rate */
3775         rtl_writephy(tp, 0x1f, 0x0c42);
3776         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3777         rtl_writephy(tp, 0x1f, 0x0000);
3778
3779         rtl8168g_disable_aldps(tp);
3780         rtl8168g_config_eee_phy(tp);
3781         rtl_enable_eee(tp);
3782 }
3783
3784 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3785 {
3786         rtl8168g_phy_adjust_10m_aldps(tp);
3787
3788         /* Enable UC LPF tune function */
3789         rtl_writephy(tp, 0x1f, 0x0a43);
3790         rtl_writephy(tp, 0x13, 0x8012);
3791         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3792         rtl_writephy(tp, 0x1f, 0x0000);
3793
3794         /* Set rg_sel_sdm_rate */
3795         rtl_writephy(tp, 0x1f, 0x0c42);
3796         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3797         rtl_writephy(tp, 0x1f, 0x0000);
3798
3799         /* Channel estimation parameters */
3800         rtl_writephy(tp, 0x1f, 0x0a43);
3801         rtl_writephy(tp, 0x13, 0x80f3);
3802         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3803         rtl_writephy(tp, 0x13, 0x80f0);
3804         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3805         rtl_writephy(tp, 0x13, 0x80ef);
3806         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3807         rtl_writephy(tp, 0x13, 0x80f6);
3808         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3809         rtl_writephy(tp, 0x13, 0x80ec);
3810         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3811         rtl_writephy(tp, 0x13, 0x80ed);
3812         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3813         rtl_writephy(tp, 0x13, 0x80f2);
3814         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3815         rtl_writephy(tp, 0x13, 0x80f4);
3816         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3817         rtl_writephy(tp, 0x1f, 0x0a43);
3818         rtl_writephy(tp, 0x13, 0x8110);
3819         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3820         rtl_writephy(tp, 0x13, 0x810f);
3821         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3822         rtl_writephy(tp, 0x13, 0x8111);
3823         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3824         rtl_writephy(tp, 0x13, 0x8113);
3825         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3826         rtl_writephy(tp, 0x13, 0x8115);
3827         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3828         rtl_writephy(tp, 0x13, 0x810e);
3829         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3830         rtl_writephy(tp, 0x13, 0x810c);
3831         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3832         rtl_writephy(tp, 0x13, 0x810b);
3833         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3834         rtl_writephy(tp, 0x1f, 0x0a43);
3835         rtl_writephy(tp, 0x13, 0x80d1);
3836         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3837         rtl_writephy(tp, 0x13, 0x80cd);
3838         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3839         rtl_writephy(tp, 0x13, 0x80d3);
3840         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3841         rtl_writephy(tp, 0x13, 0x80d5);
3842         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3843         rtl_writephy(tp, 0x13, 0x80d7);
3844         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3845
3846         /* Force PWM-mode */
3847         rtl_writephy(tp, 0x1f, 0x0bcd);
3848         rtl_writephy(tp, 0x14, 0x5065);
3849         rtl_writephy(tp, 0x14, 0xd065);
3850         rtl_writephy(tp, 0x1f, 0x0bc8);
3851         rtl_writephy(tp, 0x12, 0x00ed);
3852         rtl_writephy(tp, 0x1f, 0x0bcd);
3853         rtl_writephy(tp, 0x14, 0x1065);
3854         rtl_writephy(tp, 0x14, 0x9065);
3855         rtl_writephy(tp, 0x14, 0x1065);
3856         rtl_writephy(tp, 0x1f, 0x0000);
3857
3858         rtl8168g_disable_aldps(tp);
3859         rtl8168g_config_eee_phy(tp);
3860         rtl_enable_eee(tp);
3861 }
3862
3863 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3864 {
3865         static const struct phy_reg phy_reg_init[] = {
3866                 { 0x1f, 0x0003 },
3867                 { 0x08, 0x441d },
3868                 { 0x01, 0x9100 },
3869                 { 0x1f, 0x0000 }
3870         };
3871
3872         rtl_writephy(tp, 0x1f, 0x0000);
3873         rtl_patchphy(tp, 0x11, 1 << 12);
3874         rtl_patchphy(tp, 0x19, 1 << 13);
3875         rtl_patchphy(tp, 0x10, 1 << 15);
3876
3877         rtl_writephy_batch(tp, phy_reg_init);
3878 }
3879
3880 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3881 {
3882         static const struct phy_reg phy_reg_init[] = {
3883                 { 0x1f, 0x0005 },
3884                 { 0x1a, 0x0000 },
3885                 { 0x1f, 0x0000 },
3886
3887                 { 0x1f, 0x0004 },
3888                 { 0x1c, 0x0000 },
3889                 { 0x1f, 0x0000 },
3890
3891                 { 0x1f, 0x0001 },
3892                 { 0x15, 0x7701 },
3893                 { 0x1f, 0x0000 }
3894         };
3895
3896         /* Disable ALDPS before ram code */
3897         rtl_writephy(tp, 0x1f, 0x0000);
3898         rtl_writephy(tp, 0x18, 0x0310);
3899         msleep(100);
3900
3901         rtl_apply_firmware(tp);
3902
3903         rtl_writephy_batch(tp, phy_reg_init);
3904 }
3905
3906 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3907 {
3908         /* Disable ALDPS before setting firmware */
3909         rtl_writephy(tp, 0x1f, 0x0000);
3910         rtl_writephy(tp, 0x18, 0x0310);
3911         msleep(20);
3912
3913         rtl_apply_firmware(tp);
3914
3915         /* EEE setting */
3916         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3917         rtl_writephy(tp, 0x1f, 0x0004);
3918         rtl_writephy(tp, 0x10, 0x401f);
3919         rtl_writephy(tp, 0x19, 0x7030);
3920         rtl_writephy(tp, 0x1f, 0x0000);
3921 }
3922
3923 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3924 {
3925         static const struct phy_reg phy_reg_init[] = {
3926                 { 0x1f, 0x0004 },
3927                 { 0x10, 0xc07f },
3928                 { 0x19, 0x7030 },
3929                 { 0x1f, 0x0000 }
3930         };
3931
3932         /* Disable ALDPS before ram code */
3933         rtl_writephy(tp, 0x1f, 0x0000);
3934         rtl_writephy(tp, 0x18, 0x0310);
3935         msleep(100);
3936
3937         rtl_apply_firmware(tp);
3938
3939         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3940         rtl_writephy_batch(tp, phy_reg_init);
3941
3942         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3943 }
3944
3945 static void rtl_hw_phy_config(struct net_device *dev)
3946 {
3947         static const rtl_generic_fct phy_configs[] = {
3948                 /* PCI devices. */
3949                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3950                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3951                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3952                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3953                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3954                 /* PCI-E devices. */
3955                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3956                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3957                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3958                 [RTL_GIGA_MAC_VER_10] = NULL,
3959                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3960                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3961                 [RTL_GIGA_MAC_VER_13] = NULL,
3962                 [RTL_GIGA_MAC_VER_14] = NULL,
3963                 [RTL_GIGA_MAC_VER_15] = NULL,
3964                 [RTL_GIGA_MAC_VER_16] = NULL,
3965                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3966                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3967                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3968                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3969                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3970                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3971                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3972                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3973                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3974                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3975                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3976                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3977                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3978                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3979                 [RTL_GIGA_MAC_VER_31] = NULL,
3980                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3981                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3982                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3983                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3984                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3985                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3986                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3987                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3988                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3989                 [RTL_GIGA_MAC_VER_41] = NULL,
3990                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3991                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3992                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3993                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3994                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3995                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3996                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3997                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3998                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3999                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
4000         };
4001         struct rtl8169_private *tp = netdev_priv(dev);
4002
4003         if (phy_configs[tp->mac_version])
4004                 phy_configs[tp->mac_version](tp);
4005 }
4006
4007 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4008 {
4009         if (!test_and_set_bit(flag, tp->wk.flags))
4010                 schedule_work(&tp->wk.work);
4011 }
4012
4013 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4014 {
4015         rtl_hw_phy_config(dev);
4016
4017         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4018                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4019                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4020                 netif_dbg(tp, drv, dev,
4021                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4022                 RTL_W8(tp, 0x82, 0x01);
4023         }
4024
4025         /* We may have called phy_speed_down before */
4026         phy_speed_up(tp->phydev);
4027
4028         genphy_soft_reset(tp->phydev);
4029 }
4030
4031 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4032 {
4033         rtl_lock_work(tp);
4034
4035         rtl_unlock_config_regs(tp);
4036
4037         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4038         RTL_R32(tp, MAC4);
4039
4040         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4041         RTL_R32(tp, MAC0);
4042
4043         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4044                 rtl_rar_exgmac_set(tp, addr);
4045
4046         rtl_lock_config_regs(tp);
4047
4048         rtl_unlock_work(tp);
4049 }
4050
4051 static int rtl_set_mac_address(struct net_device *dev, void *p)
4052 {
4053         struct rtl8169_private *tp = netdev_priv(dev);
4054         struct device *d = tp_to_dev(tp);
4055         int ret;
4056
4057         ret = eth_mac_addr(dev, p);
4058         if (ret)
4059                 return ret;
4060
4061         pm_runtime_get_noresume(d);
4062
4063         if (pm_runtime_active(d))
4064                 rtl_rar_set(tp, dev->dev_addr);
4065
4066         pm_runtime_put_noidle(d);
4067
4068         return 0;
4069 }
4070
4071 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4072 {
4073         struct rtl8169_private *tp = netdev_priv(dev);
4074
4075         if (!netif_running(dev))
4076                 return -ENODEV;
4077
4078         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4079 }
4080
4081 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4082 {
4083         switch (tp->mac_version) {
4084         case RTL_GIGA_MAC_VER_25:
4085         case RTL_GIGA_MAC_VER_26:
4086         case RTL_GIGA_MAC_VER_29:
4087         case RTL_GIGA_MAC_VER_30:
4088         case RTL_GIGA_MAC_VER_32:
4089         case RTL_GIGA_MAC_VER_33:
4090         case RTL_GIGA_MAC_VER_34:
4091         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4092                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4093                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4094                 break;
4095         default:
4096                 break;
4097         }
4098 }
4099
4100 static void rtl_pll_power_down(struct rtl8169_private *tp)
4101 {
4102         if (r8168_check_dash(tp))
4103                 return;
4104
4105         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4106             tp->mac_version == RTL_GIGA_MAC_VER_33)
4107                 rtl_ephy_write(tp, 0x19, 0xff64);
4108
4109         if (device_may_wakeup(tp_to_dev(tp))) {
4110                 phy_speed_down(tp->phydev, false);
4111                 rtl_wol_suspend_quirk(tp);
4112                 return;
4113         }
4114
4115         switch (tp->mac_version) {
4116         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4117         case RTL_GIGA_MAC_VER_37:
4118         case RTL_GIGA_MAC_VER_39:
4119         case RTL_GIGA_MAC_VER_43:
4120         case RTL_GIGA_MAC_VER_44:
4121         case RTL_GIGA_MAC_VER_45:
4122         case RTL_GIGA_MAC_VER_46:
4123         case RTL_GIGA_MAC_VER_47:
4124         case RTL_GIGA_MAC_VER_48:
4125         case RTL_GIGA_MAC_VER_50:
4126         case RTL_GIGA_MAC_VER_51:
4127                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4128                 break;
4129         case RTL_GIGA_MAC_VER_40:
4130         case RTL_GIGA_MAC_VER_41:
4131         case RTL_GIGA_MAC_VER_49:
4132                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4133                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4134                 break;
4135         default:
4136                 break;
4137         }
4138 }
4139
4140 static void rtl_pll_power_up(struct rtl8169_private *tp)
4141 {
4142         switch (tp->mac_version) {
4143         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4144         case RTL_GIGA_MAC_VER_37:
4145         case RTL_GIGA_MAC_VER_39:
4146         case RTL_GIGA_MAC_VER_43:
4147                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4148                 break;
4149         case RTL_GIGA_MAC_VER_44:
4150         case RTL_GIGA_MAC_VER_45:
4151         case RTL_GIGA_MAC_VER_46:
4152         case RTL_GIGA_MAC_VER_47:
4153         case RTL_GIGA_MAC_VER_48:
4154         case RTL_GIGA_MAC_VER_50:
4155         case RTL_GIGA_MAC_VER_51:
4156                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4157                 break;
4158         case RTL_GIGA_MAC_VER_40:
4159         case RTL_GIGA_MAC_VER_41:
4160         case RTL_GIGA_MAC_VER_49:
4161                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4162                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4163                 break;
4164         default:
4165                 break;
4166         }
4167
4168         phy_resume(tp->phydev);
4169         /* give MAC/PHY some time to resume */
4170         msleep(20);
4171 }
4172
4173 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4174 {
4175         switch (tp->mac_version) {
4176         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4177         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4178                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4179                 break;
4180         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4181         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4182         case RTL_GIGA_MAC_VER_38:
4183                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4184                 break;
4185         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4186                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4187                 break;
4188         default:
4189                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4190                 break;
4191         }
4192 }
4193
4194 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4195 {
4196         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4197 }
4198
4199 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4200 {
4201         if (tp->jumbo_ops.enable) {
4202                 rtl_unlock_config_regs(tp);
4203                 tp->jumbo_ops.enable(tp);
4204                 rtl_lock_config_regs(tp);
4205         }
4206 }
4207
4208 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4209 {
4210         if (tp->jumbo_ops.disable) {
4211                 rtl_unlock_config_regs(tp);
4212                 tp->jumbo_ops.disable(tp);
4213                 rtl_lock_config_regs(tp);
4214         }
4215 }
4216
4217 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4218 {
4219         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4220         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4221         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4222 }
4223
4224 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4225 {
4226         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4227         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4228         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4229 }
4230
4231 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4232 {
4233         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4234 }
4235
4236 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4237 {
4238         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4239 }
4240
4241 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4242 {
4243         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4244         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4245         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4246         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4247 }
4248
4249 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4250 {
4251         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4252         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4253         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4254         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4255 }
4256
4257 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4258 {
4259         rtl_tx_performance_tweak(tp,
4260                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4261 }
4262
4263 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4264 {
4265         rtl_tx_performance_tweak(tp,
4266                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4267 }
4268
4269 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4270 {
4271         r8168b_0_hw_jumbo_enable(tp);
4272
4273         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4274 }
4275
4276 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4277 {
4278         r8168b_0_hw_jumbo_disable(tp);
4279
4280         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4281 }
4282
4283 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4284 {
4285         struct jumbo_ops *ops = &tp->jumbo_ops;
4286
4287         switch (tp->mac_version) {
4288         case RTL_GIGA_MAC_VER_11:
4289                 ops->disable    = r8168b_0_hw_jumbo_disable;
4290                 ops->enable     = r8168b_0_hw_jumbo_enable;
4291                 break;
4292         case RTL_GIGA_MAC_VER_12:
4293         case RTL_GIGA_MAC_VER_17:
4294                 ops->disable    = r8168b_1_hw_jumbo_disable;
4295                 ops->enable     = r8168b_1_hw_jumbo_enable;
4296                 break;
4297         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4298         case RTL_GIGA_MAC_VER_19:
4299         case RTL_GIGA_MAC_VER_20:
4300         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4301         case RTL_GIGA_MAC_VER_22:
4302         case RTL_GIGA_MAC_VER_23:
4303         case RTL_GIGA_MAC_VER_24:
4304         case RTL_GIGA_MAC_VER_25:
4305         case RTL_GIGA_MAC_VER_26:
4306                 ops->disable    = r8168c_hw_jumbo_disable;
4307                 ops->enable     = r8168c_hw_jumbo_enable;
4308                 break;
4309         case RTL_GIGA_MAC_VER_27:
4310         case RTL_GIGA_MAC_VER_28:
4311                 ops->disable    = r8168dp_hw_jumbo_disable;
4312                 ops->enable     = r8168dp_hw_jumbo_enable;
4313                 break;
4314         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4315         case RTL_GIGA_MAC_VER_32:
4316         case RTL_GIGA_MAC_VER_33:
4317         case RTL_GIGA_MAC_VER_34:
4318                 ops->disable    = r8168e_hw_jumbo_disable;
4319                 ops->enable     = r8168e_hw_jumbo_enable;
4320                 break;
4321
4322         /*
4323          * No action needed for jumbo frames with 8169.
4324          * No jumbo for 810x at all.
4325          */
4326         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4327         default:
4328                 ops->disable    = NULL;
4329                 ops->enable     = NULL;
4330                 break;
4331         }
4332 }
4333
4334 DECLARE_RTL_COND(rtl_chipcmd_cond)
4335 {
4336         return RTL_R8(tp, ChipCmd) & CmdReset;
4337 }
4338
4339 static void rtl_hw_reset(struct rtl8169_private *tp)
4340 {
4341         RTL_W8(tp, ChipCmd, CmdReset);
4342
4343         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4344 }
4345
4346 static void rtl_request_firmware(struct rtl8169_private *tp)
4347 {
4348         struct rtl_fw *rtl_fw;
4349         int rc = -ENOMEM;
4350
4351         /* firmware loaded already or no firmware available */
4352         if (tp->rtl_fw || !tp->fw_name)
4353                 return;
4354
4355         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4356         if (!rtl_fw)
4357                 goto err_warn;
4358
4359         rtl_fw->phy_write = rtl_writephy;
4360         rtl_fw->phy_read = rtl_readphy;
4361         rtl_fw->mac_mcu_write = mac_mcu_write;
4362         rtl_fw->mac_mcu_read = mac_mcu_read;
4363
4364         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4365         if (rc < 0)
4366                 goto err_free;
4367
4368         rc = rtl_check_firmware(tp, rtl_fw);
4369         if (rc < 0)
4370                 goto err_release_firmware;
4371
4372         tp->rtl_fw = rtl_fw;
4373
4374         return;
4375
4376 err_release_firmware:
4377         release_firmware(rtl_fw->fw);
4378 err_free:
4379         kfree(rtl_fw);
4380 err_warn:
4381         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4382                    tp->fw_name, rc);
4383 }
4384
4385 static void rtl_rx_close(struct rtl8169_private *tp)
4386 {
4387         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4388 }
4389
4390 DECLARE_RTL_COND(rtl_npq_cond)
4391 {
4392         return RTL_R8(tp, TxPoll) & NPQ;
4393 }
4394
4395 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4396 {
4397         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4398 }
4399
4400 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4401 {
4402         /* Disable interrupts */
4403         rtl8169_irq_mask_and_ack(tp);
4404
4405         rtl_rx_close(tp);
4406
4407         switch (tp->mac_version) {
4408         case RTL_GIGA_MAC_VER_27:
4409         case RTL_GIGA_MAC_VER_28:
4410         case RTL_GIGA_MAC_VER_31:
4411                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4412                 break;
4413         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4414         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4415                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4416                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4417                 break;
4418         default:
4419                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4420                 udelay(100);
4421                 break;
4422         }
4423
4424         rtl_hw_reset(tp);
4425 }
4426
4427 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4428 {
4429         u32 val = TX_DMA_BURST << TxDMAShift |
4430                   InterFrameGap << TxInterFrameGapShift;
4431
4432         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4433             tp->mac_version != RTL_GIGA_MAC_VER_39)
4434                 val |= TXCFG_AUTO_FIFO;
4435
4436         RTL_W32(tp, TxConfig, val);
4437 }
4438
4439 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4440 {
4441         /* Low hurts. Let's disable the filtering. */
4442         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4443 }
4444
4445 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4446 {
4447         /*
4448          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4449          * register to be written before TxDescAddrLow to work.
4450          * Switching from MMIO to I/O access fixes the issue as well.
4451          */
4452         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4453         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4454         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4455         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4456 }
4457
4458 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4459 {
4460         u32 val;
4461
4462         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4463                 val = 0x000fff00;
4464         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4465                 val = 0x00ffff00;
4466         else
4467                 return;
4468
4469         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4470                 val |= 0xff;
4471
4472         RTL_W32(tp, 0x7c, val);
4473 }
4474
4475 static void rtl_set_rx_mode(struct net_device *dev)
4476 {
4477         struct rtl8169_private *tp = netdev_priv(dev);
4478         u32 mc_filter[2];       /* Multicast hash filter */
4479         int rx_mode;
4480         u32 tmp = 0;
4481
4482         if (dev->flags & IFF_PROMISC) {
4483                 /* Unconditionally log net taps. */
4484                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4485                 rx_mode =
4486                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4487                     AcceptAllPhys;
4488                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4489         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4490                    (dev->flags & IFF_ALLMULTI)) {
4491                 /* Too many to filter perfectly -- accept all multicasts. */
4492                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4493                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4494         } else {
4495                 struct netdev_hw_addr *ha;
4496
4497                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4498                 mc_filter[1] = mc_filter[0] = 0;
4499                 netdev_for_each_mc_addr(ha, dev) {
4500                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4501                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4502                         rx_mode |= AcceptMulticast;
4503                 }
4504         }
4505
4506         if (dev->features & NETIF_F_RXALL)
4507                 rx_mode |= (AcceptErr | AcceptRunt);
4508
4509         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4510
4511         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4512                 u32 data = mc_filter[0];
4513
4514                 mc_filter[0] = swab32(mc_filter[1]);
4515                 mc_filter[1] = swab32(data);
4516         }
4517
4518         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4519                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4520
4521         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4522         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4523
4524         RTL_W32(tp, RxConfig, tmp);
4525 }
4526
4527 static void rtl_hw_start(struct  rtl8169_private *tp)
4528 {
4529         rtl_unlock_config_regs(tp);
4530
4531         tp->hw_start(tp);
4532
4533         rtl_set_rx_max_size(tp);
4534         rtl_set_rx_tx_desc_registers(tp);
4535         rtl_lock_config_regs(tp);
4536
4537         /* disable interrupt coalescing */
4538         RTL_W16(tp, IntrMitigate, 0x0000);
4539         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4540         RTL_R8(tp, IntrMask);
4541         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4542         rtl_init_rxcfg(tp);
4543         rtl_set_tx_config_registers(tp);
4544
4545         rtl_set_rx_mode(tp->dev);
4546         /* no early-rx interrupts */
4547         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4548         rtl_irq_enable(tp);
4549 }
4550
4551 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4552 {
4553         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4554                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4555
4556         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4557
4558         tp->cp_cmd |= PCIMulRW;
4559
4560         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4561             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4562                 netif_dbg(tp, drv, tp->dev,
4563                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4564                 tp->cp_cmd |= (1 << 14);
4565         }
4566
4567         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4568
4569         rtl8169_set_magic_reg(tp, tp->mac_version);
4570
4571         RTL_W32(tp, RxMissed, 0);
4572 }
4573
4574 DECLARE_RTL_COND(rtl_csiar_cond)
4575 {
4576         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4577 }
4578
4579 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4580 {
4581         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4582
4583         RTL_W32(tp, CSIDR, value);
4584         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4585                 CSIAR_BYTE_ENABLE | func << 16);
4586
4587         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4588 }
4589
4590 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4591 {
4592         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4593
4594         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4595                 CSIAR_BYTE_ENABLE);
4596
4597         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4598                 RTL_R32(tp, CSIDR) : ~0;
4599 }
4600
4601 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4602 {
4603         struct pci_dev *pdev = tp->pci_dev;
4604         u32 csi;
4605
4606         /* According to Realtek the value at config space address 0x070f
4607          * controls the L0s/L1 entrance latency. We try standard ECAM access
4608          * first and if it fails fall back to CSI.
4609          */
4610         if (pdev->cfg_size > 0x070f &&
4611             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4612                 return;
4613
4614         netdev_notice_once(tp->dev,
4615                 "No native access to PCI extended config space, falling back to CSI\n");
4616         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4617         rtl_csi_write(tp, 0x070c, csi | val << 24);
4618 }
4619
4620 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4621 {
4622         rtl_csi_access_enable(tp, 0x27);
4623 }
4624
4625 struct ephy_info {
4626         unsigned int offset;
4627         u16 mask;
4628         u16 bits;
4629 };
4630
4631 static void __rtl_ephy_init(struct rtl8169_private *tp,
4632                             const struct ephy_info *e, int len)
4633 {
4634         u16 w;
4635
4636         while (len-- > 0) {
4637                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4638                 rtl_ephy_write(tp, e->offset, w);
4639                 e++;
4640         }
4641 }
4642
4643 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4644
4645 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4646 {
4647         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4648                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4649 }
4650
4651 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4652 {
4653         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4654                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4655 }
4656
4657 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4658 {
4659         /* work around an issue when PCI reset occurs during L2/L3 state */
4660         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4661 }
4662
4663 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4664 {
4665         if (enable) {
4666                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4667                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4668         } else {
4669                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4670                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4671         }
4672
4673         udelay(10);
4674 }
4675
4676 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4677                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4678 {
4679         /* Usage of dynamic vs. static FIFO is controlled by bit
4680          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4681          */
4682         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4683         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4684 }
4685
4686 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4687                                           u8 low, u8 high)
4688 {
4689         /* FIFO thresholds for pause flow control */
4690         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4691         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4692 }
4693
4694 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4695 {
4696         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4697
4698         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4699         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4700
4701         if (tp->dev->mtu <= ETH_DATA_LEN) {
4702                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4703                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4704         }
4705 }
4706
4707 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4708 {
4709         rtl_hw_start_8168bb(tp);
4710
4711         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4712
4713         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4714 }
4715
4716 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4717 {
4718         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4719
4720         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4721
4722         if (tp->dev->mtu <= ETH_DATA_LEN)
4723                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4724
4725         rtl_disable_clock_request(tp);
4726
4727         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4728         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4729 }
4730
4731 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4732 {
4733         static const struct ephy_info e_info_8168cp[] = {
4734                 { 0x01, 0,      0x0001 },
4735                 { 0x02, 0x0800, 0x1000 },
4736                 { 0x03, 0,      0x0042 },
4737                 { 0x06, 0x0080, 0x0000 },
4738                 { 0x07, 0,      0x2000 }
4739         };
4740
4741         rtl_set_def_aspm_entry_latency(tp);
4742
4743         rtl_ephy_init(tp, e_info_8168cp);
4744
4745         __rtl_hw_start_8168cp(tp);
4746 }
4747
4748 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4749 {
4750         rtl_set_def_aspm_entry_latency(tp);
4751
4752         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4753
4754         if (tp->dev->mtu <= ETH_DATA_LEN)
4755                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4756
4757         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4758         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4759 }
4760
4761 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4762 {
4763         rtl_set_def_aspm_entry_latency(tp);
4764
4765         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4766
4767         /* Magic. */
4768         RTL_W8(tp, DBG_REG, 0x20);
4769
4770         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4771
4772         if (tp->dev->mtu <= ETH_DATA_LEN)
4773                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4774
4775         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4776         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4777 }
4778
4779 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4780 {
4781         static const struct ephy_info e_info_8168c_1[] = {
4782                 { 0x02, 0x0800, 0x1000 },
4783                 { 0x03, 0,      0x0002 },
4784                 { 0x06, 0x0080, 0x0000 }
4785         };
4786
4787         rtl_set_def_aspm_entry_latency(tp);
4788
4789         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4790
4791         rtl_ephy_init(tp, e_info_8168c_1);
4792
4793         __rtl_hw_start_8168cp(tp);
4794 }
4795
4796 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4797 {
4798         static const struct ephy_info e_info_8168c_2[] = {
4799                 { 0x01, 0,      0x0001 },
4800                 { 0x03, 0x0400, 0x0220 }
4801         };
4802
4803         rtl_set_def_aspm_entry_latency(tp);
4804
4805         rtl_ephy_init(tp, e_info_8168c_2);
4806
4807         __rtl_hw_start_8168cp(tp);
4808 }
4809
4810 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4811 {
4812         rtl_hw_start_8168c_2(tp);
4813 }
4814
4815 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4816 {
4817         rtl_set_def_aspm_entry_latency(tp);
4818
4819         __rtl_hw_start_8168cp(tp);
4820 }
4821
4822 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4823 {
4824         rtl_set_def_aspm_entry_latency(tp);
4825
4826         rtl_disable_clock_request(tp);
4827
4828         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4829
4830         if (tp->dev->mtu <= ETH_DATA_LEN)
4831                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4832
4833         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4834         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4835 }
4836
4837 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4838 {
4839         rtl_set_def_aspm_entry_latency(tp);
4840
4841         if (tp->dev->mtu <= ETH_DATA_LEN)
4842                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4843
4844         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4845
4846         rtl_disable_clock_request(tp);
4847 }
4848
4849 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4850 {
4851         static const struct ephy_info e_info_8168d_4[] = {
4852                 { 0x0b, 0x0000, 0x0048 },
4853                 { 0x19, 0x0020, 0x0050 },
4854                 { 0x0c, 0x0100, 0x0020 }
4855         };
4856
4857         rtl_set_def_aspm_entry_latency(tp);
4858
4859         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4860
4861         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4862
4863         rtl_ephy_init(tp, e_info_8168d_4);
4864
4865         rtl_enable_clock_request(tp);
4866 }
4867
4868 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4869 {
4870         static const struct ephy_info e_info_8168e_1[] = {
4871                 { 0x00, 0x0200, 0x0100 },
4872                 { 0x00, 0x0000, 0x0004 },
4873                 { 0x06, 0x0002, 0x0001 },
4874                 { 0x06, 0x0000, 0x0030 },
4875                 { 0x07, 0x0000, 0x2000 },
4876                 { 0x00, 0x0000, 0x0020 },
4877                 { 0x03, 0x5800, 0x2000 },
4878                 { 0x03, 0x0000, 0x0001 },
4879                 { 0x01, 0x0800, 0x1000 },
4880                 { 0x07, 0x0000, 0x4000 },
4881                 { 0x1e, 0x0000, 0x2000 },
4882                 { 0x19, 0xffff, 0xfe6c },
4883                 { 0x0a, 0x0000, 0x0040 }
4884         };
4885
4886         rtl_set_def_aspm_entry_latency(tp);
4887
4888         rtl_ephy_init(tp, e_info_8168e_1);
4889
4890         if (tp->dev->mtu <= ETH_DATA_LEN)
4891                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4892
4893         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4894
4895         rtl_disable_clock_request(tp);
4896
4897         /* Reset tx FIFO pointer */
4898         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4899         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4900
4901         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4902 }
4903
4904 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4905 {
4906         static const struct ephy_info e_info_8168e_2[] = {
4907                 { 0x09, 0x0000, 0x0080 },
4908                 { 0x19, 0x0000, 0x0224 }
4909         };
4910
4911         rtl_set_def_aspm_entry_latency(tp);
4912
4913         rtl_ephy_init(tp, e_info_8168e_2);
4914
4915         if (tp->dev->mtu <= ETH_DATA_LEN)
4916                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4917
4918         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4919         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4920         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4921         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4922         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4923         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4924         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4925
4926         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4927
4928         rtl_disable_clock_request(tp);
4929
4930         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4931
4932         rtl8168_config_eee_mac(tp);
4933
4934         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4935         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4936         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4937
4938         rtl_hw_aspm_clkreq_enable(tp, true);
4939 }
4940
4941 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4942 {
4943         rtl_set_def_aspm_entry_latency(tp);
4944
4945         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4946
4947         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4948         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4949         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4950         rtl_reset_packet_filter(tp);
4951         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4952         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4953         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4954         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4955
4956         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4957
4958         rtl_disable_clock_request(tp);
4959
4960         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4961         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4962         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4963         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4964
4965         rtl8168_config_eee_mac(tp);
4966 }
4967
4968 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4969 {
4970         static const struct ephy_info e_info_8168f_1[] = {
4971                 { 0x06, 0x00c0, 0x0020 },
4972                 { 0x08, 0x0001, 0x0002 },
4973                 { 0x09, 0x0000, 0x0080 },
4974                 { 0x19, 0x0000, 0x0224 }
4975         };
4976
4977         rtl_hw_start_8168f(tp);
4978
4979         rtl_ephy_init(tp, e_info_8168f_1);
4980
4981         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4982 }
4983
4984 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4985 {
4986         static const struct ephy_info e_info_8168f_1[] = {
4987                 { 0x06, 0x00c0, 0x0020 },
4988                 { 0x0f, 0xffff, 0x5200 },
4989                 { 0x1e, 0x0000, 0x4000 },
4990                 { 0x19, 0x0000, 0x0224 }
4991         };
4992
4993         rtl_hw_start_8168f(tp);
4994         rtl_pcie_state_l2l3_disable(tp);
4995
4996         rtl_ephy_init(tp, e_info_8168f_1);
4997
4998         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4999 }
5000
5001 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5002 {
5003         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5004         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5005
5006         rtl_set_def_aspm_entry_latency(tp);
5007
5008         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5009
5010         rtl_reset_packet_filter(tp);
5011         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
5012
5013         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5014         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5015
5016         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5017         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5018
5019         rtl8168_config_eee_mac(tp);
5020
5021         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5022         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5023
5024         rtl_pcie_state_l2l3_disable(tp);
5025 }
5026
5027 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5028 {
5029         static const struct ephy_info e_info_8168g_1[] = {
5030                 { 0x00, 0x0000, 0x0008 },
5031                 { 0x0c, 0x37d0, 0x0820 },
5032                 { 0x1e, 0x0000, 0x0001 },
5033                 { 0x19, 0x8000, 0x0000 }
5034         };
5035
5036         rtl_hw_start_8168g(tp);
5037
5038         /* disable aspm and clock request before access ephy */
5039         rtl_hw_aspm_clkreq_enable(tp, false);
5040         rtl_ephy_init(tp, e_info_8168g_1);
5041         rtl_hw_aspm_clkreq_enable(tp, true);
5042 }
5043
5044 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5045 {
5046         static const struct ephy_info e_info_8168g_2[] = {
5047                 { 0x00, 0x0000, 0x0008 },
5048                 { 0x0c, 0x3df0, 0x0200 },
5049                 { 0x19, 0xffff, 0xfc00 },
5050                 { 0x1e, 0xffff, 0x20eb }
5051         };
5052
5053         rtl_hw_start_8168g(tp);
5054
5055         /* disable aspm and clock request before access ephy */
5056         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5057         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5058         rtl_ephy_init(tp, e_info_8168g_2);
5059 }
5060
5061 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5062 {
5063         static const struct ephy_info e_info_8411_2[] = {
5064                 { 0x00, 0x0000, 0x0008 },
5065                 { 0x0c, 0x3df0, 0x0200 },
5066                 { 0x0f, 0xffff, 0x5200 },
5067                 { 0x19, 0x0020, 0x0000 },
5068                 { 0x1e, 0x0000, 0x2000 }
5069         };
5070
5071         rtl_hw_start_8168g(tp);
5072
5073         /* disable aspm and clock request before access ephy */
5074         rtl_hw_aspm_clkreq_enable(tp, false);
5075         rtl_ephy_init(tp, e_info_8411_2);
5076         rtl_hw_aspm_clkreq_enable(tp, true);
5077 }
5078
5079 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5080 {
5081         int rg_saw_cnt;
5082         u32 data;
5083         static const struct ephy_info e_info_8168h_1[] = {
5084                 { 0x1e, 0x0800, 0x0001 },
5085                 { 0x1d, 0x0000, 0x0800 },
5086                 { 0x05, 0xffff, 0x2089 },
5087                 { 0x06, 0xffff, 0x5881 },
5088                 { 0x04, 0xffff, 0x154a },
5089                 { 0x01, 0xffff, 0x068b }
5090         };
5091
5092         /* disable aspm and clock request before access ephy */
5093         rtl_hw_aspm_clkreq_enable(tp, false);
5094         rtl_ephy_init(tp, e_info_8168h_1);
5095
5096         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5097         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5098
5099         rtl_set_def_aspm_entry_latency(tp);
5100
5101         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5102
5103         rtl_reset_packet_filter(tp);
5104
5105         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5106
5107         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5108
5109         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5110
5111         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5112         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5113
5114         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5115         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5116
5117         rtl8168_config_eee_mac(tp);
5118
5119         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5120         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5121
5122         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5123
5124         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5125
5126         rtl_pcie_state_l2l3_disable(tp);
5127
5128         rtl_writephy(tp, 0x1f, 0x0c42);
5129         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5130         rtl_writephy(tp, 0x1f, 0x0000);
5131         if (rg_saw_cnt > 0) {
5132                 u16 sw_cnt_1ms_ini;
5133
5134                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5135                 sw_cnt_1ms_ini &= 0x0fff;
5136                 data = r8168_mac_ocp_read(tp, 0xd412);
5137                 data &= ~0x0fff;
5138                 data |= sw_cnt_1ms_ini;
5139                 r8168_mac_ocp_write(tp, 0xd412, data);
5140         }
5141
5142         data = r8168_mac_ocp_read(tp, 0xe056);
5143         data &= ~0xf0;
5144         data |= 0x70;
5145         r8168_mac_ocp_write(tp, 0xe056, data);
5146
5147         data = r8168_mac_ocp_read(tp, 0xe052);
5148         data &= ~0x6000;
5149         data |= 0x8008;
5150         r8168_mac_ocp_write(tp, 0xe052, data);
5151
5152         data = r8168_mac_ocp_read(tp, 0xe0d6);
5153         data &= ~0x01ff;
5154         data |= 0x017f;
5155         r8168_mac_ocp_write(tp, 0xe0d6, data);
5156
5157         data = r8168_mac_ocp_read(tp, 0xd420);
5158         data &= ~0x0fff;
5159         data |= 0x047f;
5160         r8168_mac_ocp_write(tp, 0xd420, data);
5161
5162         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5163         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5164         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5165         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5166
5167         rtl_hw_aspm_clkreq_enable(tp, true);
5168 }
5169
5170 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5171 {
5172         rtl8168ep_stop_cmac(tp);
5173
5174         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5175         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5176
5177         rtl_set_def_aspm_entry_latency(tp);
5178
5179         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5180
5181         rtl_reset_packet_filter(tp);
5182
5183         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5184
5185         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5186
5187         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5188         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5189
5190         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5191         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5192
5193         rtl8168_config_eee_mac(tp);
5194
5195         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5196
5197         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5198
5199         rtl_pcie_state_l2l3_disable(tp);
5200 }
5201
5202 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5203 {
5204         static const struct ephy_info e_info_8168ep_1[] = {
5205                 { 0x00, 0xffff, 0x10ab },
5206                 { 0x06, 0xffff, 0xf030 },
5207                 { 0x08, 0xffff, 0x2006 },
5208                 { 0x0d, 0xffff, 0x1666 },
5209                 { 0x0c, 0x3ff0, 0x0000 }
5210         };
5211
5212         /* disable aspm and clock request before access ephy */
5213         rtl_hw_aspm_clkreq_enable(tp, false);
5214         rtl_ephy_init(tp, e_info_8168ep_1);
5215
5216         rtl_hw_start_8168ep(tp);
5217
5218         rtl_hw_aspm_clkreq_enable(tp, true);
5219 }
5220
5221 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5222 {
5223         static const struct ephy_info e_info_8168ep_2[] = {
5224                 { 0x00, 0xffff, 0x10a3 },
5225                 { 0x19, 0xffff, 0xfc00 },
5226                 { 0x1e, 0xffff, 0x20ea }
5227         };
5228
5229         /* disable aspm and clock request before access ephy */
5230         rtl_hw_aspm_clkreq_enable(tp, false);
5231         rtl_ephy_init(tp, e_info_8168ep_2);
5232
5233         rtl_hw_start_8168ep(tp);
5234
5235         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5236         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5237
5238         rtl_hw_aspm_clkreq_enable(tp, true);
5239 }
5240
5241 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5242 {
5243         u32 data;
5244         static const struct ephy_info e_info_8168ep_3[] = {
5245                 { 0x00, 0xffff, 0x10a3 },
5246                 { 0x19, 0xffff, 0x7c00 },
5247                 { 0x1e, 0xffff, 0x20eb },
5248                 { 0x0d, 0xffff, 0x1666 }
5249         };
5250
5251         /* disable aspm and clock request before access ephy */
5252         rtl_hw_aspm_clkreq_enable(tp, false);
5253         rtl_ephy_init(tp, e_info_8168ep_3);
5254
5255         rtl_hw_start_8168ep(tp);
5256
5257         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5258         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5259
5260         data = r8168_mac_ocp_read(tp, 0xd3e2);
5261         data &= 0xf000;
5262         data |= 0x0271;
5263         r8168_mac_ocp_write(tp, 0xd3e2, data);
5264
5265         data = r8168_mac_ocp_read(tp, 0xd3e4);
5266         data &= 0xff00;
5267         r8168_mac_ocp_write(tp, 0xd3e4, data);
5268
5269         data = r8168_mac_ocp_read(tp, 0xe860);
5270         data |= 0x0080;
5271         r8168_mac_ocp_write(tp, 0xe860, data);
5272
5273         rtl_hw_aspm_clkreq_enable(tp, true);
5274 }
5275
5276 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5277 {
5278         static const struct ephy_info e_info_8102e_1[] = {
5279                 { 0x01, 0, 0x6e65 },
5280                 { 0x02, 0, 0x091f },
5281                 { 0x03, 0, 0xc2f9 },
5282                 { 0x06, 0, 0xafb5 },
5283                 { 0x07, 0, 0x0e00 },
5284                 { 0x19, 0, 0xec80 },
5285                 { 0x01, 0, 0x2e65 },
5286                 { 0x01, 0, 0x6e65 }
5287         };
5288         u8 cfg1;
5289
5290         rtl_set_def_aspm_entry_latency(tp);
5291
5292         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5293
5294         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5295
5296         RTL_W8(tp, Config1,
5297                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5298         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5299
5300         cfg1 = RTL_R8(tp, Config1);
5301         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5302                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5303
5304         rtl_ephy_init(tp, e_info_8102e_1);
5305 }
5306
5307 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5308 {
5309         rtl_set_def_aspm_entry_latency(tp);
5310
5311         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5312
5313         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5314         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5315 }
5316
5317 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5318 {
5319         rtl_hw_start_8102e_2(tp);
5320
5321         rtl_ephy_write(tp, 0x03, 0xc2f9);
5322 }
5323
5324 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5325 {
5326         static const struct ephy_info e_info_8105e_1[] = {
5327                 { 0x07, 0, 0x4000 },
5328                 { 0x19, 0, 0x0200 },
5329                 { 0x19, 0, 0x0020 },
5330                 { 0x1e, 0, 0x2000 },
5331                 { 0x03, 0, 0x0001 },
5332                 { 0x19, 0, 0x0100 },
5333                 { 0x19, 0, 0x0004 },
5334                 { 0x0a, 0, 0x0020 }
5335         };
5336
5337         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5338         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5339
5340         /* Disable Early Tally Counter */
5341         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5342
5343         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5344         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5345
5346         rtl_ephy_init(tp, e_info_8105e_1);
5347
5348         rtl_pcie_state_l2l3_disable(tp);
5349 }
5350
5351 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5352 {
5353         rtl_hw_start_8105e_1(tp);
5354         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5355 }
5356
5357 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5358 {
5359         static const struct ephy_info e_info_8402[] = {
5360                 { 0x19, 0xffff, 0xff64 },
5361                 { 0x1e, 0, 0x4000 }
5362         };
5363
5364         rtl_set_def_aspm_entry_latency(tp);
5365
5366         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5367         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5368
5369         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5370
5371         rtl_ephy_init(tp, e_info_8402);
5372
5373         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5374
5375         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5376         rtl_reset_packet_filter(tp);
5377         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5378         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5379         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5380
5381         rtl_pcie_state_l2l3_disable(tp);
5382 }
5383
5384 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5385 {
5386         rtl_hw_aspm_clkreq_enable(tp, false);
5387
5388         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5389         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5390
5391         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5392         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5393         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5394
5395         rtl_pcie_state_l2l3_disable(tp);
5396         rtl_hw_aspm_clkreq_enable(tp, true);
5397 }
5398
5399 static void rtl_hw_config(struct rtl8169_private *tp)
5400 {
5401         static const rtl_generic_fct hw_configs[] = {
5402                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5403                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5404                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5405                 [RTL_GIGA_MAC_VER_10] = NULL,
5406                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5407                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5408                 [RTL_GIGA_MAC_VER_13] = NULL,
5409                 [RTL_GIGA_MAC_VER_14] = NULL,
5410                 [RTL_GIGA_MAC_VER_15] = NULL,
5411                 [RTL_GIGA_MAC_VER_16] = NULL,
5412                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5413                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5414                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5415                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5416                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5417                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5418                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5419                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5420                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5421                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5422                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5423                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5424                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5425                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5426                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5427                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5428                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5429                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5430                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5431                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5432                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5433                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5434                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5435                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5436                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5437                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5438                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5439                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5440                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5441                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5442                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5443                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5444                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5445                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5446                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5447         };
5448
5449         if (hw_configs[tp->mac_version])
5450                 hw_configs[tp->mac_version](tp);
5451 }
5452
5453 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5454 {
5455         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5456
5457         /* Workaround for RxFIFO overflow. */
5458         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5459                 tp->irq_mask |= RxFIFOOver;
5460                 tp->irq_mask &= ~RxOverflow;
5461         }
5462
5463         rtl_hw_config(tp);
5464 }
5465
5466 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5467 {
5468         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5469                 tp->irq_mask &= ~RxFIFOOver;
5470
5471         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5472             tp->mac_version == RTL_GIGA_MAC_VER_16)
5473                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5474                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5475
5476         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5477
5478         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5479         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5480
5481         rtl_hw_config(tp);
5482 }
5483
5484 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5485 {
5486         struct rtl8169_private *tp = netdev_priv(dev);
5487
5488         if (new_mtu > ETH_DATA_LEN)
5489                 rtl_hw_jumbo_enable(tp);
5490         else
5491                 rtl_hw_jumbo_disable(tp);
5492
5493         dev->mtu = new_mtu;
5494         netdev_update_features(dev);
5495
5496         return 0;
5497 }
5498
5499 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5500 {
5501         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5502         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5503 }
5504
5505 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5506                                      void **data_buff, struct RxDesc *desc)
5507 {
5508         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5509                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5510
5511         kfree(*data_buff);
5512         *data_buff = NULL;
5513         rtl8169_make_unusable_by_asic(desc);
5514 }
5515
5516 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5517 {
5518         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5519
5520         /* Force memory writes to complete before releasing descriptor */
5521         dma_wmb();
5522
5523         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5524 }
5525
5526 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5527                                              struct RxDesc *desc)
5528 {
5529         void *data;
5530         dma_addr_t mapping;
5531         struct device *d = tp_to_dev(tp);
5532         int node = dev_to_node(d);
5533
5534         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5535         if (!data)
5536                 return NULL;
5537
5538         /* Memory should be properly aligned, but better check. */
5539         if (!IS_ALIGNED((unsigned long)data, 8)) {
5540                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5541                 goto err_out;
5542         }
5543
5544         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5545         if (unlikely(dma_mapping_error(d, mapping))) {
5546                 if (net_ratelimit())
5547                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5548                 goto err_out;
5549         }
5550
5551         desc->addr = cpu_to_le64(mapping);
5552         rtl8169_mark_to_asic(desc);
5553         return data;
5554
5555 err_out:
5556         kfree(data);
5557         return NULL;
5558 }
5559
5560 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5561 {
5562         unsigned int i;
5563
5564         for (i = 0; i < NUM_RX_DESC; i++) {
5565                 if (tp->Rx_databuff[i]) {
5566                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5567                                             tp->RxDescArray + i);
5568                 }
5569         }
5570 }
5571
5572 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5573 {
5574         desc->opts1 |= cpu_to_le32(RingEnd);
5575 }
5576
5577 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5578 {
5579         unsigned int i;
5580
5581         for (i = 0; i < NUM_RX_DESC; i++) {
5582                 void *data;
5583
5584                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5585                 if (!data) {
5586                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5587                         goto err_out;
5588                 }
5589                 tp->Rx_databuff[i] = data;
5590         }
5591
5592         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5593         return 0;
5594
5595 err_out:
5596         rtl8169_rx_clear(tp);
5597         return -ENOMEM;
5598 }
5599
5600 static int rtl8169_init_ring(struct rtl8169_private *tp)
5601 {
5602         rtl8169_init_ring_indexes(tp);
5603
5604         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5605         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5606
5607         return rtl8169_rx_fill(tp);
5608 }
5609
5610 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5611                                  struct TxDesc *desc)
5612 {
5613         unsigned int len = tx_skb->len;
5614
5615         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5616
5617         desc->opts1 = 0x00;
5618         desc->opts2 = 0x00;
5619         desc->addr = 0x00;
5620         tx_skb->len = 0;
5621 }
5622
5623 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5624                                    unsigned int n)
5625 {
5626         unsigned int i;
5627
5628         for (i = 0; i < n; i++) {
5629                 unsigned int entry = (start + i) % NUM_TX_DESC;
5630                 struct ring_info *tx_skb = tp->tx_skb + entry;
5631                 unsigned int len = tx_skb->len;
5632
5633                 if (len) {
5634                         struct sk_buff *skb = tx_skb->skb;
5635
5636                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5637                                              tp->TxDescArray + entry);
5638                         if (skb) {
5639                                 dev_consume_skb_any(skb);
5640                                 tx_skb->skb = NULL;
5641                         }
5642                 }
5643         }
5644 }
5645
5646 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5647 {
5648         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5649         tp->cur_tx = tp->dirty_tx = 0;
5650         netdev_reset_queue(tp->dev);
5651 }
5652
5653 static void rtl_reset_work(struct rtl8169_private *tp)
5654 {
5655         struct net_device *dev = tp->dev;
5656         int i;
5657
5658         napi_disable(&tp->napi);
5659         netif_stop_queue(dev);
5660         synchronize_rcu();
5661
5662         rtl8169_hw_reset(tp);
5663
5664         for (i = 0; i < NUM_RX_DESC; i++)
5665                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5666
5667         rtl8169_tx_clear(tp);
5668         rtl8169_init_ring_indexes(tp);
5669
5670         napi_enable(&tp->napi);
5671         rtl_hw_start(tp);
5672         netif_wake_queue(dev);
5673 }
5674
5675 static void rtl8169_tx_timeout(struct net_device *dev)
5676 {
5677         struct rtl8169_private *tp = netdev_priv(dev);
5678
5679         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5680 }
5681
5682 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5683 {
5684         u32 status = opts0 | len;
5685
5686         if (entry == NUM_TX_DESC - 1)
5687                 status |= RingEnd;
5688
5689         return cpu_to_le32(status);
5690 }
5691
5692 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5693                               u32 *opts)
5694 {
5695         struct skb_shared_info *info = skb_shinfo(skb);
5696         unsigned int cur_frag, entry;
5697         struct TxDesc *uninitialized_var(txd);
5698         struct device *d = tp_to_dev(tp);
5699
5700         entry = tp->cur_tx;
5701         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5702                 const skb_frag_t *frag = info->frags + cur_frag;
5703                 dma_addr_t mapping;
5704                 u32 len;
5705                 void *addr;
5706
5707                 entry = (entry + 1) % NUM_TX_DESC;
5708
5709                 txd = tp->TxDescArray + entry;
5710                 len = skb_frag_size(frag);
5711                 addr = skb_frag_address(frag);
5712                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5713                 if (unlikely(dma_mapping_error(d, mapping))) {
5714                         if (net_ratelimit())
5715                                 netif_err(tp, drv, tp->dev,
5716                                           "Failed to map TX fragments DMA!\n");
5717                         goto err_out;
5718                 }
5719
5720                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5721                 txd->opts2 = cpu_to_le32(opts[1]);
5722                 txd->addr = cpu_to_le64(mapping);
5723
5724                 tp->tx_skb[entry].len = len;
5725         }
5726
5727         if (cur_frag) {
5728                 tp->tx_skb[entry].skb = skb;
5729                 txd->opts1 |= cpu_to_le32(LastFrag);
5730         }
5731
5732         return cur_frag;
5733
5734 err_out:
5735         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5736         return -EIO;
5737 }
5738
5739 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5740 {
5741         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5742 }
5743
5744 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5745                                       struct net_device *dev);
5746 /* r8169_csum_workaround()
5747  * The hw limites the value the transport offset. When the offset is out of the
5748  * range, calculate the checksum by sw.
5749  */
5750 static void r8169_csum_workaround(struct rtl8169_private *tp,
5751                                   struct sk_buff *skb)
5752 {
5753         if (skb_is_gso(skb)) {
5754                 netdev_features_t features = tp->dev->features;
5755                 struct sk_buff *segs, *nskb;
5756
5757                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5758                 segs = skb_gso_segment(skb, features);
5759                 if (IS_ERR(segs) || !segs)
5760                         goto drop;
5761
5762                 do {
5763                         nskb = segs;
5764                         segs = segs->next;
5765                         nskb->next = NULL;
5766                         rtl8169_start_xmit(nskb, tp->dev);
5767                 } while (segs);
5768
5769                 dev_consume_skb_any(skb);
5770         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5771                 if (skb_checksum_help(skb) < 0)
5772                         goto drop;
5773
5774                 rtl8169_start_xmit(skb, tp->dev);
5775         } else {
5776 drop:
5777                 tp->dev->stats.tx_dropped++;
5778                 dev_kfree_skb_any(skb);
5779         }
5780 }
5781
5782 /* msdn_giant_send_check()
5783  * According to the document of microsoft, the TCP Pseudo Header excludes the
5784  * packet length for IPv6 TCP large packets.
5785  */
5786 static int msdn_giant_send_check(struct sk_buff *skb)
5787 {
5788         const struct ipv6hdr *ipv6h;
5789         struct tcphdr *th;
5790         int ret;
5791
5792         ret = skb_cow_head(skb, 0);
5793         if (ret)
5794                 return ret;
5795
5796         ipv6h = ipv6_hdr(skb);
5797         th = tcp_hdr(skb);
5798
5799         th->check = 0;
5800         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5801
5802         return ret;
5803 }
5804
5805 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5806                                 struct sk_buff *skb, u32 *opts)
5807 {
5808         u32 mss = skb_shinfo(skb)->gso_size;
5809
5810         if (mss) {
5811                 opts[0] |= TD_LSO;
5812                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5813         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5814                 const struct iphdr *ip = ip_hdr(skb);
5815
5816                 if (ip->protocol == IPPROTO_TCP)
5817                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5818                 else if (ip->protocol == IPPROTO_UDP)
5819                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5820                 else
5821                         WARN_ON_ONCE(1);
5822         }
5823
5824         return true;
5825 }
5826
5827 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5828                                 struct sk_buff *skb, u32 *opts)
5829 {
5830         u32 transport_offset = (u32)skb_transport_offset(skb);
5831         u32 mss = skb_shinfo(skb)->gso_size;
5832
5833         if (mss) {
5834                 if (transport_offset > GTTCPHO_MAX) {
5835                         netif_warn(tp, tx_err, tp->dev,
5836                                    "Invalid transport offset 0x%x for TSO\n",
5837                                    transport_offset);
5838                         return false;
5839                 }
5840
5841                 switch (vlan_get_protocol(skb)) {
5842                 case htons(ETH_P_IP):
5843                         opts[0] |= TD1_GTSENV4;
5844                         break;
5845
5846                 case htons(ETH_P_IPV6):
5847                         if (msdn_giant_send_check(skb))
5848                                 return false;
5849
5850                         opts[0] |= TD1_GTSENV6;
5851                         break;
5852
5853                 default:
5854                         WARN_ON_ONCE(1);
5855                         break;
5856                 }
5857
5858                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5859                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5860         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5861                 u8 ip_protocol;
5862
5863                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5864                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5865
5866                 if (transport_offset > TCPHO_MAX) {
5867                         netif_warn(tp, tx_err, tp->dev,
5868                                    "Invalid transport offset 0x%x\n",
5869                                    transport_offset);
5870                         return false;
5871                 }
5872
5873                 switch (vlan_get_protocol(skb)) {
5874                 case htons(ETH_P_IP):
5875                         opts[1] |= TD1_IPv4_CS;
5876                         ip_protocol = ip_hdr(skb)->protocol;
5877                         break;
5878
5879                 case htons(ETH_P_IPV6):
5880                         opts[1] |= TD1_IPv6_CS;
5881                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5882                         break;
5883
5884                 default:
5885                         ip_protocol = IPPROTO_RAW;
5886                         break;
5887                 }
5888
5889                 if (ip_protocol == IPPROTO_TCP)
5890                         opts[1] |= TD1_TCP_CS;
5891                 else if (ip_protocol == IPPROTO_UDP)
5892                         opts[1] |= TD1_UDP_CS;
5893                 else
5894                         WARN_ON_ONCE(1);
5895
5896                 opts[1] |= transport_offset << TCPHO_SHIFT;
5897         } else {
5898                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5899                         return !eth_skb_pad(skb);
5900         }
5901
5902         return true;
5903 }
5904
5905 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5906                                unsigned int nr_frags)
5907 {
5908         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5909
5910         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5911         return slots_avail > nr_frags;
5912 }
5913
5914 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5915                                       struct net_device *dev)
5916 {
5917         struct rtl8169_private *tp = netdev_priv(dev);
5918         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5919         struct TxDesc *txd = tp->TxDescArray + entry;
5920         struct device *d = tp_to_dev(tp);
5921         dma_addr_t mapping;
5922         u32 opts[2], len;
5923         int frags;
5924
5925         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5926                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5927                 goto err_stop_0;
5928         }
5929
5930         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5931                 goto err_stop_0;
5932
5933         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5934         opts[0] = DescOwn;
5935
5936         if (!tp->tso_csum(tp, skb, opts)) {
5937                 r8169_csum_workaround(tp, skb);
5938                 return NETDEV_TX_OK;
5939         }
5940
5941         len = skb_headlen(skb);
5942         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5943         if (unlikely(dma_mapping_error(d, mapping))) {
5944                 if (net_ratelimit())
5945                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5946                 goto err_dma_0;
5947         }
5948
5949         tp->tx_skb[entry].len = len;
5950         txd->addr = cpu_to_le64(mapping);
5951
5952         frags = rtl8169_xmit_frags(tp, skb, opts);
5953         if (frags < 0)
5954                 goto err_dma_1;
5955         else if (frags)
5956                 opts[0] |= FirstFrag;
5957         else {
5958                 opts[0] |= FirstFrag | LastFrag;
5959                 tp->tx_skb[entry].skb = skb;
5960         }
5961
5962         txd->opts2 = cpu_to_le32(opts[1]);
5963
5964         netdev_sent_queue(dev, skb->len);
5965
5966         skb_tx_timestamp(skb);
5967
5968         /* Force memory writes to complete before releasing descriptor */
5969         dma_wmb();
5970
5971         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5972
5973         /* Force all memory writes to complete before notifying device */
5974         wmb();
5975
5976         tp->cur_tx += frags + 1;
5977
5978         RTL_W8(tp, TxPoll, NPQ);
5979
5980         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5981                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5982                  * not miss a ring update when it notices a stopped queue.
5983                  */
5984                 smp_wmb();
5985                 netif_stop_queue(dev);
5986                 /* Sync with rtl_tx:
5987                  * - publish queue status and cur_tx ring index (write barrier)
5988                  * - refresh dirty_tx ring index (read barrier).
5989                  * May the current thread have a pessimistic view of the ring
5990                  * status and forget to wake up queue, a racing rtl_tx thread
5991                  * can't.
5992                  */
5993                 smp_mb();
5994                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5995                         netif_start_queue(dev);
5996         }
5997
5998         return NETDEV_TX_OK;
5999
6000 err_dma_1:
6001         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6002 err_dma_0:
6003         dev_kfree_skb_any(skb);
6004         dev->stats.tx_dropped++;
6005         return NETDEV_TX_OK;
6006
6007 err_stop_0:
6008         netif_stop_queue(dev);
6009         dev->stats.tx_dropped++;
6010         return NETDEV_TX_BUSY;
6011 }
6012
6013 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6014 {
6015         struct rtl8169_private *tp = netdev_priv(dev);
6016         struct pci_dev *pdev = tp->pci_dev;
6017         u16 pci_status, pci_cmd;
6018
6019         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6020         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6021
6022         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6023                   pci_cmd, pci_status);
6024
6025         /*
6026          * The recovery sequence below admits a very elaborated explanation:
6027          * - it seems to work;
6028          * - I did not see what else could be done;
6029          * - it makes iop3xx happy.
6030          *
6031          * Feel free to adjust to your needs.
6032          */
6033         if (pdev->broken_parity_status)
6034                 pci_cmd &= ~PCI_COMMAND_PARITY;
6035         else
6036                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6037
6038         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6039
6040         pci_write_config_word(pdev, PCI_STATUS,
6041                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6042                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6043                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6044
6045         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6046 }
6047
6048 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6049                    int budget)
6050 {
6051         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6052
6053         dirty_tx = tp->dirty_tx;
6054         smp_rmb();
6055         tx_left = tp->cur_tx - dirty_tx;
6056
6057         while (tx_left > 0) {
6058                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6059                 struct ring_info *tx_skb = tp->tx_skb + entry;
6060                 u32 status;
6061
6062                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6063                 if (status & DescOwn)
6064                         break;
6065
6066                 /* This barrier is needed to keep us from reading
6067                  * any other fields out of the Tx descriptor until
6068                  * we know the status of DescOwn
6069                  */
6070                 dma_rmb();
6071
6072                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6073                                      tp->TxDescArray + entry);
6074                 if (status & LastFrag) {
6075                         pkts_compl++;
6076                         bytes_compl += tx_skb->skb->len;
6077                         napi_consume_skb(tx_skb->skb, budget);
6078                         tx_skb->skb = NULL;
6079                 }
6080                 dirty_tx++;
6081                 tx_left--;
6082         }
6083
6084         if (tp->dirty_tx != dirty_tx) {
6085                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6086
6087                 u64_stats_update_begin(&tp->tx_stats.syncp);
6088                 tp->tx_stats.packets += pkts_compl;
6089                 tp->tx_stats.bytes += bytes_compl;
6090                 u64_stats_update_end(&tp->tx_stats.syncp);
6091
6092                 tp->dirty_tx = dirty_tx;
6093                 /* Sync with rtl8169_start_xmit:
6094                  * - publish dirty_tx ring index (write barrier)
6095                  * - refresh cur_tx ring index and queue status (read barrier)
6096                  * May the current thread miss the stopped queue condition,
6097                  * a racing xmit thread can only have a right view of the
6098                  * ring status.
6099                  */
6100                 smp_mb();
6101                 if (netif_queue_stopped(dev) &&
6102                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6103                         netif_wake_queue(dev);
6104                 }
6105                 /*
6106                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6107                  * too close. Let's kick an extra TxPoll request when a burst
6108                  * of start_xmit activity is detected (if it is not detected,
6109                  * it is slow enough). -- FR
6110                  */
6111                 if (tp->cur_tx != dirty_tx)
6112                         RTL_W8(tp, TxPoll, NPQ);
6113         }
6114 }
6115
6116 static inline int rtl8169_fragmented_frame(u32 status)
6117 {
6118         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6119 }
6120
6121 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6122 {
6123         u32 status = opts1 & RxProtoMask;
6124
6125         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6126             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6127                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6128         else
6129                 skb_checksum_none_assert(skb);
6130 }
6131
6132 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6133                                            struct rtl8169_private *tp,
6134                                            int pkt_size,
6135                                            dma_addr_t addr)
6136 {
6137         struct sk_buff *skb;
6138         struct device *d = tp_to_dev(tp);
6139
6140         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6141         prefetch(data);
6142         skb = napi_alloc_skb(&tp->napi, pkt_size);
6143         if (skb)
6144                 skb_copy_to_linear_data(skb, data, pkt_size);
6145         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6146
6147         return skb;
6148 }
6149
6150 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6151 {
6152         unsigned int cur_rx, rx_left;
6153         unsigned int count;
6154
6155         cur_rx = tp->cur_rx;
6156
6157         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6158                 unsigned int entry = cur_rx % NUM_RX_DESC;
6159                 struct RxDesc *desc = tp->RxDescArray + entry;
6160                 u32 status;
6161
6162                 status = le32_to_cpu(desc->opts1);
6163                 if (status & DescOwn)
6164                         break;
6165
6166                 /* This barrier is needed to keep us from reading
6167                  * any other fields out of the Rx descriptor until
6168                  * we know the status of DescOwn
6169                  */
6170                 dma_rmb();
6171
6172                 if (unlikely(status & RxRES)) {
6173                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6174                                    status);
6175                         dev->stats.rx_errors++;
6176                         if (status & (RxRWT | RxRUNT))
6177                                 dev->stats.rx_length_errors++;
6178                         if (status & RxCRC)
6179                                 dev->stats.rx_crc_errors++;
6180                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6181                             dev->features & NETIF_F_RXALL) {
6182                                 goto process_pkt;
6183                         }
6184                 } else {
6185                         struct sk_buff *skb;
6186                         dma_addr_t addr;
6187                         int pkt_size;
6188
6189 process_pkt:
6190                         addr = le64_to_cpu(desc->addr);
6191                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6192                                 pkt_size = (status & 0x00003fff) - 4;
6193                         else
6194                                 pkt_size = status & 0x00003fff;
6195
6196                         /*
6197                          * The driver does not support incoming fragmented
6198                          * frames. They are seen as a symptom of over-mtu
6199                          * sized frames.
6200                          */
6201                         if (unlikely(rtl8169_fragmented_frame(status))) {
6202                                 dev->stats.rx_dropped++;
6203                                 dev->stats.rx_length_errors++;
6204                                 goto release_descriptor;
6205                         }
6206
6207                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6208                                                   tp, pkt_size, addr);
6209                         if (!skb) {
6210                                 dev->stats.rx_dropped++;
6211                                 goto release_descriptor;
6212                         }
6213
6214                         rtl8169_rx_csum(skb, status);
6215                         skb_put(skb, pkt_size);
6216                         skb->protocol = eth_type_trans(skb, dev);
6217
6218                         rtl8169_rx_vlan_tag(desc, skb);
6219
6220                         if (skb->pkt_type == PACKET_MULTICAST)
6221                                 dev->stats.multicast++;
6222
6223                         napi_gro_receive(&tp->napi, skb);
6224
6225                         u64_stats_update_begin(&tp->rx_stats.syncp);
6226                         tp->rx_stats.packets++;
6227                         tp->rx_stats.bytes += pkt_size;
6228                         u64_stats_update_end(&tp->rx_stats.syncp);
6229                 }
6230 release_descriptor:
6231                 desc->opts2 = 0;
6232                 rtl8169_mark_to_asic(desc);
6233         }
6234
6235         count = cur_rx - tp->cur_rx;
6236         tp->cur_rx = cur_rx;
6237
6238         return count;
6239 }
6240
6241 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6242 {
6243         struct rtl8169_private *tp = dev_instance;
6244         u16 status = RTL_R16(tp, IntrStatus);
6245
6246         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6247                 return IRQ_NONE;
6248
6249         if (unlikely(status & SYSErr)) {
6250                 rtl8169_pcierr_interrupt(tp->dev);
6251                 goto out;
6252         }
6253
6254         if (status & LinkChg)
6255                 phy_mac_interrupt(tp->phydev);
6256
6257         if (unlikely(status & RxFIFOOver &&
6258             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6259                 netif_stop_queue(tp->dev);
6260                 /* XXX - Hack alert. See rtl_task(). */
6261                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6262         }
6263
6264         rtl_irq_disable(tp);
6265         napi_schedule_irqoff(&tp->napi);
6266 out:
6267         rtl_ack_events(tp, status);
6268
6269         return IRQ_HANDLED;
6270 }
6271
6272 static void rtl_task(struct work_struct *work)
6273 {
6274         static const struct {
6275                 int bitnr;
6276                 void (*action)(struct rtl8169_private *);
6277         } rtl_work[] = {
6278                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6279         };
6280         struct rtl8169_private *tp =
6281                 container_of(work, struct rtl8169_private, wk.work);
6282         struct net_device *dev = tp->dev;
6283         int i;
6284
6285         rtl_lock_work(tp);
6286
6287         if (!netif_running(dev) ||
6288             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6289                 goto out_unlock;
6290
6291         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6292                 bool pending;
6293
6294                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6295                 if (pending)
6296                         rtl_work[i].action(tp);
6297         }
6298
6299 out_unlock:
6300         rtl_unlock_work(tp);
6301 }
6302
6303 static int rtl8169_poll(struct napi_struct *napi, int budget)
6304 {
6305         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6306         struct net_device *dev = tp->dev;
6307         int work_done;
6308
6309         work_done = rtl_rx(dev, tp, (u32) budget);
6310
6311         rtl_tx(dev, tp, budget);
6312
6313         if (work_done < budget) {
6314                 napi_complete_done(napi, work_done);
6315                 rtl_irq_enable(tp);
6316         }
6317
6318         return work_done;
6319 }
6320
6321 static void rtl8169_rx_missed(struct net_device *dev)
6322 {
6323         struct rtl8169_private *tp = netdev_priv(dev);
6324
6325         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6326                 return;
6327
6328         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6329         RTL_W32(tp, RxMissed, 0);
6330 }
6331
6332 static void r8169_phylink_handler(struct net_device *ndev)
6333 {
6334         struct rtl8169_private *tp = netdev_priv(ndev);
6335
6336         if (netif_carrier_ok(ndev)) {
6337                 rtl_link_chg_patch(tp);
6338                 pm_request_resume(&tp->pci_dev->dev);
6339         } else {
6340                 pm_runtime_idle(&tp->pci_dev->dev);
6341         }
6342
6343         if (net_ratelimit())
6344                 phy_print_status(tp->phydev);
6345 }
6346
6347 static int r8169_phy_connect(struct rtl8169_private *tp)
6348 {
6349         struct phy_device *phydev = tp->phydev;
6350         phy_interface_t phy_mode;
6351         int ret;
6352
6353         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6354                    PHY_INTERFACE_MODE_MII;
6355
6356         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6357                                  phy_mode);
6358         if (ret)
6359                 return ret;
6360
6361         if (tp->supports_gmii)
6362                 phy_remove_link_mode(phydev,
6363                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6364         else
6365                 phy_set_max_speed(phydev, SPEED_100);
6366
6367         phy_support_asym_pause(phydev);
6368
6369         phy_attached_info(phydev);
6370
6371         return 0;
6372 }
6373
6374 static void rtl8169_down(struct net_device *dev)
6375 {
6376         struct rtl8169_private *tp = netdev_priv(dev);
6377
6378         phy_stop(tp->phydev);
6379
6380         napi_disable(&tp->napi);
6381         netif_stop_queue(dev);
6382
6383         rtl8169_hw_reset(tp);
6384         /*
6385          * At this point device interrupts can not be enabled in any function,
6386          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6387          * and napi is disabled (rtl8169_poll).
6388          */
6389         rtl8169_rx_missed(dev);
6390
6391         /* Give a racing hard_start_xmit a few cycles to complete. */
6392         synchronize_rcu();
6393
6394         rtl8169_tx_clear(tp);
6395
6396         rtl8169_rx_clear(tp);
6397
6398         rtl_pll_power_down(tp);
6399 }
6400
6401 static int rtl8169_close(struct net_device *dev)
6402 {
6403         struct rtl8169_private *tp = netdev_priv(dev);
6404         struct pci_dev *pdev = tp->pci_dev;
6405
6406         pm_runtime_get_sync(&pdev->dev);
6407
6408         /* Update counters before going down */
6409         rtl8169_update_counters(tp);
6410
6411         rtl_lock_work(tp);
6412         /* Clear all task flags */
6413         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6414
6415         rtl8169_down(dev);
6416         rtl_unlock_work(tp);
6417
6418         cancel_work_sync(&tp->wk.work);
6419
6420         phy_disconnect(tp->phydev);
6421
6422         pci_free_irq(pdev, 0, tp);
6423
6424         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6425                           tp->RxPhyAddr);
6426         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6427                           tp->TxPhyAddr);
6428         tp->TxDescArray = NULL;
6429         tp->RxDescArray = NULL;
6430
6431         pm_runtime_put_sync(&pdev->dev);
6432
6433         return 0;
6434 }
6435
6436 #ifdef CONFIG_NET_POLL_CONTROLLER
6437 static void rtl8169_netpoll(struct net_device *dev)
6438 {
6439         struct rtl8169_private *tp = netdev_priv(dev);
6440
6441         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6442 }
6443 #endif
6444
6445 static int rtl_open(struct net_device *dev)
6446 {
6447         struct rtl8169_private *tp = netdev_priv(dev);
6448         struct pci_dev *pdev = tp->pci_dev;
6449         int retval = -ENOMEM;
6450
6451         pm_runtime_get_sync(&pdev->dev);
6452
6453         /*
6454          * Rx and Tx descriptors needs 256 bytes alignment.
6455          * dma_alloc_coherent provides more.
6456          */
6457         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6458                                              &tp->TxPhyAddr, GFP_KERNEL);
6459         if (!tp->TxDescArray)
6460                 goto err_pm_runtime_put;
6461
6462         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6463                                              &tp->RxPhyAddr, GFP_KERNEL);
6464         if (!tp->RxDescArray)
6465                 goto err_free_tx_0;
6466
6467         retval = rtl8169_init_ring(tp);
6468         if (retval < 0)
6469                 goto err_free_rx_1;
6470
6471         rtl_request_firmware(tp);
6472
6473         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6474                                  dev->name);
6475         if (retval < 0)
6476                 goto err_release_fw_2;
6477
6478         retval = r8169_phy_connect(tp);
6479         if (retval)
6480                 goto err_free_irq;
6481
6482         rtl_lock_work(tp);
6483
6484         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6485
6486         napi_enable(&tp->napi);
6487
6488         rtl8169_init_phy(dev, tp);
6489
6490         rtl_pll_power_up(tp);
6491
6492         rtl_hw_start(tp);
6493
6494         if (!rtl8169_init_counter_offsets(tp))
6495                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6496
6497         phy_start(tp->phydev);
6498         netif_start_queue(dev);
6499
6500         rtl_unlock_work(tp);
6501
6502         pm_runtime_put_sync(&pdev->dev);
6503 out:
6504         return retval;
6505
6506 err_free_irq:
6507         pci_free_irq(pdev, 0, tp);
6508 err_release_fw_2:
6509         rtl_release_firmware(tp);
6510         rtl8169_rx_clear(tp);
6511 err_free_rx_1:
6512         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6513                           tp->RxPhyAddr);
6514         tp->RxDescArray = NULL;
6515 err_free_tx_0:
6516         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6517                           tp->TxPhyAddr);
6518         tp->TxDescArray = NULL;
6519 err_pm_runtime_put:
6520         pm_runtime_put_noidle(&pdev->dev);
6521         goto out;
6522 }
6523
6524 static void
6525 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6526 {
6527         struct rtl8169_private *tp = netdev_priv(dev);
6528         struct pci_dev *pdev = tp->pci_dev;
6529         struct rtl8169_counters *counters = tp->counters;
6530         unsigned int start;
6531
6532         pm_runtime_get_noresume(&pdev->dev);
6533
6534         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6535                 rtl8169_rx_missed(dev);
6536
6537         do {
6538                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6539                 stats->rx_packets = tp->rx_stats.packets;
6540                 stats->rx_bytes = tp->rx_stats.bytes;
6541         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6542
6543         do {
6544                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6545                 stats->tx_packets = tp->tx_stats.packets;
6546                 stats->tx_bytes = tp->tx_stats.bytes;
6547         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6548
6549         stats->rx_dropped       = dev->stats.rx_dropped;
6550         stats->tx_dropped       = dev->stats.tx_dropped;
6551         stats->rx_length_errors = dev->stats.rx_length_errors;
6552         stats->rx_errors        = dev->stats.rx_errors;
6553         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6554         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6555         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6556         stats->multicast        = dev->stats.multicast;
6557
6558         /*
6559          * Fetch additonal counter values missing in stats collected by driver
6560          * from tally counters.
6561          */
6562         if (pm_runtime_active(&pdev->dev))
6563                 rtl8169_update_counters(tp);
6564
6565         /*
6566          * Subtract values fetched during initalization.
6567          * See rtl8169_init_counter_offsets for a description why we do that.
6568          */
6569         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6570                 le64_to_cpu(tp->tc_offset.tx_errors);
6571         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6572                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6573         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6574                 le16_to_cpu(tp->tc_offset.tx_aborted);
6575
6576         pm_runtime_put_noidle(&pdev->dev);
6577 }
6578
6579 static void rtl8169_net_suspend(struct net_device *dev)
6580 {
6581         struct rtl8169_private *tp = netdev_priv(dev);
6582
6583         if (!netif_running(dev))
6584                 return;
6585
6586         phy_stop(tp->phydev);
6587         netif_device_detach(dev);
6588
6589         rtl_lock_work(tp);
6590         napi_disable(&tp->napi);
6591         /* Clear all task flags */
6592         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6593
6594         rtl_unlock_work(tp);
6595
6596         rtl_pll_power_down(tp);
6597 }
6598
6599 #ifdef CONFIG_PM
6600
6601 static int rtl8169_suspend(struct device *device)
6602 {
6603         struct net_device *dev = dev_get_drvdata(device);
6604         struct rtl8169_private *tp = netdev_priv(dev);
6605
6606         rtl8169_net_suspend(dev);
6607         clk_disable_unprepare(tp->clk);
6608
6609         return 0;
6610 }
6611
6612 static void __rtl8169_resume(struct net_device *dev)
6613 {
6614         struct rtl8169_private *tp = netdev_priv(dev);
6615
6616         netif_device_attach(dev);
6617
6618         rtl_pll_power_up(tp);
6619         rtl8169_init_phy(dev, tp);
6620
6621         phy_start(tp->phydev);
6622
6623         rtl_lock_work(tp);
6624         napi_enable(&tp->napi);
6625         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6626         rtl_reset_work(tp);
6627         rtl_unlock_work(tp);
6628 }
6629
6630 static int rtl8169_resume(struct device *device)
6631 {
6632         struct net_device *dev = dev_get_drvdata(device);
6633         struct rtl8169_private *tp = netdev_priv(dev);
6634
6635         rtl_rar_set(tp, dev->dev_addr);
6636
6637         clk_prepare_enable(tp->clk);
6638
6639         if (netif_running(dev))
6640                 __rtl8169_resume(dev);
6641
6642         return 0;
6643 }
6644
6645 static int rtl8169_runtime_suspend(struct device *device)
6646 {
6647         struct net_device *dev = dev_get_drvdata(device);
6648         struct rtl8169_private *tp = netdev_priv(dev);
6649
6650         if (!tp->TxDescArray)
6651                 return 0;
6652
6653         rtl_lock_work(tp);
6654         __rtl8169_set_wol(tp, WAKE_ANY);
6655         rtl_unlock_work(tp);
6656
6657         rtl8169_net_suspend(dev);
6658
6659         /* Update counters before going runtime suspend */
6660         rtl8169_rx_missed(dev);
6661         rtl8169_update_counters(tp);
6662
6663         return 0;
6664 }
6665
6666 static int rtl8169_runtime_resume(struct device *device)
6667 {
6668         struct net_device *dev = dev_get_drvdata(device);
6669         struct rtl8169_private *tp = netdev_priv(dev);
6670
6671         rtl_rar_set(tp, dev->dev_addr);
6672
6673         if (!tp->TxDescArray)
6674                 return 0;
6675
6676         rtl_lock_work(tp);
6677         __rtl8169_set_wol(tp, tp->saved_wolopts);
6678         rtl_unlock_work(tp);
6679
6680         __rtl8169_resume(dev);
6681
6682         return 0;
6683 }
6684
6685 static int rtl8169_runtime_idle(struct device *device)
6686 {
6687         struct net_device *dev = dev_get_drvdata(device);
6688
6689         if (!netif_running(dev) || !netif_carrier_ok(dev))
6690                 pm_schedule_suspend(device, 10000);
6691
6692         return -EBUSY;
6693 }
6694
6695 static const struct dev_pm_ops rtl8169_pm_ops = {
6696         .suspend                = rtl8169_suspend,
6697         .resume                 = rtl8169_resume,
6698         .freeze                 = rtl8169_suspend,
6699         .thaw                   = rtl8169_resume,
6700         .poweroff               = rtl8169_suspend,
6701         .restore                = rtl8169_resume,
6702         .runtime_suspend        = rtl8169_runtime_suspend,
6703         .runtime_resume         = rtl8169_runtime_resume,
6704         .runtime_idle           = rtl8169_runtime_idle,
6705 };
6706
6707 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6708
6709 #else /* !CONFIG_PM */
6710
6711 #define RTL8169_PM_OPS  NULL
6712
6713 #endif /* !CONFIG_PM */
6714
6715 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6716 {
6717         /* WoL fails with 8168b when the receiver is disabled. */
6718         switch (tp->mac_version) {
6719         case RTL_GIGA_MAC_VER_11:
6720         case RTL_GIGA_MAC_VER_12:
6721         case RTL_GIGA_MAC_VER_17:
6722                 pci_clear_master(tp->pci_dev);
6723
6724                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6725                 /* PCI commit */
6726                 RTL_R8(tp, ChipCmd);
6727                 break;
6728         default:
6729                 break;
6730         }
6731 }
6732
6733 static void rtl_shutdown(struct pci_dev *pdev)
6734 {
6735         struct net_device *dev = pci_get_drvdata(pdev);
6736         struct rtl8169_private *tp = netdev_priv(dev);
6737
6738         rtl8169_net_suspend(dev);
6739
6740         /* Restore original MAC address */
6741         rtl_rar_set(tp, dev->perm_addr);
6742
6743         rtl8169_hw_reset(tp);
6744
6745         if (system_state == SYSTEM_POWER_OFF) {
6746                 if (tp->saved_wolopts) {
6747                         rtl_wol_suspend_quirk(tp);
6748                         rtl_wol_shutdown_quirk(tp);
6749                 }
6750
6751                 pci_wake_from_d3(pdev, true);
6752                 pci_set_power_state(pdev, PCI_D3hot);
6753         }
6754 }
6755
6756 static void rtl_remove_one(struct pci_dev *pdev)
6757 {
6758         struct net_device *dev = pci_get_drvdata(pdev);
6759         struct rtl8169_private *tp = netdev_priv(dev);
6760
6761         if (r8168_check_dash(tp))
6762                 rtl8168_driver_stop(tp);
6763
6764         netif_napi_del(&tp->napi);
6765
6766         unregister_netdev(dev);
6767         mdiobus_unregister(tp->phydev->mdio.bus);
6768
6769         rtl_release_firmware(tp);
6770
6771         if (pci_dev_run_wake(pdev))
6772                 pm_runtime_get_noresume(&pdev->dev);
6773
6774         /* restore original MAC address */
6775         rtl_rar_set(tp, dev->perm_addr);
6776 }
6777
6778 static const struct net_device_ops rtl_netdev_ops = {
6779         .ndo_open               = rtl_open,
6780         .ndo_stop               = rtl8169_close,
6781         .ndo_get_stats64        = rtl8169_get_stats64,
6782         .ndo_start_xmit         = rtl8169_start_xmit,
6783         .ndo_tx_timeout         = rtl8169_tx_timeout,
6784         .ndo_validate_addr      = eth_validate_addr,
6785         .ndo_change_mtu         = rtl8169_change_mtu,
6786         .ndo_fix_features       = rtl8169_fix_features,
6787         .ndo_set_features       = rtl8169_set_features,
6788         .ndo_set_mac_address    = rtl_set_mac_address,
6789         .ndo_do_ioctl           = rtl8169_ioctl,
6790         .ndo_set_rx_mode        = rtl_set_rx_mode,
6791 #ifdef CONFIG_NET_POLL_CONTROLLER
6792         .ndo_poll_controller    = rtl8169_netpoll,
6793 #endif
6794
6795 };
6796
6797 static const struct rtl_cfg_info {
6798         void (*hw_start)(struct rtl8169_private *tp);
6799         u16 irq_mask;
6800         unsigned int has_gmii:1;
6801         const struct rtl_coalesce_info *coalesce_info;
6802 } rtl_cfg_infos [] = {
6803         [RTL_CFG_0] = {
6804                 .hw_start       = rtl_hw_start_8169,
6805                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6806                 .has_gmii       = 1,
6807                 .coalesce_info  = rtl_coalesce_info_8169,
6808         },
6809         [RTL_CFG_1] = {
6810                 .hw_start       = rtl_hw_start_8168,
6811                 .irq_mask       = LinkChg | RxOverflow,
6812                 .has_gmii       = 1,
6813                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6814         },
6815         [RTL_CFG_2] = {
6816                 .hw_start       = rtl_hw_start_8101,
6817                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6818                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6819         }
6820 };
6821
6822 static int rtl_alloc_irq(struct rtl8169_private *tp)
6823 {
6824         unsigned int flags;
6825
6826         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6827                 rtl_unlock_config_regs(tp);
6828                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6829                 rtl_lock_config_regs(tp);
6830                 flags = PCI_IRQ_LEGACY;
6831         } else {
6832                 flags = PCI_IRQ_ALL_TYPES;
6833         }
6834
6835         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6836 }
6837
6838 static void rtl_read_mac_address(struct rtl8169_private *tp,
6839                                  u8 mac_addr[ETH_ALEN])
6840 {
6841         u32 value;
6842
6843         /* Get MAC address */
6844         switch (tp->mac_version) {
6845         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6846         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6847                 value = rtl_eri_read(tp, 0xe0);
6848                 mac_addr[0] = (value >>  0) & 0xff;
6849                 mac_addr[1] = (value >>  8) & 0xff;
6850                 mac_addr[2] = (value >> 16) & 0xff;
6851                 mac_addr[3] = (value >> 24) & 0xff;
6852
6853                 value = rtl_eri_read(tp, 0xe4);
6854                 mac_addr[4] = (value >>  0) & 0xff;
6855                 mac_addr[5] = (value >>  8) & 0xff;
6856                 break;
6857         default:
6858                 break;
6859         }
6860 }
6861
6862 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6863 {
6864         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6865 }
6866
6867 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6868 {
6869         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6870 }
6871
6872 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6873 {
6874         struct rtl8169_private *tp = mii_bus->priv;
6875
6876         if (phyaddr > 0)
6877                 return -ENODEV;
6878
6879         return rtl_readphy(tp, phyreg);
6880 }
6881
6882 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6883                                 int phyreg, u16 val)
6884 {
6885         struct rtl8169_private *tp = mii_bus->priv;
6886
6887         if (phyaddr > 0)
6888                 return -ENODEV;
6889
6890         rtl_writephy(tp, phyreg, val);
6891
6892         return 0;
6893 }
6894
6895 static int r8169_mdio_register(struct rtl8169_private *tp)
6896 {
6897         struct pci_dev *pdev = tp->pci_dev;
6898         struct mii_bus *new_bus;
6899         int ret;
6900
6901         new_bus = devm_mdiobus_alloc(&pdev->dev);
6902         if (!new_bus)
6903                 return -ENOMEM;
6904
6905         new_bus->name = "r8169";
6906         new_bus->priv = tp;
6907         new_bus->parent = &pdev->dev;
6908         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6909         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6910
6911         new_bus->read = r8169_mdio_read_reg;
6912         new_bus->write = r8169_mdio_write_reg;
6913
6914         ret = mdiobus_register(new_bus);
6915         if (ret)
6916                 return ret;
6917
6918         tp->phydev = mdiobus_get_phy(new_bus, 0);
6919         if (!tp->phydev) {
6920                 mdiobus_unregister(new_bus);
6921                 return -ENODEV;
6922         }
6923
6924         /* PHY will be woken up in rtl_open() */
6925         phy_suspend(tp->phydev);
6926
6927         return 0;
6928 }
6929
6930 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6931 {
6932         u32 data;
6933
6934         tp->ocp_base = OCP_STD_PHY_BASE;
6935
6936         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6937
6938         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6939                 return;
6940
6941         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6942                 return;
6943
6944         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6945         msleep(1);
6946         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6947
6948         data = r8168_mac_ocp_read(tp, 0xe8de);
6949         data &= ~(1 << 14);
6950         r8168_mac_ocp_write(tp, 0xe8de, data);
6951
6952         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6953                 return;
6954
6955         data = r8168_mac_ocp_read(tp, 0xe8de);
6956         data |= (1 << 15);
6957         r8168_mac_ocp_write(tp, 0xe8de, data);
6958
6959         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6960 }
6961
6962 static void rtl_hw_initialize(struct rtl8169_private *tp)
6963 {
6964         switch (tp->mac_version) {
6965         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6966                 rtl8168ep_stop_cmac(tp);
6967                 /* fall through */
6968         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6969                 rtl_hw_init_8168g(tp);
6970                 break;
6971         default:
6972                 break;
6973         }
6974 }
6975
6976 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
6977 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
6978 {
6979         switch (tp->mac_version) {
6980         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6981         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
6982                 return false;
6983         default:
6984                 return true;
6985         }
6986 }
6987
6988 static int rtl_jumbo_max(struct rtl8169_private *tp)
6989 {
6990         /* Non-GBit versions don't support jumbo frames */
6991         if (!tp->supports_gmii)
6992                 return JUMBO_1K;
6993
6994         switch (tp->mac_version) {
6995         /* RTL8169 */
6996         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6997                 return JUMBO_7K;
6998         /* RTL8168b */
6999         case RTL_GIGA_MAC_VER_11:
7000         case RTL_GIGA_MAC_VER_12:
7001         case RTL_GIGA_MAC_VER_17:
7002                 return JUMBO_4K;
7003         /* RTL8168c */
7004         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7005                 return JUMBO_6K;
7006         default:
7007                 return JUMBO_9K;
7008         }
7009 }
7010
7011 static void rtl_disable_clk(void *data)
7012 {
7013         clk_disable_unprepare(data);
7014 }
7015
7016 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7017 {
7018         struct device *d = tp_to_dev(tp);
7019         struct clk *clk;
7020         int rc;
7021
7022         clk = devm_clk_get(d, "ether_clk");
7023         if (IS_ERR(clk)) {
7024                 rc = PTR_ERR(clk);
7025                 if (rc == -ENOENT)
7026                         /* clk-core allows NULL (for suspend / resume) */
7027                         rc = 0;
7028                 else if (rc != -EPROBE_DEFER)
7029                         dev_err(d, "failed to get clk: %d\n", rc);
7030         } else {
7031                 tp->clk = clk;
7032                 rc = clk_prepare_enable(clk);
7033                 if (rc)
7034                         dev_err(d, "failed to enable clk: %d\n", rc);
7035                 else
7036                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7037         }
7038
7039         return rc;
7040 }
7041
7042 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7043 {
7044         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7045         /* align to u16 for is_valid_ether_addr() */
7046         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7047         struct rtl8169_private *tp;
7048         struct net_device *dev;
7049         int chipset, region, i;
7050         int jumbo_max, rc;
7051
7052         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7053         if (!dev)
7054                 return -ENOMEM;
7055
7056         SET_NETDEV_DEV(dev, &pdev->dev);
7057         dev->netdev_ops = &rtl_netdev_ops;
7058         tp = netdev_priv(dev);
7059         tp->dev = dev;
7060         tp->pci_dev = pdev;
7061         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7062         tp->supports_gmii = cfg->has_gmii;
7063
7064         /* Get the *optional* external "ether_clk" used on some boards */
7065         rc = rtl_get_ether_clk(tp);
7066         if (rc)
7067                 return rc;
7068
7069         /* Disable ASPM completely as that cause random device stop working
7070          * problems as well as full system hangs for some PCIe devices users.
7071          */
7072         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7073
7074         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7075         rc = pcim_enable_device(pdev);
7076         if (rc < 0) {
7077                 dev_err(&pdev->dev, "enable failure\n");
7078                 return rc;
7079         }
7080
7081         if (pcim_set_mwi(pdev) < 0)
7082                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7083
7084         /* use first MMIO region */
7085         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7086         if (region < 0) {
7087                 dev_err(&pdev->dev, "no MMIO resource found\n");
7088                 return -ENODEV;
7089         }
7090
7091         /* check for weird/broken PCI region reporting */
7092         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7093                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7094                 return -ENODEV;
7095         }
7096
7097         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7098         if (rc < 0) {
7099                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7100                 return rc;
7101         }
7102
7103         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7104
7105         /* Identify chip attached to board */
7106         rtl8169_get_mac_version(tp);
7107         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7108                 return -ENODEV;
7109
7110         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7111
7112         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7113             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7114                 dev->features |= NETIF_F_HIGHDMA;
7115         } else {
7116                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7117                 if (rc < 0) {
7118                         dev_err(&pdev->dev, "DMA configuration failed\n");
7119                         return rc;
7120                 }
7121         }
7122
7123         rtl_init_rxcfg(tp);
7124
7125         rtl8169_irq_mask_and_ack(tp);
7126
7127         rtl_hw_initialize(tp);
7128
7129         rtl_hw_reset(tp);
7130
7131         pci_set_master(pdev);
7132
7133         rtl_init_jumbo_ops(tp);
7134
7135         chipset = tp->mac_version;
7136
7137         rc = rtl_alloc_irq(tp);
7138         if (rc < 0) {
7139                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7140                 return rc;
7141         }
7142
7143         mutex_init(&tp->wk.mutex);
7144         INIT_WORK(&tp->wk.work, rtl_task);
7145         u64_stats_init(&tp->rx_stats.syncp);
7146         u64_stats_init(&tp->tx_stats.syncp);
7147
7148         /* get MAC address */
7149         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7150         if (rc)
7151                 rtl_read_mac_address(tp, mac_addr);
7152
7153         if (is_valid_ether_addr(mac_addr))
7154                 rtl_rar_set(tp, mac_addr);
7155
7156         for (i = 0; i < ETH_ALEN; i++)
7157                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7158
7159         dev->ethtool_ops = &rtl8169_ethtool_ops;
7160
7161         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7162
7163         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7164          * properly for all devices */
7165         dev->features |= NETIF_F_RXCSUM |
7166                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7167
7168         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7169                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7170                 NETIF_F_HW_VLAN_CTAG_RX;
7171         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7172                 NETIF_F_HIGHDMA;
7173         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7174
7175         tp->cp_cmd |= RxChkSum | RxVlan;
7176
7177         /*
7178          * Pretend we are using VLANs; This bypasses a nasty bug where
7179          * Interrupts stop flowing on high load on 8110SCd controllers.
7180          */
7181         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7182                 /* Disallow toggling */
7183                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7184
7185         if (rtl_chip_supports_csum_v2(tp)) {
7186                 tp->tso_csum = rtl8169_tso_csum_v2;
7187                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7188         } else {
7189                 tp->tso_csum = rtl8169_tso_csum_v1;
7190         }
7191
7192         dev->hw_features |= NETIF_F_RXALL;
7193         dev->hw_features |= NETIF_F_RXFCS;
7194
7195         /* MTU range: 60 - hw-specific max */
7196         dev->min_mtu = ETH_ZLEN;
7197         jumbo_max = rtl_jumbo_max(tp);
7198         dev->max_mtu = jumbo_max;
7199
7200         tp->hw_start = cfg->hw_start;
7201         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7202         tp->coalesce_info = cfg->coalesce_info;
7203
7204         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7205
7206         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7207                                             &tp->counters_phys_addr,
7208                                             GFP_KERNEL);
7209         if (!tp->counters)
7210                 return -ENOMEM;
7211
7212         pci_set_drvdata(pdev, dev);
7213
7214         rc = r8169_mdio_register(tp);
7215         if (rc)
7216                 return rc;
7217
7218         /* chip gets powered up in rtl_open() */
7219         rtl_pll_power_down(tp);
7220
7221         rc = register_netdev(dev);
7222         if (rc)
7223                 goto err_mdio_unregister;
7224
7225         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7226                    rtl_chip_infos[chipset].name, dev->dev_addr,
7227                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7228                    pci_irq_vector(pdev, 0));
7229
7230         if (jumbo_max > JUMBO_1K)
7231                 netif_info(tp, probe, dev,
7232                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7233                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7234                            "ok" : "ko");
7235
7236         if (r8168_check_dash(tp))
7237                 rtl8168_driver_start(tp);
7238
7239         if (pci_dev_run_wake(pdev))
7240                 pm_runtime_put_sync(&pdev->dev);
7241
7242         return 0;
7243
7244 err_mdio_unregister:
7245         mdiobus_unregister(tp->phydev->mdio.bus);
7246         return rc;
7247 }
7248
7249 static struct pci_driver rtl8169_pci_driver = {
7250         .name           = MODULENAME,
7251         .id_table       = rtl8169_pci_tbl,
7252         .probe          = rtl_init_one,
7253         .remove         = rtl_remove_one,
7254         .shutdown       = rtl_shutdown,
7255         .driver.pm      = RTL8169_PM_OPS,
7256 };
7257
7258 module_pci_driver(rtl8169_pci_driver);