drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #define MODULENAME "r8169"
  35
  36 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  37 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  38 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  39 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  40 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  41 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  42 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  45 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  46 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  47 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  48 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  49 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  50 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  51 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  52 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  53 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  54 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  55
  56 #define R8169_MSG_DEFAULT \
  57         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  58
  59 #define TX_SLOTS_AVAIL(tp) \
  60         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  61
  62 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  63 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  64         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  65
  66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68 static const int multicast_filter_limit = 32;
  69
  70 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  79
  80 /* write/read MMIO register */
  81 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  84 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  85 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  86 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  87
  88 enum mac_version {
  89         RTL_GIGA_MAC_VER_01 = 0,
  90         RTL_GIGA_MAC_VER_02,
  91         RTL_GIGA_MAC_VER_03,
  92         RTL_GIGA_MAC_VER_04,
  93         RTL_GIGA_MAC_VER_05,
  94         RTL_GIGA_MAC_VER_06,
  95         RTL_GIGA_MAC_VER_07,
  96         RTL_GIGA_MAC_VER_08,
  97         RTL_GIGA_MAC_VER_09,
  98         RTL_GIGA_MAC_VER_10,
  99         RTL_GIGA_MAC_VER_11,
 100         RTL_GIGA_MAC_VER_12,
 101         RTL_GIGA_MAC_VER_13,
 102         RTL_GIGA_MAC_VER_14,
 103         RTL_GIGA_MAC_VER_15,
 104         RTL_GIGA_MAC_VER_16,
 105         RTL_GIGA_MAC_VER_17,
 106         RTL_GIGA_MAC_VER_18,
 107         RTL_GIGA_MAC_VER_19,
 108         RTL_GIGA_MAC_VER_20,
 109         RTL_GIGA_MAC_VER_21,
 110         RTL_GIGA_MAC_VER_22,
 111         RTL_GIGA_MAC_VER_23,
 112         RTL_GIGA_MAC_VER_24,
 113         RTL_GIGA_MAC_VER_25,
 114         RTL_GIGA_MAC_VER_26,
 115         RTL_GIGA_MAC_VER_27,
 116         RTL_GIGA_MAC_VER_28,
 117         RTL_GIGA_MAC_VER_29,
 118         RTL_GIGA_MAC_VER_30,
 119         RTL_GIGA_MAC_VER_31,
 120         RTL_GIGA_MAC_VER_32,
 121         RTL_GIGA_MAC_VER_33,
 122         RTL_GIGA_MAC_VER_34,
 123         RTL_GIGA_MAC_VER_35,
 124         RTL_GIGA_MAC_VER_36,
 125         RTL_GIGA_MAC_VER_37,
 126         RTL_GIGA_MAC_VER_38,
 127         RTL_GIGA_MAC_VER_39,
 128         RTL_GIGA_MAC_VER_40,
 129         RTL_GIGA_MAC_VER_41,
 130         RTL_GIGA_MAC_VER_42,
 131         RTL_GIGA_MAC_VER_43,
 132         RTL_GIGA_MAC_VER_44,
 133         RTL_GIGA_MAC_VER_45,
 134         RTL_GIGA_MAC_VER_46,
 135         RTL_GIGA_MAC_VER_47,
 136         RTL_GIGA_MAC_VER_48,
 137         RTL_GIGA_MAC_VER_49,
 138         RTL_GIGA_MAC_VER_50,
 139         RTL_GIGA_MAC_VER_51,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 #define JUMBO_1K        ETH_DATA_LEN
 144 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149 static const struct {
 150         const char *name;
 151         const char *fw_name;
 152 } rtl_chip_infos[] = {
 153         /* PCI devices. */
 154         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 155         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 156         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 157         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 158         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 159         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 160         /* PCI-E devices. */
 161         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 162         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 163         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 164         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 167         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 168         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 169         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 170         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 171         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 172         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 174         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 175         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 176         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 177         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 178         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 179         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 180         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 181         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 182         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 184         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 185         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 186         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 187         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 188         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 189         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 190         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 191         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 192         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 193         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 194         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 195         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 196         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 197         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 198         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 199         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 200         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 201         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 202         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 203         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 204         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 205         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 206 };
 207
 208 enum cfg_version {
 209         RTL_CFG_0 = 0x00,
 210         RTL_CFG_1,
 211         RTL_CFG_2
 212 };
 213
 214 static const struct pci_device_id rtl8169_pci_tbl[] = {
 215         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 216         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 217         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 218         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 219         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 220         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 221         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 222         { PCI_VENDOR_ID_DLINK,  0x4300,
 223                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 224         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 225         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 226         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 227         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 228         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 229                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 230         { 0x0001,                               0x8168,
 231                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 232         {}
 233 };
 234
 235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 236
 237 static int use_dac = -1;
 238 static struct {
 239         u32 msg_enable;
 240 } debug = { -1 };
 241
 242 enum rtl_registers {
 243         MAC0            = 0,    /* Ethernet hardware address. */
 244         MAC4            = 4,
 245         MAR0            = 8,    /* Multicast filter. */
 246         CounterAddrLow          = 0x10,
 247         CounterAddrHigh         = 0x14,
 248         TxDescStartAddrLow      = 0x20,
 249         TxDescStartAddrHigh     = 0x24,
 250         TxHDescStartAddrLow     = 0x28,
 251         TxHDescStartAddrHigh    = 0x2c,
 252         FLASH           = 0x30,
 253         ERSR            = 0x36,
 254         ChipCmd         = 0x37,
 255         TxPoll          = 0x38,
 256         IntrMask        = 0x3c,
 257         IntrStatus      = 0x3e,
 258
 259         TxConfig        = 0x40,
 260 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 261 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 262
 263         RxConfig        = 0x44,
 264 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 265 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 266 #define RXCFG_FIFO_SHIFT                13
 267                                         /* No threshold before first PCI xfer */
 268 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 269 #define RX_EARLY_OFF                    (1 << 11)
 270 #define RXCFG_DMA_SHIFT                 8
 271                                         /* Unlimited maximum PCI burst. */
 272 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 273
 274         RxMissed        = 0x4c,
 275         Cfg9346         = 0x50,
 276         Config0         = 0x51,
 277         Config1         = 0x52,
 278         Config2         = 0x53,
 279 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 280
 281         Config3         = 0x54,
 282         Config4         = 0x55,
 283         Config5         = 0x56,
 284         MultiIntr       = 0x5c,
 285         PHYAR           = 0x60,
 286         PHYstatus       = 0x6c,
 287         RxMaxSize       = 0xda,
 288         CPlusCmd        = 0xe0,
 289         IntrMitigate    = 0xe2,
 290
 291 #define RTL_COALESCE_MASK       0x0f
 292 #define RTL_COALESCE_SHIFT      4
 293 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 294 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 295
 296         RxDescAddrLow   = 0xe4,
 297         RxDescAddrHigh  = 0xe8,
 298         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 299
 300 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 301
 302         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 303
 304 #define TxPacketMax     (8064 >> 7)
 305 #define EarlySize       0x27
 306
 307         FuncEvent       = 0xf0,
 308         FuncEventMask   = 0xf4,
 309         FuncPresetState = 0xf8,
 310         IBCR0           = 0xf8,
 311         IBCR2           = 0xf9,
 312         IBIMR0          = 0xfa,
 313         IBISR0          = 0xfb,
 314         FuncForceEvent  = 0xfc,
 315 };
 316
 317 enum rtl8168_8101_registers {
 318         CSIDR                   = 0x64,
 319         CSIAR                   = 0x68,
 320 #define CSIAR_FLAG                      0x80000000
 321 #define CSIAR_WRITE_CMD                 0x80000000
 322 #define CSIAR_BYTE_ENABLE               0x0000f000
 323 #define CSIAR_ADDR_MASK                 0x00000fff
 324         PMCH                    = 0x6f,
 325         EPHYAR                  = 0x80,
 326 #define EPHYAR_FLAG                     0x80000000
 327 #define EPHYAR_WRITE_CMD                0x80000000
 328 #define EPHYAR_REG_MASK                 0x1f
 329 #define EPHYAR_REG_SHIFT                16
 330 #define EPHYAR_DATA_MASK                0xffff
 331         DLLPR                   = 0xd0,
 332 #define PFM_EN                          (1 << 6)
 333 #define TX_10M_PS_EN                    (1 << 7)
 334         DBG_REG                 = 0xd1,
 335 #define FIX_NAK_1                       (1 << 4)
 336 #define FIX_NAK_2                       (1 << 3)
 337         TWSI                    = 0xd2,
 338         MCU                     = 0xd3,
 339 #define NOW_IS_OOB                      (1 << 7)
 340 #define TX_EMPTY                        (1 << 5)
 341 #define RX_EMPTY                        (1 << 4)
 342 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 343 #define EN_NDP                          (1 << 3)
 344 #define EN_OOB_RESET                    (1 << 2)
 345 #define LINK_LIST_RDY                   (1 << 1)
 346         EFUSEAR                 = 0xdc,
 347 #define EFUSEAR_FLAG                    0x80000000
 348 #define EFUSEAR_WRITE_CMD               0x80000000
 349 #define EFUSEAR_READ_CMD                0x00000000
 350 #define EFUSEAR_REG_MASK                0x03ff
 351 #define EFUSEAR_REG_SHIFT               8
 352 #define EFUSEAR_DATA_MASK               0xff
 353         MISC_1                  = 0xf2,
 354 #define PFM_D3COLD_EN                   (1 << 6)
 355 };
 356
 357 enum rtl8168_registers {
 358         LED_FREQ                = 0x1a,
 359         EEE_LED                 = 0x1b,
 360         ERIDR                   = 0x70,
 361         ERIAR                   = 0x74,
 362 #define ERIAR_FLAG                      0x80000000
 363 #define ERIAR_WRITE_CMD                 0x80000000
 364 #define ERIAR_READ_CMD                  0x00000000
 365 #define ERIAR_ADDR_BYTE_ALIGN           4
 366 #define ERIAR_TYPE_SHIFT                16
 367 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 368 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 369 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 370 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 371 #define ERIAR_MASK_SHIFT                12
 372 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 373 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 374 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 375 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 376 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 377         EPHY_RXER_NUM           = 0x7c,
 378         OCPDR                   = 0xb0, /* OCP GPHY access */
 379 #define OCPDR_WRITE_CMD                 0x80000000
 380 #define OCPDR_READ_CMD                  0x00000000
 381 #define OCPDR_REG_MASK                  0x7f
 382 #define OCPDR_GPHY_REG_SHIFT            16
 383 #define OCPDR_DATA_MASK                 0xffff
 384         OCPAR                   = 0xb4,
 385 #define OCPAR_FLAG                      0x80000000
 386 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 387 #define OCPAR_GPHY_READ_CMD             0x0000f060
 388         GPHY_OCP                = 0xb8,
 389         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 390         MISC                    = 0xf0, /* 8168e only. */
 391 #define TXPLA_RST                       (1 << 29)
 392 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 393 #define PWM_EN                          (1 << 22)
 394 #define RXDV_GATED_EN                   (1 << 19)
 395 #define EARLY_TALLY_EN                  (1 << 16)
 396 };
 397
 398 enum rtl_register_content {
 399         /* InterruptStatusBits */
 400         SYSErr          = 0x8000,
 401         PCSTimeout      = 0x4000,
 402         SWInt           = 0x0100,
 403         TxDescUnavail   = 0x0080,
 404         RxFIFOOver      = 0x0040,
 405         LinkChg         = 0x0020,
 406         RxOverflow      = 0x0010,
 407         TxErr           = 0x0008,
 408         TxOK            = 0x0004,
 409         RxErr           = 0x0002,
 410         RxOK            = 0x0001,
 411
 412         /* RxStatusDesc */
 413         RxBOVF  = (1 << 24),
 414         RxFOVF  = (1 << 23),
 415         RxRWT   = (1 << 22),
 416         RxRES   = (1 << 21),
 417         RxRUNT  = (1 << 20),
 418         RxCRC   = (1 << 19),
 419
 420         /* ChipCmdBits */
 421         StopReq         = 0x80,
 422         CmdReset        = 0x10,
 423         CmdRxEnb        = 0x08,
 424         CmdTxEnb        = 0x04,
 425         RxBufEmpty      = 0x01,
 426
 427         /* TXPoll register p.5 */
 428         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 429         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 430         FSWInt          = 0x01,         /* Forced software interrupt */
 431
 432         /* Cfg9346Bits */
 433         Cfg9346_Lock    = 0x00,
 434         Cfg9346_Unlock  = 0xc0,
 435
 436         /* rx_mode_bits */
 437         AcceptErr       = 0x20,
 438         AcceptRunt      = 0x10,
 439         AcceptBroadcast = 0x08,
 440         AcceptMulticast = 0x04,
 441         AcceptMyPhys    = 0x02,
 442         AcceptAllPhys   = 0x01,
 443 #define RX_CONFIG_ACCEPT_MASK           0x3f
 444
 445         /* TxConfigBits */
 446         TxInterFrameGapShift = 24,
 447         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 448
 449         /* Config1 register p.24 */
 450         LEDS1           = (1 << 7),
 451         LEDS0           = (1 << 6),
 452         Speed_down      = (1 << 4),
 453         MEMMAP          = (1 << 3),
 454         IOMAP           = (1 << 2),
 455         VPD             = (1 << 1),
 456         PMEnable        = (1 << 0),     /* Power Management Enable */
 457
 458         /* Config2 register p. 25 */
 459         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 460         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 461         PCI_Clock_66MHz = 0x01,
 462         PCI_Clock_33MHz = 0x00,
 463
 464         /* Config3 register p.25 */
 465         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 466         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 467         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 468         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 469         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 470
 471         /* Config4 register */
 472         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 473
 474         /* Config5 register p.27 */
 475         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 476         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 477         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 478         Spi_en          = (1 << 3),
 479         LanWake         = (1 << 1),     /* LanWake enable/disable */
 480         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 481         ASPM_en         = (1 << 0),     /* ASPM enable */
 482
 483         /* CPlusCmd p.31 */
 484         EnableBist      = (1 << 15),    // 8168 8101
 485         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 486         Normal_mode     = (1 << 13),    // unused
 487         Force_half_dup  = (1 << 12),    // 8168 8101
 488         Force_rxflow_en = (1 << 11),    // 8168 8101
 489         Force_txflow_en = (1 << 10),    // 8168 8101
 490         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 491         ASF             = (1 << 8),     // 8168 8101
 492         PktCntrDisable  = (1 << 7),     // 8168 8101
 493         Mac_dbgo_sel    = 0x001c,       // 8168
 494         RxVlan          = (1 << 6),
 495         RxChkSum        = (1 << 5),
 496         PCIDAC          = (1 << 4),
 497         PCIMulRW        = (1 << 3),
 498 #define INTT_MASK       GENMASK(1, 0)
 499         INTT_0          = 0x0000,       // 8168
 500         INTT_1          = 0x0001,       // 8168
 501         INTT_2          = 0x0002,       // 8168
 502         INTT_3          = 0x0003,       // 8168
 503
 504         /* rtl8169_PHYstatus */
 505         TBI_Enable      = 0x80,
 506         TxFlowCtrl      = 0x40,
 507         RxFlowCtrl      = 0x20,
 508         _1000bpsF       = 0x10,
 509         _100bps         = 0x08,
 510         _10bps          = 0x04,
 511         LinkStatus      = 0x02,
 512         FullDup         = 0x01,
 513
 514         /* _TBICSRBit */
 515         TBILinkOK       = 0x02000000,
 516
 517         /* ResetCounterCommand */
 518         CounterReset    = 0x1,
 519
 520         /* DumpCounterCommand */
 521         CounterDump     = 0x8,
 522
 523         /* magic enable v2 */
 524         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 525 };
 526
 527 enum rtl_desc_bit {
 528         /* First doubleword. */
 529         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 530         RingEnd         = (1 << 30), /* End of descriptor ring */
 531         FirstFrag       = (1 << 29), /* First segment of a packet */
 532         LastFrag        = (1 << 28), /* Final segment of a packet */
 533 };
 534
 535 /* Generic case. */
 536 enum rtl_tx_desc_bit {
 537         /* First doubleword. */
 538         TD_LSO          = (1 << 27),            /* Large Send Offload */
 539 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 540
 541         /* Second doubleword. */
 542         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 543 };
 544
 545 /* 8169, 8168b and 810x except 8102e. */
 546 enum rtl_tx_desc_bit_0 {
 547         /* First doubleword. */
 548 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 549         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 550         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 551         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 552 };
 553
 554 /* 8102e, 8168c and beyond. */
 555 enum rtl_tx_desc_bit_1 {
 556         /* First doubleword. */
 557         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 558         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 559 #define GTTCPHO_SHIFT                   18
 560 #define GTTCPHO_MAX                     0x7fU
 561
 562         /* Second doubleword. */
 563 #define TCPHO_SHIFT                     18
 564 #define TCPHO_MAX                       0x3ffU
 565 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 566         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 567         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 568         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 569         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 570 };
 571
 572 enum rtl_rx_desc_bit {
 573         /* Rx private */
 574         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 575         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 576
 577 #define RxProtoUDP      (PID1)
 578 #define RxProtoTCP      (PID0)
 579 #define RxProtoIP       (PID1 | PID0)
 580 #define RxProtoMask     RxProtoIP
 581
 582         IPFail          = (1 << 16), /* IP checksum failed */
 583         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 584         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 585         RxVlanTag       = (1 << 16), /* VLAN tag available */
 586 };
 587
 588 #define RsvdMask        0x3fffc000
 589 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 590
 591 struct TxDesc {
 592         __le32 opts1;
 593         __le32 opts2;
 594         __le64 addr;
 595 };
 596
 597 struct RxDesc {
 598         __le32 opts1;
 599         __le32 opts2;
 600         __le64 addr;
 601 };
 602
 603 struct ring_info {
 604         struct sk_buff  *skb;
 605         u32             len;
 606 };
 607
 608 struct rtl8169_counters {
 609         __le64  tx_packets;
 610         __le64  rx_packets;
 611         __le64  tx_errors;
 612         __le32  rx_errors;
 613         __le16  rx_missed;
 614         __le16  align_errors;
 615         __le32  tx_one_collision;
 616         __le32  tx_multi_collision;
 617         __le64  rx_unicast;
 618         __le64  rx_broadcast;
 619         __le32  rx_multicast;
 620         __le16  tx_aborted;
 621         __le16  tx_underun;
 622 };
 623
 624 struct rtl8169_tc_offsets {
 625         bool    inited;
 626         __le64  tx_errors;
 627         __le32  tx_multi_collision;
 628         __le16  tx_aborted;
 629 };
 630
 631 enum rtl_flag {
 632         RTL_FLAG_TASK_ENABLED = 0,
 633         RTL_FLAG_TASK_RESET_PENDING,
 634         RTL_FLAG_MAX
 635 };
 636
 637 struct rtl8169_stats {
 638         u64                     packets;
 639         u64                     bytes;
 640         struct u64_stats_sync   syncp;
 641 };
 642
 643 struct rtl8169_private {
 644         void __iomem *mmio_addr;        /* memory map physical address */
 645         struct pci_dev *pci_dev;
 646         struct net_device *dev;
 647         struct napi_struct napi;
 648         u32 msg_enable;
 649         u16 mac_version;
 650         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 651         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 652         u32 dirty_tx;
 653         struct rtl8169_stats rx_stats;
 654         struct rtl8169_stats tx_stats;
 655         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 656         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 657         dma_addr_t TxPhyAddr;
 658         dma_addr_t RxPhyAddr;
 659         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 660         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 661         u16 cp_cmd;
 662
 663         u16 irq_mask;
 664         const struct rtl_coalesce_info *coalesce_info;
 665         struct clk *clk;
 666
 667         struct mdio_ops {
 668                 void (*write)(struct rtl8169_private *, int, int);
 669                 int (*read)(struct rtl8169_private *, int);
 670         } mdio_ops;
 671
 672         struct jumbo_ops {
 673                 void (*enable)(struct rtl8169_private *);
 674                 void (*disable)(struct rtl8169_private *);
 675         } jumbo_ops;
 676
 677         void (*hw_start)(struct rtl8169_private *tp);
 678         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 679
 680         struct {
 681                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 682                 struct mutex mutex;
 683                 struct work_struct work;
 684         } wk;
 685
 686         unsigned supports_gmii:1;
 687         struct mii_bus *mii_bus;
 688         dma_addr_t counters_phys_addr;
 689         struct rtl8169_counters *counters;
 690         struct rtl8169_tc_offsets tc_offset;
 691         u32 saved_wolopts;
 692
 693         struct rtl_fw {
 694                 const struct firmware *fw;
 695
 696 #define RTL_VER_SIZE            32
 697
 698                 char version[RTL_VER_SIZE];
 699
 700                 struct rtl_fw_phy_action {
 701                         __le32 *code;
 702                         size_t size;
 703                 } phy_action;
 704         } *rtl_fw;
 705 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 706
 707         u32 ocp_base;
 708 };
 709
 710 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 711 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 712 module_param(use_dac, int, 0);
 713 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 714 module_param_named(debug, debug.msg_enable, int, 0);
 715 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 716 MODULE_LICENSE("GPL");
 717 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 719 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 720 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 721 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 722 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 723 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 724 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 725 MODULE_FIRMWARE(FIRMWARE_8402_1);
 726 MODULE_FIRMWARE(FIRMWARE_8411_1);
 727 MODULE_FIRMWARE(FIRMWARE_8411_2);
 728 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 729 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 730 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 731 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 732 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 733 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 734 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 735 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 736
 737 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 738 {
 739         return &tp->pci_dev->dev;
 740 }
 741
 742 static void rtl_lock_work(struct rtl8169_private *tp)
 743 {
 744         mutex_lock(&tp->wk.mutex);
 745 }
 746
 747 static void rtl_unlock_work(struct rtl8169_private *tp)
 748 {
 749         mutex_unlock(&tp->wk.mutex);
 750 }
 751
 752 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 753 {
 754         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 755                                            PCI_EXP_DEVCTL_READRQ, force);
 756 }
 757
 758 struct rtl_cond {
 759         bool (*check)(struct rtl8169_private *);
 760         const char *msg;
 761 };
 762
 763 static void rtl_udelay(unsigned int d)
 764 {
 765         udelay(d);
 766 }
 767
 768 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 769                           void (*delay)(unsigned int), unsigned int d, int n,
 770                           bool high)
 771 {
 772         int i;
 773
 774         for (i = 0; i < n; i++) {
 775                 delay(d);
 776                 if (c->check(tp) == high)
 777                         return true;
 778         }
 779         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 780                   c->msg, !high, n, d);
 781         return false;
 782 }
 783
 784 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 785                                       const struct rtl_cond *c,
 786                                       unsigned int d, int n)
 787 {
 788         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 789 }
 790
 791 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 792                                      const struct rtl_cond *c,
 793                                      unsigned int d, int n)
 794 {
 795         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 796 }
 797
 798 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 799                                       const struct rtl_cond *c,
 800                                       unsigned int d, int n)
 801 {
 802         return rtl_loop_wait(tp, c, msleep, d, n, true);
 803 }
 804
 805 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 806                                      const struct rtl_cond *c,
 807                                      unsigned int d, int n)
 808 {
 809         return rtl_loop_wait(tp, c, msleep, d, n, false);
 810 }
 811
 812 #define DECLARE_RTL_COND(name)                          \
 813 static bool name ## _check(struct rtl8169_private *);   \
 814                                                         \
 815 static const struct rtl_cond name = {                   \
 816         .check  = name ## _check,                       \
 817         .msg    = #name                                 \
 818 };                                                      \
 819                                                         \
 820 static bool name ## _check(struct rtl8169_private *tp)
 821
 822 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 823 {
 824         if (reg & 0xffff0001) {
 825                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 826                 return true;
 827         }
 828         return false;
 829 }
 830
 831 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 832 {
 833         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 834 }
 835
 836 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 837 {
 838         if (rtl_ocp_reg_failure(tp, reg))
 839                 return;
 840
 841         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 842
 843         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 844 }
 845
 846 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 847 {
 848         if (rtl_ocp_reg_failure(tp, reg))
 849                 return 0;
 850
 851         RTL_W32(tp, GPHY_OCP, reg << 15);
 852
 853         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 854                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 855 }
 856
 857 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 858 {
 859         if (rtl_ocp_reg_failure(tp, reg))
 860                 return;
 861
 862         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 863 }
 864
 865 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 866 {
 867         if (rtl_ocp_reg_failure(tp, reg))
 868                 return 0;
 869
 870         RTL_W32(tp, OCPDR, reg << 15);
 871
 872         return RTL_R32(tp, OCPDR);
 873 }
 874
 875 #define OCP_STD_PHY_BASE        0xa400
 876
 877 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 878 {
 879         if (reg == 0x1f) {
 880                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 881                 return;
 882         }
 883
 884         if (tp->ocp_base != OCP_STD_PHY_BASE)
 885                 reg -= 0x10;
 886
 887         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 888 }
 889
 890 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 891 {
 892         if (tp->ocp_base != OCP_STD_PHY_BASE)
 893                 reg -= 0x10;
 894
 895         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 896 }
 897
 898 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 899 {
 900         if (reg == 0x1f) {
 901                 tp->ocp_base = value << 4;
 902                 return;
 903         }
 904
 905         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 906 }
 907
 908 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 909 {
 910         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 911 }
 912
 913 DECLARE_RTL_COND(rtl_phyar_cond)
 914 {
 915         return RTL_R32(tp, PHYAR) & 0x80000000;
 916 }
 917
 918 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 919 {
 920         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 921
 922         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 923         /*
 924          * According to hardware specs a 20us delay is required after write
 925          * complete indication, but before sending next command.
 926          */
 927         udelay(20);
 928 }
 929
 930 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 931 {
 932         int value;
 933
 934         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 935
 936         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 937                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 938
 939         /*
 940          * According to hardware specs a 20us delay is required after read
 941          * complete indication, but before sending next command.
 942          */
 943         udelay(20);
 944
 945         return value;
 946 }
 947
 948 DECLARE_RTL_COND(rtl_ocpar_cond)
 949 {
 950         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 951 }
 952
 953 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 954 {
 955         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 956         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 957         RTL_W32(tp, EPHY_RXER_NUM, 0);
 958
 959         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 960 }
 961
 962 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 963 {
 964         r8168dp_1_mdio_access(tp, reg,
 965                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 966 }
 967
 968 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 969 {
 970         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 971
 972         mdelay(1);
 973         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 974         RTL_W32(tp, EPHY_RXER_NUM, 0);
 975
 976         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 977                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 978 }
 979
 980 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 981
 982 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 983 {
 984         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 985 }
 986
 987 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 988 {
 989         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 990 }
 991
 992 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 993 {
 994         r8168dp_2_mdio_start(tp);
 995
 996         r8169_mdio_write(tp, reg, value);
 997
 998         r8168dp_2_mdio_stop(tp);
 999 }
1000
1001 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1002 {
1003         int value;
1004
1005         r8168dp_2_mdio_start(tp);
1006
1007         value = r8169_mdio_read(tp, reg);
1008
1009         r8168dp_2_mdio_stop(tp);
1010
1011         return value;
1012 }
1013
1014 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1015 {
1016         tp->mdio_ops.write(tp, location, val);
1017 }
1018
1019 static int rtl_readphy(struct rtl8169_private *tp, int location)
1020 {
1021         return tp->mdio_ops.read(tp, location);
1022 }
1023
1024 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1025 {
1026         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1027 }
1028
1029 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1030 {
1031         int val;
1032
1033         val = rtl_readphy(tp, reg_addr);
1034         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1035 }
1036
1037 DECLARE_RTL_COND(rtl_ephyar_cond)
1038 {
1039         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1040 }
1041
1042 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1043 {
1044         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1045                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1046
1047         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1048
1049         udelay(10);
1050 }
1051
1052 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1053 {
1054         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1055
1056         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1057                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1058 }
1059
1060 DECLARE_RTL_COND(rtl_eriar_cond)
1061 {
1062         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1063 }
1064
1065 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1066                           u32 val, int type)
1067 {
1068         BUG_ON((addr & 3) || (mask == 0));
1069         RTL_W32(tp, ERIDR, val);
1070         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1071
1072         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1073 }
1074
1075 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1076 {
1077         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1078
1079         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1080                 RTL_R32(tp, ERIDR) : ~0;
1081 }
1082
1083 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1084                          u32 m, int type)
1085 {
1086         u32 val;
1087
1088         val = rtl_eri_read(tp, addr, type);
1089         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1090 }
1091
1092 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1093 {
1094         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1095         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1096                 RTL_R32(tp, OCPDR) : ~0;
1097 }
1098
1099 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1100 {
1101         return rtl_eri_read(tp, reg, ERIAR_OOB);
1102 }
1103
1104 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1105 {
1106         switch (tp->mac_version) {
1107         case RTL_GIGA_MAC_VER_27:
1108         case RTL_GIGA_MAC_VER_28:
1109         case RTL_GIGA_MAC_VER_31:
1110                 return r8168dp_ocp_read(tp, mask, reg);
1111         case RTL_GIGA_MAC_VER_49:
1112         case RTL_GIGA_MAC_VER_50:
1113         case RTL_GIGA_MAC_VER_51:
1114                 return r8168ep_ocp_read(tp, mask, reg);
1115         default:
1116                 BUG();
1117                 return ~0;
1118         }
1119 }
1120
1121 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1122                               u32 data)
1123 {
1124         RTL_W32(tp, OCPDR, data);
1125         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1126         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1127 }
1128
1129 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1130                               u32 data)
1131 {
1132         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1133                       data, ERIAR_OOB);
1134 }
1135
1136 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1137 {
1138         switch (tp->mac_version) {
1139         case RTL_GIGA_MAC_VER_27:
1140         case RTL_GIGA_MAC_VER_28:
1141         case RTL_GIGA_MAC_VER_31:
1142                 r8168dp_ocp_write(tp, mask, reg, data);
1143                 break;
1144         case RTL_GIGA_MAC_VER_49:
1145         case RTL_GIGA_MAC_VER_50:
1146         case RTL_GIGA_MAC_VER_51:
1147                 r8168ep_ocp_write(tp, mask, reg, data);
1148                 break;
1149         default:
1150                 BUG();
1151                 break;
1152         }
1153 }
1154
1155 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1156 {
1157         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1158
1159         ocp_write(tp, 0x1, 0x30, 0x00000001);
1160 }
1161
1162 #define OOB_CMD_RESET           0x00
1163 #define OOB_CMD_DRIVER_START    0x05
1164 #define OOB_CMD_DRIVER_STOP     0x06
1165
1166 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1167 {
1168         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1169 }
1170
1171 DECLARE_RTL_COND(rtl_ocp_read_cond)
1172 {
1173         u16 reg;
1174
1175         reg = rtl8168_get_ocp_reg(tp);
1176
1177         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1178 }
1179
1180 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1181 {
1182         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1183 }
1184
1185 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1186 {
1187         return RTL_R8(tp, IBISR0) & 0x20;
1188 }
1189
1190 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1191 {
1192         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1193         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1194         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1195         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1196 }
1197
1198 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1199 {
1200         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1201         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1202 }
1203
1204 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1205 {
1206         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1207         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1208         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1209 }
1210
1211 static void rtl8168_driver_start(struct rtl8169_private *tp)
1212 {
1213         switch (tp->mac_version) {
1214         case RTL_GIGA_MAC_VER_27:
1215         case RTL_GIGA_MAC_VER_28:
1216         case RTL_GIGA_MAC_VER_31:
1217                 rtl8168dp_driver_start(tp);
1218                 break;
1219         case RTL_GIGA_MAC_VER_49:
1220         case RTL_GIGA_MAC_VER_50:
1221         case RTL_GIGA_MAC_VER_51:
1222                 rtl8168ep_driver_start(tp);
1223                 break;
1224         default:
1225                 BUG();
1226                 break;
1227         }
1228 }
1229
1230 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1231 {
1232         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1233         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1234 }
1235
1236 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1237 {
1238         rtl8168ep_stop_cmac(tp);
1239         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1240         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1241         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1242 }
1243
1244 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1245 {
1246         switch (tp->mac_version) {
1247         case RTL_GIGA_MAC_VER_27:
1248         case RTL_GIGA_MAC_VER_28:
1249         case RTL_GIGA_MAC_VER_31:
1250                 rtl8168dp_driver_stop(tp);
1251                 break;
1252         case RTL_GIGA_MAC_VER_49:
1253         case RTL_GIGA_MAC_VER_50:
1254         case RTL_GIGA_MAC_VER_51:
1255                 rtl8168ep_driver_stop(tp);
1256                 break;
1257         default:
1258                 BUG();
1259                 break;
1260         }
1261 }
1262
1263 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1264 {
1265         u16 reg = rtl8168_get_ocp_reg(tp);
1266
1267         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1268 }
1269
1270 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1271 {
1272         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1273 }
1274
1275 static bool r8168_check_dash(struct rtl8169_private *tp)
1276 {
1277         switch (tp->mac_version) {
1278         case RTL_GIGA_MAC_VER_27:
1279         case RTL_GIGA_MAC_VER_28:
1280         case RTL_GIGA_MAC_VER_31:
1281                 return r8168dp_check_dash(tp);
1282         case RTL_GIGA_MAC_VER_49:
1283         case RTL_GIGA_MAC_VER_50:
1284         case RTL_GIGA_MAC_VER_51:
1285                 return r8168ep_check_dash(tp);
1286         default:
1287                 return false;
1288         }
1289 }
1290
1291 struct exgmac_reg {
1292         u16 addr;
1293         u16 mask;
1294         u32 val;
1295 };
1296
1297 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1298                                    const struct exgmac_reg *r, int len)
1299 {
1300         while (len-- > 0) {
1301                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1302                 r++;
1303         }
1304 }
1305
1306 DECLARE_RTL_COND(rtl_efusear_cond)
1307 {
1308         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1309 }
1310
1311 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1312 {
1313         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1314
1315         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1316                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1317 }
1318
1319 static u16 rtl_get_events(struct rtl8169_private *tp)
1320 {
1321         return RTL_R16(tp, IntrStatus);
1322 }
1323
1324 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1325 {
1326         RTL_W16(tp, IntrStatus, bits);
1327         mmiowb();
1328 }
1329
1330 static void rtl_irq_disable(struct rtl8169_private *tp)
1331 {
1332         RTL_W16(tp, IntrMask, 0);
1333         mmiowb();
1334 }
1335
1336 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1337 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1338 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1339
1340 static void rtl_irq_enable(struct rtl8169_private *tp)
1341 {
1342         RTL_W16(tp, IntrMask, tp->irq_mask);
1343 }
1344
1345 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1346 {
1347         rtl_irq_disable(tp);
1348         rtl_ack_events(tp, 0xffff);
1349         /* PCI commit */
1350         RTL_R8(tp, ChipCmd);
1351 }
1352
1353 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1354 {
1355         struct net_device *dev = tp->dev;
1356         struct phy_device *phydev = dev->phydev;
1357
1358         if (!netif_running(dev))
1359                 return;
1360
1361         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1362             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1363                 if (phydev->speed == SPEED_1000) {
1364                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1365                                       ERIAR_EXGMAC);
1366                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1367                                       ERIAR_EXGMAC);
1368                 } else if (phydev->speed == SPEED_100) {
1369                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1370                                       ERIAR_EXGMAC);
1371                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1372                                       ERIAR_EXGMAC);
1373                 } else {
1374                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1375                                       ERIAR_EXGMAC);
1376                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1377                                       ERIAR_EXGMAC);
1378                 }
1379                 /* Reset packet filter */
1380                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1381                              ERIAR_EXGMAC);
1382                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1383                              ERIAR_EXGMAC);
1384         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1385                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1386                 if (phydev->speed == SPEED_1000) {
1387                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1388                                       ERIAR_EXGMAC);
1389                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1390                                       ERIAR_EXGMAC);
1391                 } else {
1392                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1393                                       ERIAR_EXGMAC);
1394                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1395                                       ERIAR_EXGMAC);
1396                 }
1397         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1398                 if (phydev->speed == SPEED_10) {
1399                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1400                                       ERIAR_EXGMAC);
1401                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1402                                       ERIAR_EXGMAC);
1403                 } else {
1404                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1405                                       ERIAR_EXGMAC);
1406                 }
1407         }
1408 }
1409
1410 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1411
1412 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1413 {
1414         u8 options;
1415         u32 wolopts = 0;
1416
1417         options = RTL_R8(tp, Config1);
1418         if (!(options & PMEnable))
1419                 return 0;
1420
1421         options = RTL_R8(tp, Config3);
1422         if (options & LinkUp)
1423                 wolopts |= WAKE_PHY;
1424         switch (tp->mac_version) {
1425         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1426         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1427                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1428                         wolopts |= WAKE_MAGIC;
1429                 break;
1430         default:
1431                 if (options & MagicPacket)
1432                         wolopts |= WAKE_MAGIC;
1433                 break;
1434         }
1435
1436         options = RTL_R8(tp, Config5);
1437         if (options & UWF)
1438                 wolopts |= WAKE_UCAST;
1439         if (options & BWF)
1440                 wolopts |= WAKE_BCAST;
1441         if (options & MWF)
1442                 wolopts |= WAKE_MCAST;
1443
1444         return wolopts;
1445 }
1446
1447 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1448 {
1449         struct rtl8169_private *tp = netdev_priv(dev);
1450
1451         rtl_lock_work(tp);
1452         wol->supported = WAKE_ANY;
1453         wol->wolopts = tp->saved_wolopts;
1454         rtl_unlock_work(tp);
1455 }
1456
1457 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1458 {
1459         unsigned int i, tmp;
1460         static const struct {
1461                 u32 opt;
1462                 u16 reg;
1463                 u8  mask;
1464         } cfg[] = {
1465                 { WAKE_PHY,   Config3, LinkUp },
1466                 { WAKE_UCAST, Config5, UWF },
1467                 { WAKE_BCAST, Config5, BWF },
1468                 { WAKE_MCAST, Config5, MWF },
1469                 { WAKE_ANY,   Config5, LanWake },
1470                 { WAKE_MAGIC, Config3, MagicPacket }
1471         };
1472         u8 options;
1473
1474         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1475
1476         switch (tp->mac_version) {
1477         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1478         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1479                 tmp = ARRAY_SIZE(cfg) - 1;
1480                 if (wolopts & WAKE_MAGIC)
1481                         rtl_w0w1_eri(tp,
1482                                      0x0dc,
1483                                      ERIAR_MASK_0100,
1484                                      MagicPacket_v2,
1485                                      0x0000,
1486                                      ERIAR_EXGMAC);
1487                 else
1488                         rtl_w0w1_eri(tp,
1489                                      0x0dc,
1490                                      ERIAR_MASK_0100,
1491                                      0x0000,
1492                                      MagicPacket_v2,
1493                                      ERIAR_EXGMAC);
1494                 break;
1495         default:
1496                 tmp = ARRAY_SIZE(cfg);
1497                 break;
1498         }
1499
1500         for (i = 0; i < tmp; i++) {
1501                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1502                 if (wolopts & cfg[i].opt)
1503                         options |= cfg[i].mask;
1504                 RTL_W8(tp, cfg[i].reg, options);
1505         }
1506
1507         switch (tp->mac_version) {
1508         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1509                 options = RTL_R8(tp, Config1) & ~PMEnable;
1510                 if (wolopts)
1511                         options |= PMEnable;
1512                 RTL_W8(tp, Config1, options);
1513                 break;
1514         default:
1515                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1516                 if (wolopts)
1517                         options |= PME_SIGNAL;
1518                 RTL_W8(tp, Config2, options);
1519                 break;
1520         }
1521
1522         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1523 }
1524
1525 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1526 {
1527         struct rtl8169_private *tp = netdev_priv(dev);
1528         struct device *d = tp_to_dev(tp);
1529
1530         if (wol->wolopts & ~WAKE_ANY)
1531                 return -EINVAL;
1532
1533         pm_runtime_get_noresume(d);
1534
1535         rtl_lock_work(tp);
1536
1537         tp->saved_wolopts = wol->wolopts;
1538
1539         if (pm_runtime_active(d))
1540                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1541
1542         rtl_unlock_work(tp);
1543
1544         device_set_wakeup_enable(d, tp->saved_wolopts);
1545
1546         pm_runtime_put_noidle(d);
1547
1548         return 0;
1549 }
1550
1551 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1552 {
1553         return rtl_chip_infos[tp->mac_version].fw_name;
1554 }
1555
1556 static void rtl8169_get_drvinfo(struct net_device *dev,
1557                                 struct ethtool_drvinfo *info)
1558 {
1559         struct rtl8169_private *tp = netdev_priv(dev);
1560         struct rtl_fw *rtl_fw = tp->rtl_fw;
1561
1562         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1563         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1564         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1565         if (!IS_ERR_OR_NULL(rtl_fw))
1566                 strlcpy(info->fw_version, rtl_fw->version,
1567                         sizeof(info->fw_version));
1568 }
1569
1570 static int rtl8169_get_regs_len(struct net_device *dev)
1571 {
1572         return R8169_REGS_SIZE;
1573 }
1574
1575 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1576         netdev_features_t features)
1577 {
1578         struct rtl8169_private *tp = netdev_priv(dev);
1579
1580         if (dev->mtu > TD_MSS_MAX)
1581                 features &= ~NETIF_F_ALL_TSO;
1582
1583         if (dev->mtu > JUMBO_1K &&
1584             tp->mac_version > RTL_GIGA_MAC_VER_06)
1585                 features &= ~NETIF_F_IP_CSUM;
1586
1587         return features;
1588 }
1589
1590 static int rtl8169_set_features(struct net_device *dev,
1591                                 netdev_features_t features)
1592 {
1593         struct rtl8169_private *tp = netdev_priv(dev);
1594         u32 rx_config;
1595
1596         rtl_lock_work(tp);
1597
1598         rx_config = RTL_R32(tp, RxConfig);
1599         if (features & NETIF_F_RXALL)
1600                 rx_config |= (AcceptErr | AcceptRunt);
1601         else
1602                 rx_config &= ~(AcceptErr | AcceptRunt);
1603
1604         RTL_W32(tp, RxConfig, rx_config);
1605
1606         if (features & NETIF_F_RXCSUM)
1607                 tp->cp_cmd |= RxChkSum;
1608         else
1609                 tp->cp_cmd &= ~RxChkSum;
1610
1611         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1612                 tp->cp_cmd |= RxVlan;
1613         else
1614                 tp->cp_cmd &= ~RxVlan;
1615
1616         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1617         RTL_R16(tp, CPlusCmd);
1618
1619         rtl_unlock_work(tp);
1620
1621         return 0;
1622 }
1623
1624 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1625 {
1626         return (skb_vlan_tag_present(skb)) ?
1627                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1628 }
1629
1630 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1631 {
1632         u32 opts2 = le32_to_cpu(desc->opts2);
1633
1634         if (opts2 & RxVlanTag)
1635                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1636 }
1637
1638 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1639                              void *p)
1640 {
1641         struct rtl8169_private *tp = netdev_priv(dev);
1642         u32 __iomem *data = tp->mmio_addr;
1643         u32 *dw = p;
1644         int i;
1645
1646         rtl_lock_work(tp);
1647         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1648                 memcpy_fromio(dw++, data++, 4);
1649         rtl_unlock_work(tp);
1650 }
1651
1652 static u32 rtl8169_get_msglevel(struct net_device *dev)
1653 {
1654         struct rtl8169_private *tp = netdev_priv(dev);
1655
1656         return tp->msg_enable;
1657 }
1658
1659 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1660 {
1661         struct rtl8169_private *tp = netdev_priv(dev);
1662
1663         tp->msg_enable = value;
1664 }
1665
1666 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1667         "tx_packets",
1668         "rx_packets",
1669         "tx_errors",
1670         "rx_errors",
1671         "rx_missed",
1672         "align_errors",
1673         "tx_single_collisions",
1674         "tx_multi_collisions",
1675         "unicast",
1676         "broadcast",
1677         "multicast",
1678         "tx_aborted",
1679         "tx_underrun",
1680 };
1681
1682 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1683 {
1684         switch (sset) {
1685         case ETH_SS_STATS:
1686                 return ARRAY_SIZE(rtl8169_gstrings);
1687         default:
1688                 return -EOPNOTSUPP;
1689         }
1690 }
1691
1692 DECLARE_RTL_COND(rtl_counters_cond)
1693 {
1694         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1695 }
1696
1697 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1698 {
1699         dma_addr_t paddr = tp->counters_phys_addr;
1700         u32 cmd;
1701
1702         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1703         RTL_R32(tp, CounterAddrHigh);
1704         cmd = (u64)paddr & DMA_BIT_MASK(32);
1705         RTL_W32(tp, CounterAddrLow, cmd);
1706         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1707
1708         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1709 }
1710
1711 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1712 {
1713         /*
1714          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1715          * tally counters.
1716          */
1717         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1718                 return true;
1719
1720         return rtl8169_do_counters(tp, CounterReset);
1721 }
1722
1723 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1724 {
1725         /*
1726          * Some chips are unable to dump tally counters when the receiver
1727          * is disabled.
1728          */
1729         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1730                 return true;
1731
1732         return rtl8169_do_counters(tp, CounterDump);
1733 }
1734
1735 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1736 {
1737         struct rtl8169_counters *counters = tp->counters;
1738         bool ret = false;
1739
1740         /*
1741          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1742          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1743          * reset by a power cycle, while the counter values collected by the
1744          * driver are reset at every driver unload/load cycle.
1745          *
1746          * To make sure the HW values returned by @get_stats64 match the SW
1747          * values, we collect the initial values at first open(*) and use them
1748          * as offsets to normalize the values returned by @get_stats64.
1749          *
1750          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1751          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1752          * set at open time by rtl_hw_start.
1753          */
1754
1755         if (tp->tc_offset.inited)
1756                 return true;
1757
1758         /* If both, reset and update fail, propagate to caller. */
1759         if (rtl8169_reset_counters(tp))
1760                 ret = true;
1761
1762         if (rtl8169_update_counters(tp))
1763                 ret = true;
1764
1765         tp->tc_offset.tx_errors = counters->tx_errors;
1766         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1767         tp->tc_offset.tx_aborted = counters->tx_aborted;
1768         tp->tc_offset.inited = true;
1769
1770         return ret;
1771 }
1772
1773 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1774                                       struct ethtool_stats *stats, u64 *data)
1775 {
1776         struct rtl8169_private *tp = netdev_priv(dev);
1777         struct device *d = tp_to_dev(tp);
1778         struct rtl8169_counters *counters = tp->counters;
1779
1780         ASSERT_RTNL();
1781
1782         pm_runtime_get_noresume(d);
1783
1784         if (pm_runtime_active(d))
1785                 rtl8169_update_counters(tp);
1786
1787         pm_runtime_put_noidle(d);
1788
1789         data[0] = le64_to_cpu(counters->tx_packets);
1790         data[1] = le64_to_cpu(counters->rx_packets);
1791         data[2] = le64_to_cpu(counters->tx_errors);
1792         data[3] = le32_to_cpu(counters->rx_errors);
1793         data[4] = le16_to_cpu(counters->rx_missed);
1794         data[5] = le16_to_cpu(counters->align_errors);
1795         data[6] = le32_to_cpu(counters->tx_one_collision);
1796         data[7] = le32_to_cpu(counters->tx_multi_collision);
1797         data[8] = le64_to_cpu(counters->rx_unicast);
1798         data[9] = le64_to_cpu(counters->rx_broadcast);
1799         data[10] = le32_to_cpu(counters->rx_multicast);
1800         data[11] = le16_to_cpu(counters->tx_aborted);
1801         data[12] = le16_to_cpu(counters->tx_underun);
1802 }
1803
1804 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1805 {
1806         switch(stringset) {
1807         case ETH_SS_STATS:
1808                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1809                 break;
1810         }
1811 }
1812
1813 /*
1814  * Interrupt coalescing
1815  *
1816  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1817  * >     8169, 8168 and 810x line of chipsets
1818  *
1819  * 8169, 8168, and 8136(810x) serial chipsets support it.
1820  *
1821  * > 2 - the Tx timer unit at gigabit speed
1822  *
1823  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1824  * (0xe0) bit 1 and bit 0.
1825  *
1826  * For 8169
1827  * bit[1:0] \ speed        1000M           100M            10M
1828  * 0 0                     320ns           2.56us          40.96us
1829  * 0 1                     2.56us          20.48us         327.7us
1830  * 1 0                     5.12us          40.96us         655.4us
1831  * 1 1                     10.24us         81.92us         1.31ms
1832  *
1833  * For the other
1834  * bit[1:0] \ speed        1000M           100M            10M
1835  * 0 0                     5us             2.56us          40.96us
1836  * 0 1                     40us            20.48us         327.7us
1837  * 1 0                     80us            40.96us         655.4us
1838  * 1 1                     160us           81.92us         1.31ms
1839  */
1840
1841 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1842 struct rtl_coalesce_scale {
1843         /* Rx / Tx */
1844         u32 nsecs[2];
1845 };
1846
1847 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1848 struct rtl_coalesce_info {
1849         u32 speed;
1850         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1851 };
1852
1853 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1854 #define rxtx_x1822(r, t) {              \
1855         {{(r),          (t)}},          \
1856         {{(r)*8,        (t)*8}},        \
1857         {{(r)*8*2,      (t)*8*2}},      \
1858         {{(r)*8*2*2,    (t)*8*2*2}},    \
1859 }
1860 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1861         /* speed        delays:     rx00   tx00 */
1862         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1863         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1864         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1865         { 0 },
1866 };
1867
1868 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1869         /* speed        delays:     rx00   tx00 */
1870         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1871         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1872         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1873         { 0 },
1874 };
1875 #undef rxtx_x1822
1876
1877 /* get rx/tx scale vector corresponding to current speed */
1878 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1879 {
1880         struct rtl8169_private *tp = netdev_priv(dev);
1881         struct ethtool_link_ksettings ecmd;
1882         const struct rtl_coalesce_info *ci;
1883         int rc;
1884
1885         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1886         if (rc < 0)
1887                 return ERR_PTR(rc);
1888
1889         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1890                 if (ecmd.base.speed == ci->speed) {
1891                         return ci;
1892                 }
1893         }
1894
1895         return ERR_PTR(-ELNRNG);
1896 }
1897
1898 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1899 {
1900         struct rtl8169_private *tp = netdev_priv(dev);
1901         const struct rtl_coalesce_info *ci;
1902         const struct rtl_coalesce_scale *scale;
1903         struct {
1904                 u32 *max_frames;
1905                 u32 *usecs;
1906         } coal_settings [] = {
1907                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1908                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1909         }, *p = coal_settings;
1910         int i;
1911         u16 w;
1912
1913         memset(ec, 0, sizeof(*ec));
1914
1915         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1916         ci = rtl_coalesce_info(dev);
1917         if (IS_ERR(ci))
1918                 return PTR_ERR(ci);
1919
1920         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1921
1922         /* read IntrMitigate and adjust according to scale */
1923         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1924                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1925                 w >>= RTL_COALESCE_SHIFT;
1926                 *p->usecs = w & RTL_COALESCE_MASK;
1927         }
1928
1929         for (i = 0; i < 2; i++) {
1930                 p = coal_settings + i;
1931                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1932
1933                 /*
1934                  * ethtool_coalesce says it is illegal to set both usecs and
1935                  * max_frames to 0.
1936                  */
1937                 if (!*p->usecs && !*p->max_frames)
1938                         *p->max_frames = 1;
1939         }
1940
1941         return 0;
1942 }
1943
1944 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1945 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1946                         struct net_device *dev, u32 nsec, u16 *cp01)
1947 {
1948         const struct rtl_coalesce_info *ci;
1949         u16 i;
1950
1951         ci = rtl_coalesce_info(dev);
1952         if (IS_ERR(ci))
1953                 return ERR_CAST(ci);
1954
1955         for (i = 0; i < 4; i++) {
1956                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1957                                         ci->scalev[i].nsecs[1]);
1958                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1959                         *cp01 = i;
1960                         return &ci->scalev[i];
1961                 }
1962         }
1963
1964         return ERR_PTR(-EINVAL);
1965 }
1966
1967 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1968 {
1969         struct rtl8169_private *tp = netdev_priv(dev);
1970         const struct rtl_coalesce_scale *scale;
1971         struct {
1972                 u32 frames;
1973                 u32 usecs;
1974         } coal_settings [] = {
1975                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1976                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1977         }, *p = coal_settings;
1978         u16 w = 0, cp01;
1979         int i;
1980
1981         scale = rtl_coalesce_choose_scale(dev,
1982                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1983         if (IS_ERR(scale))
1984                 return PTR_ERR(scale);
1985
1986         for (i = 0; i < 2; i++, p++) {
1987                 u32 units;
1988
1989                 /*
1990                  * accept max_frames=1 we returned in rtl_get_coalesce.
1991                  * accept it not only when usecs=0 because of e.g. the following scenario:
1992                  *
1993                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1994                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1995                  * - then user does `ethtool -C eth0 rx-usecs 100`
1996                  *
1997                  * since ethtool sends to kernel whole ethtool_coalesce
1998                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1999                  * we'll reject it below in `frames % 4 != 0`.
2000                  */
2001                 if (p->frames == 1) {
2002                         p->frames = 0;
2003                 }
2004
2005                 units = p->usecs * 1000 / scale->nsecs[i];
2006                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2007                         return -EINVAL;
2008
2009                 w <<= RTL_COALESCE_SHIFT;
2010                 w |= units;
2011                 w <<= RTL_COALESCE_SHIFT;
2012                 w |= p->frames >> 2;
2013         }
2014
2015         rtl_lock_work(tp);
2016
2017         RTL_W16(tp, IntrMitigate, swab16(w));
2018
2019         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2020         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2021         RTL_R16(tp, CPlusCmd);
2022
2023         rtl_unlock_work(tp);
2024
2025         return 0;
2026 }
2027
2028 static const struct ethtool_ops rtl8169_ethtool_ops = {
2029         .get_drvinfo            = rtl8169_get_drvinfo,
2030         .get_regs_len           = rtl8169_get_regs_len,
2031         .get_link               = ethtool_op_get_link,
2032         .get_coalesce           = rtl_get_coalesce,
2033         .set_coalesce           = rtl_set_coalesce,
2034         .get_msglevel           = rtl8169_get_msglevel,
2035         .set_msglevel           = rtl8169_set_msglevel,
2036         .get_regs               = rtl8169_get_regs,
2037         .get_wol                = rtl8169_get_wol,
2038         .set_wol                = rtl8169_set_wol,
2039         .get_strings            = rtl8169_get_strings,
2040         .get_sset_count         = rtl8169_get_sset_count,
2041         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2042         .get_ts_info            = ethtool_op_get_ts_info,
2043         .nway_reset             = phy_ethtool_nway_reset,
2044         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2045         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2046 };
2047
2048 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2049                                     u8 default_version)
2050 {
2051         /*
2052          * The driver currently handles the 8168Bf and the 8168Be identically
2053          * but they can be identified more specifically through the test below
2054          * if needed:
2055          *
2056          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2057          *
2058          * Same thing for the 8101Eb and the 8101Ec:
2059          *
2060          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2061          */
2062         static const struct rtl_mac_info {
2063                 u32 mask;
2064                 u32 val;
2065                 int mac_version;
2066         } mac_info[] = {
2067                 /* 8168EP family. */
2068                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2069                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2070                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2071
2072                 /* 8168H family. */
2073                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2074                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2075
2076                 /* 8168G family. */
2077                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2078                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2079                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2080                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2081
2082                 /* 8168F family. */
2083                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2084                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2085                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2086
2087                 /* 8168E family. */
2088                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2089                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2090                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2091
2092                 /* 8168D family. */
2093                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2094                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2095
2096                 /* 8168DP family. */
2097                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2098                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2099                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2100
2101                 /* 8168C family. */
2102                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2103                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2104                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2105                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2106                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2107                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2108                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2109
2110                 /* 8168B family. */
2111                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2112                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2113                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2114
2115                 /* 8101 family. */
2116                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2117                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2118                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2119                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2120                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2121                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2122                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2123                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2124                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2125                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2126                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2127                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2128                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2129                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2130                 /* FIXME: where did these entries come from ? -- FR */
2131                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2132                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2133
2134                 /* 8110 family. */
2135                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2136                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2137                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2138                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2139                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2140                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2141
2142                 /* Catch-all */
2143                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2144         };
2145         const struct rtl_mac_info *p = mac_info;
2146         u32 reg;
2147
2148         reg = RTL_R32(tp, TxConfig);
2149         while ((reg & p->mask) != p->val)
2150                 p++;
2151         tp->mac_version = p->mac_version;
2152
2153         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2154                 dev_notice(tp_to_dev(tp),
2155                            "unknown MAC, using family default\n");
2156                 tp->mac_version = default_version;
2157         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2158                 tp->mac_version = tp->supports_gmii ?
2159                                   RTL_GIGA_MAC_VER_42 :
2160                                   RTL_GIGA_MAC_VER_43;
2161         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2162                 tp->mac_version = tp->supports_gmii ?
2163                                   RTL_GIGA_MAC_VER_45 :
2164                                   RTL_GIGA_MAC_VER_47;
2165         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2166                 tp->mac_version = tp->supports_gmii ?
2167                                   RTL_GIGA_MAC_VER_46 :
2168                                   RTL_GIGA_MAC_VER_48;
2169         }
2170 }
2171
2172 struct phy_reg {
2173         u16 reg;
2174         u16 val;
2175 };
2176
2177 static void rtl_writephy_batch(struct rtl8169_private *tp,
2178                                const struct phy_reg *regs, int len)
2179 {
2180         while (len-- > 0) {
2181                 rtl_writephy(tp, regs->reg, regs->val);
2182                 regs++;
2183         }
2184 }
2185
2186 #define PHY_READ                0x00000000
2187 #define PHY_DATA_OR             0x10000000
2188 #define PHY_DATA_AND            0x20000000
2189 #define PHY_BJMPN               0x30000000
2190 #define PHY_MDIO_CHG            0x40000000
2191 #define PHY_CLEAR_READCOUNT     0x70000000
2192 #define PHY_WRITE               0x80000000
2193 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2194 #define PHY_COMP_EQ_SKIPN       0xa0000000
2195 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2196 #define PHY_WRITE_PREVIOUS      0xc0000000
2197 #define PHY_SKIPN               0xd0000000
2198 #define PHY_DELAY_MS            0xe0000000
2199
2200 struct fw_info {
2201         u32     magic;
2202         char    version[RTL_VER_SIZE];
2203         __le32  fw_start;
2204         __le32  fw_len;
2205         u8      chksum;
2206 } __packed;
2207
2208 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2209
2210 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2211 {
2212         const struct firmware *fw = rtl_fw->fw;
2213         struct fw_info *fw_info = (struct fw_info *)fw->data;
2214         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2215         char *version = rtl_fw->version;
2216         bool rc = false;
2217
2218         if (fw->size < FW_OPCODE_SIZE)
2219                 goto out;
2220
2221         if (!fw_info->magic) {
2222                 size_t i, size, start;
2223                 u8 checksum = 0;
2224
2225                 if (fw->size < sizeof(*fw_info))
2226                         goto out;
2227
2228                 for (i = 0; i < fw->size; i++)
2229                         checksum += fw->data[i];
2230                 if (checksum != 0)
2231                         goto out;
2232
2233                 start = le32_to_cpu(fw_info->fw_start);
2234                 if (start > fw->size)
2235                         goto out;
2236
2237                 size = le32_to_cpu(fw_info->fw_len);
2238                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2239                         goto out;
2240
2241                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2242
2243                 pa->code = (__le32 *)(fw->data + start);
2244                 pa->size = size;
2245         } else {
2246                 if (fw->size % FW_OPCODE_SIZE)
2247                         goto out;
2248
2249                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2250
2251                 pa->code = (__le32 *)fw->data;
2252                 pa->size = fw->size / FW_OPCODE_SIZE;
2253         }
2254         version[RTL_VER_SIZE - 1] = 0;
2255
2256         rc = true;
2257 out:
2258         return rc;
2259 }
2260
2261 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2262                            struct rtl_fw_phy_action *pa)
2263 {
2264         bool rc = false;
2265         size_t index;
2266
2267         for (index = 0; index < pa->size; index++) {
2268                 u32 action = le32_to_cpu(pa->code[index]);
2269                 u32 regno = (action & 0x0fff0000) >> 16;
2270
2271                 switch(action & 0xf0000000) {
2272                 case PHY_READ:
2273                 case PHY_DATA_OR:
2274                 case PHY_DATA_AND:
2275                 case PHY_MDIO_CHG:
2276                 case PHY_CLEAR_READCOUNT:
2277                 case PHY_WRITE:
2278                 case PHY_WRITE_PREVIOUS:
2279                 case PHY_DELAY_MS:
2280                         break;
2281
2282                 case PHY_BJMPN:
2283                         if (regno > index) {
2284                                 netif_err(tp, ifup, tp->dev,
2285                                           "Out of range of firmware\n");
2286                                 goto out;
2287                         }
2288                         break;
2289                 case PHY_READCOUNT_EQ_SKIP:
2290                         if (index + 2 >= pa->size) {
2291                                 netif_err(tp, ifup, tp->dev,
2292                                           "Out of range of firmware\n");
2293                                 goto out;
2294                         }
2295                         break;
2296                 case PHY_COMP_EQ_SKIPN:
2297                 case PHY_COMP_NEQ_SKIPN:
2298                 case PHY_SKIPN:
2299                         if (index + 1 + regno >= pa->size) {
2300                                 netif_err(tp, ifup, tp->dev,
2301                                           "Out of range of firmware\n");
2302                                 goto out;
2303                         }
2304                         break;
2305
2306                 default:
2307                         netif_err(tp, ifup, tp->dev,
2308                                   "Invalid action 0x%08x\n", action);
2309                         goto out;
2310                 }
2311         }
2312         rc = true;
2313 out:
2314         return rc;
2315 }
2316
2317 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2318 {
2319         struct net_device *dev = tp->dev;
2320         int rc = -EINVAL;
2321
2322         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2323                 netif_err(tp, ifup, dev, "invalid firmware\n");
2324                 goto out;
2325         }
2326
2327         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2328                 rc = 0;
2329 out:
2330         return rc;
2331 }
2332
2333 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2334 {
2335         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2336         struct mdio_ops org, *ops = &tp->mdio_ops;
2337         u32 predata, count;
2338         size_t index;
2339
2340         predata = count = 0;
2341         org.write = ops->write;
2342         org.read = ops->read;
2343
2344         for (index = 0; index < pa->size; ) {
2345                 u32 action = le32_to_cpu(pa->code[index]);
2346                 u32 data = action & 0x0000ffff;
2347                 u32 regno = (action & 0x0fff0000) >> 16;
2348
2349                 if (!action)
2350                         break;
2351
2352                 switch(action & 0xf0000000) {
2353                 case PHY_READ:
2354                         predata = rtl_readphy(tp, regno);
2355                         count++;
2356                         index++;
2357                         break;
2358                 case PHY_DATA_OR:
2359                         predata |= data;
2360                         index++;
2361                         break;
2362                 case PHY_DATA_AND:
2363                         predata &= data;
2364                         index++;
2365                         break;
2366                 case PHY_BJMPN:
2367                         index -= regno;
2368                         break;
2369                 case PHY_MDIO_CHG:
2370                         if (data == 0) {
2371                                 ops->write = org.write;
2372                                 ops->read = org.read;
2373                         } else if (data == 1) {
2374                                 ops->write = mac_mcu_write;
2375                                 ops->read = mac_mcu_read;
2376                         }
2377
2378                         index++;
2379                         break;
2380                 case PHY_CLEAR_READCOUNT:
2381                         count = 0;
2382                         index++;
2383                         break;
2384                 case PHY_WRITE:
2385                         rtl_writephy(tp, regno, data);
2386                         index++;
2387                         break;
2388                 case PHY_READCOUNT_EQ_SKIP:
2389                         index += (count == data) ? 2 : 1;
2390                         break;
2391                 case PHY_COMP_EQ_SKIPN:
2392                         if (predata == data)
2393                                 index += regno;
2394                         index++;
2395                         break;
2396                 case PHY_COMP_NEQ_SKIPN:
2397                         if (predata != data)
2398                                 index += regno;
2399                         index++;
2400                         break;
2401                 case PHY_WRITE_PREVIOUS:
2402                         rtl_writephy(tp, regno, predata);
2403                         index++;
2404                         break;
2405                 case PHY_SKIPN:
2406                         index += regno + 1;
2407                         break;
2408                 case PHY_DELAY_MS:
2409                         mdelay(data);
2410                         index++;
2411                         break;
2412
2413                 default:
2414                         BUG();
2415                 }
2416         }
2417
2418         ops->write = org.write;
2419         ops->read = org.read;
2420 }
2421
2422 static void rtl_release_firmware(struct rtl8169_private *tp)
2423 {
2424         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2425                 release_firmware(tp->rtl_fw->fw);
2426                 kfree(tp->rtl_fw);
2427         }
2428         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2429 }
2430
2431 static void rtl_apply_firmware(struct rtl8169_private *tp)
2432 {
2433         struct rtl_fw *rtl_fw = tp->rtl_fw;
2434
2435         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2436         if (!IS_ERR_OR_NULL(rtl_fw))
2437                 rtl_phy_write_fw(tp, rtl_fw);
2438 }
2439
2440 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2441 {
2442         if (rtl_readphy(tp, reg) != val)
2443                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2444         else
2445                 rtl_apply_firmware(tp);
2446 }
2447
2448 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2449 {
2450         static const struct phy_reg phy_reg_init[] = {
2451                 { 0x1f, 0x0001 },
2452                 { 0x06, 0x006e },
2453                 { 0x08, 0x0708 },
2454                 { 0x15, 0x4000 },
2455                 { 0x18, 0x65c7 },
2456
2457                 { 0x1f, 0x0001 },
2458                 { 0x03, 0x00a1 },
2459                 { 0x02, 0x0008 },
2460                 { 0x01, 0x0120 },
2461                 { 0x00, 0x1000 },
2462                 { 0x04, 0x0800 },
2463                 { 0x04, 0x0000 },
2464
2465                 { 0x03, 0xff41 },
2466                 { 0x02, 0xdf60 },
2467                 { 0x01, 0x0140 },
2468                 { 0x00, 0x0077 },
2469                 { 0x04, 0x7800 },
2470                 { 0x04, 0x7000 },
2471
2472                 { 0x03, 0x802f },
2473                 { 0x02, 0x4f02 },
2474                 { 0x01, 0x0409 },
2475                 { 0x00, 0xf0f9 },
2476                 { 0x04, 0x9800 },
2477                 { 0x04, 0x9000 },
2478
2479                 { 0x03, 0xdf01 },
2480                 { 0x02, 0xdf20 },
2481                 { 0x01, 0xff95 },
2482                 { 0x00, 0xba00 },
2483                 { 0x04, 0xa800 },
2484                 { 0x04, 0xa000 },
2485
2486                 { 0x03, 0xff41 },
2487                 { 0x02, 0xdf20 },
2488                 { 0x01, 0x0140 },
2489                 { 0x00, 0x00bb },
2490                 { 0x04, 0xb800 },
2491                 { 0x04, 0xb000 },
2492
2493                 { 0x03, 0xdf41 },
2494                 { 0x02, 0xdc60 },
2495                 { 0x01, 0x6340 },
2496                 { 0x00, 0x007d },
2497                 { 0x04, 0xd800 },
2498                 { 0x04, 0xd000 },
2499
2500                 { 0x03, 0xdf01 },
2501                 { 0x02, 0xdf20 },
2502                 { 0x01, 0x100a },
2503                 { 0x00, 0xa0ff },
2504                 { 0x04, 0xf800 },
2505                 { 0x04, 0xf000 },
2506
2507                 { 0x1f, 0x0000 },
2508                 { 0x0b, 0x0000 },
2509                 { 0x00, 0x9200 }
2510         };
2511
2512         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2513 }
2514
2515 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2516 {
2517         static const struct phy_reg phy_reg_init[] = {
2518                 { 0x1f, 0x0002 },
2519                 { 0x01, 0x90d0 },
2520                 { 0x1f, 0x0000 }
2521         };
2522
2523         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2524 }
2525
2526 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2527 {
2528         struct pci_dev *pdev = tp->pci_dev;
2529
2530         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2531             (pdev->subsystem_device != 0xe000))
2532                 return;
2533
2534         rtl_writephy(tp, 0x1f, 0x0001);
2535         rtl_writephy(tp, 0x10, 0xf01b);
2536         rtl_writephy(tp, 0x1f, 0x0000);
2537 }
2538
2539 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2540 {
2541         static const struct phy_reg phy_reg_init[] = {
2542                 { 0x1f, 0x0001 },
2543                 { 0x04, 0x0000 },
2544                 { 0x03, 0x00a1 },
2545                 { 0x02, 0x0008 },
2546                 { 0x01, 0x0120 },
2547                 { 0x00, 0x1000 },
2548                 { 0x04, 0x0800 },
2549                 { 0x04, 0x9000 },
2550                 { 0x03, 0x802f },
2551                 { 0x02, 0x4f02 },
2552                 { 0x01, 0x0409 },
2553                 { 0x00, 0xf099 },
2554                 { 0x04, 0x9800 },
2555                 { 0x04, 0xa000 },
2556                 { 0x03, 0xdf01 },
2557                 { 0x02, 0xdf20 },
2558                 { 0x01, 0xff95 },
2559                 { 0x00, 0xba00 },
2560                 { 0x04, 0xa800 },
2561                 { 0x04, 0xf000 },
2562                 { 0x03, 0xdf01 },
2563                 { 0x02, 0xdf20 },
2564                 { 0x01, 0x101a },
2565                 { 0x00, 0xa0ff },
2566                 { 0x04, 0xf800 },
2567                 { 0x04, 0x0000 },
2568                 { 0x1f, 0x0000 },
2569
2570                 { 0x1f, 0x0001 },
2571                 { 0x10, 0xf41b },
2572                 { 0x14, 0xfb54 },
2573                 { 0x18, 0xf5c7 },
2574                 { 0x1f, 0x0000 },
2575
2576                 { 0x1f, 0x0001 },
2577                 { 0x17, 0x0cc0 },
2578                 { 0x1f, 0x0000 }
2579         };
2580
2581         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2582
2583         rtl8169scd_hw_phy_config_quirk(tp);
2584 }
2585
2586 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2587 {
2588         static const struct phy_reg phy_reg_init[] = {
2589                 { 0x1f, 0x0001 },
2590                 { 0x04, 0x0000 },
2591                 { 0x03, 0x00a1 },
2592                 { 0x02, 0x0008 },
2593                 { 0x01, 0x0120 },
2594                 { 0x00, 0x1000 },
2595                 { 0x04, 0x0800 },
2596                 { 0x04, 0x9000 },
2597                 { 0x03, 0x802f },
2598                 { 0x02, 0x4f02 },
2599                 { 0x01, 0x0409 },
2600                 { 0x00, 0xf099 },
2601                 { 0x04, 0x9800 },
2602                 { 0x04, 0xa000 },
2603                 { 0x03, 0xdf01 },
2604                 { 0x02, 0xdf20 },
2605                 { 0x01, 0xff95 },
2606                 { 0x00, 0xba00 },
2607                 { 0x04, 0xa800 },
2608                 { 0x04, 0xf000 },
2609                 { 0x03, 0xdf01 },
2610                 { 0x02, 0xdf20 },
2611                 { 0x01, 0x101a },
2612                 { 0x00, 0xa0ff },
2613                 { 0x04, 0xf800 },
2614                 { 0x04, 0x0000 },
2615                 { 0x1f, 0x0000 },
2616
2617                 { 0x1f, 0x0001 },
2618                 { 0x0b, 0x8480 },
2619                 { 0x1f, 0x0000 },
2620
2621                 { 0x1f, 0x0001 },
2622                 { 0x18, 0x67c7 },
2623                 { 0x04, 0x2000 },
2624                 { 0x03, 0x002f },
2625                 { 0x02, 0x4360 },
2626                 { 0x01, 0x0109 },
2627                 { 0x00, 0x3022 },
2628                 { 0x04, 0x2800 },
2629                 { 0x1f, 0x0000 },
2630
2631                 { 0x1f, 0x0001 },
2632                 { 0x17, 0x0cc0 },
2633                 { 0x1f, 0x0000 }
2634         };
2635
2636         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2637 }
2638
2639 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2640 {
2641         static const struct phy_reg phy_reg_init[] = {
2642                 { 0x10, 0xf41b },
2643                 { 0x1f, 0x0000 }
2644         };
2645
2646         rtl_writephy(tp, 0x1f, 0x0001);
2647         rtl_patchphy(tp, 0x16, 1 << 0);
2648
2649         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2650 }
2651
2652 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2653 {
2654         static const struct phy_reg phy_reg_init[] = {
2655                 { 0x1f, 0x0001 },
2656                 { 0x10, 0xf41b },
2657                 { 0x1f, 0x0000 }
2658         };
2659
2660         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2661 }
2662
2663 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2664 {
2665         static const struct phy_reg phy_reg_init[] = {
2666                 { 0x1f, 0x0000 },
2667                 { 0x1d, 0x0f00 },
2668                 { 0x1f, 0x0002 },
2669                 { 0x0c, 0x1ec8 },
2670                 { 0x1f, 0x0000 }
2671         };
2672
2673         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2674 }
2675
2676 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2677 {
2678         static const struct phy_reg phy_reg_init[] = {
2679                 { 0x1f, 0x0001 },
2680                 { 0x1d, 0x3d98 },
2681                 { 0x1f, 0x0000 }
2682         };
2683
2684         rtl_writephy(tp, 0x1f, 0x0000);
2685         rtl_patchphy(tp, 0x14, 1 << 5);
2686         rtl_patchphy(tp, 0x0d, 1 << 5);
2687
2688         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2689 }
2690
2691 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2692 {
2693         static const struct phy_reg phy_reg_init[] = {
2694                 { 0x1f, 0x0001 },
2695                 { 0x12, 0x2300 },
2696                 { 0x1f, 0x0002 },
2697                 { 0x00, 0x88d4 },
2698                 { 0x01, 0x82b1 },
2699                 { 0x03, 0x7002 },
2700                 { 0x08, 0x9e30 },
2701                 { 0x09, 0x01f0 },
2702                 { 0x0a, 0x5500 },
2703                 { 0x0c, 0x00c8 },
2704                 { 0x1f, 0x0003 },
2705                 { 0x12, 0xc096 },
2706                 { 0x16, 0x000a },
2707                 { 0x1f, 0x0000 },
2708                 { 0x1f, 0x0000 },
2709                 { 0x09, 0x2000 },
2710                 { 0x09, 0x0000 }
2711         };
2712
2713         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2714
2715         rtl_patchphy(tp, 0x14, 1 << 5);
2716         rtl_patchphy(tp, 0x0d, 1 << 5);
2717         rtl_writephy(tp, 0x1f, 0x0000);
2718 }
2719
2720 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2721 {
2722         static const struct phy_reg phy_reg_init[] = {
2723                 { 0x1f, 0x0001 },
2724                 { 0x12, 0x2300 },
2725                 { 0x03, 0x802f },
2726                 { 0x02, 0x4f02 },
2727                 { 0x01, 0x0409 },
2728                 { 0x00, 0xf099 },
2729                 { 0x04, 0x9800 },
2730                 { 0x04, 0x9000 },
2731                 { 0x1d, 0x3d98 },
2732                 { 0x1f, 0x0002 },
2733                 { 0x0c, 0x7eb8 },
2734                 { 0x06, 0x0761 },
2735                 { 0x1f, 0x0003 },
2736                 { 0x16, 0x0f0a },
2737                 { 0x1f, 0x0000 }
2738         };
2739
2740         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2741
2742         rtl_patchphy(tp, 0x16, 1 << 0);
2743         rtl_patchphy(tp, 0x14, 1 << 5);
2744         rtl_patchphy(tp, 0x0d, 1 << 5);
2745         rtl_writephy(tp, 0x1f, 0x0000);
2746 }
2747
2748 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2749 {
2750         static const struct phy_reg phy_reg_init[] = {
2751                 { 0x1f, 0x0001 },
2752                 { 0x12, 0x2300 },
2753                 { 0x1d, 0x3d98 },
2754                 { 0x1f, 0x0002 },
2755                 { 0x0c, 0x7eb8 },
2756                 { 0x06, 0x5461 },
2757                 { 0x1f, 0x0003 },
2758                 { 0x16, 0x0f0a },
2759                 { 0x1f, 0x0000 }
2760         };
2761
2762         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2763
2764         rtl_patchphy(tp, 0x16, 1 << 0);
2765         rtl_patchphy(tp, 0x14, 1 << 5);
2766         rtl_patchphy(tp, 0x0d, 1 << 5);
2767         rtl_writephy(tp, 0x1f, 0x0000);
2768 }
2769
2770 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2771 {
2772         rtl8168c_3_hw_phy_config(tp);
2773 }
2774
2775 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2776 {
2777         static const struct phy_reg phy_reg_init_0[] = {
2778                 /* Channel Estimation */
2779                 { 0x1f, 0x0001 },
2780                 { 0x06, 0x4064 },
2781                 { 0x07, 0x2863 },
2782                 { 0x08, 0x059c },
2783                 { 0x09, 0x26b4 },
2784                 { 0x0a, 0x6a19 },
2785                 { 0x0b, 0xdcc8 },
2786                 { 0x10, 0xf06d },
2787                 { 0x14, 0x7f68 },
2788                 { 0x18, 0x7fd9 },
2789                 { 0x1c, 0xf0ff },
2790                 { 0x1d, 0x3d9c },
2791                 { 0x1f, 0x0003 },
2792                 { 0x12, 0xf49f },
2793                 { 0x13, 0x070b },
2794                 { 0x1a, 0x05ad },
2795                 { 0x14, 0x94c0 },
2796
2797                 /*
2798                  * Tx Error Issue
2799                  * Enhance line driver power
2800                  */
2801                 { 0x1f, 0x0002 },
2802                 { 0x06, 0x5561 },
2803                 { 0x1f, 0x0005 },
2804                 { 0x05, 0x8332 },
2805                 { 0x06, 0x5561 },
2806
2807                 /*
2808                  * Can not link to 1Gbps with bad cable
2809                  * Decrease SNR threshold form 21.07dB to 19.04dB
2810                  */
2811                 { 0x1f, 0x0001 },
2812                 { 0x17, 0x0cc0 },
2813
2814                 { 0x1f, 0x0000 },
2815                 { 0x0d, 0xf880 }
2816         };
2817
2818         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2819
2820         /*
2821          * Rx Error Issue
2822          * Fine Tune Switching regulator parameter
2823          */
2824         rtl_writephy(tp, 0x1f, 0x0002);
2825         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2826         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2827
2828         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2829                 static const struct phy_reg phy_reg_init[] = {
2830                         { 0x1f, 0x0002 },
2831                         { 0x05, 0x669a },
2832                         { 0x1f, 0x0005 },
2833                         { 0x05, 0x8330 },
2834                         { 0x06, 0x669a },
2835                         { 0x1f, 0x0002 }
2836                 };
2837                 int val;
2838
2839                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2840
2841                 val = rtl_readphy(tp, 0x0d);
2842
2843                 if ((val & 0x00ff) != 0x006c) {
2844                         static const u32 set[] = {
2845                                 0x0065, 0x0066, 0x0067, 0x0068,
2846                                 0x0069, 0x006a, 0x006b, 0x006c
2847                         };
2848                         int i;
2849
2850                         rtl_writephy(tp, 0x1f, 0x0002);
2851
2852                         val &= 0xff00;
2853                         for (i = 0; i < ARRAY_SIZE(set); i++)
2854                                 rtl_writephy(tp, 0x0d, val | set[i]);
2855                 }
2856         } else {
2857                 static const struct phy_reg phy_reg_init[] = {
2858                         { 0x1f, 0x0002 },
2859                         { 0x05, 0x6662 },
2860                         { 0x1f, 0x0005 },
2861                         { 0x05, 0x8330 },
2862                         { 0x06, 0x6662 }
2863                 };
2864
2865                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2866         }
2867
2868         /* RSET couple improve */
2869         rtl_writephy(tp, 0x1f, 0x0002);
2870         rtl_patchphy(tp, 0x0d, 0x0300);
2871         rtl_patchphy(tp, 0x0f, 0x0010);
2872
2873         /* Fine tune PLL performance */
2874         rtl_writephy(tp, 0x1f, 0x0002);
2875         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2876         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2877
2878         rtl_writephy(tp, 0x1f, 0x0005);
2879         rtl_writephy(tp, 0x05, 0x001b);
2880
2881         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2882
2883         rtl_writephy(tp, 0x1f, 0x0000);
2884 }
2885
2886 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2887 {
2888         static const struct phy_reg phy_reg_init_0[] = {
2889                 /* Channel Estimation */
2890                 { 0x1f, 0x0001 },
2891                 { 0x06, 0x4064 },
2892                 { 0x07, 0x2863 },
2893                 { 0x08, 0x059c },
2894                 { 0x09, 0x26b4 },
2895                 { 0x0a, 0x6a19 },
2896                 { 0x0b, 0xdcc8 },
2897                 { 0x10, 0xf06d },
2898                 { 0x14, 0x7f68 },
2899                 { 0x18, 0x7fd9 },
2900                 { 0x1c, 0xf0ff },
2901                 { 0x1d, 0x3d9c },
2902                 { 0x1f, 0x0003 },
2903                 { 0x12, 0xf49f },
2904                 { 0x13, 0x070b },
2905                 { 0x1a, 0x05ad },
2906                 { 0x14, 0x94c0 },
2907
2908                 /*
2909                  * Tx Error Issue
2910                  * Enhance line driver power
2911                  */
2912                 { 0x1f, 0x0002 },
2913                 { 0x06, 0x5561 },
2914                 { 0x1f, 0x0005 },
2915                 { 0x05, 0x8332 },
2916                 { 0x06, 0x5561 },
2917
2918                 /*
2919                  * Can not link to 1Gbps with bad cable
2920                  * Decrease SNR threshold form 21.07dB to 19.04dB
2921                  */
2922                 { 0x1f, 0x0001 },
2923                 { 0x17, 0x0cc0 },
2924
2925                 { 0x1f, 0x0000 },
2926                 { 0x0d, 0xf880 }
2927         };
2928
2929         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2930
2931         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2932                 static const struct phy_reg phy_reg_init[] = {
2933                         { 0x1f, 0x0002 },
2934                         { 0x05, 0x669a },
2935                         { 0x1f, 0x0005 },
2936                         { 0x05, 0x8330 },
2937                         { 0x06, 0x669a },
2938
2939                         { 0x1f, 0x0002 }
2940                 };
2941                 int val;
2942
2943                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2944
2945                 val = rtl_readphy(tp, 0x0d);
2946                 if ((val & 0x00ff) != 0x006c) {
2947                         static const u32 set[] = {
2948                                 0x0065, 0x0066, 0x0067, 0x0068,
2949                                 0x0069, 0x006a, 0x006b, 0x006c
2950                         };
2951                         int i;
2952
2953                         rtl_writephy(tp, 0x1f, 0x0002);
2954
2955                         val &= 0xff00;
2956                         for (i = 0; i < ARRAY_SIZE(set); i++)
2957                                 rtl_writephy(tp, 0x0d, val | set[i]);
2958                 }
2959         } else {
2960                 static const struct phy_reg phy_reg_init[] = {
2961                         { 0x1f, 0x0002 },
2962                         { 0x05, 0x2642 },
2963                         { 0x1f, 0x0005 },
2964                         { 0x05, 0x8330 },
2965                         { 0x06, 0x2642 }
2966                 };
2967
2968                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2969         }
2970
2971         /* Fine tune PLL performance */
2972         rtl_writephy(tp, 0x1f, 0x0002);
2973         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2974         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2975
2976         /* Switching regulator Slew rate */
2977         rtl_writephy(tp, 0x1f, 0x0002);
2978         rtl_patchphy(tp, 0x0f, 0x0017);
2979
2980         rtl_writephy(tp, 0x1f, 0x0005);
2981         rtl_writephy(tp, 0x05, 0x001b);
2982
2983         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2984
2985         rtl_writephy(tp, 0x1f, 0x0000);
2986 }
2987
2988 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2989 {
2990         static const struct phy_reg phy_reg_init[] = {
2991                 { 0x1f, 0x0002 },
2992                 { 0x10, 0x0008 },
2993                 { 0x0d, 0x006c },
2994
2995                 { 0x1f, 0x0000 },
2996                 { 0x0d, 0xf880 },
2997
2998                 { 0x1f, 0x0001 },
2999                 { 0x17, 0x0cc0 },
3000
3001                 { 0x1f, 0x0001 },
3002                 { 0x0b, 0xa4d8 },
3003                 { 0x09, 0x281c },
3004                 { 0x07, 0x2883 },
3005                 { 0x0a, 0x6b35 },
3006                 { 0x1d, 0x3da4 },
3007                 { 0x1c, 0xeffd },
3008                 { 0x14, 0x7f52 },
3009                 { 0x18, 0x7fc6 },
3010                 { 0x08, 0x0601 },
3011                 { 0x06, 0x4063 },
3012                 { 0x10, 0xf074 },
3013                 { 0x1f, 0x0003 },
3014                 { 0x13, 0x0789 },
3015                 { 0x12, 0xf4bd },
3016                 { 0x1a, 0x04fd },
3017                 { 0x14, 0x84b0 },
3018                 { 0x1f, 0x0000 },
3019                 { 0x00, 0x9200 },
3020
3021                 { 0x1f, 0x0005 },
3022                 { 0x01, 0x0340 },
3023                 { 0x1f, 0x0001 },
3024                 { 0x04, 0x4000 },
3025                 { 0x03, 0x1d21 },
3026                 { 0x02, 0x0c32 },
3027                 { 0x01, 0x0200 },
3028                 { 0x00, 0x5554 },
3029                 { 0x04, 0x4800 },
3030                 { 0x04, 0x4000 },
3031                 { 0x04, 0xf000 },
3032                 { 0x03, 0xdf01 },
3033                 { 0x02, 0xdf20 },
3034                 { 0x01, 0x101a },
3035                 { 0x00, 0xa0ff },
3036                 { 0x04, 0xf800 },
3037                 { 0x04, 0xf000 },
3038                 { 0x1f, 0x0000 },
3039
3040                 { 0x1f, 0x0007 },
3041                 { 0x1e, 0x0023 },
3042                 { 0x16, 0x0000 },
3043                 { 0x1f, 0x0000 }
3044         };
3045
3046         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3047 }
3048
3049 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3050 {
3051         static const struct phy_reg phy_reg_init[] = {
3052                 { 0x1f, 0x0001 },
3053                 { 0x17, 0x0cc0 },
3054
3055                 { 0x1f, 0x0007 },
3056                 { 0x1e, 0x002d },
3057                 { 0x18, 0x0040 },
3058                 { 0x1f, 0x0000 }
3059         };
3060
3061         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3062         rtl_patchphy(tp, 0x0d, 1 << 5);
3063 }
3064
3065 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3066 {
3067         static const struct phy_reg phy_reg_init[] = {
3068                 /* Enable Delay cap */
3069                 { 0x1f, 0x0005 },
3070                 { 0x05, 0x8b80 },
3071                 { 0x06, 0xc896 },
3072                 { 0x1f, 0x0000 },
3073
3074                 /* Channel estimation fine tune */
3075                 { 0x1f, 0x0001 },
3076                 { 0x0b, 0x6c20 },
3077                 { 0x07, 0x2872 },
3078                 { 0x1c, 0xefff },
3079                 { 0x1f, 0x0003 },
3080                 { 0x14, 0x6420 },
3081                 { 0x1f, 0x0000 },
3082
3083                 /* Update PFM & 10M TX idle timer */
3084                 { 0x1f, 0x0007 },
3085                 { 0x1e, 0x002f },
3086                 { 0x15, 0x1919 },
3087                 { 0x1f, 0x0000 },
3088
3089                 { 0x1f, 0x0007 },
3090                 { 0x1e, 0x00ac },
3091                 { 0x18, 0x0006 },
3092                 { 0x1f, 0x0000 }
3093         };
3094
3095         rtl_apply_firmware(tp);
3096
3097         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3098
3099         /* DCO enable for 10M IDLE Power */
3100         rtl_writephy(tp, 0x1f, 0x0007);
3101         rtl_writephy(tp, 0x1e, 0x0023);
3102         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3103         rtl_writephy(tp, 0x1f, 0x0000);
3104
3105         /* For impedance matching */
3106         rtl_writephy(tp, 0x1f, 0x0002);
3107         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3108         rtl_writephy(tp, 0x1f, 0x0000);
3109
3110         /* PHY auto speed down */
3111         rtl_writephy(tp, 0x1f, 0x0007);
3112         rtl_writephy(tp, 0x1e, 0x002d);
3113         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3114         rtl_writephy(tp, 0x1f, 0x0000);
3115         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3116
3117         rtl_writephy(tp, 0x1f, 0x0005);
3118         rtl_writephy(tp, 0x05, 0x8b86);
3119         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3120         rtl_writephy(tp, 0x1f, 0x0000);
3121
3122         rtl_writephy(tp, 0x1f, 0x0005);
3123         rtl_writephy(tp, 0x05, 0x8b85);
3124         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3125         rtl_writephy(tp, 0x1f, 0x0007);
3126         rtl_writephy(tp, 0x1e, 0x0020);
3127         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3128         rtl_writephy(tp, 0x1f, 0x0006);
3129         rtl_writephy(tp, 0x00, 0x5a00);
3130         rtl_writephy(tp, 0x1f, 0x0000);
3131         rtl_writephy(tp, 0x0d, 0x0007);
3132         rtl_writephy(tp, 0x0e, 0x003c);
3133         rtl_writephy(tp, 0x0d, 0x4007);
3134         rtl_writephy(tp, 0x0e, 0x0000);
3135         rtl_writephy(tp, 0x0d, 0x0000);
3136 }
3137
3138 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3139 {
3140         const u16 w[] = {
3141                 addr[0] | (addr[1] << 8),
3142                 addr[2] | (addr[3] << 8),
3143                 addr[4] | (addr[5] << 8)
3144         };
3145         const struct exgmac_reg e[] = {
3146                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3147                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3148                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3149                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3150         };
3151
3152         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3153 }
3154
3155 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3156 {
3157         static const struct phy_reg phy_reg_init[] = {
3158                 /* Enable Delay cap */
3159                 { 0x1f, 0x0004 },
3160                 { 0x1f, 0x0007 },
3161                 { 0x1e, 0x00ac },
3162                 { 0x18, 0x0006 },
3163                 { 0x1f, 0x0002 },
3164                 { 0x1f, 0x0000 },
3165                 { 0x1f, 0x0000 },
3166
3167                 /* Channel estimation fine tune */
3168                 { 0x1f, 0x0003 },
3169                 { 0x09, 0xa20f },
3170                 { 0x1f, 0x0000 },
3171                 { 0x1f, 0x0000 },
3172
3173                 /* Green Setting */
3174                 { 0x1f, 0x0005 },
3175                 { 0x05, 0x8b5b },
3176                 { 0x06, 0x9222 },
3177                 { 0x05, 0x8b6d },
3178                 { 0x06, 0x8000 },
3179                 { 0x05, 0x8b76 },
3180                 { 0x06, 0x8000 },
3181                 { 0x1f, 0x0000 }
3182         };
3183
3184         rtl_apply_firmware(tp);
3185
3186         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3187
3188         /* For 4-corner performance improve */
3189         rtl_writephy(tp, 0x1f, 0x0005);
3190         rtl_writephy(tp, 0x05, 0x8b80);
3191         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3192         rtl_writephy(tp, 0x1f, 0x0000);
3193
3194         /* PHY auto speed down */
3195         rtl_writephy(tp, 0x1f, 0x0004);
3196         rtl_writephy(tp, 0x1f, 0x0007);
3197         rtl_writephy(tp, 0x1e, 0x002d);
3198         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3199         rtl_writephy(tp, 0x1f, 0x0002);
3200         rtl_writephy(tp, 0x1f, 0x0000);
3201         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3202
3203         /* improve 10M EEE waveform */
3204         rtl_writephy(tp, 0x1f, 0x0005);
3205         rtl_writephy(tp, 0x05, 0x8b86);
3206         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3207         rtl_writephy(tp, 0x1f, 0x0000);
3208
3209         /* Improve 2-pair detection performance */
3210         rtl_writephy(tp, 0x1f, 0x0005);
3211         rtl_writephy(tp, 0x05, 0x8b85);
3212         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3213         rtl_writephy(tp, 0x1f, 0x0000);
3214
3215         /* EEE setting */
3216         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3217         rtl_writephy(tp, 0x1f, 0x0005);
3218         rtl_writephy(tp, 0x05, 0x8b85);
3219         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3220         rtl_writephy(tp, 0x1f, 0x0004);
3221         rtl_writephy(tp, 0x1f, 0x0007);
3222         rtl_writephy(tp, 0x1e, 0x0020);
3223         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3224         rtl_writephy(tp, 0x1f, 0x0002);
3225         rtl_writephy(tp, 0x1f, 0x0000);
3226         rtl_writephy(tp, 0x0d, 0x0007);
3227         rtl_writephy(tp, 0x0e, 0x003c);
3228         rtl_writephy(tp, 0x0d, 0x4007);
3229         rtl_writephy(tp, 0x0e, 0x0006);
3230         rtl_writephy(tp, 0x0d, 0x0000);
3231
3232         /* Green feature */
3233         rtl_writephy(tp, 0x1f, 0x0003);
3234         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3235         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3236         rtl_writephy(tp, 0x1f, 0x0000);
3237         rtl_writephy(tp, 0x1f, 0x0005);
3238         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3239         rtl_writephy(tp, 0x1f, 0x0000);
3240
3241         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3242         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3243 }
3244
3245 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3246 {
3247         /* For 4-corner performance improve */
3248         rtl_writephy(tp, 0x1f, 0x0005);
3249         rtl_writephy(tp, 0x05, 0x8b80);
3250         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3251         rtl_writephy(tp, 0x1f, 0x0000);
3252
3253         /* PHY auto speed down */
3254         rtl_writephy(tp, 0x1f, 0x0007);
3255         rtl_writephy(tp, 0x1e, 0x002d);
3256         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3257         rtl_writephy(tp, 0x1f, 0x0000);
3258         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3259
3260         /* Improve 10M EEE waveform */
3261         rtl_writephy(tp, 0x1f, 0x0005);
3262         rtl_writephy(tp, 0x05, 0x8b86);
3263         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3264         rtl_writephy(tp, 0x1f, 0x0000);
3265 }
3266
3267 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3268 {
3269         static const struct phy_reg phy_reg_init[] = {
3270                 /* Channel estimation fine tune */
3271                 { 0x1f, 0x0003 },
3272                 { 0x09, 0xa20f },
3273                 { 0x1f, 0x0000 },
3274
3275                 /* Modify green table for giga & fnet */
3276                 { 0x1f, 0x0005 },
3277                 { 0x05, 0x8b55 },
3278                 { 0x06, 0x0000 },
3279                 { 0x05, 0x8b5e },
3280                 { 0x06, 0x0000 },
3281                 { 0x05, 0x8b67 },
3282                 { 0x06, 0x0000 },
3283                 { 0x05, 0x8b70 },
3284                 { 0x06, 0x0000 },
3285                 { 0x1f, 0x0000 },
3286                 { 0x1f, 0x0007 },
3287                 { 0x1e, 0x0078 },
3288                 { 0x17, 0x0000 },
3289                 { 0x19, 0x00fb },
3290                 { 0x1f, 0x0000 },
3291
3292                 /* Modify green table for 10M */
3293                 { 0x1f, 0x0005 },
3294                 { 0x05, 0x8b79 },
3295                 { 0x06, 0xaa00 },
3296                 { 0x1f, 0x0000 },
3297
3298                 /* Disable hiimpedance detection (RTCT) */
3299                 { 0x1f, 0x0003 },
3300                 { 0x01, 0x328a },
3301                 { 0x1f, 0x0000 }
3302         };
3303
3304         rtl_apply_firmware(tp);
3305
3306         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3307
3308         rtl8168f_hw_phy_config(tp);
3309
3310         /* Improve 2-pair detection performance */
3311         rtl_writephy(tp, 0x1f, 0x0005);
3312         rtl_writephy(tp, 0x05, 0x8b85);
3313         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3314         rtl_writephy(tp, 0x1f, 0x0000);
3315 }
3316
3317 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3318 {
3319         rtl_apply_firmware(tp);
3320
3321         rtl8168f_hw_phy_config(tp);
3322 }
3323
3324 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3325 {
3326         static const struct phy_reg phy_reg_init[] = {
3327                 /* Channel estimation fine tune */
3328                 { 0x1f, 0x0003 },
3329                 { 0x09, 0xa20f },
3330                 { 0x1f, 0x0000 },
3331
3332                 /* Modify green table for giga & fnet */
3333                 { 0x1f, 0x0005 },
3334                 { 0x05, 0x8b55 },
3335                 { 0x06, 0x0000 },
3336                 { 0x05, 0x8b5e },
3337                 { 0x06, 0x0000 },
3338                 { 0x05, 0x8b67 },
3339                 { 0x06, 0x0000 },
3340                 { 0x05, 0x8b70 },
3341                 { 0x06, 0x0000 },
3342                 { 0x1f, 0x0000 },
3343                 { 0x1f, 0x0007 },
3344                 { 0x1e, 0x0078 },
3345                 { 0x17, 0x0000 },
3346                 { 0x19, 0x00aa },
3347                 { 0x1f, 0x0000 },
3348
3349                 /* Modify green table for 10M */
3350                 { 0x1f, 0x0005 },
3351                 { 0x05, 0x8b79 },
3352                 { 0x06, 0xaa00 },
3353                 { 0x1f, 0x0000 },
3354
3355                 /* Disable hiimpedance detection (RTCT) */
3356                 { 0x1f, 0x0003 },
3357                 { 0x01, 0x328a },
3358                 { 0x1f, 0x0000 }
3359         };
3360
3361
3362         rtl_apply_firmware(tp);
3363
3364         rtl8168f_hw_phy_config(tp);
3365
3366         /* Improve 2-pair detection performance */
3367         rtl_writephy(tp, 0x1f, 0x0005);
3368         rtl_writephy(tp, 0x05, 0x8b85);
3369         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3370         rtl_writephy(tp, 0x1f, 0x0000);
3371
3372         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3373
3374         /* Modify green table for giga */
3375         rtl_writephy(tp, 0x1f, 0x0005);
3376         rtl_writephy(tp, 0x05, 0x8b54);
3377         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3378         rtl_writephy(tp, 0x05, 0x8b5d);
3379         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3380         rtl_writephy(tp, 0x05, 0x8a7c);
3381         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3382         rtl_writephy(tp, 0x05, 0x8a7f);
3383         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3384         rtl_writephy(tp, 0x05, 0x8a82);
3385         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3386         rtl_writephy(tp, 0x05, 0x8a85);
3387         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3388         rtl_writephy(tp, 0x05, 0x8a88);
3389         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3390         rtl_writephy(tp, 0x1f, 0x0000);
3391
3392         /* uc same-seed solution */
3393         rtl_writephy(tp, 0x1f, 0x0005);
3394         rtl_writephy(tp, 0x05, 0x8b85);
3395         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3396         rtl_writephy(tp, 0x1f, 0x0000);
3397
3398         /* eee setting */
3399         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3400         rtl_writephy(tp, 0x1f, 0x0005);
3401         rtl_writephy(tp, 0x05, 0x8b85);
3402         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3403         rtl_writephy(tp, 0x1f, 0x0004);
3404         rtl_writephy(tp, 0x1f, 0x0007);
3405         rtl_writephy(tp, 0x1e, 0x0020);
3406         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3407         rtl_writephy(tp, 0x1f, 0x0000);
3408         rtl_writephy(tp, 0x0d, 0x0007);
3409         rtl_writephy(tp, 0x0e, 0x003c);
3410         rtl_writephy(tp, 0x0d, 0x4007);
3411         rtl_writephy(tp, 0x0e, 0x0000);
3412         rtl_writephy(tp, 0x0d, 0x0000);
3413
3414         /* Green feature */
3415         rtl_writephy(tp, 0x1f, 0x0003);
3416         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3417         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3418         rtl_writephy(tp, 0x1f, 0x0000);
3419 }
3420
3421 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3422 {
3423         rtl_apply_firmware(tp);
3424
3425         rtl_writephy(tp, 0x1f, 0x0a46);
3426         if (rtl_readphy(tp, 0x10) & 0x0100) {
3427                 rtl_writephy(tp, 0x1f, 0x0bcc);
3428                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3429         } else {
3430                 rtl_writephy(tp, 0x1f, 0x0bcc);
3431                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3432         }
3433
3434         rtl_writephy(tp, 0x1f, 0x0a46);
3435         if (rtl_readphy(tp, 0x13) & 0x0100) {
3436                 rtl_writephy(tp, 0x1f, 0x0c41);
3437                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3438         } else {
3439                 rtl_writephy(tp, 0x1f, 0x0c41);
3440                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3441         }
3442
3443         /* Enable PHY auto speed down */
3444         rtl_writephy(tp, 0x1f, 0x0a44);
3445         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3446
3447         rtl_writephy(tp, 0x1f, 0x0bcc);
3448         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3449         rtl_writephy(tp, 0x1f, 0x0a44);
3450         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3451         rtl_writephy(tp, 0x1f, 0x0a43);
3452         rtl_writephy(tp, 0x13, 0x8084);
3453         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3454         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3455
3456         /* EEE auto-fallback function */
3457         rtl_writephy(tp, 0x1f, 0x0a4b);
3458         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3459
3460         /* Enable UC LPF tune function */
3461         rtl_writephy(tp, 0x1f, 0x0a43);
3462         rtl_writephy(tp, 0x13, 0x8012);
3463         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3464
3465         rtl_writephy(tp, 0x1f, 0x0c42);
3466         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3467
3468         /* Improve SWR Efficiency */
3469         rtl_writephy(tp, 0x1f, 0x0bcd);
3470         rtl_writephy(tp, 0x14, 0x5065);
3471         rtl_writephy(tp, 0x14, 0xd065);
3472         rtl_writephy(tp, 0x1f, 0x0bc8);
3473         rtl_writephy(tp, 0x11, 0x5655);
3474         rtl_writephy(tp, 0x1f, 0x0bcd);
3475         rtl_writephy(tp, 0x14, 0x1065);
3476         rtl_writephy(tp, 0x14, 0x9065);
3477         rtl_writephy(tp, 0x14, 0x1065);
3478
3479         /* Check ALDPS bit, disable it if enabled */
3480         rtl_writephy(tp, 0x1f, 0x0a43);
3481         if (rtl_readphy(tp, 0x10) & 0x0004)
3482                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3483
3484         rtl_writephy(tp, 0x1f, 0x0000);
3485 }
3486
3487 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3488 {
3489         rtl_apply_firmware(tp);
3490 }
3491
3492 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3493 {
3494         u16 dout_tapbin;
3495         u32 data;
3496
3497         rtl_apply_firmware(tp);
3498
3499         /* CHN EST parameters adjust - giga master */
3500         rtl_writephy(tp, 0x1f, 0x0a43);
3501         rtl_writephy(tp, 0x13, 0x809b);
3502         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3503         rtl_writephy(tp, 0x13, 0x80a2);
3504         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3505         rtl_writephy(tp, 0x13, 0x80a4);
3506         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3507         rtl_writephy(tp, 0x13, 0x809c);
3508         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3509         rtl_writephy(tp, 0x1f, 0x0000);
3510
3511         /* CHN EST parameters adjust - giga slave */
3512         rtl_writephy(tp, 0x1f, 0x0a43);
3513         rtl_writephy(tp, 0x13, 0x80ad);
3514         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3515         rtl_writephy(tp, 0x13, 0x80b4);
3516         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3517         rtl_writephy(tp, 0x13, 0x80ac);
3518         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3519         rtl_writephy(tp, 0x1f, 0x0000);
3520
3521         /* CHN EST parameters adjust - fnet */
3522         rtl_writephy(tp, 0x1f, 0x0a43);
3523         rtl_writephy(tp, 0x13, 0x808e);
3524         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3525         rtl_writephy(tp, 0x13, 0x8090);
3526         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3527         rtl_writephy(tp, 0x13, 0x8092);
3528         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3529         rtl_writephy(tp, 0x1f, 0x0000);
3530
3531         /* enable R-tune & PGA-retune function */
3532         dout_tapbin = 0;
3533         rtl_writephy(tp, 0x1f, 0x0a46);
3534         data = rtl_readphy(tp, 0x13);
3535         data &= 3;
3536         data <<= 2;
3537         dout_tapbin |= data;
3538         data = rtl_readphy(tp, 0x12);
3539         data &= 0xc000;
3540         data >>= 14;
3541         dout_tapbin |= data;
3542         dout_tapbin = ~(dout_tapbin^0x08);
3543         dout_tapbin <<= 12;
3544         dout_tapbin &= 0xf000;
3545         rtl_writephy(tp, 0x1f, 0x0a43);
3546         rtl_writephy(tp, 0x13, 0x827a);
3547         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3548         rtl_writephy(tp, 0x13, 0x827b);
3549         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3550         rtl_writephy(tp, 0x13, 0x827c);
3551         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3552         rtl_writephy(tp, 0x13, 0x827d);
3553         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3554
3555         rtl_writephy(tp, 0x1f, 0x0a43);
3556         rtl_writephy(tp, 0x13, 0x0811);
3557         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3558         rtl_writephy(tp, 0x1f, 0x0a42);
3559         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3560         rtl_writephy(tp, 0x1f, 0x0000);
3561
3562         /* enable GPHY 10M */
3563         rtl_writephy(tp, 0x1f, 0x0a44);
3564         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3565         rtl_writephy(tp, 0x1f, 0x0000);
3566
3567         /* SAR ADC performance */
3568         rtl_writephy(tp, 0x1f, 0x0bca);
3569         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3570         rtl_writephy(tp, 0x1f, 0x0000);
3571
3572         rtl_writephy(tp, 0x1f, 0x0a43);
3573         rtl_writephy(tp, 0x13, 0x803f);
3574         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3575         rtl_writephy(tp, 0x13, 0x8047);
3576         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3577         rtl_writephy(tp, 0x13, 0x804f);
3578         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3579         rtl_writephy(tp, 0x13, 0x8057);
3580         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3581         rtl_writephy(tp, 0x13, 0x805f);
3582         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3583         rtl_writephy(tp, 0x13, 0x8067);
3584         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3585         rtl_writephy(tp, 0x13, 0x806f);
3586         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3587         rtl_writephy(tp, 0x1f, 0x0000);
3588
3589         /* disable phy pfm mode */
3590         rtl_writephy(tp, 0x1f, 0x0a44);
3591         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3592         rtl_writephy(tp, 0x1f, 0x0000);
3593
3594         /* Check ALDPS bit, disable it if enabled */
3595         rtl_writephy(tp, 0x1f, 0x0a43);
3596         if (rtl_readphy(tp, 0x10) & 0x0004)
3597                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3598
3599         rtl_writephy(tp, 0x1f, 0x0000);
3600 }
3601
3602 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3603 {
3604         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3605         u16 rlen;
3606         u32 data;
3607
3608         rtl_apply_firmware(tp);
3609
3610         /* CHIN EST parameter update */
3611         rtl_writephy(tp, 0x1f, 0x0a43);
3612         rtl_writephy(tp, 0x13, 0x808a);
3613         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3614         rtl_writephy(tp, 0x1f, 0x0000);
3615
3616         /* enable R-tune & PGA-retune function */
3617         rtl_writephy(tp, 0x1f, 0x0a43);
3618         rtl_writephy(tp, 0x13, 0x0811);
3619         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3620         rtl_writephy(tp, 0x1f, 0x0a42);
3621         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3622         rtl_writephy(tp, 0x1f, 0x0000);
3623
3624         /* enable GPHY 10M */
3625         rtl_writephy(tp, 0x1f, 0x0a44);
3626         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3627         rtl_writephy(tp, 0x1f, 0x0000);
3628
3629         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3630         data = r8168_mac_ocp_read(tp, 0xdd02);
3631         ioffset_p3 = ((data & 0x80)>>7);
3632         ioffset_p3 <<= 3;
3633
3634         data = r8168_mac_ocp_read(tp, 0xdd00);
3635         ioffset_p3 |= ((data & (0xe000))>>13);
3636         ioffset_p2 = ((data & (0x1e00))>>9);
3637         ioffset_p1 = ((data & (0x01e0))>>5);
3638         ioffset_p0 = ((data & 0x0010)>>4);
3639         ioffset_p0 <<= 3;
3640         ioffset_p0 |= (data & (0x07));
3641         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3642
3643         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3644             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3645                 rtl_writephy(tp, 0x1f, 0x0bcf);
3646                 rtl_writephy(tp, 0x16, data);
3647                 rtl_writephy(tp, 0x1f, 0x0000);
3648         }
3649
3650         /* Modify rlen (TX LPF corner frequency) level */
3651         rtl_writephy(tp, 0x1f, 0x0bcd);
3652         data = rtl_readphy(tp, 0x16);
3653         data &= 0x000f;
3654         rlen = 0;
3655         if (data > 3)
3656                 rlen = data - 3;
3657         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3658         rtl_writephy(tp, 0x17, data);
3659         rtl_writephy(tp, 0x1f, 0x0bcd);
3660         rtl_writephy(tp, 0x1f, 0x0000);
3661
3662         /* disable phy pfm mode */
3663         rtl_writephy(tp, 0x1f, 0x0a44);
3664         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3665         rtl_writephy(tp, 0x1f, 0x0000);
3666
3667         /* Check ALDPS bit, disable it if enabled */
3668         rtl_writephy(tp, 0x1f, 0x0a43);
3669         if (rtl_readphy(tp, 0x10) & 0x0004)
3670                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3671
3672         rtl_writephy(tp, 0x1f, 0x0000);
3673 }
3674
3675 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3676 {
3677         /* Enable PHY auto speed down */
3678         rtl_writephy(tp, 0x1f, 0x0a44);
3679         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3680         rtl_writephy(tp, 0x1f, 0x0000);
3681
3682         /* patch 10M & ALDPS */
3683         rtl_writephy(tp, 0x1f, 0x0bcc);
3684         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3685         rtl_writephy(tp, 0x1f, 0x0a44);
3686         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3687         rtl_writephy(tp, 0x1f, 0x0a43);
3688         rtl_writephy(tp, 0x13, 0x8084);
3689         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3690         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3691         rtl_writephy(tp, 0x1f, 0x0000);
3692
3693         /* Enable EEE auto-fallback function */
3694         rtl_writephy(tp, 0x1f, 0x0a4b);
3695         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3696         rtl_writephy(tp, 0x1f, 0x0000);
3697
3698         /* Enable UC LPF tune function */
3699         rtl_writephy(tp, 0x1f, 0x0a43);
3700         rtl_writephy(tp, 0x13, 0x8012);
3701         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3702         rtl_writephy(tp, 0x1f, 0x0000);
3703
3704         /* set rg_sel_sdm_rate */
3705         rtl_writephy(tp, 0x1f, 0x0c42);
3706         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3707         rtl_writephy(tp, 0x1f, 0x0000);
3708
3709         /* Check ALDPS bit, disable it if enabled */
3710         rtl_writephy(tp, 0x1f, 0x0a43);
3711         if (rtl_readphy(tp, 0x10) & 0x0004)
3712                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3713
3714         rtl_writephy(tp, 0x1f, 0x0000);
3715 }
3716
3717 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3718 {
3719         /* patch 10M & ALDPS */
3720         rtl_writephy(tp, 0x1f, 0x0bcc);
3721         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3722         rtl_writephy(tp, 0x1f, 0x0a44);
3723         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3724         rtl_writephy(tp, 0x1f, 0x0a43);
3725         rtl_writephy(tp, 0x13, 0x8084);
3726         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3727         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3728         rtl_writephy(tp, 0x1f, 0x0000);
3729
3730         /* Enable UC LPF tune function */
3731         rtl_writephy(tp, 0x1f, 0x0a43);
3732         rtl_writephy(tp, 0x13, 0x8012);
3733         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3734         rtl_writephy(tp, 0x1f, 0x0000);
3735
3736         /* Set rg_sel_sdm_rate */
3737         rtl_writephy(tp, 0x1f, 0x0c42);
3738         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3739         rtl_writephy(tp, 0x1f, 0x0000);
3740
3741         /* Channel estimation parameters */
3742         rtl_writephy(tp, 0x1f, 0x0a43);
3743         rtl_writephy(tp, 0x13, 0x80f3);
3744         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3745         rtl_writephy(tp, 0x13, 0x80f0);
3746         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3747         rtl_writephy(tp, 0x13, 0x80ef);
3748         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3749         rtl_writephy(tp, 0x13, 0x80f6);
3750         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3751         rtl_writephy(tp, 0x13, 0x80ec);
3752         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3753         rtl_writephy(tp, 0x13, 0x80ed);
3754         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3755         rtl_writephy(tp, 0x13, 0x80f2);
3756         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3757         rtl_writephy(tp, 0x13, 0x80f4);
3758         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3759         rtl_writephy(tp, 0x1f, 0x0a43);
3760         rtl_writephy(tp, 0x13, 0x8110);
3761         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3762         rtl_writephy(tp, 0x13, 0x810f);
3763         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3764         rtl_writephy(tp, 0x13, 0x8111);
3765         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3766         rtl_writephy(tp, 0x13, 0x8113);
3767         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3768         rtl_writephy(tp, 0x13, 0x8115);
3769         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3770         rtl_writephy(tp, 0x13, 0x810e);
3771         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3772         rtl_writephy(tp, 0x13, 0x810c);
3773         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3774         rtl_writephy(tp, 0x13, 0x810b);
3775         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3776         rtl_writephy(tp, 0x1f, 0x0a43);
3777         rtl_writephy(tp, 0x13, 0x80d1);
3778         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3779         rtl_writephy(tp, 0x13, 0x80cd);
3780         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3781         rtl_writephy(tp, 0x13, 0x80d3);
3782         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3783         rtl_writephy(tp, 0x13, 0x80d5);
3784         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3785         rtl_writephy(tp, 0x13, 0x80d7);
3786         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3787
3788         /* Force PWM-mode */
3789         rtl_writephy(tp, 0x1f, 0x0bcd);
3790         rtl_writephy(tp, 0x14, 0x5065);
3791         rtl_writephy(tp, 0x14, 0xd065);
3792         rtl_writephy(tp, 0x1f, 0x0bc8);
3793         rtl_writephy(tp, 0x12, 0x00ed);
3794         rtl_writephy(tp, 0x1f, 0x0bcd);
3795         rtl_writephy(tp, 0x14, 0x1065);
3796         rtl_writephy(tp, 0x14, 0x9065);
3797         rtl_writephy(tp, 0x14, 0x1065);
3798         rtl_writephy(tp, 0x1f, 0x0000);
3799
3800         /* Check ALDPS bit, disable it if enabled */
3801         rtl_writephy(tp, 0x1f, 0x0a43);
3802         if (rtl_readphy(tp, 0x10) & 0x0004)
3803                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3804
3805         rtl_writephy(tp, 0x1f, 0x0000);
3806 }
3807
3808 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3809 {
3810         static const struct phy_reg phy_reg_init[] = {
3811                 { 0x1f, 0x0003 },
3812                 { 0x08, 0x441d },
3813                 { 0x01, 0x9100 },
3814                 { 0x1f, 0x0000 }
3815         };
3816
3817         rtl_writephy(tp, 0x1f, 0x0000);
3818         rtl_patchphy(tp, 0x11, 1 << 12);
3819         rtl_patchphy(tp, 0x19, 1 << 13);
3820         rtl_patchphy(tp, 0x10, 1 << 15);
3821
3822         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3823 }
3824
3825 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3826 {
3827         static const struct phy_reg phy_reg_init[] = {
3828                 { 0x1f, 0x0005 },
3829                 { 0x1a, 0x0000 },
3830                 { 0x1f, 0x0000 },
3831
3832                 { 0x1f, 0x0004 },
3833                 { 0x1c, 0x0000 },
3834                 { 0x1f, 0x0000 },
3835
3836                 { 0x1f, 0x0001 },
3837                 { 0x15, 0x7701 },
3838                 { 0x1f, 0x0000 }
3839         };
3840
3841         /* Disable ALDPS before ram code */
3842         rtl_writephy(tp, 0x1f, 0x0000);
3843         rtl_writephy(tp, 0x18, 0x0310);
3844         msleep(100);
3845
3846         rtl_apply_firmware(tp);
3847
3848         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3849 }
3850
3851 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3852 {
3853         /* Disable ALDPS before setting firmware */
3854         rtl_writephy(tp, 0x1f, 0x0000);
3855         rtl_writephy(tp, 0x18, 0x0310);
3856         msleep(20);
3857
3858         rtl_apply_firmware(tp);
3859
3860         /* EEE setting */
3861         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3862         rtl_writephy(tp, 0x1f, 0x0004);
3863         rtl_writephy(tp, 0x10, 0x401f);
3864         rtl_writephy(tp, 0x19, 0x7030);
3865         rtl_writephy(tp, 0x1f, 0x0000);
3866 }
3867
3868 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3869 {
3870         static const struct phy_reg phy_reg_init[] = {
3871                 { 0x1f, 0x0004 },
3872                 { 0x10, 0xc07f },
3873                 { 0x19, 0x7030 },
3874                 { 0x1f, 0x0000 }
3875         };
3876
3877         /* Disable ALDPS before ram code */
3878         rtl_writephy(tp, 0x1f, 0x0000);
3879         rtl_writephy(tp, 0x18, 0x0310);
3880         msleep(100);
3881
3882         rtl_apply_firmware(tp);
3883
3884         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3885         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3886
3887         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3888 }
3889
3890 static void rtl_hw_phy_config(struct net_device *dev)
3891 {
3892         struct rtl8169_private *tp = netdev_priv(dev);
3893
3894         switch (tp->mac_version) {
3895         case RTL_GIGA_MAC_VER_01:
3896                 break;
3897         case RTL_GIGA_MAC_VER_02:
3898         case RTL_GIGA_MAC_VER_03:
3899                 rtl8169s_hw_phy_config(tp);
3900                 break;
3901         case RTL_GIGA_MAC_VER_04:
3902                 rtl8169sb_hw_phy_config(tp);
3903                 break;
3904         case RTL_GIGA_MAC_VER_05:
3905                 rtl8169scd_hw_phy_config(tp);
3906                 break;
3907         case RTL_GIGA_MAC_VER_06:
3908                 rtl8169sce_hw_phy_config(tp);
3909                 break;
3910         case RTL_GIGA_MAC_VER_07:
3911         case RTL_GIGA_MAC_VER_08:
3912         case RTL_GIGA_MAC_VER_09:
3913                 rtl8102e_hw_phy_config(tp);
3914                 break;
3915         case RTL_GIGA_MAC_VER_11:
3916                 rtl8168bb_hw_phy_config(tp);
3917                 break;
3918         case RTL_GIGA_MAC_VER_12:
3919                 rtl8168bef_hw_phy_config(tp);
3920                 break;
3921         case RTL_GIGA_MAC_VER_17:
3922                 rtl8168bef_hw_phy_config(tp);
3923                 break;
3924         case RTL_GIGA_MAC_VER_18:
3925                 rtl8168cp_1_hw_phy_config(tp);
3926                 break;
3927         case RTL_GIGA_MAC_VER_19:
3928                 rtl8168c_1_hw_phy_config(tp);
3929                 break;
3930         case RTL_GIGA_MAC_VER_20:
3931                 rtl8168c_2_hw_phy_config(tp);
3932                 break;
3933         case RTL_GIGA_MAC_VER_21:
3934                 rtl8168c_3_hw_phy_config(tp);
3935                 break;
3936         case RTL_GIGA_MAC_VER_22:
3937                 rtl8168c_4_hw_phy_config(tp);
3938                 break;
3939         case RTL_GIGA_MAC_VER_23:
3940         case RTL_GIGA_MAC_VER_24:
3941                 rtl8168cp_2_hw_phy_config(tp);
3942                 break;
3943         case RTL_GIGA_MAC_VER_25:
3944                 rtl8168d_1_hw_phy_config(tp);
3945                 break;
3946         case RTL_GIGA_MAC_VER_26:
3947                 rtl8168d_2_hw_phy_config(tp);
3948                 break;
3949         case RTL_GIGA_MAC_VER_27:
3950                 rtl8168d_3_hw_phy_config(tp);
3951                 break;
3952         case RTL_GIGA_MAC_VER_28:
3953                 rtl8168d_4_hw_phy_config(tp);
3954                 break;
3955         case RTL_GIGA_MAC_VER_29:
3956         case RTL_GIGA_MAC_VER_30:
3957                 rtl8105e_hw_phy_config(tp);
3958                 break;
3959         case RTL_GIGA_MAC_VER_31:
3960                 /* None. */
3961                 break;
3962         case RTL_GIGA_MAC_VER_32:
3963         case RTL_GIGA_MAC_VER_33:
3964                 rtl8168e_1_hw_phy_config(tp);
3965                 break;
3966         case RTL_GIGA_MAC_VER_34:
3967                 rtl8168e_2_hw_phy_config(tp);
3968                 break;
3969         case RTL_GIGA_MAC_VER_35:
3970                 rtl8168f_1_hw_phy_config(tp);
3971                 break;
3972         case RTL_GIGA_MAC_VER_36:
3973                 rtl8168f_2_hw_phy_config(tp);
3974                 break;
3975
3976         case RTL_GIGA_MAC_VER_37:
3977                 rtl8402_hw_phy_config(tp);
3978                 break;
3979
3980         case RTL_GIGA_MAC_VER_38:
3981                 rtl8411_hw_phy_config(tp);
3982                 break;
3983
3984         case RTL_GIGA_MAC_VER_39:
3985                 rtl8106e_hw_phy_config(tp);
3986                 break;
3987
3988         case RTL_GIGA_MAC_VER_40:
3989                 rtl8168g_1_hw_phy_config(tp);
3990                 break;
3991         case RTL_GIGA_MAC_VER_42:
3992         case RTL_GIGA_MAC_VER_43:
3993         case RTL_GIGA_MAC_VER_44:
3994                 rtl8168g_2_hw_phy_config(tp);
3995                 break;
3996         case RTL_GIGA_MAC_VER_45:
3997         case RTL_GIGA_MAC_VER_47:
3998                 rtl8168h_1_hw_phy_config(tp);
3999                 break;
4000         case RTL_GIGA_MAC_VER_46:
4001         case RTL_GIGA_MAC_VER_48:
4002                 rtl8168h_2_hw_phy_config(tp);
4003                 break;
4004
4005         case RTL_GIGA_MAC_VER_49:
4006                 rtl8168ep_1_hw_phy_config(tp);
4007                 break;
4008         case RTL_GIGA_MAC_VER_50:
4009         case RTL_GIGA_MAC_VER_51:
4010                 rtl8168ep_2_hw_phy_config(tp);
4011                 break;
4012
4013         case RTL_GIGA_MAC_VER_41:
4014         default:
4015                 break;
4016         }
4017 }
4018
4019 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4020 {
4021         if (!test_and_set_bit(flag, tp->wk.flags))
4022                 schedule_work(&tp->wk.work);
4023 }
4024
4025 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4026 {
4027         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4028                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4029 }
4030
4031 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4032 {
4033         rtl_hw_phy_config(dev);
4034
4035         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4036                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4037                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4038                 netif_dbg(tp, drv, dev,
4039                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4040                 RTL_W8(tp, 0x82, 0x01);
4041         }
4042
4043         /* We may have called phy_speed_down before */
4044         phy_speed_up(dev->phydev);
4045
4046         genphy_soft_reset(dev->phydev);
4047
4048         /* It was reported that several chips end up with 10MBit/Half on a
4049          * 1GBit link after resuming from S3. For whatever reason the PHY on
4050          * these chips doesn't properly start a renegotiation when soft-reset.
4051          * Explicitly requesting a renegotiation fixes this.
4052          */
4053         if (dev->phydev->autoneg == AUTONEG_ENABLE)
4054                 phy_restart_aneg(dev->phydev);
4055 }
4056
4057 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4058 {
4059         rtl_lock_work(tp);
4060
4061         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4062
4063         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4064         RTL_R32(tp, MAC4);
4065
4066         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4067         RTL_R32(tp, MAC0);
4068
4069         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4070                 rtl_rar_exgmac_set(tp, addr);
4071
4072         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4073
4074         rtl_unlock_work(tp);
4075 }
4076
4077 static int rtl_set_mac_address(struct net_device *dev, void *p)
4078 {
4079         struct rtl8169_private *tp = netdev_priv(dev);
4080         struct device *d = tp_to_dev(tp);
4081         int ret;
4082
4083         ret = eth_mac_addr(dev, p);
4084         if (ret)
4085                 return ret;
4086
4087         pm_runtime_get_noresume(d);
4088
4089         if (pm_runtime_active(d))
4090                 rtl_rar_set(tp, dev->dev_addr);
4091
4092         pm_runtime_put_noidle(d);
4093
4094         return 0;
4095 }
4096
4097 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4098 {
4099         if (!netif_running(dev))
4100                 return -ENODEV;
4101
4102         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4103 }
4104
4105 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4106 {
4107         struct mdio_ops *ops = &tp->mdio_ops;
4108
4109         switch (tp->mac_version) {
4110         case RTL_GIGA_MAC_VER_27:
4111                 ops->write      = r8168dp_1_mdio_write;
4112                 ops->read       = r8168dp_1_mdio_read;
4113                 break;
4114         case RTL_GIGA_MAC_VER_28:
4115         case RTL_GIGA_MAC_VER_31:
4116                 ops->write      = r8168dp_2_mdio_write;
4117                 ops->read       = r8168dp_2_mdio_read;
4118                 break;
4119         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4120                 ops->write      = r8168g_mdio_write;
4121                 ops->read       = r8168g_mdio_read;
4122                 break;
4123         default:
4124                 ops->write      = r8169_mdio_write;
4125                 ops->read       = r8169_mdio_read;
4126                 break;
4127         }
4128 }
4129
4130 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4131 {
4132         switch (tp->mac_version) {
4133         case RTL_GIGA_MAC_VER_25:
4134         case RTL_GIGA_MAC_VER_26:
4135         case RTL_GIGA_MAC_VER_29:
4136         case RTL_GIGA_MAC_VER_30:
4137         case RTL_GIGA_MAC_VER_32:
4138         case RTL_GIGA_MAC_VER_33:
4139         case RTL_GIGA_MAC_VER_34:
4140         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4141                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4142                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4143                 break;
4144         default:
4145                 break;
4146         }
4147 }
4148
4149 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4150 {
4151         struct phy_device *phydev;
4152
4153         if (!__rtl8169_get_wol(tp))
4154                 return false;
4155
4156         /* phydev may not be attached to netdevice */
4157         phydev = mdiobus_get_phy(tp->mii_bus, 0);
4158
4159         phy_speed_down(phydev, false);
4160         rtl_wol_suspend_quirk(tp);
4161
4162         return true;
4163 }
4164
4165 static void r8168_pll_power_down(struct rtl8169_private *tp)
4166 {
4167         if (r8168_check_dash(tp))
4168                 return;
4169
4170         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4171             tp->mac_version == RTL_GIGA_MAC_VER_33)
4172                 rtl_ephy_write(tp, 0x19, 0xff64);
4173
4174         if (rtl_wol_pll_power_down(tp))
4175                 return;
4176
4177         switch (tp->mac_version) {
4178         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4179         case RTL_GIGA_MAC_VER_37:
4180         case RTL_GIGA_MAC_VER_39:
4181         case RTL_GIGA_MAC_VER_43:
4182         case RTL_GIGA_MAC_VER_44:
4183         case RTL_GIGA_MAC_VER_45:
4184         case RTL_GIGA_MAC_VER_46:
4185         case RTL_GIGA_MAC_VER_47:
4186         case RTL_GIGA_MAC_VER_48:
4187         case RTL_GIGA_MAC_VER_50:
4188         case RTL_GIGA_MAC_VER_51:
4189                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4190                 break;
4191         case RTL_GIGA_MAC_VER_40:
4192         case RTL_GIGA_MAC_VER_41:
4193         case RTL_GIGA_MAC_VER_49:
4194                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4195                              0xfc000000, ERIAR_EXGMAC);
4196                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4197                 break;
4198         }
4199 }
4200
4201 static void r8168_pll_power_up(struct rtl8169_private *tp)
4202 {
4203         switch (tp->mac_version) {
4204         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4205         case RTL_GIGA_MAC_VER_37:
4206         case RTL_GIGA_MAC_VER_39:
4207         case RTL_GIGA_MAC_VER_43:
4208                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4209                 break;
4210         case RTL_GIGA_MAC_VER_44:
4211         case RTL_GIGA_MAC_VER_45:
4212         case RTL_GIGA_MAC_VER_46:
4213         case RTL_GIGA_MAC_VER_47:
4214         case RTL_GIGA_MAC_VER_48:
4215         case RTL_GIGA_MAC_VER_50:
4216         case RTL_GIGA_MAC_VER_51:
4217                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4218                 break;
4219         case RTL_GIGA_MAC_VER_40:
4220         case RTL_GIGA_MAC_VER_41:
4221         case RTL_GIGA_MAC_VER_49:
4222                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4223                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4224                              0x00000000, ERIAR_EXGMAC);
4225                 break;
4226         }
4227
4228         phy_resume(tp->dev->phydev);
4229         /* give MAC/PHY some time to resume */
4230         msleep(20);
4231 }
4232
4233 static void rtl_pll_power_down(struct rtl8169_private *tp)
4234 {
4235         switch (tp->mac_version) {
4236         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4237         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4238                 break;
4239         default:
4240                 r8168_pll_power_down(tp);
4241         }
4242 }
4243
4244 static void rtl_pll_power_up(struct rtl8169_private *tp)
4245 {
4246         switch (tp->mac_version) {
4247         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4248         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4249                 break;
4250         default:
4251                 r8168_pll_power_up(tp);
4252         }
4253 }
4254
4255 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4256 {
4257         switch (tp->mac_version) {
4258         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4259         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4260                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4261                 break;
4262         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4263         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4264         case RTL_GIGA_MAC_VER_38:
4265                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4266                 break;
4267         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4268                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4269                 break;
4270         default:
4271                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4272                 break;
4273         }
4274 }
4275
4276 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4277 {
4278         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4279 }
4280
4281 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4282 {
4283         if (tp->jumbo_ops.enable) {
4284                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4285                 tp->jumbo_ops.enable(tp);
4286                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4287         }
4288 }
4289
4290 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4291 {
4292         if (tp->jumbo_ops.disable) {
4293                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4294                 tp->jumbo_ops.disable(tp);
4295                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4296         }
4297 }
4298
4299 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4300 {
4301         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4302         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4303         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4304 }
4305
4306 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4307 {
4308         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4309         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4310         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4311 }
4312
4313 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4314 {
4315         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4316 }
4317
4318 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4319 {
4320         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4321 }
4322
4323 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4324 {
4325         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4326         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4327         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4328         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4329 }
4330
4331 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4332 {
4333         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4334         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4335         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4336         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4337 }
4338
4339 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4340 {
4341         rtl_tx_performance_tweak(tp,
4342                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4343 }
4344
4345 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4346 {
4347         rtl_tx_performance_tweak(tp,
4348                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4349 }
4350
4351 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4352 {
4353         r8168b_0_hw_jumbo_enable(tp);
4354
4355         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4356 }
4357
4358 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4359 {
4360         r8168b_0_hw_jumbo_disable(tp);
4361
4362         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4363 }
4364
4365 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4366 {
4367         struct jumbo_ops *ops = &tp->jumbo_ops;
4368
4369         switch (tp->mac_version) {
4370         case RTL_GIGA_MAC_VER_11:
4371                 ops->disable    = r8168b_0_hw_jumbo_disable;
4372                 ops->enable     = r8168b_0_hw_jumbo_enable;
4373                 break;
4374         case RTL_GIGA_MAC_VER_12:
4375         case RTL_GIGA_MAC_VER_17:
4376                 ops->disable    = r8168b_1_hw_jumbo_disable;
4377                 ops->enable     = r8168b_1_hw_jumbo_enable;
4378                 break;
4379         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4380         case RTL_GIGA_MAC_VER_19:
4381         case RTL_GIGA_MAC_VER_20:
4382         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4383         case RTL_GIGA_MAC_VER_22:
4384         case RTL_GIGA_MAC_VER_23:
4385         case RTL_GIGA_MAC_VER_24:
4386         case RTL_GIGA_MAC_VER_25:
4387         case RTL_GIGA_MAC_VER_26:
4388                 ops->disable    = r8168c_hw_jumbo_disable;
4389                 ops->enable     = r8168c_hw_jumbo_enable;
4390                 break;
4391         case RTL_GIGA_MAC_VER_27:
4392         case RTL_GIGA_MAC_VER_28:
4393                 ops->disable    = r8168dp_hw_jumbo_disable;
4394                 ops->enable     = r8168dp_hw_jumbo_enable;
4395                 break;
4396         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4397         case RTL_GIGA_MAC_VER_32:
4398         case RTL_GIGA_MAC_VER_33:
4399         case RTL_GIGA_MAC_VER_34:
4400                 ops->disable    = r8168e_hw_jumbo_disable;
4401                 ops->enable     = r8168e_hw_jumbo_enable;
4402                 break;
4403
4404         /*
4405          * No action needed for jumbo frames with 8169.
4406          * No jumbo for 810x at all.
4407          */
4408         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4409         default:
4410                 ops->disable    = NULL;
4411                 ops->enable     = NULL;
4412                 break;
4413         }
4414 }
4415
4416 DECLARE_RTL_COND(rtl_chipcmd_cond)
4417 {
4418         return RTL_R8(tp, ChipCmd) & CmdReset;
4419 }
4420
4421 static void rtl_hw_reset(struct rtl8169_private *tp)
4422 {
4423         RTL_W8(tp, ChipCmd, CmdReset);
4424
4425         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4426 }
4427
4428 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4429 {
4430         struct rtl_fw *rtl_fw;
4431         const char *name;
4432         int rc = -ENOMEM;
4433
4434         name = rtl_lookup_firmware_name(tp);
4435         if (!name)
4436                 goto out_no_firmware;
4437
4438         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4439         if (!rtl_fw)
4440                 goto err_warn;
4441
4442         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4443         if (rc < 0)
4444                 goto err_free;
4445
4446         rc = rtl_check_firmware(tp, rtl_fw);
4447         if (rc < 0)
4448                 goto err_release_firmware;
4449
4450         tp->rtl_fw = rtl_fw;
4451 out:
4452         return;
4453
4454 err_release_firmware:
4455         release_firmware(rtl_fw->fw);
4456 err_free:
4457         kfree(rtl_fw);
4458 err_warn:
4459         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4460                    name, rc);
4461 out_no_firmware:
4462         tp->rtl_fw = NULL;
4463         goto out;
4464 }
4465
4466 static void rtl_request_firmware(struct rtl8169_private *tp)
4467 {
4468         if (IS_ERR(tp->rtl_fw))
4469                 rtl_request_uncached_firmware(tp);
4470 }
4471
4472 static void rtl_rx_close(struct rtl8169_private *tp)
4473 {
4474         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4475 }
4476
4477 DECLARE_RTL_COND(rtl_npq_cond)
4478 {
4479         return RTL_R8(tp, TxPoll) & NPQ;
4480 }
4481
4482 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4483 {
4484         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4485 }
4486
4487 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4488 {
4489         /* Disable interrupts */
4490         rtl8169_irq_mask_and_ack(tp);
4491
4492         rtl_rx_close(tp);
4493
4494         switch (tp->mac_version) {
4495         case RTL_GIGA_MAC_VER_27:
4496         case RTL_GIGA_MAC_VER_28:
4497         case RTL_GIGA_MAC_VER_31:
4498                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4499                 break;
4500         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4501         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4502                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4503                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4504                 break;
4505         default:
4506                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4507                 udelay(100);
4508                 break;
4509         }
4510
4511         rtl_hw_reset(tp);
4512 }
4513
4514 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4515 {
4516         u32 val = TX_DMA_BURST << TxDMAShift |
4517                   InterFrameGap << TxInterFrameGapShift;
4518
4519         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4520             tp->mac_version != RTL_GIGA_MAC_VER_39)
4521                 val |= TXCFG_AUTO_FIFO;
4522
4523         RTL_W32(tp, TxConfig, val);
4524 }
4525
4526 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4527 {
4528         /* Low hurts. Let's disable the filtering. */
4529         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4530 }
4531
4532 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4533 {
4534         /*
4535          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4536          * register to be written before TxDescAddrLow to work.
4537          * Switching from MMIO to I/O access fixes the issue as well.
4538          */
4539         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4540         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4541         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4542         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4543 }
4544
4545 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4546 {
4547         u32 val;
4548
4549         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4550                 val = 0x000fff00;
4551         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4552                 val = 0x00ffff00;
4553         else
4554                 return;
4555
4556         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4557                 val |= 0xff;
4558
4559         RTL_W32(tp, 0x7c, val);
4560 }
4561
4562 static void rtl_set_rx_mode(struct net_device *dev)
4563 {
4564         struct rtl8169_private *tp = netdev_priv(dev);
4565         u32 mc_filter[2];       /* Multicast hash filter */
4566         int rx_mode;
4567         u32 tmp = 0;
4568
4569         if (dev->flags & IFF_PROMISC) {
4570                 /* Unconditionally log net taps. */
4571                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4572                 rx_mode =
4573                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4574                     AcceptAllPhys;
4575                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4576         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4577                    (dev->flags & IFF_ALLMULTI)) {
4578                 /* Too many to filter perfectly -- accept all multicasts. */
4579                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4580                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4581         } else {
4582                 struct netdev_hw_addr *ha;
4583
4584                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4585                 mc_filter[1] = mc_filter[0] = 0;
4586                 netdev_for_each_mc_addr(ha, dev) {
4587                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4588                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4589                         rx_mode |= AcceptMulticast;
4590                 }
4591         }
4592
4593         if (dev->features & NETIF_F_RXALL)
4594                 rx_mode |= (AcceptErr | AcceptRunt);
4595
4596         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4597
4598         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4599                 u32 data = mc_filter[0];
4600
4601                 mc_filter[0] = swab32(mc_filter[1]);
4602                 mc_filter[1] = swab32(data);
4603         }
4604
4605         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4606                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4607
4608         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4609         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4610
4611         RTL_W32(tp, RxConfig, tmp);
4612 }
4613
4614 static void rtl_hw_start(struct  rtl8169_private *tp)
4615 {
4616         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4617
4618         tp->hw_start(tp);
4619
4620         rtl_set_rx_max_size(tp);
4621         rtl_set_rx_tx_desc_registers(tp);
4622         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4623
4624         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4625         RTL_R8(tp, IntrMask);
4626         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4627         rtl_init_rxcfg(tp);
4628         rtl_set_tx_config_registers(tp);
4629
4630         rtl_set_rx_mode(tp->dev);
4631         /* no early-rx interrupts */
4632         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4633         rtl_irq_enable(tp);
4634 }
4635
4636 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4637 {
4638         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4639                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4640
4641         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4642
4643         tp->cp_cmd |= PCIMulRW;
4644
4645         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4646             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4647                 netif_dbg(tp, drv, tp->dev,
4648                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4649                 tp->cp_cmd |= (1 << 14);
4650         }
4651
4652         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4653
4654         rtl8169_set_magic_reg(tp, tp->mac_version);
4655
4656         /*
4657          * Undocumented corner. Supposedly:
4658          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4659          */
4660         RTL_W16(tp, IntrMitigate, 0x0000);
4661
4662         RTL_W32(tp, RxMissed, 0);
4663 }
4664
4665 DECLARE_RTL_COND(rtl_csiar_cond)
4666 {
4667         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4668 }
4669
4670 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4671 {
4672         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4673
4674         RTL_W32(tp, CSIDR, value);
4675         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4676                 CSIAR_BYTE_ENABLE | func << 16);
4677
4678         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4679 }
4680
4681 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4682 {
4683         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4684
4685         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4686                 CSIAR_BYTE_ENABLE);
4687
4688         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4689                 RTL_R32(tp, CSIDR) : ~0;
4690 }
4691
4692 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4693 {
4694         struct pci_dev *pdev = tp->pci_dev;
4695         u32 csi;
4696
4697         /* According to Realtek the value at config space address 0x070f
4698          * controls the L0s/L1 entrance latency. We try standard ECAM access
4699          * first and if it fails fall back to CSI.
4700          */
4701         if (pdev->cfg_size > 0x070f &&
4702             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4703                 return;
4704
4705         netdev_notice_once(tp->dev,
4706                 "No native access to PCI extended config space, falling back to CSI\n");
4707         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4708         rtl_csi_write(tp, 0x070c, csi | val << 24);
4709 }
4710
4711 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4712 {
4713         rtl_csi_access_enable(tp, 0x27);
4714 }
4715
4716 struct ephy_info {
4717         unsigned int offset;
4718         u16 mask;
4719         u16 bits;
4720 };
4721
4722 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4723                           int len)
4724 {
4725         u16 w;
4726
4727         while (len-- > 0) {
4728                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4729                 rtl_ephy_write(tp, e->offset, w);
4730                 e++;
4731         }
4732 }
4733
4734 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4735 {
4736         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4737                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4738 }
4739
4740 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4741 {
4742         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4743                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4744 }
4745
4746 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4747 {
4748         u8 data;
4749
4750         data = RTL_R8(tp, Config3);
4751
4752         if (enable)
4753                 data |= Rdy_to_L23;
4754         else
4755                 data &= ~Rdy_to_L23;
4756
4757         RTL_W8(tp, Config3, data);
4758 }
4759
4760 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4761 {
4762         if (enable) {
4763                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4764                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4765         } else {
4766                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4767                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4768         }
4769
4770         udelay(10);
4771 }
4772
4773 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4774 {
4775         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4776
4777         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4778         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4779
4780         if (tp->dev->mtu <= ETH_DATA_LEN) {
4781                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4782                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4783         }
4784 }
4785
4786 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4787 {
4788         rtl_hw_start_8168bb(tp);
4789
4790         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4791
4792         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4793 }
4794
4795 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4796 {
4797         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4798
4799         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4800
4801         if (tp->dev->mtu <= ETH_DATA_LEN)
4802                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4803
4804         rtl_disable_clock_request(tp);
4805
4806         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4807         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4808 }
4809
4810 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4811 {
4812         static const struct ephy_info e_info_8168cp[] = {
4813                 { 0x01, 0,      0x0001 },
4814                 { 0x02, 0x0800, 0x1000 },
4815                 { 0x03, 0,      0x0042 },
4816                 { 0x06, 0x0080, 0x0000 },
4817                 { 0x07, 0,      0x2000 }
4818         };
4819
4820         rtl_set_def_aspm_entry_latency(tp);
4821
4822         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4823
4824         __rtl_hw_start_8168cp(tp);
4825 }
4826
4827 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4828 {
4829         rtl_set_def_aspm_entry_latency(tp);
4830
4831         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4832
4833         if (tp->dev->mtu <= ETH_DATA_LEN)
4834                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4835
4836         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4837         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4838 }
4839
4840 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4841 {
4842         rtl_set_def_aspm_entry_latency(tp);
4843
4844         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4845
4846         /* Magic. */
4847         RTL_W8(tp, DBG_REG, 0x20);
4848
4849         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4850
4851         if (tp->dev->mtu <= ETH_DATA_LEN)
4852                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4853
4854         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4855         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4856 }
4857
4858 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4859 {
4860         static const struct ephy_info e_info_8168c_1[] = {
4861                 { 0x02, 0x0800, 0x1000 },
4862                 { 0x03, 0,      0x0002 },
4863                 { 0x06, 0x0080, 0x0000 }
4864         };
4865
4866         rtl_set_def_aspm_entry_latency(tp);
4867
4868         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4869
4870         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4871
4872         __rtl_hw_start_8168cp(tp);
4873 }
4874
4875 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4876 {
4877         static const struct ephy_info e_info_8168c_2[] = {
4878                 { 0x01, 0,      0x0001 },
4879                 { 0x03, 0x0400, 0x0220 }
4880         };
4881
4882         rtl_set_def_aspm_entry_latency(tp);
4883
4884         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4885
4886         __rtl_hw_start_8168cp(tp);
4887 }
4888
4889 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4890 {
4891         rtl_hw_start_8168c_2(tp);
4892 }
4893
4894 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4895 {
4896         rtl_set_def_aspm_entry_latency(tp);
4897
4898         __rtl_hw_start_8168cp(tp);
4899 }
4900
4901 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4902 {
4903         rtl_set_def_aspm_entry_latency(tp);
4904
4905         rtl_disable_clock_request(tp);
4906
4907         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4908
4909         if (tp->dev->mtu <= ETH_DATA_LEN)
4910                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4911
4912         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4913         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4914 }
4915
4916 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4917 {
4918         rtl_set_def_aspm_entry_latency(tp);
4919
4920         if (tp->dev->mtu <= ETH_DATA_LEN)
4921                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4922
4923         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4924
4925         rtl_disable_clock_request(tp);
4926 }
4927
4928 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4929 {
4930         static const struct ephy_info e_info_8168d_4[] = {
4931                 { 0x0b, 0x0000, 0x0048 },
4932                 { 0x19, 0x0020, 0x0050 },
4933                 { 0x0c, 0x0100, 0x0020 }
4934         };
4935
4936         rtl_set_def_aspm_entry_latency(tp);
4937
4938         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4939
4940         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4941
4942         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4943
4944         rtl_enable_clock_request(tp);
4945 }
4946
4947 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4948 {
4949         static const struct ephy_info e_info_8168e_1[] = {
4950                 { 0x00, 0x0200, 0x0100 },
4951                 { 0x00, 0x0000, 0x0004 },
4952                 { 0x06, 0x0002, 0x0001 },
4953                 { 0x06, 0x0000, 0x0030 },
4954                 { 0x07, 0x0000, 0x2000 },
4955                 { 0x00, 0x0000, 0x0020 },
4956                 { 0x03, 0x5800, 0x2000 },
4957                 { 0x03, 0x0000, 0x0001 },
4958                 { 0x01, 0x0800, 0x1000 },
4959                 { 0x07, 0x0000, 0x4000 },
4960                 { 0x1e, 0x0000, 0x2000 },
4961                 { 0x19, 0xffff, 0xfe6c },
4962                 { 0x0a, 0x0000, 0x0040 }
4963         };
4964
4965         rtl_set_def_aspm_entry_latency(tp);
4966
4967         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4968
4969         if (tp->dev->mtu <= ETH_DATA_LEN)
4970                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4971
4972         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4973
4974         rtl_disable_clock_request(tp);
4975
4976         /* Reset tx FIFO pointer */
4977         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4978         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4979
4980         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4981 }
4982
4983 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4984 {
4985         static const struct ephy_info e_info_8168e_2[] = {
4986                 { 0x09, 0x0000, 0x0080 },
4987                 { 0x19, 0x0000, 0x0224 }
4988         };
4989
4990         rtl_set_def_aspm_entry_latency(tp);
4991
4992         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4993
4994         if (tp->dev->mtu <= ETH_DATA_LEN)
4995                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4996
4997         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4998         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4999         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5000         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5001         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5002         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5003         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5004         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5005
5006         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5007
5008         rtl_disable_clock_request(tp);
5009
5010         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5011
5012         /* Adjust EEE LED frequency */
5013         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5014
5015         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5016         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5017         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5018
5019         rtl_hw_aspm_clkreq_enable(tp, true);
5020 }
5021
5022 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5023 {
5024         rtl_set_def_aspm_entry_latency(tp);
5025
5026         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5027
5028         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5029         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5030         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5031         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5032         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5033         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5034         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5035         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5036         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5037         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5038
5039         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5040
5041         rtl_disable_clock_request(tp);
5042
5043         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5044         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5045         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5046         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5047 }
5048
5049 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5050 {
5051         static const struct ephy_info e_info_8168f_1[] = {
5052                 { 0x06, 0x00c0, 0x0020 },
5053                 { 0x08, 0x0001, 0x0002 },
5054                 { 0x09, 0x0000, 0x0080 },
5055                 { 0x19, 0x0000, 0x0224 }
5056         };
5057
5058         rtl_hw_start_8168f(tp);
5059
5060         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5061
5062         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5063
5064         /* Adjust EEE LED frequency */
5065         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5066 }
5067
5068 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5069 {
5070         static const struct ephy_info e_info_8168f_1[] = {
5071                 { 0x06, 0x00c0, 0x0020 },
5072                 { 0x0f, 0xffff, 0x5200 },
5073                 { 0x1e, 0x0000, 0x4000 },
5074                 { 0x19, 0x0000, 0x0224 }
5075         };
5076
5077         rtl_hw_start_8168f(tp);
5078         rtl_pcie_state_l2l3_enable(tp, false);
5079
5080         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5081
5082         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5083 }
5084
5085 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5086 {
5087         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5088         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5089         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5090         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5091
5092         rtl_set_def_aspm_entry_latency(tp);
5093
5094         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5095
5096         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5097         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5098         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5099
5100         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5101         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5102
5103         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5104         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5105
5106         /* Adjust EEE LED frequency */
5107         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5108
5109         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5110         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5111
5112         rtl_pcie_state_l2l3_enable(tp, false);
5113 }
5114
5115 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5116 {
5117         static const struct ephy_info e_info_8168g_1[] = {
5118                 { 0x00, 0x0000, 0x0008 },
5119                 { 0x0c, 0x37d0, 0x0820 },
5120                 { 0x1e, 0x0000, 0x0001 },
5121                 { 0x19, 0x8000, 0x0000 }
5122         };
5123
5124         rtl_hw_start_8168g(tp);
5125
5126         /* disable aspm and clock request before access ephy */
5127         rtl_hw_aspm_clkreq_enable(tp, false);
5128         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5129         rtl_hw_aspm_clkreq_enable(tp, true);
5130 }
5131
5132 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5133 {
5134         static const struct ephy_info e_info_8168g_2[] = {
5135                 { 0x00, 0x0000, 0x0008 },
5136                 { 0x0c, 0x3df0, 0x0200 },
5137                 { 0x19, 0xffff, 0xfc00 },
5138                 { 0x1e, 0xffff, 0x20eb }
5139         };
5140
5141         rtl_hw_start_8168g(tp);
5142
5143         /* disable aspm and clock request before access ephy */
5144         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5145         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5146         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5147 }
5148
5149 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5150 {
5151         static const struct ephy_info e_info_8411_2[] = {
5152                 { 0x00, 0x0000, 0x0008 },
5153                 { 0x0c, 0x3df0, 0x0200 },
5154                 { 0x0f, 0xffff, 0x5200 },
5155                 { 0x19, 0x0020, 0x0000 },
5156                 { 0x1e, 0x0000, 0x2000 }
5157         };
5158
5159         rtl_hw_start_8168g(tp);
5160
5161         /* disable aspm and clock request before access ephy */
5162         rtl_hw_aspm_clkreq_enable(tp, false);
5163         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5164         rtl_hw_aspm_clkreq_enable(tp, true);
5165 }
5166
5167 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5168 {
5169         int rg_saw_cnt;
5170         u32 data;
5171         static const struct ephy_info e_info_8168h_1[] = {
5172                 { 0x1e, 0x0800, 0x0001 },
5173                 { 0x1d, 0x0000, 0x0800 },
5174                 { 0x05, 0xffff, 0x2089 },
5175                 { 0x06, 0xffff, 0x5881 },
5176                 { 0x04, 0xffff, 0x154a },
5177                 { 0x01, 0xffff, 0x068b }
5178         };
5179
5180         /* disable aspm and clock request before access ephy */
5181         rtl_hw_aspm_clkreq_enable(tp, false);
5182         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5183
5184         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5185         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5186         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5187         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5188
5189         rtl_set_def_aspm_entry_latency(tp);
5190
5191         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5192
5193         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5194         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5195
5196         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5197
5198         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5199
5200         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5201
5202         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5203         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5204
5205         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5206         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5207
5208         /* Adjust EEE LED frequency */
5209         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5210
5211         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5212         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5213
5214         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5215
5216         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5217
5218         rtl_pcie_state_l2l3_enable(tp, false);
5219
5220         rtl_writephy(tp, 0x1f, 0x0c42);
5221         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5222         rtl_writephy(tp, 0x1f, 0x0000);
5223         if (rg_saw_cnt > 0) {
5224                 u16 sw_cnt_1ms_ini;
5225
5226                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5227                 sw_cnt_1ms_ini &= 0x0fff;
5228                 data = r8168_mac_ocp_read(tp, 0xd412);
5229                 data &= ~0x0fff;
5230                 data |= sw_cnt_1ms_ini;
5231                 r8168_mac_ocp_write(tp, 0xd412, data);
5232         }
5233
5234         data = r8168_mac_ocp_read(tp, 0xe056);
5235         data &= ~0xf0;
5236         data |= 0x70;
5237         r8168_mac_ocp_write(tp, 0xe056, data);
5238
5239         data = r8168_mac_ocp_read(tp, 0xe052);
5240         data &= ~0x6000;
5241         data |= 0x8008;
5242         r8168_mac_ocp_write(tp, 0xe052, data);
5243
5244         data = r8168_mac_ocp_read(tp, 0xe0d6);
5245         data &= ~0x01ff;
5246         data |= 0x017f;
5247         r8168_mac_ocp_write(tp, 0xe0d6, data);
5248
5249         data = r8168_mac_ocp_read(tp, 0xd420);
5250         data &= ~0x0fff;
5251         data |= 0x047f;
5252         r8168_mac_ocp_write(tp, 0xd420, data);
5253
5254         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5255         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5256         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5257         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5258
5259         rtl_hw_aspm_clkreq_enable(tp, true);
5260 }
5261
5262 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5263 {
5264         rtl8168ep_stop_cmac(tp);
5265
5266         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5267         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5268         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5269         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5270
5271         rtl_set_def_aspm_entry_latency(tp);
5272
5273         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5274
5275         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5276         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5277
5278         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5279
5280         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5281
5282         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5283         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5284
5285         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5286         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5287
5288         /* Adjust EEE LED frequency */
5289         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5290
5291         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5292
5293         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5294
5295         rtl_pcie_state_l2l3_enable(tp, false);
5296 }
5297
5298 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5299 {
5300         static const struct ephy_info e_info_8168ep_1[] = {
5301                 { 0x00, 0xffff, 0x10ab },
5302                 { 0x06, 0xffff, 0xf030 },
5303                 { 0x08, 0xffff, 0x2006 },
5304                 { 0x0d, 0xffff, 0x1666 },
5305                 { 0x0c, 0x3ff0, 0x0000 }
5306         };
5307
5308         /* disable aspm and clock request before access ephy */
5309         rtl_hw_aspm_clkreq_enable(tp, false);
5310         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5311
5312         rtl_hw_start_8168ep(tp);
5313
5314         rtl_hw_aspm_clkreq_enable(tp, true);
5315 }
5316
5317 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5318 {
5319         static const struct ephy_info e_info_8168ep_2[] = {
5320                 { 0x00, 0xffff, 0x10a3 },
5321                 { 0x19, 0xffff, 0xfc00 },
5322                 { 0x1e, 0xffff, 0x20ea }
5323         };
5324
5325         /* disable aspm and clock request before access ephy */
5326         rtl_hw_aspm_clkreq_enable(tp, false);
5327         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5328
5329         rtl_hw_start_8168ep(tp);
5330
5331         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5332         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5333
5334         rtl_hw_aspm_clkreq_enable(tp, true);
5335 }
5336
5337 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5338 {
5339         u32 data;
5340         static const struct ephy_info e_info_8168ep_3[] = {
5341                 { 0x00, 0xffff, 0x10a3 },
5342                 { 0x19, 0xffff, 0x7c00 },
5343                 { 0x1e, 0xffff, 0x20eb },
5344                 { 0x0d, 0xffff, 0x1666 }
5345         };
5346
5347         /* disable aspm and clock request before access ephy */
5348         rtl_hw_aspm_clkreq_enable(tp, false);
5349         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5350
5351         rtl_hw_start_8168ep(tp);
5352
5353         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5354         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5355
5356         data = r8168_mac_ocp_read(tp, 0xd3e2);
5357         data &= 0xf000;
5358         data |= 0x0271;
5359         r8168_mac_ocp_write(tp, 0xd3e2, data);
5360
5361         data = r8168_mac_ocp_read(tp, 0xd3e4);
5362         data &= 0xff00;
5363         r8168_mac_ocp_write(tp, 0xd3e4, data);
5364
5365         data = r8168_mac_ocp_read(tp, 0xe860);
5366         data |= 0x0080;
5367         r8168_mac_ocp_write(tp, 0xe860, data);
5368
5369         rtl_hw_aspm_clkreq_enable(tp, true);
5370 }
5371
5372 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5373 {
5374         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5375
5376         tp->cp_cmd &= ~INTT_MASK;
5377         tp->cp_cmd |= PktCntrDisable | INTT_1;
5378         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5379
5380         RTL_W16(tp, IntrMitigate, 0x5151);
5381
5382         /* Work around for RxFIFO overflow. */
5383         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5384                 tp->irq_mask |= RxFIFOOver;
5385                 tp->irq_mask &= ~RxOverflow;
5386         }
5387
5388         switch (tp->mac_version) {
5389         case RTL_GIGA_MAC_VER_11:
5390                 rtl_hw_start_8168bb(tp);
5391                 break;
5392
5393         case RTL_GIGA_MAC_VER_12:
5394         case RTL_GIGA_MAC_VER_17:
5395                 rtl_hw_start_8168bef(tp);
5396                 break;
5397
5398         case RTL_GIGA_MAC_VER_18:
5399                 rtl_hw_start_8168cp_1(tp);
5400                 break;
5401
5402         case RTL_GIGA_MAC_VER_19:
5403                 rtl_hw_start_8168c_1(tp);
5404                 break;
5405
5406         case RTL_GIGA_MAC_VER_20:
5407                 rtl_hw_start_8168c_2(tp);
5408                 break;
5409
5410         case RTL_GIGA_MAC_VER_21:
5411                 rtl_hw_start_8168c_3(tp);
5412                 break;
5413
5414         case RTL_GIGA_MAC_VER_22:
5415                 rtl_hw_start_8168c_4(tp);
5416                 break;
5417
5418         case RTL_GIGA_MAC_VER_23:
5419                 rtl_hw_start_8168cp_2(tp);
5420                 break;
5421
5422         case RTL_GIGA_MAC_VER_24:
5423                 rtl_hw_start_8168cp_3(tp);
5424                 break;
5425
5426         case RTL_GIGA_MAC_VER_25:
5427         case RTL_GIGA_MAC_VER_26:
5428         case RTL_GIGA_MAC_VER_27:
5429                 rtl_hw_start_8168d(tp);
5430                 break;
5431
5432         case RTL_GIGA_MAC_VER_28:
5433                 rtl_hw_start_8168d_4(tp);
5434                 break;
5435
5436         case RTL_GIGA_MAC_VER_31:
5437                 rtl_hw_start_8168dp(tp);
5438                 break;
5439
5440         case RTL_GIGA_MAC_VER_32:
5441         case RTL_GIGA_MAC_VER_33:
5442                 rtl_hw_start_8168e_1(tp);
5443                 break;
5444         case RTL_GIGA_MAC_VER_34:
5445                 rtl_hw_start_8168e_2(tp);
5446                 break;
5447
5448         case RTL_GIGA_MAC_VER_35:
5449         case RTL_GIGA_MAC_VER_36:
5450                 rtl_hw_start_8168f_1(tp);
5451                 break;
5452
5453         case RTL_GIGA_MAC_VER_38:
5454                 rtl_hw_start_8411(tp);
5455                 break;
5456
5457         case RTL_GIGA_MAC_VER_40:
5458         case RTL_GIGA_MAC_VER_41:
5459                 rtl_hw_start_8168g_1(tp);
5460                 break;
5461         case RTL_GIGA_MAC_VER_42:
5462                 rtl_hw_start_8168g_2(tp);
5463                 break;
5464
5465         case RTL_GIGA_MAC_VER_44:
5466                 rtl_hw_start_8411_2(tp);
5467                 break;
5468
5469         case RTL_GIGA_MAC_VER_45:
5470         case RTL_GIGA_MAC_VER_46:
5471                 rtl_hw_start_8168h_1(tp);
5472                 break;
5473
5474         case RTL_GIGA_MAC_VER_49:
5475                 rtl_hw_start_8168ep_1(tp);
5476                 break;
5477
5478         case RTL_GIGA_MAC_VER_50:
5479                 rtl_hw_start_8168ep_2(tp);
5480                 break;
5481
5482         case RTL_GIGA_MAC_VER_51:
5483                 rtl_hw_start_8168ep_3(tp);
5484                 break;
5485
5486         default:
5487                 netif_err(tp, drv, tp->dev,
5488                           "unknown chipset (mac_version = %d)\n",
5489                           tp->mac_version);
5490                 break;
5491         }
5492 }
5493
5494 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5495 {
5496         static const struct ephy_info e_info_8102e_1[] = {
5497                 { 0x01, 0, 0x6e65 },
5498                 { 0x02, 0, 0x091f },
5499                 { 0x03, 0, 0xc2f9 },
5500                 { 0x06, 0, 0xafb5 },
5501                 { 0x07, 0, 0x0e00 },
5502                 { 0x19, 0, 0xec80 },
5503                 { 0x01, 0, 0x2e65 },
5504                 { 0x01, 0, 0x6e65 }
5505         };
5506         u8 cfg1;
5507
5508         rtl_set_def_aspm_entry_latency(tp);
5509
5510         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5511
5512         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5513
5514         RTL_W8(tp, Config1,
5515                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5516         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5517
5518         cfg1 = RTL_R8(tp, Config1);
5519         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5520                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5521
5522         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5523 }
5524
5525 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5526 {
5527         rtl_set_def_aspm_entry_latency(tp);
5528
5529         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5530
5531         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5532         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5533 }
5534
5535 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5536 {
5537         rtl_hw_start_8102e_2(tp);
5538
5539         rtl_ephy_write(tp, 0x03, 0xc2f9);
5540 }
5541
5542 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5543 {
5544         static const struct ephy_info e_info_8105e_1[] = {
5545                 { 0x07, 0, 0x4000 },
5546                 { 0x19, 0, 0x0200 },
5547                 { 0x19, 0, 0x0020 },
5548                 { 0x1e, 0, 0x2000 },
5549                 { 0x03, 0, 0x0001 },
5550                 { 0x19, 0, 0x0100 },
5551                 { 0x19, 0, 0x0004 },
5552                 { 0x0a, 0, 0x0020 }
5553         };
5554
5555         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5556         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5557
5558         /* Disable Early Tally Counter */
5559         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5560
5561         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5562         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5563
5564         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5565
5566         rtl_pcie_state_l2l3_enable(tp, false);
5567 }
5568
5569 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5570 {
5571         rtl_hw_start_8105e_1(tp);
5572         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5573 }
5574
5575 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5576 {
5577         static const struct ephy_info e_info_8402[] = {
5578                 { 0x19, 0xffff, 0xff64 },
5579                 { 0x1e, 0, 0x4000 }
5580         };
5581
5582         rtl_set_def_aspm_entry_latency(tp);
5583
5584         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5585         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5586
5587         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5588
5589         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5590
5591         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5592
5593         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5594         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5595         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5596         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5597         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5599         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5600
5601         rtl_pcie_state_l2l3_enable(tp, false);
5602 }
5603
5604 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5605 {
5606         rtl_hw_aspm_clkreq_enable(tp, false);
5607
5608         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5609         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5610
5611         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5612         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5613         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5614
5615         rtl_pcie_state_l2l3_enable(tp, false);
5616         rtl_hw_aspm_clkreq_enable(tp, true);
5617 }
5618
5619 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5620 {
5621         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5622                 tp->irq_mask &= ~RxFIFOOver;
5623
5624         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5625             tp->mac_version == RTL_GIGA_MAC_VER_16)
5626                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5627                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5628
5629         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5630
5631         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5632         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5633
5634         switch (tp->mac_version) {
5635         case RTL_GIGA_MAC_VER_07:
5636                 rtl_hw_start_8102e_1(tp);
5637                 break;
5638
5639         case RTL_GIGA_MAC_VER_08:
5640                 rtl_hw_start_8102e_3(tp);
5641                 break;
5642
5643         case RTL_GIGA_MAC_VER_09:
5644                 rtl_hw_start_8102e_2(tp);
5645                 break;
5646
5647         case RTL_GIGA_MAC_VER_29:
5648                 rtl_hw_start_8105e_1(tp);
5649                 break;
5650         case RTL_GIGA_MAC_VER_30:
5651                 rtl_hw_start_8105e_2(tp);
5652                 break;
5653
5654         case RTL_GIGA_MAC_VER_37:
5655                 rtl_hw_start_8402(tp);
5656                 break;
5657
5658         case RTL_GIGA_MAC_VER_39:
5659                 rtl_hw_start_8106(tp);
5660                 break;
5661         case RTL_GIGA_MAC_VER_43:
5662                 rtl_hw_start_8168g_2(tp);
5663                 break;
5664         case RTL_GIGA_MAC_VER_47:
5665         case RTL_GIGA_MAC_VER_48:
5666                 rtl_hw_start_8168h_1(tp);
5667                 break;
5668         }
5669
5670         RTL_W16(tp, IntrMitigate, 0x0000);
5671 }
5672
5673 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5674 {
5675         struct rtl8169_private *tp = netdev_priv(dev);
5676
5677         if (new_mtu > ETH_DATA_LEN)
5678                 rtl_hw_jumbo_enable(tp);
5679         else
5680                 rtl_hw_jumbo_disable(tp);
5681
5682         dev->mtu = new_mtu;
5683         netdev_update_features(dev);
5684
5685         return 0;
5686 }
5687
5688 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5689 {
5690         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5691         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5692 }
5693
5694 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5695                                      void **data_buff, struct RxDesc *desc)
5696 {
5697         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5698                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5699
5700         kfree(*data_buff);
5701         *data_buff = NULL;
5702         rtl8169_make_unusable_by_asic(desc);
5703 }
5704
5705 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5706 {
5707         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5708
5709         /* Force memory writes to complete before releasing descriptor */
5710         dma_wmb();
5711
5712         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5713 }
5714
5715 static inline void *rtl8169_align(void *data)
5716 {
5717         return (void *)ALIGN((long)data, 16);
5718 }
5719
5720 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5721                                              struct RxDesc *desc)
5722 {
5723         void *data;
5724         dma_addr_t mapping;
5725         struct device *d = tp_to_dev(tp);
5726         int node = dev_to_node(d);
5727
5728         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5729         if (!data)
5730                 return NULL;
5731
5732         if (rtl8169_align(data) != data) {
5733                 kfree(data);
5734                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5735                 if (!data)
5736                         return NULL;
5737         }
5738
5739         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5740                                  DMA_FROM_DEVICE);
5741         if (unlikely(dma_mapping_error(d, mapping))) {
5742                 if (net_ratelimit())
5743                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5744                 goto err_out;
5745         }
5746
5747         desc->addr = cpu_to_le64(mapping);
5748         rtl8169_mark_to_asic(desc);
5749         return data;
5750
5751 err_out:
5752         kfree(data);
5753         return NULL;
5754 }
5755
5756 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5757 {
5758         unsigned int i;
5759
5760         for (i = 0; i < NUM_RX_DESC; i++) {
5761                 if (tp->Rx_databuff[i]) {
5762                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5763                                             tp->RxDescArray + i);
5764                 }
5765         }
5766 }
5767
5768 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5769 {
5770         desc->opts1 |= cpu_to_le32(RingEnd);
5771 }
5772
5773 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5774 {
5775         unsigned int i;
5776
5777         for (i = 0; i < NUM_RX_DESC; i++) {
5778                 void *data;
5779
5780                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5781                 if (!data) {
5782                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5783                         goto err_out;
5784                 }
5785                 tp->Rx_databuff[i] = data;
5786         }
5787
5788         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5789         return 0;
5790
5791 err_out:
5792         rtl8169_rx_clear(tp);
5793         return -ENOMEM;
5794 }
5795
5796 static int rtl8169_init_ring(struct rtl8169_private *tp)
5797 {
5798         rtl8169_init_ring_indexes(tp);
5799
5800         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5801         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5802
5803         return rtl8169_rx_fill(tp);
5804 }
5805
5806 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5807                                  struct TxDesc *desc)
5808 {
5809         unsigned int len = tx_skb->len;
5810
5811         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5812
5813         desc->opts1 = 0x00;
5814         desc->opts2 = 0x00;
5815         desc->addr = 0x00;
5816         tx_skb->len = 0;
5817 }
5818
5819 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5820                                    unsigned int n)
5821 {
5822         unsigned int i;
5823
5824         for (i = 0; i < n; i++) {
5825                 unsigned int entry = (start + i) % NUM_TX_DESC;
5826                 struct ring_info *tx_skb = tp->tx_skb + entry;
5827                 unsigned int len = tx_skb->len;
5828
5829                 if (len) {
5830                         struct sk_buff *skb = tx_skb->skb;
5831
5832                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5833                                              tp->TxDescArray + entry);
5834                         if (skb) {
5835                                 dev_consume_skb_any(skb);
5836                                 tx_skb->skb = NULL;
5837                         }
5838                 }
5839         }
5840 }
5841
5842 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5843 {
5844         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5845         tp->cur_tx = tp->dirty_tx = 0;
5846         netdev_reset_queue(tp->dev);
5847 }
5848
5849 static void rtl_reset_work(struct rtl8169_private *tp)
5850 {
5851         struct net_device *dev = tp->dev;
5852         int i;
5853
5854         napi_disable(&tp->napi);
5855         netif_stop_queue(dev);
5856         synchronize_sched();
5857
5858         rtl8169_hw_reset(tp);
5859
5860         for (i = 0; i < NUM_RX_DESC; i++)
5861                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5862
5863         rtl8169_tx_clear(tp);
5864         rtl8169_init_ring_indexes(tp);
5865
5866         napi_enable(&tp->napi);
5867         rtl_hw_start(tp);
5868         netif_wake_queue(dev);
5869 }
5870
5871 static void rtl8169_tx_timeout(struct net_device *dev)
5872 {
5873         struct rtl8169_private *tp = netdev_priv(dev);
5874
5875         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5876 }
5877
5878 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5879                               u32 *opts)
5880 {
5881         struct skb_shared_info *info = skb_shinfo(skb);
5882         unsigned int cur_frag, entry;
5883         struct TxDesc *uninitialized_var(txd);
5884         struct device *d = tp_to_dev(tp);
5885
5886         entry = tp->cur_tx;
5887         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5888                 const skb_frag_t *frag = info->frags + cur_frag;
5889                 dma_addr_t mapping;
5890                 u32 status, len;
5891                 void *addr;
5892
5893                 entry = (entry + 1) % NUM_TX_DESC;
5894
5895                 txd = tp->TxDescArray + entry;
5896                 len = skb_frag_size(frag);
5897                 addr = skb_frag_address(frag);
5898                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5899                 if (unlikely(dma_mapping_error(d, mapping))) {
5900                         if (net_ratelimit())
5901                                 netif_err(tp, drv, tp->dev,
5902                                           "Failed to map TX fragments DMA!\n");
5903                         goto err_out;
5904                 }
5905
5906                 status = opts[0] | len;
5907                 if (entry == NUM_TX_DESC - 1)
5908                         status |= RingEnd;
5909
5910                 txd->opts1 = cpu_to_le32(status);
5911                 txd->opts2 = cpu_to_le32(opts[1]);
5912                 txd->addr = cpu_to_le64(mapping);
5913
5914                 tp->tx_skb[entry].len = len;
5915         }
5916
5917         if (cur_frag) {
5918                 tp->tx_skb[entry].skb = skb;
5919                 txd->opts1 |= cpu_to_le32(LastFrag);
5920         }
5921
5922         return cur_frag;
5923
5924 err_out:
5925         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5926         return -EIO;
5927 }
5928
5929 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5930 {
5931         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5932 }
5933
5934 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5935                                       struct net_device *dev);
5936 /* r8169_csum_workaround()
5937  * The hw limites the value the transport offset. When the offset is out of the
5938  * range, calculate the checksum by sw.
5939  */
5940 static void r8169_csum_workaround(struct rtl8169_private *tp,
5941                                   struct sk_buff *skb)
5942 {
5943         if (skb_shinfo(skb)->gso_size) {
5944                 netdev_features_t features = tp->dev->features;
5945                 struct sk_buff *segs, *nskb;
5946
5947                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5948                 segs = skb_gso_segment(skb, features);
5949                 if (IS_ERR(segs) || !segs)
5950                         goto drop;
5951
5952                 do {
5953                         nskb = segs;
5954                         segs = segs->next;
5955                         nskb->next = NULL;
5956                         rtl8169_start_xmit(nskb, tp->dev);
5957                 } while (segs);
5958
5959                 dev_consume_skb_any(skb);
5960         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5961                 if (skb_checksum_help(skb) < 0)
5962                         goto drop;
5963
5964                 rtl8169_start_xmit(skb, tp->dev);
5965         } else {
5966                 struct net_device_stats *stats;
5967
5968 drop:
5969                 stats = &tp->dev->stats;
5970                 stats->tx_dropped++;
5971                 dev_kfree_skb_any(skb);
5972         }
5973 }
5974
5975 /* msdn_giant_send_check()
5976  * According to the document of microsoft, the TCP Pseudo Header excludes the
5977  * packet length for IPv6 TCP large packets.
5978  */
5979 static int msdn_giant_send_check(struct sk_buff *skb)
5980 {
5981         const struct ipv6hdr *ipv6h;
5982         struct tcphdr *th;
5983         int ret;
5984
5985         ret = skb_cow_head(skb, 0);
5986         if (ret)
5987                 return ret;
5988
5989         ipv6h = ipv6_hdr(skb);
5990         th = tcp_hdr(skb);
5991
5992         th->check = 0;
5993         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5994
5995         return ret;
5996 }
5997
5998 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5999                                 struct sk_buff *skb, u32 *opts)
6000 {
6001         u32 mss = skb_shinfo(skb)->gso_size;
6002
6003         if (mss) {
6004                 opts[0] |= TD_LSO;
6005                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6006         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6007                 const struct iphdr *ip = ip_hdr(skb);
6008
6009                 if (ip->protocol == IPPROTO_TCP)
6010                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6011                 else if (ip->protocol == IPPROTO_UDP)
6012                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6013                 else
6014                         WARN_ON_ONCE(1);
6015         }
6016
6017         return true;
6018 }
6019
6020 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6021                                 struct sk_buff *skb, u32 *opts)
6022 {
6023         u32 transport_offset = (u32)skb_transport_offset(skb);
6024         u32 mss = skb_shinfo(skb)->gso_size;
6025
6026         if (mss) {
6027                 if (transport_offset > GTTCPHO_MAX) {
6028                         netif_warn(tp, tx_err, tp->dev,
6029                                    "Invalid transport offset 0x%x for TSO\n",
6030                                    transport_offset);
6031                         return false;
6032                 }
6033
6034                 switch (vlan_get_protocol(skb)) {
6035                 case htons(ETH_P_IP):
6036                         opts[0] |= TD1_GTSENV4;
6037                         break;
6038
6039                 case htons(ETH_P_IPV6):
6040                         if (msdn_giant_send_check(skb))
6041                                 return false;
6042
6043                         opts[0] |= TD1_GTSENV6;
6044                         break;
6045
6046                 default:
6047                         WARN_ON_ONCE(1);
6048                         break;
6049                 }
6050
6051                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6052                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6053         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6054                 u8 ip_protocol;
6055
6056                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6057                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6058
6059                 if (transport_offset > TCPHO_MAX) {
6060                         netif_warn(tp, tx_err, tp->dev,
6061                                    "Invalid transport offset 0x%x\n",
6062                                    transport_offset);
6063                         return false;
6064                 }
6065
6066                 switch (vlan_get_protocol(skb)) {
6067                 case htons(ETH_P_IP):
6068                         opts[1] |= TD1_IPv4_CS;
6069                         ip_protocol = ip_hdr(skb)->protocol;
6070                         break;
6071
6072                 case htons(ETH_P_IPV6):
6073                         opts[1] |= TD1_IPv6_CS;
6074                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6075                         break;
6076
6077                 default:
6078                         ip_protocol = IPPROTO_RAW;
6079                         break;
6080                 }
6081
6082                 if (ip_protocol == IPPROTO_TCP)
6083                         opts[1] |= TD1_TCP_CS;
6084                 else if (ip_protocol == IPPROTO_UDP)
6085                         opts[1] |= TD1_UDP_CS;
6086                 else
6087                         WARN_ON_ONCE(1);
6088
6089                 opts[1] |= transport_offset << TCPHO_SHIFT;
6090         } else {
6091                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6092                         return !eth_skb_pad(skb);
6093         }
6094
6095         return true;
6096 }
6097
6098 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6099                                       struct net_device *dev)
6100 {
6101         struct rtl8169_private *tp = netdev_priv(dev);
6102         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6103         struct TxDesc *txd = tp->TxDescArray + entry;
6104         struct device *d = tp_to_dev(tp);
6105         dma_addr_t mapping;
6106         u32 status, len;
6107         u32 opts[2];
6108         int frags;
6109
6110         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6111                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6112                 goto err_stop_0;
6113         }
6114
6115         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6116                 goto err_stop_0;
6117
6118         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6119         opts[0] = DescOwn;
6120
6121         if (!tp->tso_csum(tp, skb, opts)) {
6122                 r8169_csum_workaround(tp, skb);
6123                 return NETDEV_TX_OK;
6124         }
6125
6126         len = skb_headlen(skb);
6127         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6128         if (unlikely(dma_mapping_error(d, mapping))) {
6129                 if (net_ratelimit())
6130                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6131                 goto err_dma_0;
6132         }
6133
6134         tp->tx_skb[entry].len = len;
6135         txd->addr = cpu_to_le64(mapping);
6136
6137         frags = rtl8169_xmit_frags(tp, skb, opts);
6138         if (frags < 0)
6139                 goto err_dma_1;
6140         else if (frags)
6141                 opts[0] |= FirstFrag;
6142         else {
6143                 opts[0] |= FirstFrag | LastFrag;
6144                 tp->tx_skb[entry].skb = skb;
6145         }
6146
6147         txd->opts2 = cpu_to_le32(opts[1]);
6148
6149         netdev_sent_queue(dev, skb->len);
6150
6151         skb_tx_timestamp(skb);
6152
6153         /* Force memory writes to complete before releasing descriptor */
6154         dma_wmb();
6155
6156         /* Anti gcc 2.95.3 bugware (sic) */
6157         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6158         txd->opts1 = cpu_to_le32(status);
6159
6160         /* Force all memory writes to complete before notifying device */
6161         wmb();
6162
6163         tp->cur_tx += frags + 1;
6164
6165         RTL_W8(tp, TxPoll, NPQ);
6166
6167         mmiowb();
6168
6169         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6170                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6171                  * not miss a ring update when it notices a stopped queue.
6172                  */
6173                 smp_wmb();
6174                 netif_stop_queue(dev);
6175                 /* Sync with rtl_tx:
6176                  * - publish queue status and cur_tx ring index (write barrier)
6177                  * - refresh dirty_tx ring index (read barrier).
6178                  * May the current thread have a pessimistic view of the ring
6179                  * status and forget to wake up queue, a racing rtl_tx thread
6180                  * can't.
6181                  */
6182                 smp_mb();
6183                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6184                         netif_wake_queue(dev);
6185         }
6186
6187         return NETDEV_TX_OK;
6188
6189 err_dma_1:
6190         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6191 err_dma_0:
6192         dev_kfree_skb_any(skb);
6193         dev->stats.tx_dropped++;
6194         return NETDEV_TX_OK;
6195
6196 err_stop_0:
6197         netif_stop_queue(dev);
6198         dev->stats.tx_dropped++;
6199         return NETDEV_TX_BUSY;
6200 }
6201
6202 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6203 {
6204         struct rtl8169_private *tp = netdev_priv(dev);
6205         struct pci_dev *pdev = tp->pci_dev;
6206         u16 pci_status, pci_cmd;
6207
6208         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6209         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6210
6211         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6212                   pci_cmd, pci_status);
6213
6214         /*
6215          * The recovery sequence below admits a very elaborated explanation:
6216          * - it seems to work;
6217          * - I did not see what else could be done;
6218          * - it makes iop3xx happy.
6219          *
6220          * Feel free to adjust to your needs.
6221          */
6222         if (pdev->broken_parity_status)
6223                 pci_cmd &= ~PCI_COMMAND_PARITY;
6224         else
6225                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6226
6227         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6228
6229         pci_write_config_word(pdev, PCI_STATUS,
6230                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6231                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6232                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6233
6234         /* The infamous DAC f*ckup only happens at boot time */
6235         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6236                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6237                 tp->cp_cmd &= ~PCIDAC;
6238                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6239                 dev->features &= ~NETIF_F_HIGHDMA;
6240         }
6241
6242         rtl8169_hw_reset(tp);
6243
6244         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6245 }
6246
6247 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6248 {
6249         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6250
6251         dirty_tx = tp->dirty_tx;
6252         smp_rmb();
6253         tx_left = tp->cur_tx - dirty_tx;
6254
6255         while (tx_left > 0) {
6256                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6257                 struct ring_info *tx_skb = tp->tx_skb + entry;
6258                 u32 status;
6259
6260                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6261                 if (status & DescOwn)
6262                         break;
6263
6264                 /* This barrier is needed to keep us from reading
6265                  * any other fields out of the Tx descriptor until
6266                  * we know the status of DescOwn
6267                  */
6268                 dma_rmb();
6269
6270                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6271                                      tp->TxDescArray + entry);
6272                 if (status & LastFrag) {
6273                         pkts_compl++;
6274                         bytes_compl += tx_skb->skb->len;
6275                         dev_consume_skb_any(tx_skb->skb);
6276                         tx_skb->skb = NULL;
6277                 }
6278                 dirty_tx++;
6279                 tx_left--;
6280         }
6281
6282         if (tp->dirty_tx != dirty_tx) {
6283                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6284
6285                 u64_stats_update_begin(&tp->tx_stats.syncp);
6286                 tp->tx_stats.packets += pkts_compl;
6287                 tp->tx_stats.bytes += bytes_compl;
6288                 u64_stats_update_end(&tp->tx_stats.syncp);
6289
6290                 tp->dirty_tx = dirty_tx;
6291                 /* Sync with rtl8169_start_xmit:
6292                  * - publish dirty_tx ring index (write barrier)
6293                  * - refresh cur_tx ring index and queue status (read barrier)
6294                  * May the current thread miss the stopped queue condition,
6295                  * a racing xmit thread can only have a right view of the
6296                  * ring status.
6297                  */
6298                 smp_mb();
6299                 if (netif_queue_stopped(dev) &&
6300                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6301                         netif_wake_queue(dev);
6302                 }
6303                 /*
6304                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6305                  * too close. Let's kick an extra TxPoll request when a burst
6306                  * of start_xmit activity is detected (if it is not detected,
6307                  * it is slow enough). -- FR
6308                  */
6309                 if (tp->cur_tx != dirty_tx)
6310                         RTL_W8(tp, TxPoll, NPQ);
6311         }
6312 }
6313
6314 static inline int rtl8169_fragmented_frame(u32 status)
6315 {
6316         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6317 }
6318
6319 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6320 {
6321         u32 status = opts1 & RxProtoMask;
6322
6323         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6324             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6325                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6326         else
6327                 skb_checksum_none_assert(skb);
6328 }
6329
6330 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6331                                            struct rtl8169_private *tp,
6332                                            int pkt_size,
6333                                            dma_addr_t addr)
6334 {
6335         struct sk_buff *skb;
6336         struct device *d = tp_to_dev(tp);
6337
6338         data = rtl8169_align(data);
6339         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6340         prefetch(data);
6341         skb = napi_alloc_skb(&tp->napi, pkt_size);
6342         if (skb)
6343                 skb_copy_to_linear_data(skb, data, pkt_size);
6344         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6345
6346         return skb;
6347 }
6348
6349 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6350 {
6351         unsigned int cur_rx, rx_left;
6352         unsigned int count;
6353
6354         cur_rx = tp->cur_rx;
6355
6356         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6357                 unsigned int entry = cur_rx % NUM_RX_DESC;
6358                 struct RxDesc *desc = tp->RxDescArray + entry;
6359                 u32 status;
6360
6361                 status = le32_to_cpu(desc->opts1);
6362                 if (status & DescOwn)
6363                         break;
6364
6365                 /* This barrier is needed to keep us from reading
6366                  * any other fields out of the Rx descriptor until
6367                  * we know the status of DescOwn
6368                  */
6369                 dma_rmb();
6370
6371                 if (unlikely(status & RxRES)) {
6372                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6373                                    status);
6374                         dev->stats.rx_errors++;
6375                         if (status & (RxRWT | RxRUNT))
6376                                 dev->stats.rx_length_errors++;
6377                         if (status & RxCRC)
6378                                 dev->stats.rx_crc_errors++;
6379                         /* RxFOVF is a reserved bit on later chip versions */
6380                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6381                             status & RxFOVF) {
6382                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6383                                 dev->stats.rx_fifo_errors++;
6384                         } else if (status & (RxRUNT | RxCRC) &&
6385                                    !(status & RxRWT) &&
6386                                    dev->features & NETIF_F_RXALL) {
6387                                 goto process_pkt;
6388                         }
6389                 } else {
6390                         struct sk_buff *skb;
6391                         dma_addr_t addr;
6392                         int pkt_size;
6393
6394 process_pkt:
6395                         addr = le64_to_cpu(desc->addr);
6396                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6397                                 pkt_size = (status & 0x00003fff) - 4;
6398                         else
6399                                 pkt_size = status & 0x00003fff;
6400
6401                         /*
6402                          * The driver does not support incoming fragmented
6403                          * frames. They are seen as a symptom of over-mtu
6404                          * sized frames.
6405                          */
6406                         if (unlikely(rtl8169_fragmented_frame(status))) {
6407                                 dev->stats.rx_dropped++;
6408                                 dev->stats.rx_length_errors++;
6409                                 goto release_descriptor;
6410                         }
6411
6412                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6413                                                   tp, pkt_size, addr);
6414                         if (!skb) {
6415                                 dev->stats.rx_dropped++;
6416                                 goto release_descriptor;
6417                         }
6418
6419                         rtl8169_rx_csum(skb, status);
6420                         skb_put(skb, pkt_size);
6421                         skb->protocol = eth_type_trans(skb, dev);
6422
6423                         rtl8169_rx_vlan_tag(desc, skb);
6424
6425                         if (skb->pkt_type == PACKET_MULTICAST)
6426                                 dev->stats.multicast++;
6427
6428                         napi_gro_receive(&tp->napi, skb);
6429
6430                         u64_stats_update_begin(&tp->rx_stats.syncp);
6431                         tp->rx_stats.packets++;
6432                         tp->rx_stats.bytes += pkt_size;
6433                         u64_stats_update_end(&tp->rx_stats.syncp);
6434                 }
6435 release_descriptor:
6436                 desc->opts2 = 0;
6437                 rtl8169_mark_to_asic(desc);
6438         }
6439
6440         count = cur_rx - tp->cur_rx;
6441         tp->cur_rx = cur_rx;
6442
6443         return count;
6444 }
6445
6446 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6447 {
6448         struct rtl8169_private *tp = dev_instance;
6449         u16 status = rtl_get_events(tp);
6450
6451         if (status == 0xffff || !(status & tp->irq_mask))
6452                 return IRQ_NONE;
6453
6454         if (unlikely(status & SYSErr)) {
6455                 rtl8169_pcierr_interrupt(tp->dev);
6456                 goto out;
6457         }
6458
6459         if (status & LinkChg)
6460                 phy_mac_interrupt(tp->dev->phydev);
6461
6462         if (unlikely(status & RxFIFOOver &&
6463             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6464                 netif_stop_queue(tp->dev);
6465                 /* XXX - Hack alert. See rtl_task(). */
6466                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6467         }
6468
6469         if (status & RTL_EVENT_NAPI) {
6470                 rtl_irq_disable(tp);
6471                 napi_schedule_irqoff(&tp->napi);
6472         }
6473 out:
6474         rtl_ack_events(tp, status);
6475
6476         return IRQ_HANDLED;
6477 }
6478
6479 static void rtl_task(struct work_struct *work)
6480 {
6481         static const struct {
6482                 int bitnr;
6483                 void (*action)(struct rtl8169_private *);
6484         } rtl_work[] = {
6485                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6486         };
6487         struct rtl8169_private *tp =
6488                 container_of(work, struct rtl8169_private, wk.work);
6489         struct net_device *dev = tp->dev;
6490         int i;
6491
6492         rtl_lock_work(tp);
6493
6494         if (!netif_running(dev) ||
6495             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6496                 goto out_unlock;
6497
6498         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6499                 bool pending;
6500
6501                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6502                 if (pending)
6503                         rtl_work[i].action(tp);
6504         }
6505
6506 out_unlock:
6507         rtl_unlock_work(tp);
6508 }
6509
6510 static int rtl8169_poll(struct napi_struct *napi, int budget)
6511 {
6512         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6513         struct net_device *dev = tp->dev;
6514         int work_done;
6515
6516         work_done = rtl_rx(dev, tp, (u32) budget);
6517
6518         rtl_tx(dev, tp);
6519
6520         if (work_done < budget) {
6521                 napi_complete_done(napi, work_done);
6522
6523                 rtl_irq_enable(tp);
6524                 mmiowb();
6525         }
6526
6527         return work_done;
6528 }
6529
6530 static void rtl8169_rx_missed(struct net_device *dev)
6531 {
6532         struct rtl8169_private *tp = netdev_priv(dev);
6533
6534         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6535                 return;
6536
6537         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6538         RTL_W32(tp, RxMissed, 0);
6539 }
6540
6541 static void r8169_phylink_handler(struct net_device *ndev)
6542 {
6543         struct rtl8169_private *tp = netdev_priv(ndev);
6544
6545         if (netif_carrier_ok(ndev)) {
6546                 rtl_link_chg_patch(tp);
6547                 pm_request_resume(&tp->pci_dev->dev);
6548         } else {
6549                 pm_runtime_idle(&tp->pci_dev->dev);
6550         }
6551
6552         if (net_ratelimit())
6553                 phy_print_status(ndev->phydev);
6554 }
6555
6556 static int r8169_phy_connect(struct rtl8169_private *tp)
6557 {
6558         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6559         phy_interface_t phy_mode;
6560         int ret;
6561
6562         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6563                    PHY_INTERFACE_MODE_MII;
6564
6565         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6566                                  phy_mode);
6567         if (ret)
6568                 return ret;
6569
6570         if (!tp->supports_gmii)
6571                 phy_set_max_speed(phydev, SPEED_100);
6572
6573         /* Ensure to advertise everything, incl. pause */
6574         linkmode_copy(phydev->advertising, phydev->supported);
6575
6576         phy_attached_info(phydev);
6577
6578         return 0;
6579 }
6580
6581 static void rtl8169_down(struct net_device *dev)
6582 {
6583         struct rtl8169_private *tp = netdev_priv(dev);
6584
6585         phy_stop(dev->phydev);
6586
6587         napi_disable(&tp->napi);
6588         netif_stop_queue(dev);
6589
6590         rtl8169_hw_reset(tp);
6591         /*
6592          * At this point device interrupts can not be enabled in any function,
6593          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6594          * and napi is disabled (rtl8169_poll).
6595          */
6596         rtl8169_rx_missed(dev);
6597
6598         /* Give a racing hard_start_xmit a few cycles to complete. */
6599         synchronize_sched();
6600
6601         rtl8169_tx_clear(tp);
6602
6603         rtl8169_rx_clear(tp);
6604
6605         rtl_pll_power_down(tp);
6606 }
6607
6608 static int rtl8169_close(struct net_device *dev)
6609 {
6610         struct rtl8169_private *tp = netdev_priv(dev);
6611         struct pci_dev *pdev = tp->pci_dev;
6612
6613         pm_runtime_get_sync(&pdev->dev);
6614
6615         /* Update counters before going down */
6616         rtl8169_update_counters(tp);
6617
6618         rtl_lock_work(tp);
6619         /* Clear all task flags */
6620         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6621
6622         rtl8169_down(dev);
6623         rtl_unlock_work(tp);
6624
6625         cancel_work_sync(&tp->wk.work);
6626
6627         phy_disconnect(dev->phydev);
6628
6629         pci_free_irq(pdev, 0, tp);
6630
6631         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6632                           tp->RxPhyAddr);
6633         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6634                           tp->TxPhyAddr);
6635         tp->TxDescArray = NULL;
6636         tp->RxDescArray = NULL;
6637
6638         pm_runtime_put_sync(&pdev->dev);
6639
6640         return 0;
6641 }
6642
6643 #ifdef CONFIG_NET_POLL_CONTROLLER
6644 static void rtl8169_netpoll(struct net_device *dev)
6645 {
6646         struct rtl8169_private *tp = netdev_priv(dev);
6647
6648         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6649 }
6650 #endif
6651
6652 static int rtl_open(struct net_device *dev)
6653 {
6654         struct rtl8169_private *tp = netdev_priv(dev);
6655         struct pci_dev *pdev = tp->pci_dev;
6656         int retval = -ENOMEM;
6657
6658         pm_runtime_get_sync(&pdev->dev);
6659
6660         /*
6661          * Rx and Tx descriptors needs 256 bytes alignment.
6662          * dma_alloc_coherent provides more.
6663          */
6664         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6665                                              &tp->TxPhyAddr, GFP_KERNEL);
6666         if (!tp->TxDescArray)
6667                 goto err_pm_runtime_put;
6668
6669         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6670                                              &tp->RxPhyAddr, GFP_KERNEL);
6671         if (!tp->RxDescArray)
6672                 goto err_free_tx_0;
6673
6674         retval = rtl8169_init_ring(tp);
6675         if (retval < 0)
6676                 goto err_free_rx_1;
6677
6678         INIT_WORK(&tp->wk.work, rtl_task);
6679
6680         smp_mb();
6681
6682         rtl_request_firmware(tp);
6683
6684         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6685                                  dev->name);
6686         if (retval < 0)
6687                 goto err_release_fw_2;
6688
6689         retval = r8169_phy_connect(tp);
6690         if (retval)
6691                 goto err_free_irq;
6692
6693         rtl_lock_work(tp);
6694
6695         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6696
6697         napi_enable(&tp->napi);
6698
6699         rtl8169_init_phy(dev, tp);
6700
6701         rtl_pll_power_up(tp);
6702
6703         rtl_hw_start(tp);
6704
6705         if (!rtl8169_init_counter_offsets(tp))
6706                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6707
6708         phy_start(dev->phydev);
6709         netif_start_queue(dev);
6710
6711         rtl_unlock_work(tp);
6712
6713         pm_runtime_put_sync(&pdev->dev);
6714 out:
6715         return retval;
6716
6717 err_free_irq:
6718         pci_free_irq(pdev, 0, tp);
6719 err_release_fw_2:
6720         rtl_release_firmware(tp);
6721         rtl8169_rx_clear(tp);
6722 err_free_rx_1:
6723         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6724                           tp->RxPhyAddr);
6725         tp->RxDescArray = NULL;
6726 err_free_tx_0:
6727         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6728                           tp->TxPhyAddr);
6729         tp->TxDescArray = NULL;
6730 err_pm_runtime_put:
6731         pm_runtime_put_noidle(&pdev->dev);
6732         goto out;
6733 }
6734
6735 static void
6736 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6737 {
6738         struct rtl8169_private *tp = netdev_priv(dev);
6739         struct pci_dev *pdev = tp->pci_dev;
6740         struct rtl8169_counters *counters = tp->counters;
6741         unsigned int start;
6742
6743         pm_runtime_get_noresume(&pdev->dev);
6744
6745         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6746                 rtl8169_rx_missed(dev);
6747
6748         do {
6749                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6750                 stats->rx_packets = tp->rx_stats.packets;
6751                 stats->rx_bytes = tp->rx_stats.bytes;
6752         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6753
6754         do {
6755                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6756                 stats->tx_packets = tp->tx_stats.packets;
6757                 stats->tx_bytes = tp->tx_stats.bytes;
6758         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6759
6760         stats->rx_dropped       = dev->stats.rx_dropped;
6761         stats->tx_dropped       = dev->stats.tx_dropped;
6762         stats->rx_length_errors = dev->stats.rx_length_errors;
6763         stats->rx_errors        = dev->stats.rx_errors;
6764         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6765         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6766         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6767         stats->multicast        = dev->stats.multicast;
6768
6769         /*
6770          * Fetch additonal counter values missing in stats collected by driver
6771          * from tally counters.
6772          */
6773         if (pm_runtime_active(&pdev->dev))
6774                 rtl8169_update_counters(tp);
6775
6776         /*
6777          * Subtract values fetched during initalization.
6778          * See rtl8169_init_counter_offsets for a description why we do that.
6779          */
6780         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6781                 le64_to_cpu(tp->tc_offset.tx_errors);
6782         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6783                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6784         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6785                 le16_to_cpu(tp->tc_offset.tx_aborted);
6786
6787         pm_runtime_put_noidle(&pdev->dev);
6788 }
6789
6790 static void rtl8169_net_suspend(struct net_device *dev)
6791 {
6792         struct rtl8169_private *tp = netdev_priv(dev);
6793
6794         if (!netif_running(dev))
6795                 return;
6796
6797         phy_stop(dev->phydev);
6798         netif_device_detach(dev);
6799
6800         rtl_lock_work(tp);
6801         napi_disable(&tp->napi);
6802         /* Clear all task flags */
6803         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6804
6805         rtl_unlock_work(tp);
6806
6807         rtl_pll_power_down(tp);
6808 }
6809
6810 #ifdef CONFIG_PM
6811
6812 static int rtl8169_suspend(struct device *device)
6813 {
6814         struct net_device *dev = dev_get_drvdata(device);
6815         struct rtl8169_private *tp = netdev_priv(dev);
6816
6817         rtl8169_net_suspend(dev);
6818         clk_disable_unprepare(tp->clk);
6819
6820         return 0;
6821 }
6822
6823 static void __rtl8169_resume(struct net_device *dev)
6824 {
6825         struct rtl8169_private *tp = netdev_priv(dev);
6826
6827         netif_device_attach(dev);
6828
6829         rtl_pll_power_up(tp);
6830         rtl8169_init_phy(dev, tp);
6831
6832         phy_start(tp->dev->phydev);
6833
6834         rtl_lock_work(tp);
6835         napi_enable(&tp->napi);
6836         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6837         rtl_unlock_work(tp);
6838
6839         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6840 }
6841
6842 static int rtl8169_resume(struct device *device)
6843 {
6844         struct net_device *dev = dev_get_drvdata(device);
6845         struct rtl8169_private *tp = netdev_priv(dev);
6846
6847         clk_prepare_enable(tp->clk);
6848
6849         if (netif_running(dev))
6850                 __rtl8169_resume(dev);
6851
6852         return 0;
6853 }
6854
6855 static int rtl8169_runtime_suspend(struct device *device)
6856 {
6857         struct net_device *dev = dev_get_drvdata(device);
6858         struct rtl8169_private *tp = netdev_priv(dev);
6859
6860         if (!tp->TxDescArray)
6861                 return 0;
6862
6863         rtl_lock_work(tp);
6864         __rtl8169_set_wol(tp, WAKE_ANY);
6865         rtl_unlock_work(tp);
6866
6867         rtl8169_net_suspend(dev);
6868
6869         /* Update counters before going runtime suspend */
6870         rtl8169_rx_missed(dev);
6871         rtl8169_update_counters(tp);
6872
6873         return 0;
6874 }
6875
6876 static int rtl8169_runtime_resume(struct device *device)
6877 {
6878         struct net_device *dev = dev_get_drvdata(device);
6879         struct rtl8169_private *tp = netdev_priv(dev);
6880         rtl_rar_set(tp, dev->dev_addr);
6881
6882         if (!tp->TxDescArray)
6883                 return 0;
6884
6885         rtl_lock_work(tp);
6886         __rtl8169_set_wol(tp, tp->saved_wolopts);
6887         rtl_unlock_work(tp);
6888
6889         __rtl8169_resume(dev);
6890
6891         return 0;
6892 }
6893
6894 static int rtl8169_runtime_idle(struct device *device)
6895 {
6896         struct net_device *dev = dev_get_drvdata(device);
6897
6898         if (!netif_running(dev) || !netif_carrier_ok(dev))
6899                 pm_schedule_suspend(device, 10000);
6900
6901         return -EBUSY;
6902 }
6903
6904 static const struct dev_pm_ops rtl8169_pm_ops = {
6905         .suspend                = rtl8169_suspend,
6906         .resume                 = rtl8169_resume,
6907         .freeze                 = rtl8169_suspend,
6908         .thaw                   = rtl8169_resume,
6909         .poweroff               = rtl8169_suspend,
6910         .restore                = rtl8169_resume,
6911         .runtime_suspend        = rtl8169_runtime_suspend,
6912         .runtime_resume         = rtl8169_runtime_resume,
6913         .runtime_idle           = rtl8169_runtime_idle,
6914 };
6915
6916 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6917
6918 #else /* !CONFIG_PM */
6919
6920 #define RTL8169_PM_OPS  NULL
6921
6922 #endif /* !CONFIG_PM */
6923
6924 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6925 {
6926         /* WoL fails with 8168b when the receiver is disabled. */
6927         switch (tp->mac_version) {
6928         case RTL_GIGA_MAC_VER_11:
6929         case RTL_GIGA_MAC_VER_12:
6930         case RTL_GIGA_MAC_VER_17:
6931                 pci_clear_master(tp->pci_dev);
6932
6933                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6934                 /* PCI commit */
6935                 RTL_R8(tp, ChipCmd);
6936                 break;
6937         default:
6938                 break;
6939         }
6940 }
6941
6942 static void rtl_shutdown(struct pci_dev *pdev)
6943 {
6944         struct net_device *dev = pci_get_drvdata(pdev);
6945         struct rtl8169_private *tp = netdev_priv(dev);
6946
6947         rtl8169_net_suspend(dev);
6948
6949         /* Restore original MAC address */
6950         rtl_rar_set(tp, dev->perm_addr);
6951
6952         rtl8169_hw_reset(tp);
6953
6954         if (system_state == SYSTEM_POWER_OFF) {
6955                 if (tp->saved_wolopts) {
6956                         rtl_wol_suspend_quirk(tp);
6957                         rtl_wol_shutdown_quirk(tp);
6958                 }
6959
6960                 pci_wake_from_d3(pdev, true);
6961                 pci_set_power_state(pdev, PCI_D3hot);
6962         }
6963 }
6964
6965 static void rtl_remove_one(struct pci_dev *pdev)
6966 {
6967         struct net_device *dev = pci_get_drvdata(pdev);
6968         struct rtl8169_private *tp = netdev_priv(dev);
6969
6970         if (r8168_check_dash(tp))
6971                 rtl8168_driver_stop(tp);
6972
6973         netif_napi_del(&tp->napi);
6974
6975         unregister_netdev(dev);
6976         mdiobus_unregister(tp->mii_bus);
6977
6978         rtl_release_firmware(tp);
6979
6980         if (pci_dev_run_wake(pdev))
6981                 pm_runtime_get_noresume(&pdev->dev);
6982
6983         /* restore original MAC address */
6984         rtl_rar_set(tp, dev->perm_addr);
6985 }
6986
6987 static const struct net_device_ops rtl_netdev_ops = {
6988         .ndo_open               = rtl_open,
6989         .ndo_stop               = rtl8169_close,
6990         .ndo_get_stats64        = rtl8169_get_stats64,
6991         .ndo_start_xmit         = rtl8169_start_xmit,
6992         .ndo_tx_timeout         = rtl8169_tx_timeout,
6993         .ndo_validate_addr      = eth_validate_addr,
6994         .ndo_change_mtu         = rtl8169_change_mtu,
6995         .ndo_fix_features       = rtl8169_fix_features,
6996         .ndo_set_features       = rtl8169_set_features,
6997         .ndo_set_mac_address    = rtl_set_mac_address,
6998         .ndo_do_ioctl           = rtl8169_ioctl,
6999         .ndo_set_rx_mode        = rtl_set_rx_mode,
7000 #ifdef CONFIG_NET_POLL_CONTROLLER
7001         .ndo_poll_controller    = rtl8169_netpoll,
7002 #endif
7003
7004 };
7005
7006 static const struct rtl_cfg_info {
7007         void (*hw_start)(struct rtl8169_private *tp);
7008         u16 irq_mask;
7009         unsigned int has_gmii:1;
7010         const struct rtl_coalesce_info *coalesce_info;
7011         u8 default_ver;
7012 } rtl_cfg_infos [] = {
7013         [RTL_CFG_0] = {
7014                 .hw_start       = rtl_hw_start_8169,
7015                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7016                 .has_gmii       = 1,
7017                 .coalesce_info  = rtl_coalesce_info_8169,
7018                 .default_ver    = RTL_GIGA_MAC_VER_01,
7019         },
7020         [RTL_CFG_1] = {
7021                 .hw_start       = rtl_hw_start_8168,
7022                 .irq_mask       = LinkChg | RxOverflow,
7023                 .has_gmii       = 1,
7024                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7025                 .default_ver    = RTL_GIGA_MAC_VER_11,
7026         },
7027         [RTL_CFG_2] = {
7028                 .hw_start       = rtl_hw_start_8101,
7029                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
7030                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7031                 .default_ver    = RTL_GIGA_MAC_VER_13,
7032         }
7033 };
7034
7035 static int rtl_alloc_irq(struct rtl8169_private *tp)
7036 {
7037         unsigned int flags;
7038
7039         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7040                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7041                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7042                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7043                 flags = PCI_IRQ_LEGACY;
7044         } else {
7045                 flags = PCI_IRQ_ALL_TYPES;
7046         }
7047
7048         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7049 }
7050
7051 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7052 {
7053         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7054 }
7055
7056 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7057 {
7058         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7059 }
7060
7061 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7062 {
7063         struct rtl8169_private *tp = mii_bus->priv;
7064
7065         if (phyaddr > 0)
7066                 return -ENODEV;
7067
7068         return rtl_readphy(tp, phyreg);
7069 }
7070
7071 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7072                                 int phyreg, u16 val)
7073 {
7074         struct rtl8169_private *tp = mii_bus->priv;
7075
7076         if (phyaddr > 0)
7077                 return -ENODEV;
7078
7079         rtl_writephy(tp, phyreg, val);
7080
7081         return 0;
7082 }
7083
7084 static int r8169_mdio_register(struct rtl8169_private *tp)
7085 {
7086         struct pci_dev *pdev = tp->pci_dev;
7087         struct phy_device *phydev;
7088         struct mii_bus *new_bus;
7089         int ret;
7090
7091         new_bus = devm_mdiobus_alloc(&pdev->dev);
7092         if (!new_bus)
7093                 return -ENOMEM;
7094
7095         new_bus->name = "r8169";
7096         new_bus->priv = tp;
7097         new_bus->parent = &pdev->dev;
7098         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7099         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7100                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7101
7102         new_bus->read = r8169_mdio_read_reg;
7103         new_bus->write = r8169_mdio_write_reg;
7104
7105         ret = mdiobus_register(new_bus);
7106         if (ret)
7107                 return ret;
7108
7109         phydev = mdiobus_get_phy(new_bus, 0);
7110         if (!phydev) {
7111                 mdiobus_unregister(new_bus);
7112                 return -ENODEV;
7113         }
7114
7115         /* PHY will be woken up in rtl_open() */
7116         phy_suspend(phydev);
7117
7118         tp->mii_bus = new_bus;
7119
7120         return 0;
7121 }
7122
7123 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7124 {
7125         u32 data;
7126
7127         tp->ocp_base = OCP_STD_PHY_BASE;
7128
7129         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7130
7131         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7132                 return;
7133
7134         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7135                 return;
7136
7137         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7138         msleep(1);
7139         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7140
7141         data = r8168_mac_ocp_read(tp, 0xe8de);
7142         data &= ~(1 << 14);
7143         r8168_mac_ocp_write(tp, 0xe8de, data);
7144
7145         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7146                 return;
7147
7148         data = r8168_mac_ocp_read(tp, 0xe8de);
7149         data |= (1 << 15);
7150         r8168_mac_ocp_write(tp, 0xe8de, data);
7151
7152         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7153                 return;
7154 }
7155
7156 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7157 {
7158         rtl8168ep_stop_cmac(tp);
7159         rtl_hw_init_8168g(tp);
7160 }
7161
7162 static void rtl_hw_initialize(struct rtl8169_private *tp)
7163 {
7164         switch (tp->mac_version) {
7165         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7166                 rtl_hw_init_8168g(tp);
7167                 break;
7168         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7169                 rtl_hw_init_8168ep(tp);
7170                 break;
7171         default:
7172                 break;
7173         }
7174 }
7175
7176 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7177 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7178 {
7179         switch (tp->mac_version) {
7180         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7181         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7182                 return false;
7183         default:
7184                 return true;
7185         }
7186 }
7187
7188 static int rtl_jumbo_max(struct rtl8169_private *tp)
7189 {
7190         /* Non-GBit versions don't support jumbo frames */
7191         if (!tp->supports_gmii)
7192                 return JUMBO_1K;
7193
7194         switch (tp->mac_version) {
7195         /* RTL8169 */
7196         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7197                 return JUMBO_7K;
7198         /* RTL8168b */
7199         case RTL_GIGA_MAC_VER_11:
7200         case RTL_GIGA_MAC_VER_12:
7201         case RTL_GIGA_MAC_VER_17:
7202                 return JUMBO_4K;
7203         /* RTL8168c */
7204         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7205                 return JUMBO_6K;
7206         default:
7207                 return JUMBO_9K;
7208         }
7209 }
7210
7211 static void rtl_disable_clk(void *data)
7212 {
7213         clk_disable_unprepare(data);
7214 }
7215
7216 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7217 {
7218         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7219         struct rtl8169_private *tp;
7220         struct net_device *dev;
7221         int chipset, region, i;
7222         int jumbo_max, rc;
7223
7224         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7225         if (!dev)
7226                 return -ENOMEM;
7227
7228         SET_NETDEV_DEV(dev, &pdev->dev);
7229         dev->netdev_ops = &rtl_netdev_ops;
7230         tp = netdev_priv(dev);
7231         tp->dev = dev;
7232         tp->pci_dev = pdev;
7233         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7234         tp->supports_gmii = cfg->has_gmii;
7235
7236         /* Get the *optional* external "ether_clk" used on some boards */
7237         tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7238         if (IS_ERR(tp->clk)) {
7239                 rc = PTR_ERR(tp->clk);
7240                 if (rc == -ENOENT) {
7241                         /* clk-core allows NULL (for suspend / resume) */
7242                         tp->clk = NULL;
7243                 } else if (rc == -EPROBE_DEFER) {
7244                         return rc;
7245                 } else {
7246                         dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7247                         return rc;
7248                 }
7249         } else {
7250                 rc = clk_prepare_enable(tp->clk);
7251                 if (rc) {
7252                         dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7253                         return rc;
7254                 }
7255
7256                 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7257                                               tp->clk);
7258                 if (rc)
7259                         return rc;
7260         }
7261
7262         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7263         rc = pcim_enable_device(pdev);
7264         if (rc < 0) {
7265                 dev_err(&pdev->dev, "enable failure\n");
7266                 return rc;
7267         }
7268
7269         if (pcim_set_mwi(pdev) < 0)
7270                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7271
7272         /* use first MMIO region */
7273         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7274         if (region < 0) {
7275                 dev_err(&pdev->dev, "no MMIO resource found\n");
7276                 return -ENODEV;
7277         }
7278
7279         /* check for weird/broken PCI region reporting */
7280         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7281                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7282                 return -ENODEV;
7283         }
7284
7285         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7286         if (rc < 0) {
7287                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7288                 return rc;
7289         }
7290
7291         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7292
7293         /* Identify chip attached to board */
7294         rtl8169_get_mac_version(tp, cfg->default_ver);
7295
7296         if (rtl_tbi_enabled(tp)) {
7297                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7298                 return -ENODEV;
7299         }
7300
7301         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7302
7303         if (sizeof(dma_addr_t) > 4 && (use_dac == 1 || (use_dac == -1 &&
7304             tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7305             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7306
7307                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7308                 if (!pci_is_pcie(pdev))
7309                         tp->cp_cmd |= PCIDAC;
7310                 dev->features |= NETIF_F_HIGHDMA;
7311         } else {
7312                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7313                 if (rc < 0) {
7314                         dev_err(&pdev->dev, "DMA configuration failed\n");
7315                         return rc;
7316                 }
7317         }
7318
7319         rtl_init_rxcfg(tp);
7320
7321         rtl8169_irq_mask_and_ack(tp);
7322
7323         rtl_hw_initialize(tp);
7324
7325         rtl_hw_reset(tp);
7326
7327         pci_set_master(pdev);
7328
7329         rtl_init_mdio_ops(tp);
7330         rtl_init_jumbo_ops(tp);
7331
7332         chipset = tp->mac_version;
7333
7334         rc = rtl_alloc_irq(tp);
7335         if (rc < 0) {
7336                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7337                 return rc;
7338         }
7339
7340         tp->saved_wolopts = __rtl8169_get_wol(tp);
7341
7342         mutex_init(&tp->wk.mutex);
7343         u64_stats_init(&tp->rx_stats.syncp);
7344         u64_stats_init(&tp->tx_stats.syncp);
7345
7346         /* Get MAC address */
7347         switch (tp->mac_version) {
7348                 u8 mac_addr[ETH_ALEN] __aligned(4);
7349         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7350         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7351                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7352                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7353
7354                 if (is_valid_ether_addr(mac_addr))
7355                         rtl_rar_set(tp, mac_addr);
7356                 break;
7357         default:
7358                 break;
7359         }
7360         for (i = 0; i < ETH_ALEN; i++)
7361                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7362
7363         dev->ethtool_ops = &rtl8169_ethtool_ops;
7364
7365         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7366
7367         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7368          * properly for all devices */
7369         dev->features |= NETIF_F_RXCSUM |
7370                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7371
7372         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7373                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7374                 NETIF_F_HW_VLAN_CTAG_RX;
7375         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7376                 NETIF_F_HIGHDMA;
7377         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7378
7379         tp->cp_cmd |= RxChkSum | RxVlan;
7380
7381         /*
7382          * Pretend we are using VLANs; This bypasses a nasty bug where
7383          * Interrupts stop flowing on high load on 8110SCd controllers.
7384          */
7385         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7386                 /* Disallow toggling */
7387                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7388
7389         if (rtl_chip_supports_csum_v2(tp)) {
7390                 tp->tso_csum = rtl8169_tso_csum_v2;
7391                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7392         } else {
7393                 tp->tso_csum = rtl8169_tso_csum_v1;
7394         }
7395
7396         dev->hw_features |= NETIF_F_RXALL;
7397         dev->hw_features |= NETIF_F_RXFCS;
7398
7399         /* MTU range: 60 - hw-specific max */
7400         dev->min_mtu = ETH_ZLEN;
7401         jumbo_max = rtl_jumbo_max(tp);
7402         dev->max_mtu = jumbo_max;
7403
7404         tp->hw_start = cfg->hw_start;
7405         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7406         tp->coalesce_info = cfg->coalesce_info;
7407
7408         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7409
7410         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7411                                             &tp->counters_phys_addr,
7412                                             GFP_KERNEL);
7413         if (!tp->counters)
7414                 return -ENOMEM;
7415
7416         pci_set_drvdata(pdev, dev);
7417
7418         rc = r8169_mdio_register(tp);
7419         if (rc)
7420                 return rc;
7421
7422         /* chip gets powered up in rtl_open() */
7423         rtl_pll_power_down(tp);
7424
7425         rc = register_netdev(dev);
7426         if (rc)
7427                 goto err_mdio_unregister;
7428
7429         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7430                    rtl_chip_infos[chipset].name, dev->dev_addr,
7431                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7432                    pci_irq_vector(pdev, 0));
7433
7434         if (jumbo_max > JUMBO_1K)
7435                 netif_info(tp, probe, dev,
7436                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7437                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7438                            "ok" : "ko");
7439
7440         if (r8168_check_dash(tp))
7441                 rtl8168_driver_start(tp);
7442
7443         if (pci_dev_run_wake(pdev))
7444                 pm_runtime_put_sync(&pdev->dev);
7445
7446         return 0;
7447
7448 err_mdio_unregister:
7449         mdiobus_unregister(tp->mii_bus);
7450         return rc;
7451 }
7452
7453 static struct pci_driver rtl8169_pci_driver = {
7454         .name           = MODULENAME,
7455         .id_table       = rtl8169_pci_tbl,
7456         .probe          = rtl_init_one,
7457         .remove         = rtl_remove_one,
7458         .shutdown       = rtl_shutdown,
7459         .driver.pm      = RTL8169_PM_OPS,
7460 };
7461
7462 module_pci_driver(rtl8169_pci_driver);