drivers/net/ethernet/realtek/r8169.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/firmware.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pci-aspm.h>
  33 #include <linux/ipv6.h>
  34 #include <net/ip6_checksum.h>
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63 static const int multicast_filter_limit = 32;
  64
  65 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68 #define R8169_REGS_SIZE         256
  69 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75 /* write/read MMIO register */
  76 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  79 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  80 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  81 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  82
  83 enum mac_version {
  84         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  85         RTL_GIGA_MAC_VER_02,
  86         RTL_GIGA_MAC_VER_03,
  87         RTL_GIGA_MAC_VER_04,
  88         RTL_GIGA_MAC_VER_05,
  89         RTL_GIGA_MAC_VER_06,
  90         RTL_GIGA_MAC_VER_07,
  91         RTL_GIGA_MAC_VER_08,
  92         RTL_GIGA_MAC_VER_09,
  93         RTL_GIGA_MAC_VER_10,
  94         RTL_GIGA_MAC_VER_11,
  95         RTL_GIGA_MAC_VER_12,
  96         RTL_GIGA_MAC_VER_13,
  97         RTL_GIGA_MAC_VER_14,
  98         RTL_GIGA_MAC_VER_15,
  99         RTL_GIGA_MAC_VER_16,
 100         RTL_GIGA_MAC_VER_17,
 101         RTL_GIGA_MAC_VER_18,
 102         RTL_GIGA_MAC_VER_19,
 103         RTL_GIGA_MAC_VER_20,
 104         RTL_GIGA_MAC_VER_21,
 105         RTL_GIGA_MAC_VER_22,
 106         RTL_GIGA_MAC_VER_23,
 107         RTL_GIGA_MAC_VER_24,
 108         RTL_GIGA_MAC_VER_25,
 109         RTL_GIGA_MAC_VER_26,
 110         RTL_GIGA_MAC_VER_27,
 111         RTL_GIGA_MAC_VER_28,
 112         RTL_GIGA_MAC_VER_29,
 113         RTL_GIGA_MAC_VER_30,
 114         RTL_GIGA_MAC_VER_31,
 115         RTL_GIGA_MAC_VER_32,
 116         RTL_GIGA_MAC_VER_33,
 117         RTL_GIGA_MAC_VER_34,
 118         RTL_GIGA_MAC_VER_35,
 119         RTL_GIGA_MAC_VER_36,
 120         RTL_GIGA_MAC_VER_37,
 121         RTL_GIGA_MAC_VER_38,
 122         RTL_GIGA_MAC_VER_39,
 123         RTL_GIGA_MAC_VER_40,
 124         RTL_GIGA_MAC_VER_41,
 125         RTL_GIGA_MAC_VER_42,
 126         RTL_GIGA_MAC_VER_43,
 127         RTL_GIGA_MAC_VER_44,
 128         RTL_GIGA_MAC_VER_45,
 129         RTL_GIGA_MAC_VER_46,
 130         RTL_GIGA_MAC_VER_47,
 131         RTL_GIGA_MAC_VER_48,
 132         RTL_GIGA_MAC_VER_49,
 133         RTL_GIGA_MAC_VER_50,
 134         RTL_GIGA_MAC_VER_51,
 135         RTL_GIGA_MAC_NONE
 136 };
 137
 138 #define JUMBO_1K        ETH_DATA_LEN
 139 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 140 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 141 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 142 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 143
 144 static const struct {
 145         const char *name;
 146         const char *fw_name;
 147 } rtl_chip_infos[] = {
 148         /* PCI devices. */
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxRWT   = (1 << 22),
 409         RxRES   = (1 << 21),
 410         RxRUNT  = (1 << 20),
 411         RxCRC   = (1 << 19),
 412
 413         /* ChipCmdBits */
 414         StopReq         = 0x80,
 415         CmdReset        = 0x10,
 416         CmdRxEnb        = 0x08,
 417         CmdTxEnb        = 0x04,
 418         RxBufEmpty      = 0x01,
 419
 420         /* TXPoll register p.5 */
 421         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 422         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 423         FSWInt          = 0x01,         /* Forced software interrupt */
 424
 425         /* Cfg9346Bits */
 426         Cfg9346_Lock    = 0x00,
 427         Cfg9346_Unlock  = 0xc0,
 428
 429         /* rx_mode_bits */
 430         AcceptErr       = 0x20,
 431         AcceptRunt      = 0x10,
 432         AcceptBroadcast = 0x08,
 433         AcceptMulticast = 0x04,
 434         AcceptMyPhys    = 0x02,
 435         AcceptAllPhys   = 0x01,
 436 #define RX_CONFIG_ACCEPT_MASK           0x3f
 437
 438         /* TxConfigBits */
 439         TxInterFrameGapShift = 24,
 440         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 441
 442         /* Config1 register p.24 */
 443         LEDS1           = (1 << 7),
 444         LEDS0           = (1 << 6),
 445         Speed_down      = (1 << 4),
 446         MEMMAP          = (1 << 3),
 447         IOMAP           = (1 << 2),
 448         VPD             = (1 << 1),
 449         PMEnable        = (1 << 0),     /* Power Management Enable */
 450
 451         /* Config2 register p. 25 */
 452         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 453         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 454         PCI_Clock_66MHz = 0x01,
 455         PCI_Clock_33MHz = 0x00,
 456
 457         /* Config3 register p.25 */
 458         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 459         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 460         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 461         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 462         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 463
 464         /* Config4 register */
 465         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 466
 467         /* Config5 register p.27 */
 468         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 469         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 470         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 471         Spi_en          = (1 << 3),
 472         LanWake         = (1 << 1),     /* LanWake enable/disable */
 473         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 474         ASPM_en         = (1 << 0),     /* ASPM enable */
 475
 476         /* CPlusCmd p.31 */
 477         EnableBist      = (1 << 15),    // 8168 8101
 478         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 479         Normal_mode     = (1 << 13),    // unused
 480         Force_half_dup  = (1 << 12),    // 8168 8101
 481         Force_rxflow_en = (1 << 11),    // 8168 8101
 482         Force_txflow_en = (1 << 10),    // 8168 8101
 483         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 484         ASF             = (1 << 8),     // 8168 8101
 485         PktCntrDisable  = (1 << 7),     // 8168 8101
 486         Mac_dbgo_sel    = 0x001c,       // 8168
 487         RxVlan          = (1 << 6),
 488         RxChkSum        = (1 << 5),
 489         PCIDAC          = (1 << 4),
 490         PCIMulRW        = (1 << 3),
 491 #define INTT_MASK       GENMASK(1, 0)
 492
 493         /* rtl8169_PHYstatus */
 494         TBI_Enable      = 0x80,
 495         TxFlowCtrl      = 0x40,
 496         RxFlowCtrl      = 0x20,
 497         _1000bpsF       = 0x10,
 498         _100bps         = 0x08,
 499         _10bps          = 0x04,
 500         LinkStatus      = 0x02,
 501         FullDup         = 0x01,
 502
 503         /* ResetCounterCommand */
 504         CounterReset    = 0x1,
 505
 506         /* DumpCounterCommand */
 507         CounterDump     = 0x8,
 508
 509         /* magic enable v2 */
 510         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 511 };
 512
 513 enum rtl_desc_bit {
 514         /* First doubleword. */
 515         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 516         RingEnd         = (1 << 30), /* End of descriptor ring */
 517         FirstFrag       = (1 << 29), /* First segment of a packet */
 518         LastFrag        = (1 << 28), /* Final segment of a packet */
 519 };
 520
 521 /* Generic case. */
 522 enum rtl_tx_desc_bit {
 523         /* First doubleword. */
 524         TD_LSO          = (1 << 27),            /* Large Send Offload */
 525 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 526
 527         /* Second doubleword. */
 528         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 529 };
 530
 531 /* 8169, 8168b and 810x except 8102e. */
 532 enum rtl_tx_desc_bit_0 {
 533         /* First doubleword. */
 534 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 535         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 536         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 537         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 538 };
 539
 540 /* 8102e, 8168c and beyond. */
 541 enum rtl_tx_desc_bit_1 {
 542         /* First doubleword. */
 543         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 544         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 545 #define GTTCPHO_SHIFT                   18
 546 #define GTTCPHO_MAX                     0x7fU
 547
 548         /* Second doubleword. */
 549 #define TCPHO_SHIFT                     18
 550 #define TCPHO_MAX                       0x3ffU
 551 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 552         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 553         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 554         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 555         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 556 };
 557
 558 enum rtl_rx_desc_bit {
 559         /* Rx private */
 560         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 561         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 562
 563 #define RxProtoUDP      (PID1)
 564 #define RxProtoTCP      (PID0)
 565 #define RxProtoIP       (PID1 | PID0)
 566 #define RxProtoMask     RxProtoIP
 567
 568         IPFail          = (1 << 16), /* IP checksum failed */
 569         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 570         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 571         RxVlanTag       = (1 << 16), /* VLAN tag available */
 572 };
 573
 574 #define RsvdMask        0x3fffc000
 575 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 576
 577 struct TxDesc {
 578         __le32 opts1;
 579         __le32 opts2;
 580         __le64 addr;
 581 };
 582
 583 struct RxDesc {
 584         __le32 opts1;
 585         __le32 opts2;
 586         __le64 addr;
 587 };
 588
 589 struct ring_info {
 590         struct sk_buff  *skb;
 591         u32             len;
 592 };
 593
 594 struct rtl8169_counters {
 595         __le64  tx_packets;
 596         __le64  rx_packets;
 597         __le64  tx_errors;
 598         __le32  rx_errors;
 599         __le16  rx_missed;
 600         __le16  align_errors;
 601         __le32  tx_one_collision;
 602         __le32  tx_multi_collision;
 603         __le64  rx_unicast;
 604         __le64  rx_broadcast;
 605         __le32  rx_multicast;
 606         __le16  tx_aborted;
 607         __le16  tx_underun;
 608 };
 609
 610 struct rtl8169_tc_offsets {
 611         bool    inited;
 612         __le64  tx_errors;
 613         __le32  tx_multi_collision;
 614         __le16  tx_aborted;
 615 };
 616
 617 enum rtl_flag {
 618         RTL_FLAG_TASK_ENABLED = 0,
 619         RTL_FLAG_TASK_RESET_PENDING,
 620         RTL_FLAG_MAX
 621 };
 622
 623 struct rtl8169_stats {
 624         u64                     packets;
 625         u64                     bytes;
 626         struct u64_stats_sync   syncp;
 627 };
 628
 629 struct rtl8169_private;
 630 typedef void (*rtl_fw_write_t)(struct rtl8169_private *tp, int reg, int val);
 631 typedef int (*rtl_fw_read_t)(struct rtl8169_private *tp, int reg);
 632
 633 struct rtl8169_private {
 634         void __iomem *mmio_addr;        /* memory map physical address */
 635         struct pci_dev *pci_dev;
 636         struct net_device *dev;
 637         struct phy_device *phydev;
 638         struct napi_struct napi;
 639         u32 msg_enable;
 640         enum mac_version mac_version;
 641         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 642         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 643         u32 dirty_tx;
 644         struct rtl8169_stats rx_stats;
 645         struct rtl8169_stats tx_stats;
 646         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 647         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 648         dma_addr_t TxPhyAddr;
 649         dma_addr_t RxPhyAddr;
 650         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 651         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 652         u16 cp_cmd;
 653
 654         u16 irq_mask;
 655         const struct rtl_coalesce_info *coalesce_info;
 656         struct clk *clk;
 657
 658         void (*hw_start)(struct rtl8169_private *tp);
 659
 660         struct {
 661                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 662                 struct mutex mutex;
 663                 struct work_struct work;
 664         } wk;
 665
 666         unsigned irq_enabled:1;
 667         unsigned supports_gmii:1;
 668         dma_addr_t counters_phys_addr;
 669         struct rtl8169_counters *counters;
 670         struct rtl8169_tc_offsets tc_offset;
 671         u32 saved_wolopts;
 672
 673         const char *fw_name;
 674         struct rtl_fw {
 675                 rtl_fw_write_t phy_write;
 676                 rtl_fw_read_t phy_read;
 677                 rtl_fw_write_t mac_mcu_write;
 678                 rtl_fw_read_t mac_mcu_read;
 679                 const struct firmware *fw;
 680
 681 #define RTL_VER_SIZE            32
 682
 683                 char version[RTL_VER_SIZE];
 684
 685                 struct rtl_fw_phy_action {
 686                         __le32 *code;
 687                         size_t size;
 688                 } phy_action;
 689         } *rtl_fw;
 690
 691         u32 ocp_base;
 692 };
 693
 694 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 695
 696 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 697 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 698 module_param_named(debug, debug.msg_enable, int, 0);
 699 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 700 MODULE_SOFTDEP("pre: realtek");
 701 MODULE_LICENSE("GPL");
 702 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 703 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 704 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 705 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 706 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 707 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 708 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 709 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 710 MODULE_FIRMWARE(FIRMWARE_8402_1);
 711 MODULE_FIRMWARE(FIRMWARE_8411_1);
 712 MODULE_FIRMWARE(FIRMWARE_8411_2);
 713 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 714 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 715 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 716 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 717 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 719 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 720 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 721
 722 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 723 {
 724         return &tp->pci_dev->dev;
 725 }
 726
 727 static void rtl_lock_work(struct rtl8169_private *tp)
 728 {
 729         mutex_lock(&tp->wk.mutex);
 730 }
 731
 732 static void rtl_unlock_work(struct rtl8169_private *tp)
 733 {
 734         mutex_unlock(&tp->wk.mutex);
 735 }
 736
 737 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 738 {
 739         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 740 }
 741
 742 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 743 {
 744         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 745 }
 746
 747 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 748 {
 749         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 750                                            PCI_EXP_DEVCTL_READRQ, force);
 751 }
 752
 753 struct rtl_cond {
 754         bool (*check)(struct rtl8169_private *);
 755         const char *msg;
 756 };
 757
 758 static void rtl_udelay(unsigned int d)
 759 {
 760         udelay(d);
 761 }
 762
 763 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 764                           void (*delay)(unsigned int), unsigned int d, int n,
 765                           bool high)
 766 {
 767         int i;
 768
 769         for (i = 0; i < n; i++) {
 770                 if (c->check(tp) == high)
 771                         return true;
 772                 delay(d);
 773         }
 774         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 775                   c->msg, !high, n, d);
 776         return false;
 777 }
 778
 779 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 780                                       const struct rtl_cond *c,
 781                                       unsigned int d, int n)
 782 {
 783         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 784 }
 785
 786 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 787                                      const struct rtl_cond *c,
 788                                      unsigned int d, int n)
 789 {
 790         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 791 }
 792
 793 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 794                                       const struct rtl_cond *c,
 795                                       unsigned int d, int n)
 796 {
 797         return rtl_loop_wait(tp, c, msleep, d, n, true);
 798 }
 799
 800 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 801                                      const struct rtl_cond *c,
 802                                      unsigned int d, int n)
 803 {
 804         return rtl_loop_wait(tp, c, msleep, d, n, false);
 805 }
 806
 807 #define DECLARE_RTL_COND(name)                          \
 808 static bool name ## _check(struct rtl8169_private *);   \
 809                                                         \
 810 static const struct rtl_cond name = {                   \
 811         .check  = name ## _check,                       \
 812         .msg    = #name                                 \
 813 };                                                      \
 814                                                         \
 815 static bool name ## _check(struct rtl8169_private *tp)
 816
 817 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 818 {
 819         if (reg & 0xffff0001) {
 820                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 821                 return true;
 822         }
 823         return false;
 824 }
 825
 826 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 827 {
 828         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 829 }
 830
 831 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 832 {
 833         if (rtl_ocp_reg_failure(tp, reg))
 834                 return;
 835
 836         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 837
 838         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 839 }
 840
 841 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 842 {
 843         if (rtl_ocp_reg_failure(tp, reg))
 844                 return 0;
 845
 846         RTL_W32(tp, GPHY_OCP, reg << 15);
 847
 848         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 849                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 850 }
 851
 852 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 853 {
 854         if (rtl_ocp_reg_failure(tp, reg))
 855                 return;
 856
 857         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 858 }
 859
 860 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 861 {
 862         if (rtl_ocp_reg_failure(tp, reg))
 863                 return 0;
 864
 865         RTL_W32(tp, OCPDR, reg << 15);
 866
 867         return RTL_R32(tp, OCPDR);
 868 }
 869
 870 #define OCP_STD_PHY_BASE        0xa400
 871
 872 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 873 {
 874         if (reg == 0x1f) {
 875                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 876                 return;
 877         }
 878
 879         if (tp->ocp_base != OCP_STD_PHY_BASE)
 880                 reg -= 0x10;
 881
 882         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 883 }
 884
 885 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 886 {
 887         if (tp->ocp_base != OCP_STD_PHY_BASE)
 888                 reg -= 0x10;
 889
 890         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 891 }
 892
 893 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 894 {
 895         if (reg == 0x1f) {
 896                 tp->ocp_base = value << 4;
 897                 return;
 898         }
 899
 900         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 901 }
 902
 903 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 904 {
 905         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 906 }
 907
 908 DECLARE_RTL_COND(rtl_phyar_cond)
 909 {
 910         return RTL_R32(tp, PHYAR) & 0x80000000;
 911 }
 912
 913 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 914 {
 915         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 916
 917         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 918         /*
 919          * According to hardware specs a 20us delay is required after write
 920          * complete indication, but before sending next command.
 921          */
 922         udelay(20);
 923 }
 924
 925 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 926 {
 927         int value;
 928
 929         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 930
 931         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 932                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 933
 934         /*
 935          * According to hardware specs a 20us delay is required after read
 936          * complete indication, but before sending next command.
 937          */
 938         udelay(20);
 939
 940         return value;
 941 }
 942
 943 DECLARE_RTL_COND(rtl_ocpar_cond)
 944 {
 945         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 946 }
 947
 948 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 949 {
 950         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 951         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 952         RTL_W32(tp, EPHY_RXER_NUM, 0);
 953
 954         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 955 }
 956
 957 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 958 {
 959         r8168dp_1_mdio_access(tp, reg,
 960                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 961 }
 962
 963 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 964 {
 965         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 966
 967         mdelay(1);
 968         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 969         RTL_W32(tp, EPHY_RXER_NUM, 0);
 970
 971         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 972                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 973 }
 974
 975 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 976
 977 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 978 {
 979         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 980 }
 981
 982 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 983 {
 984         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 985 }
 986
 987 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 988 {
 989         r8168dp_2_mdio_start(tp);
 990
 991         r8169_mdio_write(tp, reg, value);
 992
 993         r8168dp_2_mdio_stop(tp);
 994 }
 995
 996 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 997 {
 998         int value;
 999
1000         r8168dp_2_mdio_start(tp);
1001
1002         value = r8169_mdio_read(tp, reg);
1003
1004         r8168dp_2_mdio_stop(tp);
1005
1006         return value;
1007 }
1008
1009 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1010 {
1011         switch (tp->mac_version) {
1012         case RTL_GIGA_MAC_VER_27:
1013                 r8168dp_1_mdio_write(tp, location, val);
1014                 break;
1015         case RTL_GIGA_MAC_VER_28:
1016         case RTL_GIGA_MAC_VER_31:
1017                 r8168dp_2_mdio_write(tp, location, val);
1018                 break;
1019         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1020                 r8168g_mdio_write(tp, location, val);
1021                 break;
1022         default:
1023                 r8169_mdio_write(tp, location, val);
1024                 break;
1025         }
1026 }
1027
1028 static int rtl_readphy(struct rtl8169_private *tp, int location)
1029 {
1030         switch (tp->mac_version) {
1031         case RTL_GIGA_MAC_VER_27:
1032                 return r8168dp_1_mdio_read(tp, location);
1033         case RTL_GIGA_MAC_VER_28:
1034         case RTL_GIGA_MAC_VER_31:
1035                 return r8168dp_2_mdio_read(tp, location);
1036         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1037                 return r8168g_mdio_read(tp, location);
1038         default:
1039                 return r8169_mdio_read(tp, location);
1040         }
1041 }
1042
1043 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1044 {
1045         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1046 }
1047
1048 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1049 {
1050         int val;
1051
1052         val = rtl_readphy(tp, reg_addr);
1053         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1054 }
1055
1056 DECLARE_RTL_COND(rtl_ephyar_cond)
1057 {
1058         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1059 }
1060
1061 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1062 {
1063         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1064                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1065
1066         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1067
1068         udelay(10);
1069 }
1070
1071 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1072 {
1073         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1074
1075         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1076                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1077 }
1078
1079 DECLARE_RTL_COND(rtl_eriar_cond)
1080 {
1081         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1082 }
1083
1084 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1085                            u32 val, int type)
1086 {
1087         BUG_ON((addr & 3) || (mask == 0));
1088         RTL_W32(tp, ERIDR, val);
1089         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1090
1091         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1092 }
1093
1094 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1095                           u32 val)
1096 {
1097         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1098 }
1099
1100 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1101 {
1102         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1103
1104         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1105                 RTL_R32(tp, ERIDR) : ~0;
1106 }
1107
1108 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1109 {
1110         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1111 }
1112
1113 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1114                          u32 m)
1115 {
1116         u32 val;
1117
1118         val = rtl_eri_read(tp, addr);
1119         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1120 }
1121
1122 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1123                              u32 p)
1124 {
1125         rtl_w0w1_eri(tp, addr, mask, p, 0);
1126 }
1127
1128 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1129                                u32 m)
1130 {
1131         rtl_w0w1_eri(tp, addr, mask, 0, m);
1132 }
1133
1134 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1135 {
1136         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1137         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1138                 RTL_R32(tp, OCPDR) : ~0;
1139 }
1140
1141 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1142 {
1143         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1144 }
1145
1146 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1147                               u32 data)
1148 {
1149         RTL_W32(tp, OCPDR, data);
1150         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1151         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1152 }
1153
1154 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1155                               u32 data)
1156 {
1157         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1158                        data, ERIAR_OOB);
1159 }
1160
1161 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1162 {
1163         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1164
1165         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1166 }
1167
1168 #define OOB_CMD_RESET           0x00
1169 #define OOB_CMD_DRIVER_START    0x05
1170 #define OOB_CMD_DRIVER_STOP     0x06
1171
1172 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1173 {
1174         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1175 }
1176
1177 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1178 {
1179         u16 reg;
1180
1181         reg = rtl8168_get_ocp_reg(tp);
1182
1183         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1184 }
1185
1186 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1187 {
1188         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1189 }
1190
1191 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1192 {
1193         return RTL_R8(tp, IBISR0) & 0x20;
1194 }
1195
1196 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1197 {
1198         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1199         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1200         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1201         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1202 }
1203
1204 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1205 {
1206         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1207         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1208 }
1209
1210 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1211 {
1212         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1213         r8168ep_ocp_write(tp, 0x01, 0x30,
1214                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1215         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1216 }
1217
1218 static void rtl8168_driver_start(struct rtl8169_private *tp)
1219 {
1220         switch (tp->mac_version) {
1221         case RTL_GIGA_MAC_VER_27:
1222         case RTL_GIGA_MAC_VER_28:
1223         case RTL_GIGA_MAC_VER_31:
1224                 rtl8168dp_driver_start(tp);
1225                 break;
1226         case RTL_GIGA_MAC_VER_49:
1227         case RTL_GIGA_MAC_VER_50:
1228         case RTL_GIGA_MAC_VER_51:
1229                 rtl8168ep_driver_start(tp);
1230                 break;
1231         default:
1232                 BUG();
1233                 break;
1234         }
1235 }
1236
1237 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1238 {
1239         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1240         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1241 }
1242
1243 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1244 {
1245         rtl8168ep_stop_cmac(tp);
1246         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1247         r8168ep_ocp_write(tp, 0x01, 0x30,
1248                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1249         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1250 }
1251
1252 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1253 {
1254         switch (tp->mac_version) {
1255         case RTL_GIGA_MAC_VER_27:
1256         case RTL_GIGA_MAC_VER_28:
1257         case RTL_GIGA_MAC_VER_31:
1258                 rtl8168dp_driver_stop(tp);
1259                 break;
1260         case RTL_GIGA_MAC_VER_49:
1261         case RTL_GIGA_MAC_VER_50:
1262         case RTL_GIGA_MAC_VER_51:
1263                 rtl8168ep_driver_stop(tp);
1264                 break;
1265         default:
1266                 BUG();
1267                 break;
1268         }
1269 }
1270
1271 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1272 {
1273         u16 reg = rtl8168_get_ocp_reg(tp);
1274
1275         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1276 }
1277
1278 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1279 {
1280         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1281 }
1282
1283 static bool r8168_check_dash(struct rtl8169_private *tp)
1284 {
1285         switch (tp->mac_version) {
1286         case RTL_GIGA_MAC_VER_27:
1287         case RTL_GIGA_MAC_VER_28:
1288         case RTL_GIGA_MAC_VER_31:
1289                 return r8168dp_check_dash(tp);
1290         case RTL_GIGA_MAC_VER_49:
1291         case RTL_GIGA_MAC_VER_50:
1292         case RTL_GIGA_MAC_VER_51:
1293                 return r8168ep_check_dash(tp);
1294         default:
1295                 return false;
1296         }
1297 }
1298
1299 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1300 {
1301         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1302         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1303 }
1304
1305 DECLARE_RTL_COND(rtl_efusear_cond)
1306 {
1307         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1308 }
1309
1310 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1311 {
1312         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1313
1314         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1315                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1316 }
1317
1318 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1319 {
1320         RTL_W16(tp, IntrStatus, bits);
1321 }
1322
1323 static void rtl_irq_disable(struct rtl8169_private *tp)
1324 {
1325         RTL_W16(tp, IntrMask, 0);
1326         tp->irq_enabled = 0;
1327 }
1328
1329 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1330 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1331 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1332
1333 static void rtl_irq_enable(struct rtl8169_private *tp)
1334 {
1335         tp->irq_enabled = 1;
1336         RTL_W16(tp, IntrMask, tp->irq_mask);
1337 }
1338
1339 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1340 {
1341         rtl_irq_disable(tp);
1342         rtl_ack_events(tp, 0xffff);
1343         /* PCI commit */
1344         RTL_R8(tp, ChipCmd);
1345 }
1346
1347 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1348 {
1349         struct net_device *dev = tp->dev;
1350         struct phy_device *phydev = tp->phydev;
1351
1352         if (!netif_running(dev))
1353                 return;
1354
1355         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1356             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1357                 if (phydev->speed == SPEED_1000) {
1358                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1360                 } else if (phydev->speed == SPEED_100) {
1361                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1362                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1363                 } else {
1364                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1365                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1366                 }
1367                 rtl_reset_packet_filter(tp);
1368         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1369                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1370                 if (phydev->speed == SPEED_1000) {
1371                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1372                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1373                 } else {
1374                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1375                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1376                 }
1377         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1378                 if (phydev->speed == SPEED_10) {
1379                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1380                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1381                 } else {
1382                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1383                 }
1384         }
1385 }
1386
1387 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1388
1389 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1390 {
1391         struct rtl8169_private *tp = netdev_priv(dev);
1392
1393         rtl_lock_work(tp);
1394         wol->supported = WAKE_ANY;
1395         wol->wolopts = tp->saved_wolopts;
1396         rtl_unlock_work(tp);
1397 }
1398
1399 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1400 {
1401         unsigned int i, tmp;
1402         static const struct {
1403                 u32 opt;
1404                 u16 reg;
1405                 u8  mask;
1406         } cfg[] = {
1407                 { WAKE_PHY,   Config3, LinkUp },
1408                 { WAKE_UCAST, Config5, UWF },
1409                 { WAKE_BCAST, Config5, BWF },
1410                 { WAKE_MCAST, Config5, MWF },
1411                 { WAKE_ANY,   Config5, LanWake },
1412                 { WAKE_MAGIC, Config3, MagicPacket }
1413         };
1414         u8 options;
1415
1416         rtl_unlock_config_regs(tp);
1417
1418         switch (tp->mac_version) {
1419         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1420         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1421                 tmp = ARRAY_SIZE(cfg) - 1;
1422                 if (wolopts & WAKE_MAGIC)
1423                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1424                                          MagicPacket_v2);
1425                 else
1426                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1427                                            MagicPacket_v2);
1428                 break;
1429         default:
1430                 tmp = ARRAY_SIZE(cfg);
1431                 break;
1432         }
1433
1434         for (i = 0; i < tmp; i++) {
1435                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1436                 if (wolopts & cfg[i].opt)
1437                         options |= cfg[i].mask;
1438                 RTL_W8(tp, cfg[i].reg, options);
1439         }
1440
1441         switch (tp->mac_version) {
1442         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_17:
1443                 options = RTL_R8(tp, Config1) & ~PMEnable;
1444                 if (wolopts)
1445                         options |= PMEnable;
1446                 RTL_W8(tp, Config1, options);
1447                 break;
1448         default:
1449                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1450                 if (wolopts)
1451                         options |= PME_SIGNAL;
1452                 RTL_W8(tp, Config2, options);
1453                 break;
1454         }
1455
1456         rtl_lock_config_regs(tp);
1457
1458         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1459 }
1460
1461 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1462 {
1463         struct rtl8169_private *tp = netdev_priv(dev);
1464         struct device *d = tp_to_dev(tp);
1465
1466         if (wol->wolopts & ~WAKE_ANY)
1467                 return -EINVAL;
1468
1469         pm_runtime_get_noresume(d);
1470
1471         rtl_lock_work(tp);
1472
1473         tp->saved_wolopts = wol->wolopts;
1474
1475         if (pm_runtime_active(d))
1476                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1477
1478         rtl_unlock_work(tp);
1479
1480         pm_runtime_put_noidle(d);
1481
1482         return 0;
1483 }
1484
1485 static void rtl8169_get_drvinfo(struct net_device *dev,
1486                                 struct ethtool_drvinfo *info)
1487 {
1488         struct rtl8169_private *tp = netdev_priv(dev);
1489         struct rtl_fw *rtl_fw = tp->rtl_fw;
1490
1491         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1492         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1493         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1494         if (rtl_fw)
1495                 strlcpy(info->fw_version, rtl_fw->version,
1496                         sizeof(info->fw_version));
1497 }
1498
1499 static int rtl8169_get_regs_len(struct net_device *dev)
1500 {
1501         return R8169_REGS_SIZE;
1502 }
1503
1504 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1505         netdev_features_t features)
1506 {
1507         struct rtl8169_private *tp = netdev_priv(dev);
1508
1509         if (dev->mtu > TD_MSS_MAX)
1510                 features &= ~NETIF_F_ALL_TSO;
1511
1512         if (dev->mtu > JUMBO_1K &&
1513             tp->mac_version > RTL_GIGA_MAC_VER_06)
1514                 features &= ~NETIF_F_IP_CSUM;
1515
1516         return features;
1517 }
1518
1519 static int rtl8169_set_features(struct net_device *dev,
1520                                 netdev_features_t features)
1521 {
1522         struct rtl8169_private *tp = netdev_priv(dev);
1523         u32 rx_config;
1524
1525         rtl_lock_work(tp);
1526
1527         rx_config = RTL_R32(tp, RxConfig);
1528         if (features & NETIF_F_RXALL)
1529                 rx_config |= (AcceptErr | AcceptRunt);
1530         else
1531                 rx_config &= ~(AcceptErr | AcceptRunt);
1532
1533         RTL_W32(tp, RxConfig, rx_config);
1534
1535         if (features & NETIF_F_RXCSUM)
1536                 tp->cp_cmd |= RxChkSum;
1537         else
1538                 tp->cp_cmd &= ~RxChkSum;
1539
1540         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1541                 tp->cp_cmd |= RxVlan;
1542         else
1543                 tp->cp_cmd &= ~RxVlan;
1544
1545         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1546         RTL_R16(tp, CPlusCmd);
1547
1548         rtl_unlock_work(tp);
1549
1550         return 0;
1551 }
1552
1553 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1554 {
1555         return (skb_vlan_tag_present(skb)) ?
1556                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1557 }
1558
1559 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1560 {
1561         u32 opts2 = le32_to_cpu(desc->opts2);
1562
1563         if (opts2 & RxVlanTag)
1564                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1565 }
1566
1567 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1568                              void *p)
1569 {
1570         struct rtl8169_private *tp = netdev_priv(dev);
1571         u32 __iomem *data = tp->mmio_addr;
1572         u32 *dw = p;
1573         int i;
1574
1575         rtl_lock_work(tp);
1576         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1577                 memcpy_fromio(dw++, data++, 4);
1578         rtl_unlock_work(tp);
1579 }
1580
1581 static u32 rtl8169_get_msglevel(struct net_device *dev)
1582 {
1583         struct rtl8169_private *tp = netdev_priv(dev);
1584
1585         return tp->msg_enable;
1586 }
1587
1588 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1589 {
1590         struct rtl8169_private *tp = netdev_priv(dev);
1591
1592         tp->msg_enable = value;
1593 }
1594
1595 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1596         "tx_packets",
1597         "rx_packets",
1598         "tx_errors",
1599         "rx_errors",
1600         "rx_missed",
1601         "align_errors",
1602         "tx_single_collisions",
1603         "tx_multi_collisions",
1604         "unicast",
1605         "broadcast",
1606         "multicast",
1607         "tx_aborted",
1608         "tx_underrun",
1609 };
1610
1611 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1612 {
1613         switch (sset) {
1614         case ETH_SS_STATS:
1615                 return ARRAY_SIZE(rtl8169_gstrings);
1616         default:
1617                 return -EOPNOTSUPP;
1618         }
1619 }
1620
1621 DECLARE_RTL_COND(rtl_counters_cond)
1622 {
1623         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1624 }
1625
1626 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1627 {
1628         dma_addr_t paddr = tp->counters_phys_addr;
1629         u32 cmd;
1630
1631         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1632         RTL_R32(tp, CounterAddrHigh);
1633         cmd = (u64)paddr & DMA_BIT_MASK(32);
1634         RTL_W32(tp, CounterAddrLow, cmd);
1635         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1636
1637         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1638 }
1639
1640 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1641 {
1642         /*
1643          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1644          * tally counters.
1645          */
1646         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1647                 return true;
1648
1649         return rtl8169_do_counters(tp, CounterReset);
1650 }
1651
1652 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1653 {
1654         u8 val = RTL_R8(tp, ChipCmd);
1655
1656         /*
1657          * Some chips are unable to dump tally counters when the receiver
1658          * is disabled. If 0xff chip may be in a PCI power-save state.
1659          */
1660         if (!(val & CmdRxEnb) || val == 0xff)
1661                 return true;
1662
1663         return rtl8169_do_counters(tp, CounterDump);
1664 }
1665
1666 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1667 {
1668         struct rtl8169_counters *counters = tp->counters;
1669         bool ret = false;
1670
1671         /*
1672          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1673          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1674          * reset by a power cycle, while the counter values collected by the
1675          * driver are reset at every driver unload/load cycle.
1676          *
1677          * To make sure the HW values returned by @get_stats64 match the SW
1678          * values, we collect the initial values at first open(*) and use them
1679          * as offsets to normalize the values returned by @get_stats64.
1680          *
1681          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1682          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1683          * set at open time by rtl_hw_start.
1684          */
1685
1686         if (tp->tc_offset.inited)
1687                 return true;
1688
1689         /* If both, reset and update fail, propagate to caller. */
1690         if (rtl8169_reset_counters(tp))
1691                 ret = true;
1692
1693         if (rtl8169_update_counters(tp))
1694                 ret = true;
1695
1696         tp->tc_offset.tx_errors = counters->tx_errors;
1697         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1698         tp->tc_offset.tx_aborted = counters->tx_aborted;
1699         tp->tc_offset.inited = true;
1700
1701         return ret;
1702 }
1703
1704 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1705                                       struct ethtool_stats *stats, u64 *data)
1706 {
1707         struct rtl8169_private *tp = netdev_priv(dev);
1708         struct device *d = tp_to_dev(tp);
1709         struct rtl8169_counters *counters = tp->counters;
1710
1711         ASSERT_RTNL();
1712
1713         pm_runtime_get_noresume(d);
1714
1715         if (pm_runtime_active(d))
1716                 rtl8169_update_counters(tp);
1717
1718         pm_runtime_put_noidle(d);
1719
1720         data[0] = le64_to_cpu(counters->tx_packets);
1721         data[1] = le64_to_cpu(counters->rx_packets);
1722         data[2] = le64_to_cpu(counters->tx_errors);
1723         data[3] = le32_to_cpu(counters->rx_errors);
1724         data[4] = le16_to_cpu(counters->rx_missed);
1725         data[5] = le16_to_cpu(counters->align_errors);
1726         data[6] = le32_to_cpu(counters->tx_one_collision);
1727         data[7] = le32_to_cpu(counters->tx_multi_collision);
1728         data[8] = le64_to_cpu(counters->rx_unicast);
1729         data[9] = le64_to_cpu(counters->rx_broadcast);
1730         data[10] = le32_to_cpu(counters->rx_multicast);
1731         data[11] = le16_to_cpu(counters->tx_aborted);
1732         data[12] = le16_to_cpu(counters->tx_underun);
1733 }
1734
1735 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1736 {
1737         switch(stringset) {
1738         case ETH_SS_STATS:
1739                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1740                 break;
1741         }
1742 }
1743
1744 /*
1745  * Interrupt coalescing
1746  *
1747  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1748  * >     8169, 8168 and 810x line of chipsets
1749  *
1750  * 8169, 8168, and 8136(810x) serial chipsets support it.
1751  *
1752  * > 2 - the Tx timer unit at gigabit speed
1753  *
1754  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1755  * (0xe0) bit 1 and bit 0.
1756  *
1757  * For 8169
1758  * bit[1:0] \ speed        1000M           100M            10M
1759  * 0 0                     320ns           2.56us          40.96us
1760  * 0 1                     2.56us          20.48us         327.7us
1761  * 1 0                     5.12us          40.96us         655.4us
1762  * 1 1                     10.24us         81.92us         1.31ms
1763  *
1764  * For the other
1765  * bit[1:0] \ speed        1000M           100M            10M
1766  * 0 0                     5us             2.56us          40.96us
1767  * 0 1                     40us            20.48us         327.7us
1768  * 1 0                     80us            40.96us         655.4us
1769  * 1 1                     160us           81.92us         1.31ms
1770  */
1771
1772 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1773 struct rtl_coalesce_scale {
1774         /* Rx / Tx */
1775         u32 nsecs[2];
1776 };
1777
1778 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1779 struct rtl_coalesce_info {
1780         u32 speed;
1781         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1782 };
1783
1784 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1785 #define rxtx_x1822(r, t) {              \
1786         {{(r),          (t)}},          \
1787         {{(r)*8,        (t)*8}},        \
1788         {{(r)*8*2,      (t)*8*2}},      \
1789         {{(r)*8*2*2,    (t)*8*2*2}},    \
1790 }
1791 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1792         /* speed        delays:     rx00   tx00 */
1793         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1794         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1795         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1796         { 0 },
1797 };
1798
1799 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1800         /* speed        delays:     rx00   tx00 */
1801         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1802         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1803         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1804         { 0 },
1805 };
1806 #undef rxtx_x1822
1807
1808 /* get rx/tx scale vector corresponding to current speed */
1809 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1810 {
1811         struct rtl8169_private *tp = netdev_priv(dev);
1812         struct ethtool_link_ksettings ecmd;
1813         const struct rtl_coalesce_info *ci;
1814         int rc;
1815
1816         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1817         if (rc < 0)
1818                 return ERR_PTR(rc);
1819
1820         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1821                 if (ecmd.base.speed == ci->speed) {
1822                         return ci;
1823                 }
1824         }
1825
1826         return ERR_PTR(-ELNRNG);
1827 }
1828
1829 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1830 {
1831         struct rtl8169_private *tp = netdev_priv(dev);
1832         const struct rtl_coalesce_info *ci;
1833         const struct rtl_coalesce_scale *scale;
1834         struct {
1835                 u32 *max_frames;
1836                 u32 *usecs;
1837         } coal_settings [] = {
1838                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1839                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1840         }, *p = coal_settings;
1841         int i;
1842         u16 w;
1843
1844         memset(ec, 0, sizeof(*ec));
1845
1846         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1847         ci = rtl_coalesce_info(dev);
1848         if (IS_ERR(ci))
1849                 return PTR_ERR(ci);
1850
1851         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1852
1853         /* read IntrMitigate and adjust according to scale */
1854         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1855                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1856                 w >>= RTL_COALESCE_SHIFT;
1857                 *p->usecs = w & RTL_COALESCE_MASK;
1858         }
1859
1860         for (i = 0; i < 2; i++) {
1861                 p = coal_settings + i;
1862                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1863
1864                 /*
1865                  * ethtool_coalesce says it is illegal to set both usecs and
1866                  * max_frames to 0.
1867                  */
1868                 if (!*p->usecs && !*p->max_frames)
1869                         *p->max_frames = 1;
1870         }
1871
1872         return 0;
1873 }
1874
1875 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1876 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1877                         struct net_device *dev, u32 nsec, u16 *cp01)
1878 {
1879         const struct rtl_coalesce_info *ci;
1880         u16 i;
1881
1882         ci = rtl_coalesce_info(dev);
1883         if (IS_ERR(ci))
1884                 return ERR_CAST(ci);
1885
1886         for (i = 0; i < 4; i++) {
1887                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1888                                         ci->scalev[i].nsecs[1]);
1889                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1890                         *cp01 = i;
1891                         return &ci->scalev[i];
1892                 }
1893         }
1894
1895         return ERR_PTR(-EINVAL);
1896 }
1897
1898 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1899 {
1900         struct rtl8169_private *tp = netdev_priv(dev);
1901         const struct rtl_coalesce_scale *scale;
1902         struct {
1903                 u32 frames;
1904                 u32 usecs;
1905         } coal_settings [] = {
1906                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1907                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1908         }, *p = coal_settings;
1909         u16 w = 0, cp01;
1910         int i;
1911
1912         scale = rtl_coalesce_choose_scale(dev,
1913                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1914         if (IS_ERR(scale))
1915                 return PTR_ERR(scale);
1916
1917         for (i = 0; i < 2; i++, p++) {
1918                 u32 units;
1919
1920                 /*
1921                  * accept max_frames=1 we returned in rtl_get_coalesce.
1922                  * accept it not only when usecs=0 because of e.g. the following scenario:
1923                  *
1924                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1925                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1926                  * - then user does `ethtool -C eth0 rx-usecs 100`
1927                  *
1928                  * since ethtool sends to kernel whole ethtool_coalesce
1929                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1930                  * we'll reject it below in `frames % 4 != 0`.
1931                  */
1932                 if (p->frames == 1) {
1933                         p->frames = 0;
1934                 }
1935
1936                 units = p->usecs * 1000 / scale->nsecs[i];
1937                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1938                         return -EINVAL;
1939
1940                 w <<= RTL_COALESCE_SHIFT;
1941                 w |= units;
1942                 w <<= RTL_COALESCE_SHIFT;
1943                 w |= p->frames >> 2;
1944         }
1945
1946         rtl_lock_work(tp);
1947
1948         RTL_W16(tp, IntrMitigate, swab16(w));
1949
1950         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1951         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1952         RTL_R16(tp, CPlusCmd);
1953
1954         rtl_unlock_work(tp);
1955
1956         return 0;
1957 }
1958
1959 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1960 {
1961         struct phy_device *phydev = tp->phydev;
1962         int ret;
1963
1964         switch (tp->mac_version) {
1965         case RTL_GIGA_MAC_VER_34:
1966         case RTL_GIGA_MAC_VER_35:
1967         case RTL_GIGA_MAC_VER_36:
1968         case RTL_GIGA_MAC_VER_38:
1969                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1970                 break;
1971         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1972                 ret = phy_read_paged(phydev, 0x0a5c, 0x12);
1973                 break;
1974         default:
1975                 ret = -EPROTONOSUPPORT;
1976                 break;
1977         }
1978
1979         return ret;
1980 }
1981
1982 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1983 {
1984         struct phy_device *phydev = tp->phydev;
1985         int ret;
1986
1987         switch (tp->mac_version) {
1988         case RTL_GIGA_MAC_VER_34:
1989         case RTL_GIGA_MAC_VER_35:
1990         case RTL_GIGA_MAC_VER_36:
1991         case RTL_GIGA_MAC_VER_38:
1992                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1993                 break;
1994         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1995                 ret = phy_read_paged(phydev, 0x0a5d, 0x11);
1996                 break;
1997         default:
1998                 ret = -EPROTONOSUPPORT;
1999                 break;
2000         }
2001
2002         return ret;
2003 }
2004
2005 static int rtl_get_eee_adv(struct rtl8169_private *tp)
2006 {
2007         struct phy_device *phydev = tp->phydev;
2008         int ret;
2009
2010         switch (tp->mac_version) {
2011         case RTL_GIGA_MAC_VER_34:
2012         case RTL_GIGA_MAC_VER_35:
2013         case RTL_GIGA_MAC_VER_36:
2014         case RTL_GIGA_MAC_VER_38:
2015                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2016                 break;
2017         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2018                 ret = phy_read_paged(phydev, 0x0a5d, 0x10);
2019                 break;
2020         default:
2021                 ret = -EPROTONOSUPPORT;
2022                 break;
2023         }
2024
2025         return ret;
2026 }
2027
2028 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2029 {
2030         struct phy_device *phydev = tp->phydev;
2031         int ret = 0;
2032
2033         switch (tp->mac_version) {
2034         case RTL_GIGA_MAC_VER_34:
2035         case RTL_GIGA_MAC_VER_35:
2036         case RTL_GIGA_MAC_VER_36:
2037         case RTL_GIGA_MAC_VER_38:
2038                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2039                 break;
2040         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2041                 phy_write_paged(phydev, 0x0a5d, 0x10, val);
2042                 break;
2043         default:
2044                 ret = -EPROTONOSUPPORT;
2045                 break;
2046         }
2047
2048         return ret;
2049 }
2050
2051 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2052 {
2053         struct rtl8169_private *tp = netdev_priv(dev);
2054         struct device *d = tp_to_dev(tp);
2055         int ret;
2056
2057         pm_runtime_get_noresume(d);
2058
2059         if (!pm_runtime_active(d)) {
2060                 ret = -EOPNOTSUPP;
2061                 goto out;
2062         }
2063
2064         /* Get Supported EEE */
2065         ret = rtl_get_eee_supp(tp);
2066         if (ret < 0)
2067                 goto out;
2068         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2069
2070         /* Get advertisement EEE */
2071         ret = rtl_get_eee_adv(tp);
2072         if (ret < 0)
2073                 goto out;
2074         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2075         data->eee_enabled = !!data->advertised;
2076
2077         /* Get LP advertisement EEE */
2078         ret = rtl_get_eee_lpadv(tp);
2079         if (ret < 0)
2080                 goto out;
2081         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2082         data->eee_active = !!(data->advertised & data->lp_advertised);
2083 out:
2084         pm_runtime_put_noidle(d);
2085         return ret < 0 ? ret : 0;
2086 }
2087
2088 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2089 {
2090         struct rtl8169_private *tp = netdev_priv(dev);
2091         struct device *d = tp_to_dev(tp);
2092         int old_adv, adv = 0, cap, ret;
2093
2094         pm_runtime_get_noresume(d);
2095
2096         if (!dev->phydev || !pm_runtime_active(d)) {
2097                 ret = -EOPNOTSUPP;
2098                 goto out;
2099         }
2100
2101         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2102             dev->phydev->duplex != DUPLEX_FULL) {
2103                 ret = -EPROTONOSUPPORT;
2104                 goto out;
2105         }
2106
2107         /* Get Supported EEE */
2108         ret = rtl_get_eee_supp(tp);
2109         if (ret < 0)
2110                 goto out;
2111         cap = ret;
2112
2113         ret = rtl_get_eee_adv(tp);
2114         if (ret < 0)
2115                 goto out;
2116         old_adv = ret;
2117
2118         if (data->eee_enabled) {
2119                 adv = !data->advertised ? cap :
2120                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2121                 /* Mask prohibited EEE modes */
2122                 adv &= ~dev->phydev->eee_broken_modes;
2123         }
2124
2125         if (old_adv != adv) {
2126                 ret = rtl_set_eee_adv(tp, adv);
2127                 if (ret < 0)
2128                         goto out;
2129
2130                 /* Restart autonegotiation so the new modes get sent to the
2131                  * link partner.
2132                  */
2133                 ret = phy_restart_aneg(dev->phydev);
2134         }
2135
2136 out:
2137         pm_runtime_put_noidle(d);
2138         return ret < 0 ? ret : 0;
2139 }
2140
2141 static const struct ethtool_ops rtl8169_ethtool_ops = {
2142         .get_drvinfo            = rtl8169_get_drvinfo,
2143         .get_regs_len           = rtl8169_get_regs_len,
2144         .get_link               = ethtool_op_get_link,
2145         .get_coalesce           = rtl_get_coalesce,
2146         .set_coalesce           = rtl_set_coalesce,
2147         .get_msglevel           = rtl8169_get_msglevel,
2148         .set_msglevel           = rtl8169_set_msglevel,
2149         .get_regs               = rtl8169_get_regs,
2150         .get_wol                = rtl8169_get_wol,
2151         .set_wol                = rtl8169_set_wol,
2152         .get_strings            = rtl8169_get_strings,
2153         .get_sset_count         = rtl8169_get_sset_count,
2154         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2155         .get_ts_info            = ethtool_op_get_ts_info,
2156         .nway_reset             = phy_ethtool_nway_reset,
2157         .get_eee                = rtl8169_get_eee,
2158         .set_eee                = rtl8169_set_eee,
2159         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2160         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2161 };
2162
2163 static void rtl_enable_eee(struct rtl8169_private *tp)
2164 {
2165         int supported = rtl_get_eee_supp(tp);
2166
2167         if (supported > 0)
2168                 rtl_set_eee_adv(tp, supported);
2169 }
2170
2171 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2172 {
2173         /*
2174          * The driver currently handles the 8168Bf and the 8168Be identically
2175          * but they can be identified more specifically through the test below
2176          * if needed:
2177          *
2178          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2179          *
2180          * Same thing for the 8101Eb and the 8101Ec:
2181          *
2182          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2183          */
2184         static const struct rtl_mac_info {
2185                 u16 mask;
2186                 u16 val;
2187                 u16 mac_version;
2188         } mac_info[] = {
2189                 /* 8168EP family. */
2190                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2191                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2192                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2193
2194                 /* 8168H family. */
2195                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2196                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2197
2198                 /* 8168G family. */
2199                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2200                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2201                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2202                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2203
2204                 /* 8168F family. */
2205                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2206                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2207                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2208
2209                 /* 8168E family. */
2210                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2211                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2212                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2213
2214                 /* 8168D family. */
2215                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2216                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2217
2218                 /* 8168DP family. */
2219                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2220                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2221                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2222
2223                 /* 8168C family. */
2224                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2225                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2226                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2227                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2228                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2229                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2230                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2231
2232                 /* 8168B family. */
2233                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2234                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2235                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2236
2237                 /* 8101 family. */
2238                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2239                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2240                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2241                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2242                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2243                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2244                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2245                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2246                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2247                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2248                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2249                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2250                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2251                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2252                 /* FIXME: where did these entries come from ? -- FR */
2253                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2254                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2255
2256                 /* 8110 family. */
2257                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2258                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2259                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2260                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2261                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2262
2263                 /* Catch-all */
2264                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2265         };
2266         const struct rtl_mac_info *p = mac_info;
2267         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2268
2269         while ((reg & p->mask) != p->val)
2270                 p++;
2271         tp->mac_version = p->mac_version;
2272
2273         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2274                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2275         } else if (!tp->supports_gmii) {
2276                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2277                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2278                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2279                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2280                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2281                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2282         }
2283 }
2284
2285 struct phy_reg {
2286         u16 reg;
2287         u16 val;
2288 };
2289
2290 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2291                                  const struct phy_reg *regs, int len)
2292 {
2293         while (len-- > 0) {
2294                 rtl_writephy(tp, regs->reg, regs->val);
2295                 regs++;
2296         }
2297 }
2298
2299 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2300
2301 enum rtl_fw_opcode {
2302         PHY_READ                = 0x0,
2303         PHY_DATA_OR             = 0x1,
2304         PHY_DATA_AND            = 0x2,
2305         PHY_BJMPN               = 0x3,
2306         PHY_MDIO_CHG            = 0x4,
2307         PHY_CLEAR_READCOUNT     = 0x7,
2308         PHY_WRITE               = 0x8,
2309         PHY_READCOUNT_EQ_SKIP   = 0x9,
2310         PHY_COMP_EQ_SKIPN       = 0xa,
2311         PHY_COMP_NEQ_SKIPN      = 0xb,
2312         PHY_WRITE_PREVIOUS      = 0xc,
2313         PHY_SKIPN               = 0xd,
2314         PHY_DELAY_MS            = 0xe,
2315 };
2316
2317 struct fw_info {
2318         u32     magic;
2319         char    version[RTL_VER_SIZE];
2320         __le32  fw_start;
2321         __le32  fw_len;
2322         u8      chksum;
2323 } __packed;
2324
2325 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2326
2327 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2328 {
2329         const struct firmware *fw = rtl_fw->fw;
2330         struct fw_info *fw_info = (struct fw_info *)fw->data;
2331         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2332
2333         if (fw->size < FW_OPCODE_SIZE)
2334                 return false;
2335
2336         if (!fw_info->magic) {
2337                 size_t i, size, start;
2338                 u8 checksum = 0;
2339
2340                 if (fw->size < sizeof(*fw_info))
2341                         return false;
2342
2343                 for (i = 0; i < fw->size; i++)
2344                         checksum += fw->data[i];
2345                 if (checksum != 0)
2346                         return false;
2347
2348                 start = le32_to_cpu(fw_info->fw_start);
2349                 if (start > fw->size)
2350                         return false;
2351
2352                 size = le32_to_cpu(fw_info->fw_len);
2353                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2354                         return false;
2355
2356                 strscpy(rtl_fw->version, fw_info->version, RTL_VER_SIZE);
2357
2358                 pa->code = (__le32 *)(fw->data + start);
2359                 pa->size = size;
2360         } else {
2361                 if (fw->size % FW_OPCODE_SIZE)
2362                         return false;
2363
2364                 strscpy(rtl_fw->version, tp->fw_name, RTL_VER_SIZE);
2365
2366                 pa->code = (__le32 *)fw->data;
2367                 pa->size = fw->size / FW_OPCODE_SIZE;
2368         }
2369
2370         return true;
2371 }
2372
2373 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2374                            struct rtl_fw_phy_action *pa)
2375 {
2376         bool rc = false;
2377         size_t index;
2378
2379         for (index = 0; index < pa->size; index++) {
2380                 u32 action = le32_to_cpu(pa->code[index]);
2381                 u32 regno = (action & 0x0fff0000) >> 16;
2382
2383                 switch (action >> 28) {
2384                 case PHY_READ:
2385                 case PHY_DATA_OR:
2386                 case PHY_DATA_AND:
2387                 case PHY_MDIO_CHG:
2388                 case PHY_CLEAR_READCOUNT:
2389                 case PHY_WRITE:
2390                 case PHY_WRITE_PREVIOUS:
2391                 case PHY_DELAY_MS:
2392                         break;
2393
2394                 case PHY_BJMPN:
2395                         if (regno > index) {
2396                                 netif_err(tp, ifup, tp->dev,
2397                                           "Out of range of firmware\n");
2398                                 goto out;
2399                         }
2400                         break;
2401                 case PHY_READCOUNT_EQ_SKIP:
2402                         if (index + 2 >= pa->size) {
2403                                 netif_err(tp, ifup, tp->dev,
2404                                           "Out of range of firmware\n");
2405                                 goto out;
2406                         }
2407                         break;
2408                 case PHY_COMP_EQ_SKIPN:
2409                 case PHY_COMP_NEQ_SKIPN:
2410                 case PHY_SKIPN:
2411                         if (index + 1 + regno >= pa->size) {
2412                                 netif_err(tp, ifup, tp->dev,
2413                                           "Out of range of firmware\n");
2414                                 goto out;
2415                         }
2416                         break;
2417
2418                 default:
2419                         netif_err(tp, ifup, tp->dev,
2420                                   "Invalid action 0x%08x\n", action);
2421                         goto out;
2422                 }
2423         }
2424         rc = true;
2425 out:
2426         return rc;
2427 }
2428
2429 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2430 {
2431         struct net_device *dev = tp->dev;
2432         int rc = -EINVAL;
2433
2434         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2435                 netif_err(tp, ifup, dev, "invalid firmware\n");
2436                 goto out;
2437         }
2438
2439         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2440                 rc = 0;
2441 out:
2442         return rc;
2443 }
2444
2445 static void rtl_fw_write_firmware(struct rtl8169_private *tp,
2446                                   struct rtl_fw *rtl_fw)
2447 {
2448         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2449         rtl_fw_write_t fw_write = rtl_fw->phy_write;
2450         rtl_fw_read_t fw_read = rtl_fw->phy_read;
2451         int predata = 0, count = 0;
2452         size_t index;
2453
2454         for (index = 0; index < pa->size; index++) {
2455                 u32 action = le32_to_cpu(pa->code[index]);
2456                 u32 data = action & 0x0000ffff;
2457                 u32 regno = (action & 0x0fff0000) >> 16;
2458                 enum rtl_fw_opcode opcode = action >> 28;
2459
2460                 if (!action)
2461                         break;
2462
2463                 switch (opcode) {
2464                 case PHY_READ:
2465                         predata = fw_read(tp, regno);
2466                         count++;
2467                         break;
2468                 case PHY_DATA_OR:
2469                         predata |= data;
2470                         break;
2471                 case PHY_DATA_AND:
2472                         predata &= data;
2473                         break;
2474                 case PHY_BJMPN:
2475                         index -= (regno + 1);
2476                         break;
2477                 case PHY_MDIO_CHG:
2478                         if (data == 0) {
2479                                 fw_write = rtl_fw->phy_write;
2480                                 fw_read = rtl_fw->phy_read;
2481                         } else if (data == 1) {
2482                                 fw_write = rtl_fw->mac_mcu_write;
2483                                 fw_read = rtl_fw->mac_mcu_read;
2484                         }
2485
2486                         break;
2487                 case PHY_CLEAR_READCOUNT:
2488                         count = 0;
2489                         break;
2490                 case PHY_WRITE:
2491                         fw_write(tp, regno, data);
2492                         break;
2493                 case PHY_READCOUNT_EQ_SKIP:
2494                         if (count == data)
2495                                 index++;
2496                         break;
2497                 case PHY_COMP_EQ_SKIPN:
2498                         if (predata == data)
2499                                 index += regno;
2500                         break;
2501                 case PHY_COMP_NEQ_SKIPN:
2502                         if (predata != data)
2503                                 index += regno;
2504                         break;
2505                 case PHY_WRITE_PREVIOUS:
2506                         fw_write(tp, regno, predata);
2507                         break;
2508                 case PHY_SKIPN:
2509                         index += regno;
2510                         break;
2511                 case PHY_DELAY_MS:
2512                         mdelay(data);
2513                         break;
2514                 }
2515         }
2516 }
2517
2518 static void rtl_release_firmware(struct rtl8169_private *tp)
2519 {
2520         if (tp->rtl_fw) {
2521                 release_firmware(tp->rtl_fw->fw);
2522                 kfree(tp->rtl_fw);
2523                 tp->rtl_fw = NULL;
2524         }
2525 }
2526
2527 static void rtl_apply_firmware(struct rtl8169_private *tp)
2528 {
2529         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2530         if (tp->rtl_fw)
2531                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2532 }
2533
2534 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2535 {
2536         if (rtl_readphy(tp, reg) != val)
2537                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2538         else
2539                 rtl_apply_firmware(tp);
2540 }
2541
2542 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2543 {
2544         /* Adjust EEE LED frequency */
2545         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2546                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2547
2548         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2549 }
2550
2551 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2552 {
2553         struct phy_device *phydev = tp->phydev;
2554
2555         phy_write(phydev, 0x1f, 0x0007);
2556         phy_write(phydev, 0x1e, 0x0020);
2557         phy_set_bits(phydev, 0x15, BIT(8));
2558
2559         phy_write(phydev, 0x1f, 0x0005);
2560         phy_write(phydev, 0x05, 0x8b85);
2561         phy_set_bits(phydev, 0x06, BIT(13));
2562
2563         phy_write(phydev, 0x1f, 0x0000);
2564 }
2565
2566 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2567 {
2568         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2569 }
2570
2571 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2572 {
2573         static const struct phy_reg phy_reg_init[] = {
2574                 { 0x1f, 0x0001 },
2575                 { 0x06, 0x006e },
2576                 { 0x08, 0x0708 },
2577                 { 0x15, 0x4000 },
2578                 { 0x18, 0x65c7 },
2579
2580                 { 0x1f, 0x0001 },
2581                 { 0x03, 0x00a1 },
2582                 { 0x02, 0x0008 },
2583                 { 0x01, 0x0120 },
2584                 { 0x00, 0x1000 },
2585                 { 0x04, 0x0800 },
2586                 { 0x04, 0x0000 },
2587
2588                 { 0x03, 0xff41 },
2589                 { 0x02, 0xdf60 },
2590                 { 0x01, 0x0140 },
2591                 { 0x00, 0x0077 },
2592                 { 0x04, 0x7800 },
2593                 { 0x04, 0x7000 },
2594
2595                 { 0x03, 0x802f },
2596                 { 0x02, 0x4f02 },
2597                 { 0x01, 0x0409 },
2598                 { 0x00, 0xf0f9 },
2599                 { 0x04, 0x9800 },
2600                 { 0x04, 0x9000 },
2601
2602                 { 0x03, 0xdf01 },
2603                 { 0x02, 0xdf20 },
2604                 { 0x01, 0xff95 },
2605                 { 0x00, 0xba00 },
2606                 { 0x04, 0xa800 },
2607                 { 0x04, 0xa000 },
2608
2609                 { 0x03, 0xff41 },
2610                 { 0x02, 0xdf20 },
2611                 { 0x01, 0x0140 },
2612                 { 0x00, 0x00bb },
2613                 { 0x04, 0xb800 },
2614                 { 0x04, 0xb000 },
2615
2616                 { 0x03, 0xdf41 },
2617                 { 0x02, 0xdc60 },
2618                 { 0x01, 0x6340 },
2619                 { 0x00, 0x007d },
2620                 { 0x04, 0xd800 },
2621                 { 0x04, 0xd000 },
2622
2623                 { 0x03, 0xdf01 },
2624                 { 0x02, 0xdf20 },
2625                 { 0x01, 0x100a },
2626                 { 0x00, 0xa0ff },
2627                 { 0x04, 0xf800 },
2628                 { 0x04, 0xf000 },
2629
2630                 { 0x1f, 0x0000 },
2631                 { 0x0b, 0x0000 },
2632                 { 0x00, 0x9200 }
2633         };
2634
2635         rtl_writephy_batch(tp, phy_reg_init);
2636 }
2637
2638 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2639 {
2640         static const struct phy_reg phy_reg_init[] = {
2641                 { 0x1f, 0x0002 },
2642                 { 0x01, 0x90d0 },
2643                 { 0x1f, 0x0000 }
2644         };
2645
2646         rtl_writephy_batch(tp, phy_reg_init);
2647 }
2648
2649 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2650 {
2651         struct pci_dev *pdev = tp->pci_dev;
2652
2653         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2654             (pdev->subsystem_device != 0xe000))
2655                 return;
2656
2657         rtl_writephy(tp, 0x1f, 0x0001);
2658         rtl_writephy(tp, 0x10, 0xf01b);
2659         rtl_writephy(tp, 0x1f, 0x0000);
2660 }
2661
2662 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2663 {
2664         static const struct phy_reg phy_reg_init[] = {
2665                 { 0x1f, 0x0001 },
2666                 { 0x04, 0x0000 },
2667                 { 0x03, 0x00a1 },
2668                 { 0x02, 0x0008 },
2669                 { 0x01, 0x0120 },
2670                 { 0x00, 0x1000 },
2671                 { 0x04, 0x0800 },
2672                 { 0x04, 0x9000 },
2673                 { 0x03, 0x802f },
2674                 { 0x02, 0x4f02 },
2675                 { 0x01, 0x0409 },
2676                 { 0x00, 0xf099 },
2677                 { 0x04, 0x9800 },
2678                 { 0x04, 0xa000 },
2679                 { 0x03, 0xdf01 },
2680                 { 0x02, 0xdf20 },
2681                 { 0x01, 0xff95 },
2682                 { 0x00, 0xba00 },
2683                 { 0x04, 0xa800 },
2684                 { 0x04, 0xf000 },
2685                 { 0x03, 0xdf01 },
2686                 { 0x02, 0xdf20 },
2687                 { 0x01, 0x101a },
2688                 { 0x00, 0xa0ff },
2689                 { 0x04, 0xf800 },
2690                 { 0x04, 0x0000 },
2691                 { 0x1f, 0x0000 },
2692
2693                 { 0x1f, 0x0001 },
2694                 { 0x10, 0xf41b },
2695                 { 0x14, 0xfb54 },
2696                 { 0x18, 0xf5c7 },
2697                 { 0x1f, 0x0000 },
2698
2699                 { 0x1f, 0x0001 },
2700                 { 0x17, 0x0cc0 },
2701                 { 0x1f, 0x0000 }
2702         };
2703
2704         rtl_writephy_batch(tp, phy_reg_init);
2705
2706         rtl8169scd_hw_phy_config_quirk(tp);
2707 }
2708
2709 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2710 {
2711         static const struct phy_reg phy_reg_init[] = {
2712                 { 0x1f, 0x0001 },
2713                 { 0x04, 0x0000 },
2714                 { 0x03, 0x00a1 },
2715                 { 0x02, 0x0008 },
2716                 { 0x01, 0x0120 },
2717                 { 0x00, 0x1000 },
2718                 { 0x04, 0x0800 },
2719                 { 0x04, 0x9000 },
2720                 { 0x03, 0x802f },
2721                 { 0x02, 0x4f02 },
2722                 { 0x01, 0x0409 },
2723                 { 0x00, 0xf099 },
2724                 { 0x04, 0x9800 },
2725                 { 0x04, 0xa000 },
2726                 { 0x03, 0xdf01 },
2727                 { 0x02, 0xdf20 },
2728                 { 0x01, 0xff95 },
2729                 { 0x00, 0xba00 },
2730                 { 0x04, 0xa800 },
2731                 { 0x04, 0xf000 },
2732                 { 0x03, 0xdf01 },
2733                 { 0x02, 0xdf20 },
2734                 { 0x01, 0x101a },
2735                 { 0x00, 0xa0ff },
2736                 { 0x04, 0xf800 },
2737                 { 0x04, 0x0000 },
2738                 { 0x1f, 0x0000 },
2739
2740                 { 0x1f, 0x0001 },
2741                 { 0x0b, 0x8480 },
2742                 { 0x1f, 0x0000 },
2743
2744                 { 0x1f, 0x0001 },
2745                 { 0x18, 0x67c7 },
2746                 { 0x04, 0x2000 },
2747                 { 0x03, 0x002f },
2748                 { 0x02, 0x4360 },
2749                 { 0x01, 0x0109 },
2750                 { 0x00, 0x3022 },
2751                 { 0x04, 0x2800 },
2752                 { 0x1f, 0x0000 },
2753
2754                 { 0x1f, 0x0001 },
2755                 { 0x17, 0x0cc0 },
2756                 { 0x1f, 0x0000 }
2757         };
2758
2759         rtl_writephy_batch(tp, phy_reg_init);
2760 }
2761
2762 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2763 {
2764         static const struct phy_reg phy_reg_init[] = {
2765                 { 0x10, 0xf41b },
2766                 { 0x1f, 0x0000 }
2767         };
2768
2769         rtl_writephy(tp, 0x1f, 0x0001);
2770         rtl_patchphy(tp, 0x16, 1 << 0);
2771
2772         rtl_writephy_batch(tp, phy_reg_init);
2773 }
2774
2775 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2776 {
2777         static const struct phy_reg phy_reg_init[] = {
2778                 { 0x1f, 0x0001 },
2779                 { 0x10, 0xf41b },
2780                 { 0x1f, 0x0000 }
2781         };
2782
2783         rtl_writephy_batch(tp, phy_reg_init);
2784 }
2785
2786 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2787 {
2788         static const struct phy_reg phy_reg_init[] = {
2789                 { 0x1f, 0x0000 },
2790                 { 0x1d, 0x0f00 },
2791                 { 0x1f, 0x0002 },
2792                 { 0x0c, 0x1ec8 },
2793                 { 0x1f, 0x0000 }
2794         };
2795
2796         rtl_writephy_batch(tp, phy_reg_init);
2797 }
2798
2799 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2800 {
2801         static const struct phy_reg phy_reg_init[] = {
2802                 { 0x1f, 0x0001 },
2803                 { 0x1d, 0x3d98 },
2804                 { 0x1f, 0x0000 }
2805         };
2806
2807         rtl_writephy(tp, 0x1f, 0x0000);
2808         rtl_patchphy(tp, 0x14, 1 << 5);
2809         rtl_patchphy(tp, 0x0d, 1 << 5);
2810
2811         rtl_writephy_batch(tp, phy_reg_init);
2812 }
2813
2814 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2815 {
2816         static const struct phy_reg phy_reg_init[] = {
2817                 { 0x1f, 0x0001 },
2818                 { 0x12, 0x2300 },
2819                 { 0x1f, 0x0002 },
2820                 { 0x00, 0x88d4 },
2821                 { 0x01, 0x82b1 },
2822                 { 0x03, 0x7002 },
2823                 { 0x08, 0x9e30 },
2824                 { 0x09, 0x01f0 },
2825                 { 0x0a, 0x5500 },
2826                 { 0x0c, 0x00c8 },
2827                 { 0x1f, 0x0003 },
2828                 { 0x12, 0xc096 },
2829                 { 0x16, 0x000a },
2830                 { 0x1f, 0x0000 },
2831                 { 0x1f, 0x0000 },
2832                 { 0x09, 0x2000 },
2833                 { 0x09, 0x0000 }
2834         };
2835
2836         rtl_writephy_batch(tp, phy_reg_init);
2837
2838         rtl_patchphy(tp, 0x14, 1 << 5);
2839         rtl_patchphy(tp, 0x0d, 1 << 5);
2840         rtl_writephy(tp, 0x1f, 0x0000);
2841 }
2842
2843 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2844 {
2845         static const struct phy_reg phy_reg_init[] = {
2846                 { 0x1f, 0x0001 },
2847                 { 0x12, 0x2300 },
2848                 { 0x03, 0x802f },
2849                 { 0x02, 0x4f02 },
2850                 { 0x01, 0x0409 },
2851                 { 0x00, 0xf099 },
2852                 { 0x04, 0x9800 },
2853                 { 0x04, 0x9000 },
2854                 { 0x1d, 0x3d98 },
2855                 { 0x1f, 0x0002 },
2856                 { 0x0c, 0x7eb8 },
2857                 { 0x06, 0x0761 },
2858                 { 0x1f, 0x0003 },
2859                 { 0x16, 0x0f0a },
2860                 { 0x1f, 0x0000 }
2861         };
2862
2863         rtl_writephy_batch(tp, phy_reg_init);
2864
2865         rtl_patchphy(tp, 0x16, 1 << 0);
2866         rtl_patchphy(tp, 0x14, 1 << 5);
2867         rtl_patchphy(tp, 0x0d, 1 << 5);
2868         rtl_writephy(tp, 0x1f, 0x0000);
2869 }
2870
2871 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2872 {
2873         static const struct phy_reg phy_reg_init[] = {
2874                 { 0x1f, 0x0001 },
2875                 { 0x12, 0x2300 },
2876                 { 0x1d, 0x3d98 },
2877                 { 0x1f, 0x0002 },
2878                 { 0x0c, 0x7eb8 },
2879                 { 0x06, 0x5461 },
2880                 { 0x1f, 0x0003 },
2881                 { 0x16, 0x0f0a },
2882                 { 0x1f, 0x0000 }
2883         };
2884
2885         rtl_writephy_batch(tp, phy_reg_init);
2886
2887         rtl_patchphy(tp, 0x16, 1 << 0);
2888         rtl_patchphy(tp, 0x14, 1 << 5);
2889         rtl_patchphy(tp, 0x0d, 1 << 5);
2890         rtl_writephy(tp, 0x1f, 0x0000);
2891 }
2892
2893 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2894 {
2895         rtl8168c_3_hw_phy_config(tp);
2896 }
2897
2898 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2899         /* Channel Estimation */
2900         { 0x1f, 0x0001 },
2901         { 0x06, 0x4064 },
2902         { 0x07, 0x2863 },
2903         { 0x08, 0x059c },
2904         { 0x09, 0x26b4 },
2905         { 0x0a, 0x6a19 },
2906         { 0x0b, 0xdcc8 },
2907         { 0x10, 0xf06d },
2908         { 0x14, 0x7f68 },
2909         { 0x18, 0x7fd9 },
2910         { 0x1c, 0xf0ff },
2911         { 0x1d, 0x3d9c },
2912         { 0x1f, 0x0003 },
2913         { 0x12, 0xf49f },
2914         { 0x13, 0x070b },
2915         { 0x1a, 0x05ad },
2916         { 0x14, 0x94c0 },
2917
2918         /*
2919          * Tx Error Issue
2920          * Enhance line driver power
2921          */
2922         { 0x1f, 0x0002 },
2923         { 0x06, 0x5561 },
2924         { 0x1f, 0x0005 },
2925         { 0x05, 0x8332 },
2926         { 0x06, 0x5561 },
2927
2928         /*
2929          * Can not link to 1Gbps with bad cable
2930          * Decrease SNR threshold form 21.07dB to 19.04dB
2931          */
2932         { 0x1f, 0x0001 },
2933         { 0x17, 0x0cc0 },
2934
2935         { 0x1f, 0x0000 },
2936         { 0x0d, 0xf880 }
2937 };
2938
2939 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2940         { 0x1f, 0x0002 },
2941         { 0x05, 0x669a },
2942         { 0x1f, 0x0005 },
2943         { 0x05, 0x8330 },
2944         { 0x06, 0x669a },
2945         { 0x1f, 0x0002 }
2946 };
2947
2948 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2949 {
2950         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2951
2952         /*
2953          * Rx Error Issue
2954          * Fine Tune Switching regulator parameter
2955          */
2956         rtl_writephy(tp, 0x1f, 0x0002);
2957         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2958         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2959
2960         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2961                 int val;
2962
2963                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2964
2965                 val = rtl_readphy(tp, 0x0d);
2966
2967                 if ((val & 0x00ff) != 0x006c) {
2968                         static const u32 set[] = {
2969                                 0x0065, 0x0066, 0x0067, 0x0068,
2970                                 0x0069, 0x006a, 0x006b, 0x006c
2971                         };
2972                         int i;
2973
2974                         rtl_writephy(tp, 0x1f, 0x0002);
2975
2976                         val &= 0xff00;
2977                         for (i = 0; i < ARRAY_SIZE(set); i++)
2978                                 rtl_writephy(tp, 0x0d, val | set[i]);
2979                 }
2980         } else {
2981                 static const struct phy_reg phy_reg_init[] = {
2982                         { 0x1f, 0x0002 },
2983                         { 0x05, 0x6662 },
2984                         { 0x1f, 0x0005 },
2985                         { 0x05, 0x8330 },
2986                         { 0x06, 0x6662 }
2987                 };
2988
2989                 rtl_writephy_batch(tp, phy_reg_init);
2990         }
2991
2992         /* RSET couple improve */
2993         rtl_writephy(tp, 0x1f, 0x0002);
2994         rtl_patchphy(tp, 0x0d, 0x0300);
2995         rtl_patchphy(tp, 0x0f, 0x0010);
2996
2997         /* Fine tune PLL performance */
2998         rtl_writephy(tp, 0x1f, 0x0002);
2999         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3000         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3001
3002         rtl_writephy(tp, 0x1f, 0x0005);
3003         rtl_writephy(tp, 0x05, 0x001b);
3004
3005         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3006
3007         rtl_writephy(tp, 0x1f, 0x0000);
3008 }
3009
3010 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3011 {
3012         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
3013
3014         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3015                 int val;
3016
3017                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
3018
3019                 val = rtl_readphy(tp, 0x0d);
3020                 if ((val & 0x00ff) != 0x006c) {
3021                         static const u32 set[] = {
3022                                 0x0065, 0x0066, 0x0067, 0x0068,
3023                                 0x0069, 0x006a, 0x006b, 0x006c
3024                         };
3025                         int i;
3026
3027                         rtl_writephy(tp, 0x1f, 0x0002);
3028
3029                         val &= 0xff00;
3030                         for (i = 0; i < ARRAY_SIZE(set); i++)
3031                                 rtl_writephy(tp, 0x0d, val | set[i]);
3032                 }
3033         } else {
3034                 static const struct phy_reg phy_reg_init[] = {
3035                         { 0x1f, 0x0002 },
3036                         { 0x05, 0x2642 },
3037                         { 0x1f, 0x0005 },
3038                         { 0x05, 0x8330 },
3039                         { 0x06, 0x2642 }
3040                 };
3041
3042                 rtl_writephy_batch(tp, phy_reg_init);
3043         }
3044
3045         /* Fine tune PLL performance */
3046         rtl_writephy(tp, 0x1f, 0x0002);
3047         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3048         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3049
3050         /* Switching regulator Slew rate */
3051         rtl_writephy(tp, 0x1f, 0x0002);
3052         rtl_patchphy(tp, 0x0f, 0x0017);
3053
3054         rtl_writephy(tp, 0x1f, 0x0005);
3055         rtl_writephy(tp, 0x05, 0x001b);
3056
3057         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3058
3059         rtl_writephy(tp, 0x1f, 0x0000);
3060 }
3061
3062 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3063 {
3064         static const struct phy_reg phy_reg_init[] = {
3065                 { 0x1f, 0x0002 },
3066                 { 0x10, 0x0008 },
3067                 { 0x0d, 0x006c },
3068
3069                 { 0x1f, 0x0000 },
3070                 { 0x0d, 0xf880 },
3071
3072                 { 0x1f, 0x0001 },
3073                 { 0x17, 0x0cc0 },
3074
3075                 { 0x1f, 0x0001 },
3076                 { 0x0b, 0xa4d8 },
3077                 { 0x09, 0x281c },
3078                 { 0x07, 0x2883 },
3079                 { 0x0a, 0x6b35 },
3080                 { 0x1d, 0x3da4 },
3081                 { 0x1c, 0xeffd },
3082                 { 0x14, 0x7f52 },
3083                 { 0x18, 0x7fc6 },
3084                 { 0x08, 0x0601 },
3085                 { 0x06, 0x4063 },
3086                 { 0x10, 0xf074 },
3087                 { 0x1f, 0x0003 },
3088                 { 0x13, 0x0789 },
3089                 { 0x12, 0xf4bd },
3090                 { 0x1a, 0x04fd },
3091                 { 0x14, 0x84b0 },
3092                 { 0x1f, 0x0000 },
3093                 { 0x00, 0x9200 },
3094
3095                 { 0x1f, 0x0005 },
3096                 { 0x01, 0x0340 },
3097                 { 0x1f, 0x0001 },
3098                 { 0x04, 0x4000 },
3099                 { 0x03, 0x1d21 },
3100                 { 0x02, 0x0c32 },
3101                 { 0x01, 0x0200 },
3102                 { 0x00, 0x5554 },
3103                 { 0x04, 0x4800 },
3104                 { 0x04, 0x4000 },
3105                 { 0x04, 0xf000 },
3106                 { 0x03, 0xdf01 },
3107                 { 0x02, 0xdf20 },
3108                 { 0x01, 0x101a },
3109                 { 0x00, 0xa0ff },
3110                 { 0x04, 0xf800 },
3111                 { 0x04, 0xf000 },
3112                 { 0x1f, 0x0000 },
3113
3114                 { 0x1f, 0x0007 },
3115                 { 0x1e, 0x0023 },
3116                 { 0x16, 0x0000 },
3117                 { 0x1f, 0x0000 }
3118         };
3119
3120         rtl_writephy_batch(tp, phy_reg_init);
3121 }
3122
3123 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3124 {
3125         static const struct phy_reg phy_reg_init[] = {
3126                 { 0x1f, 0x0001 },
3127                 { 0x17, 0x0cc0 },
3128
3129                 { 0x1f, 0x0007 },
3130                 { 0x1e, 0x002d },
3131                 { 0x18, 0x0040 },
3132                 { 0x1f, 0x0000 }
3133         };
3134
3135         rtl_writephy_batch(tp, phy_reg_init);
3136         rtl_patchphy(tp, 0x0d, 1 << 5);
3137 }
3138
3139 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3140 {
3141         static const struct phy_reg phy_reg_init[] = {
3142                 /* Enable Delay cap */
3143                 { 0x1f, 0x0005 },
3144                 { 0x05, 0x8b80 },
3145                 { 0x06, 0xc896 },
3146                 { 0x1f, 0x0000 },
3147
3148                 /* Channel estimation fine tune */
3149                 { 0x1f, 0x0001 },
3150                 { 0x0b, 0x6c20 },
3151                 { 0x07, 0x2872 },
3152                 { 0x1c, 0xefff },
3153                 { 0x1f, 0x0003 },
3154                 { 0x14, 0x6420 },
3155                 { 0x1f, 0x0000 },
3156
3157                 /* Update PFM & 10M TX idle timer */
3158                 { 0x1f, 0x0007 },
3159                 { 0x1e, 0x002f },
3160                 { 0x15, 0x1919 },
3161                 { 0x1f, 0x0000 },
3162
3163                 { 0x1f, 0x0007 },
3164                 { 0x1e, 0x00ac },
3165                 { 0x18, 0x0006 },
3166                 { 0x1f, 0x0000 }
3167         };
3168
3169         rtl_apply_firmware(tp);
3170
3171         rtl_writephy_batch(tp, phy_reg_init);
3172
3173         /* DCO enable for 10M IDLE Power */
3174         rtl_writephy(tp, 0x1f, 0x0007);
3175         rtl_writephy(tp, 0x1e, 0x0023);
3176         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3177         rtl_writephy(tp, 0x1f, 0x0000);
3178
3179         /* For impedance matching */
3180         rtl_writephy(tp, 0x1f, 0x0002);
3181         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3182         rtl_writephy(tp, 0x1f, 0x0000);
3183
3184         /* PHY auto speed down */
3185         rtl_writephy(tp, 0x1f, 0x0007);
3186         rtl_writephy(tp, 0x1e, 0x002d);
3187         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3188         rtl_writephy(tp, 0x1f, 0x0000);
3189         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3190
3191         rtl_writephy(tp, 0x1f, 0x0005);
3192         rtl_writephy(tp, 0x05, 0x8b86);
3193         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3194         rtl_writephy(tp, 0x1f, 0x0000);
3195
3196         rtl_writephy(tp, 0x1f, 0x0005);
3197         rtl_writephy(tp, 0x05, 0x8b85);
3198         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3199         rtl_writephy(tp, 0x1f, 0x0007);
3200         rtl_writephy(tp, 0x1e, 0x0020);
3201         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3202         rtl_writephy(tp, 0x1f, 0x0006);
3203         rtl_writephy(tp, 0x00, 0x5a00);
3204         rtl_writephy(tp, 0x1f, 0x0000);
3205         rtl_writephy(tp, 0x0d, 0x0007);
3206         rtl_writephy(tp, 0x0e, 0x003c);
3207         rtl_writephy(tp, 0x0d, 0x4007);
3208         rtl_writephy(tp, 0x0e, 0x0000);
3209         rtl_writephy(tp, 0x0d, 0x0000);
3210 }
3211
3212 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3213 {
3214         const u16 w[] = {
3215                 addr[0] | (addr[1] << 8),
3216                 addr[2] | (addr[3] << 8),
3217                 addr[4] | (addr[5] << 8)
3218         };
3219
3220         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3221         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3222         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3223         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3224 }
3225
3226 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3227 {
3228         static const struct phy_reg phy_reg_init[] = {
3229                 /* Enable Delay cap */
3230                 { 0x1f, 0x0004 },
3231                 { 0x1f, 0x0007 },
3232                 { 0x1e, 0x00ac },
3233                 { 0x18, 0x0006 },
3234                 { 0x1f, 0x0002 },
3235                 { 0x1f, 0x0000 },
3236                 { 0x1f, 0x0000 },
3237
3238                 /* Channel estimation fine tune */
3239                 { 0x1f, 0x0003 },
3240                 { 0x09, 0xa20f },
3241                 { 0x1f, 0x0000 },
3242                 { 0x1f, 0x0000 },
3243
3244                 /* Green Setting */
3245                 { 0x1f, 0x0005 },
3246                 { 0x05, 0x8b5b },
3247                 { 0x06, 0x9222 },
3248                 { 0x05, 0x8b6d },
3249                 { 0x06, 0x8000 },
3250                 { 0x05, 0x8b76 },
3251                 { 0x06, 0x8000 },
3252                 { 0x1f, 0x0000 }
3253         };
3254
3255         rtl_apply_firmware(tp);
3256
3257         rtl_writephy_batch(tp, phy_reg_init);
3258
3259         /* For 4-corner performance improve */
3260         rtl_writephy(tp, 0x1f, 0x0005);
3261         rtl_writephy(tp, 0x05, 0x8b80);
3262         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3263         rtl_writephy(tp, 0x1f, 0x0000);
3264
3265         /* PHY auto speed down */
3266         rtl_writephy(tp, 0x1f, 0x0004);
3267         rtl_writephy(tp, 0x1f, 0x0007);
3268         rtl_writephy(tp, 0x1e, 0x002d);
3269         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3270         rtl_writephy(tp, 0x1f, 0x0002);
3271         rtl_writephy(tp, 0x1f, 0x0000);
3272         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3273
3274         /* improve 10M EEE waveform */
3275         rtl_writephy(tp, 0x1f, 0x0005);
3276         rtl_writephy(tp, 0x05, 0x8b86);
3277         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3278         rtl_writephy(tp, 0x1f, 0x0000);
3279
3280         /* Improve 2-pair detection performance */
3281         rtl_writephy(tp, 0x1f, 0x0005);
3282         rtl_writephy(tp, 0x05, 0x8b85);
3283         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3284         rtl_writephy(tp, 0x1f, 0x0000);
3285
3286         rtl8168f_config_eee_phy(tp);
3287         rtl_enable_eee(tp);
3288
3289         /* Green feature */
3290         rtl_writephy(tp, 0x1f, 0x0003);
3291         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3292         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3293         rtl_writephy(tp, 0x1f, 0x0000);
3294         rtl_writephy(tp, 0x1f, 0x0005);
3295         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3296         rtl_writephy(tp, 0x1f, 0x0000);
3297
3298         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3299         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3300 }
3301
3302 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3303 {
3304         /* For 4-corner performance improve */
3305         rtl_writephy(tp, 0x1f, 0x0005);
3306         rtl_writephy(tp, 0x05, 0x8b80);
3307         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3308         rtl_writephy(tp, 0x1f, 0x0000);
3309
3310         /* PHY auto speed down */
3311         rtl_writephy(tp, 0x1f, 0x0007);
3312         rtl_writephy(tp, 0x1e, 0x002d);
3313         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3314         rtl_writephy(tp, 0x1f, 0x0000);
3315         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3316
3317         /* Improve 10M EEE waveform */
3318         rtl_writephy(tp, 0x1f, 0x0005);
3319         rtl_writephy(tp, 0x05, 0x8b86);
3320         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3321         rtl_writephy(tp, 0x1f, 0x0000);
3322
3323         rtl8168f_config_eee_phy(tp);
3324         rtl_enable_eee(tp);
3325 }
3326
3327 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3328 {
3329         static const struct phy_reg phy_reg_init[] = {
3330                 /* Channel estimation fine tune */
3331                 { 0x1f, 0x0003 },
3332                 { 0x09, 0xa20f },
3333                 { 0x1f, 0x0000 },
3334
3335                 /* Modify green table for giga & fnet */
3336                 { 0x1f, 0x0005 },
3337                 { 0x05, 0x8b55 },
3338                 { 0x06, 0x0000 },
3339                 { 0x05, 0x8b5e },
3340                 { 0x06, 0x0000 },
3341                 { 0x05, 0x8b67 },
3342                 { 0x06, 0x0000 },
3343                 { 0x05, 0x8b70 },
3344                 { 0x06, 0x0000 },
3345                 { 0x1f, 0x0000 },
3346                 { 0x1f, 0x0007 },
3347                 { 0x1e, 0x0078 },
3348                 { 0x17, 0x0000 },
3349                 { 0x19, 0x00fb },
3350                 { 0x1f, 0x0000 },
3351
3352                 /* Modify green table for 10M */
3353                 { 0x1f, 0x0005 },
3354                 { 0x05, 0x8b79 },
3355                 { 0x06, 0xaa00 },
3356                 { 0x1f, 0x0000 },
3357
3358                 /* Disable hiimpedance detection (RTCT) */
3359                 { 0x1f, 0x0003 },
3360                 { 0x01, 0x328a },
3361                 { 0x1f, 0x0000 }
3362         };
3363
3364         rtl_apply_firmware(tp);
3365
3366         rtl_writephy_batch(tp, phy_reg_init);
3367
3368         rtl8168f_hw_phy_config(tp);
3369
3370         /* Improve 2-pair detection performance */
3371         rtl_writephy(tp, 0x1f, 0x0005);
3372         rtl_writephy(tp, 0x05, 0x8b85);
3373         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3374         rtl_writephy(tp, 0x1f, 0x0000);
3375 }
3376
3377 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3378 {
3379         rtl_apply_firmware(tp);
3380
3381         rtl8168f_hw_phy_config(tp);
3382 }
3383
3384 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3385 {
3386         static const struct phy_reg phy_reg_init[] = {
3387                 /* Channel estimation fine tune */
3388                 { 0x1f, 0x0003 },
3389                 { 0x09, 0xa20f },
3390                 { 0x1f, 0x0000 },
3391
3392                 /* Modify green table for giga & fnet */
3393                 { 0x1f, 0x0005 },
3394                 { 0x05, 0x8b55 },
3395                 { 0x06, 0x0000 },
3396                 { 0x05, 0x8b5e },
3397                 { 0x06, 0x0000 },
3398                 { 0x05, 0x8b67 },
3399                 { 0x06, 0x0000 },
3400                 { 0x05, 0x8b70 },
3401                 { 0x06, 0x0000 },
3402                 { 0x1f, 0x0000 },
3403                 { 0x1f, 0x0007 },
3404                 { 0x1e, 0x0078 },
3405                 { 0x17, 0x0000 },
3406                 { 0x19, 0x00aa },
3407                 { 0x1f, 0x0000 },
3408
3409                 /* Modify green table for 10M */
3410                 { 0x1f, 0x0005 },
3411                 { 0x05, 0x8b79 },
3412                 { 0x06, 0xaa00 },
3413                 { 0x1f, 0x0000 },
3414
3415                 /* Disable hiimpedance detection (RTCT) */
3416                 { 0x1f, 0x0003 },
3417                 { 0x01, 0x328a },
3418                 { 0x1f, 0x0000 }
3419         };
3420
3421
3422         rtl_apply_firmware(tp);
3423
3424         rtl8168f_hw_phy_config(tp);
3425
3426         /* Improve 2-pair detection performance */
3427         rtl_writephy(tp, 0x1f, 0x0005);
3428         rtl_writephy(tp, 0x05, 0x8b85);
3429         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3430         rtl_writephy(tp, 0x1f, 0x0000);
3431
3432         rtl_writephy_batch(tp, phy_reg_init);
3433
3434         /* Modify green table for giga */
3435         rtl_writephy(tp, 0x1f, 0x0005);
3436         rtl_writephy(tp, 0x05, 0x8b54);
3437         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3438         rtl_writephy(tp, 0x05, 0x8b5d);
3439         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3440         rtl_writephy(tp, 0x05, 0x8a7c);
3441         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3442         rtl_writephy(tp, 0x05, 0x8a7f);
3443         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3444         rtl_writephy(tp, 0x05, 0x8a82);
3445         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3446         rtl_writephy(tp, 0x05, 0x8a85);
3447         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3448         rtl_writephy(tp, 0x05, 0x8a88);
3449         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3450         rtl_writephy(tp, 0x1f, 0x0000);
3451
3452         /* uc same-seed solution */
3453         rtl_writephy(tp, 0x1f, 0x0005);
3454         rtl_writephy(tp, 0x05, 0x8b85);
3455         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3456         rtl_writephy(tp, 0x1f, 0x0000);
3457
3458         /* Green feature */
3459         rtl_writephy(tp, 0x1f, 0x0003);
3460         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3461         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3462         rtl_writephy(tp, 0x1f, 0x0000);
3463 }
3464
3465 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3466 {
3467         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3468 }
3469
3470 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3471 {
3472         struct phy_device *phydev = tp->phydev;
3473
3474         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3475         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3476         phy_write(phydev, 0x1f, 0x0a43);
3477         phy_write(phydev, 0x13, 0x8084);
3478         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3479         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3480
3481         phy_write(phydev, 0x1f, 0x0000);
3482 }
3483
3484 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3485 {
3486         int ret;
3487
3488         rtl_apply_firmware(tp);
3489
3490         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3491         if (ret & BIT(8))
3492                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3493         else
3494                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3495
3496         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3497         if (ret & BIT(8))
3498                 phy_modify_paged(tp->phydev, 0x0c41, 0x12, 0, BIT(1));
3499         else
3500                 phy_modify_paged(tp->phydev, 0x0c41, 0x12, BIT(1), 0);
3501
3502         /* Enable PHY auto speed down */
3503         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3504
3505         rtl8168g_phy_adjust_10m_aldps(tp);
3506
3507         /* EEE auto-fallback function */
3508         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3509
3510         /* Enable UC LPF tune function */
3511         rtl_writephy(tp, 0x1f, 0x0a43);
3512         rtl_writephy(tp, 0x13, 0x8012);
3513         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3514
3515         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3516
3517         /* Improve SWR Efficiency */
3518         rtl_writephy(tp, 0x1f, 0x0bcd);
3519         rtl_writephy(tp, 0x14, 0x5065);
3520         rtl_writephy(tp, 0x14, 0xd065);
3521         rtl_writephy(tp, 0x1f, 0x0bc8);
3522         rtl_writephy(tp, 0x11, 0x5655);
3523         rtl_writephy(tp, 0x1f, 0x0bcd);
3524         rtl_writephy(tp, 0x14, 0x1065);
3525         rtl_writephy(tp, 0x14, 0x9065);
3526         rtl_writephy(tp, 0x14, 0x1065);
3527         rtl_writephy(tp, 0x1f, 0x0000);
3528
3529         rtl8168g_disable_aldps(tp);
3530         rtl8168g_config_eee_phy(tp);
3531         rtl_enable_eee(tp);
3532 }
3533
3534 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3535 {
3536         rtl_apply_firmware(tp);
3537         rtl8168g_config_eee_phy(tp);
3538         rtl_enable_eee(tp);
3539 }
3540
3541 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3542 {
3543         u16 dout_tapbin;
3544         u32 data;
3545
3546         rtl_apply_firmware(tp);
3547
3548         /* CHN EST parameters adjust - giga master */
3549         rtl_writephy(tp, 0x1f, 0x0a43);
3550         rtl_writephy(tp, 0x13, 0x809b);
3551         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3552         rtl_writephy(tp, 0x13, 0x80a2);
3553         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3554         rtl_writephy(tp, 0x13, 0x80a4);
3555         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3556         rtl_writephy(tp, 0x13, 0x809c);
3557         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3558         rtl_writephy(tp, 0x1f, 0x0000);
3559
3560         /* CHN EST parameters adjust - giga slave */
3561         rtl_writephy(tp, 0x1f, 0x0a43);
3562         rtl_writephy(tp, 0x13, 0x80ad);
3563         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3564         rtl_writephy(tp, 0x13, 0x80b4);
3565         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3566         rtl_writephy(tp, 0x13, 0x80ac);
3567         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3568         rtl_writephy(tp, 0x1f, 0x0000);
3569
3570         /* CHN EST parameters adjust - fnet */
3571         rtl_writephy(tp, 0x1f, 0x0a43);
3572         rtl_writephy(tp, 0x13, 0x808e);
3573         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3574         rtl_writephy(tp, 0x13, 0x8090);
3575         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3576         rtl_writephy(tp, 0x13, 0x8092);
3577         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3578         rtl_writephy(tp, 0x1f, 0x0000);
3579
3580         /* enable R-tune & PGA-retune function */
3581         dout_tapbin = 0;
3582         rtl_writephy(tp, 0x1f, 0x0a46);
3583         data = rtl_readphy(tp, 0x13);
3584         data &= 3;
3585         data <<= 2;
3586         dout_tapbin |= data;
3587         data = rtl_readphy(tp, 0x12);
3588         data &= 0xc000;
3589         data >>= 14;
3590         dout_tapbin |= data;
3591         dout_tapbin = ~(dout_tapbin^0x08);
3592         dout_tapbin <<= 12;
3593         dout_tapbin &= 0xf000;
3594         rtl_writephy(tp, 0x1f, 0x0a43);
3595         rtl_writephy(tp, 0x13, 0x827a);
3596         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3597         rtl_writephy(tp, 0x13, 0x827b);
3598         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3599         rtl_writephy(tp, 0x13, 0x827c);
3600         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3601         rtl_writephy(tp, 0x13, 0x827d);
3602         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3603
3604         rtl_writephy(tp, 0x1f, 0x0a43);
3605         rtl_writephy(tp, 0x13, 0x0811);
3606         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3607         rtl_writephy(tp, 0x1f, 0x0a42);
3608         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3609         rtl_writephy(tp, 0x1f, 0x0000);
3610
3611         /* enable GPHY 10M */
3612         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3613
3614         /* SAR ADC performance */
3615         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3616
3617         rtl_writephy(tp, 0x1f, 0x0a43);
3618         rtl_writephy(tp, 0x13, 0x803f);
3619         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3620         rtl_writephy(tp, 0x13, 0x8047);
3621         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3622         rtl_writephy(tp, 0x13, 0x804f);
3623         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3624         rtl_writephy(tp, 0x13, 0x8057);
3625         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3626         rtl_writephy(tp, 0x13, 0x805f);
3627         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3628         rtl_writephy(tp, 0x13, 0x8067);
3629         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3630         rtl_writephy(tp, 0x13, 0x806f);
3631         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3632         rtl_writephy(tp, 0x1f, 0x0000);
3633
3634         /* disable phy pfm mode */
3635         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3636
3637         rtl8168g_disable_aldps(tp);
3638         rtl8168g_config_eee_phy(tp);
3639         rtl_enable_eee(tp);
3640 }
3641
3642 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3643 {
3644         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3645         u16 rlen;
3646         u32 data;
3647
3648         rtl_apply_firmware(tp);
3649
3650         /* CHIN EST parameter update */
3651         rtl_writephy(tp, 0x1f, 0x0a43);
3652         rtl_writephy(tp, 0x13, 0x808a);
3653         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3654         rtl_writephy(tp, 0x1f, 0x0000);
3655
3656         /* enable R-tune & PGA-retune function */
3657         rtl_writephy(tp, 0x1f, 0x0a43);
3658         rtl_writephy(tp, 0x13, 0x0811);
3659         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3660         rtl_writephy(tp, 0x1f, 0x0a42);
3661         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3662         rtl_writephy(tp, 0x1f, 0x0000);
3663
3664         /* enable GPHY 10M */
3665         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3666
3667         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3668         data = r8168_mac_ocp_read(tp, 0xdd02);
3669         ioffset_p3 = ((data & 0x80)>>7);
3670         ioffset_p3 <<= 3;
3671
3672         data = r8168_mac_ocp_read(tp, 0xdd00);
3673         ioffset_p3 |= ((data & (0xe000))>>13);
3674         ioffset_p2 = ((data & (0x1e00))>>9);
3675         ioffset_p1 = ((data & (0x01e0))>>5);
3676         ioffset_p0 = ((data & 0x0010)>>4);
3677         ioffset_p0 <<= 3;
3678         ioffset_p0 |= (data & (0x07));
3679         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3680
3681         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3682             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3683                 rtl_writephy(tp, 0x1f, 0x0bcf);
3684                 rtl_writephy(tp, 0x16, data);
3685                 rtl_writephy(tp, 0x1f, 0x0000);
3686         }
3687
3688         /* Modify rlen (TX LPF corner frequency) level */
3689         rtl_writephy(tp, 0x1f, 0x0bcd);
3690         data = rtl_readphy(tp, 0x16);
3691         data &= 0x000f;
3692         rlen = 0;
3693         if (data > 3)
3694                 rlen = data - 3;
3695         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3696         rtl_writephy(tp, 0x17, data);
3697         rtl_writephy(tp, 0x1f, 0x0bcd);
3698         rtl_writephy(tp, 0x1f, 0x0000);
3699
3700         /* disable phy pfm mode */
3701         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3702
3703         rtl8168g_disable_aldps(tp);
3704         rtl8168g_config_eee_phy(tp);
3705         rtl_enable_eee(tp);
3706 }
3707
3708 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3709 {
3710         /* Enable PHY auto speed down */
3711         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3712
3713         rtl8168g_phy_adjust_10m_aldps(tp);
3714
3715         /* Enable EEE auto-fallback function */
3716         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3717
3718         /* Enable UC LPF tune function */
3719         rtl_writephy(tp, 0x1f, 0x0a43);
3720         rtl_writephy(tp, 0x13, 0x8012);
3721         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3722         rtl_writephy(tp, 0x1f, 0x0000);
3723
3724         /* set rg_sel_sdm_rate */
3725         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3726
3727         rtl8168g_disable_aldps(tp);
3728         rtl8168g_config_eee_phy(tp);
3729         rtl_enable_eee(tp);
3730 }
3731
3732 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3733 {
3734         rtl8168g_phy_adjust_10m_aldps(tp);
3735
3736         /* Enable UC LPF tune function */
3737         rtl_writephy(tp, 0x1f, 0x0a43);
3738         rtl_writephy(tp, 0x13, 0x8012);
3739         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3740         rtl_writephy(tp, 0x1f, 0x0000);
3741
3742         /* Set rg_sel_sdm_rate */
3743         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3744
3745         /* Channel estimation parameters */
3746         rtl_writephy(tp, 0x1f, 0x0a43);
3747         rtl_writephy(tp, 0x13, 0x80f3);
3748         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3749         rtl_writephy(tp, 0x13, 0x80f0);
3750         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3751         rtl_writephy(tp, 0x13, 0x80ef);
3752         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3753         rtl_writephy(tp, 0x13, 0x80f6);
3754         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3755         rtl_writephy(tp, 0x13, 0x80ec);
3756         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3757         rtl_writephy(tp, 0x13, 0x80ed);
3758         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3759         rtl_writephy(tp, 0x13, 0x80f2);
3760         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3761         rtl_writephy(tp, 0x13, 0x80f4);
3762         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3763         rtl_writephy(tp, 0x1f, 0x0a43);
3764         rtl_writephy(tp, 0x13, 0x8110);
3765         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3766         rtl_writephy(tp, 0x13, 0x810f);
3767         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3768         rtl_writephy(tp, 0x13, 0x8111);
3769         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3770         rtl_writephy(tp, 0x13, 0x8113);
3771         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3772         rtl_writephy(tp, 0x13, 0x8115);
3773         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3774         rtl_writephy(tp, 0x13, 0x810e);
3775         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3776         rtl_writephy(tp, 0x13, 0x810c);
3777         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3778         rtl_writephy(tp, 0x13, 0x810b);
3779         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3780         rtl_writephy(tp, 0x1f, 0x0a43);
3781         rtl_writephy(tp, 0x13, 0x80d1);
3782         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3783         rtl_writephy(tp, 0x13, 0x80cd);
3784         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3785         rtl_writephy(tp, 0x13, 0x80d3);
3786         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3787         rtl_writephy(tp, 0x13, 0x80d5);
3788         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3789         rtl_writephy(tp, 0x13, 0x80d7);
3790         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3791
3792         /* Force PWM-mode */
3793         rtl_writephy(tp, 0x1f, 0x0bcd);
3794         rtl_writephy(tp, 0x14, 0x5065);
3795         rtl_writephy(tp, 0x14, 0xd065);
3796         rtl_writephy(tp, 0x1f, 0x0bc8);
3797         rtl_writephy(tp, 0x12, 0x00ed);
3798         rtl_writephy(tp, 0x1f, 0x0bcd);
3799         rtl_writephy(tp, 0x14, 0x1065);
3800         rtl_writephy(tp, 0x14, 0x9065);
3801         rtl_writephy(tp, 0x14, 0x1065);
3802         rtl_writephy(tp, 0x1f, 0x0000);
3803
3804         rtl8168g_disable_aldps(tp);
3805         rtl8168g_config_eee_phy(tp);
3806         rtl_enable_eee(tp);
3807 }
3808
3809 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3810 {
3811         static const struct phy_reg phy_reg_init[] = {
3812                 { 0x1f, 0x0003 },
3813                 { 0x08, 0x441d },
3814                 { 0x01, 0x9100 },
3815                 { 0x1f, 0x0000 }
3816         };
3817
3818         rtl_writephy(tp, 0x1f, 0x0000);
3819         rtl_patchphy(tp, 0x11, 1 << 12);
3820         rtl_patchphy(tp, 0x19, 1 << 13);
3821         rtl_patchphy(tp, 0x10, 1 << 15);
3822
3823         rtl_writephy_batch(tp, phy_reg_init);
3824 }
3825
3826 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3827 {
3828         static const struct phy_reg phy_reg_init[] = {
3829                 { 0x1f, 0x0005 },
3830                 { 0x1a, 0x0000 },
3831                 { 0x1f, 0x0000 },
3832
3833                 { 0x1f, 0x0004 },
3834                 { 0x1c, 0x0000 },
3835                 { 0x1f, 0x0000 },
3836
3837                 { 0x1f, 0x0001 },
3838                 { 0x15, 0x7701 },
3839                 { 0x1f, 0x0000 }
3840         };
3841
3842         /* Disable ALDPS before ram code */
3843         rtl_writephy(tp, 0x1f, 0x0000);
3844         rtl_writephy(tp, 0x18, 0x0310);
3845         msleep(100);
3846
3847         rtl_apply_firmware(tp);
3848
3849         rtl_writephy_batch(tp, phy_reg_init);
3850 }
3851
3852 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3853 {
3854         /* Disable ALDPS before setting firmware */
3855         rtl_writephy(tp, 0x1f, 0x0000);
3856         rtl_writephy(tp, 0x18, 0x0310);
3857         msleep(20);
3858
3859         rtl_apply_firmware(tp);
3860
3861         /* EEE setting */
3862         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3863         rtl_writephy(tp, 0x1f, 0x0004);
3864         rtl_writephy(tp, 0x10, 0x401f);
3865         rtl_writephy(tp, 0x19, 0x7030);
3866         rtl_writephy(tp, 0x1f, 0x0000);
3867 }
3868
3869 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3870 {
3871         static const struct phy_reg phy_reg_init[] = {
3872                 { 0x1f, 0x0004 },
3873                 { 0x10, 0xc07f },
3874                 { 0x19, 0x7030 },
3875                 { 0x1f, 0x0000 }
3876         };
3877
3878         /* Disable ALDPS before ram code */
3879         rtl_writephy(tp, 0x1f, 0x0000);
3880         rtl_writephy(tp, 0x18, 0x0310);
3881         msleep(100);
3882
3883         rtl_apply_firmware(tp);
3884
3885         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3886         rtl_writephy_batch(tp, phy_reg_init);
3887
3888         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3889 }
3890
3891 static void rtl_hw_phy_config(struct net_device *dev)
3892 {
3893         static const rtl_generic_fct phy_configs[] = {
3894                 /* PCI devices. */
3895                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3896                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3897                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3898                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3899                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3900                 /* PCI-E devices. */
3901                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3902                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3903                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3904                 [RTL_GIGA_MAC_VER_10] = NULL,
3905                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3906                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3907                 [RTL_GIGA_MAC_VER_13] = NULL,
3908                 [RTL_GIGA_MAC_VER_14] = NULL,
3909                 [RTL_GIGA_MAC_VER_15] = NULL,
3910                 [RTL_GIGA_MAC_VER_16] = NULL,
3911                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3912                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3913                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3914                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3915                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3916                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3917                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3918                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3919                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3920                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3921                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3922                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3923                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3924                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3925                 [RTL_GIGA_MAC_VER_31] = NULL,
3926                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3927                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3928                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3929                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3930                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3931                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3932                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3933                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3934                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3935                 [RTL_GIGA_MAC_VER_41] = NULL,
3936                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3937                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3938                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3939                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3940                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3941                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3942                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3943                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3944                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3945                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3946         };
3947         struct rtl8169_private *tp = netdev_priv(dev);
3948
3949         if (phy_configs[tp->mac_version])
3950                 phy_configs[tp->mac_version](tp);
3951 }
3952
3953 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3954 {
3955         if (!test_and_set_bit(flag, tp->wk.flags))
3956                 schedule_work(&tp->wk.work);
3957 }
3958
3959 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3960 {
3961         rtl_hw_phy_config(dev);
3962
3963         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3964                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3965                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3966                 netif_dbg(tp, drv, dev,
3967                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3968                 RTL_W8(tp, 0x82, 0x01);
3969         }
3970
3971         /* We may have called phy_speed_down before */
3972         phy_speed_up(tp->phydev);
3973
3974         genphy_soft_reset(tp->phydev);
3975 }
3976
3977 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3978 {
3979         rtl_lock_work(tp);
3980
3981         rtl_unlock_config_regs(tp);
3982
3983         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3984         RTL_R32(tp, MAC4);
3985
3986         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3987         RTL_R32(tp, MAC0);
3988
3989         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3990                 rtl_rar_exgmac_set(tp, addr);
3991
3992         rtl_lock_config_regs(tp);
3993
3994         rtl_unlock_work(tp);
3995 }
3996
3997 static int rtl_set_mac_address(struct net_device *dev, void *p)
3998 {
3999         struct rtl8169_private *tp = netdev_priv(dev);
4000         struct device *d = tp_to_dev(tp);
4001         int ret;
4002
4003         ret = eth_mac_addr(dev, p);
4004         if (ret)
4005                 return ret;
4006
4007         pm_runtime_get_noresume(d);
4008
4009         if (pm_runtime_active(d))
4010                 rtl_rar_set(tp, dev->dev_addr);
4011
4012         pm_runtime_put_noidle(d);
4013
4014         return 0;
4015 }
4016
4017 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4018 {
4019         struct rtl8169_private *tp = netdev_priv(dev);
4020
4021         if (!netif_running(dev))
4022                 return -ENODEV;
4023
4024         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4025 }
4026
4027 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4028 {
4029         switch (tp->mac_version) {
4030         case RTL_GIGA_MAC_VER_25:
4031         case RTL_GIGA_MAC_VER_26:
4032         case RTL_GIGA_MAC_VER_29:
4033         case RTL_GIGA_MAC_VER_30:
4034         case RTL_GIGA_MAC_VER_32:
4035         case RTL_GIGA_MAC_VER_33:
4036         case RTL_GIGA_MAC_VER_34:
4037         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4038                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4039                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4040                 break;
4041         default:
4042                 break;
4043         }
4044 }
4045
4046 static void rtl_pll_power_down(struct rtl8169_private *tp)
4047 {
4048         if (r8168_check_dash(tp))
4049                 return;
4050
4051         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4052             tp->mac_version == RTL_GIGA_MAC_VER_33)
4053                 rtl_ephy_write(tp, 0x19, 0xff64);
4054
4055         if (device_may_wakeup(tp_to_dev(tp))) {
4056                 phy_speed_down(tp->phydev, false);
4057                 rtl_wol_suspend_quirk(tp);
4058                 return;
4059         }
4060
4061         switch (tp->mac_version) {
4062         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4063         case RTL_GIGA_MAC_VER_37:
4064         case RTL_GIGA_MAC_VER_39:
4065         case RTL_GIGA_MAC_VER_43:
4066         case RTL_GIGA_MAC_VER_44:
4067         case RTL_GIGA_MAC_VER_45:
4068         case RTL_GIGA_MAC_VER_46:
4069         case RTL_GIGA_MAC_VER_47:
4070         case RTL_GIGA_MAC_VER_48:
4071         case RTL_GIGA_MAC_VER_50:
4072         case RTL_GIGA_MAC_VER_51:
4073                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4074                 break;
4075         case RTL_GIGA_MAC_VER_40:
4076         case RTL_GIGA_MAC_VER_41:
4077         case RTL_GIGA_MAC_VER_49:
4078                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4079                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4080                 break;
4081         default:
4082                 break;
4083         }
4084 }
4085
4086 static void rtl_pll_power_up(struct rtl8169_private *tp)
4087 {
4088         switch (tp->mac_version) {
4089         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4090         case RTL_GIGA_MAC_VER_37:
4091         case RTL_GIGA_MAC_VER_39:
4092         case RTL_GIGA_MAC_VER_43:
4093                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4094                 break;
4095         case RTL_GIGA_MAC_VER_44:
4096         case RTL_GIGA_MAC_VER_45:
4097         case RTL_GIGA_MAC_VER_46:
4098         case RTL_GIGA_MAC_VER_47:
4099         case RTL_GIGA_MAC_VER_48:
4100         case RTL_GIGA_MAC_VER_50:
4101         case RTL_GIGA_MAC_VER_51:
4102                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4103                 break;
4104         case RTL_GIGA_MAC_VER_40:
4105         case RTL_GIGA_MAC_VER_41:
4106         case RTL_GIGA_MAC_VER_49:
4107                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4108                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4109                 break;
4110         default:
4111                 break;
4112         }
4113
4114         phy_resume(tp->phydev);
4115         /* give MAC/PHY some time to resume */
4116         msleep(20);
4117 }
4118
4119 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4120 {
4121         switch (tp->mac_version) {
4122         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4123         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4124                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4125                 break;
4126         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4127         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4128         case RTL_GIGA_MAC_VER_38:
4129                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4130                 break;
4131         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4132                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4133                 break;
4134         default:
4135                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4136                 break;
4137         }
4138 }
4139
4140 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4141 {
4142         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4143 }
4144
4145 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4146 {
4147         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4148         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4149         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4150 }
4151
4152 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4153 {
4154         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4155         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4156         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4157 }
4158
4159 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4160 {
4161         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4162 }
4163
4164 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4165 {
4166         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4167 }
4168
4169 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4170 {
4171         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4172         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4173         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4174         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4175 }
4176
4177 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4178 {
4179         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4180         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4181         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4182         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4183 }
4184
4185 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4186 {
4187         rtl_tx_performance_tweak(tp,
4188                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4189 }
4190
4191 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4192 {
4193         rtl_tx_performance_tweak(tp,
4194                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4195 }
4196
4197 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4198 {
4199         r8168b_0_hw_jumbo_enable(tp);
4200
4201         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4202 }
4203
4204 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4205 {
4206         r8168b_0_hw_jumbo_disable(tp);
4207
4208         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4209 }
4210
4211 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4212 {
4213         rtl_unlock_config_regs(tp);
4214         switch (tp->mac_version) {
4215         case RTL_GIGA_MAC_VER_11:
4216                 r8168b_0_hw_jumbo_enable(tp);
4217                 break;
4218         case RTL_GIGA_MAC_VER_12:
4219         case RTL_GIGA_MAC_VER_17:
4220                 r8168b_1_hw_jumbo_enable(tp);
4221                 break;
4222         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4223                 r8168c_hw_jumbo_enable(tp);
4224                 break;
4225         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4226                 r8168dp_hw_jumbo_enable(tp);
4227                 break;
4228         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4229                 r8168e_hw_jumbo_enable(tp);
4230                 break;
4231         default:
4232                 break;
4233         }
4234         rtl_lock_config_regs(tp);
4235 }
4236
4237 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4238 {
4239         rtl_unlock_config_regs(tp);
4240         switch (tp->mac_version) {
4241         case RTL_GIGA_MAC_VER_11:
4242                 r8168b_0_hw_jumbo_disable(tp);
4243                 break;
4244         case RTL_GIGA_MAC_VER_12:
4245         case RTL_GIGA_MAC_VER_17:
4246                 r8168b_1_hw_jumbo_disable(tp);
4247                 break;
4248         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4249                 r8168c_hw_jumbo_disable(tp);
4250                 break;
4251         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4252                 r8168dp_hw_jumbo_disable(tp);
4253                 break;
4254         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4255                 r8168e_hw_jumbo_disable(tp);
4256                 break;
4257         default:
4258                 break;
4259         }
4260         rtl_lock_config_regs(tp);
4261 }
4262
4263 DECLARE_RTL_COND(rtl_chipcmd_cond)
4264 {
4265         return RTL_R8(tp, ChipCmd) & CmdReset;
4266 }
4267
4268 static void rtl_hw_reset(struct rtl8169_private *tp)
4269 {
4270         RTL_W8(tp, ChipCmd, CmdReset);
4271
4272         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4273 }
4274
4275 static void rtl_request_firmware(struct rtl8169_private *tp)
4276 {
4277         struct rtl_fw *rtl_fw;
4278         int rc = -ENOMEM;
4279
4280         /* firmware loaded already or no firmware available */
4281         if (tp->rtl_fw || !tp->fw_name)
4282                 return;
4283
4284         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4285         if (!rtl_fw)
4286                 goto err_warn;
4287
4288         rtl_fw->phy_write = rtl_writephy;
4289         rtl_fw->phy_read = rtl_readphy;
4290         rtl_fw->mac_mcu_write = mac_mcu_write;
4291         rtl_fw->mac_mcu_read = mac_mcu_read;
4292
4293         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4294         if (rc < 0)
4295                 goto err_free;
4296
4297         rc = rtl_check_firmware(tp, rtl_fw);
4298         if (rc < 0)
4299                 goto err_release_firmware;
4300
4301         tp->rtl_fw = rtl_fw;
4302
4303         return;
4304
4305 err_release_firmware:
4306         release_firmware(rtl_fw->fw);
4307 err_free:
4308         kfree(rtl_fw);
4309 err_warn:
4310         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4311                    tp->fw_name, rc);
4312 }
4313
4314 static void rtl_rx_close(struct rtl8169_private *tp)
4315 {
4316         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4317 }
4318
4319 DECLARE_RTL_COND(rtl_npq_cond)
4320 {
4321         return RTL_R8(tp, TxPoll) & NPQ;
4322 }
4323
4324 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4325 {
4326         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4327 }
4328
4329 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4330 {
4331         /* Disable interrupts */
4332         rtl8169_irq_mask_and_ack(tp);
4333
4334         rtl_rx_close(tp);
4335
4336         switch (tp->mac_version) {
4337         case RTL_GIGA_MAC_VER_27:
4338         case RTL_GIGA_MAC_VER_28:
4339         case RTL_GIGA_MAC_VER_31:
4340                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4341                 break;
4342         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4343         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4344                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4345                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4346                 break;
4347         default:
4348                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4349                 udelay(100);
4350                 break;
4351         }
4352
4353         rtl_hw_reset(tp);
4354 }
4355
4356 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4357 {
4358         u32 val = TX_DMA_BURST << TxDMAShift |
4359                   InterFrameGap << TxInterFrameGapShift;
4360
4361         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4362             tp->mac_version != RTL_GIGA_MAC_VER_39)
4363                 val |= TXCFG_AUTO_FIFO;
4364
4365         RTL_W32(tp, TxConfig, val);
4366 }
4367
4368 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4369 {
4370         /* Low hurts. Let's disable the filtering. */
4371         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4372 }
4373
4374 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4375 {
4376         /*
4377          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4378          * register to be written before TxDescAddrLow to work.
4379          * Switching from MMIO to I/O access fixes the issue as well.
4380          */
4381         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4382         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4383         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4384         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4385 }
4386
4387 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4388 {
4389         u32 val;
4390
4391         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4392                 val = 0x000fff00;
4393         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4394                 val = 0x00ffff00;
4395         else
4396                 return;
4397
4398         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4399                 val |= 0xff;
4400
4401         RTL_W32(tp, 0x7c, val);
4402 }
4403
4404 static void rtl_set_rx_mode(struct net_device *dev)
4405 {
4406         struct rtl8169_private *tp = netdev_priv(dev);
4407         u32 mc_filter[2];       /* Multicast hash filter */
4408         int rx_mode;
4409         u32 tmp = 0;
4410
4411         if (dev->flags & IFF_PROMISC) {
4412                 /* Unconditionally log net taps. */
4413                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4414                 rx_mode =
4415                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4416                     AcceptAllPhys;
4417                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4418         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4419                    (dev->flags & IFF_ALLMULTI)) {
4420                 /* Too many to filter perfectly -- accept all multicasts. */
4421                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4422                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4423         } else {
4424                 struct netdev_hw_addr *ha;
4425
4426                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4427                 mc_filter[1] = mc_filter[0] = 0;
4428                 netdev_for_each_mc_addr(ha, dev) {
4429                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4430                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4431                         rx_mode |= AcceptMulticast;
4432                 }
4433         }
4434
4435         if (dev->features & NETIF_F_RXALL)
4436                 rx_mode |= (AcceptErr | AcceptRunt);
4437
4438         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4439
4440         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4441                 u32 data = mc_filter[0];
4442
4443                 mc_filter[0] = swab32(mc_filter[1]);
4444                 mc_filter[1] = swab32(data);
4445         }
4446
4447         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4448                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4449
4450         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4451         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4452
4453         RTL_W32(tp, RxConfig, tmp);
4454 }
4455
4456 static void rtl_hw_start(struct  rtl8169_private *tp)
4457 {
4458         rtl_unlock_config_regs(tp);
4459
4460         tp->hw_start(tp);
4461
4462         rtl_set_rx_max_size(tp);
4463         rtl_set_rx_tx_desc_registers(tp);
4464         rtl_lock_config_regs(tp);
4465
4466         /* disable interrupt coalescing */
4467         RTL_W16(tp, IntrMitigate, 0x0000);
4468         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4469         RTL_R8(tp, IntrMask);
4470         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4471         rtl_init_rxcfg(tp);
4472         rtl_set_tx_config_registers(tp);
4473
4474         rtl_set_rx_mode(tp->dev);
4475         /* no early-rx interrupts */
4476         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4477         rtl_irq_enable(tp);
4478 }
4479
4480 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4481 {
4482         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4483                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4484
4485         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4486
4487         tp->cp_cmd |= PCIMulRW;
4488
4489         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4490             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4491                 netif_dbg(tp, drv, tp->dev,
4492                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4493                 tp->cp_cmd |= (1 << 14);
4494         }
4495
4496         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4497
4498         rtl8169_set_magic_reg(tp, tp->mac_version);
4499
4500         RTL_W32(tp, RxMissed, 0);
4501 }
4502
4503 DECLARE_RTL_COND(rtl_csiar_cond)
4504 {
4505         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4506 }
4507
4508 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4509 {
4510         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4511
4512         RTL_W32(tp, CSIDR, value);
4513         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4514                 CSIAR_BYTE_ENABLE | func << 16);
4515
4516         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4517 }
4518
4519 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4520 {
4521         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4522
4523         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4524                 CSIAR_BYTE_ENABLE);
4525
4526         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4527                 RTL_R32(tp, CSIDR) : ~0;
4528 }
4529
4530 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4531 {
4532         struct pci_dev *pdev = tp->pci_dev;
4533         u32 csi;
4534
4535         /* According to Realtek the value at config space address 0x070f
4536          * controls the L0s/L1 entrance latency. We try standard ECAM access
4537          * first and if it fails fall back to CSI.
4538          */
4539         if (pdev->cfg_size > 0x070f &&
4540             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4541                 return;
4542
4543         netdev_notice_once(tp->dev,
4544                 "No native access to PCI extended config space, falling back to CSI\n");
4545         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4546         rtl_csi_write(tp, 0x070c, csi | val << 24);
4547 }
4548
4549 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4550 {
4551         rtl_csi_access_enable(tp, 0x27);
4552 }
4553
4554 struct ephy_info {
4555         unsigned int offset;
4556         u16 mask;
4557         u16 bits;
4558 };
4559
4560 static void __rtl_ephy_init(struct rtl8169_private *tp,
4561                             const struct ephy_info *e, int len)
4562 {
4563         u16 w;
4564
4565         while (len-- > 0) {
4566                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4567                 rtl_ephy_write(tp, e->offset, w);
4568                 e++;
4569         }
4570 }
4571
4572 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4573
4574 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4575 {
4576         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4577                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4578 }
4579
4580 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4581 {
4582         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4583                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4584 }
4585
4586 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4587 {
4588         /* work around an issue when PCI reset occurs during L2/L3 state */
4589         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4590 }
4591
4592 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4593 {
4594         if (enable) {
4595                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4596                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4597         } else {
4598                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4599                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4600         }
4601
4602         udelay(10);
4603 }
4604
4605 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4606                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4607 {
4608         /* Usage of dynamic vs. static FIFO is controlled by bit
4609          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4610          */
4611         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4612         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4613 }
4614
4615 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4616                                           u8 low, u8 high)
4617 {
4618         /* FIFO thresholds for pause flow control */
4619         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4620         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4621 }
4622
4623 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4624 {
4625         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4626
4627         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4628         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4629
4630         if (tp->dev->mtu <= ETH_DATA_LEN) {
4631                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4632                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4633         }
4634 }
4635
4636 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4637 {
4638         rtl_hw_start_8168bb(tp);
4639
4640         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4641
4642         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4643 }
4644
4645 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4646 {
4647         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4648
4649         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4650
4651         if (tp->dev->mtu <= ETH_DATA_LEN)
4652                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4653
4654         rtl_disable_clock_request(tp);
4655
4656         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4657         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4658 }
4659
4660 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4661 {
4662         static const struct ephy_info e_info_8168cp[] = {
4663                 { 0x01, 0,      0x0001 },
4664                 { 0x02, 0x0800, 0x1000 },
4665                 { 0x03, 0,      0x0042 },
4666                 { 0x06, 0x0080, 0x0000 },
4667                 { 0x07, 0,      0x2000 }
4668         };
4669
4670         rtl_set_def_aspm_entry_latency(tp);
4671
4672         rtl_ephy_init(tp, e_info_8168cp);
4673
4674         __rtl_hw_start_8168cp(tp);
4675 }
4676
4677 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4678 {
4679         rtl_set_def_aspm_entry_latency(tp);
4680
4681         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4682
4683         if (tp->dev->mtu <= ETH_DATA_LEN)
4684                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4685
4686         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4687         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4688 }
4689
4690 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4691 {
4692         rtl_set_def_aspm_entry_latency(tp);
4693
4694         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4695
4696         /* Magic. */
4697         RTL_W8(tp, DBG_REG, 0x20);
4698
4699         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4700
4701         if (tp->dev->mtu <= ETH_DATA_LEN)
4702                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4703
4704         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4705         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4706 }
4707
4708 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4709 {
4710         static const struct ephy_info e_info_8168c_1[] = {
4711                 { 0x02, 0x0800, 0x1000 },
4712                 { 0x03, 0,      0x0002 },
4713                 { 0x06, 0x0080, 0x0000 }
4714         };
4715
4716         rtl_set_def_aspm_entry_latency(tp);
4717
4718         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4719
4720         rtl_ephy_init(tp, e_info_8168c_1);
4721
4722         __rtl_hw_start_8168cp(tp);
4723 }
4724
4725 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4726 {
4727         static const struct ephy_info e_info_8168c_2[] = {
4728                 { 0x01, 0,      0x0001 },
4729                 { 0x03, 0x0400, 0x0220 }
4730         };
4731
4732         rtl_set_def_aspm_entry_latency(tp);
4733
4734         rtl_ephy_init(tp, e_info_8168c_2);
4735
4736         __rtl_hw_start_8168cp(tp);
4737 }
4738
4739 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4740 {
4741         rtl_hw_start_8168c_2(tp);
4742 }
4743
4744 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4745 {
4746         rtl_set_def_aspm_entry_latency(tp);
4747
4748         __rtl_hw_start_8168cp(tp);
4749 }
4750
4751 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4752 {
4753         rtl_set_def_aspm_entry_latency(tp);
4754
4755         rtl_disable_clock_request(tp);
4756
4757         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4758
4759         if (tp->dev->mtu <= ETH_DATA_LEN)
4760                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4761
4762         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4763         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4764 }
4765
4766 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4767 {
4768         rtl_set_def_aspm_entry_latency(tp);
4769
4770         if (tp->dev->mtu <= ETH_DATA_LEN)
4771                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4772
4773         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4774
4775         rtl_disable_clock_request(tp);
4776 }
4777
4778 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4779 {
4780         static const struct ephy_info e_info_8168d_4[] = {
4781                 { 0x0b, 0x0000, 0x0048 },
4782                 { 0x19, 0x0020, 0x0050 },
4783                 { 0x0c, 0x0100, 0x0020 }
4784         };
4785
4786         rtl_set_def_aspm_entry_latency(tp);
4787
4788         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4789
4790         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4791
4792         rtl_ephy_init(tp, e_info_8168d_4);
4793
4794         rtl_enable_clock_request(tp);
4795 }
4796
4797 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4798 {
4799         static const struct ephy_info e_info_8168e_1[] = {
4800                 { 0x00, 0x0200, 0x0100 },
4801                 { 0x00, 0x0000, 0x0004 },
4802                 { 0x06, 0x0002, 0x0001 },
4803                 { 0x06, 0x0000, 0x0030 },
4804                 { 0x07, 0x0000, 0x2000 },
4805                 { 0x00, 0x0000, 0x0020 },
4806                 { 0x03, 0x5800, 0x2000 },
4807                 { 0x03, 0x0000, 0x0001 },
4808                 { 0x01, 0x0800, 0x1000 },
4809                 { 0x07, 0x0000, 0x4000 },
4810                 { 0x1e, 0x0000, 0x2000 },
4811                 { 0x19, 0xffff, 0xfe6c },
4812                 { 0x0a, 0x0000, 0x0040 }
4813         };
4814
4815         rtl_set_def_aspm_entry_latency(tp);
4816
4817         rtl_ephy_init(tp, e_info_8168e_1);
4818
4819         if (tp->dev->mtu <= ETH_DATA_LEN)
4820                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4821
4822         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4823
4824         rtl_disable_clock_request(tp);
4825
4826         /* Reset tx FIFO pointer */
4827         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4828         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4829
4830         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4831 }
4832
4833 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4834 {
4835         static const struct ephy_info e_info_8168e_2[] = {
4836                 { 0x09, 0x0000, 0x0080 },
4837                 { 0x19, 0x0000, 0x0224 }
4838         };
4839
4840         rtl_set_def_aspm_entry_latency(tp);
4841
4842         rtl_ephy_init(tp, e_info_8168e_2);
4843
4844         if (tp->dev->mtu <= ETH_DATA_LEN)
4845                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4846
4847         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4848         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4849         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4850         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4851         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4852         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4853         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4854
4855         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4856
4857         rtl_disable_clock_request(tp);
4858
4859         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4860
4861         rtl8168_config_eee_mac(tp);
4862
4863         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4864         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4865         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4866
4867         rtl_hw_aspm_clkreq_enable(tp, true);
4868 }
4869
4870 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4871 {
4872         rtl_set_def_aspm_entry_latency(tp);
4873
4874         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4875
4876         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4877         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4878         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4879         rtl_reset_packet_filter(tp);
4880         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4881         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4882         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4883         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4884
4885         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4886
4887         rtl_disable_clock_request(tp);
4888
4889         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4890         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4891         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4892         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4893
4894         rtl8168_config_eee_mac(tp);
4895 }
4896
4897 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4898 {
4899         static const struct ephy_info e_info_8168f_1[] = {
4900                 { 0x06, 0x00c0, 0x0020 },
4901                 { 0x08, 0x0001, 0x0002 },
4902                 { 0x09, 0x0000, 0x0080 },
4903                 { 0x19, 0x0000, 0x0224 }
4904         };
4905
4906         rtl_hw_start_8168f(tp);
4907
4908         rtl_ephy_init(tp, e_info_8168f_1);
4909
4910         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4911 }
4912
4913 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4914 {
4915         static const struct ephy_info e_info_8168f_1[] = {
4916                 { 0x06, 0x00c0, 0x0020 },
4917                 { 0x0f, 0xffff, 0x5200 },
4918                 { 0x1e, 0x0000, 0x4000 },
4919                 { 0x19, 0x0000, 0x0224 }
4920         };
4921
4922         rtl_hw_start_8168f(tp);
4923         rtl_pcie_state_l2l3_disable(tp);
4924
4925         rtl_ephy_init(tp, e_info_8168f_1);
4926
4927         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4928 }
4929
4930 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4931 {
4932         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4933         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4934
4935         rtl_set_def_aspm_entry_latency(tp);
4936
4937         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4938
4939         rtl_reset_packet_filter(tp);
4940         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4941
4942         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4943         RTL_W8(tp, MaxTxPacketSize, EarlySize);
4944
4945         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4946         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4947
4948         rtl8168_config_eee_mac(tp);
4949
4950         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4951         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4952
4953         rtl_pcie_state_l2l3_disable(tp);
4954 }
4955
4956 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4957 {
4958         static const struct ephy_info e_info_8168g_1[] = {
4959                 { 0x00, 0x0000, 0x0008 },
4960                 { 0x0c, 0x37d0, 0x0820 },
4961                 { 0x1e, 0x0000, 0x0001 },
4962                 { 0x19, 0x8000, 0x0000 }
4963         };
4964
4965         rtl_hw_start_8168g(tp);
4966
4967         /* disable aspm and clock request before access ephy */
4968         rtl_hw_aspm_clkreq_enable(tp, false);
4969         rtl_ephy_init(tp, e_info_8168g_1);
4970         rtl_hw_aspm_clkreq_enable(tp, true);
4971 }
4972
4973 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4974 {
4975         static const struct ephy_info e_info_8168g_2[] = {
4976                 { 0x00, 0x0000, 0x0008 },
4977                 { 0x0c, 0x3df0, 0x0200 },
4978                 { 0x19, 0xffff, 0xfc00 },
4979                 { 0x1e, 0xffff, 0x20eb }
4980         };
4981
4982         rtl_hw_start_8168g(tp);
4983
4984         /* disable aspm and clock request before access ephy */
4985         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4986         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4987         rtl_ephy_init(tp, e_info_8168g_2);
4988 }
4989
4990 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4991 {
4992         static const struct ephy_info e_info_8411_2[] = {
4993                 { 0x00, 0x0000, 0x0008 },
4994                 { 0x0c, 0x3df0, 0x0200 },
4995                 { 0x0f, 0xffff, 0x5200 },
4996                 { 0x19, 0x0020, 0x0000 },
4997                 { 0x1e, 0x0000, 0x2000 }
4998         };
4999
5000         rtl_hw_start_8168g(tp);
5001
5002         /* disable aspm and clock request before access ephy */
5003         rtl_hw_aspm_clkreq_enable(tp, false);
5004         rtl_ephy_init(tp, e_info_8411_2);
5005         rtl_hw_aspm_clkreq_enable(tp, true);
5006 }
5007
5008 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5009 {
5010         int rg_saw_cnt;
5011         u32 data;
5012         static const struct ephy_info e_info_8168h_1[] = {
5013                 { 0x1e, 0x0800, 0x0001 },
5014                 { 0x1d, 0x0000, 0x0800 },
5015                 { 0x05, 0xffff, 0x2089 },
5016                 { 0x06, 0xffff, 0x5881 },
5017                 { 0x04, 0xffff, 0x154a },
5018                 { 0x01, 0xffff, 0x068b }
5019         };
5020
5021         /* disable aspm and clock request before access ephy */
5022         rtl_hw_aspm_clkreq_enable(tp, false);
5023         rtl_ephy_init(tp, e_info_8168h_1);
5024
5025         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5026         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5027
5028         rtl_set_def_aspm_entry_latency(tp);
5029
5030         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5031
5032         rtl_reset_packet_filter(tp);
5033
5034         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5035
5036         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5037
5038         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5039
5040         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5041         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5042
5043         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5044         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5045
5046         rtl8168_config_eee_mac(tp);
5047
5048         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5049         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5050
5051         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5052
5053         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5054
5055         rtl_pcie_state_l2l3_disable(tp);
5056
5057         rtl_writephy(tp, 0x1f, 0x0c42);
5058         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5059         rtl_writephy(tp, 0x1f, 0x0000);
5060         if (rg_saw_cnt > 0) {
5061                 u16 sw_cnt_1ms_ini;
5062
5063                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5064                 sw_cnt_1ms_ini &= 0x0fff;
5065                 data = r8168_mac_ocp_read(tp, 0xd412);
5066                 data &= ~0x0fff;
5067                 data |= sw_cnt_1ms_ini;
5068                 r8168_mac_ocp_write(tp, 0xd412, data);
5069         }
5070
5071         data = r8168_mac_ocp_read(tp, 0xe056);
5072         data &= ~0xf0;
5073         data |= 0x70;
5074         r8168_mac_ocp_write(tp, 0xe056, data);
5075
5076         data = r8168_mac_ocp_read(tp, 0xe052);
5077         data &= ~0x6000;
5078         data |= 0x8008;
5079         r8168_mac_ocp_write(tp, 0xe052, data);
5080
5081         data = r8168_mac_ocp_read(tp, 0xe0d6);
5082         data &= ~0x01ff;
5083         data |= 0x017f;
5084         r8168_mac_ocp_write(tp, 0xe0d6, data);
5085
5086         data = r8168_mac_ocp_read(tp, 0xd420);
5087         data &= ~0x0fff;
5088         data |= 0x047f;
5089         r8168_mac_ocp_write(tp, 0xd420, data);
5090
5091         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5092         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5093         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5094         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5095
5096         rtl_hw_aspm_clkreq_enable(tp, true);
5097 }
5098
5099 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5100 {
5101         rtl8168ep_stop_cmac(tp);
5102
5103         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5104         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5105
5106         rtl_set_def_aspm_entry_latency(tp);
5107
5108         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5109
5110         rtl_reset_packet_filter(tp);
5111
5112         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5113
5114         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5115
5116         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5117         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5118
5119         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5120         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5121
5122         rtl8168_config_eee_mac(tp);
5123
5124         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5125
5126         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5127
5128         rtl_pcie_state_l2l3_disable(tp);
5129 }
5130
5131 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5132 {
5133         static const struct ephy_info e_info_8168ep_1[] = {
5134                 { 0x00, 0xffff, 0x10ab },
5135                 { 0x06, 0xffff, 0xf030 },
5136                 { 0x08, 0xffff, 0x2006 },
5137                 { 0x0d, 0xffff, 0x1666 },
5138                 { 0x0c, 0x3ff0, 0x0000 }
5139         };
5140
5141         /* disable aspm and clock request before access ephy */
5142         rtl_hw_aspm_clkreq_enable(tp, false);
5143         rtl_ephy_init(tp, e_info_8168ep_1);
5144
5145         rtl_hw_start_8168ep(tp);
5146
5147         rtl_hw_aspm_clkreq_enable(tp, true);
5148 }
5149
5150 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5151 {
5152         static const struct ephy_info e_info_8168ep_2[] = {
5153                 { 0x00, 0xffff, 0x10a3 },
5154                 { 0x19, 0xffff, 0xfc00 },
5155                 { 0x1e, 0xffff, 0x20ea }
5156         };
5157
5158         /* disable aspm and clock request before access ephy */
5159         rtl_hw_aspm_clkreq_enable(tp, false);
5160         rtl_ephy_init(tp, e_info_8168ep_2);
5161
5162         rtl_hw_start_8168ep(tp);
5163
5164         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5165         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5166
5167         rtl_hw_aspm_clkreq_enable(tp, true);
5168 }
5169
5170 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5171 {
5172         u32 data;
5173         static const struct ephy_info e_info_8168ep_3[] = {
5174                 { 0x00, 0xffff, 0x10a3 },
5175                 { 0x19, 0xffff, 0x7c00 },
5176                 { 0x1e, 0xffff, 0x20eb },
5177                 { 0x0d, 0xffff, 0x1666 }
5178         };
5179
5180         /* disable aspm and clock request before access ephy */
5181         rtl_hw_aspm_clkreq_enable(tp, false);
5182         rtl_ephy_init(tp, e_info_8168ep_3);
5183
5184         rtl_hw_start_8168ep(tp);
5185
5186         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5187         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5188
5189         data = r8168_mac_ocp_read(tp, 0xd3e2);
5190         data &= 0xf000;
5191         data |= 0x0271;
5192         r8168_mac_ocp_write(tp, 0xd3e2, data);
5193
5194         data = r8168_mac_ocp_read(tp, 0xd3e4);
5195         data &= 0xff00;
5196         r8168_mac_ocp_write(tp, 0xd3e4, data);
5197
5198         data = r8168_mac_ocp_read(tp, 0xe860);
5199         data |= 0x0080;
5200         r8168_mac_ocp_write(tp, 0xe860, data);
5201
5202         rtl_hw_aspm_clkreq_enable(tp, true);
5203 }
5204
5205 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5206 {
5207         static const struct ephy_info e_info_8102e_1[] = {
5208                 { 0x01, 0, 0x6e65 },
5209                 { 0x02, 0, 0x091f },
5210                 { 0x03, 0, 0xc2f9 },
5211                 { 0x06, 0, 0xafb5 },
5212                 { 0x07, 0, 0x0e00 },
5213                 { 0x19, 0, 0xec80 },
5214                 { 0x01, 0, 0x2e65 },
5215                 { 0x01, 0, 0x6e65 }
5216         };
5217         u8 cfg1;
5218
5219         rtl_set_def_aspm_entry_latency(tp);
5220
5221         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5222
5223         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5224
5225         RTL_W8(tp, Config1,
5226                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5227         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5228
5229         cfg1 = RTL_R8(tp, Config1);
5230         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5231                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5232
5233         rtl_ephy_init(tp, e_info_8102e_1);
5234 }
5235
5236 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5237 {
5238         rtl_set_def_aspm_entry_latency(tp);
5239
5240         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5241
5242         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5243         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5244 }
5245
5246 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5247 {
5248         rtl_hw_start_8102e_2(tp);
5249
5250         rtl_ephy_write(tp, 0x03, 0xc2f9);
5251 }
5252
5253 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5254 {
5255         static const struct ephy_info e_info_8105e_1[] = {
5256                 { 0x07, 0, 0x4000 },
5257                 { 0x19, 0, 0x0200 },
5258                 { 0x19, 0, 0x0020 },
5259                 { 0x1e, 0, 0x2000 },
5260                 { 0x03, 0, 0x0001 },
5261                 { 0x19, 0, 0x0100 },
5262                 { 0x19, 0, 0x0004 },
5263                 { 0x0a, 0, 0x0020 }
5264         };
5265
5266         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5267         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5268
5269         /* Disable Early Tally Counter */
5270         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5271
5272         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5273         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5274
5275         rtl_ephy_init(tp, e_info_8105e_1);
5276
5277         rtl_pcie_state_l2l3_disable(tp);
5278 }
5279
5280 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5281 {
5282         rtl_hw_start_8105e_1(tp);
5283         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5284 }
5285
5286 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5287 {
5288         static const struct ephy_info e_info_8402[] = {
5289                 { 0x19, 0xffff, 0xff64 },
5290                 { 0x1e, 0, 0x4000 }
5291         };
5292
5293         rtl_set_def_aspm_entry_latency(tp);
5294
5295         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5296         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5297
5298         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5299
5300         rtl_ephy_init(tp, e_info_8402);
5301
5302         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5303
5304         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5305         rtl_reset_packet_filter(tp);
5306         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5307         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5308         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5309
5310         rtl_pcie_state_l2l3_disable(tp);
5311 }
5312
5313 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5314 {
5315         rtl_hw_aspm_clkreq_enable(tp, false);
5316
5317         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5318         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5319
5320         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5321         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5322         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5323
5324         rtl_pcie_state_l2l3_disable(tp);
5325         rtl_hw_aspm_clkreq_enable(tp, true);
5326 }
5327
5328 static void rtl_hw_config(struct rtl8169_private *tp)
5329 {
5330         static const rtl_generic_fct hw_configs[] = {
5331                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5332                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5333                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5334                 [RTL_GIGA_MAC_VER_10] = NULL,
5335                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5336                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5337                 [RTL_GIGA_MAC_VER_13] = NULL,
5338                 [RTL_GIGA_MAC_VER_14] = NULL,
5339                 [RTL_GIGA_MAC_VER_15] = NULL,
5340                 [RTL_GIGA_MAC_VER_16] = NULL,
5341                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5342                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5343                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5344                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5345                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5346                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5347                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5348                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5349                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5350                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5351                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5352                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5353                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5354                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5355                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5356                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5357                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5358                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5359                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5360                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5361                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5362                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5363                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5364                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5365                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5366                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5367                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5368                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5369                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5370                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5371                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5372                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5373                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5374                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5375                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5376         };
5377
5378         if (hw_configs[tp->mac_version])
5379                 hw_configs[tp->mac_version](tp);
5380 }
5381
5382 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5383 {
5384         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5385
5386         /* Workaround for RxFIFO overflow. */
5387         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5388                 tp->irq_mask |= RxFIFOOver;
5389                 tp->irq_mask &= ~RxOverflow;
5390         }
5391
5392         rtl_hw_config(tp);
5393 }
5394
5395 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5396 {
5397         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5398                 tp->irq_mask &= ~RxFIFOOver;
5399
5400         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5401             tp->mac_version == RTL_GIGA_MAC_VER_16)
5402                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5403                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5404
5405         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5406
5407         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5408         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5409
5410         rtl_hw_config(tp);
5411 }
5412
5413 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5414 {
5415         struct rtl8169_private *tp = netdev_priv(dev);
5416
5417         if (new_mtu > ETH_DATA_LEN)
5418                 rtl_hw_jumbo_enable(tp);
5419         else
5420                 rtl_hw_jumbo_disable(tp);
5421
5422         dev->mtu = new_mtu;
5423         netdev_update_features(dev);
5424
5425         return 0;
5426 }
5427
5428 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5429 {
5430         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5431         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5432 }
5433
5434 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5435                                      void **data_buff, struct RxDesc *desc)
5436 {
5437         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5438                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5439
5440         kfree(*data_buff);
5441         *data_buff = NULL;
5442         rtl8169_make_unusable_by_asic(desc);
5443 }
5444
5445 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5446 {
5447         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5448
5449         /* Force memory writes to complete before releasing descriptor */
5450         dma_wmb();
5451
5452         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5453 }
5454
5455 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5456                                              struct RxDesc *desc)
5457 {
5458         void *data;
5459         dma_addr_t mapping;
5460         struct device *d = tp_to_dev(tp);
5461         int node = dev_to_node(d);
5462
5463         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5464         if (!data)
5465                 return NULL;
5466
5467         /* Memory should be properly aligned, but better check. */
5468         if (!IS_ALIGNED((unsigned long)data, 8)) {
5469                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5470                 goto err_out;
5471         }
5472
5473         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5474         if (unlikely(dma_mapping_error(d, mapping))) {
5475                 if (net_ratelimit())
5476                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5477                 goto err_out;
5478         }
5479
5480         desc->addr = cpu_to_le64(mapping);
5481         rtl8169_mark_to_asic(desc);
5482         return data;
5483
5484 err_out:
5485         kfree(data);
5486         return NULL;
5487 }
5488
5489 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5490 {
5491         unsigned int i;
5492
5493         for (i = 0; i < NUM_RX_DESC; i++) {
5494                 if (tp->Rx_databuff[i]) {
5495                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5496                                             tp->RxDescArray + i);
5497                 }
5498         }
5499 }
5500
5501 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5502 {
5503         desc->opts1 |= cpu_to_le32(RingEnd);
5504 }
5505
5506 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5507 {
5508         unsigned int i;
5509
5510         for (i = 0; i < NUM_RX_DESC; i++) {
5511                 void *data;
5512
5513                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5514                 if (!data) {
5515                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5516                         goto err_out;
5517                 }
5518                 tp->Rx_databuff[i] = data;
5519         }
5520
5521         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5522         return 0;
5523
5524 err_out:
5525         rtl8169_rx_clear(tp);
5526         return -ENOMEM;
5527 }
5528
5529 static int rtl8169_init_ring(struct rtl8169_private *tp)
5530 {
5531         rtl8169_init_ring_indexes(tp);
5532
5533         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5534         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5535
5536         return rtl8169_rx_fill(tp);
5537 }
5538
5539 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5540                                  struct TxDesc *desc)
5541 {
5542         unsigned int len = tx_skb->len;
5543
5544         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5545
5546         desc->opts1 = 0x00;
5547         desc->opts2 = 0x00;
5548         desc->addr = 0x00;
5549         tx_skb->len = 0;
5550 }
5551
5552 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5553                                    unsigned int n)
5554 {
5555         unsigned int i;
5556
5557         for (i = 0; i < n; i++) {
5558                 unsigned int entry = (start + i) % NUM_TX_DESC;
5559                 struct ring_info *tx_skb = tp->tx_skb + entry;
5560                 unsigned int len = tx_skb->len;
5561
5562                 if (len) {
5563                         struct sk_buff *skb = tx_skb->skb;
5564
5565                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5566                                              tp->TxDescArray + entry);
5567                         if (skb) {
5568                                 dev_consume_skb_any(skb);
5569                                 tx_skb->skb = NULL;
5570                         }
5571                 }
5572         }
5573 }
5574
5575 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5576 {
5577         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5578         tp->cur_tx = tp->dirty_tx = 0;
5579         netdev_reset_queue(tp->dev);
5580 }
5581
5582 static void rtl_reset_work(struct rtl8169_private *tp)
5583 {
5584         struct net_device *dev = tp->dev;
5585         int i;
5586
5587         napi_disable(&tp->napi);
5588         netif_stop_queue(dev);
5589         synchronize_rcu();
5590
5591         rtl8169_hw_reset(tp);
5592
5593         for (i = 0; i < NUM_RX_DESC; i++)
5594                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5595
5596         rtl8169_tx_clear(tp);
5597         rtl8169_init_ring_indexes(tp);
5598
5599         napi_enable(&tp->napi);
5600         rtl_hw_start(tp);
5601         netif_wake_queue(dev);
5602 }
5603
5604 static void rtl8169_tx_timeout(struct net_device *dev)
5605 {
5606         struct rtl8169_private *tp = netdev_priv(dev);
5607
5608         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5609 }
5610
5611 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5612 {
5613         u32 status = opts0 | len;
5614
5615         if (entry == NUM_TX_DESC - 1)
5616                 status |= RingEnd;
5617
5618         return cpu_to_le32(status);
5619 }
5620
5621 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5622                               u32 *opts)
5623 {
5624         struct skb_shared_info *info = skb_shinfo(skb);
5625         unsigned int cur_frag, entry;
5626         struct TxDesc *uninitialized_var(txd);
5627         struct device *d = tp_to_dev(tp);
5628
5629         entry = tp->cur_tx;
5630         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5631                 const skb_frag_t *frag = info->frags + cur_frag;
5632                 dma_addr_t mapping;
5633                 u32 len;
5634                 void *addr;
5635
5636                 entry = (entry + 1) % NUM_TX_DESC;
5637
5638                 txd = tp->TxDescArray + entry;
5639                 len = skb_frag_size(frag);
5640                 addr = skb_frag_address(frag);
5641                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5642                 if (unlikely(dma_mapping_error(d, mapping))) {
5643                         if (net_ratelimit())
5644                                 netif_err(tp, drv, tp->dev,
5645                                           "Failed to map TX fragments DMA!\n");
5646                         goto err_out;
5647                 }
5648
5649                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5650                 txd->opts2 = cpu_to_le32(opts[1]);
5651                 txd->addr = cpu_to_le64(mapping);
5652
5653                 tp->tx_skb[entry].len = len;
5654         }
5655
5656         if (cur_frag) {
5657                 tp->tx_skb[entry].skb = skb;
5658                 txd->opts1 |= cpu_to_le32(LastFrag);
5659         }
5660
5661         return cur_frag;
5662
5663 err_out:
5664         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5665         return -EIO;
5666 }
5667
5668 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5669 {
5670         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5671 }
5672
5673 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5674                                       struct net_device *dev);
5675 /* r8169_csum_workaround()
5676  * The hw limites the value the transport offset. When the offset is out of the
5677  * range, calculate the checksum by sw.
5678  */
5679 static void r8169_csum_workaround(struct rtl8169_private *tp,
5680                                   struct sk_buff *skb)
5681 {
5682         if (skb_is_gso(skb)) {
5683                 netdev_features_t features = tp->dev->features;
5684                 struct sk_buff *segs, *nskb;
5685
5686                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5687                 segs = skb_gso_segment(skb, features);
5688                 if (IS_ERR(segs) || !segs)
5689                         goto drop;
5690
5691                 do {
5692                         nskb = segs;
5693                         segs = segs->next;
5694                         nskb->next = NULL;
5695                         rtl8169_start_xmit(nskb, tp->dev);
5696                 } while (segs);
5697
5698                 dev_consume_skb_any(skb);
5699         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5700                 if (skb_checksum_help(skb) < 0)
5701                         goto drop;
5702
5703                 rtl8169_start_xmit(skb, tp->dev);
5704         } else {
5705 drop:
5706                 tp->dev->stats.tx_dropped++;
5707                 dev_kfree_skb_any(skb);
5708         }
5709 }
5710
5711 /* msdn_giant_send_check()
5712  * According to the document of microsoft, the TCP Pseudo Header excludes the
5713  * packet length for IPv6 TCP large packets.
5714  */
5715 static int msdn_giant_send_check(struct sk_buff *skb)
5716 {
5717         const struct ipv6hdr *ipv6h;
5718         struct tcphdr *th;
5719         int ret;
5720
5721         ret = skb_cow_head(skb, 0);
5722         if (ret)
5723                 return ret;
5724
5725         ipv6h = ipv6_hdr(skb);
5726         th = tcp_hdr(skb);
5727
5728         th->check = 0;
5729         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5730
5731         return ret;
5732 }
5733
5734 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5735 {
5736         u32 mss = skb_shinfo(skb)->gso_size;
5737
5738         if (mss) {
5739                 opts[0] |= TD_LSO;
5740                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5741         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5742                 const struct iphdr *ip = ip_hdr(skb);
5743
5744                 if (ip->protocol == IPPROTO_TCP)
5745                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5746                 else if (ip->protocol == IPPROTO_UDP)
5747                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5748                 else
5749                         WARN_ON_ONCE(1);
5750         }
5751 }
5752
5753 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5754                                 struct sk_buff *skb, u32 *opts)
5755 {
5756         u32 transport_offset = (u32)skb_transport_offset(skb);
5757         u32 mss = skb_shinfo(skb)->gso_size;
5758
5759         if (mss) {
5760                 if (transport_offset > GTTCPHO_MAX) {
5761                         netif_warn(tp, tx_err, tp->dev,
5762                                    "Invalid transport offset 0x%x for TSO\n",
5763                                    transport_offset);
5764                         return false;
5765                 }
5766
5767                 switch (vlan_get_protocol(skb)) {
5768                 case htons(ETH_P_IP):
5769                         opts[0] |= TD1_GTSENV4;
5770                         break;
5771
5772                 case htons(ETH_P_IPV6):
5773                         if (msdn_giant_send_check(skb))
5774                                 return false;
5775
5776                         opts[0] |= TD1_GTSENV6;
5777                         break;
5778
5779                 default:
5780                         WARN_ON_ONCE(1);
5781                         break;
5782                 }
5783
5784                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5785                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5786         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5787                 u8 ip_protocol;
5788
5789                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5790                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5791
5792                 if (transport_offset > TCPHO_MAX) {
5793                         netif_warn(tp, tx_err, tp->dev,
5794                                    "Invalid transport offset 0x%x\n",
5795                                    transport_offset);
5796                         return false;
5797                 }
5798
5799                 switch (vlan_get_protocol(skb)) {
5800                 case htons(ETH_P_IP):
5801                         opts[1] |= TD1_IPv4_CS;
5802                         ip_protocol = ip_hdr(skb)->protocol;
5803                         break;
5804
5805                 case htons(ETH_P_IPV6):
5806                         opts[1] |= TD1_IPv6_CS;
5807                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5808                         break;
5809
5810                 default:
5811                         ip_protocol = IPPROTO_RAW;
5812                         break;
5813                 }
5814
5815                 if (ip_protocol == IPPROTO_TCP)
5816                         opts[1] |= TD1_TCP_CS;
5817                 else if (ip_protocol == IPPROTO_UDP)
5818                         opts[1] |= TD1_UDP_CS;
5819                 else
5820                         WARN_ON_ONCE(1);
5821
5822                 opts[1] |= transport_offset << TCPHO_SHIFT;
5823         } else {
5824                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5825                         return !eth_skb_pad(skb);
5826         }
5827
5828         return true;
5829 }
5830
5831 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5832                                unsigned int nr_frags)
5833 {
5834         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5835
5836         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5837         return slots_avail > nr_frags;
5838 }
5839
5840 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5841 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5842 {
5843         switch (tp->mac_version) {
5844         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5845         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5846                 return false;
5847         default:
5848                 return true;
5849         }
5850 }
5851
5852 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5853                                       struct net_device *dev)
5854 {
5855         struct rtl8169_private *tp = netdev_priv(dev);
5856         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5857         struct TxDesc *txd = tp->TxDescArray + entry;
5858         struct device *d = tp_to_dev(tp);
5859         dma_addr_t mapping;
5860         u32 opts[2], len;
5861         int frags;
5862
5863         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5864                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5865                 goto err_stop_0;
5866         }
5867
5868         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5869                 goto err_stop_0;
5870
5871         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
5872         opts[0] = DescOwn;
5873
5874         if (rtl_chip_supports_csum_v2(tp)) {
5875                 if (!rtl8169_tso_csum_v2(tp, skb, opts)) {
5876                         r8169_csum_workaround(tp, skb);
5877                         return NETDEV_TX_OK;
5878                 }
5879         } else {
5880                 rtl8169_tso_csum_v1(skb, opts);
5881         }
5882
5883         len = skb_headlen(skb);
5884         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5885         if (unlikely(dma_mapping_error(d, mapping))) {
5886                 if (net_ratelimit())
5887                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5888                 goto err_dma_0;
5889         }
5890
5891         tp->tx_skb[entry].len = len;
5892         txd->addr = cpu_to_le64(mapping);
5893
5894         frags = rtl8169_xmit_frags(tp, skb, opts);
5895         if (frags < 0)
5896                 goto err_dma_1;
5897         else if (frags)
5898                 opts[0] |= FirstFrag;
5899         else {
5900                 opts[0] |= FirstFrag | LastFrag;
5901                 tp->tx_skb[entry].skb = skb;
5902         }
5903
5904         txd->opts2 = cpu_to_le32(opts[1]);
5905
5906         netdev_sent_queue(dev, skb->len);
5907
5908         skb_tx_timestamp(skb);
5909
5910         /* Force memory writes to complete before releasing descriptor */
5911         dma_wmb();
5912
5913         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5914
5915         /* Force all memory writes to complete before notifying device */
5916         wmb();
5917
5918         tp->cur_tx += frags + 1;
5919
5920         RTL_W8(tp, TxPoll, NPQ);
5921
5922         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5923                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5924                  * not miss a ring update when it notices a stopped queue.
5925                  */
5926                 smp_wmb();
5927                 netif_stop_queue(dev);
5928                 /* Sync with rtl_tx:
5929                  * - publish queue status and cur_tx ring index (write barrier)
5930                  * - refresh dirty_tx ring index (read barrier).
5931                  * May the current thread have a pessimistic view of the ring
5932                  * status and forget to wake up queue, a racing rtl_tx thread
5933                  * can't.
5934                  */
5935                 smp_mb();
5936                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5937                         netif_start_queue(dev);
5938         }
5939
5940         return NETDEV_TX_OK;
5941
5942 err_dma_1:
5943         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5944 err_dma_0:
5945         dev_kfree_skb_any(skb);
5946         dev->stats.tx_dropped++;
5947         return NETDEV_TX_OK;
5948
5949 err_stop_0:
5950         netif_stop_queue(dev);
5951         dev->stats.tx_dropped++;
5952         return NETDEV_TX_BUSY;
5953 }
5954
5955 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5956 {
5957         struct rtl8169_private *tp = netdev_priv(dev);
5958         struct pci_dev *pdev = tp->pci_dev;
5959         u16 pci_status, pci_cmd;
5960
5961         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5962         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5963
5964         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5965                   pci_cmd, pci_status);
5966
5967         /*
5968          * The recovery sequence below admits a very elaborated explanation:
5969          * - it seems to work;
5970          * - I did not see what else could be done;
5971          * - it makes iop3xx happy.
5972          *
5973          * Feel free to adjust to your needs.
5974          */
5975         if (pdev->broken_parity_status)
5976                 pci_cmd &= ~PCI_COMMAND_PARITY;
5977         else
5978                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5979
5980         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5981
5982         pci_write_config_word(pdev, PCI_STATUS,
5983                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5984                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5985                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5986
5987         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5988 }
5989
5990 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5991                    int budget)
5992 {
5993         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5994
5995         dirty_tx = tp->dirty_tx;
5996         smp_rmb();
5997         tx_left = tp->cur_tx - dirty_tx;
5998
5999         while (tx_left > 0) {
6000                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6001                 struct ring_info *tx_skb = tp->tx_skb + entry;
6002                 u32 status;
6003
6004                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6005                 if (status & DescOwn)
6006                         break;
6007
6008                 /* This barrier is needed to keep us from reading
6009                  * any other fields out of the Tx descriptor until
6010                  * we know the status of DescOwn
6011                  */
6012                 dma_rmb();
6013
6014                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6015                                      tp->TxDescArray + entry);
6016                 if (status & LastFrag) {
6017                         pkts_compl++;
6018                         bytes_compl += tx_skb->skb->len;
6019                         napi_consume_skb(tx_skb->skb, budget);
6020                         tx_skb->skb = NULL;
6021                 }
6022                 dirty_tx++;
6023                 tx_left--;
6024         }
6025
6026         if (tp->dirty_tx != dirty_tx) {
6027                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6028
6029                 u64_stats_update_begin(&tp->tx_stats.syncp);
6030                 tp->tx_stats.packets += pkts_compl;
6031                 tp->tx_stats.bytes += bytes_compl;
6032                 u64_stats_update_end(&tp->tx_stats.syncp);
6033
6034                 tp->dirty_tx = dirty_tx;
6035                 /* Sync with rtl8169_start_xmit:
6036                  * - publish dirty_tx ring index (write barrier)
6037                  * - refresh cur_tx ring index and queue status (read barrier)
6038                  * May the current thread miss the stopped queue condition,
6039                  * a racing xmit thread can only have a right view of the
6040                  * ring status.
6041                  */
6042                 smp_mb();
6043                 if (netif_queue_stopped(dev) &&
6044                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6045                         netif_wake_queue(dev);
6046                 }
6047                 /*
6048                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6049                  * too close. Let's kick an extra TxPoll request when a burst
6050                  * of start_xmit activity is detected (if it is not detected,
6051                  * it is slow enough). -- FR
6052                  */
6053                 if (tp->cur_tx != dirty_tx)
6054                         RTL_W8(tp, TxPoll, NPQ);
6055         }
6056 }
6057
6058 static inline int rtl8169_fragmented_frame(u32 status)
6059 {
6060         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6061 }
6062
6063 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6064 {
6065         u32 status = opts1 & RxProtoMask;
6066
6067         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6068             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6069                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6070         else
6071                 skb_checksum_none_assert(skb);
6072 }
6073
6074 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6075                                            struct rtl8169_private *tp,
6076                                            int pkt_size,
6077                                            dma_addr_t addr)
6078 {
6079         struct sk_buff *skb;
6080         struct device *d = tp_to_dev(tp);
6081
6082         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6083         prefetch(data);
6084         skb = napi_alloc_skb(&tp->napi, pkt_size);
6085         if (skb)
6086                 skb_copy_to_linear_data(skb, data, pkt_size);
6087         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6088
6089         return skb;
6090 }
6091
6092 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6093 {
6094         unsigned int cur_rx, rx_left;
6095         unsigned int count;
6096
6097         cur_rx = tp->cur_rx;
6098
6099         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6100                 unsigned int entry = cur_rx % NUM_RX_DESC;
6101                 struct RxDesc *desc = tp->RxDescArray + entry;
6102                 u32 status;
6103
6104                 status = le32_to_cpu(desc->opts1);
6105                 if (status & DescOwn)
6106                         break;
6107
6108                 /* This barrier is needed to keep us from reading
6109                  * any other fields out of the Rx descriptor until
6110                  * we know the status of DescOwn
6111                  */
6112                 dma_rmb();
6113
6114                 if (unlikely(status & RxRES)) {
6115                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6116                                    status);
6117                         dev->stats.rx_errors++;
6118                         if (status & (RxRWT | RxRUNT))
6119                                 dev->stats.rx_length_errors++;
6120                         if (status & RxCRC)
6121                                 dev->stats.rx_crc_errors++;
6122                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
6123                             dev->features & NETIF_F_RXALL) {
6124                                 goto process_pkt;
6125                         }
6126                 } else {
6127                         struct sk_buff *skb;
6128                         dma_addr_t addr;
6129                         int pkt_size;
6130
6131 process_pkt:
6132                         addr = le64_to_cpu(desc->addr);
6133                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6134                                 pkt_size = (status & 0x00003fff) - 4;
6135                         else
6136                                 pkt_size = status & 0x00003fff;
6137
6138                         /*
6139                          * The driver does not support incoming fragmented
6140                          * frames. They are seen as a symptom of over-mtu
6141                          * sized frames.
6142                          */
6143                         if (unlikely(rtl8169_fragmented_frame(status))) {
6144                                 dev->stats.rx_dropped++;
6145                                 dev->stats.rx_length_errors++;
6146                                 goto release_descriptor;
6147                         }
6148
6149                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6150                                                   tp, pkt_size, addr);
6151                         if (!skb) {
6152                                 dev->stats.rx_dropped++;
6153                                 goto release_descriptor;
6154                         }
6155
6156                         rtl8169_rx_csum(skb, status);
6157                         skb_put(skb, pkt_size);
6158                         skb->protocol = eth_type_trans(skb, dev);
6159
6160                         rtl8169_rx_vlan_tag(desc, skb);
6161
6162                         if (skb->pkt_type == PACKET_MULTICAST)
6163                                 dev->stats.multicast++;
6164
6165                         napi_gro_receive(&tp->napi, skb);
6166
6167                         u64_stats_update_begin(&tp->rx_stats.syncp);
6168                         tp->rx_stats.packets++;
6169                         tp->rx_stats.bytes += pkt_size;
6170                         u64_stats_update_end(&tp->rx_stats.syncp);
6171                 }
6172 release_descriptor:
6173                 desc->opts2 = 0;
6174                 rtl8169_mark_to_asic(desc);
6175         }
6176
6177         count = cur_rx - tp->cur_rx;
6178         tp->cur_rx = cur_rx;
6179
6180         return count;
6181 }
6182
6183 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6184 {
6185         struct rtl8169_private *tp = dev_instance;
6186         u16 status = RTL_R16(tp, IntrStatus);
6187
6188         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6189                 return IRQ_NONE;
6190
6191         if (unlikely(status & SYSErr)) {
6192                 rtl8169_pcierr_interrupt(tp->dev);
6193                 goto out;
6194         }
6195
6196         if (status & LinkChg)
6197                 phy_mac_interrupt(tp->phydev);
6198
6199         if (unlikely(status & RxFIFOOver &&
6200             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6201                 netif_stop_queue(tp->dev);
6202                 /* XXX - Hack alert. See rtl_task(). */
6203                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6204         }
6205
6206         rtl_irq_disable(tp);
6207         napi_schedule_irqoff(&tp->napi);
6208 out:
6209         rtl_ack_events(tp, status);
6210
6211         return IRQ_HANDLED;
6212 }
6213
6214 static void rtl_task(struct work_struct *work)
6215 {
6216         static const struct {
6217                 int bitnr;
6218                 void (*action)(struct rtl8169_private *);
6219         } rtl_work[] = {
6220                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6221         };
6222         struct rtl8169_private *tp =
6223                 container_of(work, struct rtl8169_private, wk.work);
6224         struct net_device *dev = tp->dev;
6225         int i;
6226
6227         rtl_lock_work(tp);
6228
6229         if (!netif_running(dev) ||
6230             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6231                 goto out_unlock;
6232
6233         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6234                 bool pending;
6235
6236                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6237                 if (pending)
6238                         rtl_work[i].action(tp);
6239         }
6240
6241 out_unlock:
6242         rtl_unlock_work(tp);
6243 }
6244
6245 static int rtl8169_poll(struct napi_struct *napi, int budget)
6246 {
6247         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6248         struct net_device *dev = tp->dev;
6249         int work_done;
6250
6251         work_done = rtl_rx(dev, tp, (u32) budget);
6252
6253         rtl_tx(dev, tp, budget);
6254
6255         if (work_done < budget) {
6256                 napi_complete_done(napi, work_done);
6257                 rtl_irq_enable(tp);
6258         }
6259
6260         return work_done;
6261 }
6262
6263 static void rtl8169_rx_missed(struct net_device *dev)
6264 {
6265         struct rtl8169_private *tp = netdev_priv(dev);
6266
6267         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6268                 return;
6269
6270         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6271         RTL_W32(tp, RxMissed, 0);
6272 }
6273
6274 static void r8169_phylink_handler(struct net_device *ndev)
6275 {
6276         struct rtl8169_private *tp = netdev_priv(ndev);
6277
6278         if (netif_carrier_ok(ndev)) {
6279                 rtl_link_chg_patch(tp);
6280                 pm_request_resume(&tp->pci_dev->dev);
6281         } else {
6282                 pm_runtime_idle(&tp->pci_dev->dev);
6283         }
6284
6285         if (net_ratelimit())
6286                 phy_print_status(tp->phydev);
6287 }
6288
6289 static int r8169_phy_connect(struct rtl8169_private *tp)
6290 {
6291         struct phy_device *phydev = tp->phydev;
6292         phy_interface_t phy_mode;
6293         int ret;
6294
6295         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6296                    PHY_INTERFACE_MODE_MII;
6297
6298         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6299                                  phy_mode);
6300         if (ret)
6301                 return ret;
6302
6303         if (tp->supports_gmii)
6304                 phy_remove_link_mode(phydev,
6305                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
6306         else
6307                 phy_set_max_speed(phydev, SPEED_100);
6308
6309         phy_support_asym_pause(phydev);
6310
6311         phy_attached_info(phydev);
6312
6313         return 0;
6314 }
6315
6316 static void rtl8169_down(struct net_device *dev)
6317 {
6318         struct rtl8169_private *tp = netdev_priv(dev);
6319
6320         phy_stop(tp->phydev);
6321
6322         napi_disable(&tp->napi);
6323         netif_stop_queue(dev);
6324
6325         rtl8169_hw_reset(tp);
6326         /*
6327          * At this point device interrupts can not be enabled in any function,
6328          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6329          * and napi is disabled (rtl8169_poll).
6330          */
6331         rtl8169_rx_missed(dev);
6332
6333         /* Give a racing hard_start_xmit a few cycles to complete. */
6334         synchronize_rcu();
6335
6336         rtl8169_tx_clear(tp);
6337
6338         rtl8169_rx_clear(tp);
6339
6340         rtl_pll_power_down(tp);
6341 }
6342
6343 static int rtl8169_close(struct net_device *dev)
6344 {
6345         struct rtl8169_private *tp = netdev_priv(dev);
6346         struct pci_dev *pdev = tp->pci_dev;
6347
6348         pm_runtime_get_sync(&pdev->dev);
6349
6350         /* Update counters before going down */
6351         rtl8169_update_counters(tp);
6352
6353         rtl_lock_work(tp);
6354         /* Clear all task flags */
6355         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6356
6357         rtl8169_down(dev);
6358         rtl_unlock_work(tp);
6359
6360         cancel_work_sync(&tp->wk.work);
6361
6362         phy_disconnect(tp->phydev);
6363
6364         pci_free_irq(pdev, 0, tp);
6365
6366         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6367                           tp->RxPhyAddr);
6368         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6369                           tp->TxPhyAddr);
6370         tp->TxDescArray = NULL;
6371         tp->RxDescArray = NULL;
6372
6373         pm_runtime_put_sync(&pdev->dev);
6374
6375         return 0;
6376 }
6377
6378 #ifdef CONFIG_NET_POLL_CONTROLLER
6379 static void rtl8169_netpoll(struct net_device *dev)
6380 {
6381         struct rtl8169_private *tp = netdev_priv(dev);
6382
6383         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6384 }
6385 #endif
6386
6387 static int rtl_open(struct net_device *dev)
6388 {
6389         struct rtl8169_private *tp = netdev_priv(dev);
6390         struct pci_dev *pdev = tp->pci_dev;
6391         int retval = -ENOMEM;
6392
6393         pm_runtime_get_sync(&pdev->dev);
6394
6395         /*
6396          * Rx and Tx descriptors needs 256 bytes alignment.
6397          * dma_alloc_coherent provides more.
6398          */
6399         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6400                                              &tp->TxPhyAddr, GFP_KERNEL);
6401         if (!tp->TxDescArray)
6402                 goto err_pm_runtime_put;
6403
6404         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6405                                              &tp->RxPhyAddr, GFP_KERNEL);
6406         if (!tp->RxDescArray)
6407                 goto err_free_tx_0;
6408
6409         retval = rtl8169_init_ring(tp);
6410         if (retval < 0)
6411                 goto err_free_rx_1;
6412
6413         rtl_request_firmware(tp);
6414
6415         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6416                                  dev->name);
6417         if (retval < 0)
6418                 goto err_release_fw_2;
6419
6420         retval = r8169_phy_connect(tp);
6421         if (retval)
6422                 goto err_free_irq;
6423
6424         rtl_lock_work(tp);
6425
6426         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6427
6428         napi_enable(&tp->napi);
6429
6430         rtl8169_init_phy(dev, tp);
6431
6432         rtl_pll_power_up(tp);
6433
6434         rtl_hw_start(tp);
6435
6436         if (!rtl8169_init_counter_offsets(tp))
6437                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6438
6439         phy_start(tp->phydev);
6440         netif_start_queue(dev);
6441
6442         rtl_unlock_work(tp);
6443
6444         pm_runtime_put_sync(&pdev->dev);
6445 out:
6446         return retval;
6447
6448 err_free_irq:
6449         pci_free_irq(pdev, 0, tp);
6450 err_release_fw_2:
6451         rtl_release_firmware(tp);
6452         rtl8169_rx_clear(tp);
6453 err_free_rx_1:
6454         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6455                           tp->RxPhyAddr);
6456         tp->RxDescArray = NULL;
6457 err_free_tx_0:
6458         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6459                           tp->TxPhyAddr);
6460         tp->TxDescArray = NULL;
6461 err_pm_runtime_put:
6462         pm_runtime_put_noidle(&pdev->dev);
6463         goto out;
6464 }
6465
6466 static void
6467 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6468 {
6469         struct rtl8169_private *tp = netdev_priv(dev);
6470         struct pci_dev *pdev = tp->pci_dev;
6471         struct rtl8169_counters *counters = tp->counters;
6472         unsigned int start;
6473
6474         pm_runtime_get_noresume(&pdev->dev);
6475
6476         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6477                 rtl8169_rx_missed(dev);
6478
6479         do {
6480                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6481                 stats->rx_packets = tp->rx_stats.packets;
6482                 stats->rx_bytes = tp->rx_stats.bytes;
6483         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6484
6485         do {
6486                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6487                 stats->tx_packets = tp->tx_stats.packets;
6488                 stats->tx_bytes = tp->tx_stats.bytes;
6489         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6490
6491         stats->rx_dropped       = dev->stats.rx_dropped;
6492         stats->tx_dropped       = dev->stats.tx_dropped;
6493         stats->rx_length_errors = dev->stats.rx_length_errors;
6494         stats->rx_errors        = dev->stats.rx_errors;
6495         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6496         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6497         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6498         stats->multicast        = dev->stats.multicast;
6499
6500         /*
6501          * Fetch additonal counter values missing in stats collected by driver
6502          * from tally counters.
6503          */
6504         if (pm_runtime_active(&pdev->dev))
6505                 rtl8169_update_counters(tp);
6506
6507         /*
6508          * Subtract values fetched during initalization.
6509          * See rtl8169_init_counter_offsets for a description why we do that.
6510          */
6511         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6512                 le64_to_cpu(tp->tc_offset.tx_errors);
6513         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6514                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6515         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6516                 le16_to_cpu(tp->tc_offset.tx_aborted);
6517
6518         pm_runtime_put_noidle(&pdev->dev);
6519 }
6520
6521 static void rtl8169_net_suspend(struct net_device *dev)
6522 {
6523         struct rtl8169_private *tp = netdev_priv(dev);
6524
6525         if (!netif_running(dev))
6526                 return;
6527
6528         phy_stop(tp->phydev);
6529         netif_device_detach(dev);
6530
6531         rtl_lock_work(tp);
6532         napi_disable(&tp->napi);
6533         /* Clear all task flags */
6534         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6535
6536         rtl_unlock_work(tp);
6537
6538         rtl_pll_power_down(tp);
6539 }
6540
6541 #ifdef CONFIG_PM
6542
6543 static int rtl8169_suspend(struct device *device)
6544 {
6545         struct net_device *dev = dev_get_drvdata(device);
6546         struct rtl8169_private *tp = netdev_priv(dev);
6547
6548         rtl8169_net_suspend(dev);
6549         clk_disable_unprepare(tp->clk);
6550
6551         return 0;
6552 }
6553
6554 static void __rtl8169_resume(struct net_device *dev)
6555 {
6556         struct rtl8169_private *tp = netdev_priv(dev);
6557
6558         netif_device_attach(dev);
6559
6560         rtl_pll_power_up(tp);
6561         rtl8169_init_phy(dev, tp);
6562
6563         phy_start(tp->phydev);
6564
6565         rtl_lock_work(tp);
6566         napi_enable(&tp->napi);
6567         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6568         rtl_reset_work(tp);
6569         rtl_unlock_work(tp);
6570 }
6571
6572 static int rtl8169_resume(struct device *device)
6573 {
6574         struct net_device *dev = dev_get_drvdata(device);
6575         struct rtl8169_private *tp = netdev_priv(dev);
6576
6577         rtl_rar_set(tp, dev->dev_addr);
6578
6579         clk_prepare_enable(tp->clk);
6580
6581         if (netif_running(dev))
6582                 __rtl8169_resume(dev);
6583
6584         return 0;
6585 }
6586
6587 static int rtl8169_runtime_suspend(struct device *device)
6588 {
6589         struct net_device *dev = dev_get_drvdata(device);
6590         struct rtl8169_private *tp = netdev_priv(dev);
6591
6592         if (!tp->TxDescArray)
6593                 return 0;
6594
6595         rtl_lock_work(tp);
6596         __rtl8169_set_wol(tp, WAKE_ANY);
6597         rtl_unlock_work(tp);
6598
6599         rtl8169_net_suspend(dev);
6600
6601         /* Update counters before going runtime suspend */
6602         rtl8169_rx_missed(dev);
6603         rtl8169_update_counters(tp);
6604
6605         return 0;
6606 }
6607
6608 static int rtl8169_runtime_resume(struct device *device)
6609 {
6610         struct net_device *dev = dev_get_drvdata(device);
6611         struct rtl8169_private *tp = netdev_priv(dev);
6612
6613         rtl_rar_set(tp, dev->dev_addr);
6614
6615         if (!tp->TxDescArray)
6616                 return 0;
6617
6618         rtl_lock_work(tp);
6619         __rtl8169_set_wol(tp, tp->saved_wolopts);
6620         rtl_unlock_work(tp);
6621
6622         __rtl8169_resume(dev);
6623
6624         return 0;
6625 }
6626
6627 static int rtl8169_runtime_idle(struct device *device)
6628 {
6629         struct net_device *dev = dev_get_drvdata(device);
6630
6631         if (!netif_running(dev) || !netif_carrier_ok(dev))
6632                 pm_schedule_suspend(device, 10000);
6633
6634         return -EBUSY;
6635 }
6636
6637 static const struct dev_pm_ops rtl8169_pm_ops = {
6638         .suspend                = rtl8169_suspend,
6639         .resume                 = rtl8169_resume,
6640         .freeze                 = rtl8169_suspend,
6641         .thaw                   = rtl8169_resume,
6642         .poweroff               = rtl8169_suspend,
6643         .restore                = rtl8169_resume,
6644         .runtime_suspend        = rtl8169_runtime_suspend,
6645         .runtime_resume         = rtl8169_runtime_resume,
6646         .runtime_idle           = rtl8169_runtime_idle,
6647 };
6648
6649 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6650
6651 #else /* !CONFIG_PM */
6652
6653 #define RTL8169_PM_OPS  NULL
6654
6655 #endif /* !CONFIG_PM */
6656
6657 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6658 {
6659         /* WoL fails with 8168b when the receiver is disabled. */
6660         switch (tp->mac_version) {
6661         case RTL_GIGA_MAC_VER_11:
6662         case RTL_GIGA_MAC_VER_12:
6663         case RTL_GIGA_MAC_VER_17:
6664                 pci_clear_master(tp->pci_dev);
6665
6666                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6667                 /* PCI commit */
6668                 RTL_R8(tp, ChipCmd);
6669                 break;
6670         default:
6671                 break;
6672         }
6673 }
6674
6675 static void rtl_shutdown(struct pci_dev *pdev)
6676 {
6677         struct net_device *dev = pci_get_drvdata(pdev);
6678         struct rtl8169_private *tp = netdev_priv(dev);
6679
6680         rtl8169_net_suspend(dev);
6681
6682         /* Restore original MAC address */
6683         rtl_rar_set(tp, dev->perm_addr);
6684
6685         rtl8169_hw_reset(tp);
6686
6687         if (system_state == SYSTEM_POWER_OFF) {
6688                 if (tp->saved_wolopts) {
6689                         rtl_wol_suspend_quirk(tp);
6690                         rtl_wol_shutdown_quirk(tp);
6691                 }
6692
6693                 pci_wake_from_d3(pdev, true);
6694                 pci_set_power_state(pdev, PCI_D3hot);
6695         }
6696 }
6697
6698 static void rtl_remove_one(struct pci_dev *pdev)
6699 {
6700         struct net_device *dev = pci_get_drvdata(pdev);
6701         struct rtl8169_private *tp = netdev_priv(dev);
6702
6703         if (r8168_check_dash(tp))
6704                 rtl8168_driver_stop(tp);
6705
6706         netif_napi_del(&tp->napi);
6707
6708         unregister_netdev(dev);
6709         mdiobus_unregister(tp->phydev->mdio.bus);
6710
6711         rtl_release_firmware(tp);
6712
6713         if (pci_dev_run_wake(pdev))
6714                 pm_runtime_get_noresume(&pdev->dev);
6715
6716         /* restore original MAC address */
6717         rtl_rar_set(tp, dev->perm_addr);
6718 }
6719
6720 static const struct net_device_ops rtl_netdev_ops = {
6721         .ndo_open               = rtl_open,
6722         .ndo_stop               = rtl8169_close,
6723         .ndo_get_stats64        = rtl8169_get_stats64,
6724         .ndo_start_xmit         = rtl8169_start_xmit,
6725         .ndo_tx_timeout         = rtl8169_tx_timeout,
6726         .ndo_validate_addr      = eth_validate_addr,
6727         .ndo_change_mtu         = rtl8169_change_mtu,
6728         .ndo_fix_features       = rtl8169_fix_features,
6729         .ndo_set_features       = rtl8169_set_features,
6730         .ndo_set_mac_address    = rtl_set_mac_address,
6731         .ndo_do_ioctl           = rtl8169_ioctl,
6732         .ndo_set_rx_mode        = rtl_set_rx_mode,
6733 #ifdef CONFIG_NET_POLL_CONTROLLER
6734         .ndo_poll_controller    = rtl8169_netpoll,
6735 #endif
6736
6737 };
6738
6739 static const struct rtl_cfg_info {
6740         void (*hw_start)(struct rtl8169_private *tp);
6741         u16 irq_mask;
6742         unsigned int has_gmii:1;
6743         const struct rtl_coalesce_info *coalesce_info;
6744 } rtl_cfg_infos [] = {
6745         [RTL_CFG_0] = {
6746                 .hw_start       = rtl_hw_start_8169,
6747                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6748                 .has_gmii       = 1,
6749                 .coalesce_info  = rtl_coalesce_info_8169,
6750         },
6751         [RTL_CFG_1] = {
6752                 .hw_start       = rtl_hw_start_8168,
6753                 .irq_mask       = LinkChg | RxOverflow,
6754                 .has_gmii       = 1,
6755                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6756         },
6757         [RTL_CFG_2] = {
6758                 .hw_start       = rtl_hw_start_8101,
6759                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6760                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6761         }
6762 };
6763
6764 static int rtl_alloc_irq(struct rtl8169_private *tp)
6765 {
6766         unsigned int flags;
6767
6768         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6769                 rtl_unlock_config_regs(tp);
6770                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6771                 rtl_lock_config_regs(tp);
6772                 flags = PCI_IRQ_LEGACY;
6773         } else {
6774                 flags = PCI_IRQ_ALL_TYPES;
6775         }
6776
6777         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6778 }
6779
6780 static void rtl_read_mac_address(struct rtl8169_private *tp,
6781                                  u8 mac_addr[ETH_ALEN])
6782 {
6783         u32 value;
6784
6785         /* Get MAC address */
6786         switch (tp->mac_version) {
6787         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6788         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6789                 value = rtl_eri_read(tp, 0xe0);
6790                 mac_addr[0] = (value >>  0) & 0xff;
6791                 mac_addr[1] = (value >>  8) & 0xff;
6792                 mac_addr[2] = (value >> 16) & 0xff;
6793                 mac_addr[3] = (value >> 24) & 0xff;
6794
6795                 value = rtl_eri_read(tp, 0xe4);
6796                 mac_addr[4] = (value >>  0) & 0xff;
6797                 mac_addr[5] = (value >>  8) & 0xff;
6798                 break;
6799         default:
6800                 break;
6801         }
6802 }
6803
6804 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6805 {
6806         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6807 }
6808
6809 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6810 {
6811         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6812 }
6813
6814 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6815 {
6816         struct rtl8169_private *tp = mii_bus->priv;
6817
6818         if (phyaddr > 0)
6819                 return -ENODEV;
6820
6821         return rtl_readphy(tp, phyreg);
6822 }
6823
6824 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6825                                 int phyreg, u16 val)
6826 {
6827         struct rtl8169_private *tp = mii_bus->priv;
6828
6829         if (phyaddr > 0)
6830                 return -ENODEV;
6831
6832         rtl_writephy(tp, phyreg, val);
6833
6834         return 0;
6835 }
6836
6837 static int r8169_mdio_register(struct rtl8169_private *tp)
6838 {
6839         struct pci_dev *pdev = tp->pci_dev;
6840         struct mii_bus *new_bus;
6841         int ret;
6842
6843         new_bus = devm_mdiobus_alloc(&pdev->dev);
6844         if (!new_bus)
6845                 return -ENOMEM;
6846
6847         new_bus->name = "r8169";
6848         new_bus->priv = tp;
6849         new_bus->parent = &pdev->dev;
6850         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6851         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6852
6853         new_bus->read = r8169_mdio_read_reg;
6854         new_bus->write = r8169_mdio_write_reg;
6855
6856         ret = mdiobus_register(new_bus);
6857         if (ret)
6858                 return ret;
6859
6860         tp->phydev = mdiobus_get_phy(new_bus, 0);
6861         if (!tp->phydev) {
6862                 mdiobus_unregister(new_bus);
6863                 return -ENODEV;
6864         }
6865
6866         /* PHY will be woken up in rtl_open() */
6867         phy_suspend(tp->phydev);
6868
6869         return 0;
6870 }
6871
6872 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6873 {
6874         u32 data;
6875
6876         tp->ocp_base = OCP_STD_PHY_BASE;
6877
6878         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6879
6880         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6881                 return;
6882
6883         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6884                 return;
6885
6886         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6887         msleep(1);
6888         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6889
6890         data = r8168_mac_ocp_read(tp, 0xe8de);
6891         data &= ~(1 << 14);
6892         r8168_mac_ocp_write(tp, 0xe8de, data);
6893
6894         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6895                 return;
6896
6897         data = r8168_mac_ocp_read(tp, 0xe8de);
6898         data |= (1 << 15);
6899         r8168_mac_ocp_write(tp, 0xe8de, data);
6900
6901         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6902 }
6903
6904 static void rtl_hw_initialize(struct rtl8169_private *tp)
6905 {
6906         switch (tp->mac_version) {
6907         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
6908                 rtl8168ep_stop_cmac(tp);
6909                 /* fall through */
6910         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6911                 rtl_hw_init_8168g(tp);
6912                 break;
6913         default:
6914                 break;
6915         }
6916 }
6917
6918 static int rtl_jumbo_max(struct rtl8169_private *tp)
6919 {
6920         /* Non-GBit versions don't support jumbo frames */
6921         if (!tp->supports_gmii)
6922                 return JUMBO_1K;
6923
6924         switch (tp->mac_version) {
6925         /* RTL8169 */
6926         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6927                 return JUMBO_7K;
6928         /* RTL8168b */
6929         case RTL_GIGA_MAC_VER_11:
6930         case RTL_GIGA_MAC_VER_12:
6931         case RTL_GIGA_MAC_VER_17:
6932                 return JUMBO_4K;
6933         /* RTL8168c */
6934         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6935                 return JUMBO_6K;
6936         default:
6937                 return JUMBO_9K;
6938         }
6939 }
6940
6941 static void rtl_disable_clk(void *data)
6942 {
6943         clk_disable_unprepare(data);
6944 }
6945
6946 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6947 {
6948         struct device *d = tp_to_dev(tp);
6949         struct clk *clk;
6950         int rc;
6951
6952         clk = devm_clk_get(d, "ether_clk");
6953         if (IS_ERR(clk)) {
6954                 rc = PTR_ERR(clk);
6955                 if (rc == -ENOENT)
6956                         /* clk-core allows NULL (for suspend / resume) */
6957                         rc = 0;
6958                 else if (rc != -EPROBE_DEFER)
6959                         dev_err(d, "failed to get clk: %d\n", rc);
6960         } else {
6961                 tp->clk = clk;
6962                 rc = clk_prepare_enable(clk);
6963                 if (rc)
6964                         dev_err(d, "failed to enable clk: %d\n", rc);
6965                 else
6966                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6967         }
6968
6969         return rc;
6970 }
6971
6972 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6973 {
6974         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
6975         /* align to u16 for is_valid_ether_addr() */
6976         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
6977         struct rtl8169_private *tp;
6978         struct net_device *dev;
6979         int chipset, region, i;
6980         int jumbo_max, rc;
6981
6982         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6983         if (!dev)
6984                 return -ENOMEM;
6985
6986         SET_NETDEV_DEV(dev, &pdev->dev);
6987         dev->netdev_ops = &rtl_netdev_ops;
6988         tp = netdev_priv(dev);
6989         tp->dev = dev;
6990         tp->pci_dev = pdev;
6991         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6992         tp->supports_gmii = cfg->has_gmii;
6993
6994         /* Get the *optional* external "ether_clk" used on some boards */
6995         rc = rtl_get_ether_clk(tp);
6996         if (rc)
6997                 return rc;
6998
6999         /* Disable ASPM completely as that cause random device stop working
7000          * problems as well as full system hangs for some PCIe devices users.
7001          */
7002         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7003
7004         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7005         rc = pcim_enable_device(pdev);
7006         if (rc < 0) {
7007                 dev_err(&pdev->dev, "enable failure\n");
7008                 return rc;
7009         }
7010
7011         if (pcim_set_mwi(pdev) < 0)
7012                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7013
7014         /* use first MMIO region */
7015         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7016         if (region < 0) {
7017                 dev_err(&pdev->dev, "no MMIO resource found\n");
7018                 return -ENODEV;
7019         }
7020
7021         /* check for weird/broken PCI region reporting */
7022         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7023                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7024                 return -ENODEV;
7025         }
7026
7027         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7028         if (rc < 0) {
7029                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7030                 return rc;
7031         }
7032
7033         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7034
7035         /* Identify chip attached to board */
7036         rtl8169_get_mac_version(tp);
7037         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7038                 return -ENODEV;
7039
7040         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7041
7042         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7043             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7044                 dev->features |= NETIF_F_HIGHDMA;
7045         } else {
7046                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7047                 if (rc < 0) {
7048                         dev_err(&pdev->dev, "DMA configuration failed\n");
7049                         return rc;
7050                 }
7051         }
7052
7053         rtl_init_rxcfg(tp);
7054
7055         rtl8169_irq_mask_and_ack(tp);
7056
7057         rtl_hw_initialize(tp);
7058
7059         rtl_hw_reset(tp);
7060
7061         pci_set_master(pdev);
7062
7063         chipset = tp->mac_version;
7064
7065         rc = rtl_alloc_irq(tp);
7066         if (rc < 0) {
7067                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7068                 return rc;
7069         }
7070
7071         mutex_init(&tp->wk.mutex);
7072         INIT_WORK(&tp->wk.work, rtl_task);
7073         u64_stats_init(&tp->rx_stats.syncp);
7074         u64_stats_init(&tp->tx_stats.syncp);
7075
7076         /* get MAC address */
7077         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7078         if (rc)
7079                 rtl_read_mac_address(tp, mac_addr);
7080
7081         if (is_valid_ether_addr(mac_addr))
7082                 rtl_rar_set(tp, mac_addr);
7083
7084         for (i = 0; i < ETH_ALEN; i++)
7085                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7086
7087         dev->ethtool_ops = &rtl8169_ethtool_ops;
7088
7089         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7090
7091         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7092          * properly for all devices */
7093         dev->features |= NETIF_F_RXCSUM |
7094                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7095
7096         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7097                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7098                 NETIF_F_HW_VLAN_CTAG_RX;
7099         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7100                 NETIF_F_HIGHDMA;
7101         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7102
7103         tp->cp_cmd |= RxChkSum | RxVlan;
7104
7105         /*
7106          * Pretend we are using VLANs; This bypasses a nasty bug where
7107          * Interrupts stop flowing on high load on 8110SCd controllers.
7108          */
7109         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7110                 /* Disallow toggling */
7111                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7112
7113         if (rtl_chip_supports_csum_v2(tp))
7114                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7115
7116         dev->hw_features |= NETIF_F_RXALL;
7117         dev->hw_features |= NETIF_F_RXFCS;
7118
7119         /* MTU range: 60 - hw-specific max */
7120         dev->min_mtu = ETH_ZLEN;
7121         jumbo_max = rtl_jumbo_max(tp);
7122         dev->max_mtu = jumbo_max;
7123
7124         tp->hw_start = cfg->hw_start;
7125         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7126         tp->coalesce_info = cfg->coalesce_info;
7127
7128         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7129
7130         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7131                                             &tp->counters_phys_addr,
7132                                             GFP_KERNEL);
7133         if (!tp->counters)
7134                 return -ENOMEM;
7135
7136         pci_set_drvdata(pdev, dev);
7137
7138         rc = r8169_mdio_register(tp);
7139         if (rc)
7140                 return rc;
7141
7142         /* chip gets powered up in rtl_open() */
7143         rtl_pll_power_down(tp);
7144
7145         rc = register_netdev(dev);
7146         if (rc)
7147                 goto err_mdio_unregister;
7148
7149         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7150                    rtl_chip_infos[chipset].name, dev->dev_addr,
7151                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7152                    pci_irq_vector(pdev, 0));
7153
7154         if (jumbo_max > JUMBO_1K)
7155                 netif_info(tp, probe, dev,
7156                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7157                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7158                            "ok" : "ko");
7159
7160         if (r8168_check_dash(tp))
7161                 rtl8168_driver_start(tp);
7162
7163         if (pci_dev_run_wake(pdev))
7164                 pm_runtime_put_sync(&pdev->dev);
7165
7166         return 0;
7167
7168 err_mdio_unregister:
7169         mdiobus_unregister(tp->phydev->mdio.bus);
7170         return rc;
7171 }
7172
7173 static struct pci_driver rtl8169_pci_driver = {
7174         .name           = MODULENAME,
7175         .id_table       = rtl8169_pci_tbl,
7176         .probe          = rtl_init_one,
7177         .remove         = rtl_remove_one,
7178         .shutdown       = rtl_shutdown,
7179         .driver.pm      = RTL8169_PM_OPS,
7180 };
7181
7182 module_pci_driver(rtl8169_pci_driver);