drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/phy.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/prefetch.h>
  29 #include <linux/ipv6.h>
  30 #include <net/ip6_checksum.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 #define TX_SLOTS_AVAIL(tp) \
  62         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  63
  64 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  65 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  66         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  73 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  74
  75 #define R8169_REGS_SIZE         256
  76 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  77 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  78 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  79 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  80 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  81
  82 #define RTL8169_TX_TIMEOUT      (6*HZ)
  83
  84 /* write/read MMIO register */
  85 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  86 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  87 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  88 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  89 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  90 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  91
  92 enum mac_version {
  93         RTL_GIGA_MAC_VER_01 = 0,
  94         RTL_GIGA_MAC_VER_02,
  95         RTL_GIGA_MAC_VER_03,
  96         RTL_GIGA_MAC_VER_04,
  97         RTL_GIGA_MAC_VER_05,
  98         RTL_GIGA_MAC_VER_06,
  99         RTL_GIGA_MAC_VER_07,
 100         RTL_GIGA_MAC_VER_08,
 101         RTL_GIGA_MAC_VER_09,
 102         RTL_GIGA_MAC_VER_10,
 103         RTL_GIGA_MAC_VER_11,
 104         RTL_GIGA_MAC_VER_12,
 105         RTL_GIGA_MAC_VER_13,
 106         RTL_GIGA_MAC_VER_14,
 107         RTL_GIGA_MAC_VER_15,
 108         RTL_GIGA_MAC_VER_16,
 109         RTL_GIGA_MAC_VER_17,
 110         RTL_GIGA_MAC_VER_18,
 111         RTL_GIGA_MAC_VER_19,
 112         RTL_GIGA_MAC_VER_20,
 113         RTL_GIGA_MAC_VER_21,
 114         RTL_GIGA_MAC_VER_22,
 115         RTL_GIGA_MAC_VER_23,
 116         RTL_GIGA_MAC_VER_24,
 117         RTL_GIGA_MAC_VER_25,
 118         RTL_GIGA_MAC_VER_26,
 119         RTL_GIGA_MAC_VER_27,
 120         RTL_GIGA_MAC_VER_28,
 121         RTL_GIGA_MAC_VER_29,
 122         RTL_GIGA_MAC_VER_30,
 123         RTL_GIGA_MAC_VER_31,
 124         RTL_GIGA_MAC_VER_32,
 125         RTL_GIGA_MAC_VER_33,
 126         RTL_GIGA_MAC_VER_34,
 127         RTL_GIGA_MAC_VER_35,
 128         RTL_GIGA_MAC_VER_36,
 129         RTL_GIGA_MAC_VER_37,
 130         RTL_GIGA_MAC_VER_38,
 131         RTL_GIGA_MAC_VER_39,
 132         RTL_GIGA_MAC_VER_40,
 133         RTL_GIGA_MAC_VER_41,
 134         RTL_GIGA_MAC_VER_42,
 135         RTL_GIGA_MAC_VER_43,
 136         RTL_GIGA_MAC_VER_44,
 137         RTL_GIGA_MAC_VER_45,
 138         RTL_GIGA_MAC_VER_46,
 139         RTL_GIGA_MAC_VER_47,
 140         RTL_GIGA_MAC_VER_48,
 141         RTL_GIGA_MAC_VER_49,
 142         RTL_GIGA_MAC_VER_50,
 143         RTL_GIGA_MAC_VER_51,
 144         RTL_GIGA_MAC_NONE   = 0xff,
 145 };
 146
 147 enum rtl_tx_desc_version {
 148         RTL_TD_0        = 0,
 149         RTL_TD_1        = 1,
 150 };
 151
 152 #define JUMBO_1K        ETH_DATA_LEN
 153 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 154 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 155 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 156 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 157
 158 #define _R(NAME,TD,FW,SZ) {     \
 159         .name = NAME,           \
 160         .txd_version = TD,      \
 161         .fw_name = FW,          \
 162         .jumbo_max = SZ,        \
 163 }
 164
 165 static const struct {
 166         const char *name;
 167         enum rtl_tx_desc_version txd_version;
 168         const char *fw_name;
 169         u16 jumbo_max;
 170 } rtl_chip_infos[] = {
 171         /* PCI devices. */
 172         [RTL_GIGA_MAC_VER_01] =
 173                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K),
 174         [RTL_GIGA_MAC_VER_02] =
 175                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K),
 176         [RTL_GIGA_MAC_VER_03] =
 177                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K),
 178         [RTL_GIGA_MAC_VER_04] =
 179                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K),
 180         [RTL_GIGA_MAC_VER_05] =
 181                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 182         [RTL_GIGA_MAC_VER_06] =
 183                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 184         /* PCI-E devices. */
 185         [RTL_GIGA_MAC_VER_07] =
 186                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 187         [RTL_GIGA_MAC_VER_08] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 189         [RTL_GIGA_MAC_VER_09] =
 190                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 191         [RTL_GIGA_MAC_VER_10] =
 192                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 193         [RTL_GIGA_MAC_VER_11] =
 194                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 195         [RTL_GIGA_MAC_VER_12] =
 196                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 197         [RTL_GIGA_MAC_VER_13] =
 198                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 199         [RTL_GIGA_MAC_VER_14] =
 200                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 201         [RTL_GIGA_MAC_VER_15] =
 202                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 203         [RTL_GIGA_MAC_VER_16] =
 204                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 205         [RTL_GIGA_MAC_VER_17] =
 206                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 207         [RTL_GIGA_MAC_VER_18] =
 208                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 209         [RTL_GIGA_MAC_VER_19] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 211         [RTL_GIGA_MAC_VER_20] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 213         [RTL_GIGA_MAC_VER_21] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 215         [RTL_GIGA_MAC_VER_22] =
 216                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 217         [RTL_GIGA_MAC_VER_23] =
 218                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 219         [RTL_GIGA_MAC_VER_24] =
 220                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 221         [RTL_GIGA_MAC_VER_25] =
 222                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
 223         [RTL_GIGA_MAC_VER_26] =
 224                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
 225         [RTL_GIGA_MAC_VER_27] =
 226                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 227         [RTL_GIGA_MAC_VER_28] =
 228                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 229         [RTL_GIGA_MAC_VER_29] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 231         [RTL_GIGA_MAC_VER_30] =
 232                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 233         [RTL_GIGA_MAC_VER_31] =
 234                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 235         [RTL_GIGA_MAC_VER_32] =
 236                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
 237         [RTL_GIGA_MAC_VER_33] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
 239         [RTL_GIGA_MAC_VER_34] =
 240                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
 241         [RTL_GIGA_MAC_VER_35] =
 242                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
 243         [RTL_GIGA_MAC_VER_36] =
 244                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
 245         [RTL_GIGA_MAC_VER_37] =
 246                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,  JUMBO_1K),
 247         [RTL_GIGA_MAC_VER_38] =
 248                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,  JUMBO_9K),
 249         [RTL_GIGA_MAC_VER_39] =
 250                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
 251         [RTL_GIGA_MAC_VER_40] =
 252                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
 253         [RTL_GIGA_MAC_VER_41] =
 254                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K),
 255         [RTL_GIGA_MAC_VER_42] =
 256                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
 257         [RTL_GIGA_MAC_VER_43] =
 258                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
 259         [RTL_GIGA_MAC_VER_44] =
 260                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,  JUMBO_9K),
 261         [RTL_GIGA_MAC_VER_45] =
 262                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
 263         [RTL_GIGA_MAC_VER_46] =
 264                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
 265         [RTL_GIGA_MAC_VER_47] =
 266                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
 267         [RTL_GIGA_MAC_VER_48] =
 268                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
 269         [RTL_GIGA_MAC_VER_49] =
 270                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 271         [RTL_GIGA_MAC_VER_50] =
 272                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 273         [RTL_GIGA_MAC_VER_51] =
 274                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 275 };
 276 #undef _R
 277
 278 enum cfg_version {
 279         RTL_CFG_0 = 0x00,
 280         RTL_CFG_1,
 281         RTL_CFG_2
 282 };
 283
 284 static const struct pci_device_id rtl8169_pci_tbl[] = {
 285         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 286         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 287         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 288         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 289         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 290         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 291         { PCI_VENDOR_ID_DLINK,                  0x4300,
 292                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 293         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 294         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 295         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 296         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 297         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 298                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 299         { 0x0001,                               0x8168,
 300                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 301         {0,},
 302 };
 303
 304 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 305
 306 static int use_dac = -1;
 307 static struct {
 308         u32 msg_enable;
 309 } debug = { -1 };
 310
 311 enum rtl_registers {
 312         MAC0            = 0,    /* Ethernet hardware address. */
 313         MAC4            = 4,
 314         MAR0            = 8,    /* Multicast filter. */
 315         CounterAddrLow          = 0x10,
 316         CounterAddrHigh         = 0x14,
 317         TxDescStartAddrLow      = 0x20,
 318         TxDescStartAddrHigh     = 0x24,
 319         TxHDescStartAddrLow     = 0x28,
 320         TxHDescStartAddrHigh    = 0x2c,
 321         FLASH           = 0x30,
 322         ERSR            = 0x36,
 323         ChipCmd         = 0x37,
 324         TxPoll          = 0x38,
 325         IntrMask        = 0x3c,
 326         IntrStatus      = 0x3e,
 327
 328         TxConfig        = 0x40,
 329 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 330 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 331
 332         RxConfig        = 0x44,
 333 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 334 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 335 #define RXCFG_FIFO_SHIFT                13
 336                                         /* No threshold before first PCI xfer */
 337 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 338 #define RX_EARLY_OFF                    (1 << 11)
 339 #define RXCFG_DMA_SHIFT                 8
 340                                         /* Unlimited maximum PCI burst. */
 341 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 342
 343         RxMissed        = 0x4c,
 344         Cfg9346         = 0x50,
 345         Config0         = 0x51,
 346         Config1         = 0x52,
 347         Config2         = 0x53,
 348 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 349
 350         Config3         = 0x54,
 351         Config4         = 0x55,
 352         Config5         = 0x56,
 353         MultiIntr       = 0x5c,
 354         PHYAR           = 0x60,
 355         PHYstatus       = 0x6c,
 356         RxMaxSize       = 0xda,
 357         CPlusCmd        = 0xe0,
 358         IntrMitigate    = 0xe2,
 359
 360 #define RTL_COALESCE_MASK       0x0f
 361 #define RTL_COALESCE_SHIFT      4
 362 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 363 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 364
 365         RxDescAddrLow   = 0xe4,
 366         RxDescAddrHigh  = 0xe8,
 367         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 368
 369 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 370
 371         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 372
 373 #define TxPacketMax     (8064 >> 7)
 374 #define EarlySize       0x27
 375
 376         FuncEvent       = 0xf0,
 377         FuncEventMask   = 0xf4,
 378         FuncPresetState = 0xf8,
 379         IBCR0           = 0xf8,
 380         IBCR2           = 0xf9,
 381         IBIMR0          = 0xfa,
 382         IBISR0          = 0xfb,
 383         FuncForceEvent  = 0xfc,
 384 };
 385
 386 enum rtl8168_8101_registers {
 387         CSIDR                   = 0x64,
 388         CSIAR                   = 0x68,
 389 #define CSIAR_FLAG                      0x80000000
 390 #define CSIAR_WRITE_CMD                 0x80000000
 391 #define CSIAR_BYTE_ENABLE               0x0000f000
 392 #define CSIAR_ADDR_MASK                 0x00000fff
 393         PMCH                    = 0x6f,
 394         EPHYAR                  = 0x80,
 395 #define EPHYAR_FLAG                     0x80000000
 396 #define EPHYAR_WRITE_CMD                0x80000000
 397 #define EPHYAR_REG_MASK                 0x1f
 398 #define EPHYAR_REG_SHIFT                16
 399 #define EPHYAR_DATA_MASK                0xffff
 400         DLLPR                   = 0xd0,
 401 #define PFM_EN                          (1 << 6)
 402 #define TX_10M_PS_EN                    (1 << 7)
 403         DBG_REG                 = 0xd1,
 404 #define FIX_NAK_1                       (1 << 4)
 405 #define FIX_NAK_2                       (1 << 3)
 406         TWSI                    = 0xd2,
 407         MCU                     = 0xd3,
 408 #define NOW_IS_OOB                      (1 << 7)
 409 #define TX_EMPTY                        (1 << 5)
 410 #define RX_EMPTY                        (1 << 4)
 411 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 412 #define EN_NDP                          (1 << 3)
 413 #define EN_OOB_RESET                    (1 << 2)
 414 #define LINK_LIST_RDY                   (1 << 1)
 415         EFUSEAR                 = 0xdc,
 416 #define EFUSEAR_FLAG                    0x80000000
 417 #define EFUSEAR_WRITE_CMD               0x80000000
 418 #define EFUSEAR_READ_CMD                0x00000000
 419 #define EFUSEAR_REG_MASK                0x03ff
 420 #define EFUSEAR_REG_SHIFT               8
 421 #define EFUSEAR_DATA_MASK               0xff
 422         MISC_1                  = 0xf2,
 423 #define PFM_D3COLD_EN                   (1 << 6)
 424 };
 425
 426 enum rtl8168_registers {
 427         LED_FREQ                = 0x1a,
 428         EEE_LED                 = 0x1b,
 429         ERIDR                   = 0x70,
 430         ERIAR                   = 0x74,
 431 #define ERIAR_FLAG                      0x80000000
 432 #define ERIAR_WRITE_CMD                 0x80000000
 433 #define ERIAR_READ_CMD                  0x00000000
 434 #define ERIAR_ADDR_BYTE_ALIGN           4
 435 #define ERIAR_TYPE_SHIFT                16
 436 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 437 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 438 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 439 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 440 #define ERIAR_MASK_SHIFT                12
 441 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 442 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 443 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 444 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 445 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 446         EPHY_RXER_NUM           = 0x7c,
 447         OCPDR                   = 0xb0, /* OCP GPHY access */
 448 #define OCPDR_WRITE_CMD                 0x80000000
 449 #define OCPDR_READ_CMD                  0x00000000
 450 #define OCPDR_REG_MASK                  0x7f
 451 #define OCPDR_GPHY_REG_SHIFT            16
 452 #define OCPDR_DATA_MASK                 0xffff
 453         OCPAR                   = 0xb4,
 454 #define OCPAR_FLAG                      0x80000000
 455 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 456 #define OCPAR_GPHY_READ_CMD             0x0000f060
 457         GPHY_OCP                = 0xb8,
 458         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 459         MISC                    = 0xf0, /* 8168e only. */
 460 #define TXPLA_RST                       (1 << 29)
 461 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 462 #define PWM_EN                          (1 << 22)
 463 #define RXDV_GATED_EN                   (1 << 19)
 464 #define EARLY_TALLY_EN                  (1 << 16)
 465 };
 466
 467 enum rtl_register_content {
 468         /* InterruptStatusBits */
 469         SYSErr          = 0x8000,
 470         PCSTimeout      = 0x4000,
 471         SWInt           = 0x0100,
 472         TxDescUnavail   = 0x0080,
 473         RxFIFOOver      = 0x0040,
 474         LinkChg         = 0x0020,
 475         RxOverflow      = 0x0010,
 476         TxErr           = 0x0008,
 477         TxOK            = 0x0004,
 478         RxErr           = 0x0002,
 479         RxOK            = 0x0001,
 480
 481         /* RxStatusDesc */
 482         RxBOVF  = (1 << 24),
 483         RxFOVF  = (1 << 23),
 484         RxRWT   = (1 << 22),
 485         RxRES   = (1 << 21),
 486         RxRUNT  = (1 << 20),
 487         RxCRC   = (1 << 19),
 488
 489         /* ChipCmdBits */
 490         StopReq         = 0x80,
 491         CmdReset        = 0x10,
 492         CmdRxEnb        = 0x08,
 493         CmdTxEnb        = 0x04,
 494         RxBufEmpty      = 0x01,
 495
 496         /* TXPoll register p.5 */
 497         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 498         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 499         FSWInt          = 0x01,         /* Forced software interrupt */
 500
 501         /* Cfg9346Bits */
 502         Cfg9346_Lock    = 0x00,
 503         Cfg9346_Unlock  = 0xc0,
 504
 505         /* rx_mode_bits */
 506         AcceptErr       = 0x20,
 507         AcceptRunt      = 0x10,
 508         AcceptBroadcast = 0x08,
 509         AcceptMulticast = 0x04,
 510         AcceptMyPhys    = 0x02,
 511         AcceptAllPhys   = 0x01,
 512 #define RX_CONFIG_ACCEPT_MASK           0x3f
 513
 514         /* TxConfigBits */
 515         TxInterFrameGapShift = 24,
 516         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 517
 518         /* Config1 register p.24 */
 519         LEDS1           = (1 << 7),
 520         LEDS0           = (1 << 6),
 521         Speed_down      = (1 << 4),
 522         MEMMAP          = (1 << 3),
 523         IOMAP           = (1 << 2),
 524         VPD             = (1 << 1),
 525         PMEnable        = (1 << 0),     /* Power Management Enable */
 526
 527         /* Config2 register p. 25 */
 528         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 529         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 530         PCI_Clock_66MHz = 0x01,
 531         PCI_Clock_33MHz = 0x00,
 532
 533         /* Config3 register p.25 */
 534         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 535         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 536         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 537         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 538         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 539
 540         /* Config4 register */
 541         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 542
 543         /* Config5 register p.27 */
 544         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 545         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 546         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 547         Spi_en          = (1 << 3),
 548         LanWake         = (1 << 1),     /* LanWake enable/disable */
 549         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 550         ASPM_en         = (1 << 0),     /* ASPM enable */
 551
 552         /* CPlusCmd p.31 */
 553         EnableBist      = (1 << 15),    // 8168 8101
 554         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 555         Normal_mode     = (1 << 13),    // unused
 556         Force_half_dup  = (1 << 12),    // 8168 8101
 557         Force_rxflow_en = (1 << 11),    // 8168 8101
 558         Force_txflow_en = (1 << 10),    // 8168 8101
 559         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 560         ASF             = (1 << 8),     // 8168 8101
 561         PktCntrDisable  = (1 << 7),     // 8168 8101
 562         Mac_dbgo_sel    = 0x001c,       // 8168
 563         RxVlan          = (1 << 6),
 564         RxChkSum        = (1 << 5),
 565         PCIDAC          = (1 << 4),
 566         PCIMulRW        = (1 << 3),
 567 #define INTT_MASK       GENMASK(1, 0)
 568         INTT_0          = 0x0000,       // 8168
 569         INTT_1          = 0x0001,       // 8168
 570         INTT_2          = 0x0002,       // 8168
 571         INTT_3          = 0x0003,       // 8168
 572
 573         /* rtl8169_PHYstatus */
 574         TBI_Enable      = 0x80,
 575         TxFlowCtrl      = 0x40,
 576         RxFlowCtrl      = 0x20,
 577         _1000bpsF       = 0x10,
 578         _100bps         = 0x08,
 579         _10bps          = 0x04,
 580         LinkStatus      = 0x02,
 581         FullDup         = 0x01,
 582
 583         /* _TBICSRBit */
 584         TBILinkOK       = 0x02000000,
 585
 586         /* ResetCounterCommand */
 587         CounterReset    = 0x1,
 588
 589         /* DumpCounterCommand */
 590         CounterDump     = 0x8,
 591
 592         /* magic enable v2 */
 593         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 594 };
 595
 596 enum rtl_desc_bit {
 597         /* First doubleword. */
 598         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 599         RingEnd         = (1 << 30), /* End of descriptor ring */
 600         FirstFrag       = (1 << 29), /* First segment of a packet */
 601         LastFrag        = (1 << 28), /* Final segment of a packet */
 602 };
 603
 604 /* Generic case. */
 605 enum rtl_tx_desc_bit {
 606         /* First doubleword. */
 607         TD_LSO          = (1 << 27),            /* Large Send Offload */
 608 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 609
 610         /* Second doubleword. */
 611         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 612 };
 613
 614 /* 8169, 8168b and 810x except 8102e. */
 615 enum rtl_tx_desc_bit_0 {
 616         /* First doubleword. */
 617 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 618         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 619         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 620         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 621 };
 622
 623 /* 8102e, 8168c and beyond. */
 624 enum rtl_tx_desc_bit_1 {
 625         /* First doubleword. */
 626         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 627         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 628 #define GTTCPHO_SHIFT                   18
 629 #define GTTCPHO_MAX                     0x7fU
 630
 631         /* Second doubleword. */
 632 #define TCPHO_SHIFT                     18
 633 #define TCPHO_MAX                       0x3ffU
 634 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 635         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 636         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 637         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 638         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 639 };
 640
 641 enum rtl_rx_desc_bit {
 642         /* Rx private */
 643         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 644         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 645
 646 #define RxProtoUDP      (PID1)
 647 #define RxProtoTCP      (PID0)
 648 #define RxProtoIP       (PID1 | PID0)
 649 #define RxProtoMask     RxProtoIP
 650
 651         IPFail          = (1 << 16), /* IP checksum failed */
 652         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 653         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 654         RxVlanTag       = (1 << 16), /* VLAN tag available */
 655 };
 656
 657 #define RsvdMask        0x3fffc000
 658 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 659
 660 struct TxDesc {
 661         __le32 opts1;
 662         __le32 opts2;
 663         __le64 addr;
 664 };
 665
 666 struct RxDesc {
 667         __le32 opts1;
 668         __le32 opts2;
 669         __le64 addr;
 670 };
 671
 672 struct ring_info {
 673         struct sk_buff  *skb;
 674         u32             len;
 675         u8              __pad[sizeof(void *) - sizeof(u32)];
 676 };
 677
 678 struct rtl8169_counters {
 679         __le64  tx_packets;
 680         __le64  rx_packets;
 681         __le64  tx_errors;
 682         __le32  rx_errors;
 683         __le16  rx_missed;
 684         __le16  align_errors;
 685         __le32  tx_one_collision;
 686         __le32  tx_multi_collision;
 687         __le64  rx_unicast;
 688         __le64  rx_broadcast;
 689         __le32  rx_multicast;
 690         __le16  tx_aborted;
 691         __le16  tx_underun;
 692 };
 693
 694 struct rtl8169_tc_offsets {
 695         bool    inited;
 696         __le64  tx_errors;
 697         __le32  tx_multi_collision;
 698         __le16  tx_aborted;
 699 };
 700
 701 enum rtl_flag {
 702         RTL_FLAG_TASK_ENABLED,
 703         RTL_FLAG_TASK_SLOW_PENDING,
 704         RTL_FLAG_TASK_RESET_PENDING,
 705         RTL_FLAG_MAX
 706 };
 707
 708 struct rtl8169_stats {
 709         u64                     packets;
 710         u64                     bytes;
 711         struct u64_stats_sync   syncp;
 712 };
 713
 714 struct rtl8169_private {
 715         void __iomem *mmio_addr;        /* memory map physical address */
 716         struct pci_dev *pci_dev;
 717         struct net_device *dev;
 718         struct napi_struct napi;
 719         u32 msg_enable;
 720         u16 mac_version;
 721         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 722         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 723         u32 dirty_tx;
 724         struct rtl8169_stats rx_stats;
 725         struct rtl8169_stats tx_stats;
 726         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 727         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 728         dma_addr_t TxPhyAddr;
 729         dma_addr_t RxPhyAddr;
 730         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 731         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 732         u16 cp_cmd;
 733
 734         u16 event_slow;
 735         const struct rtl_coalesce_info *coalesce_info;
 736
 737         struct mdio_ops {
 738                 void (*write)(struct rtl8169_private *, int, int);
 739                 int (*read)(struct rtl8169_private *, int);
 740         } mdio_ops;
 741
 742         struct jumbo_ops {
 743                 void (*enable)(struct rtl8169_private *);
 744                 void (*disable)(struct rtl8169_private *);
 745         } jumbo_ops;
 746
 747         void (*hw_start)(struct rtl8169_private *tp);
 748         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 749
 750         struct {
 751                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 752                 struct mutex mutex;
 753                 struct work_struct work;
 754         } wk;
 755
 756         unsigned supports_gmii:1;
 757         struct mii_bus *mii_bus;
 758         dma_addr_t counters_phys_addr;
 759         struct rtl8169_counters *counters;
 760         struct rtl8169_tc_offsets tc_offset;
 761         u32 saved_wolopts;
 762
 763         struct rtl_fw {
 764                 const struct firmware *fw;
 765
 766 #define RTL_VER_SIZE            32
 767
 768                 char version[RTL_VER_SIZE];
 769
 770                 struct rtl_fw_phy_action {
 771                         __le32 *code;
 772                         size_t size;
 773                 } phy_action;
 774         } *rtl_fw;
 775 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 776
 777         u32 ocp_base;
 778 };
 779
 780 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 781 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 782 module_param(use_dac, int, 0);
 783 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 784 module_param_named(debug, debug.msg_enable, int, 0);
 785 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 786 MODULE_LICENSE("GPL");
 787 MODULE_VERSION(RTL8169_VERSION);
 788 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 789 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 790 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 791 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 792 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 793 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 794 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 795 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 796 MODULE_FIRMWARE(FIRMWARE_8402_1);
 797 MODULE_FIRMWARE(FIRMWARE_8411_1);
 798 MODULE_FIRMWARE(FIRMWARE_8411_2);
 799 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 800 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 801 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 802 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 803 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 804 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 805 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 806 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 807
 808 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 809 {
 810         return &tp->pci_dev->dev;
 811 }
 812
 813 static void rtl_lock_work(struct rtl8169_private *tp)
 814 {
 815         mutex_lock(&tp->wk.mutex);
 816 }
 817
 818 static void rtl_unlock_work(struct rtl8169_private *tp)
 819 {
 820         mutex_unlock(&tp->wk.mutex);
 821 }
 822
 823 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 824 {
 825         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 826                                            PCI_EXP_DEVCTL_READRQ, force);
 827 }
 828
 829 struct rtl_cond {
 830         bool (*check)(struct rtl8169_private *);
 831         const char *msg;
 832 };
 833
 834 static void rtl_udelay(unsigned int d)
 835 {
 836         udelay(d);
 837 }
 838
 839 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 840                           void (*delay)(unsigned int), unsigned int d, int n,
 841                           bool high)
 842 {
 843         int i;
 844
 845         for (i = 0; i < n; i++) {
 846                 delay(d);
 847                 if (c->check(tp) == high)
 848                         return true;
 849         }
 850         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 851                   c->msg, !high, n, d);
 852         return false;
 853 }
 854
 855 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 856                                       const struct rtl_cond *c,
 857                                       unsigned int d, int n)
 858 {
 859         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 860 }
 861
 862 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 863                                      const struct rtl_cond *c,
 864                                      unsigned int d, int n)
 865 {
 866         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 867 }
 868
 869 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 870                                       const struct rtl_cond *c,
 871                                       unsigned int d, int n)
 872 {
 873         return rtl_loop_wait(tp, c, msleep, d, n, true);
 874 }
 875
 876 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 877                                      const struct rtl_cond *c,
 878                                      unsigned int d, int n)
 879 {
 880         return rtl_loop_wait(tp, c, msleep, d, n, false);
 881 }
 882
 883 #define DECLARE_RTL_COND(name)                          \
 884 static bool name ## _check(struct rtl8169_private *);   \
 885                                                         \
 886 static const struct rtl_cond name = {                   \
 887         .check  = name ## _check,                       \
 888         .msg    = #name                                 \
 889 };                                                      \
 890                                                         \
 891 static bool name ## _check(struct rtl8169_private *tp)
 892
 893 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 894 {
 895         if (reg & 0xffff0001) {
 896                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 897                 return true;
 898         }
 899         return false;
 900 }
 901
 902 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 903 {
 904         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 905 }
 906
 907 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 908 {
 909         if (rtl_ocp_reg_failure(tp, reg))
 910                 return;
 911
 912         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 913
 914         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 915 }
 916
 917 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 918 {
 919         if (rtl_ocp_reg_failure(tp, reg))
 920                 return 0;
 921
 922         RTL_W32(tp, GPHY_OCP, reg << 15);
 923
 924         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 925                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 926 }
 927
 928 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 929 {
 930         if (rtl_ocp_reg_failure(tp, reg))
 931                 return;
 932
 933         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 934 }
 935
 936 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 937 {
 938         if (rtl_ocp_reg_failure(tp, reg))
 939                 return 0;
 940
 941         RTL_W32(tp, OCPDR, reg << 15);
 942
 943         return RTL_R32(tp, OCPDR);
 944 }
 945
 946 #define OCP_STD_PHY_BASE        0xa400
 947
 948 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 949 {
 950         if (reg == 0x1f) {
 951                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 952                 return;
 953         }
 954
 955         if (tp->ocp_base != OCP_STD_PHY_BASE)
 956                 reg -= 0x10;
 957
 958         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 959 }
 960
 961 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 962 {
 963         if (tp->ocp_base != OCP_STD_PHY_BASE)
 964                 reg -= 0x10;
 965
 966         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 967 }
 968
 969 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 970 {
 971         if (reg == 0x1f) {
 972                 tp->ocp_base = value << 4;
 973                 return;
 974         }
 975
 976         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 977 }
 978
 979 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 980 {
 981         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 982 }
 983
 984 DECLARE_RTL_COND(rtl_phyar_cond)
 985 {
 986         return RTL_R32(tp, PHYAR) & 0x80000000;
 987 }
 988
 989 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 990 {
 991         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 992
 993         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 994         /*
 995          * According to hardware specs a 20us delay is required after write
 996          * complete indication, but before sending next command.
 997          */
 998         udelay(20);
 999 }
1000
1001 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1002 {
1003         int value;
1004
1005         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1006
1007         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1008                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1009
1010         /*
1011          * According to hardware specs a 20us delay is required after read
1012          * complete indication, but before sending next command.
1013          */
1014         udelay(20);
1015
1016         return value;
1017 }
1018
1019 DECLARE_RTL_COND(rtl_ocpar_cond)
1020 {
1021         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1022 }
1023
1024 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1025 {
1026         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1027         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1028         RTL_W32(tp, EPHY_RXER_NUM, 0);
1029
1030         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1031 }
1032
1033 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1034 {
1035         r8168dp_1_mdio_access(tp, reg,
1036                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1037 }
1038
1039 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1040 {
1041         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1042
1043         mdelay(1);
1044         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1045         RTL_W32(tp, EPHY_RXER_NUM, 0);
1046
1047         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1048                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1049 }
1050
1051 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1052
1053 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1054 {
1055         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1056 }
1057
1058 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1059 {
1060         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1061 }
1062
1063 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1064 {
1065         r8168dp_2_mdio_start(tp);
1066
1067         r8169_mdio_write(tp, reg, value);
1068
1069         r8168dp_2_mdio_stop(tp);
1070 }
1071
1072 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1073 {
1074         int value;
1075
1076         r8168dp_2_mdio_start(tp);
1077
1078         value = r8169_mdio_read(tp, reg);
1079
1080         r8168dp_2_mdio_stop(tp);
1081
1082         return value;
1083 }
1084
1085 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1086 {
1087         tp->mdio_ops.write(tp, location, val);
1088 }
1089
1090 static int rtl_readphy(struct rtl8169_private *tp, int location)
1091 {
1092         return tp->mdio_ops.read(tp, location);
1093 }
1094
1095 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1096 {
1097         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1098 }
1099
1100 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1101 {
1102         int val;
1103
1104         val = rtl_readphy(tp, reg_addr);
1105         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1106 }
1107
1108 DECLARE_RTL_COND(rtl_ephyar_cond)
1109 {
1110         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1111 }
1112
1113 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1114 {
1115         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1116                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1117
1118         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1119
1120         udelay(10);
1121 }
1122
1123 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1124 {
1125         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1126
1127         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1128                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1129 }
1130
1131 DECLARE_RTL_COND(rtl_eriar_cond)
1132 {
1133         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1134 }
1135
1136 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1137                           u32 val, int type)
1138 {
1139         BUG_ON((addr & 3) || (mask == 0));
1140         RTL_W32(tp, ERIDR, val);
1141         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1142
1143         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1144 }
1145
1146 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1147 {
1148         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1149
1150         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1151                 RTL_R32(tp, ERIDR) : ~0;
1152 }
1153
1154 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1155                          u32 m, int type)
1156 {
1157         u32 val;
1158
1159         val = rtl_eri_read(tp, addr, type);
1160         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1161 }
1162
1163 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1164 {
1165         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1166         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1167                 RTL_R32(tp, OCPDR) : ~0;
1168 }
1169
1170 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1171 {
1172         return rtl_eri_read(tp, reg, ERIAR_OOB);
1173 }
1174
1175 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1176 {
1177         switch (tp->mac_version) {
1178         case RTL_GIGA_MAC_VER_27:
1179         case RTL_GIGA_MAC_VER_28:
1180         case RTL_GIGA_MAC_VER_31:
1181                 return r8168dp_ocp_read(tp, mask, reg);
1182         case RTL_GIGA_MAC_VER_49:
1183         case RTL_GIGA_MAC_VER_50:
1184         case RTL_GIGA_MAC_VER_51:
1185                 return r8168ep_ocp_read(tp, mask, reg);
1186         default:
1187                 BUG();
1188                 return ~0;
1189         }
1190 }
1191
1192 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1193                               u32 data)
1194 {
1195         RTL_W32(tp, OCPDR, data);
1196         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1197         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1198 }
1199
1200 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1201                               u32 data)
1202 {
1203         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1204                       data, ERIAR_OOB);
1205 }
1206
1207 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1208 {
1209         switch (tp->mac_version) {
1210         case RTL_GIGA_MAC_VER_27:
1211         case RTL_GIGA_MAC_VER_28:
1212         case RTL_GIGA_MAC_VER_31:
1213                 r8168dp_ocp_write(tp, mask, reg, data);
1214                 break;
1215         case RTL_GIGA_MAC_VER_49:
1216         case RTL_GIGA_MAC_VER_50:
1217         case RTL_GIGA_MAC_VER_51:
1218                 r8168ep_ocp_write(tp, mask, reg, data);
1219                 break;
1220         default:
1221                 BUG();
1222                 break;
1223         }
1224 }
1225
1226 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1227 {
1228         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1229
1230         ocp_write(tp, 0x1, 0x30, 0x00000001);
1231 }
1232
1233 #define OOB_CMD_RESET           0x00
1234 #define OOB_CMD_DRIVER_START    0x05
1235 #define OOB_CMD_DRIVER_STOP     0x06
1236
1237 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1238 {
1239         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1240 }
1241
1242 DECLARE_RTL_COND(rtl_ocp_read_cond)
1243 {
1244         u16 reg;
1245
1246         reg = rtl8168_get_ocp_reg(tp);
1247
1248         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1249 }
1250
1251 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1252 {
1253         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1254 }
1255
1256 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1257 {
1258         return RTL_R8(tp, IBISR0) & 0x20;
1259 }
1260
1261 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1262 {
1263         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1264         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1265         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1266         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1267 }
1268
1269 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1270 {
1271         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1272         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1273 }
1274
1275 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1276 {
1277         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1278         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1279         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1280 }
1281
1282 static void rtl8168_driver_start(struct rtl8169_private *tp)
1283 {
1284         switch (tp->mac_version) {
1285         case RTL_GIGA_MAC_VER_27:
1286         case RTL_GIGA_MAC_VER_28:
1287         case RTL_GIGA_MAC_VER_31:
1288                 rtl8168dp_driver_start(tp);
1289                 break;
1290         case RTL_GIGA_MAC_VER_49:
1291         case RTL_GIGA_MAC_VER_50:
1292         case RTL_GIGA_MAC_VER_51:
1293                 rtl8168ep_driver_start(tp);
1294                 break;
1295         default:
1296                 BUG();
1297                 break;
1298         }
1299 }
1300
1301 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1302 {
1303         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1304         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1305 }
1306
1307 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1308 {
1309         rtl8168ep_stop_cmac(tp);
1310         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1311         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1312         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1313 }
1314
1315 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1316 {
1317         switch (tp->mac_version) {
1318         case RTL_GIGA_MAC_VER_27:
1319         case RTL_GIGA_MAC_VER_28:
1320         case RTL_GIGA_MAC_VER_31:
1321                 rtl8168dp_driver_stop(tp);
1322                 break;
1323         case RTL_GIGA_MAC_VER_49:
1324         case RTL_GIGA_MAC_VER_50:
1325         case RTL_GIGA_MAC_VER_51:
1326                 rtl8168ep_driver_stop(tp);
1327                 break;
1328         default:
1329                 BUG();
1330                 break;
1331         }
1332 }
1333
1334 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1335 {
1336         u16 reg = rtl8168_get_ocp_reg(tp);
1337
1338         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1339 }
1340
1341 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1342 {
1343         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1344 }
1345
1346 static bool r8168_check_dash(struct rtl8169_private *tp)
1347 {
1348         switch (tp->mac_version) {
1349         case RTL_GIGA_MAC_VER_27:
1350         case RTL_GIGA_MAC_VER_28:
1351         case RTL_GIGA_MAC_VER_31:
1352                 return r8168dp_check_dash(tp);
1353         case RTL_GIGA_MAC_VER_49:
1354         case RTL_GIGA_MAC_VER_50:
1355         case RTL_GIGA_MAC_VER_51:
1356                 return r8168ep_check_dash(tp);
1357         default:
1358                 return false;
1359         }
1360 }
1361
1362 struct exgmac_reg {
1363         u16 addr;
1364         u16 mask;
1365         u32 val;
1366 };
1367
1368 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1369                                    const struct exgmac_reg *r, int len)
1370 {
1371         while (len-- > 0) {
1372                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1373                 r++;
1374         }
1375 }
1376
1377 DECLARE_RTL_COND(rtl_efusear_cond)
1378 {
1379         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1380 }
1381
1382 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1383 {
1384         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1385
1386         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1387                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1388 }
1389
1390 static u16 rtl_get_events(struct rtl8169_private *tp)
1391 {
1392         return RTL_R16(tp, IntrStatus);
1393 }
1394
1395 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1396 {
1397         RTL_W16(tp, IntrStatus, bits);
1398         mmiowb();
1399 }
1400
1401 static void rtl_irq_disable(struct rtl8169_private *tp)
1402 {
1403         RTL_W16(tp, IntrMask, 0);
1404         mmiowb();
1405 }
1406
1407 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1408 {
1409         RTL_W16(tp, IntrMask, bits);
1410 }
1411
1412 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1413 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1414 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1415
1416 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1417 {
1418         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1419 }
1420
1421 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1422 {
1423         rtl_irq_disable(tp);
1424         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1425         RTL_R8(tp, ChipCmd);
1426 }
1427
1428 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1429 {
1430         struct net_device *dev = tp->dev;
1431
1432         if (!netif_running(dev))
1433                 return;
1434
1435         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1436             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1437                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1438                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1439                                       ERIAR_EXGMAC);
1440                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1441                                       ERIAR_EXGMAC);
1442                 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1443                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1444                                       ERIAR_EXGMAC);
1445                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1446                                       ERIAR_EXGMAC);
1447                 } else {
1448                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1449                                       ERIAR_EXGMAC);
1450                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1451                                       ERIAR_EXGMAC);
1452                 }
1453                 /* Reset packet filter */
1454                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1455                              ERIAR_EXGMAC);
1456                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1457                              ERIAR_EXGMAC);
1458         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1459                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1460                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1461                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1462                                       ERIAR_EXGMAC);
1463                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1464                                       ERIAR_EXGMAC);
1465                 } else {
1466                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1467                                       ERIAR_EXGMAC);
1468                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1469                                       ERIAR_EXGMAC);
1470                 }
1471         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1472                 if (RTL_R8(tp, PHYstatus) & _10bps) {
1473                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1474                                       ERIAR_EXGMAC);
1475                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1476                                       ERIAR_EXGMAC);
1477                 } else {
1478                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1479                                       ERIAR_EXGMAC);
1480                 }
1481         }
1482 }
1483
1484 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1485
1486 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1487 {
1488         u8 options;
1489         u32 wolopts = 0;
1490
1491         options = RTL_R8(tp, Config1);
1492         if (!(options & PMEnable))
1493                 return 0;
1494
1495         options = RTL_R8(tp, Config3);
1496         if (options & LinkUp)
1497                 wolopts |= WAKE_PHY;
1498         switch (tp->mac_version) {
1499         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1500         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1501                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1502                         wolopts |= WAKE_MAGIC;
1503                 break;
1504         default:
1505                 if (options & MagicPacket)
1506                         wolopts |= WAKE_MAGIC;
1507                 break;
1508         }
1509
1510         options = RTL_R8(tp, Config5);
1511         if (options & UWF)
1512                 wolopts |= WAKE_UCAST;
1513         if (options & BWF)
1514                 wolopts |= WAKE_BCAST;
1515         if (options & MWF)
1516                 wolopts |= WAKE_MCAST;
1517
1518         return wolopts;
1519 }
1520
1521 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1522 {
1523         struct rtl8169_private *tp = netdev_priv(dev);
1524
1525         rtl_lock_work(tp);
1526         wol->supported = WAKE_ANY;
1527         wol->wolopts = tp->saved_wolopts;
1528         rtl_unlock_work(tp);
1529 }
1530
1531 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1532 {
1533         unsigned int i, tmp;
1534         static const struct {
1535                 u32 opt;
1536                 u16 reg;
1537                 u8  mask;
1538         } cfg[] = {
1539                 { WAKE_PHY,   Config3, LinkUp },
1540                 { WAKE_UCAST, Config5, UWF },
1541                 { WAKE_BCAST, Config5, BWF },
1542                 { WAKE_MCAST, Config5, MWF },
1543                 { WAKE_ANY,   Config5, LanWake },
1544                 { WAKE_MAGIC, Config3, MagicPacket }
1545         };
1546         u8 options;
1547
1548         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1549
1550         switch (tp->mac_version) {
1551         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1552         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1553                 tmp = ARRAY_SIZE(cfg) - 1;
1554                 if (wolopts & WAKE_MAGIC)
1555                         rtl_w0w1_eri(tp,
1556                                      0x0dc,
1557                                      ERIAR_MASK_0100,
1558                                      MagicPacket_v2,
1559                                      0x0000,
1560                                      ERIAR_EXGMAC);
1561                 else
1562                         rtl_w0w1_eri(tp,
1563                                      0x0dc,
1564                                      ERIAR_MASK_0100,
1565                                      0x0000,
1566                                      MagicPacket_v2,
1567                                      ERIAR_EXGMAC);
1568                 break;
1569         default:
1570                 tmp = ARRAY_SIZE(cfg);
1571                 break;
1572         }
1573
1574         for (i = 0; i < tmp; i++) {
1575                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1576                 if (wolopts & cfg[i].opt)
1577                         options |= cfg[i].mask;
1578                 RTL_W8(tp, cfg[i].reg, options);
1579         }
1580
1581         switch (tp->mac_version) {
1582         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1583                 options = RTL_R8(tp, Config1) & ~PMEnable;
1584                 if (wolopts)
1585                         options |= PMEnable;
1586                 RTL_W8(tp, Config1, options);
1587                 break;
1588         default:
1589                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1590                 if (wolopts)
1591                         options |= PME_SIGNAL;
1592                 RTL_W8(tp, Config2, options);
1593                 break;
1594         }
1595
1596         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1597 }
1598
1599 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1600 {
1601         struct rtl8169_private *tp = netdev_priv(dev);
1602         struct device *d = tp_to_dev(tp);
1603
1604         if (wol->wolopts & ~WAKE_ANY)
1605                 return -EINVAL;
1606
1607         pm_runtime_get_noresume(d);
1608
1609         rtl_lock_work(tp);
1610
1611         tp->saved_wolopts = wol->wolopts;
1612
1613         if (pm_runtime_active(d))
1614                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1615
1616         rtl_unlock_work(tp);
1617
1618         device_set_wakeup_enable(d, tp->saved_wolopts);
1619
1620         pm_runtime_put_noidle(d);
1621
1622         return 0;
1623 }
1624
1625 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1626 {
1627         return rtl_chip_infos[tp->mac_version].fw_name;
1628 }
1629
1630 static void rtl8169_get_drvinfo(struct net_device *dev,
1631                                 struct ethtool_drvinfo *info)
1632 {
1633         struct rtl8169_private *tp = netdev_priv(dev);
1634         struct rtl_fw *rtl_fw = tp->rtl_fw;
1635
1636         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1637         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1638         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1639         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1640         if (!IS_ERR_OR_NULL(rtl_fw))
1641                 strlcpy(info->fw_version, rtl_fw->version,
1642                         sizeof(info->fw_version));
1643 }
1644
1645 static int rtl8169_get_regs_len(struct net_device *dev)
1646 {
1647         return R8169_REGS_SIZE;
1648 }
1649
1650 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1651         netdev_features_t features)
1652 {
1653         struct rtl8169_private *tp = netdev_priv(dev);
1654
1655         if (dev->mtu > TD_MSS_MAX)
1656                 features &= ~NETIF_F_ALL_TSO;
1657
1658         if (dev->mtu > JUMBO_1K &&
1659             tp->mac_version > RTL_GIGA_MAC_VER_06)
1660                 features &= ~NETIF_F_IP_CSUM;
1661
1662         return features;
1663 }
1664
1665 static int rtl8169_set_features(struct net_device *dev,
1666                                 netdev_features_t features)
1667 {
1668         struct rtl8169_private *tp = netdev_priv(dev);
1669         u32 rx_config;
1670
1671         rtl_lock_work(tp);
1672
1673         rx_config = RTL_R32(tp, RxConfig);
1674         if (features & NETIF_F_RXALL)
1675                 rx_config |= (AcceptErr | AcceptRunt);
1676         else
1677                 rx_config &= ~(AcceptErr | AcceptRunt);
1678
1679         RTL_W32(tp, RxConfig, rx_config);
1680
1681         if (features & NETIF_F_RXCSUM)
1682                 tp->cp_cmd |= RxChkSum;
1683         else
1684                 tp->cp_cmd &= ~RxChkSum;
1685
1686         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1687                 tp->cp_cmd |= RxVlan;
1688         else
1689                 tp->cp_cmd &= ~RxVlan;
1690
1691         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1692         RTL_R16(tp, CPlusCmd);
1693
1694         rtl_unlock_work(tp);
1695
1696         return 0;
1697 }
1698
1699 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1700 {
1701         return (skb_vlan_tag_present(skb)) ?
1702                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1703 }
1704
1705 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1706 {
1707         u32 opts2 = le32_to_cpu(desc->opts2);
1708
1709         if (opts2 & RxVlanTag)
1710                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1711 }
1712
1713 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1714                              void *p)
1715 {
1716         struct rtl8169_private *tp = netdev_priv(dev);
1717         u32 __iomem *data = tp->mmio_addr;
1718         u32 *dw = p;
1719         int i;
1720
1721         rtl_lock_work(tp);
1722         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1723                 memcpy_fromio(dw++, data++, 4);
1724         rtl_unlock_work(tp);
1725 }
1726
1727 static u32 rtl8169_get_msglevel(struct net_device *dev)
1728 {
1729         struct rtl8169_private *tp = netdev_priv(dev);
1730
1731         return tp->msg_enable;
1732 }
1733
1734 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1735 {
1736         struct rtl8169_private *tp = netdev_priv(dev);
1737
1738         tp->msg_enable = value;
1739 }
1740
1741 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1742         "tx_packets",
1743         "rx_packets",
1744         "tx_errors",
1745         "rx_errors",
1746         "rx_missed",
1747         "align_errors",
1748         "tx_single_collisions",
1749         "tx_multi_collisions",
1750         "unicast",
1751         "broadcast",
1752         "multicast",
1753         "tx_aborted",
1754         "tx_underrun",
1755 };
1756
1757 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1758 {
1759         switch (sset) {
1760         case ETH_SS_STATS:
1761                 return ARRAY_SIZE(rtl8169_gstrings);
1762         default:
1763                 return -EOPNOTSUPP;
1764         }
1765 }
1766
1767 DECLARE_RTL_COND(rtl_counters_cond)
1768 {
1769         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1770 }
1771
1772 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1773 {
1774         dma_addr_t paddr = tp->counters_phys_addr;
1775         u32 cmd;
1776
1777         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1778         RTL_R32(tp, CounterAddrHigh);
1779         cmd = (u64)paddr & DMA_BIT_MASK(32);
1780         RTL_W32(tp, CounterAddrLow, cmd);
1781         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1782
1783         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1784 }
1785
1786 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1787 {
1788         /*
1789          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1790          * tally counters.
1791          */
1792         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1793                 return true;
1794
1795         return rtl8169_do_counters(tp, CounterReset);
1796 }
1797
1798 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1799 {
1800         /*
1801          * Some chips are unable to dump tally counters when the receiver
1802          * is disabled.
1803          */
1804         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1805                 return true;
1806
1807         return rtl8169_do_counters(tp, CounterDump);
1808 }
1809
1810 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1811 {
1812         struct rtl8169_counters *counters = tp->counters;
1813         bool ret = false;
1814
1815         /*
1816          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1817          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1818          * reset by a power cycle, while the counter values collected by the
1819          * driver are reset at every driver unload/load cycle.
1820          *
1821          * To make sure the HW values returned by @get_stats64 match the SW
1822          * values, we collect the initial values at first open(*) and use them
1823          * as offsets to normalize the values returned by @get_stats64.
1824          *
1825          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1826          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1827          * set at open time by rtl_hw_start.
1828          */
1829
1830         if (tp->tc_offset.inited)
1831                 return true;
1832
1833         /* If both, reset and update fail, propagate to caller. */
1834         if (rtl8169_reset_counters(tp))
1835                 ret = true;
1836
1837         if (rtl8169_update_counters(tp))
1838                 ret = true;
1839
1840         tp->tc_offset.tx_errors = counters->tx_errors;
1841         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1842         tp->tc_offset.tx_aborted = counters->tx_aborted;
1843         tp->tc_offset.inited = true;
1844
1845         return ret;
1846 }
1847
1848 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1849                                       struct ethtool_stats *stats, u64 *data)
1850 {
1851         struct rtl8169_private *tp = netdev_priv(dev);
1852         struct device *d = tp_to_dev(tp);
1853         struct rtl8169_counters *counters = tp->counters;
1854
1855         ASSERT_RTNL();
1856
1857         pm_runtime_get_noresume(d);
1858
1859         if (pm_runtime_active(d))
1860                 rtl8169_update_counters(tp);
1861
1862         pm_runtime_put_noidle(d);
1863
1864         data[0] = le64_to_cpu(counters->tx_packets);
1865         data[1] = le64_to_cpu(counters->rx_packets);
1866         data[2] = le64_to_cpu(counters->tx_errors);
1867         data[3] = le32_to_cpu(counters->rx_errors);
1868         data[4] = le16_to_cpu(counters->rx_missed);
1869         data[5] = le16_to_cpu(counters->align_errors);
1870         data[6] = le32_to_cpu(counters->tx_one_collision);
1871         data[7] = le32_to_cpu(counters->tx_multi_collision);
1872         data[8] = le64_to_cpu(counters->rx_unicast);
1873         data[9] = le64_to_cpu(counters->rx_broadcast);
1874         data[10] = le32_to_cpu(counters->rx_multicast);
1875         data[11] = le16_to_cpu(counters->tx_aborted);
1876         data[12] = le16_to_cpu(counters->tx_underun);
1877 }
1878
1879 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1880 {
1881         switch(stringset) {
1882         case ETH_SS_STATS:
1883                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1884                 break;
1885         }
1886 }
1887
1888 /*
1889  * Interrupt coalescing
1890  *
1891  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1892  * >     8169, 8168 and 810x line of chipsets
1893  *
1894  * 8169, 8168, and 8136(810x) serial chipsets support it.
1895  *
1896  * > 2 - the Tx timer unit at gigabit speed
1897  *
1898  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1899  * (0xe0) bit 1 and bit 0.
1900  *
1901  * For 8169
1902  * bit[1:0] \ speed        1000M           100M            10M
1903  * 0 0                     320ns           2.56us          40.96us
1904  * 0 1                     2.56us          20.48us         327.7us
1905  * 1 0                     5.12us          40.96us         655.4us
1906  * 1 1                     10.24us         81.92us         1.31ms
1907  *
1908  * For the other
1909  * bit[1:0] \ speed        1000M           100M            10M
1910  * 0 0                     5us             2.56us          40.96us
1911  * 0 1                     40us            20.48us         327.7us
1912  * 1 0                     80us            40.96us         655.4us
1913  * 1 1                     160us           81.92us         1.31ms
1914  */
1915
1916 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1917 struct rtl_coalesce_scale {
1918         /* Rx / Tx */
1919         u32 nsecs[2];
1920 };
1921
1922 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1923 struct rtl_coalesce_info {
1924         u32 speed;
1925         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1926 };
1927
1928 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1929 #define rxtx_x1822(r, t) {              \
1930         {{(r),          (t)}},          \
1931         {{(r)*8,        (t)*8}},        \
1932         {{(r)*8*2,      (t)*8*2}},      \
1933         {{(r)*8*2*2,    (t)*8*2*2}},    \
1934 }
1935 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1936         /* speed        delays:     rx00   tx00 */
1937         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1938         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1939         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1940         { 0 },
1941 };
1942
1943 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1944         /* speed        delays:     rx00   tx00 */
1945         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1946         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1947         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1948         { 0 },
1949 };
1950 #undef rxtx_x1822
1951
1952 /* get rx/tx scale vector corresponding to current speed */
1953 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1954 {
1955         struct rtl8169_private *tp = netdev_priv(dev);
1956         struct ethtool_link_ksettings ecmd;
1957         const struct rtl_coalesce_info *ci;
1958         int rc;
1959
1960         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1961         if (rc < 0)
1962                 return ERR_PTR(rc);
1963
1964         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1965                 if (ecmd.base.speed == ci->speed) {
1966                         return ci;
1967                 }
1968         }
1969
1970         return ERR_PTR(-ELNRNG);
1971 }
1972
1973 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1974 {
1975         struct rtl8169_private *tp = netdev_priv(dev);
1976         const struct rtl_coalesce_info *ci;
1977         const struct rtl_coalesce_scale *scale;
1978         struct {
1979                 u32 *max_frames;
1980                 u32 *usecs;
1981         } coal_settings [] = {
1982                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1983                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1984         }, *p = coal_settings;
1985         int i;
1986         u16 w;
1987
1988         memset(ec, 0, sizeof(*ec));
1989
1990         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1991         ci = rtl_coalesce_info(dev);
1992         if (IS_ERR(ci))
1993                 return PTR_ERR(ci);
1994
1995         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1996
1997         /* read IntrMitigate and adjust according to scale */
1998         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1999                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2000                 w >>= RTL_COALESCE_SHIFT;
2001                 *p->usecs = w & RTL_COALESCE_MASK;
2002         }
2003
2004         for (i = 0; i < 2; i++) {
2005                 p = coal_settings + i;
2006                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2007
2008                 /*
2009                  * ethtool_coalesce says it is illegal to set both usecs and
2010                  * max_frames to 0.
2011                  */
2012                 if (!*p->usecs && !*p->max_frames)
2013                         *p->max_frames = 1;
2014         }
2015
2016         return 0;
2017 }
2018
2019 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2020 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2021                         struct net_device *dev, u32 nsec, u16 *cp01)
2022 {
2023         const struct rtl_coalesce_info *ci;
2024         u16 i;
2025
2026         ci = rtl_coalesce_info(dev);
2027         if (IS_ERR(ci))
2028                 return ERR_CAST(ci);
2029
2030         for (i = 0; i < 4; i++) {
2031                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2032                                         ci->scalev[i].nsecs[1]);
2033                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2034                         *cp01 = i;
2035                         return &ci->scalev[i];
2036                 }
2037         }
2038
2039         return ERR_PTR(-EINVAL);
2040 }
2041
2042 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2043 {
2044         struct rtl8169_private *tp = netdev_priv(dev);
2045         const struct rtl_coalesce_scale *scale;
2046         struct {
2047                 u32 frames;
2048                 u32 usecs;
2049         } coal_settings [] = {
2050                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2051                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2052         }, *p = coal_settings;
2053         u16 w = 0, cp01;
2054         int i;
2055
2056         scale = rtl_coalesce_choose_scale(dev,
2057                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2058         if (IS_ERR(scale))
2059                 return PTR_ERR(scale);
2060
2061         for (i = 0; i < 2; i++, p++) {
2062                 u32 units;
2063
2064                 /*
2065                  * accept max_frames=1 we returned in rtl_get_coalesce.
2066                  * accept it not only when usecs=0 because of e.g. the following scenario:
2067                  *
2068                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2069                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2070                  * - then user does `ethtool -C eth0 rx-usecs 100`
2071                  *
2072                  * since ethtool sends to kernel whole ethtool_coalesce
2073                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2074                  * we'll reject it below in `frames % 4 != 0`.
2075                  */
2076                 if (p->frames == 1) {
2077                         p->frames = 0;
2078                 }
2079
2080                 units = p->usecs * 1000 / scale->nsecs[i];
2081                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2082                         return -EINVAL;
2083
2084                 w <<= RTL_COALESCE_SHIFT;
2085                 w |= units;
2086                 w <<= RTL_COALESCE_SHIFT;
2087                 w |= p->frames >> 2;
2088         }
2089
2090         rtl_lock_work(tp);
2091
2092         RTL_W16(tp, IntrMitigate, swab16(w));
2093
2094         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2095         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2096         RTL_R16(tp, CPlusCmd);
2097
2098         rtl_unlock_work(tp);
2099
2100         return 0;
2101 }
2102
2103 static const struct ethtool_ops rtl8169_ethtool_ops = {
2104         .get_drvinfo            = rtl8169_get_drvinfo,
2105         .get_regs_len           = rtl8169_get_regs_len,
2106         .get_link               = ethtool_op_get_link,
2107         .get_coalesce           = rtl_get_coalesce,
2108         .set_coalesce           = rtl_set_coalesce,
2109         .get_msglevel           = rtl8169_get_msglevel,
2110         .set_msglevel           = rtl8169_set_msglevel,
2111         .get_regs               = rtl8169_get_regs,
2112         .get_wol                = rtl8169_get_wol,
2113         .set_wol                = rtl8169_set_wol,
2114         .get_strings            = rtl8169_get_strings,
2115         .get_sset_count         = rtl8169_get_sset_count,
2116         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2117         .get_ts_info            = ethtool_op_get_ts_info,
2118         .nway_reset             = phy_ethtool_nway_reset,
2119         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2120         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2121 };
2122
2123 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2124                                     u8 default_version)
2125 {
2126         /*
2127          * The driver currently handles the 8168Bf and the 8168Be identically
2128          * but they can be identified more specifically through the test below
2129          * if needed:
2130          *
2131          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2132          *
2133          * Same thing for the 8101Eb and the 8101Ec:
2134          *
2135          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2136          */
2137         static const struct rtl_mac_info {
2138                 u32 mask;
2139                 u32 val;
2140                 int mac_version;
2141         } mac_info[] = {
2142                 /* 8168EP family. */
2143                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2144                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2145                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2146
2147                 /* 8168H family. */
2148                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2149                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2150
2151                 /* 8168G family. */
2152                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2153                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2154                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2155                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2156
2157                 /* 8168F family. */
2158                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2159                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2160                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2161
2162                 /* 8168E family. */
2163                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2164                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2165                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2166
2167                 /* 8168D family. */
2168                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2169                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2170
2171                 /* 8168DP family. */
2172                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2173                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2174                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2175
2176                 /* 8168C family. */
2177                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2178                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2179                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2180                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2181                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2182                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2183                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2184
2185                 /* 8168B family. */
2186                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2187                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2188                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2189
2190                 /* 8101 family. */
2191                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2192                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2193                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2194                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2195                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2196                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2197                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2198                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2199                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2200                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2201                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2202                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2203                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2204                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2205                 /* FIXME: where did these entries come from ? -- FR */
2206                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2207                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2208
2209                 /* 8110 family. */
2210                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2211                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2212                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2213                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2214                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2215                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2216
2217                 /* Catch-all */
2218                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2219         };
2220         const struct rtl_mac_info *p = mac_info;
2221         u32 reg;
2222
2223         reg = RTL_R32(tp, TxConfig);
2224         while ((reg & p->mask) != p->val)
2225                 p++;
2226         tp->mac_version = p->mac_version;
2227
2228         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2229                 dev_notice(tp_to_dev(tp),
2230                            "unknown MAC, using family default\n");
2231                 tp->mac_version = default_version;
2232         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2233                 tp->mac_version = tp->supports_gmii ?
2234                                   RTL_GIGA_MAC_VER_42 :
2235                                   RTL_GIGA_MAC_VER_43;
2236         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2237                 tp->mac_version = tp->supports_gmii ?
2238                                   RTL_GIGA_MAC_VER_45 :
2239                                   RTL_GIGA_MAC_VER_47;
2240         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2241                 tp->mac_version = tp->supports_gmii ?
2242                                   RTL_GIGA_MAC_VER_46 :
2243                                   RTL_GIGA_MAC_VER_48;
2244         }
2245 }
2246
2247 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2248 {
2249         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2250 }
2251
2252 struct phy_reg {
2253         u16 reg;
2254         u16 val;
2255 };
2256
2257 static void rtl_writephy_batch(struct rtl8169_private *tp,
2258                                const struct phy_reg *regs, int len)
2259 {
2260         while (len-- > 0) {
2261                 rtl_writephy(tp, regs->reg, regs->val);
2262                 regs++;
2263         }
2264 }
2265
2266 #define PHY_READ                0x00000000
2267 #define PHY_DATA_OR             0x10000000
2268 #define PHY_DATA_AND            0x20000000
2269 #define PHY_BJMPN               0x30000000
2270 #define PHY_MDIO_CHG            0x40000000
2271 #define PHY_CLEAR_READCOUNT     0x70000000
2272 #define PHY_WRITE               0x80000000
2273 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2274 #define PHY_COMP_EQ_SKIPN       0xa0000000
2275 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2276 #define PHY_WRITE_PREVIOUS      0xc0000000
2277 #define PHY_SKIPN               0xd0000000
2278 #define PHY_DELAY_MS            0xe0000000
2279
2280 struct fw_info {
2281         u32     magic;
2282         char    version[RTL_VER_SIZE];
2283         __le32  fw_start;
2284         __le32  fw_len;
2285         u8      chksum;
2286 } __packed;
2287
2288 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2289
2290 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2291 {
2292         const struct firmware *fw = rtl_fw->fw;
2293         struct fw_info *fw_info = (struct fw_info *)fw->data;
2294         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2295         char *version = rtl_fw->version;
2296         bool rc = false;
2297
2298         if (fw->size < FW_OPCODE_SIZE)
2299                 goto out;
2300
2301         if (!fw_info->magic) {
2302                 size_t i, size, start;
2303                 u8 checksum = 0;
2304
2305                 if (fw->size < sizeof(*fw_info))
2306                         goto out;
2307
2308                 for (i = 0; i < fw->size; i++)
2309                         checksum += fw->data[i];
2310                 if (checksum != 0)
2311                         goto out;
2312
2313                 start = le32_to_cpu(fw_info->fw_start);
2314                 if (start > fw->size)
2315                         goto out;
2316
2317                 size = le32_to_cpu(fw_info->fw_len);
2318                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2319                         goto out;
2320
2321                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2322
2323                 pa->code = (__le32 *)(fw->data + start);
2324                 pa->size = size;
2325         } else {
2326                 if (fw->size % FW_OPCODE_SIZE)
2327                         goto out;
2328
2329                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2330
2331                 pa->code = (__le32 *)fw->data;
2332                 pa->size = fw->size / FW_OPCODE_SIZE;
2333         }
2334         version[RTL_VER_SIZE - 1] = 0;
2335
2336         rc = true;
2337 out:
2338         return rc;
2339 }
2340
2341 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2342                            struct rtl_fw_phy_action *pa)
2343 {
2344         bool rc = false;
2345         size_t index;
2346
2347         for (index = 0; index < pa->size; index++) {
2348                 u32 action = le32_to_cpu(pa->code[index]);
2349                 u32 regno = (action & 0x0fff0000) >> 16;
2350
2351                 switch(action & 0xf0000000) {
2352                 case PHY_READ:
2353                 case PHY_DATA_OR:
2354                 case PHY_DATA_AND:
2355                 case PHY_MDIO_CHG:
2356                 case PHY_CLEAR_READCOUNT:
2357                 case PHY_WRITE:
2358                 case PHY_WRITE_PREVIOUS:
2359                 case PHY_DELAY_MS:
2360                         break;
2361
2362                 case PHY_BJMPN:
2363                         if (regno > index) {
2364                                 netif_err(tp, ifup, tp->dev,
2365                                           "Out of range of firmware\n");
2366                                 goto out;
2367                         }
2368                         break;
2369                 case PHY_READCOUNT_EQ_SKIP:
2370                         if (index + 2 >= pa->size) {
2371                                 netif_err(tp, ifup, tp->dev,
2372                                           "Out of range of firmware\n");
2373                                 goto out;
2374                         }
2375                         break;
2376                 case PHY_COMP_EQ_SKIPN:
2377                 case PHY_COMP_NEQ_SKIPN:
2378                 case PHY_SKIPN:
2379                         if (index + 1 + regno >= pa->size) {
2380                                 netif_err(tp, ifup, tp->dev,
2381                                           "Out of range of firmware\n");
2382                                 goto out;
2383                         }
2384                         break;
2385
2386                 default:
2387                         netif_err(tp, ifup, tp->dev,
2388                                   "Invalid action 0x%08x\n", action);
2389                         goto out;
2390                 }
2391         }
2392         rc = true;
2393 out:
2394         return rc;
2395 }
2396
2397 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2398 {
2399         struct net_device *dev = tp->dev;
2400         int rc = -EINVAL;
2401
2402         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2403                 netif_err(tp, ifup, dev, "invalid firmware\n");
2404                 goto out;
2405         }
2406
2407         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2408                 rc = 0;
2409 out:
2410         return rc;
2411 }
2412
2413 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2414 {
2415         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2416         struct mdio_ops org, *ops = &tp->mdio_ops;
2417         u32 predata, count;
2418         size_t index;
2419
2420         predata = count = 0;
2421         org.write = ops->write;
2422         org.read = ops->read;
2423
2424         for (index = 0; index < pa->size; ) {
2425                 u32 action = le32_to_cpu(pa->code[index]);
2426                 u32 data = action & 0x0000ffff;
2427                 u32 regno = (action & 0x0fff0000) >> 16;
2428
2429                 if (!action)
2430                         break;
2431
2432                 switch(action & 0xf0000000) {
2433                 case PHY_READ:
2434                         predata = rtl_readphy(tp, regno);
2435                         count++;
2436                         index++;
2437                         break;
2438                 case PHY_DATA_OR:
2439                         predata |= data;
2440                         index++;
2441                         break;
2442                 case PHY_DATA_AND:
2443                         predata &= data;
2444                         index++;
2445                         break;
2446                 case PHY_BJMPN:
2447                         index -= regno;
2448                         break;
2449                 case PHY_MDIO_CHG:
2450                         if (data == 0) {
2451                                 ops->write = org.write;
2452                                 ops->read = org.read;
2453                         } else if (data == 1) {
2454                                 ops->write = mac_mcu_write;
2455                                 ops->read = mac_mcu_read;
2456                         }
2457
2458                         index++;
2459                         break;
2460                 case PHY_CLEAR_READCOUNT:
2461                         count = 0;
2462                         index++;
2463                         break;
2464                 case PHY_WRITE:
2465                         rtl_writephy(tp, regno, data);
2466                         index++;
2467                         break;
2468                 case PHY_READCOUNT_EQ_SKIP:
2469                         index += (count == data) ? 2 : 1;
2470                         break;
2471                 case PHY_COMP_EQ_SKIPN:
2472                         if (predata == data)
2473                                 index += regno;
2474                         index++;
2475                         break;
2476                 case PHY_COMP_NEQ_SKIPN:
2477                         if (predata != data)
2478                                 index += regno;
2479                         index++;
2480                         break;
2481                 case PHY_WRITE_PREVIOUS:
2482                         rtl_writephy(tp, regno, predata);
2483                         index++;
2484                         break;
2485                 case PHY_SKIPN:
2486                         index += regno + 1;
2487                         break;
2488                 case PHY_DELAY_MS:
2489                         mdelay(data);
2490                         index++;
2491                         break;
2492
2493                 default:
2494                         BUG();
2495                 }
2496         }
2497
2498         ops->write = org.write;
2499         ops->read = org.read;
2500 }
2501
2502 static void rtl_release_firmware(struct rtl8169_private *tp)
2503 {
2504         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2505                 release_firmware(tp->rtl_fw->fw);
2506                 kfree(tp->rtl_fw);
2507         }
2508         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2509 }
2510
2511 static void rtl_apply_firmware(struct rtl8169_private *tp)
2512 {
2513         struct rtl_fw *rtl_fw = tp->rtl_fw;
2514
2515         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2516         if (!IS_ERR_OR_NULL(rtl_fw))
2517                 rtl_phy_write_fw(tp, rtl_fw);
2518 }
2519
2520 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2521 {
2522         if (rtl_readphy(tp, reg) != val)
2523                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2524         else
2525                 rtl_apply_firmware(tp);
2526 }
2527
2528 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2529 {
2530         static const struct phy_reg phy_reg_init[] = {
2531                 { 0x1f, 0x0001 },
2532                 { 0x06, 0x006e },
2533                 { 0x08, 0x0708 },
2534                 { 0x15, 0x4000 },
2535                 { 0x18, 0x65c7 },
2536
2537                 { 0x1f, 0x0001 },
2538                 { 0x03, 0x00a1 },
2539                 { 0x02, 0x0008 },
2540                 { 0x01, 0x0120 },
2541                 { 0x00, 0x1000 },
2542                 { 0x04, 0x0800 },
2543                 { 0x04, 0x0000 },
2544
2545                 { 0x03, 0xff41 },
2546                 { 0x02, 0xdf60 },
2547                 { 0x01, 0x0140 },
2548                 { 0x00, 0x0077 },
2549                 { 0x04, 0x7800 },
2550                 { 0x04, 0x7000 },
2551
2552                 { 0x03, 0x802f },
2553                 { 0x02, 0x4f02 },
2554                 { 0x01, 0x0409 },
2555                 { 0x00, 0xf0f9 },
2556                 { 0x04, 0x9800 },
2557                 { 0x04, 0x9000 },
2558
2559                 { 0x03, 0xdf01 },
2560                 { 0x02, 0xdf20 },
2561                 { 0x01, 0xff95 },
2562                 { 0x00, 0xba00 },
2563                 { 0x04, 0xa800 },
2564                 { 0x04, 0xa000 },
2565
2566                 { 0x03, 0xff41 },
2567                 { 0x02, 0xdf20 },
2568                 { 0x01, 0x0140 },
2569                 { 0x00, 0x00bb },
2570                 { 0x04, 0xb800 },
2571                 { 0x04, 0xb000 },
2572
2573                 { 0x03, 0xdf41 },
2574                 { 0x02, 0xdc60 },
2575                 { 0x01, 0x6340 },
2576                 { 0x00, 0x007d },
2577                 { 0x04, 0xd800 },
2578                 { 0x04, 0xd000 },
2579
2580                 { 0x03, 0xdf01 },
2581                 { 0x02, 0xdf20 },
2582                 { 0x01, 0x100a },
2583                 { 0x00, 0xa0ff },
2584                 { 0x04, 0xf800 },
2585                 { 0x04, 0xf000 },
2586
2587                 { 0x1f, 0x0000 },
2588                 { 0x0b, 0x0000 },
2589                 { 0x00, 0x9200 }
2590         };
2591
2592         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2593 }
2594
2595 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2596 {
2597         static const struct phy_reg phy_reg_init[] = {
2598                 { 0x1f, 0x0002 },
2599                 { 0x01, 0x90d0 },
2600                 { 0x1f, 0x0000 }
2601         };
2602
2603         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2604 }
2605
2606 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2607 {
2608         struct pci_dev *pdev = tp->pci_dev;
2609
2610         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2611             (pdev->subsystem_device != 0xe000))
2612                 return;
2613
2614         rtl_writephy(tp, 0x1f, 0x0001);
2615         rtl_writephy(tp, 0x10, 0xf01b);
2616         rtl_writephy(tp, 0x1f, 0x0000);
2617 }
2618
2619 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2620 {
2621         static const struct phy_reg phy_reg_init[] = {
2622                 { 0x1f, 0x0001 },
2623                 { 0x04, 0x0000 },
2624                 { 0x03, 0x00a1 },
2625                 { 0x02, 0x0008 },
2626                 { 0x01, 0x0120 },
2627                 { 0x00, 0x1000 },
2628                 { 0x04, 0x0800 },
2629                 { 0x04, 0x9000 },
2630                 { 0x03, 0x802f },
2631                 { 0x02, 0x4f02 },
2632                 { 0x01, 0x0409 },
2633                 { 0x00, 0xf099 },
2634                 { 0x04, 0x9800 },
2635                 { 0x04, 0xa000 },
2636                 { 0x03, 0xdf01 },
2637                 { 0x02, 0xdf20 },
2638                 { 0x01, 0xff95 },
2639                 { 0x00, 0xba00 },
2640                 { 0x04, 0xa800 },
2641                 { 0x04, 0xf000 },
2642                 { 0x03, 0xdf01 },
2643                 { 0x02, 0xdf20 },
2644                 { 0x01, 0x101a },
2645                 { 0x00, 0xa0ff },
2646                 { 0x04, 0xf800 },
2647                 { 0x04, 0x0000 },
2648                 { 0x1f, 0x0000 },
2649
2650                 { 0x1f, 0x0001 },
2651                 { 0x10, 0xf41b },
2652                 { 0x14, 0xfb54 },
2653                 { 0x18, 0xf5c7 },
2654                 { 0x1f, 0x0000 },
2655
2656                 { 0x1f, 0x0001 },
2657                 { 0x17, 0x0cc0 },
2658                 { 0x1f, 0x0000 }
2659         };
2660
2661         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2662
2663         rtl8169scd_hw_phy_config_quirk(tp);
2664 }
2665
2666 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2667 {
2668         static const struct phy_reg phy_reg_init[] = {
2669                 { 0x1f, 0x0001 },
2670                 { 0x04, 0x0000 },
2671                 { 0x03, 0x00a1 },
2672                 { 0x02, 0x0008 },
2673                 { 0x01, 0x0120 },
2674                 { 0x00, 0x1000 },
2675                 { 0x04, 0x0800 },
2676                 { 0x04, 0x9000 },
2677                 { 0x03, 0x802f },
2678                 { 0x02, 0x4f02 },
2679                 { 0x01, 0x0409 },
2680                 { 0x00, 0xf099 },
2681                 { 0x04, 0x9800 },
2682                 { 0x04, 0xa000 },
2683                 { 0x03, 0xdf01 },
2684                 { 0x02, 0xdf20 },
2685                 { 0x01, 0xff95 },
2686                 { 0x00, 0xba00 },
2687                 { 0x04, 0xa800 },
2688                 { 0x04, 0xf000 },
2689                 { 0x03, 0xdf01 },
2690                 { 0x02, 0xdf20 },
2691                 { 0x01, 0x101a },
2692                 { 0x00, 0xa0ff },
2693                 { 0x04, 0xf800 },
2694                 { 0x04, 0x0000 },
2695                 { 0x1f, 0x0000 },
2696
2697                 { 0x1f, 0x0001 },
2698                 { 0x0b, 0x8480 },
2699                 { 0x1f, 0x0000 },
2700
2701                 { 0x1f, 0x0001 },
2702                 { 0x18, 0x67c7 },
2703                 { 0x04, 0x2000 },
2704                 { 0x03, 0x002f },
2705                 { 0x02, 0x4360 },
2706                 { 0x01, 0x0109 },
2707                 { 0x00, 0x3022 },
2708                 { 0x04, 0x2800 },
2709                 { 0x1f, 0x0000 },
2710
2711                 { 0x1f, 0x0001 },
2712                 { 0x17, 0x0cc0 },
2713                 { 0x1f, 0x0000 }
2714         };
2715
2716         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2717 }
2718
2719 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2720 {
2721         static const struct phy_reg phy_reg_init[] = {
2722                 { 0x10, 0xf41b },
2723                 { 0x1f, 0x0000 }
2724         };
2725
2726         rtl_writephy(tp, 0x1f, 0x0001);
2727         rtl_patchphy(tp, 0x16, 1 << 0);
2728
2729         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2730 }
2731
2732 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2733 {
2734         static const struct phy_reg phy_reg_init[] = {
2735                 { 0x1f, 0x0001 },
2736                 { 0x10, 0xf41b },
2737                 { 0x1f, 0x0000 }
2738         };
2739
2740         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2741 }
2742
2743 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2744 {
2745         static const struct phy_reg phy_reg_init[] = {
2746                 { 0x1f, 0x0000 },
2747                 { 0x1d, 0x0f00 },
2748                 { 0x1f, 0x0002 },
2749                 { 0x0c, 0x1ec8 },
2750                 { 0x1f, 0x0000 }
2751         };
2752
2753         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754 }
2755
2756 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2757 {
2758         static const struct phy_reg phy_reg_init[] = {
2759                 { 0x1f, 0x0001 },
2760                 { 0x1d, 0x3d98 },
2761                 { 0x1f, 0x0000 }
2762         };
2763
2764         rtl_writephy(tp, 0x1f, 0x0000);
2765         rtl_patchphy(tp, 0x14, 1 << 5);
2766         rtl_patchphy(tp, 0x0d, 1 << 5);
2767
2768         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2769 }
2770
2771 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2772 {
2773         static const struct phy_reg phy_reg_init[] = {
2774                 { 0x1f, 0x0001 },
2775                 { 0x12, 0x2300 },
2776                 { 0x1f, 0x0002 },
2777                 { 0x00, 0x88d4 },
2778                 { 0x01, 0x82b1 },
2779                 { 0x03, 0x7002 },
2780                 { 0x08, 0x9e30 },
2781                 { 0x09, 0x01f0 },
2782                 { 0x0a, 0x5500 },
2783                 { 0x0c, 0x00c8 },
2784                 { 0x1f, 0x0003 },
2785                 { 0x12, 0xc096 },
2786                 { 0x16, 0x000a },
2787                 { 0x1f, 0x0000 },
2788                 { 0x1f, 0x0000 },
2789                 { 0x09, 0x2000 },
2790                 { 0x09, 0x0000 }
2791         };
2792
2793         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2794
2795         rtl_patchphy(tp, 0x14, 1 << 5);
2796         rtl_patchphy(tp, 0x0d, 1 << 5);
2797         rtl_writephy(tp, 0x1f, 0x0000);
2798 }
2799
2800 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2801 {
2802         static const struct phy_reg phy_reg_init[] = {
2803                 { 0x1f, 0x0001 },
2804                 { 0x12, 0x2300 },
2805                 { 0x03, 0x802f },
2806                 { 0x02, 0x4f02 },
2807                 { 0x01, 0x0409 },
2808                 { 0x00, 0xf099 },
2809                 { 0x04, 0x9800 },
2810                 { 0x04, 0x9000 },
2811                 { 0x1d, 0x3d98 },
2812                 { 0x1f, 0x0002 },
2813                 { 0x0c, 0x7eb8 },
2814                 { 0x06, 0x0761 },
2815                 { 0x1f, 0x0003 },
2816                 { 0x16, 0x0f0a },
2817                 { 0x1f, 0x0000 }
2818         };
2819
2820         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2821
2822         rtl_patchphy(tp, 0x16, 1 << 0);
2823         rtl_patchphy(tp, 0x14, 1 << 5);
2824         rtl_patchphy(tp, 0x0d, 1 << 5);
2825         rtl_writephy(tp, 0x1f, 0x0000);
2826 }
2827
2828 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2829 {
2830         static const struct phy_reg phy_reg_init[] = {
2831                 { 0x1f, 0x0001 },
2832                 { 0x12, 0x2300 },
2833                 { 0x1d, 0x3d98 },
2834                 { 0x1f, 0x0002 },
2835                 { 0x0c, 0x7eb8 },
2836                 { 0x06, 0x5461 },
2837                 { 0x1f, 0x0003 },
2838                 { 0x16, 0x0f0a },
2839                 { 0x1f, 0x0000 }
2840         };
2841
2842         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2843
2844         rtl_patchphy(tp, 0x16, 1 << 0);
2845         rtl_patchphy(tp, 0x14, 1 << 5);
2846         rtl_patchphy(tp, 0x0d, 1 << 5);
2847         rtl_writephy(tp, 0x1f, 0x0000);
2848 }
2849
2850 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2851 {
2852         rtl8168c_3_hw_phy_config(tp);
2853 }
2854
2855 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2856 {
2857         static const struct phy_reg phy_reg_init_0[] = {
2858                 /* Channel Estimation */
2859                 { 0x1f, 0x0001 },
2860                 { 0x06, 0x4064 },
2861                 { 0x07, 0x2863 },
2862                 { 0x08, 0x059c },
2863                 { 0x09, 0x26b4 },
2864                 { 0x0a, 0x6a19 },
2865                 { 0x0b, 0xdcc8 },
2866                 { 0x10, 0xf06d },
2867                 { 0x14, 0x7f68 },
2868                 { 0x18, 0x7fd9 },
2869                 { 0x1c, 0xf0ff },
2870                 { 0x1d, 0x3d9c },
2871                 { 0x1f, 0x0003 },
2872                 { 0x12, 0xf49f },
2873                 { 0x13, 0x070b },
2874                 { 0x1a, 0x05ad },
2875                 { 0x14, 0x94c0 },
2876
2877                 /*
2878                  * Tx Error Issue
2879                  * Enhance line driver power
2880                  */
2881                 { 0x1f, 0x0002 },
2882                 { 0x06, 0x5561 },
2883                 { 0x1f, 0x0005 },
2884                 { 0x05, 0x8332 },
2885                 { 0x06, 0x5561 },
2886
2887                 /*
2888                  * Can not link to 1Gbps with bad cable
2889                  * Decrease SNR threshold form 21.07dB to 19.04dB
2890                  */
2891                 { 0x1f, 0x0001 },
2892                 { 0x17, 0x0cc0 },
2893
2894                 { 0x1f, 0x0000 },
2895                 { 0x0d, 0xf880 }
2896         };
2897
2898         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2899
2900         /*
2901          * Rx Error Issue
2902          * Fine Tune Switching regulator parameter
2903          */
2904         rtl_writephy(tp, 0x1f, 0x0002);
2905         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2906         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2907
2908         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2909                 static const struct phy_reg phy_reg_init[] = {
2910                         { 0x1f, 0x0002 },
2911                         { 0x05, 0x669a },
2912                         { 0x1f, 0x0005 },
2913                         { 0x05, 0x8330 },
2914                         { 0x06, 0x669a },
2915                         { 0x1f, 0x0002 }
2916                 };
2917                 int val;
2918
2919                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2920
2921                 val = rtl_readphy(tp, 0x0d);
2922
2923                 if ((val & 0x00ff) != 0x006c) {
2924                         static const u32 set[] = {
2925                                 0x0065, 0x0066, 0x0067, 0x0068,
2926                                 0x0069, 0x006a, 0x006b, 0x006c
2927                         };
2928                         int i;
2929
2930                         rtl_writephy(tp, 0x1f, 0x0002);
2931
2932                         val &= 0xff00;
2933                         for (i = 0; i < ARRAY_SIZE(set); i++)
2934                                 rtl_writephy(tp, 0x0d, val | set[i]);
2935                 }
2936         } else {
2937                 static const struct phy_reg phy_reg_init[] = {
2938                         { 0x1f, 0x0002 },
2939                         { 0x05, 0x6662 },
2940                         { 0x1f, 0x0005 },
2941                         { 0x05, 0x8330 },
2942                         { 0x06, 0x6662 }
2943                 };
2944
2945                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2946         }
2947
2948         /* RSET couple improve */
2949         rtl_writephy(tp, 0x1f, 0x0002);
2950         rtl_patchphy(tp, 0x0d, 0x0300);
2951         rtl_patchphy(tp, 0x0f, 0x0010);
2952
2953         /* Fine tune PLL performance */
2954         rtl_writephy(tp, 0x1f, 0x0002);
2955         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2956         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2957
2958         rtl_writephy(tp, 0x1f, 0x0005);
2959         rtl_writephy(tp, 0x05, 0x001b);
2960
2961         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2962
2963         rtl_writephy(tp, 0x1f, 0x0000);
2964 }
2965
2966 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2967 {
2968         static const struct phy_reg phy_reg_init_0[] = {
2969                 /* Channel Estimation */
2970                 { 0x1f, 0x0001 },
2971                 { 0x06, 0x4064 },
2972                 { 0x07, 0x2863 },
2973                 { 0x08, 0x059c },
2974                 { 0x09, 0x26b4 },
2975                 { 0x0a, 0x6a19 },
2976                 { 0x0b, 0xdcc8 },
2977                 { 0x10, 0xf06d },
2978                 { 0x14, 0x7f68 },
2979                 { 0x18, 0x7fd9 },
2980                 { 0x1c, 0xf0ff },
2981                 { 0x1d, 0x3d9c },
2982                 { 0x1f, 0x0003 },
2983                 { 0x12, 0xf49f },
2984                 { 0x13, 0x070b },
2985                 { 0x1a, 0x05ad },
2986                 { 0x14, 0x94c0 },
2987
2988                 /*
2989                  * Tx Error Issue
2990                  * Enhance line driver power
2991                  */
2992                 { 0x1f, 0x0002 },
2993                 { 0x06, 0x5561 },
2994                 { 0x1f, 0x0005 },
2995                 { 0x05, 0x8332 },
2996                 { 0x06, 0x5561 },
2997
2998                 /*
2999                  * Can not link to 1Gbps with bad cable
3000                  * Decrease SNR threshold form 21.07dB to 19.04dB
3001                  */
3002                 { 0x1f, 0x0001 },
3003                 { 0x17, 0x0cc0 },
3004
3005                 { 0x1f, 0x0000 },
3006                 { 0x0d, 0xf880 }
3007         };
3008
3009         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3010
3011         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3012                 static const struct phy_reg phy_reg_init[] = {
3013                         { 0x1f, 0x0002 },
3014                         { 0x05, 0x669a },
3015                         { 0x1f, 0x0005 },
3016                         { 0x05, 0x8330 },
3017                         { 0x06, 0x669a },
3018
3019                         { 0x1f, 0x0002 }
3020                 };
3021                 int val;
3022
3023                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3024
3025                 val = rtl_readphy(tp, 0x0d);
3026                 if ((val & 0x00ff) != 0x006c) {
3027                         static const u32 set[] = {
3028                                 0x0065, 0x0066, 0x0067, 0x0068,
3029                                 0x0069, 0x006a, 0x006b, 0x006c
3030                         };
3031                         int i;
3032
3033                         rtl_writephy(tp, 0x1f, 0x0002);
3034
3035                         val &= 0xff00;
3036                         for (i = 0; i < ARRAY_SIZE(set); i++)
3037                                 rtl_writephy(tp, 0x0d, val | set[i]);
3038                 }
3039         } else {
3040                 static const struct phy_reg phy_reg_init[] = {
3041                         { 0x1f, 0x0002 },
3042                         { 0x05, 0x2642 },
3043                         { 0x1f, 0x0005 },
3044                         { 0x05, 0x8330 },
3045                         { 0x06, 0x2642 }
3046                 };
3047
3048                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3049         }
3050
3051         /* Fine tune PLL performance */
3052         rtl_writephy(tp, 0x1f, 0x0002);
3053         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3054         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3055
3056         /* Switching regulator Slew rate */
3057         rtl_writephy(tp, 0x1f, 0x0002);
3058         rtl_patchphy(tp, 0x0f, 0x0017);
3059
3060         rtl_writephy(tp, 0x1f, 0x0005);
3061         rtl_writephy(tp, 0x05, 0x001b);
3062
3063         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3064
3065         rtl_writephy(tp, 0x1f, 0x0000);
3066 }
3067
3068 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3069 {
3070         static const struct phy_reg phy_reg_init[] = {
3071                 { 0x1f, 0x0002 },
3072                 { 0x10, 0x0008 },
3073                 { 0x0d, 0x006c },
3074
3075                 { 0x1f, 0x0000 },
3076                 { 0x0d, 0xf880 },
3077
3078                 { 0x1f, 0x0001 },
3079                 { 0x17, 0x0cc0 },
3080
3081                 { 0x1f, 0x0001 },
3082                 { 0x0b, 0xa4d8 },
3083                 { 0x09, 0x281c },
3084                 { 0x07, 0x2883 },
3085                 { 0x0a, 0x6b35 },
3086                 { 0x1d, 0x3da4 },
3087                 { 0x1c, 0xeffd },
3088                 { 0x14, 0x7f52 },
3089                 { 0x18, 0x7fc6 },
3090                 { 0x08, 0x0601 },
3091                 { 0x06, 0x4063 },
3092                 { 0x10, 0xf074 },
3093                 { 0x1f, 0x0003 },
3094                 { 0x13, 0x0789 },
3095                 { 0x12, 0xf4bd },
3096                 { 0x1a, 0x04fd },
3097                 { 0x14, 0x84b0 },
3098                 { 0x1f, 0x0000 },
3099                 { 0x00, 0x9200 },
3100
3101                 { 0x1f, 0x0005 },
3102                 { 0x01, 0x0340 },
3103                 { 0x1f, 0x0001 },
3104                 { 0x04, 0x4000 },
3105                 { 0x03, 0x1d21 },
3106                 { 0x02, 0x0c32 },
3107                 { 0x01, 0x0200 },
3108                 { 0x00, 0x5554 },
3109                 { 0x04, 0x4800 },
3110                 { 0x04, 0x4000 },
3111                 { 0x04, 0xf000 },
3112                 { 0x03, 0xdf01 },
3113                 { 0x02, 0xdf20 },
3114                 { 0x01, 0x101a },
3115                 { 0x00, 0xa0ff },
3116                 { 0x04, 0xf800 },
3117                 { 0x04, 0xf000 },
3118                 { 0x1f, 0x0000 },
3119
3120                 { 0x1f, 0x0007 },
3121                 { 0x1e, 0x0023 },
3122                 { 0x16, 0x0000 },
3123                 { 0x1f, 0x0000 }
3124         };
3125
3126         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3127 }
3128
3129 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3130 {
3131         static const struct phy_reg phy_reg_init[] = {
3132                 { 0x1f, 0x0001 },
3133                 { 0x17, 0x0cc0 },
3134
3135                 { 0x1f, 0x0007 },
3136                 { 0x1e, 0x002d },
3137                 { 0x18, 0x0040 },
3138                 { 0x1f, 0x0000 }
3139         };
3140
3141         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3142         rtl_patchphy(tp, 0x0d, 1 << 5);
3143 }
3144
3145 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3146 {
3147         static const struct phy_reg phy_reg_init[] = {
3148                 /* Enable Delay cap */
3149                 { 0x1f, 0x0005 },
3150                 { 0x05, 0x8b80 },
3151                 { 0x06, 0xc896 },
3152                 { 0x1f, 0x0000 },
3153
3154                 /* Channel estimation fine tune */
3155                 { 0x1f, 0x0001 },
3156                 { 0x0b, 0x6c20 },
3157                 { 0x07, 0x2872 },
3158                 { 0x1c, 0xefff },
3159                 { 0x1f, 0x0003 },
3160                 { 0x14, 0x6420 },
3161                 { 0x1f, 0x0000 },
3162
3163                 /* Update PFM & 10M TX idle timer */
3164                 { 0x1f, 0x0007 },
3165                 { 0x1e, 0x002f },
3166                 { 0x15, 0x1919 },
3167                 { 0x1f, 0x0000 },
3168
3169                 { 0x1f, 0x0007 },
3170                 { 0x1e, 0x00ac },
3171                 { 0x18, 0x0006 },
3172                 { 0x1f, 0x0000 }
3173         };
3174
3175         rtl_apply_firmware(tp);
3176
3177         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3178
3179         /* DCO enable for 10M IDLE Power */
3180         rtl_writephy(tp, 0x1f, 0x0007);
3181         rtl_writephy(tp, 0x1e, 0x0023);
3182         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3183         rtl_writephy(tp, 0x1f, 0x0000);
3184
3185         /* For impedance matching */
3186         rtl_writephy(tp, 0x1f, 0x0002);
3187         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3188         rtl_writephy(tp, 0x1f, 0x0000);
3189
3190         /* PHY auto speed down */
3191         rtl_writephy(tp, 0x1f, 0x0007);
3192         rtl_writephy(tp, 0x1e, 0x002d);
3193         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3194         rtl_writephy(tp, 0x1f, 0x0000);
3195         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3196
3197         rtl_writephy(tp, 0x1f, 0x0005);
3198         rtl_writephy(tp, 0x05, 0x8b86);
3199         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3200         rtl_writephy(tp, 0x1f, 0x0000);
3201
3202         rtl_writephy(tp, 0x1f, 0x0005);
3203         rtl_writephy(tp, 0x05, 0x8b85);
3204         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3205         rtl_writephy(tp, 0x1f, 0x0007);
3206         rtl_writephy(tp, 0x1e, 0x0020);
3207         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3208         rtl_writephy(tp, 0x1f, 0x0006);
3209         rtl_writephy(tp, 0x00, 0x5a00);
3210         rtl_writephy(tp, 0x1f, 0x0000);
3211         rtl_writephy(tp, 0x0d, 0x0007);
3212         rtl_writephy(tp, 0x0e, 0x003c);
3213         rtl_writephy(tp, 0x0d, 0x4007);
3214         rtl_writephy(tp, 0x0e, 0x0000);
3215         rtl_writephy(tp, 0x0d, 0x0000);
3216 }
3217
3218 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3219 {
3220         const u16 w[] = {
3221                 addr[0] | (addr[1] << 8),
3222                 addr[2] | (addr[3] << 8),
3223                 addr[4] | (addr[5] << 8)
3224         };
3225         const struct exgmac_reg e[] = {
3226                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3227                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3228                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3229                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3230         };
3231
3232         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3233 }
3234
3235 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3236 {
3237         static const struct phy_reg phy_reg_init[] = {
3238                 /* Enable Delay cap */
3239                 { 0x1f, 0x0004 },
3240                 { 0x1f, 0x0007 },
3241                 { 0x1e, 0x00ac },
3242                 { 0x18, 0x0006 },
3243                 { 0x1f, 0x0002 },
3244                 { 0x1f, 0x0000 },
3245                 { 0x1f, 0x0000 },
3246
3247                 /* Channel estimation fine tune */
3248                 { 0x1f, 0x0003 },
3249                 { 0x09, 0xa20f },
3250                 { 0x1f, 0x0000 },
3251                 { 0x1f, 0x0000 },
3252
3253                 /* Green Setting */
3254                 { 0x1f, 0x0005 },
3255                 { 0x05, 0x8b5b },
3256                 { 0x06, 0x9222 },
3257                 { 0x05, 0x8b6d },
3258                 { 0x06, 0x8000 },
3259                 { 0x05, 0x8b76 },
3260                 { 0x06, 0x8000 },
3261                 { 0x1f, 0x0000 }
3262         };
3263
3264         rtl_apply_firmware(tp);
3265
3266         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3267
3268         /* For 4-corner performance improve */
3269         rtl_writephy(tp, 0x1f, 0x0005);
3270         rtl_writephy(tp, 0x05, 0x8b80);
3271         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3272         rtl_writephy(tp, 0x1f, 0x0000);
3273
3274         /* PHY auto speed down */
3275         rtl_writephy(tp, 0x1f, 0x0004);
3276         rtl_writephy(tp, 0x1f, 0x0007);
3277         rtl_writephy(tp, 0x1e, 0x002d);
3278         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3279         rtl_writephy(tp, 0x1f, 0x0002);
3280         rtl_writephy(tp, 0x1f, 0x0000);
3281         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3282
3283         /* improve 10M EEE waveform */
3284         rtl_writephy(tp, 0x1f, 0x0005);
3285         rtl_writephy(tp, 0x05, 0x8b86);
3286         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3287         rtl_writephy(tp, 0x1f, 0x0000);
3288
3289         /* Improve 2-pair detection performance */
3290         rtl_writephy(tp, 0x1f, 0x0005);
3291         rtl_writephy(tp, 0x05, 0x8b85);
3292         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3293         rtl_writephy(tp, 0x1f, 0x0000);
3294
3295         /* EEE setting */
3296         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3297         rtl_writephy(tp, 0x1f, 0x0005);
3298         rtl_writephy(tp, 0x05, 0x8b85);
3299         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3300         rtl_writephy(tp, 0x1f, 0x0004);
3301         rtl_writephy(tp, 0x1f, 0x0007);
3302         rtl_writephy(tp, 0x1e, 0x0020);
3303         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3304         rtl_writephy(tp, 0x1f, 0x0002);
3305         rtl_writephy(tp, 0x1f, 0x0000);
3306         rtl_writephy(tp, 0x0d, 0x0007);
3307         rtl_writephy(tp, 0x0e, 0x003c);
3308         rtl_writephy(tp, 0x0d, 0x4007);
3309         rtl_writephy(tp, 0x0e, 0x0006);
3310         rtl_writephy(tp, 0x0d, 0x0000);
3311
3312         /* Green feature */
3313         rtl_writephy(tp, 0x1f, 0x0003);
3314         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3315         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3316         rtl_writephy(tp, 0x1f, 0x0000);
3317         rtl_writephy(tp, 0x1f, 0x0005);
3318         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3319         rtl_writephy(tp, 0x1f, 0x0000);
3320
3321         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3322         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3323 }
3324
3325 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3326 {
3327         /* For 4-corner performance improve */
3328         rtl_writephy(tp, 0x1f, 0x0005);
3329         rtl_writephy(tp, 0x05, 0x8b80);
3330         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3331         rtl_writephy(tp, 0x1f, 0x0000);
3332
3333         /* PHY auto speed down */
3334         rtl_writephy(tp, 0x1f, 0x0007);
3335         rtl_writephy(tp, 0x1e, 0x002d);
3336         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3337         rtl_writephy(tp, 0x1f, 0x0000);
3338         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3339
3340         /* Improve 10M EEE waveform */
3341         rtl_writephy(tp, 0x1f, 0x0005);
3342         rtl_writephy(tp, 0x05, 0x8b86);
3343         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3344         rtl_writephy(tp, 0x1f, 0x0000);
3345 }
3346
3347 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3348 {
3349         static const struct phy_reg phy_reg_init[] = {
3350                 /* Channel estimation fine tune */
3351                 { 0x1f, 0x0003 },
3352                 { 0x09, 0xa20f },
3353                 { 0x1f, 0x0000 },
3354
3355                 /* Modify green table for giga & fnet */
3356                 { 0x1f, 0x0005 },
3357                 { 0x05, 0x8b55 },
3358                 { 0x06, 0x0000 },
3359                 { 0x05, 0x8b5e },
3360                 { 0x06, 0x0000 },
3361                 { 0x05, 0x8b67 },
3362                 { 0x06, 0x0000 },
3363                 { 0x05, 0x8b70 },
3364                 { 0x06, 0x0000 },
3365                 { 0x1f, 0x0000 },
3366                 { 0x1f, 0x0007 },
3367                 { 0x1e, 0x0078 },
3368                 { 0x17, 0x0000 },
3369                 { 0x19, 0x00fb },
3370                 { 0x1f, 0x0000 },
3371
3372                 /* Modify green table for 10M */
3373                 { 0x1f, 0x0005 },
3374                 { 0x05, 0x8b79 },
3375                 { 0x06, 0xaa00 },
3376                 { 0x1f, 0x0000 },
3377
3378                 /* Disable hiimpedance detection (RTCT) */
3379                 { 0x1f, 0x0003 },
3380                 { 0x01, 0x328a },
3381                 { 0x1f, 0x0000 }
3382         };
3383
3384         rtl_apply_firmware(tp);
3385
3386         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3387
3388         rtl8168f_hw_phy_config(tp);
3389
3390         /* Improve 2-pair detection performance */
3391         rtl_writephy(tp, 0x1f, 0x0005);
3392         rtl_writephy(tp, 0x05, 0x8b85);
3393         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3394         rtl_writephy(tp, 0x1f, 0x0000);
3395 }
3396
3397 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3398 {
3399         rtl_apply_firmware(tp);
3400
3401         rtl8168f_hw_phy_config(tp);
3402 }
3403
3404 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3405 {
3406         static const struct phy_reg phy_reg_init[] = {
3407                 /* Channel estimation fine tune */
3408                 { 0x1f, 0x0003 },
3409                 { 0x09, 0xa20f },
3410                 { 0x1f, 0x0000 },
3411
3412                 /* Modify green table for giga & fnet */
3413                 { 0x1f, 0x0005 },
3414                 { 0x05, 0x8b55 },
3415                 { 0x06, 0x0000 },
3416                 { 0x05, 0x8b5e },
3417                 { 0x06, 0x0000 },
3418                 { 0x05, 0x8b67 },
3419                 { 0x06, 0x0000 },
3420                 { 0x05, 0x8b70 },
3421                 { 0x06, 0x0000 },
3422                 { 0x1f, 0x0000 },
3423                 { 0x1f, 0x0007 },
3424                 { 0x1e, 0x0078 },
3425                 { 0x17, 0x0000 },
3426                 { 0x19, 0x00aa },
3427                 { 0x1f, 0x0000 },
3428
3429                 /* Modify green table for 10M */
3430                 { 0x1f, 0x0005 },
3431                 { 0x05, 0x8b79 },
3432                 { 0x06, 0xaa00 },
3433                 { 0x1f, 0x0000 },
3434
3435                 /* Disable hiimpedance detection (RTCT) */
3436                 { 0x1f, 0x0003 },
3437                 { 0x01, 0x328a },
3438                 { 0x1f, 0x0000 }
3439         };
3440
3441
3442         rtl_apply_firmware(tp);
3443
3444         rtl8168f_hw_phy_config(tp);
3445
3446         /* Improve 2-pair detection performance */
3447         rtl_writephy(tp, 0x1f, 0x0005);
3448         rtl_writephy(tp, 0x05, 0x8b85);
3449         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3450         rtl_writephy(tp, 0x1f, 0x0000);
3451
3452         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3453
3454         /* Modify green table for giga */
3455         rtl_writephy(tp, 0x1f, 0x0005);
3456         rtl_writephy(tp, 0x05, 0x8b54);
3457         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3458         rtl_writephy(tp, 0x05, 0x8b5d);
3459         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3460         rtl_writephy(tp, 0x05, 0x8a7c);
3461         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3462         rtl_writephy(tp, 0x05, 0x8a7f);
3463         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3464         rtl_writephy(tp, 0x05, 0x8a82);
3465         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3466         rtl_writephy(tp, 0x05, 0x8a85);
3467         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3468         rtl_writephy(tp, 0x05, 0x8a88);
3469         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3470         rtl_writephy(tp, 0x1f, 0x0000);
3471
3472         /* uc same-seed solution */
3473         rtl_writephy(tp, 0x1f, 0x0005);
3474         rtl_writephy(tp, 0x05, 0x8b85);
3475         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3476         rtl_writephy(tp, 0x1f, 0x0000);
3477
3478         /* eee setting */
3479         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3480         rtl_writephy(tp, 0x1f, 0x0005);
3481         rtl_writephy(tp, 0x05, 0x8b85);
3482         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3483         rtl_writephy(tp, 0x1f, 0x0004);
3484         rtl_writephy(tp, 0x1f, 0x0007);
3485         rtl_writephy(tp, 0x1e, 0x0020);
3486         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3487         rtl_writephy(tp, 0x1f, 0x0000);
3488         rtl_writephy(tp, 0x0d, 0x0007);
3489         rtl_writephy(tp, 0x0e, 0x003c);
3490         rtl_writephy(tp, 0x0d, 0x4007);
3491         rtl_writephy(tp, 0x0e, 0x0000);
3492         rtl_writephy(tp, 0x0d, 0x0000);
3493
3494         /* Green feature */
3495         rtl_writephy(tp, 0x1f, 0x0003);
3496         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3497         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3498         rtl_writephy(tp, 0x1f, 0x0000);
3499 }
3500
3501 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3502 {
3503         rtl_apply_firmware(tp);
3504
3505         rtl_writephy(tp, 0x1f, 0x0a46);
3506         if (rtl_readphy(tp, 0x10) & 0x0100) {
3507                 rtl_writephy(tp, 0x1f, 0x0bcc);
3508                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3509         } else {
3510                 rtl_writephy(tp, 0x1f, 0x0bcc);
3511                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3512         }
3513
3514         rtl_writephy(tp, 0x1f, 0x0a46);
3515         if (rtl_readphy(tp, 0x13) & 0x0100) {
3516                 rtl_writephy(tp, 0x1f, 0x0c41);
3517                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3518         } else {
3519                 rtl_writephy(tp, 0x1f, 0x0c41);
3520                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3521         }
3522
3523         /* Enable PHY auto speed down */
3524         rtl_writephy(tp, 0x1f, 0x0a44);
3525         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3526
3527         rtl_writephy(tp, 0x1f, 0x0bcc);
3528         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3529         rtl_writephy(tp, 0x1f, 0x0a44);
3530         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3531         rtl_writephy(tp, 0x1f, 0x0a43);
3532         rtl_writephy(tp, 0x13, 0x8084);
3533         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3534         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3535
3536         /* EEE auto-fallback function */
3537         rtl_writephy(tp, 0x1f, 0x0a4b);
3538         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3539
3540         /* Enable UC LPF tune function */
3541         rtl_writephy(tp, 0x1f, 0x0a43);
3542         rtl_writephy(tp, 0x13, 0x8012);
3543         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3544
3545         rtl_writephy(tp, 0x1f, 0x0c42);
3546         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3547
3548         /* Improve SWR Efficiency */
3549         rtl_writephy(tp, 0x1f, 0x0bcd);
3550         rtl_writephy(tp, 0x14, 0x5065);
3551         rtl_writephy(tp, 0x14, 0xd065);
3552         rtl_writephy(tp, 0x1f, 0x0bc8);
3553         rtl_writephy(tp, 0x11, 0x5655);
3554         rtl_writephy(tp, 0x1f, 0x0bcd);
3555         rtl_writephy(tp, 0x14, 0x1065);
3556         rtl_writephy(tp, 0x14, 0x9065);
3557         rtl_writephy(tp, 0x14, 0x1065);
3558
3559         /* Check ALDPS bit, disable it if enabled */
3560         rtl_writephy(tp, 0x1f, 0x0a43);
3561         if (rtl_readphy(tp, 0x10) & 0x0004)
3562                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3563
3564         rtl_writephy(tp, 0x1f, 0x0000);
3565 }
3566
3567 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3568 {
3569         rtl_apply_firmware(tp);
3570 }
3571
3572 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3573 {
3574         u16 dout_tapbin;
3575         u32 data;
3576
3577         rtl_apply_firmware(tp);
3578
3579         /* CHN EST parameters adjust - giga master */
3580         rtl_writephy(tp, 0x1f, 0x0a43);
3581         rtl_writephy(tp, 0x13, 0x809b);
3582         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3583         rtl_writephy(tp, 0x13, 0x80a2);
3584         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3585         rtl_writephy(tp, 0x13, 0x80a4);
3586         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3587         rtl_writephy(tp, 0x13, 0x809c);
3588         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3589         rtl_writephy(tp, 0x1f, 0x0000);
3590
3591         /* CHN EST parameters adjust - giga slave */
3592         rtl_writephy(tp, 0x1f, 0x0a43);
3593         rtl_writephy(tp, 0x13, 0x80ad);
3594         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3595         rtl_writephy(tp, 0x13, 0x80b4);
3596         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3597         rtl_writephy(tp, 0x13, 0x80ac);
3598         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3599         rtl_writephy(tp, 0x1f, 0x0000);
3600
3601         /* CHN EST parameters adjust - fnet */
3602         rtl_writephy(tp, 0x1f, 0x0a43);
3603         rtl_writephy(tp, 0x13, 0x808e);
3604         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3605         rtl_writephy(tp, 0x13, 0x8090);
3606         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3607         rtl_writephy(tp, 0x13, 0x8092);
3608         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3609         rtl_writephy(tp, 0x1f, 0x0000);
3610
3611         /* enable R-tune & PGA-retune function */
3612         dout_tapbin = 0;
3613         rtl_writephy(tp, 0x1f, 0x0a46);
3614         data = rtl_readphy(tp, 0x13);
3615         data &= 3;
3616         data <<= 2;
3617         dout_tapbin |= data;
3618         data = rtl_readphy(tp, 0x12);
3619         data &= 0xc000;
3620         data >>= 14;
3621         dout_tapbin |= data;
3622         dout_tapbin = ~(dout_tapbin^0x08);
3623         dout_tapbin <<= 12;
3624         dout_tapbin &= 0xf000;
3625         rtl_writephy(tp, 0x1f, 0x0a43);
3626         rtl_writephy(tp, 0x13, 0x827a);
3627         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3628         rtl_writephy(tp, 0x13, 0x827b);
3629         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3630         rtl_writephy(tp, 0x13, 0x827c);
3631         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3632         rtl_writephy(tp, 0x13, 0x827d);
3633         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3634
3635         rtl_writephy(tp, 0x1f, 0x0a43);
3636         rtl_writephy(tp, 0x13, 0x0811);
3637         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3638         rtl_writephy(tp, 0x1f, 0x0a42);
3639         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3640         rtl_writephy(tp, 0x1f, 0x0000);
3641
3642         /* enable GPHY 10M */
3643         rtl_writephy(tp, 0x1f, 0x0a44);
3644         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3645         rtl_writephy(tp, 0x1f, 0x0000);
3646
3647         /* SAR ADC performance */
3648         rtl_writephy(tp, 0x1f, 0x0bca);
3649         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3650         rtl_writephy(tp, 0x1f, 0x0000);
3651
3652         rtl_writephy(tp, 0x1f, 0x0a43);
3653         rtl_writephy(tp, 0x13, 0x803f);
3654         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3655         rtl_writephy(tp, 0x13, 0x8047);
3656         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3657         rtl_writephy(tp, 0x13, 0x804f);
3658         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3659         rtl_writephy(tp, 0x13, 0x8057);
3660         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3661         rtl_writephy(tp, 0x13, 0x805f);
3662         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3663         rtl_writephy(tp, 0x13, 0x8067);
3664         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3665         rtl_writephy(tp, 0x13, 0x806f);
3666         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3667         rtl_writephy(tp, 0x1f, 0x0000);
3668
3669         /* disable phy pfm mode */
3670         rtl_writephy(tp, 0x1f, 0x0a44);
3671         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3672         rtl_writephy(tp, 0x1f, 0x0000);
3673
3674         /* Check ALDPS bit, disable it if enabled */
3675         rtl_writephy(tp, 0x1f, 0x0a43);
3676         if (rtl_readphy(tp, 0x10) & 0x0004)
3677                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3678
3679         rtl_writephy(tp, 0x1f, 0x0000);
3680 }
3681
3682 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3683 {
3684         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3685         u16 rlen;
3686         u32 data;
3687
3688         rtl_apply_firmware(tp);
3689
3690         /* CHIN EST parameter update */
3691         rtl_writephy(tp, 0x1f, 0x0a43);
3692         rtl_writephy(tp, 0x13, 0x808a);
3693         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3694         rtl_writephy(tp, 0x1f, 0x0000);
3695
3696         /* enable R-tune & PGA-retune function */
3697         rtl_writephy(tp, 0x1f, 0x0a43);
3698         rtl_writephy(tp, 0x13, 0x0811);
3699         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3700         rtl_writephy(tp, 0x1f, 0x0a42);
3701         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3702         rtl_writephy(tp, 0x1f, 0x0000);
3703
3704         /* enable GPHY 10M */
3705         rtl_writephy(tp, 0x1f, 0x0a44);
3706         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3707         rtl_writephy(tp, 0x1f, 0x0000);
3708
3709         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3710         data = r8168_mac_ocp_read(tp, 0xdd02);
3711         ioffset_p3 = ((data & 0x80)>>7);
3712         ioffset_p3 <<= 3;
3713
3714         data = r8168_mac_ocp_read(tp, 0xdd00);
3715         ioffset_p3 |= ((data & (0xe000))>>13);
3716         ioffset_p2 = ((data & (0x1e00))>>9);
3717         ioffset_p1 = ((data & (0x01e0))>>5);
3718         ioffset_p0 = ((data & 0x0010)>>4);
3719         ioffset_p0 <<= 3;
3720         ioffset_p0 |= (data & (0x07));
3721         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3722
3723         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3724             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3725                 rtl_writephy(tp, 0x1f, 0x0bcf);
3726                 rtl_writephy(tp, 0x16, data);
3727                 rtl_writephy(tp, 0x1f, 0x0000);
3728         }
3729
3730         /* Modify rlen (TX LPF corner frequency) level */
3731         rtl_writephy(tp, 0x1f, 0x0bcd);
3732         data = rtl_readphy(tp, 0x16);
3733         data &= 0x000f;
3734         rlen = 0;
3735         if (data > 3)
3736                 rlen = data - 3;
3737         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3738         rtl_writephy(tp, 0x17, data);
3739         rtl_writephy(tp, 0x1f, 0x0bcd);
3740         rtl_writephy(tp, 0x1f, 0x0000);
3741
3742         /* disable phy pfm mode */
3743         rtl_writephy(tp, 0x1f, 0x0a44);
3744         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3745         rtl_writephy(tp, 0x1f, 0x0000);
3746
3747         /* Check ALDPS bit, disable it if enabled */
3748         rtl_writephy(tp, 0x1f, 0x0a43);
3749         if (rtl_readphy(tp, 0x10) & 0x0004)
3750                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3751
3752         rtl_writephy(tp, 0x1f, 0x0000);
3753 }
3754
3755 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3756 {
3757         /* Enable PHY auto speed down */
3758         rtl_writephy(tp, 0x1f, 0x0a44);
3759         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3760         rtl_writephy(tp, 0x1f, 0x0000);
3761
3762         /* patch 10M & ALDPS */
3763         rtl_writephy(tp, 0x1f, 0x0bcc);
3764         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3765         rtl_writephy(tp, 0x1f, 0x0a44);
3766         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3767         rtl_writephy(tp, 0x1f, 0x0a43);
3768         rtl_writephy(tp, 0x13, 0x8084);
3769         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3770         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3771         rtl_writephy(tp, 0x1f, 0x0000);
3772
3773         /* Enable EEE auto-fallback function */
3774         rtl_writephy(tp, 0x1f, 0x0a4b);
3775         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3776         rtl_writephy(tp, 0x1f, 0x0000);
3777
3778         /* Enable UC LPF tune function */
3779         rtl_writephy(tp, 0x1f, 0x0a43);
3780         rtl_writephy(tp, 0x13, 0x8012);
3781         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3782         rtl_writephy(tp, 0x1f, 0x0000);
3783
3784         /* set rg_sel_sdm_rate */
3785         rtl_writephy(tp, 0x1f, 0x0c42);
3786         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3787         rtl_writephy(tp, 0x1f, 0x0000);
3788
3789         /* Check ALDPS bit, disable it if enabled */
3790         rtl_writephy(tp, 0x1f, 0x0a43);
3791         if (rtl_readphy(tp, 0x10) & 0x0004)
3792                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3793
3794         rtl_writephy(tp, 0x1f, 0x0000);
3795 }
3796
3797 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3798 {
3799         /* patch 10M & ALDPS */
3800         rtl_writephy(tp, 0x1f, 0x0bcc);
3801         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3802         rtl_writephy(tp, 0x1f, 0x0a44);
3803         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3804         rtl_writephy(tp, 0x1f, 0x0a43);
3805         rtl_writephy(tp, 0x13, 0x8084);
3806         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3807         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3808         rtl_writephy(tp, 0x1f, 0x0000);
3809
3810         /* Enable UC LPF tune function */
3811         rtl_writephy(tp, 0x1f, 0x0a43);
3812         rtl_writephy(tp, 0x13, 0x8012);
3813         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3814         rtl_writephy(tp, 0x1f, 0x0000);
3815
3816         /* Set rg_sel_sdm_rate */
3817         rtl_writephy(tp, 0x1f, 0x0c42);
3818         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3819         rtl_writephy(tp, 0x1f, 0x0000);
3820
3821         /* Channel estimation parameters */
3822         rtl_writephy(tp, 0x1f, 0x0a43);
3823         rtl_writephy(tp, 0x13, 0x80f3);
3824         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3825         rtl_writephy(tp, 0x13, 0x80f0);
3826         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3827         rtl_writephy(tp, 0x13, 0x80ef);
3828         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3829         rtl_writephy(tp, 0x13, 0x80f6);
3830         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3831         rtl_writephy(tp, 0x13, 0x80ec);
3832         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3833         rtl_writephy(tp, 0x13, 0x80ed);
3834         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3835         rtl_writephy(tp, 0x13, 0x80f2);
3836         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3837         rtl_writephy(tp, 0x13, 0x80f4);
3838         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3839         rtl_writephy(tp, 0x1f, 0x0a43);
3840         rtl_writephy(tp, 0x13, 0x8110);
3841         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3842         rtl_writephy(tp, 0x13, 0x810f);
3843         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3844         rtl_writephy(tp, 0x13, 0x8111);
3845         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3846         rtl_writephy(tp, 0x13, 0x8113);
3847         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3848         rtl_writephy(tp, 0x13, 0x8115);
3849         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3850         rtl_writephy(tp, 0x13, 0x810e);
3851         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3852         rtl_writephy(tp, 0x13, 0x810c);
3853         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3854         rtl_writephy(tp, 0x13, 0x810b);
3855         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3856         rtl_writephy(tp, 0x1f, 0x0a43);
3857         rtl_writephy(tp, 0x13, 0x80d1);
3858         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3859         rtl_writephy(tp, 0x13, 0x80cd);
3860         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3861         rtl_writephy(tp, 0x13, 0x80d3);
3862         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3863         rtl_writephy(tp, 0x13, 0x80d5);
3864         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3865         rtl_writephy(tp, 0x13, 0x80d7);
3866         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3867
3868         /* Force PWM-mode */
3869         rtl_writephy(tp, 0x1f, 0x0bcd);
3870         rtl_writephy(tp, 0x14, 0x5065);
3871         rtl_writephy(tp, 0x14, 0xd065);
3872         rtl_writephy(tp, 0x1f, 0x0bc8);
3873         rtl_writephy(tp, 0x12, 0x00ed);
3874         rtl_writephy(tp, 0x1f, 0x0bcd);
3875         rtl_writephy(tp, 0x14, 0x1065);
3876         rtl_writephy(tp, 0x14, 0x9065);
3877         rtl_writephy(tp, 0x14, 0x1065);
3878         rtl_writephy(tp, 0x1f, 0x0000);
3879
3880         /* Check ALDPS bit, disable it if enabled */
3881         rtl_writephy(tp, 0x1f, 0x0a43);
3882         if (rtl_readphy(tp, 0x10) & 0x0004)
3883                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3884
3885         rtl_writephy(tp, 0x1f, 0x0000);
3886 }
3887
3888 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3889 {
3890         static const struct phy_reg phy_reg_init[] = {
3891                 { 0x1f, 0x0003 },
3892                 { 0x08, 0x441d },
3893                 { 0x01, 0x9100 },
3894                 { 0x1f, 0x0000 }
3895         };
3896
3897         rtl_writephy(tp, 0x1f, 0x0000);
3898         rtl_patchphy(tp, 0x11, 1 << 12);
3899         rtl_patchphy(tp, 0x19, 1 << 13);
3900         rtl_patchphy(tp, 0x10, 1 << 15);
3901
3902         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3903 }
3904
3905 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3906 {
3907         static const struct phy_reg phy_reg_init[] = {
3908                 { 0x1f, 0x0005 },
3909                 { 0x1a, 0x0000 },
3910                 { 0x1f, 0x0000 },
3911
3912                 { 0x1f, 0x0004 },
3913                 { 0x1c, 0x0000 },
3914                 { 0x1f, 0x0000 },
3915
3916                 { 0x1f, 0x0001 },
3917                 { 0x15, 0x7701 },
3918                 { 0x1f, 0x0000 }
3919         };
3920
3921         /* Disable ALDPS before ram code */
3922         rtl_writephy(tp, 0x1f, 0x0000);
3923         rtl_writephy(tp, 0x18, 0x0310);
3924         msleep(100);
3925
3926         rtl_apply_firmware(tp);
3927
3928         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3929 }
3930
3931 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3932 {
3933         /* Disable ALDPS before setting firmware */
3934         rtl_writephy(tp, 0x1f, 0x0000);
3935         rtl_writephy(tp, 0x18, 0x0310);
3936         msleep(20);
3937
3938         rtl_apply_firmware(tp);
3939
3940         /* EEE setting */
3941         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3942         rtl_writephy(tp, 0x1f, 0x0004);
3943         rtl_writephy(tp, 0x10, 0x401f);
3944         rtl_writephy(tp, 0x19, 0x7030);
3945         rtl_writephy(tp, 0x1f, 0x0000);
3946 }
3947
3948 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3949 {
3950         static const struct phy_reg phy_reg_init[] = {
3951                 { 0x1f, 0x0004 },
3952                 { 0x10, 0xc07f },
3953                 { 0x19, 0x7030 },
3954                 { 0x1f, 0x0000 }
3955         };
3956
3957         /* Disable ALDPS before ram code */
3958         rtl_writephy(tp, 0x1f, 0x0000);
3959         rtl_writephy(tp, 0x18, 0x0310);
3960         msleep(100);
3961
3962         rtl_apply_firmware(tp);
3963
3964         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3965         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3966
3967         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3968 }
3969
3970 static void rtl_hw_phy_config(struct net_device *dev)
3971 {
3972         struct rtl8169_private *tp = netdev_priv(dev);
3973
3974         rtl8169_print_mac_version(tp);
3975
3976         switch (tp->mac_version) {
3977         case RTL_GIGA_MAC_VER_01:
3978                 break;
3979         case RTL_GIGA_MAC_VER_02:
3980         case RTL_GIGA_MAC_VER_03:
3981                 rtl8169s_hw_phy_config(tp);
3982                 break;
3983         case RTL_GIGA_MAC_VER_04:
3984                 rtl8169sb_hw_phy_config(tp);
3985                 break;
3986         case RTL_GIGA_MAC_VER_05:
3987                 rtl8169scd_hw_phy_config(tp);
3988                 break;
3989         case RTL_GIGA_MAC_VER_06:
3990                 rtl8169sce_hw_phy_config(tp);
3991                 break;
3992         case RTL_GIGA_MAC_VER_07:
3993         case RTL_GIGA_MAC_VER_08:
3994         case RTL_GIGA_MAC_VER_09:
3995                 rtl8102e_hw_phy_config(tp);
3996                 break;
3997         case RTL_GIGA_MAC_VER_11:
3998                 rtl8168bb_hw_phy_config(tp);
3999                 break;
4000         case RTL_GIGA_MAC_VER_12:
4001                 rtl8168bef_hw_phy_config(tp);
4002                 break;
4003         case RTL_GIGA_MAC_VER_17:
4004                 rtl8168bef_hw_phy_config(tp);
4005                 break;
4006         case RTL_GIGA_MAC_VER_18:
4007                 rtl8168cp_1_hw_phy_config(tp);
4008                 break;
4009         case RTL_GIGA_MAC_VER_19:
4010                 rtl8168c_1_hw_phy_config(tp);
4011                 break;
4012         case RTL_GIGA_MAC_VER_20:
4013                 rtl8168c_2_hw_phy_config(tp);
4014                 break;
4015         case RTL_GIGA_MAC_VER_21:
4016                 rtl8168c_3_hw_phy_config(tp);
4017                 break;
4018         case RTL_GIGA_MAC_VER_22:
4019                 rtl8168c_4_hw_phy_config(tp);
4020                 break;
4021         case RTL_GIGA_MAC_VER_23:
4022         case RTL_GIGA_MAC_VER_24:
4023                 rtl8168cp_2_hw_phy_config(tp);
4024                 break;
4025         case RTL_GIGA_MAC_VER_25:
4026                 rtl8168d_1_hw_phy_config(tp);
4027                 break;
4028         case RTL_GIGA_MAC_VER_26:
4029                 rtl8168d_2_hw_phy_config(tp);
4030                 break;
4031         case RTL_GIGA_MAC_VER_27:
4032                 rtl8168d_3_hw_phy_config(tp);
4033                 break;
4034         case RTL_GIGA_MAC_VER_28:
4035                 rtl8168d_4_hw_phy_config(tp);
4036                 break;
4037         case RTL_GIGA_MAC_VER_29:
4038         case RTL_GIGA_MAC_VER_30:
4039                 rtl8105e_hw_phy_config(tp);
4040                 break;
4041         case RTL_GIGA_MAC_VER_31:
4042                 /* None. */
4043                 break;
4044         case RTL_GIGA_MAC_VER_32:
4045         case RTL_GIGA_MAC_VER_33:
4046                 rtl8168e_1_hw_phy_config(tp);
4047                 break;
4048         case RTL_GIGA_MAC_VER_34:
4049                 rtl8168e_2_hw_phy_config(tp);
4050                 break;
4051         case RTL_GIGA_MAC_VER_35:
4052                 rtl8168f_1_hw_phy_config(tp);
4053                 break;
4054         case RTL_GIGA_MAC_VER_36:
4055                 rtl8168f_2_hw_phy_config(tp);
4056                 break;
4057
4058         case RTL_GIGA_MAC_VER_37:
4059                 rtl8402_hw_phy_config(tp);
4060                 break;
4061
4062         case RTL_GIGA_MAC_VER_38:
4063                 rtl8411_hw_phy_config(tp);
4064                 break;
4065
4066         case RTL_GIGA_MAC_VER_39:
4067                 rtl8106e_hw_phy_config(tp);
4068                 break;
4069
4070         case RTL_GIGA_MAC_VER_40:
4071                 rtl8168g_1_hw_phy_config(tp);
4072                 break;
4073         case RTL_GIGA_MAC_VER_42:
4074         case RTL_GIGA_MAC_VER_43:
4075         case RTL_GIGA_MAC_VER_44:
4076                 rtl8168g_2_hw_phy_config(tp);
4077                 break;
4078         case RTL_GIGA_MAC_VER_45:
4079         case RTL_GIGA_MAC_VER_47:
4080                 rtl8168h_1_hw_phy_config(tp);
4081                 break;
4082         case RTL_GIGA_MAC_VER_46:
4083         case RTL_GIGA_MAC_VER_48:
4084                 rtl8168h_2_hw_phy_config(tp);
4085                 break;
4086
4087         case RTL_GIGA_MAC_VER_49:
4088                 rtl8168ep_1_hw_phy_config(tp);
4089                 break;
4090         case RTL_GIGA_MAC_VER_50:
4091         case RTL_GIGA_MAC_VER_51:
4092                 rtl8168ep_2_hw_phy_config(tp);
4093                 break;
4094
4095         case RTL_GIGA_MAC_VER_41:
4096         default:
4097                 break;
4098         }
4099 }
4100
4101 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4102 {
4103         if (!test_and_set_bit(flag, tp->wk.flags))
4104                 schedule_work(&tp->wk.work);
4105 }
4106
4107 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4108 {
4109         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4110                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4111 }
4112
4113 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4114 {
4115         rtl_hw_phy_config(dev);
4116
4117         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4118                 netif_dbg(tp, drv, dev,
4119                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4120                 RTL_W8(tp, 0x82, 0x01);
4121         }
4122
4123         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4124
4125         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4126                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4127
4128         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4129                 netif_dbg(tp, drv, dev,
4130                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4131                 RTL_W8(tp, 0x82, 0x01);
4132                 netif_dbg(tp, drv, dev,
4133                           "Set PHY Reg 0x0bh = 0x00h\n");
4134                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4135         }
4136
4137         /* We may have called phy_speed_down before */
4138         phy_speed_up(dev->phydev);
4139
4140         genphy_soft_reset(dev->phydev);
4141 }
4142
4143 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4144 {
4145         rtl_lock_work(tp);
4146
4147         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4148
4149         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4150         RTL_R32(tp, MAC4);
4151
4152         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4153         RTL_R32(tp, MAC0);
4154
4155         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4156                 rtl_rar_exgmac_set(tp, addr);
4157
4158         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4159
4160         rtl_unlock_work(tp);
4161 }
4162
4163 static int rtl_set_mac_address(struct net_device *dev, void *p)
4164 {
4165         struct rtl8169_private *tp = netdev_priv(dev);
4166         struct device *d = tp_to_dev(tp);
4167         int ret;
4168
4169         ret = eth_mac_addr(dev, p);
4170         if (ret)
4171                 return ret;
4172
4173         pm_runtime_get_noresume(d);
4174
4175         if (pm_runtime_active(d))
4176                 rtl_rar_set(tp, dev->dev_addr);
4177
4178         pm_runtime_put_noidle(d);
4179
4180         return 0;
4181 }
4182
4183 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4184 {
4185         if (!netif_running(dev))
4186                 return -ENODEV;
4187
4188         return phy_mii_ioctl(dev->phydev, ifr, cmd);
4189 }
4190
4191 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4192 {
4193         struct mdio_ops *ops = &tp->mdio_ops;
4194
4195         switch (tp->mac_version) {
4196         case RTL_GIGA_MAC_VER_27:
4197                 ops->write      = r8168dp_1_mdio_write;
4198                 ops->read       = r8168dp_1_mdio_read;
4199                 break;
4200         case RTL_GIGA_MAC_VER_28:
4201         case RTL_GIGA_MAC_VER_31:
4202                 ops->write      = r8168dp_2_mdio_write;
4203                 ops->read       = r8168dp_2_mdio_read;
4204                 break;
4205         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4206                 ops->write      = r8168g_mdio_write;
4207                 ops->read       = r8168g_mdio_read;
4208                 break;
4209         default:
4210                 ops->write      = r8169_mdio_write;
4211                 ops->read       = r8169_mdio_read;
4212                 break;
4213         }
4214 }
4215
4216 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4217 {
4218         switch (tp->mac_version) {
4219         case RTL_GIGA_MAC_VER_25:
4220         case RTL_GIGA_MAC_VER_26:
4221         case RTL_GIGA_MAC_VER_29:
4222         case RTL_GIGA_MAC_VER_30:
4223         case RTL_GIGA_MAC_VER_32:
4224         case RTL_GIGA_MAC_VER_33:
4225         case RTL_GIGA_MAC_VER_34:
4226         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4227                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4228                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4229                 break;
4230         default:
4231                 break;
4232         }
4233 }
4234
4235 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4236 {
4237         if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4238                 return false;
4239
4240         phy_speed_down(tp->dev->phydev, false);
4241         rtl_wol_suspend_quirk(tp);
4242
4243         return true;
4244 }
4245
4246 static void r8168_pll_power_down(struct rtl8169_private *tp)
4247 {
4248         if (r8168_check_dash(tp))
4249                 return;
4250
4251         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4252             tp->mac_version == RTL_GIGA_MAC_VER_33)
4253                 rtl_ephy_write(tp, 0x19, 0xff64);
4254
4255         if (rtl_wol_pll_power_down(tp))
4256                 return;
4257
4258         switch (tp->mac_version) {
4259         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4260         case RTL_GIGA_MAC_VER_37:
4261         case RTL_GIGA_MAC_VER_39:
4262         case RTL_GIGA_MAC_VER_43:
4263         case RTL_GIGA_MAC_VER_44:
4264         case RTL_GIGA_MAC_VER_45:
4265         case RTL_GIGA_MAC_VER_46:
4266         case RTL_GIGA_MAC_VER_47:
4267         case RTL_GIGA_MAC_VER_48:
4268         case RTL_GIGA_MAC_VER_50:
4269         case RTL_GIGA_MAC_VER_51:
4270                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4271                 break;
4272         case RTL_GIGA_MAC_VER_40:
4273         case RTL_GIGA_MAC_VER_41:
4274         case RTL_GIGA_MAC_VER_49:
4275                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4276                              0xfc000000, ERIAR_EXGMAC);
4277                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4278                 break;
4279         }
4280 }
4281
4282 static void r8168_pll_power_up(struct rtl8169_private *tp)
4283 {
4284         switch (tp->mac_version) {
4285         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4286         case RTL_GIGA_MAC_VER_37:
4287         case RTL_GIGA_MAC_VER_39:
4288         case RTL_GIGA_MAC_VER_43:
4289                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4290                 break;
4291         case RTL_GIGA_MAC_VER_44:
4292         case RTL_GIGA_MAC_VER_45:
4293         case RTL_GIGA_MAC_VER_46:
4294         case RTL_GIGA_MAC_VER_47:
4295         case RTL_GIGA_MAC_VER_48:
4296         case RTL_GIGA_MAC_VER_50:
4297         case RTL_GIGA_MAC_VER_51:
4298                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4299                 break;
4300         case RTL_GIGA_MAC_VER_40:
4301         case RTL_GIGA_MAC_VER_41:
4302         case RTL_GIGA_MAC_VER_49:
4303                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4304                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4305                              0x00000000, ERIAR_EXGMAC);
4306                 break;
4307         }
4308
4309         phy_resume(tp->dev->phydev);
4310         /* give MAC/PHY some time to resume */
4311         msleep(20);
4312 }
4313
4314 static void rtl_pll_power_down(struct rtl8169_private *tp)
4315 {
4316         switch (tp->mac_version) {
4317         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4318         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4319                 break;
4320         default:
4321                 r8168_pll_power_down(tp);
4322         }
4323 }
4324
4325 static void rtl_pll_power_up(struct rtl8169_private *tp)
4326 {
4327         switch (tp->mac_version) {
4328         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4329         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4330                 break;
4331         default:
4332                 r8168_pll_power_up(tp);
4333         }
4334 }
4335
4336 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4337 {
4338         switch (tp->mac_version) {
4339         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4340         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4341                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4342                 break;
4343         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4344         case RTL_GIGA_MAC_VER_34:
4345         case RTL_GIGA_MAC_VER_35:
4346                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4347                 break;
4348         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4349                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4350                 break;
4351         default:
4352                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4353                 break;
4354         }
4355 }
4356
4357 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4358 {
4359         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4360 }
4361
4362 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4363 {
4364         if (tp->jumbo_ops.enable) {
4365                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4366                 tp->jumbo_ops.enable(tp);
4367                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4368         }
4369 }
4370
4371 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4372 {
4373         if (tp->jumbo_ops.disable) {
4374                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4375                 tp->jumbo_ops.disable(tp);
4376                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4377         }
4378 }
4379
4380 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4381 {
4382         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4383         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4384         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4385 }
4386
4387 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4388 {
4389         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4390         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4391         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4392 }
4393
4394 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4395 {
4396         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4397 }
4398
4399 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4400 {
4401         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4402 }
4403
4404 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4405 {
4406         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4407         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4408         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4409         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4410 }
4411
4412 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4413 {
4414         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4415         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4416         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4417         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4418 }
4419
4420 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4421 {
4422         rtl_tx_performance_tweak(tp,
4423                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4424 }
4425
4426 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4427 {
4428         rtl_tx_performance_tweak(tp,
4429                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4430 }
4431
4432 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4433 {
4434         r8168b_0_hw_jumbo_enable(tp);
4435
4436         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4437 }
4438
4439 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4440 {
4441         r8168b_0_hw_jumbo_disable(tp);
4442
4443         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4444 }
4445
4446 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4447 {
4448         struct jumbo_ops *ops = &tp->jumbo_ops;
4449
4450         switch (tp->mac_version) {
4451         case RTL_GIGA_MAC_VER_11:
4452                 ops->disable    = r8168b_0_hw_jumbo_disable;
4453                 ops->enable     = r8168b_0_hw_jumbo_enable;
4454                 break;
4455         case RTL_GIGA_MAC_VER_12:
4456         case RTL_GIGA_MAC_VER_17:
4457                 ops->disable    = r8168b_1_hw_jumbo_disable;
4458                 ops->enable     = r8168b_1_hw_jumbo_enable;
4459                 break;
4460         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4461         case RTL_GIGA_MAC_VER_19:
4462         case RTL_GIGA_MAC_VER_20:
4463         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4464         case RTL_GIGA_MAC_VER_22:
4465         case RTL_GIGA_MAC_VER_23:
4466         case RTL_GIGA_MAC_VER_24:
4467         case RTL_GIGA_MAC_VER_25:
4468         case RTL_GIGA_MAC_VER_26:
4469                 ops->disable    = r8168c_hw_jumbo_disable;
4470                 ops->enable     = r8168c_hw_jumbo_enable;
4471                 break;
4472         case RTL_GIGA_MAC_VER_27:
4473         case RTL_GIGA_MAC_VER_28:
4474                 ops->disable    = r8168dp_hw_jumbo_disable;
4475                 ops->enable     = r8168dp_hw_jumbo_enable;
4476                 break;
4477         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4478         case RTL_GIGA_MAC_VER_32:
4479         case RTL_GIGA_MAC_VER_33:
4480         case RTL_GIGA_MAC_VER_34:
4481                 ops->disable    = r8168e_hw_jumbo_disable;
4482                 ops->enable     = r8168e_hw_jumbo_enable;
4483                 break;
4484
4485         /*
4486          * No action needed for jumbo frames with 8169.
4487          * No jumbo for 810x at all.
4488          */
4489         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4490         default:
4491                 ops->disable    = NULL;
4492                 ops->enable     = NULL;
4493                 break;
4494         }
4495 }
4496
4497 DECLARE_RTL_COND(rtl_chipcmd_cond)
4498 {
4499         return RTL_R8(tp, ChipCmd) & CmdReset;
4500 }
4501
4502 static void rtl_hw_reset(struct rtl8169_private *tp)
4503 {
4504         RTL_W8(tp, ChipCmd, CmdReset);
4505
4506         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4507 }
4508
4509 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4510 {
4511         struct rtl_fw *rtl_fw;
4512         const char *name;
4513         int rc = -ENOMEM;
4514
4515         name = rtl_lookup_firmware_name(tp);
4516         if (!name)
4517                 goto out_no_firmware;
4518
4519         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4520         if (!rtl_fw)
4521                 goto err_warn;
4522
4523         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4524         if (rc < 0)
4525                 goto err_free;
4526
4527         rc = rtl_check_firmware(tp, rtl_fw);
4528         if (rc < 0)
4529                 goto err_release_firmware;
4530
4531         tp->rtl_fw = rtl_fw;
4532 out:
4533         return;
4534
4535 err_release_firmware:
4536         release_firmware(rtl_fw->fw);
4537 err_free:
4538         kfree(rtl_fw);
4539 err_warn:
4540         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4541                    name, rc);
4542 out_no_firmware:
4543         tp->rtl_fw = NULL;
4544         goto out;
4545 }
4546
4547 static void rtl_request_firmware(struct rtl8169_private *tp)
4548 {
4549         if (IS_ERR(tp->rtl_fw))
4550                 rtl_request_uncached_firmware(tp);
4551 }
4552
4553 static void rtl_rx_close(struct rtl8169_private *tp)
4554 {
4555         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4556 }
4557
4558 DECLARE_RTL_COND(rtl_npq_cond)
4559 {
4560         return RTL_R8(tp, TxPoll) & NPQ;
4561 }
4562
4563 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4564 {
4565         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4566 }
4567
4568 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4569 {
4570         /* Disable interrupts */
4571         rtl8169_irq_mask_and_ack(tp);
4572
4573         rtl_rx_close(tp);
4574
4575         switch (tp->mac_version) {
4576         case RTL_GIGA_MAC_VER_27:
4577         case RTL_GIGA_MAC_VER_28:
4578         case RTL_GIGA_MAC_VER_31:
4579                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4580                 break;
4581         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4582         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4583                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4584                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4585                 break;
4586         default:
4587                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4588                 udelay(100);
4589                 break;
4590         }
4591
4592         rtl_hw_reset(tp);
4593 }
4594
4595 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4596 {
4597         /* Set DMA burst size and Interframe Gap Time */
4598         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
4599                 (InterFrameGap << TxInterFrameGapShift));
4600 }
4601
4602 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4603 {
4604         /* Low hurts. Let's disable the filtering. */
4605         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4606 }
4607
4608 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4609 {
4610         /*
4611          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4612          * register to be written before TxDescAddrLow to work.
4613          * Switching from MMIO to I/O access fixes the issue as well.
4614          */
4615         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4616         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4617         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4618         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4619 }
4620
4621 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4622 {
4623         static const struct rtl_cfg2_info {
4624                 u32 mac_version;
4625                 u32 clk;
4626                 u32 val;
4627         } cfg2_info [] = {
4628                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4629                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4630                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4631                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4632         };
4633         const struct rtl_cfg2_info *p = cfg2_info;
4634         unsigned int i;
4635         u32 clk;
4636
4637         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4638         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4639                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4640                         RTL_W32(tp, 0x7c, p->val);
4641                         break;
4642                 }
4643         }
4644 }
4645
4646 static void rtl_set_rx_mode(struct net_device *dev)
4647 {
4648         struct rtl8169_private *tp = netdev_priv(dev);
4649         u32 mc_filter[2];       /* Multicast hash filter */
4650         int rx_mode;
4651         u32 tmp = 0;
4652
4653         if (dev->flags & IFF_PROMISC) {
4654                 /* Unconditionally log net taps. */
4655                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4656                 rx_mode =
4657                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4658                     AcceptAllPhys;
4659                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4660         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4661                    (dev->flags & IFF_ALLMULTI)) {
4662                 /* Too many to filter perfectly -- accept all multicasts. */
4663                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4664                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4665         } else {
4666                 struct netdev_hw_addr *ha;
4667
4668                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4669                 mc_filter[1] = mc_filter[0] = 0;
4670                 netdev_for_each_mc_addr(ha, dev) {
4671                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4672                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4673                         rx_mode |= AcceptMulticast;
4674                 }
4675         }
4676
4677         if (dev->features & NETIF_F_RXALL)
4678                 rx_mode |= (AcceptErr | AcceptRunt);
4679
4680         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4681
4682         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4683                 u32 data = mc_filter[0];
4684
4685                 mc_filter[0] = swab32(mc_filter[1]);
4686                 mc_filter[1] = swab32(data);
4687         }
4688
4689         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4690                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4691
4692         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4693         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4694
4695         RTL_W32(tp, RxConfig, tmp);
4696 }
4697
4698 static void rtl_hw_start(struct  rtl8169_private *tp)
4699 {
4700         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4701
4702         tp->hw_start(tp);
4703
4704         rtl_set_rx_max_size(tp);
4705         rtl_set_rx_tx_desc_registers(tp);
4706         rtl_set_rx_tx_config_registers(tp);
4707         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4708
4709         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4710         RTL_R8(tp, IntrMask);
4711         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4712         rtl_set_rx_mode(tp->dev);
4713         /* no early-rx interrupts */
4714         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4715         rtl_irq_enable_all(tp);
4716 }
4717
4718 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4719 {
4720         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4721                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4722
4723         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4724
4725         tp->cp_cmd |= PCIMulRW;
4726
4727         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4728             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4729                 netif_dbg(tp, drv, tp->dev,
4730                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4731                 tp->cp_cmd |= (1 << 14);
4732         }
4733
4734         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4735
4736         rtl8169_set_magic_reg(tp, tp->mac_version);
4737
4738         /*
4739          * Undocumented corner. Supposedly:
4740          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4741          */
4742         RTL_W16(tp, IntrMitigate, 0x0000);
4743
4744         RTL_W32(tp, RxMissed, 0);
4745 }
4746
4747 DECLARE_RTL_COND(rtl_csiar_cond)
4748 {
4749         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4750 }
4751
4752 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4753 {
4754         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4755
4756         RTL_W32(tp, CSIDR, value);
4757         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4758                 CSIAR_BYTE_ENABLE | func << 16);
4759
4760         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4761 }
4762
4763 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4764 {
4765         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4766
4767         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4768                 CSIAR_BYTE_ENABLE);
4769
4770         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4771                 RTL_R32(tp, CSIDR) : ~0;
4772 }
4773
4774 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4775 {
4776         struct pci_dev *pdev = tp->pci_dev;
4777         u32 csi;
4778
4779         /* According to Realtek the value at config space address 0x070f
4780          * controls the L0s/L1 entrance latency. We try standard ECAM access
4781          * first and if it fails fall back to CSI.
4782          */
4783         if (pdev->cfg_size > 0x070f &&
4784             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4785                 return;
4786
4787         netdev_notice_once(tp->dev,
4788                 "No native access to PCI extended config space, falling back to CSI\n");
4789         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4790         rtl_csi_write(tp, 0x070c, csi | val << 24);
4791 }
4792
4793 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4794 {
4795         rtl_csi_access_enable(tp, 0x27);
4796 }
4797
4798 struct ephy_info {
4799         unsigned int offset;
4800         u16 mask;
4801         u16 bits;
4802 };
4803
4804 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4805                           int len)
4806 {
4807         u16 w;
4808
4809         while (len-- > 0) {
4810                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4811                 rtl_ephy_write(tp, e->offset, w);
4812                 e++;
4813         }
4814 }
4815
4816 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4817 {
4818         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4819                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4820 }
4821
4822 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4823 {
4824         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4825                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4826 }
4827
4828 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4829 {
4830         u8 data;
4831
4832         data = RTL_R8(tp, Config3);
4833
4834         if (enable)
4835                 data |= Rdy_to_L23;
4836         else
4837                 data &= ~Rdy_to_L23;
4838
4839         RTL_W8(tp, Config3, data);
4840 }
4841
4842 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4843 {
4844         if (enable) {
4845                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4846                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4847         } else {
4848                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4849                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4850         }
4851 }
4852
4853 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4854 {
4855         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4856
4857         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4858         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4859
4860         if (tp->dev->mtu <= ETH_DATA_LEN) {
4861                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4862                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4863         }
4864 }
4865
4866 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4867 {
4868         rtl_hw_start_8168bb(tp);
4869
4870         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4871
4872         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4873 }
4874
4875 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4876 {
4877         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4878
4879         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4880
4881         if (tp->dev->mtu <= ETH_DATA_LEN)
4882                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4883
4884         rtl_disable_clock_request(tp);
4885
4886         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4887         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4888 }
4889
4890 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4891 {
4892         static const struct ephy_info e_info_8168cp[] = {
4893                 { 0x01, 0,      0x0001 },
4894                 { 0x02, 0x0800, 0x1000 },
4895                 { 0x03, 0,      0x0042 },
4896                 { 0x06, 0x0080, 0x0000 },
4897                 { 0x07, 0,      0x2000 }
4898         };
4899
4900         rtl_set_def_aspm_entry_latency(tp);
4901
4902         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4903
4904         __rtl_hw_start_8168cp(tp);
4905 }
4906
4907 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4908 {
4909         rtl_set_def_aspm_entry_latency(tp);
4910
4911         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4912
4913         if (tp->dev->mtu <= ETH_DATA_LEN)
4914                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4915
4916         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4917         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4918 }
4919
4920 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4921 {
4922         rtl_set_def_aspm_entry_latency(tp);
4923
4924         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4925
4926         /* Magic. */
4927         RTL_W8(tp, DBG_REG, 0x20);
4928
4929         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4930
4931         if (tp->dev->mtu <= ETH_DATA_LEN)
4932                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4933
4934         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4935         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4936 }
4937
4938 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4939 {
4940         static const struct ephy_info e_info_8168c_1[] = {
4941                 { 0x02, 0x0800, 0x1000 },
4942                 { 0x03, 0,      0x0002 },
4943                 { 0x06, 0x0080, 0x0000 }
4944         };
4945
4946         rtl_set_def_aspm_entry_latency(tp);
4947
4948         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4949
4950         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4951
4952         __rtl_hw_start_8168cp(tp);
4953 }
4954
4955 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4956 {
4957         static const struct ephy_info e_info_8168c_2[] = {
4958                 { 0x01, 0,      0x0001 },
4959                 { 0x03, 0x0400, 0x0220 }
4960         };
4961
4962         rtl_set_def_aspm_entry_latency(tp);
4963
4964         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4965
4966         __rtl_hw_start_8168cp(tp);
4967 }
4968
4969 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4970 {
4971         rtl_hw_start_8168c_2(tp);
4972 }
4973
4974 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4975 {
4976         rtl_set_def_aspm_entry_latency(tp);
4977
4978         __rtl_hw_start_8168cp(tp);
4979 }
4980
4981 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4982 {
4983         rtl_set_def_aspm_entry_latency(tp);
4984
4985         rtl_disable_clock_request(tp);
4986
4987         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4988
4989         if (tp->dev->mtu <= ETH_DATA_LEN)
4990                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4991
4992         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4993         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4994 }
4995
4996 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4997 {
4998         rtl_set_def_aspm_entry_latency(tp);
4999
5000         if (tp->dev->mtu <= ETH_DATA_LEN)
5001                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5002
5003         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5004
5005         rtl_disable_clock_request(tp);
5006 }
5007
5008 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5009 {
5010         static const struct ephy_info e_info_8168d_4[] = {
5011                 { 0x0b, 0x0000, 0x0048 },
5012                 { 0x19, 0x0020, 0x0050 },
5013                 { 0x0c, 0x0100, 0x0020 }
5014         };
5015
5016         rtl_set_def_aspm_entry_latency(tp);
5017
5018         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5019
5020         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5021
5022         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5023
5024         rtl_enable_clock_request(tp);
5025 }
5026
5027 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5028 {
5029         static const struct ephy_info e_info_8168e_1[] = {
5030                 { 0x00, 0x0200, 0x0100 },
5031                 { 0x00, 0x0000, 0x0004 },
5032                 { 0x06, 0x0002, 0x0001 },
5033                 { 0x06, 0x0000, 0x0030 },
5034                 { 0x07, 0x0000, 0x2000 },
5035                 { 0x00, 0x0000, 0x0020 },
5036                 { 0x03, 0x5800, 0x2000 },
5037                 { 0x03, 0x0000, 0x0001 },
5038                 { 0x01, 0x0800, 0x1000 },
5039                 { 0x07, 0x0000, 0x4000 },
5040                 { 0x1e, 0x0000, 0x2000 },
5041                 { 0x19, 0xffff, 0xfe6c },
5042                 { 0x0a, 0x0000, 0x0040 }
5043         };
5044
5045         rtl_set_def_aspm_entry_latency(tp);
5046
5047         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5048
5049         if (tp->dev->mtu <= ETH_DATA_LEN)
5050                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5051
5052         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5053
5054         rtl_disable_clock_request(tp);
5055
5056         /* Reset tx FIFO pointer */
5057         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5058         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5059
5060         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5061 }
5062
5063 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5064 {
5065         static const struct ephy_info e_info_8168e_2[] = {
5066                 { 0x09, 0x0000, 0x0080 },
5067                 { 0x19, 0x0000, 0x0224 }
5068         };
5069
5070         rtl_set_def_aspm_entry_latency(tp);
5071
5072         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5073
5074         if (tp->dev->mtu <= ETH_DATA_LEN)
5075                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5076
5077         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5078         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5079         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5080         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5081         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5082         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5083         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5084         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5085
5086         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5087
5088         rtl_disable_clock_request(tp);
5089
5090         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5091         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5092
5093         /* Adjust EEE LED frequency */
5094         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5095
5096         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5097         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5098         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5099
5100         rtl_hw_aspm_clkreq_enable(tp, true);
5101 }
5102
5103 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5104 {
5105         rtl_set_def_aspm_entry_latency(tp);
5106
5107         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5108
5109         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5110         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5111         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5112         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5113         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5114         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5115         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5116         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5117         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5118         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5119
5120         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5121
5122         rtl_disable_clock_request(tp);
5123
5124         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5125         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5126         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5127         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5128         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5129 }
5130
5131 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5132 {
5133         static const struct ephy_info e_info_8168f_1[] = {
5134                 { 0x06, 0x00c0, 0x0020 },
5135                 { 0x08, 0x0001, 0x0002 },
5136                 { 0x09, 0x0000, 0x0080 },
5137                 { 0x19, 0x0000, 0x0224 }
5138         };
5139
5140         rtl_hw_start_8168f(tp);
5141
5142         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5143
5144         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5145
5146         /* Adjust EEE LED frequency */
5147         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5148 }
5149
5150 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5151 {
5152         static const struct ephy_info e_info_8168f_1[] = {
5153                 { 0x06, 0x00c0, 0x0020 },
5154                 { 0x0f, 0xffff, 0x5200 },
5155                 { 0x1e, 0x0000, 0x4000 },
5156                 { 0x19, 0x0000, 0x0224 }
5157         };
5158
5159         rtl_hw_start_8168f(tp);
5160         rtl_pcie_state_l2l3_enable(tp, false);
5161
5162         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5163
5164         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5165 }
5166
5167 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5168 {
5169         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5170
5171         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5172         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5173         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5174         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5175
5176         rtl_set_def_aspm_entry_latency(tp);
5177
5178         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5179
5180         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5181         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5182         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5183
5184         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5185         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5186
5187         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5188         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5189
5190         /* Adjust EEE LED frequency */
5191         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5192
5193         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5194         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5195
5196         rtl_pcie_state_l2l3_enable(tp, false);
5197 }
5198
5199 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5200 {
5201         static const struct ephy_info e_info_8168g_1[] = {
5202                 { 0x00, 0x0000, 0x0008 },
5203                 { 0x0c, 0x37d0, 0x0820 },
5204                 { 0x1e, 0x0000, 0x0001 },
5205                 { 0x19, 0x8000, 0x0000 }
5206         };
5207
5208         rtl_hw_start_8168g(tp);
5209
5210         /* disable aspm and clock request before access ephy */
5211         rtl_hw_aspm_clkreq_enable(tp, false);
5212         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5213         rtl_hw_aspm_clkreq_enable(tp, true);
5214 }
5215
5216 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5217 {
5218         static const struct ephy_info e_info_8168g_2[] = {
5219                 { 0x00, 0x0000, 0x0008 },
5220                 { 0x0c, 0x3df0, 0x0200 },
5221                 { 0x19, 0xffff, 0xfc00 },
5222                 { 0x1e, 0xffff, 0x20eb }
5223         };
5224
5225         rtl_hw_start_8168g(tp);
5226
5227         /* disable aspm and clock request before access ephy */
5228         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5229         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5230         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5231 }
5232
5233 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5234 {
5235         static const struct ephy_info e_info_8411_2[] = {
5236                 { 0x00, 0x0000, 0x0008 },
5237                 { 0x0c, 0x3df0, 0x0200 },
5238                 { 0x0f, 0xffff, 0x5200 },
5239                 { 0x19, 0x0020, 0x0000 },
5240                 { 0x1e, 0x0000, 0x2000 }
5241         };
5242
5243         rtl_hw_start_8168g(tp);
5244
5245         /* disable aspm and clock request before access ephy */
5246         rtl_hw_aspm_clkreq_enable(tp, false);
5247         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5248         rtl_hw_aspm_clkreq_enable(tp, true);
5249 }
5250
5251 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5252 {
5253         int rg_saw_cnt;
5254         u32 data;
5255         static const struct ephy_info e_info_8168h_1[] = {
5256                 { 0x1e, 0x0800, 0x0001 },
5257                 { 0x1d, 0x0000, 0x0800 },
5258                 { 0x05, 0xffff, 0x2089 },
5259                 { 0x06, 0xffff, 0x5881 },
5260                 { 0x04, 0xffff, 0x154a },
5261                 { 0x01, 0xffff, 0x068b }
5262         };
5263
5264         /* disable aspm and clock request before access ephy */
5265         rtl_hw_aspm_clkreq_enable(tp, false);
5266         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5267
5268         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5269
5270         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5271         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5272         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5273         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5274
5275         rtl_set_def_aspm_entry_latency(tp);
5276
5277         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5278
5279         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5280         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5281
5282         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5283
5284         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5285
5286         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5287
5288         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5289         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5290
5291         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5292         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5293
5294         /* Adjust EEE LED frequency */
5295         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5296
5297         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5298         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5299
5300         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5301
5302         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5303
5304         rtl_pcie_state_l2l3_enable(tp, false);
5305
5306         rtl_writephy(tp, 0x1f, 0x0c42);
5307         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5308         rtl_writephy(tp, 0x1f, 0x0000);
5309         if (rg_saw_cnt > 0) {
5310                 u16 sw_cnt_1ms_ini;
5311
5312                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5313                 sw_cnt_1ms_ini &= 0x0fff;
5314                 data = r8168_mac_ocp_read(tp, 0xd412);
5315                 data &= ~0x0fff;
5316                 data |= sw_cnt_1ms_ini;
5317                 r8168_mac_ocp_write(tp, 0xd412, data);
5318         }
5319
5320         data = r8168_mac_ocp_read(tp, 0xe056);
5321         data &= ~0xf0;
5322         data |= 0x70;
5323         r8168_mac_ocp_write(tp, 0xe056, data);
5324
5325         data = r8168_mac_ocp_read(tp, 0xe052);
5326         data &= ~0x6000;
5327         data |= 0x8008;
5328         r8168_mac_ocp_write(tp, 0xe052, data);
5329
5330         data = r8168_mac_ocp_read(tp, 0xe0d6);
5331         data &= ~0x01ff;
5332         data |= 0x017f;
5333         r8168_mac_ocp_write(tp, 0xe0d6, data);
5334
5335         data = r8168_mac_ocp_read(tp, 0xd420);
5336         data &= ~0x0fff;
5337         data |= 0x047f;
5338         r8168_mac_ocp_write(tp, 0xd420, data);
5339
5340         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5341         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5342         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5343         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5344
5345         rtl_hw_aspm_clkreq_enable(tp, true);
5346 }
5347
5348 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5349 {
5350         rtl8168ep_stop_cmac(tp);
5351
5352         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5353
5354         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5355         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5356         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5357         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5358
5359         rtl_set_def_aspm_entry_latency(tp);
5360
5361         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5362
5363         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5364         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5365
5366         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5367
5368         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5369
5370         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5371         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5372
5373         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5374         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5375
5376         /* Adjust EEE LED frequency */
5377         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5378
5379         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5380
5381         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5382
5383         rtl_pcie_state_l2l3_enable(tp, false);
5384 }
5385
5386 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5387 {
5388         static const struct ephy_info e_info_8168ep_1[] = {
5389                 { 0x00, 0xffff, 0x10ab },
5390                 { 0x06, 0xffff, 0xf030 },
5391                 { 0x08, 0xffff, 0x2006 },
5392                 { 0x0d, 0xffff, 0x1666 },
5393                 { 0x0c, 0x3ff0, 0x0000 }
5394         };
5395
5396         /* disable aspm and clock request before access ephy */
5397         rtl_hw_aspm_clkreq_enable(tp, false);
5398         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5399
5400         rtl_hw_start_8168ep(tp);
5401
5402         rtl_hw_aspm_clkreq_enable(tp, true);
5403 }
5404
5405 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5406 {
5407         static const struct ephy_info e_info_8168ep_2[] = {
5408                 { 0x00, 0xffff, 0x10a3 },
5409                 { 0x19, 0xffff, 0xfc00 },
5410                 { 0x1e, 0xffff, 0x20ea }
5411         };
5412
5413         /* disable aspm and clock request before access ephy */
5414         rtl_hw_aspm_clkreq_enable(tp, false);
5415         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5416
5417         rtl_hw_start_8168ep(tp);
5418
5419         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5420         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5421
5422         rtl_hw_aspm_clkreq_enable(tp, true);
5423 }
5424
5425 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5426 {
5427         u32 data;
5428         static const struct ephy_info e_info_8168ep_3[] = {
5429                 { 0x00, 0xffff, 0x10a3 },
5430                 { 0x19, 0xffff, 0x7c00 },
5431                 { 0x1e, 0xffff, 0x20eb },
5432                 { 0x0d, 0xffff, 0x1666 }
5433         };
5434
5435         /* disable aspm and clock request before access ephy */
5436         rtl_hw_aspm_clkreq_enable(tp, false);
5437         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5438
5439         rtl_hw_start_8168ep(tp);
5440
5441         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5442         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5443
5444         data = r8168_mac_ocp_read(tp, 0xd3e2);
5445         data &= 0xf000;
5446         data |= 0x0271;
5447         r8168_mac_ocp_write(tp, 0xd3e2, data);
5448
5449         data = r8168_mac_ocp_read(tp, 0xd3e4);
5450         data &= 0xff00;
5451         r8168_mac_ocp_write(tp, 0xd3e4, data);
5452
5453         data = r8168_mac_ocp_read(tp, 0xe860);
5454         data |= 0x0080;
5455         r8168_mac_ocp_write(tp, 0xe860, data);
5456
5457         rtl_hw_aspm_clkreq_enable(tp, true);
5458 }
5459
5460 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5461 {
5462         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5463
5464         tp->cp_cmd &= ~INTT_MASK;
5465         tp->cp_cmd |= PktCntrDisable | INTT_1;
5466         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5467
5468         RTL_W16(tp, IntrMitigate, 0x5151);
5469
5470         /* Work around for RxFIFO overflow. */
5471         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5472                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5473                 tp->event_slow &= ~RxOverflow;
5474         }
5475
5476         switch (tp->mac_version) {
5477         case RTL_GIGA_MAC_VER_11:
5478                 rtl_hw_start_8168bb(tp);
5479                 break;
5480
5481         case RTL_GIGA_MAC_VER_12:
5482         case RTL_GIGA_MAC_VER_17:
5483                 rtl_hw_start_8168bef(tp);
5484                 break;
5485
5486         case RTL_GIGA_MAC_VER_18:
5487                 rtl_hw_start_8168cp_1(tp);
5488                 break;
5489
5490         case RTL_GIGA_MAC_VER_19:
5491                 rtl_hw_start_8168c_1(tp);
5492                 break;
5493
5494         case RTL_GIGA_MAC_VER_20:
5495                 rtl_hw_start_8168c_2(tp);
5496                 break;
5497
5498         case RTL_GIGA_MAC_VER_21:
5499                 rtl_hw_start_8168c_3(tp);
5500                 break;
5501
5502         case RTL_GIGA_MAC_VER_22:
5503                 rtl_hw_start_8168c_4(tp);
5504                 break;
5505
5506         case RTL_GIGA_MAC_VER_23:
5507                 rtl_hw_start_8168cp_2(tp);
5508                 break;
5509
5510         case RTL_GIGA_MAC_VER_24:
5511                 rtl_hw_start_8168cp_3(tp);
5512                 break;
5513
5514         case RTL_GIGA_MAC_VER_25:
5515         case RTL_GIGA_MAC_VER_26:
5516         case RTL_GIGA_MAC_VER_27:
5517                 rtl_hw_start_8168d(tp);
5518                 break;
5519
5520         case RTL_GIGA_MAC_VER_28:
5521                 rtl_hw_start_8168d_4(tp);
5522                 break;
5523
5524         case RTL_GIGA_MAC_VER_31:
5525                 rtl_hw_start_8168dp(tp);
5526                 break;
5527
5528         case RTL_GIGA_MAC_VER_32:
5529         case RTL_GIGA_MAC_VER_33:
5530                 rtl_hw_start_8168e_1(tp);
5531                 break;
5532         case RTL_GIGA_MAC_VER_34:
5533                 rtl_hw_start_8168e_2(tp);
5534                 break;
5535
5536         case RTL_GIGA_MAC_VER_35:
5537         case RTL_GIGA_MAC_VER_36:
5538                 rtl_hw_start_8168f_1(tp);
5539                 break;
5540
5541         case RTL_GIGA_MAC_VER_38:
5542                 rtl_hw_start_8411(tp);
5543                 break;
5544
5545         case RTL_GIGA_MAC_VER_40:
5546         case RTL_GIGA_MAC_VER_41:
5547                 rtl_hw_start_8168g_1(tp);
5548                 break;
5549         case RTL_GIGA_MAC_VER_42:
5550                 rtl_hw_start_8168g_2(tp);
5551                 break;
5552
5553         case RTL_GIGA_MAC_VER_44:
5554                 rtl_hw_start_8411_2(tp);
5555                 break;
5556
5557         case RTL_GIGA_MAC_VER_45:
5558         case RTL_GIGA_MAC_VER_46:
5559                 rtl_hw_start_8168h_1(tp);
5560                 break;
5561
5562         case RTL_GIGA_MAC_VER_49:
5563                 rtl_hw_start_8168ep_1(tp);
5564                 break;
5565
5566         case RTL_GIGA_MAC_VER_50:
5567                 rtl_hw_start_8168ep_2(tp);
5568                 break;
5569
5570         case RTL_GIGA_MAC_VER_51:
5571                 rtl_hw_start_8168ep_3(tp);
5572                 break;
5573
5574         default:
5575                 netif_err(tp, drv, tp->dev,
5576                           "unknown chipset (mac_version = %d)\n",
5577                           tp->mac_version);
5578                 break;
5579         }
5580 }
5581
5582 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5583 {
5584         static const struct ephy_info e_info_8102e_1[] = {
5585                 { 0x01, 0, 0x6e65 },
5586                 { 0x02, 0, 0x091f },
5587                 { 0x03, 0, 0xc2f9 },
5588                 { 0x06, 0, 0xafb5 },
5589                 { 0x07, 0, 0x0e00 },
5590                 { 0x19, 0, 0xec80 },
5591                 { 0x01, 0, 0x2e65 },
5592                 { 0x01, 0, 0x6e65 }
5593         };
5594         u8 cfg1;
5595
5596         rtl_set_def_aspm_entry_latency(tp);
5597
5598         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5599
5600         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5601
5602         RTL_W8(tp, Config1,
5603                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5604         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5605
5606         cfg1 = RTL_R8(tp, Config1);
5607         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5608                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5609
5610         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5611 }
5612
5613 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5614 {
5615         rtl_set_def_aspm_entry_latency(tp);
5616
5617         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5618
5619         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5620         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5621 }
5622
5623 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5624 {
5625         rtl_hw_start_8102e_2(tp);
5626
5627         rtl_ephy_write(tp, 0x03, 0xc2f9);
5628 }
5629
5630 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5631 {
5632         static const struct ephy_info e_info_8105e_1[] = {
5633                 { 0x07, 0, 0x4000 },
5634                 { 0x19, 0, 0x0200 },
5635                 { 0x19, 0, 0x0020 },
5636                 { 0x1e, 0, 0x2000 },
5637                 { 0x03, 0, 0x0001 },
5638                 { 0x19, 0, 0x0100 },
5639                 { 0x19, 0, 0x0004 },
5640                 { 0x0a, 0, 0x0020 }
5641         };
5642
5643         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5644         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5645
5646         /* Disable Early Tally Counter */
5647         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5648
5649         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5650         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5651
5652         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5653
5654         rtl_pcie_state_l2l3_enable(tp, false);
5655 }
5656
5657 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5658 {
5659         rtl_hw_start_8105e_1(tp);
5660         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5661 }
5662
5663 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5664 {
5665         static const struct ephy_info e_info_8402[] = {
5666                 { 0x19, 0xffff, 0xff64 },
5667                 { 0x1e, 0, 0x4000 }
5668         };
5669
5670         rtl_set_def_aspm_entry_latency(tp);
5671
5672         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5673         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5674
5675         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5676         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5677
5678         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5679
5680         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5681
5682         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5683         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5684         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5685         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5686         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5687         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5688         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5689
5690         rtl_pcie_state_l2l3_enable(tp, false);
5691 }
5692
5693 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5694 {
5695         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5696         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5697
5698         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5699         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5700         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5701
5702         rtl_pcie_state_l2l3_enable(tp, false);
5703 }
5704
5705 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5706 {
5707         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5708                 tp->event_slow &= ~RxFIFOOver;
5709
5710         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5711             tp->mac_version == RTL_GIGA_MAC_VER_16)
5712                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5713                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5714
5715         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5716
5717         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5718         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5719
5720         switch (tp->mac_version) {
5721         case RTL_GIGA_MAC_VER_07:
5722                 rtl_hw_start_8102e_1(tp);
5723                 break;
5724
5725         case RTL_GIGA_MAC_VER_08:
5726                 rtl_hw_start_8102e_3(tp);
5727                 break;
5728
5729         case RTL_GIGA_MAC_VER_09:
5730                 rtl_hw_start_8102e_2(tp);
5731                 break;
5732
5733         case RTL_GIGA_MAC_VER_29:
5734                 rtl_hw_start_8105e_1(tp);
5735                 break;
5736         case RTL_GIGA_MAC_VER_30:
5737                 rtl_hw_start_8105e_2(tp);
5738                 break;
5739
5740         case RTL_GIGA_MAC_VER_37:
5741                 rtl_hw_start_8402(tp);
5742                 break;
5743
5744         case RTL_GIGA_MAC_VER_39:
5745                 rtl_hw_start_8106(tp);
5746                 break;
5747         case RTL_GIGA_MAC_VER_43:
5748                 rtl_hw_start_8168g_2(tp);
5749                 break;
5750         case RTL_GIGA_MAC_VER_47:
5751         case RTL_GIGA_MAC_VER_48:
5752                 rtl_hw_start_8168h_1(tp);
5753                 break;
5754         }
5755
5756         RTL_W16(tp, IntrMitigate, 0x0000);
5757 }
5758
5759 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5760 {
5761         struct rtl8169_private *tp = netdev_priv(dev);
5762
5763         if (new_mtu > ETH_DATA_LEN)
5764                 rtl_hw_jumbo_enable(tp);
5765         else
5766                 rtl_hw_jumbo_disable(tp);
5767
5768         dev->mtu = new_mtu;
5769         netdev_update_features(dev);
5770
5771         return 0;
5772 }
5773
5774 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5775 {
5776         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5777         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5778 }
5779
5780 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5781                                      void **data_buff, struct RxDesc *desc)
5782 {
5783         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5784                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5785
5786         kfree(*data_buff);
5787         *data_buff = NULL;
5788         rtl8169_make_unusable_by_asic(desc);
5789 }
5790
5791 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5792 {
5793         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5794
5795         /* Force memory writes to complete before releasing descriptor */
5796         dma_wmb();
5797
5798         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5799 }
5800
5801 static inline void *rtl8169_align(void *data)
5802 {
5803         return (void *)ALIGN((long)data, 16);
5804 }
5805
5806 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5807                                              struct RxDesc *desc)
5808 {
5809         void *data;
5810         dma_addr_t mapping;
5811         struct device *d = tp_to_dev(tp);
5812         int node = dev_to_node(d);
5813
5814         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5815         if (!data)
5816                 return NULL;
5817
5818         if (rtl8169_align(data) != data) {
5819                 kfree(data);
5820                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5821                 if (!data)
5822                         return NULL;
5823         }
5824
5825         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5826                                  DMA_FROM_DEVICE);
5827         if (unlikely(dma_mapping_error(d, mapping))) {
5828                 if (net_ratelimit())
5829                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5830                 goto err_out;
5831         }
5832
5833         desc->addr = cpu_to_le64(mapping);
5834         rtl8169_mark_to_asic(desc);
5835         return data;
5836
5837 err_out:
5838         kfree(data);
5839         return NULL;
5840 }
5841
5842 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5843 {
5844         unsigned int i;
5845
5846         for (i = 0; i < NUM_RX_DESC; i++) {
5847                 if (tp->Rx_databuff[i]) {
5848                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5849                                             tp->RxDescArray + i);
5850                 }
5851         }
5852 }
5853
5854 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5855 {
5856         desc->opts1 |= cpu_to_le32(RingEnd);
5857 }
5858
5859 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5860 {
5861         unsigned int i;
5862
5863         for (i = 0; i < NUM_RX_DESC; i++) {
5864                 void *data;
5865
5866                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5867                 if (!data) {
5868                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5869                         goto err_out;
5870                 }
5871                 tp->Rx_databuff[i] = data;
5872         }
5873
5874         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5875         return 0;
5876
5877 err_out:
5878         rtl8169_rx_clear(tp);
5879         return -ENOMEM;
5880 }
5881
5882 static int rtl8169_init_ring(struct rtl8169_private *tp)
5883 {
5884         rtl8169_init_ring_indexes(tp);
5885
5886         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5887         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5888
5889         return rtl8169_rx_fill(tp);
5890 }
5891
5892 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5893                                  struct TxDesc *desc)
5894 {
5895         unsigned int len = tx_skb->len;
5896
5897         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5898
5899         desc->opts1 = 0x00;
5900         desc->opts2 = 0x00;
5901         desc->addr = 0x00;
5902         tx_skb->len = 0;
5903 }
5904
5905 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5906                                    unsigned int n)
5907 {
5908         unsigned int i;
5909
5910         for (i = 0; i < n; i++) {
5911                 unsigned int entry = (start + i) % NUM_TX_DESC;
5912                 struct ring_info *tx_skb = tp->tx_skb + entry;
5913                 unsigned int len = tx_skb->len;
5914
5915                 if (len) {
5916                         struct sk_buff *skb = tx_skb->skb;
5917
5918                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5919                                              tp->TxDescArray + entry);
5920                         if (skb) {
5921                                 dev_consume_skb_any(skb);
5922                                 tx_skb->skb = NULL;
5923                         }
5924                 }
5925         }
5926 }
5927
5928 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5929 {
5930         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5931         tp->cur_tx = tp->dirty_tx = 0;
5932 }
5933
5934 static void rtl_reset_work(struct rtl8169_private *tp)
5935 {
5936         struct net_device *dev = tp->dev;
5937         int i;
5938
5939         napi_disable(&tp->napi);
5940         netif_stop_queue(dev);
5941         synchronize_sched();
5942
5943         rtl8169_hw_reset(tp);
5944
5945         for (i = 0; i < NUM_RX_DESC; i++)
5946                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5947
5948         rtl8169_tx_clear(tp);
5949         rtl8169_init_ring_indexes(tp);
5950
5951         napi_enable(&tp->napi);
5952         rtl_hw_start(tp);
5953         netif_wake_queue(dev);
5954 }
5955
5956 static void rtl8169_tx_timeout(struct net_device *dev)
5957 {
5958         struct rtl8169_private *tp = netdev_priv(dev);
5959
5960         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5961 }
5962
5963 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5964                               u32 *opts)
5965 {
5966         struct skb_shared_info *info = skb_shinfo(skb);
5967         unsigned int cur_frag, entry;
5968         struct TxDesc *uninitialized_var(txd);
5969         struct device *d = tp_to_dev(tp);
5970
5971         entry = tp->cur_tx;
5972         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5973                 const skb_frag_t *frag = info->frags + cur_frag;
5974                 dma_addr_t mapping;
5975                 u32 status, len;
5976                 void *addr;
5977
5978                 entry = (entry + 1) % NUM_TX_DESC;
5979
5980                 txd = tp->TxDescArray + entry;
5981                 len = skb_frag_size(frag);
5982                 addr = skb_frag_address(frag);
5983                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5984                 if (unlikely(dma_mapping_error(d, mapping))) {
5985                         if (net_ratelimit())
5986                                 netif_err(tp, drv, tp->dev,
5987                                           "Failed to map TX fragments DMA!\n");
5988                         goto err_out;
5989                 }
5990
5991                 /* Anti gcc 2.95.3 bugware (sic) */
5992                 status = opts[0] | len |
5993                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5994
5995                 txd->opts1 = cpu_to_le32(status);
5996                 txd->opts2 = cpu_to_le32(opts[1]);
5997                 txd->addr = cpu_to_le64(mapping);
5998
5999                 tp->tx_skb[entry].len = len;
6000         }
6001
6002         if (cur_frag) {
6003                 tp->tx_skb[entry].skb = skb;
6004                 txd->opts1 |= cpu_to_le32(LastFrag);
6005         }
6006
6007         return cur_frag;
6008
6009 err_out:
6010         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6011         return -EIO;
6012 }
6013
6014 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6015 {
6016         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6017 }
6018
6019 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6020                                       struct net_device *dev);
6021 /* r8169_csum_workaround()
6022  * The hw limites the value the transport offset. When the offset is out of the
6023  * range, calculate the checksum by sw.
6024  */
6025 static void r8169_csum_workaround(struct rtl8169_private *tp,
6026                                   struct sk_buff *skb)
6027 {
6028         if (skb_shinfo(skb)->gso_size) {
6029                 netdev_features_t features = tp->dev->features;
6030                 struct sk_buff *segs, *nskb;
6031
6032                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6033                 segs = skb_gso_segment(skb, features);
6034                 if (IS_ERR(segs) || !segs)
6035                         goto drop;
6036
6037                 do {
6038                         nskb = segs;
6039                         segs = segs->next;
6040                         nskb->next = NULL;
6041                         rtl8169_start_xmit(nskb, tp->dev);
6042                 } while (segs);
6043
6044                 dev_consume_skb_any(skb);
6045         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6046                 if (skb_checksum_help(skb) < 0)
6047                         goto drop;
6048
6049                 rtl8169_start_xmit(skb, tp->dev);
6050         } else {
6051                 struct net_device_stats *stats;
6052
6053 drop:
6054                 stats = &tp->dev->stats;
6055                 stats->tx_dropped++;
6056                 dev_kfree_skb_any(skb);
6057         }
6058 }
6059
6060 /* msdn_giant_send_check()
6061  * According to the document of microsoft, the TCP Pseudo Header excludes the
6062  * packet length for IPv6 TCP large packets.
6063  */
6064 static int msdn_giant_send_check(struct sk_buff *skb)
6065 {
6066         const struct ipv6hdr *ipv6h;
6067         struct tcphdr *th;
6068         int ret;
6069
6070         ret = skb_cow_head(skb, 0);
6071         if (ret)
6072                 return ret;
6073
6074         ipv6h = ipv6_hdr(skb);
6075         th = tcp_hdr(skb);
6076
6077         th->check = 0;
6078         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6079
6080         return ret;
6081 }
6082
6083 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6084                                 struct sk_buff *skb, u32 *opts)
6085 {
6086         u32 mss = skb_shinfo(skb)->gso_size;
6087
6088         if (mss) {
6089                 opts[0] |= TD_LSO;
6090                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6091         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6092                 const struct iphdr *ip = ip_hdr(skb);
6093
6094                 if (ip->protocol == IPPROTO_TCP)
6095                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6096                 else if (ip->protocol == IPPROTO_UDP)
6097                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6098                 else
6099                         WARN_ON_ONCE(1);
6100         }
6101
6102         return true;
6103 }
6104
6105 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6106                                 struct sk_buff *skb, u32 *opts)
6107 {
6108         u32 transport_offset = (u32)skb_transport_offset(skb);
6109         u32 mss = skb_shinfo(skb)->gso_size;
6110
6111         if (mss) {
6112                 if (transport_offset > GTTCPHO_MAX) {
6113                         netif_warn(tp, tx_err, tp->dev,
6114                                    "Invalid transport offset 0x%x for TSO\n",
6115                                    transport_offset);
6116                         return false;
6117                 }
6118
6119                 switch (vlan_get_protocol(skb)) {
6120                 case htons(ETH_P_IP):
6121                         opts[0] |= TD1_GTSENV4;
6122                         break;
6123
6124                 case htons(ETH_P_IPV6):
6125                         if (msdn_giant_send_check(skb))
6126                                 return false;
6127
6128                         opts[0] |= TD1_GTSENV6;
6129                         break;
6130
6131                 default:
6132                         WARN_ON_ONCE(1);
6133                         break;
6134                 }
6135
6136                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6137                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6138         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6139                 u8 ip_protocol;
6140
6141                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6142                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6143
6144                 if (transport_offset > TCPHO_MAX) {
6145                         netif_warn(tp, tx_err, tp->dev,
6146                                    "Invalid transport offset 0x%x\n",
6147                                    transport_offset);
6148                         return false;
6149                 }
6150
6151                 switch (vlan_get_protocol(skb)) {
6152                 case htons(ETH_P_IP):
6153                         opts[1] |= TD1_IPv4_CS;
6154                         ip_protocol = ip_hdr(skb)->protocol;
6155                         break;
6156
6157                 case htons(ETH_P_IPV6):
6158                         opts[1] |= TD1_IPv6_CS;
6159                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6160                         break;
6161
6162                 default:
6163                         ip_protocol = IPPROTO_RAW;
6164                         break;
6165                 }
6166
6167                 if (ip_protocol == IPPROTO_TCP)
6168                         opts[1] |= TD1_TCP_CS;
6169                 else if (ip_protocol == IPPROTO_UDP)
6170                         opts[1] |= TD1_UDP_CS;
6171                 else
6172                         WARN_ON_ONCE(1);
6173
6174                 opts[1] |= transport_offset << TCPHO_SHIFT;
6175         } else {
6176                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6177                         return !eth_skb_pad(skb);
6178         }
6179
6180         return true;
6181 }
6182
6183 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6184                                       struct net_device *dev)
6185 {
6186         struct rtl8169_private *tp = netdev_priv(dev);
6187         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6188         struct TxDesc *txd = tp->TxDescArray + entry;
6189         struct device *d = tp_to_dev(tp);
6190         dma_addr_t mapping;
6191         u32 status, len;
6192         u32 opts[2];
6193         int frags;
6194
6195         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6196                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6197                 goto err_stop_0;
6198         }
6199
6200         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6201                 goto err_stop_0;
6202
6203         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6204         opts[0] = DescOwn;
6205
6206         if (!tp->tso_csum(tp, skb, opts)) {
6207                 r8169_csum_workaround(tp, skb);
6208                 return NETDEV_TX_OK;
6209         }
6210
6211         len = skb_headlen(skb);
6212         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6213         if (unlikely(dma_mapping_error(d, mapping))) {
6214                 if (net_ratelimit())
6215                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6216                 goto err_dma_0;
6217         }
6218
6219         tp->tx_skb[entry].len = len;
6220         txd->addr = cpu_to_le64(mapping);
6221
6222         frags = rtl8169_xmit_frags(tp, skb, opts);
6223         if (frags < 0)
6224                 goto err_dma_1;
6225         else if (frags)
6226                 opts[0] |= FirstFrag;
6227         else {
6228                 opts[0] |= FirstFrag | LastFrag;
6229                 tp->tx_skb[entry].skb = skb;
6230         }
6231
6232         txd->opts2 = cpu_to_le32(opts[1]);
6233
6234         skb_tx_timestamp(skb);
6235
6236         /* Force memory writes to complete before releasing descriptor */
6237         dma_wmb();
6238
6239         /* Anti gcc 2.95.3 bugware (sic) */
6240         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6241         txd->opts1 = cpu_to_le32(status);
6242
6243         /* Force all memory writes to complete before notifying device */
6244         wmb();
6245
6246         tp->cur_tx += frags + 1;
6247
6248         RTL_W8(tp, TxPoll, NPQ);
6249
6250         mmiowb();
6251
6252         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6253                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6254                  * not miss a ring update when it notices a stopped queue.
6255                  */
6256                 smp_wmb();
6257                 netif_stop_queue(dev);
6258                 /* Sync with rtl_tx:
6259                  * - publish queue status and cur_tx ring index (write barrier)
6260                  * - refresh dirty_tx ring index (read barrier).
6261                  * May the current thread have a pessimistic view of the ring
6262                  * status and forget to wake up queue, a racing rtl_tx thread
6263                  * can't.
6264                  */
6265                 smp_mb();
6266                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6267                         netif_wake_queue(dev);
6268         }
6269
6270         return NETDEV_TX_OK;
6271
6272 err_dma_1:
6273         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6274 err_dma_0:
6275         dev_kfree_skb_any(skb);
6276         dev->stats.tx_dropped++;
6277         return NETDEV_TX_OK;
6278
6279 err_stop_0:
6280         netif_stop_queue(dev);
6281         dev->stats.tx_dropped++;
6282         return NETDEV_TX_BUSY;
6283 }
6284
6285 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6286 {
6287         struct rtl8169_private *tp = netdev_priv(dev);
6288         struct pci_dev *pdev = tp->pci_dev;
6289         u16 pci_status, pci_cmd;
6290
6291         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6292         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6293
6294         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6295                   pci_cmd, pci_status);
6296
6297         /*
6298          * The recovery sequence below admits a very elaborated explanation:
6299          * - it seems to work;
6300          * - I did not see what else could be done;
6301          * - it makes iop3xx happy.
6302          *
6303          * Feel free to adjust to your needs.
6304          */
6305         if (pdev->broken_parity_status)
6306                 pci_cmd &= ~PCI_COMMAND_PARITY;
6307         else
6308                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6309
6310         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6311
6312         pci_write_config_word(pdev, PCI_STATUS,
6313                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6314                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6315                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6316
6317         /* The infamous DAC f*ckup only happens at boot time */
6318         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6319                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6320                 tp->cp_cmd &= ~PCIDAC;
6321                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6322                 dev->features &= ~NETIF_F_HIGHDMA;
6323         }
6324
6325         rtl8169_hw_reset(tp);
6326
6327         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6328 }
6329
6330 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6331 {
6332         unsigned int dirty_tx, tx_left;
6333
6334         dirty_tx = tp->dirty_tx;
6335         smp_rmb();
6336         tx_left = tp->cur_tx - dirty_tx;
6337
6338         while (tx_left > 0) {
6339                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6340                 struct ring_info *tx_skb = tp->tx_skb + entry;
6341                 u32 status;
6342
6343                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6344                 if (status & DescOwn)
6345                         break;
6346
6347                 /* This barrier is needed to keep us from reading
6348                  * any other fields out of the Tx descriptor until
6349                  * we know the status of DescOwn
6350                  */
6351                 dma_rmb();
6352
6353                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6354                                      tp->TxDescArray + entry);
6355                 if (status & LastFrag) {
6356                         u64_stats_update_begin(&tp->tx_stats.syncp);
6357                         tp->tx_stats.packets++;
6358                         tp->tx_stats.bytes += tx_skb->skb->len;
6359                         u64_stats_update_end(&tp->tx_stats.syncp);
6360                         dev_consume_skb_any(tx_skb->skb);
6361                         tx_skb->skb = NULL;
6362                 }
6363                 dirty_tx++;
6364                 tx_left--;
6365         }
6366
6367         if (tp->dirty_tx != dirty_tx) {
6368                 tp->dirty_tx = dirty_tx;
6369                 /* Sync with rtl8169_start_xmit:
6370                  * - publish dirty_tx ring index (write barrier)
6371                  * - refresh cur_tx ring index and queue status (read barrier)
6372                  * May the current thread miss the stopped queue condition,
6373                  * a racing xmit thread can only have a right view of the
6374                  * ring status.
6375                  */
6376                 smp_mb();
6377                 if (netif_queue_stopped(dev) &&
6378                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6379                         netif_wake_queue(dev);
6380                 }
6381                 /*
6382                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6383                  * too close. Let's kick an extra TxPoll request when a burst
6384                  * of start_xmit activity is detected (if it is not detected,
6385                  * it is slow enough). -- FR
6386                  */
6387                 if (tp->cur_tx != dirty_tx)
6388                         RTL_W8(tp, TxPoll, NPQ);
6389         }
6390 }
6391
6392 static inline int rtl8169_fragmented_frame(u32 status)
6393 {
6394         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6395 }
6396
6397 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6398 {
6399         u32 status = opts1 & RxProtoMask;
6400
6401         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6402             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6403                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6404         else
6405                 skb_checksum_none_assert(skb);
6406 }
6407
6408 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6409                                            struct rtl8169_private *tp,
6410                                            int pkt_size,
6411                                            dma_addr_t addr)
6412 {
6413         struct sk_buff *skb;
6414         struct device *d = tp_to_dev(tp);
6415
6416         data = rtl8169_align(data);
6417         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6418         prefetch(data);
6419         skb = napi_alloc_skb(&tp->napi, pkt_size);
6420         if (skb)
6421                 skb_copy_to_linear_data(skb, data, pkt_size);
6422         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6423
6424         return skb;
6425 }
6426
6427 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6428 {
6429         unsigned int cur_rx, rx_left;
6430         unsigned int count;
6431
6432         cur_rx = tp->cur_rx;
6433
6434         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6435                 unsigned int entry = cur_rx % NUM_RX_DESC;
6436                 struct RxDesc *desc = tp->RxDescArray + entry;
6437                 u32 status;
6438
6439                 status = le32_to_cpu(desc->opts1);
6440                 if (status & DescOwn)
6441                         break;
6442
6443                 /* This barrier is needed to keep us from reading
6444                  * any other fields out of the Rx descriptor until
6445                  * we know the status of DescOwn
6446                  */
6447                 dma_rmb();
6448
6449                 if (unlikely(status & RxRES)) {
6450                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6451                                    status);
6452                         dev->stats.rx_errors++;
6453                         if (status & (RxRWT | RxRUNT))
6454                                 dev->stats.rx_length_errors++;
6455                         if (status & RxCRC)
6456                                 dev->stats.rx_crc_errors++;
6457                         /* RxFOVF is a reserved bit on later chip versions */
6458                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6459                             status & RxFOVF) {
6460                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6461                                 dev->stats.rx_fifo_errors++;
6462                         } else if (status & (RxRUNT | RxCRC) &&
6463                                    !(status & RxRWT) &&
6464                                    dev->features & NETIF_F_RXALL) {
6465                                 goto process_pkt;
6466                         }
6467                 } else {
6468                         struct sk_buff *skb;
6469                         dma_addr_t addr;
6470                         int pkt_size;
6471
6472 process_pkt:
6473                         addr = le64_to_cpu(desc->addr);
6474                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6475                                 pkt_size = (status & 0x00003fff) - 4;
6476                         else
6477                                 pkt_size = status & 0x00003fff;
6478
6479                         /*
6480                          * The driver does not support incoming fragmented
6481                          * frames. They are seen as a symptom of over-mtu
6482                          * sized frames.
6483                          */
6484                         if (unlikely(rtl8169_fragmented_frame(status))) {
6485                                 dev->stats.rx_dropped++;
6486                                 dev->stats.rx_length_errors++;
6487                                 goto release_descriptor;
6488                         }
6489
6490                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6491                                                   tp, pkt_size, addr);
6492                         if (!skb) {
6493                                 dev->stats.rx_dropped++;
6494                                 goto release_descriptor;
6495                         }
6496
6497                         rtl8169_rx_csum(skb, status);
6498                         skb_put(skb, pkt_size);
6499                         skb->protocol = eth_type_trans(skb, dev);
6500
6501                         rtl8169_rx_vlan_tag(desc, skb);
6502
6503                         if (skb->pkt_type == PACKET_MULTICAST)
6504                                 dev->stats.multicast++;
6505
6506                         napi_gro_receive(&tp->napi, skb);
6507
6508                         u64_stats_update_begin(&tp->rx_stats.syncp);
6509                         tp->rx_stats.packets++;
6510                         tp->rx_stats.bytes += pkt_size;
6511                         u64_stats_update_end(&tp->rx_stats.syncp);
6512                 }
6513 release_descriptor:
6514                 desc->opts2 = 0;
6515                 rtl8169_mark_to_asic(desc);
6516         }
6517
6518         count = cur_rx - tp->cur_rx;
6519         tp->cur_rx = cur_rx;
6520
6521         return count;
6522 }
6523
6524 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6525 {
6526         struct rtl8169_private *tp = dev_instance;
6527         int handled = 0;
6528         u16 status;
6529
6530         status = rtl_get_events(tp);
6531         if (status && status != 0xffff) {
6532                 status &= RTL_EVENT_NAPI | tp->event_slow;
6533                 if (status) {
6534                         handled = 1;
6535
6536                         rtl_irq_disable(tp);
6537                         napi_schedule_irqoff(&tp->napi);
6538                 }
6539         }
6540         return IRQ_RETVAL(handled);
6541 }
6542
6543 /*
6544  * Workqueue context.
6545  */
6546 static void rtl_slow_event_work(struct rtl8169_private *tp)
6547 {
6548         struct net_device *dev = tp->dev;
6549         u16 status;
6550
6551         status = rtl_get_events(tp) & tp->event_slow;
6552         rtl_ack_events(tp, status);
6553
6554         if (unlikely(status & RxFIFOOver)) {
6555                 switch (tp->mac_version) {
6556                 /* Work around for rx fifo overflow */
6557                 case RTL_GIGA_MAC_VER_11:
6558                         netif_stop_queue(dev);
6559                         /* XXX - Hack alert. See rtl_task(). */
6560                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6561                 default:
6562                         break;
6563                 }
6564         }
6565
6566         if (unlikely(status & SYSErr))
6567                 rtl8169_pcierr_interrupt(dev);
6568
6569         if (status & LinkChg)
6570                 phy_mac_interrupt(dev->phydev);
6571
6572         rtl_irq_enable_all(tp);
6573 }
6574
6575 static void rtl_task(struct work_struct *work)
6576 {
6577         static const struct {
6578                 int bitnr;
6579                 void (*action)(struct rtl8169_private *);
6580         } rtl_work[] = {
6581                 /* XXX - keep rtl_slow_event_work() as first element. */
6582                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6583                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6584         };
6585         struct rtl8169_private *tp =
6586                 container_of(work, struct rtl8169_private, wk.work);
6587         struct net_device *dev = tp->dev;
6588         int i;
6589
6590         rtl_lock_work(tp);
6591
6592         if (!netif_running(dev) ||
6593             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6594                 goto out_unlock;
6595
6596         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6597                 bool pending;
6598
6599                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6600                 if (pending)
6601                         rtl_work[i].action(tp);
6602         }
6603
6604 out_unlock:
6605         rtl_unlock_work(tp);
6606 }
6607
6608 static int rtl8169_poll(struct napi_struct *napi, int budget)
6609 {
6610         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6611         struct net_device *dev = tp->dev;
6612         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6613         int work_done= 0;
6614         u16 status;
6615
6616         status = rtl_get_events(tp);
6617         rtl_ack_events(tp, status & ~tp->event_slow);
6618
6619         if (status & RTL_EVENT_NAPI_RX)
6620                 work_done = rtl_rx(dev, tp, (u32) budget);
6621
6622         if (status & RTL_EVENT_NAPI_TX)
6623                 rtl_tx(dev, tp);
6624
6625         if (status & tp->event_slow) {
6626                 enable_mask &= ~tp->event_slow;
6627
6628                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6629         }
6630
6631         if (work_done < budget) {
6632                 napi_complete_done(napi, work_done);
6633
6634                 rtl_irq_enable(tp, enable_mask);
6635                 mmiowb();
6636         }
6637
6638         return work_done;
6639 }
6640
6641 static void rtl8169_rx_missed(struct net_device *dev)
6642 {
6643         struct rtl8169_private *tp = netdev_priv(dev);
6644
6645         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6646                 return;
6647
6648         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6649         RTL_W32(tp, RxMissed, 0);
6650 }
6651
6652 static void r8169_phylink_handler(struct net_device *ndev)
6653 {
6654         struct rtl8169_private *tp = netdev_priv(ndev);
6655
6656         if (netif_carrier_ok(ndev)) {
6657                 rtl_link_chg_patch(tp);
6658                 pm_request_resume(&tp->pci_dev->dev);
6659         } else {
6660                 pm_runtime_idle(&tp->pci_dev->dev);
6661         }
6662
6663         if (net_ratelimit())
6664                 phy_print_status(ndev->phydev);
6665 }
6666
6667 static int r8169_phy_connect(struct rtl8169_private *tp)
6668 {
6669         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6670         phy_interface_t phy_mode;
6671         int ret;
6672
6673         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6674                    PHY_INTERFACE_MODE_MII;
6675
6676         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6677                                  phy_mode);
6678         if (ret)
6679                 return ret;
6680
6681         if (!tp->supports_gmii)
6682                 phy_set_max_speed(phydev, SPEED_100);
6683
6684         /* Ensure to advertise everything, incl. pause */
6685         phydev->advertising = phydev->supported;
6686
6687         phy_attached_info(phydev);
6688
6689         return 0;
6690 }
6691
6692 static void rtl8169_down(struct net_device *dev)
6693 {
6694         struct rtl8169_private *tp = netdev_priv(dev);
6695
6696         phy_stop(dev->phydev);
6697
6698         napi_disable(&tp->napi);
6699         netif_stop_queue(dev);
6700
6701         rtl8169_hw_reset(tp);
6702         /*
6703          * At this point device interrupts can not be enabled in any function,
6704          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6705          * and napi is disabled (rtl8169_poll).
6706          */
6707         rtl8169_rx_missed(dev);
6708
6709         /* Give a racing hard_start_xmit a few cycles to complete. */
6710         synchronize_sched();
6711
6712         rtl8169_tx_clear(tp);
6713
6714         rtl8169_rx_clear(tp);
6715
6716         rtl_pll_power_down(tp);
6717 }
6718
6719 static int rtl8169_close(struct net_device *dev)
6720 {
6721         struct rtl8169_private *tp = netdev_priv(dev);
6722         struct pci_dev *pdev = tp->pci_dev;
6723
6724         pm_runtime_get_sync(&pdev->dev);
6725
6726         /* Update counters before going down */
6727         rtl8169_update_counters(tp);
6728
6729         rtl_lock_work(tp);
6730         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6731
6732         rtl8169_down(dev);
6733         rtl_unlock_work(tp);
6734
6735         cancel_work_sync(&tp->wk.work);
6736
6737         phy_disconnect(dev->phydev);
6738
6739         pci_free_irq(pdev, 0, tp);
6740
6741         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6742                           tp->RxPhyAddr);
6743         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6744                           tp->TxPhyAddr);
6745         tp->TxDescArray = NULL;
6746         tp->RxDescArray = NULL;
6747
6748         pm_runtime_put_sync(&pdev->dev);
6749
6750         return 0;
6751 }
6752
6753 #ifdef CONFIG_NET_POLL_CONTROLLER
6754 static void rtl8169_netpoll(struct net_device *dev)
6755 {
6756         struct rtl8169_private *tp = netdev_priv(dev);
6757
6758         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6759 }
6760 #endif
6761
6762 static int rtl_open(struct net_device *dev)
6763 {
6764         struct rtl8169_private *tp = netdev_priv(dev);
6765         struct pci_dev *pdev = tp->pci_dev;
6766         int retval = -ENOMEM;
6767
6768         pm_runtime_get_sync(&pdev->dev);
6769
6770         /*
6771          * Rx and Tx descriptors needs 256 bytes alignment.
6772          * dma_alloc_coherent provides more.
6773          */
6774         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6775                                              &tp->TxPhyAddr, GFP_KERNEL);
6776         if (!tp->TxDescArray)
6777                 goto err_pm_runtime_put;
6778
6779         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6780                                              &tp->RxPhyAddr, GFP_KERNEL);
6781         if (!tp->RxDescArray)
6782                 goto err_free_tx_0;
6783
6784         retval = rtl8169_init_ring(tp);
6785         if (retval < 0)
6786                 goto err_free_rx_1;
6787
6788         INIT_WORK(&tp->wk.work, rtl_task);
6789
6790         smp_mb();
6791
6792         rtl_request_firmware(tp);
6793
6794         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6795                                  dev->name);
6796         if (retval < 0)
6797                 goto err_release_fw_2;
6798
6799         retval = r8169_phy_connect(tp);
6800         if (retval)
6801                 goto err_free_irq;
6802
6803         rtl_lock_work(tp);
6804
6805         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6806
6807         napi_enable(&tp->napi);
6808
6809         rtl8169_init_phy(dev, tp);
6810
6811         rtl_pll_power_up(tp);
6812
6813         rtl_hw_start(tp);
6814
6815         if (!rtl8169_init_counter_offsets(tp))
6816                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6817
6818         phy_start(dev->phydev);
6819         netif_start_queue(dev);
6820
6821         rtl_unlock_work(tp);
6822
6823         pm_runtime_put_sync(&pdev->dev);
6824 out:
6825         return retval;
6826
6827 err_free_irq:
6828         pci_free_irq(pdev, 0, tp);
6829 err_release_fw_2:
6830         rtl_release_firmware(tp);
6831         rtl8169_rx_clear(tp);
6832 err_free_rx_1:
6833         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6834                           tp->RxPhyAddr);
6835         tp->RxDescArray = NULL;
6836 err_free_tx_0:
6837         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6838                           tp->TxPhyAddr);
6839         tp->TxDescArray = NULL;
6840 err_pm_runtime_put:
6841         pm_runtime_put_noidle(&pdev->dev);
6842         goto out;
6843 }
6844
6845 static void
6846 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6847 {
6848         struct rtl8169_private *tp = netdev_priv(dev);
6849         struct pci_dev *pdev = tp->pci_dev;
6850         struct rtl8169_counters *counters = tp->counters;
6851         unsigned int start;
6852
6853         pm_runtime_get_noresume(&pdev->dev);
6854
6855         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6856                 rtl8169_rx_missed(dev);
6857
6858         do {
6859                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6860                 stats->rx_packets = tp->rx_stats.packets;
6861                 stats->rx_bytes = tp->rx_stats.bytes;
6862         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6863
6864         do {
6865                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6866                 stats->tx_packets = tp->tx_stats.packets;
6867                 stats->tx_bytes = tp->tx_stats.bytes;
6868         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6869
6870         stats->rx_dropped       = dev->stats.rx_dropped;
6871         stats->tx_dropped       = dev->stats.tx_dropped;
6872         stats->rx_length_errors = dev->stats.rx_length_errors;
6873         stats->rx_errors        = dev->stats.rx_errors;
6874         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6875         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6876         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6877         stats->multicast        = dev->stats.multicast;
6878
6879         /*
6880          * Fetch additonal counter values missing in stats collected by driver
6881          * from tally counters.
6882          */
6883         if (pm_runtime_active(&pdev->dev))
6884                 rtl8169_update_counters(tp);
6885
6886         /*
6887          * Subtract values fetched during initalization.
6888          * See rtl8169_init_counter_offsets for a description why we do that.
6889          */
6890         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6891                 le64_to_cpu(tp->tc_offset.tx_errors);
6892         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6893                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6894         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6895                 le16_to_cpu(tp->tc_offset.tx_aborted);
6896
6897         pm_runtime_put_noidle(&pdev->dev);
6898 }
6899
6900 static void rtl8169_net_suspend(struct net_device *dev)
6901 {
6902         struct rtl8169_private *tp = netdev_priv(dev);
6903
6904         if (!netif_running(dev))
6905                 return;
6906
6907         phy_stop(dev->phydev);
6908         netif_device_detach(dev);
6909         netif_stop_queue(dev);
6910
6911         rtl_lock_work(tp);
6912         napi_disable(&tp->napi);
6913         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6914         rtl_unlock_work(tp);
6915
6916         rtl_pll_power_down(tp);
6917 }
6918
6919 #ifdef CONFIG_PM
6920
6921 static int rtl8169_suspend(struct device *device)
6922 {
6923         struct pci_dev *pdev = to_pci_dev(device);
6924         struct net_device *dev = pci_get_drvdata(pdev);
6925
6926         rtl8169_net_suspend(dev);
6927
6928         return 0;
6929 }
6930
6931 static void __rtl8169_resume(struct net_device *dev)
6932 {
6933         struct rtl8169_private *tp = netdev_priv(dev);
6934
6935         netif_device_attach(dev);
6936
6937         rtl_pll_power_up(tp);
6938         rtl8169_init_phy(dev, tp);
6939
6940         phy_start(tp->dev->phydev);
6941
6942         rtl_lock_work(tp);
6943         napi_enable(&tp->napi);
6944         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6945         rtl_unlock_work(tp);
6946
6947         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6948 }
6949
6950 static int rtl8169_resume(struct device *device)
6951 {
6952         struct pci_dev *pdev = to_pci_dev(device);
6953         struct net_device *dev = pci_get_drvdata(pdev);
6954
6955         if (netif_running(dev))
6956                 __rtl8169_resume(dev);
6957
6958         return 0;
6959 }
6960
6961 static int rtl8169_runtime_suspend(struct device *device)
6962 {
6963         struct pci_dev *pdev = to_pci_dev(device);
6964         struct net_device *dev = pci_get_drvdata(pdev);
6965         struct rtl8169_private *tp = netdev_priv(dev);
6966
6967         if (!tp->TxDescArray) {
6968                 rtl_pll_power_down(tp);
6969                 return 0;
6970         }
6971
6972         rtl_lock_work(tp);
6973         __rtl8169_set_wol(tp, WAKE_ANY);
6974         rtl_unlock_work(tp);
6975
6976         rtl8169_net_suspend(dev);
6977
6978         /* Update counters before going runtime suspend */
6979         rtl8169_rx_missed(dev);
6980         rtl8169_update_counters(tp);
6981
6982         return 0;
6983 }
6984
6985 static int rtl8169_runtime_resume(struct device *device)
6986 {
6987         struct pci_dev *pdev = to_pci_dev(device);
6988         struct net_device *dev = pci_get_drvdata(pdev);
6989         struct rtl8169_private *tp = netdev_priv(dev);
6990         rtl_rar_set(tp, dev->dev_addr);
6991
6992         if (!tp->TxDescArray)
6993                 return 0;
6994
6995         rtl_lock_work(tp);
6996         __rtl8169_set_wol(tp, tp->saved_wolopts);
6997         rtl_unlock_work(tp);
6998
6999         __rtl8169_resume(dev);
7000
7001         return 0;
7002 }
7003
7004 static int rtl8169_runtime_idle(struct device *device)
7005 {
7006         struct pci_dev *pdev = to_pci_dev(device);
7007         struct net_device *dev = pci_get_drvdata(pdev);
7008
7009         if (!netif_running(dev) || !netif_carrier_ok(dev))
7010                 pm_schedule_suspend(device, 10000);
7011
7012         return -EBUSY;
7013 }
7014
7015 static const struct dev_pm_ops rtl8169_pm_ops = {
7016         .suspend                = rtl8169_suspend,
7017         .resume                 = rtl8169_resume,
7018         .freeze                 = rtl8169_suspend,
7019         .thaw                   = rtl8169_resume,
7020         .poweroff               = rtl8169_suspend,
7021         .restore                = rtl8169_resume,
7022         .runtime_suspend        = rtl8169_runtime_suspend,
7023         .runtime_resume         = rtl8169_runtime_resume,
7024         .runtime_idle           = rtl8169_runtime_idle,
7025 };
7026
7027 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7028
7029 #else /* !CONFIG_PM */
7030
7031 #define RTL8169_PM_OPS  NULL
7032
7033 #endif /* !CONFIG_PM */
7034
7035 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7036 {
7037         /* WoL fails with 8168b when the receiver is disabled. */
7038         switch (tp->mac_version) {
7039         case RTL_GIGA_MAC_VER_11:
7040         case RTL_GIGA_MAC_VER_12:
7041         case RTL_GIGA_MAC_VER_17:
7042                 pci_clear_master(tp->pci_dev);
7043
7044                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7045                 /* PCI commit */
7046                 RTL_R8(tp, ChipCmd);
7047                 break;
7048         default:
7049                 break;
7050         }
7051 }
7052
7053 static void rtl_shutdown(struct pci_dev *pdev)
7054 {
7055         struct net_device *dev = pci_get_drvdata(pdev);
7056         struct rtl8169_private *tp = netdev_priv(dev);
7057
7058         rtl8169_net_suspend(dev);
7059
7060         /* Restore original MAC address */
7061         rtl_rar_set(tp, dev->perm_addr);
7062
7063         rtl8169_hw_reset(tp);
7064
7065         if (system_state == SYSTEM_POWER_OFF) {
7066                 if (tp->saved_wolopts) {
7067                         rtl_wol_suspend_quirk(tp);
7068                         rtl_wol_shutdown_quirk(tp);
7069                 }
7070
7071                 pci_wake_from_d3(pdev, true);
7072                 pci_set_power_state(pdev, PCI_D3hot);
7073         }
7074 }
7075
7076 static void rtl_remove_one(struct pci_dev *pdev)
7077 {
7078         struct net_device *dev = pci_get_drvdata(pdev);
7079         struct rtl8169_private *tp = netdev_priv(dev);
7080
7081         if (r8168_check_dash(tp))
7082                 rtl8168_driver_stop(tp);
7083
7084         netif_napi_del(&tp->napi);
7085
7086         unregister_netdev(dev);
7087         mdiobus_unregister(tp->mii_bus);
7088
7089         rtl_release_firmware(tp);
7090
7091         if (pci_dev_run_wake(pdev))
7092                 pm_runtime_get_noresume(&pdev->dev);
7093
7094         /* restore original MAC address */
7095         rtl_rar_set(tp, dev->perm_addr);
7096 }
7097
7098 static const struct net_device_ops rtl_netdev_ops = {
7099         .ndo_open               = rtl_open,
7100         .ndo_stop               = rtl8169_close,
7101         .ndo_get_stats64        = rtl8169_get_stats64,
7102         .ndo_start_xmit         = rtl8169_start_xmit,
7103         .ndo_tx_timeout         = rtl8169_tx_timeout,
7104         .ndo_validate_addr      = eth_validate_addr,
7105         .ndo_change_mtu         = rtl8169_change_mtu,
7106         .ndo_fix_features       = rtl8169_fix_features,
7107         .ndo_set_features       = rtl8169_set_features,
7108         .ndo_set_mac_address    = rtl_set_mac_address,
7109         .ndo_do_ioctl           = rtl8169_ioctl,
7110         .ndo_set_rx_mode        = rtl_set_rx_mode,
7111 #ifdef CONFIG_NET_POLL_CONTROLLER
7112         .ndo_poll_controller    = rtl8169_netpoll,
7113 #endif
7114
7115 };
7116
7117 static const struct rtl_cfg_info {
7118         void (*hw_start)(struct rtl8169_private *tp);
7119         u16 event_slow;
7120         unsigned int has_gmii:1;
7121         const struct rtl_coalesce_info *coalesce_info;
7122         u8 default_ver;
7123 } rtl_cfg_infos [] = {
7124         [RTL_CFG_0] = {
7125                 .hw_start       = rtl_hw_start_8169,
7126                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7127                 .has_gmii       = 1,
7128                 .coalesce_info  = rtl_coalesce_info_8169,
7129                 .default_ver    = RTL_GIGA_MAC_VER_01,
7130         },
7131         [RTL_CFG_1] = {
7132                 .hw_start       = rtl_hw_start_8168,
7133                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7134                 .has_gmii       = 1,
7135                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7136                 .default_ver    = RTL_GIGA_MAC_VER_11,
7137         },
7138         [RTL_CFG_2] = {
7139                 .hw_start       = rtl_hw_start_8101,
7140                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7141                                   PCSTimeout,
7142                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7143                 .default_ver    = RTL_GIGA_MAC_VER_13,
7144         }
7145 };
7146
7147 static int rtl_alloc_irq(struct rtl8169_private *tp)
7148 {
7149         unsigned int flags;
7150
7151         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7152                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7153                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7154                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7155                 flags = PCI_IRQ_LEGACY;
7156         } else {
7157                 flags = PCI_IRQ_ALL_TYPES;
7158         }
7159
7160         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7161 }
7162
7163 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7164 {
7165         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7166 }
7167
7168 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7169 {
7170         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7171 }
7172
7173 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7174 {
7175         struct rtl8169_private *tp = mii_bus->priv;
7176
7177         if (phyaddr > 0)
7178                 return -ENODEV;
7179
7180         return rtl_readphy(tp, phyreg);
7181 }
7182
7183 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7184                                 int phyreg, u16 val)
7185 {
7186         struct rtl8169_private *tp = mii_bus->priv;
7187
7188         if (phyaddr > 0)
7189                 return -ENODEV;
7190
7191         rtl_writephy(tp, phyreg, val);
7192
7193         return 0;
7194 }
7195
7196 static int r8169_mdio_register(struct rtl8169_private *tp)
7197 {
7198         struct pci_dev *pdev = tp->pci_dev;
7199         struct phy_device *phydev;
7200         struct mii_bus *new_bus;
7201         int ret;
7202
7203         new_bus = devm_mdiobus_alloc(&pdev->dev);
7204         if (!new_bus)
7205                 return -ENOMEM;
7206
7207         new_bus->name = "r8169";
7208         new_bus->priv = tp;
7209         new_bus->parent = &pdev->dev;
7210         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7211         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7212                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7213
7214         new_bus->read = r8169_mdio_read_reg;
7215         new_bus->write = r8169_mdio_write_reg;
7216
7217         ret = mdiobus_register(new_bus);
7218         if (ret)
7219                 return ret;
7220
7221         phydev = mdiobus_get_phy(new_bus, 0);
7222         if (!phydev) {
7223                 mdiobus_unregister(new_bus);
7224                 return -ENODEV;
7225         }
7226
7227         /* PHY will be woken up in rtl_open() */
7228         phy_suspend(phydev);
7229
7230         tp->mii_bus = new_bus;
7231
7232         return 0;
7233 }
7234
7235 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7236 {
7237         u32 data;
7238
7239         tp->ocp_base = OCP_STD_PHY_BASE;
7240
7241         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7242
7243         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7244                 return;
7245
7246         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7247                 return;
7248
7249         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7250         msleep(1);
7251         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7252
7253         data = r8168_mac_ocp_read(tp, 0xe8de);
7254         data &= ~(1 << 14);
7255         r8168_mac_ocp_write(tp, 0xe8de, data);
7256
7257         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7258                 return;
7259
7260         data = r8168_mac_ocp_read(tp, 0xe8de);
7261         data |= (1 << 15);
7262         r8168_mac_ocp_write(tp, 0xe8de, data);
7263
7264         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7265                 return;
7266 }
7267
7268 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7269 {
7270         rtl8168ep_stop_cmac(tp);
7271         rtl_hw_init_8168g(tp);
7272 }
7273
7274 static void rtl_hw_initialize(struct rtl8169_private *tp)
7275 {
7276         switch (tp->mac_version) {
7277         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7278                 rtl_hw_init_8168g(tp);
7279                 break;
7280         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7281                 rtl_hw_init_8168ep(tp);
7282                 break;
7283         default:
7284                 break;
7285         }
7286 }
7287
7288 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7289 {
7290         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7291         struct rtl8169_private *tp;
7292         struct net_device *dev;
7293         int chipset, region, i;
7294         int rc;
7295
7296         if (netif_msg_drv(&debug)) {
7297                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7298                        MODULENAME, RTL8169_VERSION);
7299         }
7300
7301         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7302         if (!dev)
7303                 return -ENOMEM;
7304
7305         SET_NETDEV_DEV(dev, &pdev->dev);
7306         dev->netdev_ops = &rtl_netdev_ops;
7307         tp = netdev_priv(dev);
7308         tp->dev = dev;
7309         tp->pci_dev = pdev;
7310         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7311         tp->supports_gmii = cfg->has_gmii;
7312
7313         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7314         rc = pcim_enable_device(pdev);
7315         if (rc < 0) {
7316                 dev_err(&pdev->dev, "enable failure\n");
7317                 return rc;
7318         }
7319
7320         if (pcim_set_mwi(pdev) < 0)
7321                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7322
7323         /* use first MMIO region */
7324         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7325         if (region < 0) {
7326                 dev_err(&pdev->dev, "no MMIO resource found\n");
7327                 return -ENODEV;
7328         }
7329
7330         /* check for weird/broken PCI region reporting */
7331         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7332                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7333                 return -ENODEV;
7334         }
7335
7336         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7337         if (rc < 0) {
7338                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7339                 return rc;
7340         }
7341
7342         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7343
7344         if (!pci_is_pcie(pdev))
7345                 dev_info(&pdev->dev, "not PCI Express\n");
7346
7347         /* Identify chip attached to board */
7348         rtl8169_get_mac_version(tp, cfg->default_ver);
7349
7350         if (rtl_tbi_enabled(tp)) {
7351                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7352                 return -ENODEV;
7353         }
7354
7355         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7356
7357         if ((sizeof(dma_addr_t) > 4) &&
7358             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7359                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7360             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7361             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7362
7363                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7364                 if (!pci_is_pcie(pdev))
7365                         tp->cp_cmd |= PCIDAC;
7366                 dev->features |= NETIF_F_HIGHDMA;
7367         } else {
7368                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7369                 if (rc < 0) {
7370                         dev_err(&pdev->dev, "DMA configuration failed\n");
7371                         return rc;
7372                 }
7373         }
7374
7375         rtl_init_rxcfg(tp);
7376
7377         rtl_irq_disable(tp);
7378
7379         rtl_hw_initialize(tp);
7380
7381         rtl_hw_reset(tp);
7382
7383         rtl_ack_events(tp, 0xffff);
7384
7385         pci_set_master(pdev);
7386
7387         rtl_init_mdio_ops(tp);
7388         rtl_init_jumbo_ops(tp);
7389
7390         rtl8169_print_mac_version(tp);
7391
7392         chipset = tp->mac_version;
7393
7394         rc = rtl_alloc_irq(tp);
7395         if (rc < 0) {
7396                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7397                 return rc;
7398         }
7399
7400         /* override BIOS settings, use userspace tools to enable WOL */
7401         __rtl8169_set_wol(tp, 0);
7402
7403         mutex_init(&tp->wk.mutex);
7404         u64_stats_init(&tp->rx_stats.syncp);
7405         u64_stats_init(&tp->tx_stats.syncp);
7406
7407         /* Get MAC address */
7408         switch (tp->mac_version) {
7409                 u8 mac_addr[ETH_ALEN] __aligned(4);
7410         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7411         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7412                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7413                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7414
7415                 if (is_valid_ether_addr(mac_addr))
7416                         rtl_rar_set(tp, mac_addr);
7417                 break;
7418         default:
7419                 break;
7420         }
7421         for (i = 0; i < ETH_ALEN; i++)
7422                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7423
7424         dev->ethtool_ops = &rtl8169_ethtool_ops;
7425         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7426
7427         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7428
7429         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7430          * properly for all devices */
7431         dev->features |= NETIF_F_RXCSUM |
7432                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7433
7434         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7435                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7436                 NETIF_F_HW_VLAN_CTAG_RX;
7437         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7438                 NETIF_F_HIGHDMA;
7439
7440         tp->cp_cmd |= RxChkSum | RxVlan;
7441
7442         /*
7443          * Pretend we are using VLANs; This bypasses a nasty bug where
7444          * Interrupts stop flowing on high load on 8110SCd controllers.
7445          */
7446         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7447                 /* Disallow toggling */
7448                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7449
7450         switch (rtl_chip_infos[chipset].txd_version) {
7451         case RTL_TD_0:
7452                 tp->tso_csum = rtl8169_tso_csum_v1;
7453                 break;
7454         case RTL_TD_1:
7455                 tp->tso_csum = rtl8169_tso_csum_v2;
7456                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7457                 break;
7458         default:
7459                 WARN_ON_ONCE(1);
7460         }
7461
7462         dev->hw_features |= NETIF_F_RXALL;
7463         dev->hw_features |= NETIF_F_RXFCS;
7464
7465         /* MTU range: 60 - hw-specific max */
7466         dev->min_mtu = ETH_ZLEN;
7467         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7468
7469         tp->hw_start = cfg->hw_start;
7470         tp->event_slow = cfg->event_slow;
7471         tp->coalesce_info = cfg->coalesce_info;
7472
7473         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7474
7475         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7476                                             &tp->counters_phys_addr,
7477                                             GFP_KERNEL);
7478         if (!tp->counters)
7479                 return -ENOMEM;
7480
7481         pci_set_drvdata(pdev, dev);
7482
7483         rc = r8169_mdio_register(tp);
7484         if (rc)
7485                 return rc;
7486
7487         rc = register_netdev(dev);
7488         if (rc)
7489                 goto err_mdio_unregister;
7490
7491         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7492                    rtl_chip_infos[chipset].name, dev->dev_addr,
7493                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7494                    pci_irq_vector(pdev, 0));
7495         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7496                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7497                            "tx checksumming: %s]\n",
7498                            rtl_chip_infos[chipset].jumbo_max,
7499                           tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
7500         }
7501
7502         if (r8168_check_dash(tp))
7503                 rtl8168_driver_start(tp);
7504
7505         if (pci_dev_run_wake(pdev))
7506                 pm_runtime_put_sync(&pdev->dev);
7507
7508         return 0;
7509
7510 err_mdio_unregister:
7511         mdiobus_unregister(tp->mii_bus);
7512         return rc;
7513 }
7514
7515 static struct pci_driver rtl8169_pci_driver = {
7516         .name           = MODULENAME,
7517         .id_table       = rtl8169_pci_tbl,
7518         .probe          = rtl_init_one,
7519         .remove         = rtl_remove_one,
7520         .shutdown       = rtl_shutdown,
7521         .driver.pm      = RTL8169_PM_OPS,
7522 };
7523
7524 module_pci_driver(rtl8169_pci_driver);