drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  49 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  50 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  51 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  52 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  53 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  54 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  55 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  56 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  57 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  58 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  59
  60 #ifdef RTL8169_DEBUG
  61 #define assert(expr) \
  62         if (!(expr)) {                                  \
  63                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  64                 #expr,__FILE__,__func__,__LINE__);              \
  65         }
  66 #define dprintk(fmt, args...) \
  67         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  68 #else
  69 #define assert(expr) do {} while (0)
  70 #define dprintk(fmt, args...)   do {} while (0)
  71 #endif /* RTL8169_DEBUG */
  72
  73 #define R8169_MSG_DEFAULT \
  74         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  75
  76 #define TX_SLOTS_AVAIL(tp) \
  77         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  78
  79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  81         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  82
  83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  84    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  85 static const int multicast_filter_limit = 32;
  86
  87 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  88 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  89
  90 #define R8169_REGS_SIZE         256
  91 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  92 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  93 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  94 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  95 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  96
  97 #define RTL8169_TX_TIMEOUT      (6*HZ)
  98 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  99
 100 /* write/read MMIO register */
 101 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
 102 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
 103 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
 104 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
 105 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
 106 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
 107
 108 enum mac_version {
 109         RTL_GIGA_MAC_VER_01 = 0,
 110         RTL_GIGA_MAC_VER_02,
 111         RTL_GIGA_MAC_VER_03,
 112         RTL_GIGA_MAC_VER_04,
 113         RTL_GIGA_MAC_VER_05,
 114         RTL_GIGA_MAC_VER_06,
 115         RTL_GIGA_MAC_VER_07,
 116         RTL_GIGA_MAC_VER_08,
 117         RTL_GIGA_MAC_VER_09,
 118         RTL_GIGA_MAC_VER_10,
 119         RTL_GIGA_MAC_VER_11,
 120         RTL_GIGA_MAC_VER_12,
 121         RTL_GIGA_MAC_VER_13,
 122         RTL_GIGA_MAC_VER_14,
 123         RTL_GIGA_MAC_VER_15,
 124         RTL_GIGA_MAC_VER_16,
 125         RTL_GIGA_MAC_VER_17,
 126         RTL_GIGA_MAC_VER_18,
 127         RTL_GIGA_MAC_VER_19,
 128         RTL_GIGA_MAC_VER_20,
 129         RTL_GIGA_MAC_VER_21,
 130         RTL_GIGA_MAC_VER_22,
 131         RTL_GIGA_MAC_VER_23,
 132         RTL_GIGA_MAC_VER_24,
 133         RTL_GIGA_MAC_VER_25,
 134         RTL_GIGA_MAC_VER_26,
 135         RTL_GIGA_MAC_VER_27,
 136         RTL_GIGA_MAC_VER_28,
 137         RTL_GIGA_MAC_VER_29,
 138         RTL_GIGA_MAC_VER_30,
 139         RTL_GIGA_MAC_VER_31,
 140         RTL_GIGA_MAC_VER_32,
 141         RTL_GIGA_MAC_VER_33,
 142         RTL_GIGA_MAC_VER_34,
 143         RTL_GIGA_MAC_VER_35,
 144         RTL_GIGA_MAC_VER_36,
 145         RTL_GIGA_MAC_VER_37,
 146         RTL_GIGA_MAC_VER_38,
 147         RTL_GIGA_MAC_VER_39,
 148         RTL_GIGA_MAC_VER_40,
 149         RTL_GIGA_MAC_VER_41,
 150         RTL_GIGA_MAC_VER_42,
 151         RTL_GIGA_MAC_VER_43,
 152         RTL_GIGA_MAC_VER_44,
 153         RTL_GIGA_MAC_VER_45,
 154         RTL_GIGA_MAC_VER_46,
 155         RTL_GIGA_MAC_VER_47,
 156         RTL_GIGA_MAC_VER_48,
 157         RTL_GIGA_MAC_VER_49,
 158         RTL_GIGA_MAC_VER_50,
 159         RTL_GIGA_MAC_VER_51,
 160         RTL_GIGA_MAC_NONE   = 0xff,
 161 };
 162
 163 enum rtl_tx_desc_version {
 164         RTL_TD_0        = 0,
 165         RTL_TD_1        = 1,
 166 };
 167
 168 #define JUMBO_1K        ETH_DATA_LEN
 169 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 170 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 171 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 172 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 173
 174 #define _R(NAME,TD,FW,SZ,B) {   \
 175         .name = NAME,           \
 176         .txd_version = TD,      \
 177         .fw_name = FW,          \
 178         .jumbo_max = SZ,        \
 179         .jumbo_tx_csum = B      \
 180 }
 181
 182 static const struct {
 183         const char *name;
 184         enum rtl_tx_desc_version txd_version;
 185         const char *fw_name;
 186         u16 jumbo_max;
 187         bool jumbo_tx_csum;
 188 } rtl_chip_infos[] = {
 189         /* PCI devices. */
 190         [RTL_GIGA_MAC_VER_01] =
 191                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 192         [RTL_GIGA_MAC_VER_02] =
 193                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 194         [RTL_GIGA_MAC_VER_03] =
 195                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 196         [RTL_GIGA_MAC_VER_04] =
 197                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 198         [RTL_GIGA_MAC_VER_05] =
 199                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 200         [RTL_GIGA_MAC_VER_06] =
 201                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 202         /* PCI-E devices. */
 203         [RTL_GIGA_MAC_VER_07] =
 204                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 205         [RTL_GIGA_MAC_VER_08] =
 206                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 207         [RTL_GIGA_MAC_VER_09] =
 208                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 209         [RTL_GIGA_MAC_VER_10] =
 210                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 211         [RTL_GIGA_MAC_VER_11] =
 212                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 213         [RTL_GIGA_MAC_VER_12] =
 214                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 215         [RTL_GIGA_MAC_VER_13] =
 216                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 217         [RTL_GIGA_MAC_VER_14] =
 218                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 219         [RTL_GIGA_MAC_VER_15] =
 220                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 221         [RTL_GIGA_MAC_VER_16] =
 222                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 223         [RTL_GIGA_MAC_VER_17] =
 224                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 225         [RTL_GIGA_MAC_VER_18] =
 226                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 227         [RTL_GIGA_MAC_VER_19] =
 228                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 229         [RTL_GIGA_MAC_VER_20] =
 230                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 231         [RTL_GIGA_MAC_VER_21] =
 232                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 233         [RTL_GIGA_MAC_VER_22] =
 234                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 235         [RTL_GIGA_MAC_VER_23] =
 236                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 237         [RTL_GIGA_MAC_VER_24] =
 238                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 239         [RTL_GIGA_MAC_VER_25] =
 240                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 241                                                         JUMBO_9K, false),
 242         [RTL_GIGA_MAC_VER_26] =
 243                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 244                                                         JUMBO_9K, false),
 245         [RTL_GIGA_MAC_VER_27] =
 246                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 247         [RTL_GIGA_MAC_VER_28] =
 248                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_29] =
 250                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 251                                                         JUMBO_1K, true),
 252         [RTL_GIGA_MAC_VER_30] =
 253                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 254                                                         JUMBO_1K, true),
 255         [RTL_GIGA_MAC_VER_31] =
 256                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 257         [RTL_GIGA_MAC_VER_32] =
 258                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 259                                                         JUMBO_9K, false),
 260         [RTL_GIGA_MAC_VER_33] =
 261                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 262                                                         JUMBO_9K, false),
 263         [RTL_GIGA_MAC_VER_34] =
 264                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 265                                                         JUMBO_9K, false),
 266         [RTL_GIGA_MAC_VER_35] =
 267                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 268                                                         JUMBO_9K, false),
 269         [RTL_GIGA_MAC_VER_36] =
 270                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 271                                                         JUMBO_9K, false),
 272         [RTL_GIGA_MAC_VER_37] =
 273                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,
 274                                                         JUMBO_1K, true),
 275         [RTL_GIGA_MAC_VER_38] =
 276                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,
 277                                                         JUMBO_9K, false),
 278         [RTL_GIGA_MAC_VER_39] =
 279                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
 280                                                         JUMBO_1K, true),
 281         [RTL_GIGA_MAC_VER_40] =
 282                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
 283                                                         JUMBO_9K, false),
 284         [RTL_GIGA_MAC_VER_41] =
 285                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
 286         [RTL_GIGA_MAC_VER_42] =
 287                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
 288                                                         JUMBO_9K, false),
 289         [RTL_GIGA_MAC_VER_43] =
 290                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
 291                                                         JUMBO_1K, true),
 292         [RTL_GIGA_MAC_VER_44] =
 293                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
 294                                                         JUMBO_9K, false),
 295         [RTL_GIGA_MAC_VER_45] =
 296                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
 297                                                         JUMBO_9K, false),
 298         [RTL_GIGA_MAC_VER_46] =
 299                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
 300                                                         JUMBO_9K, false),
 301         [RTL_GIGA_MAC_VER_47] =
 302                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
 303                                                         JUMBO_1K, false),
 304         [RTL_GIGA_MAC_VER_48] =
 305                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
 306                                                         JUMBO_1K, false),
 307         [RTL_GIGA_MAC_VER_49] =
 308                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 309                                                         JUMBO_9K, false),
 310         [RTL_GIGA_MAC_VER_50] =
 311                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 312                                                         JUMBO_9K, false),
 313         [RTL_GIGA_MAC_VER_51] =
 314                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL,
 315                                                         JUMBO_9K, false),
 316 };
 317 #undef _R
 318
 319 enum cfg_version {
 320         RTL_CFG_0 = 0x00,
 321         RTL_CFG_1,
 322         RTL_CFG_2
 323 };
 324
 325 static const struct pci_device_id rtl8169_pci_tbl[] = {
 326         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 327         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 328         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 329         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 330         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 331         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 332         { PCI_VENDOR_ID_DLINK,                  0x4300,
 333                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 334         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 335         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 336         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 337         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 338         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 339                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 340         { 0x0001,                               0x8168,
 341                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 342         {0,},
 343 };
 344
 345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 346
 347 static int use_dac = -1;
 348 static struct {
 349         u32 msg_enable;
 350 } debug = { -1 };
 351
 352 enum rtl_registers {
 353         MAC0            = 0,    /* Ethernet hardware address. */
 354         MAC4            = 4,
 355         MAR0            = 8,    /* Multicast filter. */
 356         CounterAddrLow          = 0x10,
 357         CounterAddrHigh         = 0x14,
 358         TxDescStartAddrLow      = 0x20,
 359         TxDescStartAddrHigh     = 0x24,
 360         TxHDescStartAddrLow     = 0x28,
 361         TxHDescStartAddrHigh    = 0x2c,
 362         FLASH           = 0x30,
 363         ERSR            = 0x36,
 364         ChipCmd         = 0x37,
 365         TxPoll          = 0x38,
 366         IntrMask        = 0x3c,
 367         IntrStatus      = 0x3e,
 368
 369         TxConfig        = 0x40,
 370 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 371 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 372
 373         RxConfig        = 0x44,
 374 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 375 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 376 #define RXCFG_FIFO_SHIFT                13
 377                                         /* No threshold before first PCI xfer */
 378 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 379 #define RX_EARLY_OFF                    (1 << 11)
 380 #define RXCFG_DMA_SHIFT                 8
 381                                         /* Unlimited maximum PCI burst. */
 382 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 383
 384         RxMissed        = 0x4c,
 385         Cfg9346         = 0x50,
 386         Config0         = 0x51,
 387         Config1         = 0x52,
 388         Config2         = 0x53,
 389 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 390
 391         Config3         = 0x54,
 392         Config4         = 0x55,
 393         Config5         = 0x56,
 394         MultiIntr       = 0x5c,
 395         PHYAR           = 0x60,
 396         PHYstatus       = 0x6c,
 397         RxMaxSize       = 0xda,
 398         CPlusCmd        = 0xe0,
 399         IntrMitigate    = 0xe2,
 400
 401 #define RTL_COALESCE_MASK       0x0f
 402 #define RTL_COALESCE_SHIFT      4
 403 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 404 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 405
 406         RxDescAddrLow   = 0xe4,
 407         RxDescAddrHigh  = 0xe8,
 408         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 409
 410 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 411
 412         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 413
 414 #define TxPacketMax     (8064 >> 7)
 415 #define EarlySize       0x27
 416
 417         FuncEvent       = 0xf0,
 418         FuncEventMask   = 0xf4,
 419         FuncPresetState = 0xf8,
 420         IBCR0           = 0xf8,
 421         IBCR2           = 0xf9,
 422         IBIMR0          = 0xfa,
 423         IBISR0          = 0xfb,
 424         FuncForceEvent  = 0xfc,
 425 };
 426
 427 enum rtl8110_registers {
 428         TBICSR                  = 0x64,
 429         TBI_ANAR                = 0x68,
 430         TBI_LPAR                = 0x6a,
 431 };
 432
 433 enum rtl8168_8101_registers {
 434         CSIDR                   = 0x64,
 435         CSIAR                   = 0x68,
 436 #define CSIAR_FLAG                      0x80000000
 437 #define CSIAR_WRITE_CMD                 0x80000000
 438 #define CSIAR_BYTE_ENABLE               0x0f
 439 #define CSIAR_BYTE_ENABLE_SHIFT         12
 440 #define CSIAR_ADDR_MASK                 0x0fff
 441 #define CSIAR_FUNC_CARD                 0x00000000
 442 #define CSIAR_FUNC_SDIO                 0x00010000
 443 #define CSIAR_FUNC_NIC                  0x00020000
 444 #define CSIAR_FUNC_NIC2                 0x00010000
 445         PMCH                    = 0x6f,
 446         EPHYAR                  = 0x80,
 447 #define EPHYAR_FLAG                     0x80000000
 448 #define EPHYAR_WRITE_CMD                0x80000000
 449 #define EPHYAR_REG_MASK                 0x1f
 450 #define EPHYAR_REG_SHIFT                16
 451 #define EPHYAR_DATA_MASK                0xffff
 452         DLLPR                   = 0xd0,
 453 #define PFM_EN                          (1 << 6)
 454 #define TX_10M_PS_EN                    (1 << 7)
 455         DBG_REG                 = 0xd1,
 456 #define FIX_NAK_1                       (1 << 4)
 457 #define FIX_NAK_2                       (1 << 3)
 458         TWSI                    = 0xd2,
 459         MCU                     = 0xd3,
 460 #define NOW_IS_OOB                      (1 << 7)
 461 #define TX_EMPTY                        (1 << 5)
 462 #define RX_EMPTY                        (1 << 4)
 463 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 464 #define EN_NDP                          (1 << 3)
 465 #define EN_OOB_RESET                    (1 << 2)
 466 #define LINK_LIST_RDY                   (1 << 1)
 467         EFUSEAR                 = 0xdc,
 468 #define EFUSEAR_FLAG                    0x80000000
 469 #define EFUSEAR_WRITE_CMD               0x80000000
 470 #define EFUSEAR_READ_CMD                0x00000000
 471 #define EFUSEAR_REG_MASK                0x03ff
 472 #define EFUSEAR_REG_SHIFT               8
 473 #define EFUSEAR_DATA_MASK               0xff
 474         MISC_1                  = 0xf2,
 475 #define PFM_D3COLD_EN                   (1 << 6)
 476 };
 477
 478 enum rtl8168_registers {
 479         LED_FREQ                = 0x1a,
 480         EEE_LED                 = 0x1b,
 481         ERIDR                   = 0x70,
 482         ERIAR                   = 0x74,
 483 #define ERIAR_FLAG                      0x80000000
 484 #define ERIAR_WRITE_CMD                 0x80000000
 485 #define ERIAR_READ_CMD                  0x00000000
 486 #define ERIAR_ADDR_BYTE_ALIGN           4
 487 #define ERIAR_TYPE_SHIFT                16
 488 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 489 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 490 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 491 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 492 #define ERIAR_MASK_SHIFT                12
 493 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 494 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 495 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 496 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 497 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 498         EPHY_RXER_NUM           = 0x7c,
 499         OCPDR                   = 0xb0, /* OCP GPHY access */
 500 #define OCPDR_WRITE_CMD                 0x80000000
 501 #define OCPDR_READ_CMD                  0x00000000
 502 #define OCPDR_REG_MASK                  0x7f
 503 #define OCPDR_GPHY_REG_SHIFT            16
 504 #define OCPDR_DATA_MASK                 0xffff
 505         OCPAR                   = 0xb4,
 506 #define OCPAR_FLAG                      0x80000000
 507 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 508 #define OCPAR_GPHY_READ_CMD             0x0000f060
 509         GPHY_OCP                = 0xb8,
 510         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 511         MISC                    = 0xf0, /* 8168e only. */
 512 #define TXPLA_RST                       (1 << 29)
 513 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 514 #define PWM_EN                          (1 << 22)
 515 #define RXDV_GATED_EN                   (1 << 19)
 516 #define EARLY_TALLY_EN                  (1 << 16)
 517 };
 518
 519 enum rtl_register_content {
 520         /* InterruptStatusBits */
 521         SYSErr          = 0x8000,
 522         PCSTimeout      = 0x4000,
 523         SWInt           = 0x0100,
 524         TxDescUnavail   = 0x0080,
 525         RxFIFOOver      = 0x0040,
 526         LinkChg         = 0x0020,
 527         RxOverflow      = 0x0010,
 528         TxErr           = 0x0008,
 529         TxOK            = 0x0004,
 530         RxErr           = 0x0002,
 531         RxOK            = 0x0001,
 532
 533         /* RxStatusDesc */
 534         RxBOVF  = (1 << 24),
 535         RxFOVF  = (1 << 23),
 536         RxRWT   = (1 << 22),
 537         RxRES   = (1 << 21),
 538         RxRUNT  = (1 << 20),
 539         RxCRC   = (1 << 19),
 540
 541         /* ChipCmdBits */
 542         StopReq         = 0x80,
 543         CmdReset        = 0x10,
 544         CmdRxEnb        = 0x08,
 545         CmdTxEnb        = 0x04,
 546         RxBufEmpty      = 0x01,
 547
 548         /* TXPoll register p.5 */
 549         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 550         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 551         FSWInt          = 0x01,         /* Forced software interrupt */
 552
 553         /* Cfg9346Bits */
 554         Cfg9346_Lock    = 0x00,
 555         Cfg9346_Unlock  = 0xc0,
 556
 557         /* rx_mode_bits */
 558         AcceptErr       = 0x20,
 559         AcceptRunt      = 0x10,
 560         AcceptBroadcast = 0x08,
 561         AcceptMulticast = 0x04,
 562         AcceptMyPhys    = 0x02,
 563         AcceptAllPhys   = 0x01,
 564 #define RX_CONFIG_ACCEPT_MASK           0x3f
 565
 566         /* TxConfigBits */
 567         TxInterFrameGapShift = 24,
 568         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 569
 570         /* Config1 register p.24 */
 571         LEDS1           = (1 << 7),
 572         LEDS0           = (1 << 6),
 573         Speed_down      = (1 << 4),
 574         MEMMAP          = (1 << 3),
 575         IOMAP           = (1 << 2),
 576         VPD             = (1 << 1),
 577         PMEnable        = (1 << 0),     /* Power Management Enable */
 578
 579         /* Config2 register p. 25 */
 580         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 581         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 582         PCI_Clock_66MHz = 0x01,
 583         PCI_Clock_33MHz = 0x00,
 584
 585         /* Config3 register p.25 */
 586         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 587         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 588         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 589         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 590         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 591
 592         /* Config4 register */
 593         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 594
 595         /* Config5 register p.27 */
 596         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 597         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 598         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 599         Spi_en          = (1 << 3),
 600         LanWake         = (1 << 1),     /* LanWake enable/disable */
 601         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 602         ASPM_en         = (1 << 0),     /* ASPM enable */
 603
 604         /* TBICSR p.28 */
 605         TBIReset        = 0x80000000,
 606         TBILoopback     = 0x40000000,
 607         TBINwEnable     = 0x20000000,
 608         TBINwRestart    = 0x10000000,
 609         TBILinkOk       = 0x02000000,
 610         TBINwComplete   = 0x01000000,
 611
 612         /* CPlusCmd p.31 */
 613         EnableBist      = (1 << 15),    // 8168 8101
 614         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 615         Normal_mode     = (1 << 13),    // unused
 616         Force_half_dup  = (1 << 12),    // 8168 8101
 617         Force_rxflow_en = (1 << 11),    // 8168 8101
 618         Force_txflow_en = (1 << 10),    // 8168 8101
 619         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 620         ASF             = (1 << 8),     // 8168 8101
 621         PktCntrDisable  = (1 << 7),     // 8168 8101
 622         Mac_dbgo_sel    = 0x001c,       // 8168
 623         RxVlan          = (1 << 6),
 624         RxChkSum        = (1 << 5),
 625         PCIDAC          = (1 << 4),
 626         PCIMulRW        = (1 << 3),
 627         INTT_0          = 0x0000,       // 8168
 628         INTT_1          = 0x0001,       // 8168
 629         INTT_2          = 0x0002,       // 8168
 630         INTT_3          = 0x0003,       // 8168
 631
 632         /* rtl8169_PHYstatus */
 633         TBI_Enable      = 0x80,
 634         TxFlowCtrl      = 0x40,
 635         RxFlowCtrl      = 0x20,
 636         _1000bpsF       = 0x10,
 637         _100bps         = 0x08,
 638         _10bps          = 0x04,
 639         LinkStatus      = 0x02,
 640         FullDup         = 0x01,
 641
 642         /* _TBICSRBit */
 643         TBILinkOK       = 0x02000000,
 644
 645         /* ResetCounterCommand */
 646         CounterReset    = 0x1,
 647
 648         /* DumpCounterCommand */
 649         CounterDump     = 0x8,
 650
 651         /* magic enable v2 */
 652         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 653 };
 654
 655 enum rtl_desc_bit {
 656         /* First doubleword. */
 657         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 658         RingEnd         = (1 << 30), /* End of descriptor ring */
 659         FirstFrag       = (1 << 29), /* First segment of a packet */
 660         LastFrag        = (1 << 28), /* Final segment of a packet */
 661 };
 662
 663 /* Generic case. */
 664 enum rtl_tx_desc_bit {
 665         /* First doubleword. */
 666         TD_LSO          = (1 << 27),            /* Large Send Offload */
 667 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 668
 669         /* Second doubleword. */
 670         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 671 };
 672
 673 /* 8169, 8168b and 810x except 8102e. */
 674 enum rtl_tx_desc_bit_0 {
 675         /* First doubleword. */
 676 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 677         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 678         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 679         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 680 };
 681
 682 /* 8102e, 8168c and beyond. */
 683 enum rtl_tx_desc_bit_1 {
 684         /* First doubleword. */
 685         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 686         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 687 #define GTTCPHO_SHIFT                   18
 688 #define GTTCPHO_MAX                     0x7fU
 689
 690         /* Second doubleword. */
 691 #define TCPHO_SHIFT                     18
 692 #define TCPHO_MAX                       0x3ffU
 693 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 694         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 695         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 696         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 697         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 698 };
 699
 700 enum rtl_rx_desc_bit {
 701         /* Rx private */
 702         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 703         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 704
 705 #define RxProtoUDP      (PID1)
 706 #define RxProtoTCP      (PID0)
 707 #define RxProtoIP       (PID1 | PID0)
 708 #define RxProtoMask     RxProtoIP
 709
 710         IPFail          = (1 << 16), /* IP checksum failed */
 711         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 712         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 713         RxVlanTag       = (1 << 16), /* VLAN tag available */
 714 };
 715
 716 #define RsvdMask        0x3fffc000
 717
 718 struct TxDesc {
 719         __le32 opts1;
 720         __le32 opts2;
 721         __le64 addr;
 722 };
 723
 724 struct RxDesc {
 725         __le32 opts1;
 726         __le32 opts2;
 727         __le64 addr;
 728 };
 729
 730 struct ring_info {
 731         struct sk_buff  *skb;
 732         u32             len;
 733         u8              __pad[sizeof(void *) - sizeof(u32)];
 734 };
 735
 736 struct rtl8169_counters {
 737         __le64  tx_packets;
 738         __le64  rx_packets;
 739         __le64  tx_errors;
 740         __le32  rx_errors;
 741         __le16  rx_missed;
 742         __le16  align_errors;
 743         __le32  tx_one_collision;
 744         __le32  tx_multi_collision;
 745         __le64  rx_unicast;
 746         __le64  rx_broadcast;
 747         __le32  rx_multicast;
 748         __le16  tx_aborted;
 749         __le16  tx_underun;
 750 };
 751
 752 struct rtl8169_tc_offsets {
 753         bool    inited;
 754         __le64  tx_errors;
 755         __le32  tx_multi_collision;
 756         __le16  tx_aborted;
 757 };
 758
 759 enum rtl_flag {
 760         RTL_FLAG_TASK_ENABLED,
 761         RTL_FLAG_TASK_SLOW_PENDING,
 762         RTL_FLAG_TASK_RESET_PENDING,
 763         RTL_FLAG_TASK_PHY_PENDING,
 764         RTL_FLAG_MAX
 765 };
 766
 767 struct rtl8169_stats {
 768         u64                     packets;
 769         u64                     bytes;
 770         struct u64_stats_sync   syncp;
 771 };
 772
 773 struct rtl8169_private {
 774         void __iomem *mmio_addr;        /* memory map physical address */
 775         struct pci_dev *pci_dev;
 776         struct net_device *dev;
 777         struct napi_struct napi;
 778         u32 msg_enable;
 779         u16 txd_version;
 780         u16 mac_version;
 781         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 782         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 783         u32 dirty_tx;
 784         struct rtl8169_stats rx_stats;
 785         struct rtl8169_stats tx_stats;
 786         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 787         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 788         dma_addr_t TxPhyAddr;
 789         dma_addr_t RxPhyAddr;
 790         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 791         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 792         struct timer_list timer;
 793         u16 cp_cmd;
 794
 795         u16 event_slow;
 796         const struct rtl_coalesce_info *coalesce_info;
 797
 798         struct mdio_ops {
 799                 void (*write)(struct rtl8169_private *, int, int);
 800                 int (*read)(struct rtl8169_private *, int);
 801         } mdio_ops;
 802
 803         struct pll_power_ops {
 804                 void (*down)(struct rtl8169_private *);
 805                 void (*up)(struct rtl8169_private *);
 806         } pll_power_ops;
 807
 808         struct jumbo_ops {
 809                 void (*enable)(struct rtl8169_private *);
 810                 void (*disable)(struct rtl8169_private *);
 811         } jumbo_ops;
 812
 813         struct csi_ops {
 814                 void (*write)(struct rtl8169_private *, int, int);
 815                 u32 (*read)(struct rtl8169_private *, int);
 816         } csi_ops;
 817
 818         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 819         int (*get_link_ksettings)(struct net_device *,
 820                                   struct ethtool_link_ksettings *);
 821         void (*phy_reset_enable)(struct rtl8169_private *tp);
 822         void (*hw_start)(struct rtl8169_private *tp);
 823         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 824         unsigned int (*link_ok)(struct rtl8169_private *tp);
 825         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 826         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 827
 828         struct {
 829                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 830                 struct mutex mutex;
 831                 struct work_struct work;
 832         } wk;
 833
 834         struct mii_if_info mii;
 835         dma_addr_t counters_phys_addr;
 836         struct rtl8169_counters *counters;
 837         struct rtl8169_tc_offsets tc_offset;
 838         u32 saved_wolopts;
 839         u32 opts1_mask;
 840
 841         struct rtl_fw {
 842                 const struct firmware *fw;
 843
 844 #define RTL_VER_SIZE            32
 845
 846                 char version[RTL_VER_SIZE];
 847
 848                 struct rtl_fw_phy_action {
 849                         __le32 *code;
 850                         size_t size;
 851                 } phy_action;
 852         } *rtl_fw;
 853 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 854
 855         u32 ocp_base;
 856 };
 857
 858 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 859 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 860 module_param(use_dac, int, 0);
 861 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 862 module_param_named(debug, debug.msg_enable, int, 0);
 863 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 864 MODULE_LICENSE("GPL");
 865 MODULE_VERSION(RTL8169_VERSION);
 866 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 867 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 868 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 869 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 870 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 871 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 872 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 873 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 874 MODULE_FIRMWARE(FIRMWARE_8402_1);
 875 MODULE_FIRMWARE(FIRMWARE_8411_1);
 876 MODULE_FIRMWARE(FIRMWARE_8411_2);
 877 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 878 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 879 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 880 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 881 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 882 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 883 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 884 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 885
 886 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 887 {
 888         return &tp->pci_dev->dev;
 889 }
 890
 891 static void rtl_lock_work(struct rtl8169_private *tp)
 892 {
 893         mutex_lock(&tp->wk.mutex);
 894 }
 895
 896 static void rtl_unlock_work(struct rtl8169_private *tp)
 897 {
 898         mutex_unlock(&tp->wk.mutex);
 899 }
 900
 901 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 902 {
 903         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 904                                            PCI_EXP_DEVCTL_READRQ, force);
 905 }
 906
 907 struct rtl_cond {
 908         bool (*check)(struct rtl8169_private *);
 909         const char *msg;
 910 };
 911
 912 static void rtl_udelay(unsigned int d)
 913 {
 914         udelay(d);
 915 }
 916
 917 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 918                           void (*delay)(unsigned int), unsigned int d, int n,
 919                           bool high)
 920 {
 921         int i;
 922
 923         for (i = 0; i < n; i++) {
 924                 delay(d);
 925                 if (c->check(tp) == high)
 926                         return true;
 927         }
 928         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 929                   c->msg, !high, n, d);
 930         return false;
 931 }
 932
 933 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 934                                       const struct rtl_cond *c,
 935                                       unsigned int d, int n)
 936 {
 937         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 938 }
 939
 940 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 941                                      const struct rtl_cond *c,
 942                                      unsigned int d, int n)
 943 {
 944         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 945 }
 946
 947 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 948                                       const struct rtl_cond *c,
 949                                       unsigned int d, int n)
 950 {
 951         return rtl_loop_wait(tp, c, msleep, d, n, true);
 952 }
 953
 954 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 955                                      const struct rtl_cond *c,
 956                                      unsigned int d, int n)
 957 {
 958         return rtl_loop_wait(tp, c, msleep, d, n, false);
 959 }
 960
 961 #define DECLARE_RTL_COND(name)                          \
 962 static bool name ## _check(struct rtl8169_private *);   \
 963                                                         \
 964 static const struct rtl_cond name = {                   \
 965         .check  = name ## _check,                       \
 966         .msg    = #name                                 \
 967 };                                                      \
 968                                                         \
 969 static bool name ## _check(struct rtl8169_private *tp)
 970
 971 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 972 {
 973         if (reg & 0xffff0001) {
 974                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 975                 return true;
 976         }
 977         return false;
 978 }
 979
 980 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 981 {
 982         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 983 }
 984
 985 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 986 {
 987         if (rtl_ocp_reg_failure(tp, reg))
 988                 return;
 989
 990         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 991
 992         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 993 }
 994
 995 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 996 {
 997         if (rtl_ocp_reg_failure(tp, reg))
 998                 return 0;
 999
1000         RTL_W32(tp, GPHY_OCP, reg << 15);
1001
1002         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1003                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
1004 }
1005
1006 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1007 {
1008         if (rtl_ocp_reg_failure(tp, reg))
1009                 return;
1010
1011         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1012 }
1013
1014 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1015 {
1016         if (rtl_ocp_reg_failure(tp, reg))
1017                 return 0;
1018
1019         RTL_W32(tp, OCPDR, reg << 15);
1020
1021         return RTL_R32(tp, OCPDR);
1022 }
1023
1024 #define OCP_STD_PHY_BASE        0xa400
1025
1026 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1027 {
1028         if (reg == 0x1f) {
1029                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1030                 return;
1031         }
1032
1033         if (tp->ocp_base != OCP_STD_PHY_BASE)
1034                 reg -= 0x10;
1035
1036         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1037 }
1038
1039 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1040 {
1041         if (tp->ocp_base != OCP_STD_PHY_BASE)
1042                 reg -= 0x10;
1043
1044         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1045 }
1046
1047 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1048 {
1049         if (reg == 0x1f) {
1050                 tp->ocp_base = value << 4;
1051                 return;
1052         }
1053
1054         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1055 }
1056
1057 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1058 {
1059         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1060 }
1061
1062 DECLARE_RTL_COND(rtl_phyar_cond)
1063 {
1064         return RTL_R32(tp, PHYAR) & 0x80000000;
1065 }
1066
1067 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1068 {
1069         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1070
1071         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1072         /*
1073          * According to hardware specs a 20us delay is required after write
1074          * complete indication, but before sending next command.
1075          */
1076         udelay(20);
1077 }
1078
1079 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1080 {
1081         int value;
1082
1083         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1084
1085         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1086                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1087
1088         /*
1089          * According to hardware specs a 20us delay is required after read
1090          * complete indication, but before sending next command.
1091          */
1092         udelay(20);
1093
1094         return value;
1095 }
1096
1097 DECLARE_RTL_COND(rtl_ocpar_cond)
1098 {
1099         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1100 }
1101
1102 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1103 {
1104         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1105         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1106         RTL_W32(tp, EPHY_RXER_NUM, 0);
1107
1108         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1109 }
1110
1111 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1112 {
1113         r8168dp_1_mdio_access(tp, reg,
1114                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1115 }
1116
1117 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1118 {
1119         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1120
1121         mdelay(1);
1122         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1123         RTL_W32(tp, EPHY_RXER_NUM, 0);
1124
1125         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1126                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1127 }
1128
1129 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1130
1131 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1132 {
1133         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1134 }
1135
1136 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1137 {
1138         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1139 }
1140
1141 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1142 {
1143         r8168dp_2_mdio_start(tp);
1144
1145         r8169_mdio_write(tp, reg, value);
1146
1147         r8168dp_2_mdio_stop(tp);
1148 }
1149
1150 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1151 {
1152         int value;
1153
1154         r8168dp_2_mdio_start(tp);
1155
1156         value = r8169_mdio_read(tp, reg);
1157
1158         r8168dp_2_mdio_stop(tp);
1159
1160         return value;
1161 }
1162
1163 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1164 {
1165         tp->mdio_ops.write(tp, location, val);
1166 }
1167
1168 static int rtl_readphy(struct rtl8169_private *tp, int location)
1169 {
1170         return tp->mdio_ops.read(tp, location);
1171 }
1172
1173 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1174 {
1175         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1176 }
1177
1178 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1179 {
1180         int val;
1181
1182         val = rtl_readphy(tp, reg_addr);
1183         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1184 }
1185
1186 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1187                            int val)
1188 {
1189         struct rtl8169_private *tp = netdev_priv(dev);
1190
1191         rtl_writephy(tp, location, val);
1192 }
1193
1194 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1195 {
1196         struct rtl8169_private *tp = netdev_priv(dev);
1197
1198         return rtl_readphy(tp, location);
1199 }
1200
1201 DECLARE_RTL_COND(rtl_ephyar_cond)
1202 {
1203         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1204 }
1205
1206 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1207 {
1208         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1209                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1210
1211         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1212
1213         udelay(10);
1214 }
1215
1216 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1217 {
1218         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1219
1220         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1221                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1222 }
1223
1224 DECLARE_RTL_COND(rtl_eriar_cond)
1225 {
1226         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1227 }
1228
1229 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1230                           u32 val, int type)
1231 {
1232         BUG_ON((addr & 3) || (mask == 0));
1233         RTL_W32(tp, ERIDR, val);
1234         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1235
1236         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1237 }
1238
1239 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1240 {
1241         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1242
1243         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1244                 RTL_R32(tp, ERIDR) : ~0;
1245 }
1246
1247 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1248                          u32 m, int type)
1249 {
1250         u32 val;
1251
1252         val = rtl_eri_read(tp, addr, type);
1253         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1254 }
1255
1256 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1257 {
1258         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1259         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1260                 RTL_R32(tp, OCPDR) : ~0;
1261 }
1262
1263 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1264 {
1265         return rtl_eri_read(tp, reg, ERIAR_OOB);
1266 }
1267
1268 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1269 {
1270         switch (tp->mac_version) {
1271         case RTL_GIGA_MAC_VER_27:
1272         case RTL_GIGA_MAC_VER_28:
1273         case RTL_GIGA_MAC_VER_31:
1274                 return r8168dp_ocp_read(tp, mask, reg);
1275         case RTL_GIGA_MAC_VER_49:
1276         case RTL_GIGA_MAC_VER_50:
1277         case RTL_GIGA_MAC_VER_51:
1278                 return r8168ep_ocp_read(tp, mask, reg);
1279         default:
1280                 BUG();
1281                 return ~0;
1282         }
1283 }
1284
1285 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1286                               u32 data)
1287 {
1288         RTL_W32(tp, OCPDR, data);
1289         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1290         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1291 }
1292
1293 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1294                               u32 data)
1295 {
1296         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1297                       data, ERIAR_OOB);
1298 }
1299
1300 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1301 {
1302         switch (tp->mac_version) {
1303         case RTL_GIGA_MAC_VER_27:
1304         case RTL_GIGA_MAC_VER_28:
1305         case RTL_GIGA_MAC_VER_31:
1306                 r8168dp_ocp_write(tp, mask, reg, data);
1307                 break;
1308         case RTL_GIGA_MAC_VER_49:
1309         case RTL_GIGA_MAC_VER_50:
1310         case RTL_GIGA_MAC_VER_51:
1311                 r8168ep_ocp_write(tp, mask, reg, data);
1312                 break;
1313         default:
1314                 BUG();
1315                 break;
1316         }
1317 }
1318
1319 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1320 {
1321         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1322
1323         ocp_write(tp, 0x1, 0x30, 0x00000001);
1324 }
1325
1326 #define OOB_CMD_RESET           0x00
1327 #define OOB_CMD_DRIVER_START    0x05
1328 #define OOB_CMD_DRIVER_STOP     0x06
1329
1330 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1331 {
1332         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1333 }
1334
1335 DECLARE_RTL_COND(rtl_ocp_read_cond)
1336 {
1337         u16 reg;
1338
1339         reg = rtl8168_get_ocp_reg(tp);
1340
1341         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1342 }
1343
1344 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1345 {
1346         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1347 }
1348
1349 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1350 {
1351         return RTL_R8(tp, IBISR0) & 0x20;
1352 }
1353
1354 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1355 {
1356         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1357         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1358         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1359         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1360 }
1361
1362 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1363 {
1364         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1365         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1366 }
1367
1368 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1369 {
1370         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1371         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1372         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1373 }
1374
1375 static void rtl8168_driver_start(struct rtl8169_private *tp)
1376 {
1377         switch (tp->mac_version) {
1378         case RTL_GIGA_MAC_VER_27:
1379         case RTL_GIGA_MAC_VER_28:
1380         case RTL_GIGA_MAC_VER_31:
1381                 rtl8168dp_driver_start(tp);
1382                 break;
1383         case RTL_GIGA_MAC_VER_49:
1384         case RTL_GIGA_MAC_VER_50:
1385         case RTL_GIGA_MAC_VER_51:
1386                 rtl8168ep_driver_start(tp);
1387                 break;
1388         default:
1389                 BUG();
1390                 break;
1391         }
1392 }
1393
1394 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1395 {
1396         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1397         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1398 }
1399
1400 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1401 {
1402         rtl8168ep_stop_cmac(tp);
1403         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1404         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1405         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1406 }
1407
1408 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1409 {
1410         switch (tp->mac_version) {
1411         case RTL_GIGA_MAC_VER_27:
1412         case RTL_GIGA_MAC_VER_28:
1413         case RTL_GIGA_MAC_VER_31:
1414                 rtl8168dp_driver_stop(tp);
1415                 break;
1416         case RTL_GIGA_MAC_VER_49:
1417         case RTL_GIGA_MAC_VER_50:
1418         case RTL_GIGA_MAC_VER_51:
1419                 rtl8168ep_driver_stop(tp);
1420                 break;
1421         default:
1422                 BUG();
1423                 break;
1424         }
1425 }
1426
1427 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1428 {
1429         u16 reg = rtl8168_get_ocp_reg(tp);
1430
1431         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1432 }
1433
1434 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1435 {
1436         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1437 }
1438
1439 static bool r8168_check_dash(struct rtl8169_private *tp)
1440 {
1441         switch (tp->mac_version) {
1442         case RTL_GIGA_MAC_VER_27:
1443         case RTL_GIGA_MAC_VER_28:
1444         case RTL_GIGA_MAC_VER_31:
1445                 return r8168dp_check_dash(tp);
1446         case RTL_GIGA_MAC_VER_49:
1447         case RTL_GIGA_MAC_VER_50:
1448         case RTL_GIGA_MAC_VER_51:
1449                 return r8168ep_check_dash(tp);
1450         default:
1451                 return false;
1452         }
1453 }
1454
1455 struct exgmac_reg {
1456         u16 addr;
1457         u16 mask;
1458         u32 val;
1459 };
1460
1461 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1462                                    const struct exgmac_reg *r, int len)
1463 {
1464         while (len-- > 0) {
1465                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1466                 r++;
1467         }
1468 }
1469
1470 DECLARE_RTL_COND(rtl_efusear_cond)
1471 {
1472         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1473 }
1474
1475 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1476 {
1477         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1478
1479         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1480                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1481 }
1482
1483 static u16 rtl_get_events(struct rtl8169_private *tp)
1484 {
1485         return RTL_R16(tp, IntrStatus);
1486 }
1487
1488 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1489 {
1490         RTL_W16(tp, IntrStatus, bits);
1491         mmiowb();
1492 }
1493
1494 static void rtl_irq_disable(struct rtl8169_private *tp)
1495 {
1496         RTL_W16(tp, IntrMask, 0);
1497         mmiowb();
1498 }
1499
1500 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1501 {
1502         RTL_W16(tp, IntrMask, bits);
1503 }
1504
1505 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1506 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1507 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1508
1509 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1510 {
1511         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1512 }
1513
1514 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1515 {
1516         rtl_irq_disable(tp);
1517         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1518         RTL_R8(tp, ChipCmd);
1519 }
1520
1521 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1522 {
1523         return RTL_R32(tp, TBICSR) & TBIReset;
1524 }
1525
1526 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1527 {
1528         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1529 }
1530
1531 static unsigned int rtl8169_tbi_link_ok(struct rtl8169_private *tp)
1532 {
1533         return RTL_R32(tp, TBICSR) & TBILinkOk;
1534 }
1535
1536 static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
1537 {
1538         return RTL_R8(tp, PHYstatus) & LinkStatus;
1539 }
1540
1541 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1542 {
1543         RTL_W32(tp, TBICSR, RTL_R32(tp, TBICSR) | TBIReset);
1544 }
1545
1546 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1547 {
1548         unsigned int val;
1549
1550         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1551         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1552 }
1553
1554 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1555 {
1556         struct net_device *dev = tp->dev;
1557
1558         if (!netif_running(dev))
1559                 return;
1560
1561         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1562             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1563                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1564                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1565                                       ERIAR_EXGMAC);
1566                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1567                                       ERIAR_EXGMAC);
1568                 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1569                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1570                                       ERIAR_EXGMAC);
1571                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1572                                       ERIAR_EXGMAC);
1573                 } else {
1574                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1575                                       ERIAR_EXGMAC);
1576                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1577                                       ERIAR_EXGMAC);
1578                 }
1579                 /* Reset packet filter */
1580                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1581                              ERIAR_EXGMAC);
1582                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1583                              ERIAR_EXGMAC);
1584         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1585                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1586                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1587                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1588                                       ERIAR_EXGMAC);
1589                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1590                                       ERIAR_EXGMAC);
1591                 } else {
1592                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1593                                       ERIAR_EXGMAC);
1594                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1595                                       ERIAR_EXGMAC);
1596                 }
1597         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1598                 if (RTL_R8(tp, PHYstatus) & _10bps) {
1599                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1600                                       ERIAR_EXGMAC);
1601                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1602                                       ERIAR_EXGMAC);
1603                 } else {
1604                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1605                                       ERIAR_EXGMAC);
1606                 }
1607         }
1608 }
1609
1610 static void rtl8169_check_link_status(struct net_device *dev,
1611                                       struct rtl8169_private *tp)
1612 {
1613         struct device *d = tp_to_dev(tp);
1614
1615         if (tp->link_ok(tp)) {
1616                 rtl_link_chg_patch(tp);
1617                 /* This is to cancel a scheduled suspend if there's one. */
1618                 pm_request_resume(d);
1619                 netif_carrier_on(dev);
1620                 if (net_ratelimit())
1621                         netif_info(tp, ifup, dev, "link up\n");
1622         } else {
1623                 netif_carrier_off(dev);
1624                 netif_info(tp, ifdown, dev, "link down\n");
1625                 pm_runtime_idle(d);
1626         }
1627 }
1628
1629 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1630
1631 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1632 {
1633         u8 options;
1634         u32 wolopts = 0;
1635
1636         options = RTL_R8(tp, Config1);
1637         if (!(options & PMEnable))
1638                 return 0;
1639
1640         options = RTL_R8(tp, Config3);
1641         if (options & LinkUp)
1642                 wolopts |= WAKE_PHY;
1643         switch (tp->mac_version) {
1644         case RTL_GIGA_MAC_VER_34:
1645         case RTL_GIGA_MAC_VER_35:
1646         case RTL_GIGA_MAC_VER_36:
1647         case RTL_GIGA_MAC_VER_37:
1648         case RTL_GIGA_MAC_VER_38:
1649         case RTL_GIGA_MAC_VER_40:
1650         case RTL_GIGA_MAC_VER_41:
1651         case RTL_GIGA_MAC_VER_42:
1652         case RTL_GIGA_MAC_VER_43:
1653         case RTL_GIGA_MAC_VER_44:
1654         case RTL_GIGA_MAC_VER_45:
1655         case RTL_GIGA_MAC_VER_46:
1656         case RTL_GIGA_MAC_VER_47:
1657         case RTL_GIGA_MAC_VER_48:
1658         case RTL_GIGA_MAC_VER_49:
1659         case RTL_GIGA_MAC_VER_50:
1660         case RTL_GIGA_MAC_VER_51:
1661                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1662                         wolopts |= WAKE_MAGIC;
1663                 break;
1664         default:
1665                 if (options & MagicPacket)
1666                         wolopts |= WAKE_MAGIC;
1667                 break;
1668         }
1669
1670         options = RTL_R8(tp, Config5);
1671         if (options & UWF)
1672                 wolopts |= WAKE_UCAST;
1673         if (options & BWF)
1674                 wolopts |= WAKE_BCAST;
1675         if (options & MWF)
1676                 wolopts |= WAKE_MCAST;
1677
1678         return wolopts;
1679 }
1680
1681 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1682 {
1683         struct rtl8169_private *tp = netdev_priv(dev);
1684         struct device *d = tp_to_dev(tp);
1685
1686         pm_runtime_get_noresume(d);
1687
1688         rtl_lock_work(tp);
1689
1690         wol->supported = WAKE_ANY;
1691         if (pm_runtime_active(d))
1692                 wol->wolopts = __rtl8169_get_wol(tp);
1693         else
1694                 wol->wolopts = tp->saved_wolopts;
1695
1696         rtl_unlock_work(tp);
1697
1698         pm_runtime_put_noidle(d);
1699 }
1700
1701 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1702 {
1703         unsigned int i, tmp;
1704         static const struct {
1705                 u32 opt;
1706                 u16 reg;
1707                 u8  mask;
1708         } cfg[] = {
1709                 { WAKE_PHY,   Config3, LinkUp },
1710                 { WAKE_UCAST, Config5, UWF },
1711                 { WAKE_BCAST, Config5, BWF },
1712                 { WAKE_MCAST, Config5, MWF },
1713                 { WAKE_ANY,   Config5, LanWake },
1714                 { WAKE_MAGIC, Config3, MagicPacket }
1715         };
1716         u8 options;
1717
1718         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1719
1720         switch (tp->mac_version) {
1721         case RTL_GIGA_MAC_VER_34:
1722         case RTL_GIGA_MAC_VER_35:
1723         case RTL_GIGA_MAC_VER_36:
1724         case RTL_GIGA_MAC_VER_37:
1725         case RTL_GIGA_MAC_VER_38:
1726         case RTL_GIGA_MAC_VER_40:
1727         case RTL_GIGA_MAC_VER_41:
1728         case RTL_GIGA_MAC_VER_42:
1729         case RTL_GIGA_MAC_VER_43:
1730         case RTL_GIGA_MAC_VER_44:
1731         case RTL_GIGA_MAC_VER_45:
1732         case RTL_GIGA_MAC_VER_46:
1733         case RTL_GIGA_MAC_VER_47:
1734         case RTL_GIGA_MAC_VER_48:
1735         case RTL_GIGA_MAC_VER_49:
1736         case RTL_GIGA_MAC_VER_50:
1737         case RTL_GIGA_MAC_VER_51:
1738                 tmp = ARRAY_SIZE(cfg) - 1;
1739                 if (wolopts & WAKE_MAGIC)
1740                         rtl_w0w1_eri(tp,
1741                                      0x0dc,
1742                                      ERIAR_MASK_0100,
1743                                      MagicPacket_v2,
1744                                      0x0000,
1745                                      ERIAR_EXGMAC);
1746                 else
1747                         rtl_w0w1_eri(tp,
1748                                      0x0dc,
1749                                      ERIAR_MASK_0100,
1750                                      0x0000,
1751                                      MagicPacket_v2,
1752                                      ERIAR_EXGMAC);
1753                 break;
1754         default:
1755                 tmp = ARRAY_SIZE(cfg);
1756                 break;
1757         }
1758
1759         for (i = 0; i < tmp; i++) {
1760                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1761                 if (wolopts & cfg[i].opt)
1762                         options |= cfg[i].mask;
1763                 RTL_W8(tp, cfg[i].reg, options);
1764         }
1765
1766         switch (tp->mac_version) {
1767         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1768                 options = RTL_R8(tp, Config1) & ~PMEnable;
1769                 if (wolopts)
1770                         options |= PMEnable;
1771                 RTL_W8(tp, Config1, options);
1772                 break;
1773         default:
1774                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1775                 if (wolopts)
1776                         options |= PME_SIGNAL;
1777                 RTL_W8(tp, Config2, options);
1778                 break;
1779         }
1780
1781         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1782 }
1783
1784 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1785 {
1786         struct rtl8169_private *tp = netdev_priv(dev);
1787         struct device *d = tp_to_dev(tp);
1788
1789         pm_runtime_get_noresume(d);
1790
1791         rtl_lock_work(tp);
1792
1793         if (pm_runtime_active(d))
1794                 __rtl8169_set_wol(tp, wol->wolopts);
1795         else
1796                 tp->saved_wolopts = wol->wolopts;
1797
1798         rtl_unlock_work(tp);
1799
1800         device_set_wakeup_enable(d, wol->wolopts);
1801
1802         pm_runtime_put_noidle(d);
1803
1804         return 0;
1805 }
1806
1807 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1808 {
1809         return rtl_chip_infos[tp->mac_version].fw_name;
1810 }
1811
1812 static void rtl8169_get_drvinfo(struct net_device *dev,
1813                                 struct ethtool_drvinfo *info)
1814 {
1815         struct rtl8169_private *tp = netdev_priv(dev);
1816         struct rtl_fw *rtl_fw = tp->rtl_fw;
1817
1818         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1819         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1820         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1821         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1822         if (!IS_ERR_OR_NULL(rtl_fw))
1823                 strlcpy(info->fw_version, rtl_fw->version,
1824                         sizeof(info->fw_version));
1825 }
1826
1827 static int rtl8169_get_regs_len(struct net_device *dev)
1828 {
1829         return R8169_REGS_SIZE;
1830 }
1831
1832 static int rtl8169_set_speed_tbi(struct net_device *dev,
1833                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1834 {
1835         struct rtl8169_private *tp = netdev_priv(dev);
1836         int ret = 0;
1837         u32 reg;
1838
1839         reg = RTL_R32(tp, TBICSR);
1840         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1841             (duplex == DUPLEX_FULL)) {
1842                 RTL_W32(tp, TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1843         } else if (autoneg == AUTONEG_ENABLE)
1844                 RTL_W32(tp, TBICSR, reg | TBINwEnable | TBINwRestart);
1845         else {
1846                 netif_warn(tp, link, dev,
1847                            "incorrect speed setting refused in TBI mode\n");
1848                 ret = -EOPNOTSUPP;
1849         }
1850
1851         return ret;
1852 }
1853
1854 static int rtl8169_set_speed_xmii(struct net_device *dev,
1855                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1856 {
1857         struct rtl8169_private *tp = netdev_priv(dev);
1858         int giga_ctrl, bmcr;
1859         int rc = -EINVAL;
1860
1861         rtl_writephy(tp, 0x1f, 0x0000);
1862
1863         if (autoneg == AUTONEG_ENABLE) {
1864                 int auto_nego;
1865
1866                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1867                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1868                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1869
1870                 if (adv & ADVERTISED_10baseT_Half)
1871                         auto_nego |= ADVERTISE_10HALF;
1872                 if (adv & ADVERTISED_10baseT_Full)
1873                         auto_nego |= ADVERTISE_10FULL;
1874                 if (adv & ADVERTISED_100baseT_Half)
1875                         auto_nego |= ADVERTISE_100HALF;
1876                 if (adv & ADVERTISED_100baseT_Full)
1877                         auto_nego |= ADVERTISE_100FULL;
1878
1879                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1880
1881                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1882                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1883
1884                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1885                 if (tp->mii.supports_gmii) {
1886                         if (adv & ADVERTISED_1000baseT_Half)
1887                                 giga_ctrl |= ADVERTISE_1000HALF;
1888                         if (adv & ADVERTISED_1000baseT_Full)
1889                                 giga_ctrl |= ADVERTISE_1000FULL;
1890                 } else if (adv & (ADVERTISED_1000baseT_Half |
1891                                   ADVERTISED_1000baseT_Full)) {
1892                         netif_info(tp, link, dev,
1893                                    "PHY does not support 1000Mbps\n");
1894                         goto out;
1895                 }
1896
1897                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1898
1899                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1900                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1901         } else {
1902                 if (speed == SPEED_10)
1903                         bmcr = 0;
1904                 else if (speed == SPEED_100)
1905                         bmcr = BMCR_SPEED100;
1906                 else
1907                         goto out;
1908
1909                 if (duplex == DUPLEX_FULL)
1910                         bmcr |= BMCR_FULLDPLX;
1911         }
1912
1913         rtl_writephy(tp, MII_BMCR, bmcr);
1914
1915         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1916             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1917                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1918                         rtl_writephy(tp, 0x17, 0x2138);
1919                         rtl_writephy(tp, 0x0e, 0x0260);
1920                 } else {
1921                         rtl_writephy(tp, 0x17, 0x2108);
1922                         rtl_writephy(tp, 0x0e, 0x0000);
1923                 }
1924         }
1925
1926         rc = 0;
1927 out:
1928         return rc;
1929 }
1930
1931 static int rtl8169_set_speed(struct net_device *dev,
1932                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1933 {
1934         struct rtl8169_private *tp = netdev_priv(dev);
1935         int ret;
1936
1937         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1938         if (ret < 0)
1939                 goto out;
1940
1941         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1942             (advertising & ADVERTISED_1000baseT_Full) &&
1943             !pci_is_pcie(tp->pci_dev)) {
1944                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1945         }
1946 out:
1947         return ret;
1948 }
1949
1950 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1951         netdev_features_t features)
1952 {
1953         struct rtl8169_private *tp = netdev_priv(dev);
1954
1955         if (dev->mtu > TD_MSS_MAX)
1956                 features &= ~NETIF_F_ALL_TSO;
1957
1958         if (dev->mtu > JUMBO_1K &&
1959             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1960                 features &= ~NETIF_F_IP_CSUM;
1961
1962         return features;
1963 }
1964
1965 static void __rtl8169_set_features(struct net_device *dev,
1966                                    netdev_features_t features)
1967 {
1968         struct rtl8169_private *tp = netdev_priv(dev);
1969         u32 rx_config;
1970
1971         rx_config = RTL_R32(tp, RxConfig);
1972         if (features & NETIF_F_RXALL)
1973                 rx_config |= (AcceptErr | AcceptRunt);
1974         else
1975                 rx_config &= ~(AcceptErr | AcceptRunt);
1976
1977         RTL_W32(tp, RxConfig, rx_config);
1978
1979         if (features & NETIF_F_RXCSUM)
1980                 tp->cp_cmd |= RxChkSum;
1981         else
1982                 tp->cp_cmd &= ~RxChkSum;
1983
1984         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1985                 tp->cp_cmd |= RxVlan;
1986         else
1987                 tp->cp_cmd &= ~RxVlan;
1988
1989         tp->cp_cmd |= RTL_R16(tp, CPlusCmd) & ~(RxVlan | RxChkSum);
1990
1991         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1992         RTL_R16(tp, CPlusCmd);
1993 }
1994
1995 static int rtl8169_set_features(struct net_device *dev,
1996                                 netdev_features_t features)
1997 {
1998         struct rtl8169_private *tp = netdev_priv(dev);
1999
2000         features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2001
2002         rtl_lock_work(tp);
2003         if (features ^ dev->features)
2004                 __rtl8169_set_features(dev, features);
2005         rtl_unlock_work(tp);
2006
2007         return 0;
2008 }
2009
2010
2011 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2012 {
2013         return (skb_vlan_tag_present(skb)) ?
2014                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2015 }
2016
2017 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2018 {
2019         u32 opts2 = le32_to_cpu(desc->opts2);
2020
2021         if (opts2 & RxVlanTag)
2022                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2023 }
2024
2025 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2026                                           struct ethtool_link_ksettings *cmd)
2027 {
2028         struct rtl8169_private *tp = netdev_priv(dev);
2029         u32 status;
2030         u32 supported, advertising;
2031
2032         supported =
2033                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2034         cmd->base.port = PORT_FIBRE;
2035
2036         status = RTL_R32(tp, TBICSR);
2037         advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
2038         cmd->base.autoneg = !!(status & TBINwEnable);
2039
2040         cmd->base.speed = SPEED_1000;
2041         cmd->base.duplex = DUPLEX_FULL; /* Always set */
2042
2043         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2044                                                 supported);
2045         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2046                                                 advertising);
2047
2048         return 0;
2049 }
2050
2051 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2052                                            struct ethtool_link_ksettings *cmd)
2053 {
2054         struct rtl8169_private *tp = netdev_priv(dev);
2055
2056         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2057
2058         return 0;
2059 }
2060
2061 static int rtl8169_get_link_ksettings(struct net_device *dev,
2062                                       struct ethtool_link_ksettings *cmd)
2063 {
2064         struct rtl8169_private *tp = netdev_priv(dev);
2065         int rc;
2066
2067         rtl_lock_work(tp);
2068         rc = tp->get_link_ksettings(dev, cmd);
2069         rtl_unlock_work(tp);
2070
2071         return rc;
2072 }
2073
2074 static int rtl8169_set_link_ksettings(struct net_device *dev,
2075                                       const struct ethtool_link_ksettings *cmd)
2076 {
2077         struct rtl8169_private *tp = netdev_priv(dev);
2078         int rc;
2079         u32 advertising;
2080
2081         if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2082             cmd->link_modes.advertising))
2083                 return -EINVAL;
2084
2085         del_timer_sync(&tp->timer);
2086
2087         rtl_lock_work(tp);
2088         rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2089                                cmd->base.duplex, advertising);
2090         rtl_unlock_work(tp);
2091
2092         return rc;
2093 }
2094
2095 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2096                              void *p)
2097 {
2098         struct rtl8169_private *tp = netdev_priv(dev);
2099         u32 __iomem *data = tp->mmio_addr;
2100         u32 *dw = p;
2101         int i;
2102
2103         rtl_lock_work(tp);
2104         for (i = 0; i < R8169_REGS_SIZE; i += 4)
2105                 memcpy_fromio(dw++, data++, 4);
2106         rtl_unlock_work(tp);
2107 }
2108
2109 static u32 rtl8169_get_msglevel(struct net_device *dev)
2110 {
2111         struct rtl8169_private *tp = netdev_priv(dev);
2112
2113         return tp->msg_enable;
2114 }
2115
2116 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2117 {
2118         struct rtl8169_private *tp = netdev_priv(dev);
2119
2120         tp->msg_enable = value;
2121 }
2122
2123 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2124         "tx_packets",
2125         "rx_packets",
2126         "tx_errors",
2127         "rx_errors",
2128         "rx_missed",
2129         "align_errors",
2130         "tx_single_collisions",
2131         "tx_multi_collisions",
2132         "unicast",
2133         "broadcast",
2134         "multicast",
2135         "tx_aborted",
2136         "tx_underrun",
2137 };
2138
2139 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2140 {
2141         switch (sset) {
2142         case ETH_SS_STATS:
2143                 return ARRAY_SIZE(rtl8169_gstrings);
2144         default:
2145                 return -EOPNOTSUPP;
2146         }
2147 }
2148
2149 DECLARE_RTL_COND(rtl_counters_cond)
2150 {
2151         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
2152 }
2153
2154 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2155 {
2156         struct rtl8169_private *tp = netdev_priv(dev);
2157         dma_addr_t paddr = tp->counters_phys_addr;
2158         u32 cmd;
2159
2160         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2161         RTL_R32(tp, CounterAddrHigh);
2162         cmd = (u64)paddr & DMA_BIT_MASK(32);
2163         RTL_W32(tp, CounterAddrLow, cmd);
2164         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
2165
2166         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2167 }
2168
2169 static bool rtl8169_reset_counters(struct net_device *dev)
2170 {
2171         struct rtl8169_private *tp = netdev_priv(dev);
2172
2173         /*
2174          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2175          * tally counters.
2176          */
2177         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2178                 return true;
2179
2180         return rtl8169_do_counters(dev, CounterReset);
2181 }
2182
2183 static bool rtl8169_update_counters(struct net_device *dev)
2184 {
2185         struct rtl8169_private *tp = netdev_priv(dev);
2186
2187         /*
2188          * Some chips are unable to dump tally counters when the receiver
2189          * is disabled.
2190          */
2191         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
2192                 return true;
2193
2194         return rtl8169_do_counters(dev, CounterDump);
2195 }
2196
2197 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2198 {
2199         struct rtl8169_private *tp = netdev_priv(dev);
2200         struct rtl8169_counters *counters = tp->counters;
2201         bool ret = false;
2202
2203         /*
2204          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
2205          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2206          * reset by a power cycle, while the counter values collected by the
2207          * driver are reset at every driver unload/load cycle.
2208          *
2209          * To make sure the HW values returned by @get_stats64 match the SW
2210          * values, we collect the initial values at first open(*) and use them
2211          * as offsets to normalize the values returned by @get_stats64.
2212          *
2213          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2214          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2215          * set at open time by rtl_hw_start.
2216          */
2217
2218         if (tp->tc_offset.inited)
2219                 return true;
2220
2221         /* If both, reset and update fail, propagate to caller. */
2222         if (rtl8169_reset_counters(dev))
2223                 ret = true;
2224
2225         if (rtl8169_update_counters(dev))
2226                 ret = true;
2227
2228         tp->tc_offset.tx_errors = counters->tx_errors;
2229         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2230         tp->tc_offset.tx_aborted = counters->tx_aborted;
2231         tp->tc_offset.inited = true;
2232
2233         return ret;
2234 }
2235
2236 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2237                                       struct ethtool_stats *stats, u64 *data)
2238 {
2239         struct rtl8169_private *tp = netdev_priv(dev);
2240         struct device *d = tp_to_dev(tp);
2241         struct rtl8169_counters *counters = tp->counters;
2242
2243         ASSERT_RTNL();
2244
2245         pm_runtime_get_noresume(d);
2246
2247         if (pm_runtime_active(d))
2248                 rtl8169_update_counters(dev);
2249
2250         pm_runtime_put_noidle(d);
2251
2252         data[0] = le64_to_cpu(counters->tx_packets);
2253         data[1] = le64_to_cpu(counters->rx_packets);
2254         data[2] = le64_to_cpu(counters->tx_errors);
2255         data[3] = le32_to_cpu(counters->rx_errors);
2256         data[4] = le16_to_cpu(counters->rx_missed);
2257         data[5] = le16_to_cpu(counters->align_errors);
2258         data[6] = le32_to_cpu(counters->tx_one_collision);
2259         data[7] = le32_to_cpu(counters->tx_multi_collision);
2260         data[8] = le64_to_cpu(counters->rx_unicast);
2261         data[9] = le64_to_cpu(counters->rx_broadcast);
2262         data[10] = le32_to_cpu(counters->rx_multicast);
2263         data[11] = le16_to_cpu(counters->tx_aborted);
2264         data[12] = le16_to_cpu(counters->tx_underun);
2265 }
2266
2267 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2268 {
2269         switch(stringset) {
2270         case ETH_SS_STATS:
2271                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2272                 break;
2273         }
2274 }
2275
2276 static int rtl8169_nway_reset(struct net_device *dev)
2277 {
2278         struct rtl8169_private *tp = netdev_priv(dev);
2279
2280         return mii_nway_restart(&tp->mii);
2281 }
2282
2283 /*
2284  * Interrupt coalescing
2285  *
2286  * > 1 - the availability of the IntrMitigate (0xe2) register through the
2287  * >     8169, 8168 and 810x line of chipsets
2288  *
2289  * 8169, 8168, and 8136(810x) serial chipsets support it.
2290  *
2291  * > 2 - the Tx timer unit at gigabit speed
2292  *
2293  * The unit of the timer depends on both the speed and the setting of CPlusCmd
2294  * (0xe0) bit 1 and bit 0.
2295  *
2296  * For 8169
2297  * bit[1:0] \ speed        1000M           100M            10M
2298  * 0 0                     320ns           2.56us          40.96us
2299  * 0 1                     2.56us          20.48us         327.7us
2300  * 1 0                     5.12us          40.96us         655.4us
2301  * 1 1                     10.24us         81.92us         1.31ms
2302  *
2303  * For the other
2304  * bit[1:0] \ speed        1000M           100M            10M
2305  * 0 0                     5us             2.56us          40.96us
2306  * 0 1                     40us            20.48us         327.7us
2307  * 1 0                     80us            40.96us         655.4us
2308  * 1 1                     160us           81.92us         1.31ms
2309  */
2310
2311 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2312 struct rtl_coalesce_scale {
2313         /* Rx / Tx */
2314         u32 nsecs[2];
2315 };
2316
2317 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2318 struct rtl_coalesce_info {
2319         u32 speed;
2320         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
2321 };
2322
2323 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2324 #define rxtx_x1822(r, t) {              \
2325         {{(r),          (t)}},          \
2326         {{(r)*8,        (t)*8}},        \
2327         {{(r)*8*2,      (t)*8*2}},      \
2328         {{(r)*8*2*2,    (t)*8*2*2}},    \
2329 }
2330 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2331         /* speed        delays:     rx00   tx00 */
2332         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2333         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2334         { SPEED_1000,   rxtx_x1822(  320,   320)        },
2335         { 0 },
2336 };
2337
2338 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2339         /* speed        delays:     rx00   tx00 */
2340         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2341         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2342         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
2343         { 0 },
2344 };
2345 #undef rxtx_x1822
2346
2347 /* get rx/tx scale vector corresponding to current speed */
2348 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2349 {
2350         struct rtl8169_private *tp = netdev_priv(dev);
2351         struct ethtool_link_ksettings ecmd;
2352         const struct rtl_coalesce_info *ci;
2353         int rc;
2354
2355         rc = rtl8169_get_link_ksettings(dev, &ecmd);
2356         if (rc < 0)
2357                 return ERR_PTR(rc);
2358
2359         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2360                 if (ecmd.base.speed == ci->speed) {
2361                         return ci;
2362                 }
2363         }
2364
2365         return ERR_PTR(-ELNRNG);
2366 }
2367
2368 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2369 {
2370         struct rtl8169_private *tp = netdev_priv(dev);
2371         const struct rtl_coalesce_info *ci;
2372         const struct rtl_coalesce_scale *scale;
2373         struct {
2374                 u32 *max_frames;
2375                 u32 *usecs;
2376         } coal_settings [] = {
2377                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2378                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2379         }, *p = coal_settings;
2380         int i;
2381         u16 w;
2382
2383         memset(ec, 0, sizeof(*ec));
2384
2385         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2386         ci = rtl_coalesce_info(dev);
2387         if (IS_ERR(ci))
2388                 return PTR_ERR(ci);
2389
2390         scale = &ci->scalev[RTL_R16(tp, CPlusCmd) & 3];
2391
2392         /* read IntrMitigate and adjust according to scale */
2393         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2394                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2395                 w >>= RTL_COALESCE_SHIFT;
2396                 *p->usecs = w & RTL_COALESCE_MASK;
2397         }
2398
2399         for (i = 0; i < 2; i++) {
2400                 p = coal_settings + i;
2401                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2402
2403                 /*
2404                  * ethtool_coalesce says it is illegal to set both usecs and
2405                  * max_frames to 0.
2406                  */
2407                 if (!*p->usecs && !*p->max_frames)
2408                         *p->max_frames = 1;
2409         }
2410
2411         return 0;
2412 }
2413
2414 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2415 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2416                         struct net_device *dev, u32 nsec, u16 *cp01)
2417 {
2418         const struct rtl_coalesce_info *ci;
2419         u16 i;
2420
2421         ci = rtl_coalesce_info(dev);
2422         if (IS_ERR(ci))
2423                 return ERR_CAST(ci);
2424
2425         for (i = 0; i < 4; i++) {
2426                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2427                                         ci->scalev[i].nsecs[1]);
2428                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2429                         *cp01 = i;
2430                         return &ci->scalev[i];
2431                 }
2432         }
2433
2434         return ERR_PTR(-EINVAL);
2435 }
2436
2437 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2438 {
2439         struct rtl8169_private *tp = netdev_priv(dev);
2440         const struct rtl_coalesce_scale *scale;
2441         struct {
2442                 u32 frames;
2443                 u32 usecs;
2444         } coal_settings [] = {
2445                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2446                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2447         }, *p = coal_settings;
2448         u16 w = 0, cp01;
2449         int i;
2450
2451         scale = rtl_coalesce_choose_scale(dev,
2452                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2453         if (IS_ERR(scale))
2454                 return PTR_ERR(scale);
2455
2456         for (i = 0; i < 2; i++, p++) {
2457                 u32 units;
2458
2459                 /*
2460                  * accept max_frames=1 we returned in rtl_get_coalesce.
2461                  * accept it not only when usecs=0 because of e.g. the following scenario:
2462                  *
2463                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2464                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2465                  * - then user does `ethtool -C eth0 rx-usecs 100`
2466                  *
2467                  * since ethtool sends to kernel whole ethtool_coalesce
2468                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2469                  * we'll reject it below in `frames % 4 != 0`.
2470                  */
2471                 if (p->frames == 1) {
2472                         p->frames = 0;
2473                 }
2474
2475                 units = p->usecs * 1000 / scale->nsecs[i];
2476                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2477                         return -EINVAL;
2478
2479                 w <<= RTL_COALESCE_SHIFT;
2480                 w |= units;
2481                 w <<= RTL_COALESCE_SHIFT;
2482                 w |= p->frames >> 2;
2483         }
2484
2485         rtl_lock_work(tp);
2486
2487         RTL_W16(tp, IntrMitigate, swab16(w));
2488
2489         tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2490         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2491         RTL_R16(tp, CPlusCmd);
2492
2493         rtl_unlock_work(tp);
2494
2495         return 0;
2496 }
2497
2498 static const struct ethtool_ops rtl8169_ethtool_ops = {
2499         .get_drvinfo            = rtl8169_get_drvinfo,
2500         .get_regs_len           = rtl8169_get_regs_len,
2501         .get_link               = ethtool_op_get_link,
2502         .get_coalesce           = rtl_get_coalesce,
2503         .set_coalesce           = rtl_set_coalesce,
2504         .get_msglevel           = rtl8169_get_msglevel,
2505         .set_msglevel           = rtl8169_set_msglevel,
2506         .get_regs               = rtl8169_get_regs,
2507         .get_wol                = rtl8169_get_wol,
2508         .set_wol                = rtl8169_set_wol,
2509         .get_strings            = rtl8169_get_strings,
2510         .get_sset_count         = rtl8169_get_sset_count,
2511         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2512         .get_ts_info            = ethtool_op_get_ts_info,
2513         .nway_reset             = rtl8169_nway_reset,
2514         .get_link_ksettings     = rtl8169_get_link_ksettings,
2515         .set_link_ksettings     = rtl8169_set_link_ksettings,
2516 };
2517
2518 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2519                                     struct net_device *dev, u8 default_version)
2520 {
2521         /*
2522          * The driver currently handles the 8168Bf and the 8168Be identically
2523          * but they can be identified more specifically through the test below
2524          * if needed:
2525          *
2526          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2527          *
2528          * Same thing for the 8101Eb and the 8101Ec:
2529          *
2530          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2531          */
2532         static const struct rtl_mac_info {
2533                 u32 mask;
2534                 u32 val;
2535                 int mac_version;
2536         } mac_info[] = {
2537                 /* 8168EP family. */
2538                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2539                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2540                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2541
2542                 /* 8168H family. */
2543                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2544                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2545
2546                 /* 8168G family. */
2547                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2548                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2549                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2550                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2551
2552                 /* 8168F family. */
2553                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2554                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2555                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2556
2557                 /* 8168E family. */
2558                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2559                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
2560                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2561                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2562
2563                 /* 8168D family. */
2564                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
2565                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2566                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2567
2568                 /* 8168DP family. */
2569                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2570                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2571                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2572
2573                 /* 8168C family. */
2574                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
2575                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2576                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2577                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2578                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2579                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2580                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2581                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
2582                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2583
2584                 /* 8168B family. */
2585                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2586                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
2587                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2588                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2589
2590                 /* 8101 family. */
2591                 { 0x7cf00000, 0x44900000,       RTL_GIGA_MAC_VER_39 },
2592                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2593                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2594                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
2595                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
2596                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2597                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2598                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
2599                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
2600                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2601                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2602                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2603                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2604                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2605                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2606                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2607                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2608                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2609                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2610                 /* FIXME: where did these entries come from ? -- FR */
2611                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2612                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2613
2614                 /* 8110 family. */
2615                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2616                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2617                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2618                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2619                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2620                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2621
2622                 /* Catch-all */
2623                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2624         };
2625         const struct rtl_mac_info *p = mac_info;
2626         u32 reg;
2627
2628         reg = RTL_R32(tp, TxConfig);
2629         while ((reg & p->mask) != p->val)
2630                 p++;
2631         tp->mac_version = p->mac_version;
2632
2633         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2634                 netif_notice(tp, probe, dev,
2635                              "unknown MAC, using family default\n");
2636                 tp->mac_version = default_version;
2637         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2638                 tp->mac_version = tp->mii.supports_gmii ?
2639                                   RTL_GIGA_MAC_VER_42 :
2640                                   RTL_GIGA_MAC_VER_43;
2641         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2642                 tp->mac_version = tp->mii.supports_gmii ?
2643                                   RTL_GIGA_MAC_VER_45 :
2644                                   RTL_GIGA_MAC_VER_47;
2645         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2646                 tp->mac_version = tp->mii.supports_gmii ?
2647                                   RTL_GIGA_MAC_VER_46 :
2648                                   RTL_GIGA_MAC_VER_48;
2649         }
2650 }
2651
2652 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2653 {
2654         dprintk("mac_version = 0x%02x\n", tp->mac_version);
2655 }
2656
2657 struct phy_reg {
2658         u16 reg;
2659         u16 val;
2660 };
2661
2662 static void rtl_writephy_batch(struct rtl8169_private *tp,
2663                                const struct phy_reg *regs, int len)
2664 {
2665         while (len-- > 0) {
2666                 rtl_writephy(tp, regs->reg, regs->val);
2667                 regs++;
2668         }
2669 }
2670
2671 #define PHY_READ                0x00000000
2672 #define PHY_DATA_OR             0x10000000
2673 #define PHY_DATA_AND            0x20000000
2674 #define PHY_BJMPN               0x30000000
2675 #define PHY_MDIO_CHG            0x40000000
2676 #define PHY_CLEAR_READCOUNT     0x70000000
2677 #define PHY_WRITE               0x80000000
2678 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2679 #define PHY_COMP_EQ_SKIPN       0xa0000000
2680 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2681 #define PHY_WRITE_PREVIOUS      0xc0000000
2682 #define PHY_SKIPN               0xd0000000
2683 #define PHY_DELAY_MS            0xe0000000
2684
2685 struct fw_info {
2686         u32     magic;
2687         char    version[RTL_VER_SIZE];
2688         __le32  fw_start;
2689         __le32  fw_len;
2690         u8      chksum;
2691 } __packed;
2692
2693 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2694
2695 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2696 {
2697         const struct firmware *fw = rtl_fw->fw;
2698         struct fw_info *fw_info = (struct fw_info *)fw->data;
2699         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2700         char *version = rtl_fw->version;
2701         bool rc = false;
2702
2703         if (fw->size < FW_OPCODE_SIZE)
2704                 goto out;
2705
2706         if (!fw_info->magic) {
2707                 size_t i, size, start;
2708                 u8 checksum = 0;
2709
2710                 if (fw->size < sizeof(*fw_info))
2711                         goto out;
2712
2713                 for (i = 0; i < fw->size; i++)
2714                         checksum += fw->data[i];
2715                 if (checksum != 0)
2716                         goto out;
2717
2718                 start = le32_to_cpu(fw_info->fw_start);
2719                 if (start > fw->size)
2720                         goto out;
2721
2722                 size = le32_to_cpu(fw_info->fw_len);
2723                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2724                         goto out;
2725
2726                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2727
2728                 pa->code = (__le32 *)(fw->data + start);
2729                 pa->size = size;
2730         } else {
2731                 if (fw->size % FW_OPCODE_SIZE)
2732                         goto out;
2733
2734                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2735
2736                 pa->code = (__le32 *)fw->data;
2737                 pa->size = fw->size / FW_OPCODE_SIZE;
2738         }
2739         version[RTL_VER_SIZE - 1] = 0;
2740
2741         rc = true;
2742 out:
2743         return rc;
2744 }
2745
2746 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2747                            struct rtl_fw_phy_action *pa)
2748 {
2749         bool rc = false;
2750         size_t index;
2751
2752         for (index = 0; index < pa->size; index++) {
2753                 u32 action = le32_to_cpu(pa->code[index]);
2754                 u32 regno = (action & 0x0fff0000) >> 16;
2755
2756                 switch(action & 0xf0000000) {
2757                 case PHY_READ:
2758                 case PHY_DATA_OR:
2759                 case PHY_DATA_AND:
2760                 case PHY_MDIO_CHG:
2761                 case PHY_CLEAR_READCOUNT:
2762                 case PHY_WRITE:
2763                 case PHY_WRITE_PREVIOUS:
2764                 case PHY_DELAY_MS:
2765                         break;
2766
2767                 case PHY_BJMPN:
2768                         if (regno > index) {
2769                                 netif_err(tp, ifup, tp->dev,
2770                                           "Out of range of firmware\n");
2771                                 goto out;
2772                         }
2773                         break;
2774                 case PHY_READCOUNT_EQ_SKIP:
2775                         if (index + 2 >= pa->size) {
2776                                 netif_err(tp, ifup, tp->dev,
2777                                           "Out of range of firmware\n");
2778                                 goto out;
2779                         }
2780                         break;
2781                 case PHY_COMP_EQ_SKIPN:
2782                 case PHY_COMP_NEQ_SKIPN:
2783                 case PHY_SKIPN:
2784                         if (index + 1 + regno >= pa->size) {
2785                                 netif_err(tp, ifup, tp->dev,
2786                                           "Out of range of firmware\n");
2787                                 goto out;
2788                         }
2789                         break;
2790
2791                 default:
2792                         netif_err(tp, ifup, tp->dev,
2793                                   "Invalid action 0x%08x\n", action);
2794                         goto out;
2795                 }
2796         }
2797         rc = true;
2798 out:
2799         return rc;
2800 }
2801
2802 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2803 {
2804         struct net_device *dev = tp->dev;
2805         int rc = -EINVAL;
2806
2807         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2808                 netif_err(tp, ifup, dev, "invalid firmware\n");
2809                 goto out;
2810         }
2811
2812         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2813                 rc = 0;
2814 out:
2815         return rc;
2816 }
2817
2818 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2819 {
2820         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2821         struct mdio_ops org, *ops = &tp->mdio_ops;
2822         u32 predata, count;
2823         size_t index;
2824
2825         predata = count = 0;
2826         org.write = ops->write;
2827         org.read = ops->read;
2828
2829         for (index = 0; index < pa->size; ) {
2830                 u32 action = le32_to_cpu(pa->code[index]);
2831                 u32 data = action & 0x0000ffff;
2832                 u32 regno = (action & 0x0fff0000) >> 16;
2833
2834                 if (!action)
2835                         break;
2836
2837                 switch(action & 0xf0000000) {
2838                 case PHY_READ:
2839                         predata = rtl_readphy(tp, regno);
2840                         count++;
2841                         index++;
2842                         break;
2843                 case PHY_DATA_OR:
2844                         predata |= data;
2845                         index++;
2846                         break;
2847                 case PHY_DATA_AND:
2848                         predata &= data;
2849                         index++;
2850                         break;
2851                 case PHY_BJMPN:
2852                         index -= regno;
2853                         break;
2854                 case PHY_MDIO_CHG:
2855                         if (data == 0) {
2856                                 ops->write = org.write;
2857                                 ops->read = org.read;
2858                         } else if (data == 1) {
2859                                 ops->write = mac_mcu_write;
2860                                 ops->read = mac_mcu_read;
2861                         }
2862
2863                         index++;
2864                         break;
2865                 case PHY_CLEAR_READCOUNT:
2866                         count = 0;
2867                         index++;
2868                         break;
2869                 case PHY_WRITE:
2870                         rtl_writephy(tp, regno, data);
2871                         index++;
2872                         break;
2873                 case PHY_READCOUNT_EQ_SKIP:
2874                         index += (count == data) ? 2 : 1;
2875                         break;
2876                 case PHY_COMP_EQ_SKIPN:
2877                         if (predata == data)
2878                                 index += regno;
2879                         index++;
2880                         break;
2881                 case PHY_COMP_NEQ_SKIPN:
2882                         if (predata != data)
2883                                 index += regno;
2884                         index++;
2885                         break;
2886                 case PHY_WRITE_PREVIOUS:
2887                         rtl_writephy(tp, regno, predata);
2888                         index++;
2889                         break;
2890                 case PHY_SKIPN:
2891                         index += regno + 1;
2892                         break;
2893                 case PHY_DELAY_MS:
2894                         mdelay(data);
2895                         index++;
2896                         break;
2897
2898                 default:
2899                         BUG();
2900                 }
2901         }
2902
2903         ops->write = org.write;
2904         ops->read = org.read;
2905 }
2906
2907 static void rtl_release_firmware(struct rtl8169_private *tp)
2908 {
2909         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2910                 release_firmware(tp->rtl_fw->fw);
2911                 kfree(tp->rtl_fw);
2912         }
2913         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2914 }
2915
2916 static void rtl_apply_firmware(struct rtl8169_private *tp)
2917 {
2918         struct rtl_fw *rtl_fw = tp->rtl_fw;
2919
2920         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2921         if (!IS_ERR_OR_NULL(rtl_fw))
2922                 rtl_phy_write_fw(tp, rtl_fw);
2923 }
2924
2925 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2926 {
2927         if (rtl_readphy(tp, reg) != val)
2928                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2929         else
2930                 rtl_apply_firmware(tp);
2931 }
2932
2933 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2934 {
2935         static const struct phy_reg phy_reg_init[] = {
2936                 { 0x1f, 0x0001 },
2937                 { 0x06, 0x006e },
2938                 { 0x08, 0x0708 },
2939                 { 0x15, 0x4000 },
2940                 { 0x18, 0x65c7 },
2941
2942                 { 0x1f, 0x0001 },
2943                 { 0x03, 0x00a1 },
2944                 { 0x02, 0x0008 },
2945                 { 0x01, 0x0120 },
2946                 { 0x00, 0x1000 },
2947                 { 0x04, 0x0800 },
2948                 { 0x04, 0x0000 },
2949
2950                 { 0x03, 0xff41 },
2951                 { 0x02, 0xdf60 },
2952                 { 0x01, 0x0140 },
2953                 { 0x00, 0x0077 },
2954                 { 0x04, 0x7800 },
2955                 { 0x04, 0x7000 },
2956
2957                 { 0x03, 0x802f },
2958                 { 0x02, 0x4f02 },
2959                 { 0x01, 0x0409 },
2960                 { 0x00, 0xf0f9 },
2961                 { 0x04, 0x9800 },
2962                 { 0x04, 0x9000 },
2963
2964                 { 0x03, 0xdf01 },
2965                 { 0x02, 0xdf20 },
2966                 { 0x01, 0xff95 },
2967                 { 0x00, 0xba00 },
2968                 { 0x04, 0xa800 },
2969                 { 0x04, 0xa000 },
2970
2971                 { 0x03, 0xff41 },
2972                 { 0x02, 0xdf20 },
2973                 { 0x01, 0x0140 },
2974                 { 0x00, 0x00bb },
2975                 { 0x04, 0xb800 },
2976                 { 0x04, 0xb000 },
2977
2978                 { 0x03, 0xdf41 },
2979                 { 0x02, 0xdc60 },
2980                 { 0x01, 0x6340 },
2981                 { 0x00, 0x007d },
2982                 { 0x04, 0xd800 },
2983                 { 0x04, 0xd000 },
2984
2985                 { 0x03, 0xdf01 },
2986                 { 0x02, 0xdf20 },
2987                 { 0x01, 0x100a },
2988                 { 0x00, 0xa0ff },
2989                 { 0x04, 0xf800 },
2990                 { 0x04, 0xf000 },
2991
2992                 { 0x1f, 0x0000 },
2993                 { 0x0b, 0x0000 },
2994                 { 0x00, 0x9200 }
2995         };
2996
2997         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2998 }
2999
3000 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
3001 {
3002         static const struct phy_reg phy_reg_init[] = {
3003                 { 0x1f, 0x0002 },
3004                 { 0x01, 0x90d0 },
3005                 { 0x1f, 0x0000 }
3006         };
3007
3008         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3009 }
3010
3011 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
3012 {
3013         struct pci_dev *pdev = tp->pci_dev;
3014
3015         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3016             (pdev->subsystem_device != 0xe000))
3017                 return;
3018
3019         rtl_writephy(tp, 0x1f, 0x0001);
3020         rtl_writephy(tp, 0x10, 0xf01b);
3021         rtl_writephy(tp, 0x1f, 0x0000);
3022 }
3023
3024 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
3025 {
3026         static const struct phy_reg phy_reg_init[] = {
3027                 { 0x1f, 0x0001 },
3028                 { 0x04, 0x0000 },
3029                 { 0x03, 0x00a1 },
3030                 { 0x02, 0x0008 },
3031                 { 0x01, 0x0120 },
3032                 { 0x00, 0x1000 },
3033                 { 0x04, 0x0800 },
3034                 { 0x04, 0x9000 },
3035                 { 0x03, 0x802f },
3036                 { 0x02, 0x4f02 },
3037                 { 0x01, 0x0409 },
3038                 { 0x00, 0xf099 },
3039                 { 0x04, 0x9800 },
3040                 { 0x04, 0xa000 },
3041                 { 0x03, 0xdf01 },
3042                 { 0x02, 0xdf20 },
3043                 { 0x01, 0xff95 },
3044                 { 0x00, 0xba00 },
3045                 { 0x04, 0xa800 },
3046                 { 0x04, 0xf000 },
3047                 { 0x03, 0xdf01 },
3048                 { 0x02, 0xdf20 },
3049                 { 0x01, 0x101a },
3050                 { 0x00, 0xa0ff },
3051                 { 0x04, 0xf800 },
3052                 { 0x04, 0x0000 },
3053                 { 0x1f, 0x0000 },
3054
3055                 { 0x1f, 0x0001 },
3056                 { 0x10, 0xf41b },
3057                 { 0x14, 0xfb54 },
3058                 { 0x18, 0xf5c7 },
3059                 { 0x1f, 0x0000 },
3060
3061                 { 0x1f, 0x0001 },
3062                 { 0x17, 0x0cc0 },
3063                 { 0x1f, 0x0000 }
3064         };
3065
3066         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3067
3068         rtl8169scd_hw_phy_config_quirk(tp);
3069 }
3070
3071 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
3072 {
3073         static const struct phy_reg phy_reg_init[] = {
3074                 { 0x1f, 0x0001 },
3075                 { 0x04, 0x0000 },
3076                 { 0x03, 0x00a1 },
3077                 { 0x02, 0x0008 },
3078                 { 0x01, 0x0120 },
3079                 { 0x00, 0x1000 },
3080                 { 0x04, 0x0800 },
3081                 { 0x04, 0x9000 },
3082                 { 0x03, 0x802f },
3083                 { 0x02, 0x4f02 },
3084                 { 0x01, 0x0409 },
3085                 { 0x00, 0xf099 },
3086                 { 0x04, 0x9800 },
3087                 { 0x04, 0xa000 },
3088                 { 0x03, 0xdf01 },
3089                 { 0x02, 0xdf20 },
3090                 { 0x01, 0xff95 },
3091                 { 0x00, 0xba00 },
3092                 { 0x04, 0xa800 },
3093                 { 0x04, 0xf000 },
3094                 { 0x03, 0xdf01 },
3095                 { 0x02, 0xdf20 },
3096                 { 0x01, 0x101a },
3097                 { 0x00, 0xa0ff },
3098                 { 0x04, 0xf800 },
3099                 { 0x04, 0x0000 },
3100                 { 0x1f, 0x0000 },
3101
3102                 { 0x1f, 0x0001 },
3103                 { 0x0b, 0x8480 },
3104                 { 0x1f, 0x0000 },
3105
3106                 { 0x1f, 0x0001 },
3107                 { 0x18, 0x67c7 },
3108                 { 0x04, 0x2000 },
3109                 { 0x03, 0x002f },
3110                 { 0x02, 0x4360 },
3111                 { 0x01, 0x0109 },
3112                 { 0x00, 0x3022 },
3113                 { 0x04, 0x2800 },
3114                 { 0x1f, 0x0000 },
3115
3116                 { 0x1f, 0x0001 },
3117                 { 0x17, 0x0cc0 },
3118                 { 0x1f, 0x0000 }
3119         };
3120
3121         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3122 }
3123
3124 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3125 {
3126         static const struct phy_reg phy_reg_init[] = {
3127                 { 0x10, 0xf41b },
3128                 { 0x1f, 0x0000 }
3129         };
3130
3131         rtl_writephy(tp, 0x1f, 0x0001);
3132         rtl_patchphy(tp, 0x16, 1 << 0);
3133
3134         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3135 }
3136
3137 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3138 {
3139         static const struct phy_reg phy_reg_init[] = {
3140                 { 0x1f, 0x0001 },
3141                 { 0x10, 0xf41b },
3142                 { 0x1f, 0x0000 }
3143         };
3144
3145         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3146 }
3147
3148 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3149 {
3150         static const struct phy_reg phy_reg_init[] = {
3151                 { 0x1f, 0x0000 },
3152                 { 0x1d, 0x0f00 },
3153                 { 0x1f, 0x0002 },
3154                 { 0x0c, 0x1ec8 },
3155                 { 0x1f, 0x0000 }
3156         };
3157
3158         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3159 }
3160
3161 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3162 {
3163         static const struct phy_reg phy_reg_init[] = {
3164                 { 0x1f, 0x0001 },
3165                 { 0x1d, 0x3d98 },
3166                 { 0x1f, 0x0000 }
3167         };
3168
3169         rtl_writephy(tp, 0x1f, 0x0000);
3170         rtl_patchphy(tp, 0x14, 1 << 5);
3171         rtl_patchphy(tp, 0x0d, 1 << 5);
3172
3173         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3174 }
3175
3176 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3177 {
3178         static const struct phy_reg phy_reg_init[] = {
3179                 { 0x1f, 0x0001 },
3180                 { 0x12, 0x2300 },
3181                 { 0x1f, 0x0002 },
3182                 { 0x00, 0x88d4 },
3183                 { 0x01, 0x82b1 },
3184                 { 0x03, 0x7002 },
3185                 { 0x08, 0x9e30 },
3186                 { 0x09, 0x01f0 },
3187                 { 0x0a, 0x5500 },
3188                 { 0x0c, 0x00c8 },
3189                 { 0x1f, 0x0003 },
3190                 { 0x12, 0xc096 },
3191                 { 0x16, 0x000a },
3192                 { 0x1f, 0x0000 },
3193                 { 0x1f, 0x0000 },
3194                 { 0x09, 0x2000 },
3195                 { 0x09, 0x0000 }
3196         };
3197
3198         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3199
3200         rtl_patchphy(tp, 0x14, 1 << 5);
3201         rtl_patchphy(tp, 0x0d, 1 << 5);
3202         rtl_writephy(tp, 0x1f, 0x0000);
3203 }
3204
3205 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3206 {
3207         static const struct phy_reg phy_reg_init[] = {
3208                 { 0x1f, 0x0001 },
3209                 { 0x12, 0x2300 },
3210                 { 0x03, 0x802f },
3211                 { 0x02, 0x4f02 },
3212                 { 0x01, 0x0409 },
3213                 { 0x00, 0xf099 },
3214                 { 0x04, 0x9800 },
3215                 { 0x04, 0x9000 },
3216                 { 0x1d, 0x3d98 },
3217                 { 0x1f, 0x0002 },
3218                 { 0x0c, 0x7eb8 },
3219                 { 0x06, 0x0761 },
3220                 { 0x1f, 0x0003 },
3221                 { 0x16, 0x0f0a },
3222                 { 0x1f, 0x0000 }
3223         };
3224
3225         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3226
3227         rtl_patchphy(tp, 0x16, 1 << 0);
3228         rtl_patchphy(tp, 0x14, 1 << 5);
3229         rtl_patchphy(tp, 0x0d, 1 << 5);
3230         rtl_writephy(tp, 0x1f, 0x0000);
3231 }
3232
3233 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3234 {
3235         static const struct phy_reg phy_reg_init[] = {
3236                 { 0x1f, 0x0001 },
3237                 { 0x12, 0x2300 },
3238                 { 0x1d, 0x3d98 },
3239                 { 0x1f, 0x0002 },
3240                 { 0x0c, 0x7eb8 },
3241                 { 0x06, 0x5461 },
3242                 { 0x1f, 0x0003 },
3243                 { 0x16, 0x0f0a },
3244                 { 0x1f, 0x0000 }
3245         };
3246
3247         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3248
3249         rtl_patchphy(tp, 0x16, 1 << 0);
3250         rtl_patchphy(tp, 0x14, 1 << 5);
3251         rtl_patchphy(tp, 0x0d, 1 << 5);
3252         rtl_writephy(tp, 0x1f, 0x0000);
3253 }
3254
3255 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3256 {
3257         rtl8168c_3_hw_phy_config(tp);
3258 }
3259
3260 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3261 {
3262         static const struct phy_reg phy_reg_init_0[] = {
3263                 /* Channel Estimation */
3264                 { 0x1f, 0x0001 },
3265                 { 0x06, 0x4064 },
3266                 { 0x07, 0x2863 },
3267                 { 0x08, 0x059c },
3268                 { 0x09, 0x26b4 },
3269                 { 0x0a, 0x6a19 },
3270                 { 0x0b, 0xdcc8 },
3271                 { 0x10, 0xf06d },
3272                 { 0x14, 0x7f68 },
3273                 { 0x18, 0x7fd9 },
3274                 { 0x1c, 0xf0ff },
3275                 { 0x1d, 0x3d9c },
3276                 { 0x1f, 0x0003 },
3277                 { 0x12, 0xf49f },
3278                 { 0x13, 0x070b },
3279                 { 0x1a, 0x05ad },
3280                 { 0x14, 0x94c0 },
3281
3282                 /*
3283                  * Tx Error Issue
3284                  * Enhance line driver power
3285                  */
3286                 { 0x1f, 0x0002 },
3287                 { 0x06, 0x5561 },
3288                 { 0x1f, 0x0005 },
3289                 { 0x05, 0x8332 },
3290                 { 0x06, 0x5561 },
3291
3292                 /*
3293                  * Can not link to 1Gbps with bad cable
3294                  * Decrease SNR threshold form 21.07dB to 19.04dB
3295                  */
3296                 { 0x1f, 0x0001 },
3297                 { 0x17, 0x0cc0 },
3298
3299                 { 0x1f, 0x0000 },
3300                 { 0x0d, 0xf880 }
3301         };
3302
3303         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3304
3305         /*
3306          * Rx Error Issue
3307          * Fine Tune Switching regulator parameter
3308          */
3309         rtl_writephy(tp, 0x1f, 0x0002);
3310         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3311         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3312
3313         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3314                 static const struct phy_reg phy_reg_init[] = {
3315                         { 0x1f, 0x0002 },
3316                         { 0x05, 0x669a },
3317                         { 0x1f, 0x0005 },
3318                         { 0x05, 0x8330 },
3319                         { 0x06, 0x669a },
3320                         { 0x1f, 0x0002 }
3321                 };
3322                 int val;
3323
3324                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3325
3326                 val = rtl_readphy(tp, 0x0d);
3327
3328                 if ((val & 0x00ff) != 0x006c) {
3329                         static const u32 set[] = {
3330                                 0x0065, 0x0066, 0x0067, 0x0068,
3331                                 0x0069, 0x006a, 0x006b, 0x006c
3332                         };
3333                         int i;
3334
3335                         rtl_writephy(tp, 0x1f, 0x0002);
3336
3337                         val &= 0xff00;
3338                         for (i = 0; i < ARRAY_SIZE(set); i++)
3339                                 rtl_writephy(tp, 0x0d, val | set[i]);
3340                 }
3341         } else {
3342                 static const struct phy_reg phy_reg_init[] = {
3343                         { 0x1f, 0x0002 },
3344                         { 0x05, 0x6662 },
3345                         { 0x1f, 0x0005 },
3346                         { 0x05, 0x8330 },
3347                         { 0x06, 0x6662 }
3348                 };
3349
3350                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3351         }
3352
3353         /* RSET couple improve */
3354         rtl_writephy(tp, 0x1f, 0x0002);
3355         rtl_patchphy(tp, 0x0d, 0x0300);
3356         rtl_patchphy(tp, 0x0f, 0x0010);
3357
3358         /* Fine tune PLL performance */
3359         rtl_writephy(tp, 0x1f, 0x0002);
3360         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3361         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3362
3363         rtl_writephy(tp, 0x1f, 0x0005);
3364         rtl_writephy(tp, 0x05, 0x001b);
3365
3366         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3367
3368         rtl_writephy(tp, 0x1f, 0x0000);
3369 }
3370
3371 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3372 {
3373         static const struct phy_reg phy_reg_init_0[] = {
3374                 /* Channel Estimation */
3375                 { 0x1f, 0x0001 },
3376                 { 0x06, 0x4064 },
3377                 { 0x07, 0x2863 },
3378                 { 0x08, 0x059c },
3379                 { 0x09, 0x26b4 },
3380                 { 0x0a, 0x6a19 },
3381                 { 0x0b, 0xdcc8 },
3382                 { 0x10, 0xf06d },
3383                 { 0x14, 0x7f68 },
3384                 { 0x18, 0x7fd9 },
3385                 { 0x1c, 0xf0ff },
3386                 { 0x1d, 0x3d9c },
3387                 { 0x1f, 0x0003 },
3388                 { 0x12, 0xf49f },
3389                 { 0x13, 0x070b },
3390                 { 0x1a, 0x05ad },
3391                 { 0x14, 0x94c0 },
3392
3393                 /*
3394                  * Tx Error Issue
3395                  * Enhance line driver power
3396                  */
3397                 { 0x1f, 0x0002 },
3398                 { 0x06, 0x5561 },
3399                 { 0x1f, 0x0005 },
3400                 { 0x05, 0x8332 },
3401                 { 0x06, 0x5561 },
3402
3403                 /*
3404                  * Can not link to 1Gbps with bad cable
3405                  * Decrease SNR threshold form 21.07dB to 19.04dB
3406                  */
3407                 { 0x1f, 0x0001 },
3408                 { 0x17, 0x0cc0 },
3409
3410                 { 0x1f, 0x0000 },
3411                 { 0x0d, 0xf880 }
3412         };
3413
3414         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3415
3416         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3417                 static const struct phy_reg phy_reg_init[] = {
3418                         { 0x1f, 0x0002 },
3419                         { 0x05, 0x669a },
3420                         { 0x1f, 0x0005 },
3421                         { 0x05, 0x8330 },
3422                         { 0x06, 0x669a },
3423
3424                         { 0x1f, 0x0002 }
3425                 };
3426                 int val;
3427
3428                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3429
3430                 val = rtl_readphy(tp, 0x0d);
3431                 if ((val & 0x00ff) != 0x006c) {
3432                         static const u32 set[] = {
3433                                 0x0065, 0x0066, 0x0067, 0x0068,
3434                                 0x0069, 0x006a, 0x006b, 0x006c
3435                         };
3436                         int i;
3437
3438                         rtl_writephy(tp, 0x1f, 0x0002);
3439
3440                         val &= 0xff00;
3441                         for (i = 0; i < ARRAY_SIZE(set); i++)
3442                                 rtl_writephy(tp, 0x0d, val | set[i]);
3443                 }
3444         } else {
3445                 static const struct phy_reg phy_reg_init[] = {
3446                         { 0x1f, 0x0002 },
3447                         { 0x05, 0x2642 },
3448                         { 0x1f, 0x0005 },
3449                         { 0x05, 0x8330 },
3450                         { 0x06, 0x2642 }
3451                 };
3452
3453                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3454         }
3455
3456         /* Fine tune PLL performance */
3457         rtl_writephy(tp, 0x1f, 0x0002);
3458         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3459         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3460
3461         /* Switching regulator Slew rate */
3462         rtl_writephy(tp, 0x1f, 0x0002);
3463         rtl_patchphy(tp, 0x0f, 0x0017);
3464
3465         rtl_writephy(tp, 0x1f, 0x0005);
3466         rtl_writephy(tp, 0x05, 0x001b);
3467
3468         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3469
3470         rtl_writephy(tp, 0x1f, 0x0000);
3471 }
3472
3473 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3474 {
3475         static const struct phy_reg phy_reg_init[] = {
3476                 { 0x1f, 0x0002 },
3477                 { 0x10, 0x0008 },
3478                 { 0x0d, 0x006c },
3479
3480                 { 0x1f, 0x0000 },
3481                 { 0x0d, 0xf880 },
3482
3483                 { 0x1f, 0x0001 },
3484                 { 0x17, 0x0cc0 },
3485
3486                 { 0x1f, 0x0001 },
3487                 { 0x0b, 0xa4d8 },
3488                 { 0x09, 0x281c },
3489                 { 0x07, 0x2883 },
3490                 { 0x0a, 0x6b35 },
3491                 { 0x1d, 0x3da4 },
3492                 { 0x1c, 0xeffd },
3493                 { 0x14, 0x7f52 },
3494                 { 0x18, 0x7fc6 },
3495                 { 0x08, 0x0601 },
3496                 { 0x06, 0x4063 },
3497                 { 0x10, 0xf074 },
3498                 { 0x1f, 0x0003 },
3499                 { 0x13, 0x0789 },
3500                 { 0x12, 0xf4bd },
3501                 { 0x1a, 0x04fd },
3502                 { 0x14, 0x84b0 },
3503                 { 0x1f, 0x0000 },
3504                 { 0x00, 0x9200 },
3505
3506                 { 0x1f, 0x0005 },
3507                 { 0x01, 0x0340 },
3508                 { 0x1f, 0x0001 },
3509                 { 0x04, 0x4000 },
3510                 { 0x03, 0x1d21 },
3511                 { 0x02, 0x0c32 },
3512                 { 0x01, 0x0200 },
3513                 { 0x00, 0x5554 },
3514                 { 0x04, 0x4800 },
3515                 { 0x04, 0x4000 },
3516                 { 0x04, 0xf000 },
3517                 { 0x03, 0xdf01 },
3518                 { 0x02, 0xdf20 },
3519                 { 0x01, 0x101a },
3520                 { 0x00, 0xa0ff },
3521                 { 0x04, 0xf800 },
3522                 { 0x04, 0xf000 },
3523                 { 0x1f, 0x0000 },
3524
3525                 { 0x1f, 0x0007 },
3526                 { 0x1e, 0x0023 },
3527                 { 0x16, 0x0000 },
3528                 { 0x1f, 0x0000 }
3529         };
3530
3531         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3532 }
3533
3534 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3535 {
3536         static const struct phy_reg phy_reg_init[] = {
3537                 { 0x1f, 0x0001 },
3538                 { 0x17, 0x0cc0 },
3539
3540                 { 0x1f, 0x0007 },
3541                 { 0x1e, 0x002d },
3542                 { 0x18, 0x0040 },
3543                 { 0x1f, 0x0000 }
3544         };
3545
3546         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3547         rtl_patchphy(tp, 0x0d, 1 << 5);
3548 }
3549
3550 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3551 {
3552         static const struct phy_reg phy_reg_init[] = {
3553                 /* Enable Delay cap */
3554                 { 0x1f, 0x0005 },
3555                 { 0x05, 0x8b80 },
3556                 { 0x06, 0xc896 },
3557                 { 0x1f, 0x0000 },
3558
3559                 /* Channel estimation fine tune */
3560                 { 0x1f, 0x0001 },
3561                 { 0x0b, 0x6c20 },
3562                 { 0x07, 0x2872 },
3563                 { 0x1c, 0xefff },
3564                 { 0x1f, 0x0003 },
3565                 { 0x14, 0x6420 },
3566                 { 0x1f, 0x0000 },
3567
3568                 /* Update PFM & 10M TX idle timer */
3569                 { 0x1f, 0x0007 },
3570                 { 0x1e, 0x002f },
3571                 { 0x15, 0x1919 },
3572                 { 0x1f, 0x0000 },
3573
3574                 { 0x1f, 0x0007 },
3575                 { 0x1e, 0x00ac },
3576                 { 0x18, 0x0006 },
3577                 { 0x1f, 0x0000 }
3578         };
3579
3580         rtl_apply_firmware(tp);
3581
3582         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3583
3584         /* DCO enable for 10M IDLE Power */
3585         rtl_writephy(tp, 0x1f, 0x0007);
3586         rtl_writephy(tp, 0x1e, 0x0023);
3587         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3588         rtl_writephy(tp, 0x1f, 0x0000);
3589
3590         /* For impedance matching */
3591         rtl_writephy(tp, 0x1f, 0x0002);
3592         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3593         rtl_writephy(tp, 0x1f, 0x0000);
3594
3595         /* PHY auto speed down */
3596         rtl_writephy(tp, 0x1f, 0x0007);
3597         rtl_writephy(tp, 0x1e, 0x002d);
3598         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3599         rtl_writephy(tp, 0x1f, 0x0000);
3600         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3601
3602         rtl_writephy(tp, 0x1f, 0x0005);
3603         rtl_writephy(tp, 0x05, 0x8b86);
3604         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3605         rtl_writephy(tp, 0x1f, 0x0000);
3606
3607         rtl_writephy(tp, 0x1f, 0x0005);
3608         rtl_writephy(tp, 0x05, 0x8b85);
3609         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3610         rtl_writephy(tp, 0x1f, 0x0007);
3611         rtl_writephy(tp, 0x1e, 0x0020);
3612         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3613         rtl_writephy(tp, 0x1f, 0x0006);
3614         rtl_writephy(tp, 0x00, 0x5a00);
3615         rtl_writephy(tp, 0x1f, 0x0000);
3616         rtl_writephy(tp, 0x0d, 0x0007);
3617         rtl_writephy(tp, 0x0e, 0x003c);
3618         rtl_writephy(tp, 0x0d, 0x4007);
3619         rtl_writephy(tp, 0x0e, 0x0000);
3620         rtl_writephy(tp, 0x0d, 0x0000);
3621 }
3622
3623 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3624 {
3625         const u16 w[] = {
3626                 addr[0] | (addr[1] << 8),
3627                 addr[2] | (addr[3] << 8),
3628                 addr[4] | (addr[5] << 8)
3629         };
3630         const struct exgmac_reg e[] = {
3631                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3632                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3633                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3634                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3635         };
3636
3637         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3638 }
3639
3640 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3641 {
3642         static const struct phy_reg phy_reg_init[] = {
3643                 /* Enable Delay cap */
3644                 { 0x1f, 0x0004 },
3645                 { 0x1f, 0x0007 },
3646                 { 0x1e, 0x00ac },
3647                 { 0x18, 0x0006 },
3648                 { 0x1f, 0x0002 },
3649                 { 0x1f, 0x0000 },
3650                 { 0x1f, 0x0000 },
3651
3652                 /* Channel estimation fine tune */
3653                 { 0x1f, 0x0003 },
3654                 { 0x09, 0xa20f },
3655                 { 0x1f, 0x0000 },
3656                 { 0x1f, 0x0000 },
3657
3658                 /* Green Setting */
3659                 { 0x1f, 0x0005 },
3660                 { 0x05, 0x8b5b },
3661                 { 0x06, 0x9222 },
3662                 { 0x05, 0x8b6d },
3663                 { 0x06, 0x8000 },
3664                 { 0x05, 0x8b76 },
3665                 { 0x06, 0x8000 },
3666                 { 0x1f, 0x0000 }
3667         };
3668
3669         rtl_apply_firmware(tp);
3670
3671         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3672
3673         /* For 4-corner performance improve */
3674         rtl_writephy(tp, 0x1f, 0x0005);
3675         rtl_writephy(tp, 0x05, 0x8b80);
3676         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3677         rtl_writephy(tp, 0x1f, 0x0000);
3678
3679         /* PHY auto speed down */
3680         rtl_writephy(tp, 0x1f, 0x0004);
3681         rtl_writephy(tp, 0x1f, 0x0007);
3682         rtl_writephy(tp, 0x1e, 0x002d);
3683         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3684         rtl_writephy(tp, 0x1f, 0x0002);
3685         rtl_writephy(tp, 0x1f, 0x0000);
3686         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3687
3688         /* improve 10M EEE waveform */
3689         rtl_writephy(tp, 0x1f, 0x0005);
3690         rtl_writephy(tp, 0x05, 0x8b86);
3691         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3692         rtl_writephy(tp, 0x1f, 0x0000);
3693
3694         /* Improve 2-pair detection performance */
3695         rtl_writephy(tp, 0x1f, 0x0005);
3696         rtl_writephy(tp, 0x05, 0x8b85);
3697         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3698         rtl_writephy(tp, 0x1f, 0x0000);
3699
3700         /* EEE setting */
3701         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3702         rtl_writephy(tp, 0x1f, 0x0005);
3703         rtl_writephy(tp, 0x05, 0x8b85);
3704         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3705         rtl_writephy(tp, 0x1f, 0x0004);
3706         rtl_writephy(tp, 0x1f, 0x0007);
3707         rtl_writephy(tp, 0x1e, 0x0020);
3708         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3709         rtl_writephy(tp, 0x1f, 0x0002);
3710         rtl_writephy(tp, 0x1f, 0x0000);
3711         rtl_writephy(tp, 0x0d, 0x0007);
3712         rtl_writephy(tp, 0x0e, 0x003c);
3713         rtl_writephy(tp, 0x0d, 0x4007);
3714         rtl_writephy(tp, 0x0e, 0x0006);
3715         rtl_writephy(tp, 0x0d, 0x0000);
3716
3717         /* Green feature */
3718         rtl_writephy(tp, 0x1f, 0x0003);
3719         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3720         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3721         rtl_writephy(tp, 0x1f, 0x0000);
3722         rtl_writephy(tp, 0x1f, 0x0005);
3723         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3724         rtl_writephy(tp, 0x1f, 0x0000);
3725
3726         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3727         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3728 }
3729
3730 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3731 {
3732         /* For 4-corner performance improve */
3733         rtl_writephy(tp, 0x1f, 0x0005);
3734         rtl_writephy(tp, 0x05, 0x8b80);
3735         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3736         rtl_writephy(tp, 0x1f, 0x0000);
3737
3738         /* PHY auto speed down */
3739         rtl_writephy(tp, 0x1f, 0x0007);
3740         rtl_writephy(tp, 0x1e, 0x002d);
3741         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3742         rtl_writephy(tp, 0x1f, 0x0000);
3743         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3744
3745         /* Improve 10M EEE waveform */
3746         rtl_writephy(tp, 0x1f, 0x0005);
3747         rtl_writephy(tp, 0x05, 0x8b86);
3748         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3749         rtl_writephy(tp, 0x1f, 0x0000);
3750 }
3751
3752 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3753 {
3754         static const struct phy_reg phy_reg_init[] = {
3755                 /* Channel estimation fine tune */
3756                 { 0x1f, 0x0003 },
3757                 { 0x09, 0xa20f },
3758                 { 0x1f, 0x0000 },
3759
3760                 /* Modify green table for giga & fnet */
3761                 { 0x1f, 0x0005 },
3762                 { 0x05, 0x8b55 },
3763                 { 0x06, 0x0000 },
3764                 { 0x05, 0x8b5e },
3765                 { 0x06, 0x0000 },
3766                 { 0x05, 0x8b67 },
3767                 { 0x06, 0x0000 },
3768                 { 0x05, 0x8b70 },
3769                 { 0x06, 0x0000 },
3770                 { 0x1f, 0x0000 },
3771                 { 0x1f, 0x0007 },
3772                 { 0x1e, 0x0078 },
3773                 { 0x17, 0x0000 },
3774                 { 0x19, 0x00fb },
3775                 { 0x1f, 0x0000 },
3776
3777                 /* Modify green table for 10M */
3778                 { 0x1f, 0x0005 },
3779                 { 0x05, 0x8b79 },
3780                 { 0x06, 0xaa00 },
3781                 { 0x1f, 0x0000 },
3782
3783                 /* Disable hiimpedance detection (RTCT) */
3784                 { 0x1f, 0x0003 },
3785                 { 0x01, 0x328a },
3786                 { 0x1f, 0x0000 }
3787         };
3788
3789         rtl_apply_firmware(tp);
3790
3791         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3792
3793         rtl8168f_hw_phy_config(tp);
3794
3795         /* Improve 2-pair detection performance */
3796         rtl_writephy(tp, 0x1f, 0x0005);
3797         rtl_writephy(tp, 0x05, 0x8b85);
3798         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3799         rtl_writephy(tp, 0x1f, 0x0000);
3800 }
3801
3802 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3803 {
3804         rtl_apply_firmware(tp);
3805
3806         rtl8168f_hw_phy_config(tp);
3807 }
3808
3809 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3810 {
3811         static const struct phy_reg phy_reg_init[] = {
3812                 /* Channel estimation fine tune */
3813                 { 0x1f, 0x0003 },
3814                 { 0x09, 0xa20f },
3815                 { 0x1f, 0x0000 },
3816
3817                 /* Modify green table for giga & fnet */
3818                 { 0x1f, 0x0005 },
3819                 { 0x05, 0x8b55 },
3820                 { 0x06, 0x0000 },
3821                 { 0x05, 0x8b5e },
3822                 { 0x06, 0x0000 },
3823                 { 0x05, 0x8b67 },
3824                 { 0x06, 0x0000 },
3825                 { 0x05, 0x8b70 },
3826                 { 0x06, 0x0000 },
3827                 { 0x1f, 0x0000 },
3828                 { 0x1f, 0x0007 },
3829                 { 0x1e, 0x0078 },
3830                 { 0x17, 0x0000 },
3831                 { 0x19, 0x00aa },
3832                 { 0x1f, 0x0000 },
3833
3834                 /* Modify green table for 10M */
3835                 { 0x1f, 0x0005 },
3836                 { 0x05, 0x8b79 },
3837                 { 0x06, 0xaa00 },
3838                 { 0x1f, 0x0000 },
3839
3840                 /* Disable hiimpedance detection (RTCT) */
3841                 { 0x1f, 0x0003 },
3842                 { 0x01, 0x328a },
3843                 { 0x1f, 0x0000 }
3844         };
3845
3846
3847         rtl_apply_firmware(tp);
3848
3849         rtl8168f_hw_phy_config(tp);
3850
3851         /* Improve 2-pair detection performance */
3852         rtl_writephy(tp, 0x1f, 0x0005);
3853         rtl_writephy(tp, 0x05, 0x8b85);
3854         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3855         rtl_writephy(tp, 0x1f, 0x0000);
3856
3857         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3858
3859         /* Modify green table for giga */
3860         rtl_writephy(tp, 0x1f, 0x0005);
3861         rtl_writephy(tp, 0x05, 0x8b54);
3862         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3863         rtl_writephy(tp, 0x05, 0x8b5d);
3864         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3865         rtl_writephy(tp, 0x05, 0x8a7c);
3866         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3867         rtl_writephy(tp, 0x05, 0x8a7f);
3868         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3869         rtl_writephy(tp, 0x05, 0x8a82);
3870         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3871         rtl_writephy(tp, 0x05, 0x8a85);
3872         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3873         rtl_writephy(tp, 0x05, 0x8a88);
3874         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3875         rtl_writephy(tp, 0x1f, 0x0000);
3876
3877         /* uc same-seed solution */
3878         rtl_writephy(tp, 0x1f, 0x0005);
3879         rtl_writephy(tp, 0x05, 0x8b85);
3880         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3881         rtl_writephy(tp, 0x1f, 0x0000);
3882
3883         /* eee setting */
3884         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3885         rtl_writephy(tp, 0x1f, 0x0005);
3886         rtl_writephy(tp, 0x05, 0x8b85);
3887         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3888         rtl_writephy(tp, 0x1f, 0x0004);
3889         rtl_writephy(tp, 0x1f, 0x0007);
3890         rtl_writephy(tp, 0x1e, 0x0020);
3891         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3892         rtl_writephy(tp, 0x1f, 0x0000);
3893         rtl_writephy(tp, 0x0d, 0x0007);
3894         rtl_writephy(tp, 0x0e, 0x003c);
3895         rtl_writephy(tp, 0x0d, 0x4007);
3896         rtl_writephy(tp, 0x0e, 0x0000);
3897         rtl_writephy(tp, 0x0d, 0x0000);
3898
3899         /* Green feature */
3900         rtl_writephy(tp, 0x1f, 0x0003);
3901         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3902         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3903         rtl_writephy(tp, 0x1f, 0x0000);
3904 }
3905
3906 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3907 {
3908         rtl_apply_firmware(tp);
3909
3910         rtl_writephy(tp, 0x1f, 0x0a46);
3911         if (rtl_readphy(tp, 0x10) & 0x0100) {
3912                 rtl_writephy(tp, 0x1f, 0x0bcc);
3913                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3914         } else {
3915                 rtl_writephy(tp, 0x1f, 0x0bcc);
3916                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3917         }
3918
3919         rtl_writephy(tp, 0x1f, 0x0a46);
3920         if (rtl_readphy(tp, 0x13) & 0x0100) {
3921                 rtl_writephy(tp, 0x1f, 0x0c41);
3922                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3923         } else {
3924                 rtl_writephy(tp, 0x1f, 0x0c41);
3925                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3926         }
3927
3928         /* Enable PHY auto speed down */
3929         rtl_writephy(tp, 0x1f, 0x0a44);
3930         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3931
3932         rtl_writephy(tp, 0x1f, 0x0bcc);
3933         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3934         rtl_writephy(tp, 0x1f, 0x0a44);
3935         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3936         rtl_writephy(tp, 0x1f, 0x0a43);
3937         rtl_writephy(tp, 0x13, 0x8084);
3938         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3939         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3940
3941         /* EEE auto-fallback function */
3942         rtl_writephy(tp, 0x1f, 0x0a4b);
3943         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3944
3945         /* Enable UC LPF tune function */
3946         rtl_writephy(tp, 0x1f, 0x0a43);
3947         rtl_writephy(tp, 0x13, 0x8012);
3948         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3949
3950         rtl_writephy(tp, 0x1f, 0x0c42);
3951         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3952
3953         /* Improve SWR Efficiency */
3954         rtl_writephy(tp, 0x1f, 0x0bcd);
3955         rtl_writephy(tp, 0x14, 0x5065);
3956         rtl_writephy(tp, 0x14, 0xd065);
3957         rtl_writephy(tp, 0x1f, 0x0bc8);
3958         rtl_writephy(tp, 0x11, 0x5655);
3959         rtl_writephy(tp, 0x1f, 0x0bcd);
3960         rtl_writephy(tp, 0x14, 0x1065);
3961         rtl_writephy(tp, 0x14, 0x9065);
3962         rtl_writephy(tp, 0x14, 0x1065);
3963
3964         /* Check ALDPS bit, disable it if enabled */
3965         rtl_writephy(tp, 0x1f, 0x0a43);
3966         if (rtl_readphy(tp, 0x10) & 0x0004)
3967                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3968
3969         rtl_writephy(tp, 0x1f, 0x0000);
3970 }
3971
3972 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3973 {
3974         rtl_apply_firmware(tp);
3975 }
3976
3977 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3978 {
3979         u16 dout_tapbin;
3980         u32 data;
3981
3982         rtl_apply_firmware(tp);
3983
3984         /* CHN EST parameters adjust - giga master */
3985         rtl_writephy(tp, 0x1f, 0x0a43);
3986         rtl_writephy(tp, 0x13, 0x809b);
3987         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3988         rtl_writephy(tp, 0x13, 0x80a2);
3989         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3990         rtl_writephy(tp, 0x13, 0x80a4);
3991         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3992         rtl_writephy(tp, 0x13, 0x809c);
3993         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3994         rtl_writephy(tp, 0x1f, 0x0000);
3995
3996         /* CHN EST parameters adjust - giga slave */
3997         rtl_writephy(tp, 0x1f, 0x0a43);
3998         rtl_writephy(tp, 0x13, 0x80ad);
3999         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
4000         rtl_writephy(tp, 0x13, 0x80b4);
4001         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
4002         rtl_writephy(tp, 0x13, 0x80ac);
4003         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
4004         rtl_writephy(tp, 0x1f, 0x0000);
4005
4006         /* CHN EST parameters adjust - fnet */
4007         rtl_writephy(tp, 0x1f, 0x0a43);
4008         rtl_writephy(tp, 0x13, 0x808e);
4009         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
4010         rtl_writephy(tp, 0x13, 0x8090);
4011         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
4012         rtl_writephy(tp, 0x13, 0x8092);
4013         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
4014         rtl_writephy(tp, 0x1f, 0x0000);
4015
4016         /* enable R-tune & PGA-retune function */
4017         dout_tapbin = 0;
4018         rtl_writephy(tp, 0x1f, 0x0a46);
4019         data = rtl_readphy(tp, 0x13);
4020         data &= 3;
4021         data <<= 2;
4022         dout_tapbin |= data;
4023         data = rtl_readphy(tp, 0x12);
4024         data &= 0xc000;
4025         data >>= 14;
4026         dout_tapbin |= data;
4027         dout_tapbin = ~(dout_tapbin^0x08);
4028         dout_tapbin <<= 12;
4029         dout_tapbin &= 0xf000;
4030         rtl_writephy(tp, 0x1f, 0x0a43);
4031         rtl_writephy(tp, 0x13, 0x827a);
4032         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4033         rtl_writephy(tp, 0x13, 0x827b);
4034         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4035         rtl_writephy(tp, 0x13, 0x827c);
4036         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4037         rtl_writephy(tp, 0x13, 0x827d);
4038         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4039
4040         rtl_writephy(tp, 0x1f, 0x0a43);
4041         rtl_writephy(tp, 0x13, 0x0811);
4042         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4043         rtl_writephy(tp, 0x1f, 0x0a42);
4044         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4045         rtl_writephy(tp, 0x1f, 0x0000);
4046
4047         /* enable GPHY 10M */
4048         rtl_writephy(tp, 0x1f, 0x0a44);
4049         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4050         rtl_writephy(tp, 0x1f, 0x0000);
4051
4052         /* SAR ADC performance */
4053         rtl_writephy(tp, 0x1f, 0x0bca);
4054         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
4055         rtl_writephy(tp, 0x1f, 0x0000);
4056
4057         rtl_writephy(tp, 0x1f, 0x0a43);
4058         rtl_writephy(tp, 0x13, 0x803f);
4059         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4060         rtl_writephy(tp, 0x13, 0x8047);
4061         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4062         rtl_writephy(tp, 0x13, 0x804f);
4063         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4064         rtl_writephy(tp, 0x13, 0x8057);
4065         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4066         rtl_writephy(tp, 0x13, 0x805f);
4067         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4068         rtl_writephy(tp, 0x13, 0x8067);
4069         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4070         rtl_writephy(tp, 0x13, 0x806f);
4071         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4072         rtl_writephy(tp, 0x1f, 0x0000);
4073
4074         /* disable phy pfm mode */
4075         rtl_writephy(tp, 0x1f, 0x0a44);
4076         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4077         rtl_writephy(tp, 0x1f, 0x0000);
4078
4079         /* Check ALDPS bit, disable it if enabled */
4080         rtl_writephy(tp, 0x1f, 0x0a43);
4081         if (rtl_readphy(tp, 0x10) & 0x0004)
4082                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4083
4084         rtl_writephy(tp, 0x1f, 0x0000);
4085 }
4086
4087 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4088 {
4089         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4090         u16 rlen;
4091         u32 data;
4092
4093         rtl_apply_firmware(tp);
4094
4095         /* CHIN EST parameter update */
4096         rtl_writephy(tp, 0x1f, 0x0a43);
4097         rtl_writephy(tp, 0x13, 0x808a);
4098         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
4099         rtl_writephy(tp, 0x1f, 0x0000);
4100
4101         /* enable R-tune & PGA-retune function */
4102         rtl_writephy(tp, 0x1f, 0x0a43);
4103         rtl_writephy(tp, 0x13, 0x0811);
4104         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4105         rtl_writephy(tp, 0x1f, 0x0a42);
4106         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4107         rtl_writephy(tp, 0x1f, 0x0000);
4108
4109         /* enable GPHY 10M */
4110         rtl_writephy(tp, 0x1f, 0x0a44);
4111         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4112         rtl_writephy(tp, 0x1f, 0x0000);
4113
4114         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4115         data = r8168_mac_ocp_read(tp, 0xdd02);
4116         ioffset_p3 = ((data & 0x80)>>7);
4117         ioffset_p3 <<= 3;
4118
4119         data = r8168_mac_ocp_read(tp, 0xdd00);
4120         ioffset_p3 |= ((data & (0xe000))>>13);
4121         ioffset_p2 = ((data & (0x1e00))>>9);
4122         ioffset_p1 = ((data & (0x01e0))>>5);
4123         ioffset_p0 = ((data & 0x0010)>>4);
4124         ioffset_p0 <<= 3;
4125         ioffset_p0 |= (data & (0x07));
4126         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4127
4128         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
4129             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
4130                 rtl_writephy(tp, 0x1f, 0x0bcf);
4131                 rtl_writephy(tp, 0x16, data);
4132                 rtl_writephy(tp, 0x1f, 0x0000);
4133         }
4134
4135         /* Modify rlen (TX LPF corner frequency) level */
4136         rtl_writephy(tp, 0x1f, 0x0bcd);
4137         data = rtl_readphy(tp, 0x16);
4138         data &= 0x000f;
4139         rlen = 0;
4140         if (data > 3)
4141                 rlen = data - 3;
4142         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4143         rtl_writephy(tp, 0x17, data);
4144         rtl_writephy(tp, 0x1f, 0x0bcd);
4145         rtl_writephy(tp, 0x1f, 0x0000);
4146
4147         /* disable phy pfm mode */
4148         rtl_writephy(tp, 0x1f, 0x0a44);
4149         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4150         rtl_writephy(tp, 0x1f, 0x0000);
4151
4152         /* Check ALDPS bit, disable it if enabled */
4153         rtl_writephy(tp, 0x1f, 0x0a43);
4154         if (rtl_readphy(tp, 0x10) & 0x0004)
4155                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4156
4157         rtl_writephy(tp, 0x1f, 0x0000);
4158 }
4159
4160 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4161 {
4162         /* Enable PHY auto speed down */
4163         rtl_writephy(tp, 0x1f, 0x0a44);
4164         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4165         rtl_writephy(tp, 0x1f, 0x0000);
4166
4167         /* patch 10M & ALDPS */
4168         rtl_writephy(tp, 0x1f, 0x0bcc);
4169         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4170         rtl_writephy(tp, 0x1f, 0x0a44);
4171         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4172         rtl_writephy(tp, 0x1f, 0x0a43);
4173         rtl_writephy(tp, 0x13, 0x8084);
4174         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4175         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4176         rtl_writephy(tp, 0x1f, 0x0000);
4177
4178         /* Enable EEE auto-fallback function */
4179         rtl_writephy(tp, 0x1f, 0x0a4b);
4180         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4181         rtl_writephy(tp, 0x1f, 0x0000);
4182
4183         /* Enable UC LPF tune function */
4184         rtl_writephy(tp, 0x1f, 0x0a43);
4185         rtl_writephy(tp, 0x13, 0x8012);
4186         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4187         rtl_writephy(tp, 0x1f, 0x0000);
4188
4189         /* set rg_sel_sdm_rate */
4190         rtl_writephy(tp, 0x1f, 0x0c42);
4191         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4192         rtl_writephy(tp, 0x1f, 0x0000);
4193
4194         /* Check ALDPS bit, disable it if enabled */
4195         rtl_writephy(tp, 0x1f, 0x0a43);
4196         if (rtl_readphy(tp, 0x10) & 0x0004)
4197                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4198
4199         rtl_writephy(tp, 0x1f, 0x0000);
4200 }
4201
4202 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4203 {
4204         /* patch 10M & ALDPS */
4205         rtl_writephy(tp, 0x1f, 0x0bcc);
4206         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4207         rtl_writephy(tp, 0x1f, 0x0a44);
4208         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4209         rtl_writephy(tp, 0x1f, 0x0a43);
4210         rtl_writephy(tp, 0x13, 0x8084);
4211         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4212         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4213         rtl_writephy(tp, 0x1f, 0x0000);
4214
4215         /* Enable UC LPF tune function */
4216         rtl_writephy(tp, 0x1f, 0x0a43);
4217         rtl_writephy(tp, 0x13, 0x8012);
4218         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4219         rtl_writephy(tp, 0x1f, 0x0000);
4220
4221         /* Set rg_sel_sdm_rate */
4222         rtl_writephy(tp, 0x1f, 0x0c42);
4223         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4224         rtl_writephy(tp, 0x1f, 0x0000);
4225
4226         /* Channel estimation parameters */
4227         rtl_writephy(tp, 0x1f, 0x0a43);
4228         rtl_writephy(tp, 0x13, 0x80f3);
4229         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4230         rtl_writephy(tp, 0x13, 0x80f0);
4231         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4232         rtl_writephy(tp, 0x13, 0x80ef);
4233         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4234         rtl_writephy(tp, 0x13, 0x80f6);
4235         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4236         rtl_writephy(tp, 0x13, 0x80ec);
4237         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4238         rtl_writephy(tp, 0x13, 0x80ed);
4239         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4240         rtl_writephy(tp, 0x13, 0x80f2);
4241         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4242         rtl_writephy(tp, 0x13, 0x80f4);
4243         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4244         rtl_writephy(tp, 0x1f, 0x0a43);
4245         rtl_writephy(tp, 0x13, 0x8110);
4246         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4247         rtl_writephy(tp, 0x13, 0x810f);
4248         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4249         rtl_writephy(tp, 0x13, 0x8111);
4250         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4251         rtl_writephy(tp, 0x13, 0x8113);
4252         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4253         rtl_writephy(tp, 0x13, 0x8115);
4254         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4255         rtl_writephy(tp, 0x13, 0x810e);
4256         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4257         rtl_writephy(tp, 0x13, 0x810c);
4258         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4259         rtl_writephy(tp, 0x13, 0x810b);
4260         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4261         rtl_writephy(tp, 0x1f, 0x0a43);
4262         rtl_writephy(tp, 0x13, 0x80d1);
4263         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4264         rtl_writephy(tp, 0x13, 0x80cd);
4265         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4266         rtl_writephy(tp, 0x13, 0x80d3);
4267         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4268         rtl_writephy(tp, 0x13, 0x80d5);
4269         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4270         rtl_writephy(tp, 0x13, 0x80d7);
4271         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4272
4273         /* Force PWM-mode */
4274         rtl_writephy(tp, 0x1f, 0x0bcd);
4275         rtl_writephy(tp, 0x14, 0x5065);
4276         rtl_writephy(tp, 0x14, 0xd065);
4277         rtl_writephy(tp, 0x1f, 0x0bc8);
4278         rtl_writephy(tp, 0x12, 0x00ed);
4279         rtl_writephy(tp, 0x1f, 0x0bcd);
4280         rtl_writephy(tp, 0x14, 0x1065);
4281         rtl_writephy(tp, 0x14, 0x9065);
4282         rtl_writephy(tp, 0x14, 0x1065);
4283         rtl_writephy(tp, 0x1f, 0x0000);
4284
4285         /* Check ALDPS bit, disable it if enabled */
4286         rtl_writephy(tp, 0x1f, 0x0a43);
4287         if (rtl_readphy(tp, 0x10) & 0x0004)
4288                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4289
4290         rtl_writephy(tp, 0x1f, 0x0000);
4291 }
4292
4293 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4294 {
4295         static const struct phy_reg phy_reg_init[] = {
4296                 { 0x1f, 0x0003 },
4297                 { 0x08, 0x441d },
4298                 { 0x01, 0x9100 },
4299                 { 0x1f, 0x0000 }
4300         };
4301
4302         rtl_writephy(tp, 0x1f, 0x0000);
4303         rtl_patchphy(tp, 0x11, 1 << 12);
4304         rtl_patchphy(tp, 0x19, 1 << 13);
4305         rtl_patchphy(tp, 0x10, 1 << 15);
4306
4307         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4308 }
4309
4310 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4311 {
4312         static const struct phy_reg phy_reg_init[] = {
4313                 { 0x1f, 0x0005 },
4314                 { 0x1a, 0x0000 },
4315                 { 0x1f, 0x0000 },
4316
4317                 { 0x1f, 0x0004 },
4318                 { 0x1c, 0x0000 },
4319                 { 0x1f, 0x0000 },
4320
4321                 { 0x1f, 0x0001 },
4322                 { 0x15, 0x7701 },
4323                 { 0x1f, 0x0000 }
4324         };
4325
4326         /* Disable ALDPS before ram code */
4327         rtl_writephy(tp, 0x1f, 0x0000);
4328         rtl_writephy(tp, 0x18, 0x0310);
4329         msleep(100);
4330
4331         rtl_apply_firmware(tp);
4332
4333         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4334 }
4335
4336 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4337 {
4338         /* Disable ALDPS before setting firmware */
4339         rtl_writephy(tp, 0x1f, 0x0000);
4340         rtl_writephy(tp, 0x18, 0x0310);
4341         msleep(20);
4342
4343         rtl_apply_firmware(tp);
4344
4345         /* EEE setting */
4346         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4347         rtl_writephy(tp, 0x1f, 0x0004);
4348         rtl_writephy(tp, 0x10, 0x401f);
4349         rtl_writephy(tp, 0x19, 0x7030);
4350         rtl_writephy(tp, 0x1f, 0x0000);
4351 }
4352
4353 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4354 {
4355         static const struct phy_reg phy_reg_init[] = {
4356                 { 0x1f, 0x0004 },
4357                 { 0x10, 0xc07f },
4358                 { 0x19, 0x7030 },
4359                 { 0x1f, 0x0000 }
4360         };
4361
4362         /* Disable ALDPS before ram code */
4363         rtl_writephy(tp, 0x1f, 0x0000);
4364         rtl_writephy(tp, 0x18, 0x0310);
4365         msleep(100);
4366
4367         rtl_apply_firmware(tp);
4368
4369         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4370         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4371
4372         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4373 }
4374
4375 static void rtl_hw_phy_config(struct net_device *dev)
4376 {
4377         struct rtl8169_private *tp = netdev_priv(dev);
4378
4379         rtl8169_print_mac_version(tp);
4380
4381         switch (tp->mac_version) {
4382         case RTL_GIGA_MAC_VER_01:
4383                 break;
4384         case RTL_GIGA_MAC_VER_02:
4385         case RTL_GIGA_MAC_VER_03:
4386                 rtl8169s_hw_phy_config(tp);
4387                 break;
4388         case RTL_GIGA_MAC_VER_04:
4389                 rtl8169sb_hw_phy_config(tp);
4390                 break;
4391         case RTL_GIGA_MAC_VER_05:
4392                 rtl8169scd_hw_phy_config(tp);
4393                 break;
4394         case RTL_GIGA_MAC_VER_06:
4395                 rtl8169sce_hw_phy_config(tp);
4396                 break;
4397         case RTL_GIGA_MAC_VER_07:
4398         case RTL_GIGA_MAC_VER_08:
4399         case RTL_GIGA_MAC_VER_09:
4400                 rtl8102e_hw_phy_config(tp);
4401                 break;
4402         case RTL_GIGA_MAC_VER_11:
4403                 rtl8168bb_hw_phy_config(tp);
4404                 break;
4405         case RTL_GIGA_MAC_VER_12:
4406                 rtl8168bef_hw_phy_config(tp);
4407                 break;
4408         case RTL_GIGA_MAC_VER_17:
4409                 rtl8168bef_hw_phy_config(tp);
4410                 break;
4411         case RTL_GIGA_MAC_VER_18:
4412                 rtl8168cp_1_hw_phy_config(tp);
4413                 break;
4414         case RTL_GIGA_MAC_VER_19:
4415                 rtl8168c_1_hw_phy_config(tp);
4416                 break;
4417         case RTL_GIGA_MAC_VER_20:
4418                 rtl8168c_2_hw_phy_config(tp);
4419                 break;
4420         case RTL_GIGA_MAC_VER_21:
4421                 rtl8168c_3_hw_phy_config(tp);
4422                 break;
4423         case RTL_GIGA_MAC_VER_22:
4424                 rtl8168c_4_hw_phy_config(tp);
4425                 break;
4426         case RTL_GIGA_MAC_VER_23:
4427         case RTL_GIGA_MAC_VER_24:
4428                 rtl8168cp_2_hw_phy_config(tp);
4429                 break;
4430         case RTL_GIGA_MAC_VER_25:
4431                 rtl8168d_1_hw_phy_config(tp);
4432                 break;
4433         case RTL_GIGA_MAC_VER_26:
4434                 rtl8168d_2_hw_phy_config(tp);
4435                 break;
4436         case RTL_GIGA_MAC_VER_27:
4437                 rtl8168d_3_hw_phy_config(tp);
4438                 break;
4439         case RTL_GIGA_MAC_VER_28:
4440                 rtl8168d_4_hw_phy_config(tp);
4441                 break;
4442         case RTL_GIGA_MAC_VER_29:
4443         case RTL_GIGA_MAC_VER_30:
4444                 rtl8105e_hw_phy_config(tp);
4445                 break;
4446         case RTL_GIGA_MAC_VER_31:
4447                 /* None. */
4448                 break;
4449         case RTL_GIGA_MAC_VER_32:
4450         case RTL_GIGA_MAC_VER_33:
4451                 rtl8168e_1_hw_phy_config(tp);
4452                 break;
4453         case RTL_GIGA_MAC_VER_34:
4454                 rtl8168e_2_hw_phy_config(tp);
4455                 break;
4456         case RTL_GIGA_MAC_VER_35:
4457                 rtl8168f_1_hw_phy_config(tp);
4458                 break;
4459         case RTL_GIGA_MAC_VER_36:
4460                 rtl8168f_2_hw_phy_config(tp);
4461                 break;
4462
4463         case RTL_GIGA_MAC_VER_37:
4464                 rtl8402_hw_phy_config(tp);
4465                 break;
4466
4467         case RTL_GIGA_MAC_VER_38:
4468                 rtl8411_hw_phy_config(tp);
4469                 break;
4470
4471         case RTL_GIGA_MAC_VER_39:
4472                 rtl8106e_hw_phy_config(tp);
4473                 break;
4474
4475         case RTL_GIGA_MAC_VER_40:
4476                 rtl8168g_1_hw_phy_config(tp);
4477                 break;
4478         case RTL_GIGA_MAC_VER_42:
4479         case RTL_GIGA_MAC_VER_43:
4480         case RTL_GIGA_MAC_VER_44:
4481                 rtl8168g_2_hw_phy_config(tp);
4482                 break;
4483         case RTL_GIGA_MAC_VER_45:
4484         case RTL_GIGA_MAC_VER_47:
4485                 rtl8168h_1_hw_phy_config(tp);
4486                 break;
4487         case RTL_GIGA_MAC_VER_46:
4488         case RTL_GIGA_MAC_VER_48:
4489                 rtl8168h_2_hw_phy_config(tp);
4490                 break;
4491
4492         case RTL_GIGA_MAC_VER_49:
4493                 rtl8168ep_1_hw_phy_config(tp);
4494                 break;
4495         case RTL_GIGA_MAC_VER_50:
4496         case RTL_GIGA_MAC_VER_51:
4497                 rtl8168ep_2_hw_phy_config(tp);
4498                 break;
4499
4500         case RTL_GIGA_MAC_VER_41:
4501         default:
4502                 break;
4503         }
4504 }
4505
4506 static void rtl_phy_work(struct rtl8169_private *tp)
4507 {
4508         struct timer_list *timer = &tp->timer;
4509         unsigned long timeout = RTL8169_PHY_TIMEOUT;
4510
4511         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4512
4513         if (tp->phy_reset_pending(tp)) {
4514                 /*
4515                  * A busy loop could burn quite a few cycles on nowadays CPU.
4516                  * Let's delay the execution of the timer for a few ticks.
4517                  */
4518                 timeout = HZ/10;
4519                 goto out_mod_timer;
4520         }
4521
4522         if (tp->link_ok(tp))
4523                 return;
4524
4525         netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4526
4527         tp->phy_reset_enable(tp);
4528
4529 out_mod_timer:
4530         mod_timer(timer, jiffies + timeout);
4531 }
4532
4533 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4534 {
4535         if (!test_and_set_bit(flag, tp->wk.flags))
4536                 schedule_work(&tp->wk.work);
4537 }
4538
4539 static void rtl8169_phy_timer(struct timer_list *t)
4540 {
4541         struct rtl8169_private *tp = from_timer(tp, t, timer);
4542
4543         rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4544 }
4545
4546 DECLARE_RTL_COND(rtl_phy_reset_cond)
4547 {
4548         return tp->phy_reset_pending(tp);
4549 }
4550
4551 static void rtl8169_phy_reset(struct net_device *dev,
4552                               struct rtl8169_private *tp)
4553 {
4554         tp->phy_reset_enable(tp);
4555         rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4556 }
4557
4558 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4559 {
4560         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4561             (RTL_R8(tp, PHYstatus) & TBI_Enable);
4562 }
4563
4564 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4565 {
4566         rtl_hw_phy_config(dev);
4567
4568         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4569                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4570                 RTL_W8(tp, 0x82, 0x01);
4571         }
4572
4573         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4574
4575         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4576                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4577
4578         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4579                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4580                 RTL_W8(tp, 0x82, 0x01);
4581                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4582                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4583         }
4584
4585         rtl8169_phy_reset(dev, tp);
4586
4587         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4588                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4589                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4590                           (tp->mii.supports_gmii ?
4591                            ADVERTISED_1000baseT_Half |
4592                            ADVERTISED_1000baseT_Full : 0));
4593
4594         if (rtl_tbi_enabled(tp))
4595                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4596 }
4597
4598 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4599 {
4600         rtl_lock_work(tp);
4601
4602         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4603
4604         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4605         RTL_R32(tp, MAC4);
4606
4607         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4608         RTL_R32(tp, MAC0);
4609
4610         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4611                 rtl_rar_exgmac_set(tp, addr);
4612
4613         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4614
4615         rtl_unlock_work(tp);
4616 }
4617
4618 static int rtl_set_mac_address(struct net_device *dev, void *p)
4619 {
4620         struct rtl8169_private *tp = netdev_priv(dev);
4621         struct device *d = tp_to_dev(tp);
4622         int ret;
4623
4624         ret = eth_mac_addr(dev, p);
4625         if (ret)
4626                 return ret;
4627
4628         pm_runtime_get_noresume(d);
4629
4630         if (pm_runtime_active(d))
4631                 rtl_rar_set(tp, dev->dev_addr);
4632
4633         pm_runtime_put_noidle(d);
4634
4635         return 0;
4636 }
4637
4638 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4639 {
4640         struct rtl8169_private *tp = netdev_priv(dev);
4641         struct mii_ioctl_data *data = if_mii(ifr);
4642
4643         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4644 }
4645
4646 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4647                           struct mii_ioctl_data *data, int cmd)
4648 {
4649         switch (cmd) {
4650         case SIOCGMIIPHY:
4651                 data->phy_id = 32; /* Internal PHY */
4652                 return 0;
4653
4654         case SIOCGMIIREG:
4655                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4656                 return 0;
4657
4658         case SIOCSMIIREG:
4659                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4660                 return 0;
4661         }
4662         return -EOPNOTSUPP;
4663 }
4664
4665 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4666 {
4667         return -EOPNOTSUPP;
4668 }
4669
4670 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4671 {
4672         struct mdio_ops *ops = &tp->mdio_ops;
4673
4674         switch (tp->mac_version) {
4675         case RTL_GIGA_MAC_VER_27:
4676                 ops->write      = r8168dp_1_mdio_write;
4677                 ops->read       = r8168dp_1_mdio_read;
4678                 break;
4679         case RTL_GIGA_MAC_VER_28:
4680         case RTL_GIGA_MAC_VER_31:
4681                 ops->write      = r8168dp_2_mdio_write;
4682                 ops->read       = r8168dp_2_mdio_read;
4683                 break;
4684         case RTL_GIGA_MAC_VER_40:
4685         case RTL_GIGA_MAC_VER_41:
4686         case RTL_GIGA_MAC_VER_42:
4687         case RTL_GIGA_MAC_VER_43:
4688         case RTL_GIGA_MAC_VER_44:
4689         case RTL_GIGA_MAC_VER_45:
4690         case RTL_GIGA_MAC_VER_46:
4691         case RTL_GIGA_MAC_VER_47:
4692         case RTL_GIGA_MAC_VER_48:
4693         case RTL_GIGA_MAC_VER_49:
4694         case RTL_GIGA_MAC_VER_50:
4695         case RTL_GIGA_MAC_VER_51:
4696                 ops->write      = r8168g_mdio_write;
4697                 ops->read       = r8168g_mdio_read;
4698                 break;
4699         default:
4700                 ops->write      = r8169_mdio_write;
4701                 ops->read       = r8169_mdio_read;
4702                 break;
4703         }
4704 }
4705
4706 static void rtl_speed_down(struct rtl8169_private *tp)
4707 {
4708         u32 adv;
4709         int lpa;
4710
4711         rtl_writephy(tp, 0x1f, 0x0000);
4712         lpa = rtl_readphy(tp, MII_LPA);
4713
4714         if (lpa & (LPA_10HALF | LPA_10FULL))
4715                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4716         else if (lpa & (LPA_100HALF | LPA_100FULL))
4717                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4718                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4719         else
4720                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4721                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4722                       (tp->mii.supports_gmii ?
4723                        ADVERTISED_1000baseT_Half |
4724                        ADVERTISED_1000baseT_Full : 0);
4725
4726         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4727                           adv);
4728 }
4729
4730 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4731 {
4732         switch (tp->mac_version) {
4733         case RTL_GIGA_MAC_VER_25:
4734         case RTL_GIGA_MAC_VER_26:
4735         case RTL_GIGA_MAC_VER_29:
4736         case RTL_GIGA_MAC_VER_30:
4737         case RTL_GIGA_MAC_VER_32:
4738         case RTL_GIGA_MAC_VER_33:
4739         case RTL_GIGA_MAC_VER_34:
4740         case RTL_GIGA_MAC_VER_37:
4741         case RTL_GIGA_MAC_VER_38:
4742         case RTL_GIGA_MAC_VER_39:
4743         case RTL_GIGA_MAC_VER_40:
4744         case RTL_GIGA_MAC_VER_41:
4745         case RTL_GIGA_MAC_VER_42:
4746         case RTL_GIGA_MAC_VER_43:
4747         case RTL_GIGA_MAC_VER_44:
4748         case RTL_GIGA_MAC_VER_45:
4749         case RTL_GIGA_MAC_VER_46:
4750         case RTL_GIGA_MAC_VER_47:
4751         case RTL_GIGA_MAC_VER_48:
4752         case RTL_GIGA_MAC_VER_49:
4753         case RTL_GIGA_MAC_VER_50:
4754         case RTL_GIGA_MAC_VER_51:
4755                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4756                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4757                 break;
4758         default:
4759                 break;
4760         }
4761 }
4762
4763 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4764 {
4765         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4766                 return false;
4767
4768         rtl_speed_down(tp);
4769         rtl_wol_suspend_quirk(tp);
4770
4771         return true;
4772 }
4773
4774 static void r810x_phy_power_down(struct rtl8169_private *tp)
4775 {
4776         rtl_writephy(tp, 0x1f, 0x0000);
4777         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4778 }
4779
4780 static void r810x_phy_power_up(struct rtl8169_private *tp)
4781 {
4782         rtl_writephy(tp, 0x1f, 0x0000);
4783         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4784 }
4785
4786 static void r810x_pll_power_down(struct rtl8169_private *tp)
4787 {
4788         if (rtl_wol_pll_power_down(tp))
4789                 return;
4790
4791         r810x_phy_power_down(tp);
4792
4793         switch (tp->mac_version) {
4794         case RTL_GIGA_MAC_VER_07:
4795         case RTL_GIGA_MAC_VER_08:
4796         case RTL_GIGA_MAC_VER_09:
4797         case RTL_GIGA_MAC_VER_10:
4798         case RTL_GIGA_MAC_VER_13:
4799         case RTL_GIGA_MAC_VER_16:
4800                 break;
4801         default:
4802                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4803                 break;
4804         }
4805 }
4806
4807 static void r810x_pll_power_up(struct rtl8169_private *tp)
4808 {
4809         r810x_phy_power_up(tp);
4810
4811         switch (tp->mac_version) {
4812         case RTL_GIGA_MAC_VER_07:
4813         case RTL_GIGA_MAC_VER_08:
4814         case RTL_GIGA_MAC_VER_09:
4815         case RTL_GIGA_MAC_VER_10:
4816         case RTL_GIGA_MAC_VER_13:
4817         case RTL_GIGA_MAC_VER_16:
4818                 break;
4819         case RTL_GIGA_MAC_VER_47:
4820         case RTL_GIGA_MAC_VER_48:
4821                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4822                 break;
4823         default:
4824                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4825                 break;
4826         }
4827 }
4828
4829 static void r8168_phy_power_up(struct rtl8169_private *tp)
4830 {
4831         rtl_writephy(tp, 0x1f, 0x0000);
4832         switch (tp->mac_version) {
4833         case RTL_GIGA_MAC_VER_11:
4834         case RTL_GIGA_MAC_VER_12:
4835         case RTL_GIGA_MAC_VER_17:
4836         case RTL_GIGA_MAC_VER_18:
4837         case RTL_GIGA_MAC_VER_19:
4838         case RTL_GIGA_MAC_VER_20:
4839         case RTL_GIGA_MAC_VER_21:
4840         case RTL_GIGA_MAC_VER_22:
4841         case RTL_GIGA_MAC_VER_23:
4842         case RTL_GIGA_MAC_VER_24:
4843         case RTL_GIGA_MAC_VER_25:
4844         case RTL_GIGA_MAC_VER_26:
4845         case RTL_GIGA_MAC_VER_27:
4846         case RTL_GIGA_MAC_VER_28:
4847         case RTL_GIGA_MAC_VER_31:
4848                 rtl_writephy(tp, 0x0e, 0x0000);
4849                 break;
4850         default:
4851                 break;
4852         }
4853         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4854 }
4855
4856 static void r8168_phy_power_down(struct rtl8169_private *tp)
4857 {
4858         rtl_writephy(tp, 0x1f, 0x0000);
4859         switch (tp->mac_version) {
4860         case RTL_GIGA_MAC_VER_32:
4861         case RTL_GIGA_MAC_VER_33:
4862         case RTL_GIGA_MAC_VER_40:
4863         case RTL_GIGA_MAC_VER_41:
4864                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4865                 break;
4866
4867         case RTL_GIGA_MAC_VER_11:
4868         case RTL_GIGA_MAC_VER_12:
4869         case RTL_GIGA_MAC_VER_17:
4870         case RTL_GIGA_MAC_VER_18:
4871         case RTL_GIGA_MAC_VER_19:
4872         case RTL_GIGA_MAC_VER_20:
4873         case RTL_GIGA_MAC_VER_21:
4874         case RTL_GIGA_MAC_VER_22:
4875         case RTL_GIGA_MAC_VER_23:
4876         case RTL_GIGA_MAC_VER_24:
4877         case RTL_GIGA_MAC_VER_25:
4878         case RTL_GIGA_MAC_VER_26:
4879         case RTL_GIGA_MAC_VER_27:
4880         case RTL_GIGA_MAC_VER_28:
4881         case RTL_GIGA_MAC_VER_31:
4882                 rtl_writephy(tp, 0x0e, 0x0200);
4883         default:
4884                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4885                 break;
4886         }
4887 }
4888
4889 static void r8168_pll_power_down(struct rtl8169_private *tp)
4890 {
4891         if (r8168_check_dash(tp))
4892                 return;
4893
4894         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4895              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4896             (RTL_R16(tp, CPlusCmd) & ASF)) {
4897                 return;
4898         }
4899
4900         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4901             tp->mac_version == RTL_GIGA_MAC_VER_33)
4902                 rtl_ephy_write(tp, 0x19, 0xff64);
4903
4904         if (rtl_wol_pll_power_down(tp))
4905                 return;
4906
4907         r8168_phy_power_down(tp);
4908
4909         switch (tp->mac_version) {
4910         case RTL_GIGA_MAC_VER_25:
4911         case RTL_GIGA_MAC_VER_26:
4912         case RTL_GIGA_MAC_VER_27:
4913         case RTL_GIGA_MAC_VER_28:
4914         case RTL_GIGA_MAC_VER_31:
4915         case RTL_GIGA_MAC_VER_32:
4916         case RTL_GIGA_MAC_VER_33:
4917         case RTL_GIGA_MAC_VER_44:
4918         case RTL_GIGA_MAC_VER_45:
4919         case RTL_GIGA_MAC_VER_46:
4920         case RTL_GIGA_MAC_VER_50:
4921         case RTL_GIGA_MAC_VER_51:
4922                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4923                 break;
4924         case RTL_GIGA_MAC_VER_40:
4925         case RTL_GIGA_MAC_VER_41:
4926         case RTL_GIGA_MAC_VER_49:
4927                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4928                              0xfc000000, ERIAR_EXGMAC);
4929                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4930                 break;
4931         }
4932 }
4933
4934 static void r8168_pll_power_up(struct rtl8169_private *tp)
4935 {
4936         switch (tp->mac_version) {
4937         case RTL_GIGA_MAC_VER_25:
4938         case RTL_GIGA_MAC_VER_26:
4939         case RTL_GIGA_MAC_VER_27:
4940         case RTL_GIGA_MAC_VER_28:
4941         case RTL_GIGA_MAC_VER_31:
4942         case RTL_GIGA_MAC_VER_32:
4943         case RTL_GIGA_MAC_VER_33:
4944                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4945                 break;
4946         case RTL_GIGA_MAC_VER_44:
4947         case RTL_GIGA_MAC_VER_45:
4948         case RTL_GIGA_MAC_VER_46:
4949         case RTL_GIGA_MAC_VER_50:
4950         case RTL_GIGA_MAC_VER_51:
4951                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4952                 break;
4953         case RTL_GIGA_MAC_VER_40:
4954         case RTL_GIGA_MAC_VER_41:
4955         case RTL_GIGA_MAC_VER_49:
4956                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4957                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4958                              0x00000000, ERIAR_EXGMAC);
4959                 break;
4960         }
4961
4962         r8168_phy_power_up(tp);
4963 }
4964
4965 static void rtl_generic_op(struct rtl8169_private *tp,
4966                            void (*op)(struct rtl8169_private *))
4967 {
4968         if (op)
4969                 op(tp);
4970 }
4971
4972 static void rtl_pll_power_down(struct rtl8169_private *tp)
4973 {
4974         rtl_generic_op(tp, tp->pll_power_ops.down);
4975 }
4976
4977 static void rtl_pll_power_up(struct rtl8169_private *tp)
4978 {
4979         rtl_generic_op(tp, tp->pll_power_ops.up);
4980 }
4981
4982 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4983 {
4984         struct pll_power_ops *ops = &tp->pll_power_ops;
4985
4986         switch (tp->mac_version) {
4987         case RTL_GIGA_MAC_VER_07:
4988         case RTL_GIGA_MAC_VER_08:
4989         case RTL_GIGA_MAC_VER_09:
4990         case RTL_GIGA_MAC_VER_10:
4991         case RTL_GIGA_MAC_VER_16:
4992         case RTL_GIGA_MAC_VER_29:
4993         case RTL_GIGA_MAC_VER_30:
4994         case RTL_GIGA_MAC_VER_37:
4995         case RTL_GIGA_MAC_VER_39:
4996         case RTL_GIGA_MAC_VER_43:
4997         case RTL_GIGA_MAC_VER_47:
4998         case RTL_GIGA_MAC_VER_48:
4999                 ops->down       = r810x_pll_power_down;
5000                 ops->up         = r810x_pll_power_up;
5001                 break;
5002
5003         case RTL_GIGA_MAC_VER_11:
5004         case RTL_GIGA_MAC_VER_12:
5005         case RTL_GIGA_MAC_VER_17:
5006         case RTL_GIGA_MAC_VER_18:
5007         case RTL_GIGA_MAC_VER_19:
5008         case RTL_GIGA_MAC_VER_20:
5009         case RTL_GIGA_MAC_VER_21:
5010         case RTL_GIGA_MAC_VER_22:
5011         case RTL_GIGA_MAC_VER_23:
5012         case RTL_GIGA_MAC_VER_24:
5013         case RTL_GIGA_MAC_VER_25:
5014         case RTL_GIGA_MAC_VER_26:
5015         case RTL_GIGA_MAC_VER_27:
5016         case RTL_GIGA_MAC_VER_28:
5017         case RTL_GIGA_MAC_VER_31:
5018         case RTL_GIGA_MAC_VER_32:
5019         case RTL_GIGA_MAC_VER_33:
5020         case RTL_GIGA_MAC_VER_34:
5021         case RTL_GIGA_MAC_VER_35:
5022         case RTL_GIGA_MAC_VER_36:
5023         case RTL_GIGA_MAC_VER_38:
5024         case RTL_GIGA_MAC_VER_40:
5025         case RTL_GIGA_MAC_VER_41:
5026         case RTL_GIGA_MAC_VER_42:
5027         case RTL_GIGA_MAC_VER_44:
5028         case RTL_GIGA_MAC_VER_45:
5029         case RTL_GIGA_MAC_VER_46:
5030         case RTL_GIGA_MAC_VER_49:
5031         case RTL_GIGA_MAC_VER_50:
5032         case RTL_GIGA_MAC_VER_51:
5033                 ops->down       = r8168_pll_power_down;
5034                 ops->up         = r8168_pll_power_up;
5035                 break;
5036
5037         default:
5038                 ops->down       = NULL;
5039                 ops->up         = NULL;
5040                 break;
5041         }
5042 }
5043
5044 static void rtl_init_rxcfg(struct rtl8169_private *tp)
5045 {
5046         switch (tp->mac_version) {
5047         case RTL_GIGA_MAC_VER_01:
5048         case RTL_GIGA_MAC_VER_02:
5049         case RTL_GIGA_MAC_VER_03:
5050         case RTL_GIGA_MAC_VER_04:
5051         case RTL_GIGA_MAC_VER_05:
5052         case RTL_GIGA_MAC_VER_06:
5053         case RTL_GIGA_MAC_VER_10:
5054         case RTL_GIGA_MAC_VER_11:
5055         case RTL_GIGA_MAC_VER_12:
5056         case RTL_GIGA_MAC_VER_13:
5057         case RTL_GIGA_MAC_VER_14:
5058         case RTL_GIGA_MAC_VER_15:
5059         case RTL_GIGA_MAC_VER_16:
5060         case RTL_GIGA_MAC_VER_17:
5061                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5062                 break;
5063         case RTL_GIGA_MAC_VER_18:
5064         case RTL_GIGA_MAC_VER_19:
5065         case RTL_GIGA_MAC_VER_20:
5066         case RTL_GIGA_MAC_VER_21:
5067         case RTL_GIGA_MAC_VER_22:
5068         case RTL_GIGA_MAC_VER_23:
5069         case RTL_GIGA_MAC_VER_24:
5070         case RTL_GIGA_MAC_VER_34:
5071         case RTL_GIGA_MAC_VER_35:
5072                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5073                 break;
5074         case RTL_GIGA_MAC_VER_40:
5075         case RTL_GIGA_MAC_VER_41:
5076         case RTL_GIGA_MAC_VER_42:
5077         case RTL_GIGA_MAC_VER_43:
5078         case RTL_GIGA_MAC_VER_44:
5079         case RTL_GIGA_MAC_VER_45:
5080         case RTL_GIGA_MAC_VER_46:
5081         case RTL_GIGA_MAC_VER_47:
5082         case RTL_GIGA_MAC_VER_48:
5083         case RTL_GIGA_MAC_VER_49:
5084         case RTL_GIGA_MAC_VER_50:
5085         case RTL_GIGA_MAC_VER_51:
5086                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
5087                 break;
5088         default:
5089                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
5090                 break;
5091         }
5092 }
5093
5094 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5095 {
5096         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5097 }
5098
5099 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5100 {
5101         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5102         rtl_generic_op(tp, tp->jumbo_ops.enable);
5103         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5104 }
5105
5106 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5107 {
5108         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5109         rtl_generic_op(tp, tp->jumbo_ops.disable);
5110         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5111 }
5112
5113 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5114 {
5115         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5116         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
5117         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
5118 }
5119
5120 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5121 {
5122         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5123         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
5124         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5125 }
5126
5127 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5128 {
5129         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5130 }
5131
5132 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5133 {
5134         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5135 }
5136
5137 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5138 {
5139         RTL_W8(tp, MaxTxPacketSize, 0x3f);
5140         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
5141         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
5142         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
5143 }
5144
5145 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5146 {
5147         RTL_W8(tp, MaxTxPacketSize, 0x0c);
5148         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
5149         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
5150         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5151 }
5152
5153 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5154 {
5155         rtl_tx_performance_tweak(tp,
5156                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5157 }
5158
5159 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5160 {
5161         rtl_tx_performance_tweak(tp,
5162                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5163 }
5164
5165 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5166 {
5167         r8168b_0_hw_jumbo_enable(tp);
5168
5169         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
5170 }
5171
5172 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5173 {
5174         r8168b_0_hw_jumbo_disable(tp);
5175
5176         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5177 }
5178
5179 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5180 {
5181         struct jumbo_ops *ops = &tp->jumbo_ops;
5182
5183         switch (tp->mac_version) {
5184         case RTL_GIGA_MAC_VER_11:
5185                 ops->disable    = r8168b_0_hw_jumbo_disable;
5186                 ops->enable     = r8168b_0_hw_jumbo_enable;
5187                 break;
5188         case RTL_GIGA_MAC_VER_12:
5189         case RTL_GIGA_MAC_VER_17:
5190                 ops->disable    = r8168b_1_hw_jumbo_disable;
5191                 ops->enable     = r8168b_1_hw_jumbo_enable;
5192                 break;
5193         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5194         case RTL_GIGA_MAC_VER_19:
5195         case RTL_GIGA_MAC_VER_20:
5196         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5197         case RTL_GIGA_MAC_VER_22:
5198         case RTL_GIGA_MAC_VER_23:
5199         case RTL_GIGA_MAC_VER_24:
5200         case RTL_GIGA_MAC_VER_25:
5201         case RTL_GIGA_MAC_VER_26:
5202                 ops->disable    = r8168c_hw_jumbo_disable;
5203                 ops->enable     = r8168c_hw_jumbo_enable;
5204                 break;
5205         case RTL_GIGA_MAC_VER_27:
5206         case RTL_GIGA_MAC_VER_28:
5207                 ops->disable    = r8168dp_hw_jumbo_disable;
5208                 ops->enable     = r8168dp_hw_jumbo_enable;
5209                 break;
5210         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5211         case RTL_GIGA_MAC_VER_32:
5212         case RTL_GIGA_MAC_VER_33:
5213         case RTL_GIGA_MAC_VER_34:
5214                 ops->disable    = r8168e_hw_jumbo_disable;
5215                 ops->enable     = r8168e_hw_jumbo_enable;
5216                 break;
5217
5218         /*
5219          * No action needed for jumbo frames with 8169.
5220          * No jumbo for 810x at all.
5221          */
5222         case RTL_GIGA_MAC_VER_40:
5223         case RTL_GIGA_MAC_VER_41:
5224         case RTL_GIGA_MAC_VER_42:
5225         case RTL_GIGA_MAC_VER_43:
5226         case RTL_GIGA_MAC_VER_44:
5227         case RTL_GIGA_MAC_VER_45:
5228         case RTL_GIGA_MAC_VER_46:
5229         case RTL_GIGA_MAC_VER_47:
5230         case RTL_GIGA_MAC_VER_48:
5231         case RTL_GIGA_MAC_VER_49:
5232         case RTL_GIGA_MAC_VER_50:
5233         case RTL_GIGA_MAC_VER_51:
5234         default:
5235                 ops->disable    = NULL;
5236                 ops->enable     = NULL;
5237                 break;
5238         }
5239 }
5240
5241 DECLARE_RTL_COND(rtl_chipcmd_cond)
5242 {
5243         return RTL_R8(tp, ChipCmd) & CmdReset;
5244 }
5245
5246 static void rtl_hw_reset(struct rtl8169_private *tp)
5247 {
5248         RTL_W8(tp, ChipCmd, CmdReset);
5249
5250         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5251 }
5252
5253 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5254 {
5255         struct rtl_fw *rtl_fw;
5256         const char *name;
5257         int rc = -ENOMEM;
5258
5259         name = rtl_lookup_firmware_name(tp);
5260         if (!name)
5261                 goto out_no_firmware;
5262
5263         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5264         if (!rtl_fw)
5265                 goto err_warn;
5266
5267         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
5268         if (rc < 0)
5269                 goto err_free;
5270
5271         rc = rtl_check_firmware(tp, rtl_fw);
5272         if (rc < 0)
5273                 goto err_release_firmware;
5274
5275         tp->rtl_fw = rtl_fw;
5276 out:
5277         return;
5278
5279 err_release_firmware:
5280         release_firmware(rtl_fw->fw);
5281 err_free:
5282         kfree(rtl_fw);
5283 err_warn:
5284         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5285                    name, rc);
5286 out_no_firmware:
5287         tp->rtl_fw = NULL;
5288         goto out;
5289 }
5290
5291 static void rtl_request_firmware(struct rtl8169_private *tp)
5292 {
5293         if (IS_ERR(tp->rtl_fw))
5294                 rtl_request_uncached_firmware(tp);
5295 }
5296
5297 static void rtl_rx_close(struct rtl8169_private *tp)
5298 {
5299         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5300 }
5301
5302 DECLARE_RTL_COND(rtl_npq_cond)
5303 {
5304         return RTL_R8(tp, TxPoll) & NPQ;
5305 }
5306
5307 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5308 {
5309         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
5310 }
5311
5312 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5313 {
5314         /* Disable interrupts */
5315         rtl8169_irq_mask_and_ack(tp);
5316
5317         rtl_rx_close(tp);
5318
5319         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5320             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5321             tp->mac_version == RTL_GIGA_MAC_VER_31) {
5322                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5323         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5324                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5325                    tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5326                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5327                    tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5328                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5329                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5330                    tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5331                    tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5332                    tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5333                    tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5334                    tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5335                    tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5336                    tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5337                    tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5338                    tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5339                    tp->mac_version == RTL_GIGA_MAC_VER_51) {
5340                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5341                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5342         } else {
5343                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
5344                 udelay(100);
5345         }
5346
5347         rtl_hw_reset(tp);
5348 }
5349
5350 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5351 {
5352         /* Set DMA burst size and Interframe Gap Time */
5353         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
5354                 (InterFrameGap << TxInterFrameGapShift));
5355 }
5356
5357 static void rtl_hw_start(struct  rtl8169_private *tp)
5358 {
5359         tp->hw_start(tp);
5360         rtl_irq_enable_all(tp);
5361 }
5362
5363 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
5364 {
5365         /*
5366          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5367          * register to be written before TxDescAddrLow to work.
5368          * Switching from MMIO to I/O access fixes the issue as well.
5369          */
5370         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5371         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5372         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5373         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5374 }
5375
5376 static u16 rtl_rw_cpluscmd(struct rtl8169_private *tp)
5377 {
5378         u16 cmd;
5379
5380         cmd = RTL_R16(tp, CPlusCmd);
5381         RTL_W16(tp, CPlusCmd, cmd);
5382         return cmd;
5383 }
5384
5385 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
5386 {
5387         /* Low hurts. Let's disable the filtering. */
5388         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
5389 }
5390
5391 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
5392 {
5393         static const struct rtl_cfg2_info {
5394                 u32 mac_version;
5395                 u32 clk;
5396                 u32 val;
5397         } cfg2_info [] = {
5398                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5399                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5400                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5401                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5402         };
5403         const struct rtl_cfg2_info *p = cfg2_info;
5404         unsigned int i;
5405         u32 clk;
5406
5407         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
5408         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5409                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5410                         RTL_W32(tp, 0x7c, p->val);
5411                         break;
5412                 }
5413         }
5414 }
5415
5416 static void rtl_set_rx_mode(struct net_device *dev)
5417 {
5418         struct rtl8169_private *tp = netdev_priv(dev);
5419         u32 mc_filter[2];       /* Multicast hash filter */
5420         int rx_mode;
5421         u32 tmp = 0;
5422
5423         if (dev->flags & IFF_PROMISC) {
5424                 /* Unconditionally log net taps. */
5425                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5426                 rx_mode =
5427                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5428                     AcceptAllPhys;
5429                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5430         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5431                    (dev->flags & IFF_ALLMULTI)) {
5432                 /* Too many to filter perfectly -- accept all multicasts. */
5433                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5434                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5435         } else {
5436                 struct netdev_hw_addr *ha;
5437
5438                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5439                 mc_filter[1] = mc_filter[0] = 0;
5440                 netdev_for_each_mc_addr(ha, dev) {
5441                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5442                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5443                         rx_mode |= AcceptMulticast;
5444                 }
5445         }
5446
5447         if (dev->features & NETIF_F_RXALL)
5448                 rx_mode |= (AcceptErr | AcceptRunt);
5449
5450         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5451
5452         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5453                 u32 data = mc_filter[0];
5454
5455                 mc_filter[0] = swab32(mc_filter[1]);
5456                 mc_filter[1] = swab32(data);
5457         }
5458
5459         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5460                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5461
5462         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
5463         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
5464
5465         RTL_W32(tp, RxConfig, tmp);
5466 }
5467
5468 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5469 {
5470         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5471                 RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) | PCIMulRW);
5472                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5473         }
5474
5475         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
5476         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5477             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5478             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5479             tp->mac_version == RTL_GIGA_MAC_VER_04)
5480                 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5481
5482         rtl_init_rxcfg(tp);
5483
5484         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5485
5486         rtl_set_rx_max_size(tp);
5487
5488         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5489             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5490             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5491             tp->mac_version == RTL_GIGA_MAC_VER_04)
5492                 rtl_set_rx_tx_config_registers(tp);
5493
5494         tp->cp_cmd |= rtl_rw_cpluscmd(tp) | PCIMulRW;
5495
5496         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5497             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5498                 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5499                         "Bit-3 and bit-14 MUST be 1\n");
5500                 tp->cp_cmd |= (1 << 14);
5501         }
5502
5503         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5504
5505         rtl8169_set_magic_reg(tp, tp->mac_version);
5506
5507         /*
5508          * Undocumented corner. Supposedly:
5509          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5510          */
5511         RTL_W16(tp, IntrMitigate, 0x0000);
5512
5513         rtl_set_rx_tx_desc_registers(tp);
5514
5515         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5516             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5517             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5518             tp->mac_version != RTL_GIGA_MAC_VER_04) {
5519                 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5520                 rtl_set_rx_tx_config_registers(tp);
5521         }
5522
5523         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
5524
5525         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5526         RTL_R8(tp, IntrMask);
5527
5528         RTL_W32(tp, RxMissed, 0);
5529
5530         rtl_set_rx_mode(tp->dev);
5531
5532         /* no early-rx interrupts */
5533         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
5534 }
5535
5536 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5537 {
5538         if (tp->csi_ops.write)
5539                 tp->csi_ops.write(tp, addr, value);
5540 }
5541
5542 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5543 {
5544         return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5545 }
5546
5547 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5548 {
5549         u32 csi;
5550
5551         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5552         rtl_csi_write(tp, 0x070c, csi | bits);
5553 }
5554
5555 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5556 {
5557         rtl_csi_access_enable(tp, 0x17000000);
5558 }
5559
5560 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5561 {
5562         rtl_csi_access_enable(tp, 0x27000000);
5563 }
5564
5565 DECLARE_RTL_COND(rtl_csiar_cond)
5566 {
5567         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
5568 }
5569
5570 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5571 {
5572         RTL_W32(tp, CSIDR, value);
5573         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5574                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5575
5576         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5577 }
5578
5579 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5580 {
5581         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) |
5582                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5583
5584         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5585                 RTL_R32(tp, CSIDR) : ~0;
5586 }
5587
5588 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5589 {
5590         RTL_W32(tp, CSIDR, value);
5591         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5592                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5593                 CSIAR_FUNC_NIC);
5594
5595         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5596 }
5597
5598 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5599 {
5600         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5601                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5602
5603         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5604                 RTL_R32(tp, CSIDR) : ~0;
5605 }
5606
5607 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5608 {
5609         RTL_W32(tp, CSIDR, value);
5610         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5611                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5612                 CSIAR_FUNC_NIC2);
5613
5614         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5615 }
5616
5617 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5618 {
5619         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5620                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5621
5622         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5623                 RTL_R32(tp, CSIDR) : ~0;
5624 }
5625
5626 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5627 {
5628         struct csi_ops *ops = &tp->csi_ops;
5629
5630         switch (tp->mac_version) {
5631         case RTL_GIGA_MAC_VER_01:
5632         case RTL_GIGA_MAC_VER_02:
5633         case RTL_GIGA_MAC_VER_03:
5634         case RTL_GIGA_MAC_VER_04:
5635         case RTL_GIGA_MAC_VER_05:
5636         case RTL_GIGA_MAC_VER_06:
5637         case RTL_GIGA_MAC_VER_10:
5638         case RTL_GIGA_MAC_VER_11:
5639         case RTL_GIGA_MAC_VER_12:
5640         case RTL_GIGA_MAC_VER_13:
5641         case RTL_GIGA_MAC_VER_14:
5642         case RTL_GIGA_MAC_VER_15:
5643         case RTL_GIGA_MAC_VER_16:
5644         case RTL_GIGA_MAC_VER_17:
5645                 ops->write      = NULL;
5646                 ops->read       = NULL;
5647                 break;
5648
5649         case RTL_GIGA_MAC_VER_37:
5650         case RTL_GIGA_MAC_VER_38:
5651                 ops->write      = r8402_csi_write;
5652                 ops->read       = r8402_csi_read;
5653                 break;
5654
5655         case RTL_GIGA_MAC_VER_44:
5656                 ops->write      = r8411_csi_write;
5657                 ops->read       = r8411_csi_read;
5658                 break;
5659
5660         default:
5661                 ops->write      = r8169_csi_write;
5662                 ops->read       = r8169_csi_read;
5663                 break;
5664         }
5665 }
5666
5667 struct ephy_info {
5668         unsigned int offset;
5669         u16 mask;
5670         u16 bits;
5671 };
5672
5673 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5674                           int len)
5675 {
5676         u16 w;
5677
5678         while (len-- > 0) {
5679                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5680                 rtl_ephy_write(tp, e->offset, w);
5681                 e++;
5682         }
5683 }
5684
5685 static void rtl_disable_clock_request(struct rtl8169_private *tp)
5686 {
5687         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
5688                                    PCI_EXP_LNKCTL_CLKREQ_EN);
5689 }
5690
5691 static void rtl_enable_clock_request(struct rtl8169_private *tp)
5692 {
5693         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
5694                                  PCI_EXP_LNKCTL_CLKREQ_EN);
5695 }
5696
5697 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5698 {
5699         u8 data;
5700
5701         data = RTL_R8(tp, Config3);
5702
5703         if (enable)
5704                 data |= Rdy_to_L23;
5705         else
5706                 data &= ~Rdy_to_L23;
5707
5708         RTL_W8(tp, Config3, data);
5709 }
5710
5711 #define R8168_CPCMD_QUIRK_MASK (\
5712         EnableBist | \
5713         Mac_dbgo_oe | \
5714         Force_half_dup | \
5715         Force_rxflow_en | \
5716         Force_txflow_en | \
5717         Cxpl_dbg_sel | \
5718         ASF | \
5719         PktCntrDisable | \
5720         Mac_dbgo_sel)
5721
5722 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5723 {
5724         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5725
5726         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5727
5728         if (tp->dev->mtu <= ETH_DATA_LEN) {
5729                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
5730                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5731         }
5732 }
5733
5734 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5735 {
5736         rtl_hw_start_8168bb(tp);
5737
5738         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5739
5740         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5741 }
5742
5743 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5744 {
5745         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
5746
5747         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5748
5749         if (tp->dev->mtu <= ETH_DATA_LEN)
5750                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5751
5752         rtl_disable_clock_request(tp);
5753
5754         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5755 }
5756
5757 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5758 {
5759         static const struct ephy_info e_info_8168cp[] = {
5760                 { 0x01, 0,      0x0001 },
5761                 { 0x02, 0x0800, 0x1000 },
5762                 { 0x03, 0,      0x0042 },
5763                 { 0x06, 0x0080, 0x0000 },
5764                 { 0x07, 0,      0x2000 }
5765         };
5766
5767         rtl_csi_access_enable_2(tp);
5768
5769         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5770
5771         __rtl_hw_start_8168cp(tp);
5772 }
5773
5774 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5775 {
5776         rtl_csi_access_enable_2(tp);
5777
5778         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5779
5780         if (tp->dev->mtu <= ETH_DATA_LEN)
5781                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5782
5783         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5784 }
5785
5786 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5787 {
5788         rtl_csi_access_enable_2(tp);
5789
5790         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5791
5792         /* Magic. */
5793         RTL_W8(tp, DBG_REG, 0x20);
5794
5795         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5796
5797         if (tp->dev->mtu <= ETH_DATA_LEN)
5798                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5799
5800         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5801 }
5802
5803 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5804 {
5805         static const struct ephy_info e_info_8168c_1[] = {
5806                 { 0x02, 0x0800, 0x1000 },
5807                 { 0x03, 0,      0x0002 },
5808                 { 0x06, 0x0080, 0x0000 }
5809         };
5810
5811         rtl_csi_access_enable_2(tp);
5812
5813         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5814
5815         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5816
5817         __rtl_hw_start_8168cp(tp);
5818 }
5819
5820 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5821 {
5822         static const struct ephy_info e_info_8168c_2[] = {
5823                 { 0x01, 0,      0x0001 },
5824                 { 0x03, 0x0400, 0x0220 }
5825         };
5826
5827         rtl_csi_access_enable_2(tp);
5828
5829         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5830
5831         __rtl_hw_start_8168cp(tp);
5832 }
5833
5834 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5835 {
5836         rtl_hw_start_8168c_2(tp);
5837 }
5838
5839 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5840 {
5841         rtl_csi_access_enable_2(tp);
5842
5843         __rtl_hw_start_8168cp(tp);
5844 }
5845
5846 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5847 {
5848         rtl_csi_access_enable_2(tp);
5849
5850         rtl_disable_clock_request(tp);
5851
5852         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5853
5854         if (tp->dev->mtu <= ETH_DATA_LEN)
5855                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5856
5857         RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5858 }
5859
5860 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5861 {
5862         rtl_csi_access_enable_1(tp);
5863
5864         if (tp->dev->mtu <= ETH_DATA_LEN)
5865                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5866
5867         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5868
5869         rtl_disable_clock_request(tp);
5870 }
5871
5872 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5873 {
5874         static const struct ephy_info e_info_8168d_4[] = {
5875                 { 0x0b, 0x0000, 0x0048 },
5876                 { 0x19, 0x0020, 0x0050 },
5877                 { 0x0c, 0x0100, 0x0020 }
5878         };
5879
5880         rtl_csi_access_enable_1(tp);
5881
5882         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5883
5884         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5885
5886         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5887
5888         rtl_enable_clock_request(tp);
5889 }
5890
5891 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5892 {
5893         static const struct ephy_info e_info_8168e_1[] = {
5894                 { 0x00, 0x0200, 0x0100 },
5895                 { 0x00, 0x0000, 0x0004 },
5896                 { 0x06, 0x0002, 0x0001 },
5897                 { 0x06, 0x0000, 0x0030 },
5898                 { 0x07, 0x0000, 0x2000 },
5899                 { 0x00, 0x0000, 0x0020 },
5900                 { 0x03, 0x5800, 0x2000 },
5901                 { 0x03, 0x0000, 0x0001 },
5902                 { 0x01, 0x0800, 0x1000 },
5903                 { 0x07, 0x0000, 0x4000 },
5904                 { 0x1e, 0x0000, 0x2000 },
5905                 { 0x19, 0xffff, 0xfe6c },
5906                 { 0x0a, 0x0000, 0x0040 }
5907         };
5908
5909         rtl_csi_access_enable_2(tp);
5910
5911         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5912
5913         if (tp->dev->mtu <= ETH_DATA_LEN)
5914                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5915
5916         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5917
5918         rtl_disable_clock_request(tp);
5919
5920         /* Reset tx FIFO pointer */
5921         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5922         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5923
5924         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5925 }
5926
5927 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5928 {
5929         static const struct ephy_info e_info_8168e_2[] = {
5930                 { 0x09, 0x0000, 0x0080 },
5931                 { 0x19, 0x0000, 0x0224 }
5932         };
5933
5934         rtl_csi_access_enable_1(tp);
5935
5936         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5937
5938         if (tp->dev->mtu <= ETH_DATA_LEN)
5939                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5940
5941         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5942         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5943         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5944         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5945         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5946         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5947         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5948         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5949
5950         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5951
5952         rtl_disable_clock_request(tp);
5953
5954         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5955         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5956
5957         /* Adjust EEE LED frequency */
5958         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5959
5960         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5961         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5962         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5963 }
5964
5965 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5966 {
5967         rtl_csi_access_enable_2(tp);
5968
5969         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5970
5971         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5972         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5973         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5974         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5975         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5976         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5977         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5978         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5979         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5980         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5981
5982         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5983
5984         rtl_disable_clock_request(tp);
5985
5986         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5987         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5988         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5989         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5990         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5991 }
5992
5993 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5994 {
5995         static const struct ephy_info e_info_8168f_1[] = {
5996                 { 0x06, 0x00c0, 0x0020 },
5997                 { 0x08, 0x0001, 0x0002 },
5998                 { 0x09, 0x0000, 0x0080 },
5999                 { 0x19, 0x0000, 0x0224 }
6000         };
6001
6002         rtl_hw_start_8168f(tp);
6003
6004         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6005
6006         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6007
6008         /* Adjust EEE LED frequency */
6009         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6010 }
6011
6012 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6013 {
6014         static const struct ephy_info e_info_8168f_1[] = {
6015                 { 0x06, 0x00c0, 0x0020 },
6016                 { 0x0f, 0xffff, 0x5200 },
6017                 { 0x1e, 0x0000, 0x4000 },
6018                 { 0x19, 0x0000, 0x0224 }
6019         };
6020
6021         rtl_hw_start_8168f(tp);
6022         rtl_pcie_state_l2l3_enable(tp, false);
6023
6024         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6025
6026         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6027 }
6028
6029 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6030 {
6031         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6032
6033         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6034         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6035         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6036         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6037
6038         rtl_csi_access_enable_1(tp);
6039
6040         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6041
6042         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6043         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6044         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6045
6046         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6047         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6048
6049         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6050         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6051
6052         /* Adjust EEE LED frequency */
6053         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6054
6055         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6056         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6057
6058         rtl_pcie_state_l2l3_enable(tp, false);
6059 }
6060
6061 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6062 {
6063         static const struct ephy_info e_info_8168g_1[] = {
6064                 { 0x00, 0x0000, 0x0008 },
6065                 { 0x0c, 0x37d0, 0x0820 },
6066                 { 0x1e, 0x0000, 0x0001 },
6067                 { 0x19, 0x8000, 0x0000 }
6068         };
6069
6070         rtl_hw_start_8168g(tp);
6071
6072         /* disable aspm and clock request before access ephy */
6073         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6074         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6075         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6076 }
6077
6078 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6079 {
6080         static const struct ephy_info e_info_8168g_2[] = {
6081                 { 0x00, 0x0000, 0x0008 },
6082                 { 0x0c, 0x3df0, 0x0200 },
6083                 { 0x19, 0xffff, 0xfc00 },
6084                 { 0x1e, 0xffff, 0x20eb }
6085         };
6086
6087         rtl_hw_start_8168g(tp);
6088
6089         /* disable aspm and clock request before access ephy */
6090         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6091         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6092         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6093 }
6094
6095 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6096 {
6097         static const struct ephy_info e_info_8411_2[] = {
6098                 { 0x00, 0x0000, 0x0008 },
6099                 { 0x0c, 0x3df0, 0x0200 },
6100                 { 0x0f, 0xffff, 0x5200 },
6101                 { 0x19, 0x0020, 0x0000 },
6102                 { 0x1e, 0x0000, 0x2000 }
6103         };
6104
6105         rtl_hw_start_8168g(tp);
6106
6107         /* disable aspm and clock request before access ephy */
6108         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6109         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6110         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6111 }
6112
6113 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6114 {
6115         int rg_saw_cnt;
6116         u32 data;
6117         static const struct ephy_info e_info_8168h_1[] = {
6118                 { 0x1e, 0x0800, 0x0001 },
6119                 { 0x1d, 0x0000, 0x0800 },
6120                 { 0x05, 0xffff, 0x2089 },
6121                 { 0x06, 0xffff, 0x5881 },
6122                 { 0x04, 0xffff, 0x154a },
6123                 { 0x01, 0xffff, 0x068b }
6124         };
6125
6126         /* disable aspm and clock request before access ephy */
6127         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6128         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6129         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6130
6131         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6132
6133         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6134         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6135         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6136         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6137
6138         rtl_csi_access_enable_1(tp);
6139
6140         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6141
6142         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6143         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6144
6145         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6146
6147         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6148
6149         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6150
6151         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6152         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6153
6154         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6155         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6156
6157         /* Adjust EEE LED frequency */
6158         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6159
6160         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6161         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6162
6163         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6164
6165         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6166
6167         rtl_pcie_state_l2l3_enable(tp, false);
6168
6169         rtl_writephy(tp, 0x1f, 0x0c42);
6170         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6171         rtl_writephy(tp, 0x1f, 0x0000);
6172         if (rg_saw_cnt > 0) {
6173                 u16 sw_cnt_1ms_ini;
6174
6175                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6176                 sw_cnt_1ms_ini &= 0x0fff;
6177                 data = r8168_mac_ocp_read(tp, 0xd412);
6178                 data &= ~0x0fff;
6179                 data |= sw_cnt_1ms_ini;
6180                 r8168_mac_ocp_write(tp, 0xd412, data);
6181         }
6182
6183         data = r8168_mac_ocp_read(tp, 0xe056);
6184         data &= ~0xf0;
6185         data |= 0x70;
6186         r8168_mac_ocp_write(tp, 0xe056, data);
6187
6188         data = r8168_mac_ocp_read(tp, 0xe052);
6189         data &= ~0x6000;
6190         data |= 0x8008;
6191         r8168_mac_ocp_write(tp, 0xe052, data);
6192
6193         data = r8168_mac_ocp_read(tp, 0xe0d6);
6194         data &= ~0x01ff;
6195         data |= 0x017f;
6196         r8168_mac_ocp_write(tp, 0xe0d6, data);
6197
6198         data = r8168_mac_ocp_read(tp, 0xd420);
6199         data &= ~0x0fff;
6200         data |= 0x047f;
6201         r8168_mac_ocp_write(tp, 0xd420, data);
6202
6203         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6204         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6205         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6206         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6207 }
6208
6209 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6210 {
6211         rtl8168ep_stop_cmac(tp);
6212
6213         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6214
6215         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6216         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6217         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6218         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6219
6220         rtl_csi_access_enable_1(tp);
6221
6222         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6223
6224         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6225         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6226
6227         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6228
6229         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6230
6231         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
6232         RTL_W8(tp, MaxTxPacketSize, EarlySize);
6233
6234         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6235         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6236
6237         /* Adjust EEE LED frequency */
6238         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6239
6240         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6241
6242         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6243
6244         rtl_pcie_state_l2l3_enable(tp, false);
6245 }
6246
6247 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6248 {
6249         static const struct ephy_info e_info_8168ep_1[] = {
6250                 { 0x00, 0xffff, 0x10ab },
6251                 { 0x06, 0xffff, 0xf030 },
6252                 { 0x08, 0xffff, 0x2006 },
6253                 { 0x0d, 0xffff, 0x1666 },
6254                 { 0x0c, 0x3ff0, 0x0000 }
6255         };
6256
6257         /* disable aspm and clock request before access ephy */
6258         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6259         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6260         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6261
6262         rtl_hw_start_8168ep(tp);
6263 }
6264
6265 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6266 {
6267         static const struct ephy_info e_info_8168ep_2[] = {
6268                 { 0x00, 0xffff, 0x10a3 },
6269                 { 0x19, 0xffff, 0xfc00 },
6270                 { 0x1e, 0xffff, 0x20ea }
6271         };
6272
6273         /* disable aspm and clock request before access ephy */
6274         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6275         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6276         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6277
6278         rtl_hw_start_8168ep(tp);
6279
6280         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6281         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6282 }
6283
6284 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6285 {
6286         u32 data;
6287         static const struct ephy_info e_info_8168ep_3[] = {
6288                 { 0x00, 0xffff, 0x10a3 },
6289                 { 0x19, 0xffff, 0x7c00 },
6290                 { 0x1e, 0xffff, 0x20eb },
6291                 { 0x0d, 0xffff, 0x1666 }
6292         };
6293
6294         /* disable aspm and clock request before access ephy */
6295         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
6296         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
6297         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6298
6299         rtl_hw_start_8168ep(tp);
6300
6301         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6302         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6303
6304         data = r8168_mac_ocp_read(tp, 0xd3e2);
6305         data &= 0xf000;
6306         data |= 0x0271;
6307         r8168_mac_ocp_write(tp, 0xd3e2, data);
6308
6309         data = r8168_mac_ocp_read(tp, 0xd3e4);
6310         data &= 0xff00;
6311         r8168_mac_ocp_write(tp, 0xd3e4, data);
6312
6313         data = r8168_mac_ocp_read(tp, 0xe860);
6314         data |= 0x0080;
6315         r8168_mac_ocp_write(tp, 0xe860, data);
6316 }
6317
6318 static void rtl_hw_start_8168(struct rtl8169_private *tp)
6319 {
6320         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6321
6322         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
6323
6324         rtl_set_rx_max_size(tp);
6325
6326         tp->cp_cmd |= RTL_R16(tp, CPlusCmd) | PktCntrDisable | INTT_1;
6327
6328         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6329
6330         RTL_W16(tp, IntrMitigate, 0x5151);
6331
6332         /* Work around for RxFIFO overflow. */
6333         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6334                 tp->event_slow |= RxFIFOOver | PCSTimeout;
6335                 tp->event_slow &= ~RxOverflow;
6336         }
6337
6338         rtl_set_rx_tx_desc_registers(tp);
6339
6340         rtl_set_rx_tx_config_registers(tp);
6341
6342         RTL_R8(tp, IntrMask);
6343
6344         switch (tp->mac_version) {
6345         case RTL_GIGA_MAC_VER_11:
6346                 rtl_hw_start_8168bb(tp);
6347                 break;
6348
6349         case RTL_GIGA_MAC_VER_12:
6350         case RTL_GIGA_MAC_VER_17:
6351                 rtl_hw_start_8168bef(tp);
6352                 break;
6353
6354         case RTL_GIGA_MAC_VER_18:
6355                 rtl_hw_start_8168cp_1(tp);
6356                 break;
6357
6358         case RTL_GIGA_MAC_VER_19:
6359                 rtl_hw_start_8168c_1(tp);
6360                 break;
6361
6362         case RTL_GIGA_MAC_VER_20:
6363                 rtl_hw_start_8168c_2(tp);
6364                 break;
6365
6366         case RTL_GIGA_MAC_VER_21:
6367                 rtl_hw_start_8168c_3(tp);
6368                 break;
6369
6370         case RTL_GIGA_MAC_VER_22:
6371                 rtl_hw_start_8168c_4(tp);
6372                 break;
6373
6374         case RTL_GIGA_MAC_VER_23:
6375                 rtl_hw_start_8168cp_2(tp);
6376                 break;
6377
6378         case RTL_GIGA_MAC_VER_24:
6379                 rtl_hw_start_8168cp_3(tp);
6380                 break;
6381
6382         case RTL_GIGA_MAC_VER_25:
6383         case RTL_GIGA_MAC_VER_26:
6384         case RTL_GIGA_MAC_VER_27:
6385                 rtl_hw_start_8168d(tp);
6386                 break;
6387
6388         case RTL_GIGA_MAC_VER_28:
6389                 rtl_hw_start_8168d_4(tp);
6390                 break;
6391
6392         case RTL_GIGA_MAC_VER_31:
6393                 rtl_hw_start_8168dp(tp);
6394                 break;
6395
6396         case RTL_GIGA_MAC_VER_32:
6397         case RTL_GIGA_MAC_VER_33:
6398                 rtl_hw_start_8168e_1(tp);
6399                 break;
6400         case RTL_GIGA_MAC_VER_34:
6401                 rtl_hw_start_8168e_2(tp);
6402                 break;
6403
6404         case RTL_GIGA_MAC_VER_35:
6405         case RTL_GIGA_MAC_VER_36:
6406                 rtl_hw_start_8168f_1(tp);
6407                 break;
6408
6409         case RTL_GIGA_MAC_VER_38:
6410                 rtl_hw_start_8411(tp);
6411                 break;
6412
6413         case RTL_GIGA_MAC_VER_40:
6414         case RTL_GIGA_MAC_VER_41:
6415                 rtl_hw_start_8168g_1(tp);
6416                 break;
6417         case RTL_GIGA_MAC_VER_42:
6418                 rtl_hw_start_8168g_2(tp);
6419                 break;
6420
6421         case RTL_GIGA_MAC_VER_44:
6422                 rtl_hw_start_8411_2(tp);
6423                 break;
6424
6425         case RTL_GIGA_MAC_VER_45:
6426         case RTL_GIGA_MAC_VER_46:
6427                 rtl_hw_start_8168h_1(tp);
6428                 break;
6429
6430         case RTL_GIGA_MAC_VER_49:
6431                 rtl_hw_start_8168ep_1(tp);
6432                 break;
6433
6434         case RTL_GIGA_MAC_VER_50:
6435                 rtl_hw_start_8168ep_2(tp);
6436                 break;
6437
6438         case RTL_GIGA_MAC_VER_51:
6439                 rtl_hw_start_8168ep_3(tp);
6440                 break;
6441
6442         default:
6443                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6444                        tp->dev->name, tp->mac_version);
6445                 break;
6446         }
6447
6448         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6449
6450         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
6451
6452         rtl_set_rx_mode(tp->dev);
6453
6454         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
6455 }
6456
6457 #define R810X_CPCMD_QUIRK_MASK (\
6458         EnableBist | \
6459         Mac_dbgo_oe | \
6460         Force_half_dup | \
6461         Force_rxflow_en | \
6462         Force_txflow_en | \
6463         Cxpl_dbg_sel | \
6464         ASF | \
6465         PktCntrDisable | \
6466         Mac_dbgo_sel)
6467
6468 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6469 {
6470         static const struct ephy_info e_info_8102e_1[] = {
6471                 { 0x01, 0, 0x6e65 },
6472                 { 0x02, 0, 0x091f },
6473                 { 0x03, 0, 0xc2f9 },
6474                 { 0x06, 0, 0xafb5 },
6475                 { 0x07, 0, 0x0e00 },
6476                 { 0x19, 0, 0xec80 },
6477                 { 0x01, 0, 0x2e65 },
6478                 { 0x01, 0, 0x6e65 }
6479         };
6480         u8 cfg1;
6481
6482         rtl_csi_access_enable_2(tp);
6483
6484         RTL_W8(tp, DBG_REG, FIX_NAK_1);
6485
6486         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6487
6488         RTL_W8(tp, Config1,
6489                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6490         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6491
6492         cfg1 = RTL_R8(tp, Config1);
6493         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6494                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
6495
6496         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6497 }
6498
6499 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6500 {
6501         rtl_csi_access_enable_2(tp);
6502
6503         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6504
6505         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
6506         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
6507 }
6508
6509 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6510 {
6511         rtl_hw_start_8102e_2(tp);
6512
6513         rtl_ephy_write(tp, 0x03, 0xc2f9);
6514 }
6515
6516 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6517 {
6518         static const struct ephy_info e_info_8105e_1[] = {
6519                 { 0x07, 0, 0x4000 },
6520                 { 0x19, 0, 0x0200 },
6521                 { 0x19, 0, 0x0020 },
6522                 { 0x1e, 0, 0x2000 },
6523                 { 0x03, 0, 0x0001 },
6524                 { 0x19, 0, 0x0100 },
6525                 { 0x19, 0, 0x0004 },
6526                 { 0x0a, 0, 0x0020 }
6527         };
6528
6529         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6530         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6531
6532         /* Disable Early Tally Counter */
6533         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
6534
6535         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6536         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
6537
6538         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6539
6540         rtl_pcie_state_l2l3_enable(tp, false);
6541 }
6542
6543 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6544 {
6545         rtl_hw_start_8105e_1(tp);
6546         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6547 }
6548
6549 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6550 {
6551         static const struct ephy_info e_info_8402[] = {
6552                 { 0x19, 0xffff, 0xff64 },
6553                 { 0x1e, 0, 0x4000 }
6554         };
6555
6556         rtl_csi_access_enable_2(tp);
6557
6558         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6559         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6560
6561         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
6562         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6563
6564         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6565
6566         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6567
6568         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6569         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6570         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6571         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6572         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6573         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6574         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6575
6576         rtl_pcie_state_l2l3_enable(tp, false);
6577 }
6578
6579 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6580 {
6581         /* Force LAN exit from ASPM if Rx/Tx are not idle */
6582         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
6583
6584         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6585         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
6586         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
6587
6588         rtl_pcie_state_l2l3_enable(tp, false);
6589 }
6590
6591 static void rtl_hw_start_8101(struct rtl8169_private *tp)
6592 {
6593         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6594                 tp->event_slow &= ~RxFIFOOver;
6595
6596         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6597             tp->mac_version == RTL_GIGA_MAC_VER_16)
6598                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
6599                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
6600
6601         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
6602
6603         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
6604
6605         rtl_set_rx_max_size(tp);
6606
6607         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6608         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6609
6610         rtl_set_rx_tx_desc_registers(tp);
6611
6612         rtl_set_rx_tx_config_registers(tp);
6613
6614         switch (tp->mac_version) {
6615         case RTL_GIGA_MAC_VER_07:
6616                 rtl_hw_start_8102e_1(tp);
6617                 break;
6618
6619         case RTL_GIGA_MAC_VER_08:
6620                 rtl_hw_start_8102e_3(tp);
6621                 break;
6622
6623         case RTL_GIGA_MAC_VER_09:
6624                 rtl_hw_start_8102e_2(tp);
6625                 break;
6626
6627         case RTL_GIGA_MAC_VER_29:
6628                 rtl_hw_start_8105e_1(tp);
6629                 break;
6630         case RTL_GIGA_MAC_VER_30:
6631                 rtl_hw_start_8105e_2(tp);
6632                 break;
6633
6634         case RTL_GIGA_MAC_VER_37:
6635                 rtl_hw_start_8402(tp);
6636                 break;
6637
6638         case RTL_GIGA_MAC_VER_39:
6639                 rtl_hw_start_8106(tp);
6640                 break;
6641         case RTL_GIGA_MAC_VER_43:
6642                 rtl_hw_start_8168g_2(tp);
6643                 break;
6644         case RTL_GIGA_MAC_VER_47:
6645         case RTL_GIGA_MAC_VER_48:
6646                 rtl_hw_start_8168h_1(tp);
6647                 break;
6648         }
6649
6650         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6651
6652         RTL_W16(tp, IntrMitigate, 0x0000);
6653
6654         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
6655
6656         rtl_set_rx_mode(tp->dev);
6657
6658         RTL_R8(tp, IntrMask);
6659
6660         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
6661 }
6662
6663 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6664 {
6665         struct rtl8169_private *tp = netdev_priv(dev);
6666
6667         if (new_mtu > ETH_DATA_LEN)
6668                 rtl_hw_jumbo_enable(tp);
6669         else
6670                 rtl_hw_jumbo_disable(tp);
6671
6672         dev->mtu = new_mtu;
6673         netdev_update_features(dev);
6674
6675         return 0;
6676 }
6677
6678 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6679 {
6680         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6681         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6682 }
6683
6684 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6685                                      void **data_buff, struct RxDesc *desc)
6686 {
6687         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
6688                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
6689
6690         kfree(*data_buff);
6691         *data_buff = NULL;
6692         rtl8169_make_unusable_by_asic(desc);
6693 }
6694
6695 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
6696 {
6697         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6698
6699         /* Force memory writes to complete before releasing descriptor */
6700         dma_wmb();
6701
6702         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
6703 }
6704
6705 static inline void *rtl8169_align(void *data)
6706 {
6707         return (void *)ALIGN((long)data, 16);
6708 }
6709
6710 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6711                                              struct RxDesc *desc)
6712 {
6713         void *data;
6714         dma_addr_t mapping;
6715         struct device *d = tp_to_dev(tp);
6716         int node = dev_to_node(d);
6717
6718         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6719         if (!data)
6720                 return NULL;
6721
6722         if (rtl8169_align(data) != data) {
6723                 kfree(data);
6724                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6725                 if (!data)
6726                         return NULL;
6727         }
6728
6729         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
6730                                  DMA_FROM_DEVICE);
6731         if (unlikely(dma_mapping_error(d, mapping))) {
6732                 if (net_ratelimit())
6733                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6734                 goto err_out;
6735         }
6736
6737         desc->addr = cpu_to_le64(mapping);
6738         rtl8169_mark_to_asic(desc);
6739         return data;
6740
6741 err_out:
6742         kfree(data);
6743         return NULL;
6744 }
6745
6746 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6747 {
6748         unsigned int i;
6749
6750         for (i = 0; i < NUM_RX_DESC; i++) {
6751                 if (tp->Rx_databuff[i]) {
6752                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6753                                             tp->RxDescArray + i);
6754                 }
6755         }
6756 }
6757
6758 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6759 {
6760         desc->opts1 |= cpu_to_le32(RingEnd);
6761 }
6762
6763 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6764 {
6765         unsigned int i;
6766
6767         for (i = 0; i < NUM_RX_DESC; i++) {
6768                 void *data;
6769
6770                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6771                 if (!data) {
6772                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6773                         goto err_out;
6774                 }
6775                 tp->Rx_databuff[i] = data;
6776         }
6777
6778         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6779         return 0;
6780
6781 err_out:
6782         rtl8169_rx_clear(tp);
6783         return -ENOMEM;
6784 }
6785
6786 static int rtl8169_init_ring(struct rtl8169_private *tp)
6787 {
6788         rtl8169_init_ring_indexes(tp);
6789
6790         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6791         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
6792
6793         return rtl8169_rx_fill(tp);
6794 }
6795
6796 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6797                                  struct TxDesc *desc)
6798 {
6799         unsigned int len = tx_skb->len;
6800
6801         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6802
6803         desc->opts1 = 0x00;
6804         desc->opts2 = 0x00;
6805         desc->addr = 0x00;
6806         tx_skb->len = 0;
6807 }
6808
6809 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6810                                    unsigned int n)
6811 {
6812         unsigned int i;
6813
6814         for (i = 0; i < n; i++) {
6815                 unsigned int entry = (start + i) % NUM_TX_DESC;
6816                 struct ring_info *tx_skb = tp->tx_skb + entry;
6817                 unsigned int len = tx_skb->len;
6818
6819                 if (len) {
6820                         struct sk_buff *skb = tx_skb->skb;
6821
6822                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6823                                              tp->TxDescArray + entry);
6824                         if (skb) {
6825                                 dev_consume_skb_any(skb);
6826                                 tx_skb->skb = NULL;
6827                         }
6828                 }
6829         }
6830 }
6831
6832 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6833 {
6834         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6835         tp->cur_tx = tp->dirty_tx = 0;
6836 }
6837
6838 static void rtl_reset_work(struct rtl8169_private *tp)
6839 {
6840         struct net_device *dev = tp->dev;
6841         int i;
6842
6843         napi_disable(&tp->napi);
6844         netif_stop_queue(dev);
6845         synchronize_sched();
6846
6847         rtl8169_hw_reset(tp);
6848
6849         for (i = 0; i < NUM_RX_DESC; i++)
6850                 rtl8169_mark_to_asic(tp->RxDescArray + i);
6851
6852         rtl8169_tx_clear(tp);
6853         rtl8169_init_ring_indexes(tp);
6854
6855         napi_enable(&tp->napi);
6856         rtl_hw_start(tp);
6857         netif_wake_queue(dev);
6858         rtl8169_check_link_status(dev, tp);
6859 }
6860
6861 static void rtl8169_tx_timeout(struct net_device *dev)
6862 {
6863         struct rtl8169_private *tp = netdev_priv(dev);
6864
6865         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6866 }
6867
6868 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6869                               u32 *opts)
6870 {
6871         struct skb_shared_info *info = skb_shinfo(skb);
6872         unsigned int cur_frag, entry;
6873         struct TxDesc *uninitialized_var(txd);
6874         struct device *d = tp_to_dev(tp);
6875
6876         entry = tp->cur_tx;
6877         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6878                 const skb_frag_t *frag = info->frags + cur_frag;
6879                 dma_addr_t mapping;
6880                 u32 status, len;
6881                 void *addr;
6882
6883                 entry = (entry + 1) % NUM_TX_DESC;
6884
6885                 txd = tp->TxDescArray + entry;
6886                 len = skb_frag_size(frag);
6887                 addr = skb_frag_address(frag);
6888                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6889                 if (unlikely(dma_mapping_error(d, mapping))) {
6890                         if (net_ratelimit())
6891                                 netif_err(tp, drv, tp->dev,
6892                                           "Failed to map TX fragments DMA!\n");
6893                         goto err_out;
6894                 }
6895
6896                 /* Anti gcc 2.95.3 bugware (sic) */
6897                 status = opts[0] | len |
6898                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6899
6900                 txd->opts1 = cpu_to_le32(status);
6901                 txd->opts2 = cpu_to_le32(opts[1]);
6902                 txd->addr = cpu_to_le64(mapping);
6903
6904                 tp->tx_skb[entry].len = len;
6905         }
6906
6907         if (cur_frag) {
6908                 tp->tx_skb[entry].skb = skb;
6909                 txd->opts1 |= cpu_to_le32(LastFrag);
6910         }
6911
6912         return cur_frag;
6913
6914 err_out:
6915         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6916         return -EIO;
6917 }
6918
6919 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6920 {
6921         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6922 }
6923
6924 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6925                                       struct net_device *dev);
6926 /* r8169_csum_workaround()
6927  * The hw limites the value the transport offset. When the offset is out of the
6928  * range, calculate the checksum by sw.
6929  */
6930 static void r8169_csum_workaround(struct rtl8169_private *tp,
6931                                   struct sk_buff *skb)
6932 {
6933         if (skb_shinfo(skb)->gso_size) {
6934                 netdev_features_t features = tp->dev->features;
6935                 struct sk_buff *segs, *nskb;
6936
6937                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6938                 segs = skb_gso_segment(skb, features);
6939                 if (IS_ERR(segs) || !segs)
6940                         goto drop;
6941
6942                 do {
6943                         nskb = segs;
6944                         segs = segs->next;
6945                         nskb->next = NULL;
6946                         rtl8169_start_xmit(nskb, tp->dev);
6947                 } while (segs);
6948
6949                 dev_consume_skb_any(skb);
6950         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6951                 if (skb_checksum_help(skb) < 0)
6952                         goto drop;
6953
6954                 rtl8169_start_xmit(skb, tp->dev);
6955         } else {
6956                 struct net_device_stats *stats;
6957
6958 drop:
6959                 stats = &tp->dev->stats;
6960                 stats->tx_dropped++;
6961                 dev_kfree_skb_any(skb);
6962         }
6963 }
6964
6965 /* msdn_giant_send_check()
6966  * According to the document of microsoft, the TCP Pseudo Header excludes the
6967  * packet length for IPv6 TCP large packets.
6968  */
6969 static int msdn_giant_send_check(struct sk_buff *skb)
6970 {
6971         const struct ipv6hdr *ipv6h;
6972         struct tcphdr *th;
6973         int ret;
6974
6975         ret = skb_cow_head(skb, 0);
6976         if (ret)
6977                 return ret;
6978
6979         ipv6h = ipv6_hdr(skb);
6980         th = tcp_hdr(skb);
6981
6982         th->check = 0;
6983         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6984
6985         return ret;
6986 }
6987
6988 static inline __be16 get_protocol(struct sk_buff *skb)
6989 {
6990         __be16 protocol;
6991
6992         if (skb->protocol == htons(ETH_P_8021Q))
6993                 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6994         else
6995                 protocol = skb->protocol;
6996
6997         return protocol;
6998 }
6999
7000 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7001                                 struct sk_buff *skb, u32 *opts)
7002 {
7003         u32 mss = skb_shinfo(skb)->gso_size;
7004
7005         if (mss) {
7006                 opts[0] |= TD_LSO;
7007                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7008         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7009                 const struct iphdr *ip = ip_hdr(skb);
7010
7011                 if (ip->protocol == IPPROTO_TCP)
7012                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7013                 else if (ip->protocol == IPPROTO_UDP)
7014                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7015                 else
7016                         WARN_ON_ONCE(1);
7017         }
7018
7019         return true;
7020 }
7021
7022 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7023                                 struct sk_buff *skb, u32 *opts)
7024 {
7025         u32 transport_offset = (u32)skb_transport_offset(skb);
7026         u32 mss = skb_shinfo(skb)->gso_size;
7027
7028         if (mss) {
7029                 if (transport_offset > GTTCPHO_MAX) {
7030                         netif_warn(tp, tx_err, tp->dev,
7031                                    "Invalid transport offset 0x%x for TSO\n",
7032                                    transport_offset);
7033                         return false;
7034                 }
7035
7036                 switch (get_protocol(skb)) {
7037                 case htons(ETH_P_IP):
7038                         opts[0] |= TD1_GTSENV4;
7039                         break;
7040
7041                 case htons(ETH_P_IPV6):
7042                         if (msdn_giant_send_check(skb))
7043                                 return false;
7044
7045                         opts[0] |= TD1_GTSENV6;
7046                         break;
7047
7048                 default:
7049                         WARN_ON_ONCE(1);
7050                         break;
7051                 }
7052
7053                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7054                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7055         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7056                 u8 ip_protocol;
7057
7058                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7059                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7060
7061                 if (transport_offset > TCPHO_MAX) {
7062                         netif_warn(tp, tx_err, tp->dev,
7063                                    "Invalid transport offset 0x%x\n",
7064                                    transport_offset);
7065                         return false;
7066                 }
7067
7068                 switch (get_protocol(skb)) {
7069                 case htons(ETH_P_IP):
7070                         opts[1] |= TD1_IPv4_CS;
7071                         ip_protocol = ip_hdr(skb)->protocol;
7072                         break;
7073
7074                 case htons(ETH_P_IPV6):
7075                         opts[1] |= TD1_IPv6_CS;
7076                         ip_protocol = ipv6_hdr(skb)->nexthdr;
7077                         break;
7078
7079                 default:
7080                         ip_protocol = IPPROTO_RAW;
7081                         break;
7082                 }
7083
7084                 if (ip_protocol == IPPROTO_TCP)
7085                         opts[1] |= TD1_TCP_CS;
7086                 else if (ip_protocol == IPPROTO_UDP)
7087                         opts[1] |= TD1_UDP_CS;
7088                 else
7089                         WARN_ON_ONCE(1);
7090
7091                 opts[1] |= transport_offset << TCPHO_SHIFT;
7092         } else {
7093                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7094                         return !eth_skb_pad(skb);
7095         }
7096
7097         return true;
7098 }
7099
7100 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7101                                       struct net_device *dev)
7102 {
7103         struct rtl8169_private *tp = netdev_priv(dev);
7104         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7105         struct TxDesc *txd = tp->TxDescArray + entry;
7106         struct device *d = tp_to_dev(tp);
7107         dma_addr_t mapping;
7108         u32 status, len;
7109         u32 opts[2];
7110         int frags;
7111
7112         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7113                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7114                 goto err_stop_0;
7115         }
7116
7117         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7118                 goto err_stop_0;
7119
7120         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7121         opts[0] = DescOwn;
7122
7123         if (!tp->tso_csum(tp, skb, opts)) {
7124                 r8169_csum_workaround(tp, skb);
7125                 return NETDEV_TX_OK;
7126         }
7127
7128         len = skb_headlen(skb);
7129         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7130         if (unlikely(dma_mapping_error(d, mapping))) {
7131                 if (net_ratelimit())
7132                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7133                 goto err_dma_0;
7134         }
7135
7136         tp->tx_skb[entry].len = len;
7137         txd->addr = cpu_to_le64(mapping);
7138
7139         frags = rtl8169_xmit_frags(tp, skb, opts);
7140         if (frags < 0)
7141                 goto err_dma_1;
7142         else if (frags)
7143                 opts[0] |= FirstFrag;
7144         else {
7145                 opts[0] |= FirstFrag | LastFrag;
7146                 tp->tx_skb[entry].skb = skb;
7147         }
7148
7149         txd->opts2 = cpu_to_le32(opts[1]);
7150
7151         skb_tx_timestamp(skb);
7152
7153         /* Force memory writes to complete before releasing descriptor */
7154         dma_wmb();
7155
7156         /* Anti gcc 2.95.3 bugware (sic) */
7157         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7158         txd->opts1 = cpu_to_le32(status);
7159
7160         /* Force all memory writes to complete before notifying device */
7161         wmb();
7162
7163         tp->cur_tx += frags + 1;
7164
7165         RTL_W8(tp, TxPoll, NPQ);
7166
7167         mmiowb();
7168
7169         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7170                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7171                  * not miss a ring update when it notices a stopped queue.
7172                  */
7173                 smp_wmb();
7174                 netif_stop_queue(dev);
7175                 /* Sync with rtl_tx:
7176                  * - publish queue status and cur_tx ring index (write barrier)
7177                  * - refresh dirty_tx ring index (read barrier).
7178                  * May the current thread have a pessimistic view of the ring
7179                  * status and forget to wake up queue, a racing rtl_tx thread
7180                  * can't.
7181                  */
7182                 smp_mb();
7183                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7184                         netif_wake_queue(dev);
7185         }
7186
7187         return NETDEV_TX_OK;
7188
7189 err_dma_1:
7190         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7191 err_dma_0:
7192         dev_kfree_skb_any(skb);
7193         dev->stats.tx_dropped++;
7194         return NETDEV_TX_OK;
7195
7196 err_stop_0:
7197         netif_stop_queue(dev);
7198         dev->stats.tx_dropped++;
7199         return NETDEV_TX_BUSY;
7200 }
7201
7202 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7203 {
7204         struct rtl8169_private *tp = netdev_priv(dev);
7205         struct pci_dev *pdev = tp->pci_dev;
7206         u16 pci_status, pci_cmd;
7207
7208         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7209         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7210
7211         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7212                   pci_cmd, pci_status);
7213
7214         /*
7215          * The recovery sequence below admits a very elaborated explanation:
7216          * - it seems to work;
7217          * - I did not see what else could be done;
7218          * - it makes iop3xx happy.
7219          *
7220          * Feel free to adjust to your needs.
7221          */
7222         if (pdev->broken_parity_status)
7223                 pci_cmd &= ~PCI_COMMAND_PARITY;
7224         else
7225                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7226
7227         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7228
7229         pci_write_config_word(pdev, PCI_STATUS,
7230                 pci_status & (PCI_STATUS_DETECTED_PARITY |
7231                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7232                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7233
7234         /* The infamous DAC f*ckup only happens at boot time */
7235         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7236                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7237                 tp->cp_cmd &= ~PCIDAC;
7238                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7239                 dev->features &= ~NETIF_F_HIGHDMA;
7240         }
7241
7242         rtl8169_hw_reset(tp);
7243
7244         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7245 }
7246
7247 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7248 {
7249         unsigned int dirty_tx, tx_left;
7250
7251         dirty_tx = tp->dirty_tx;
7252         smp_rmb();
7253         tx_left = tp->cur_tx - dirty_tx;
7254
7255         while (tx_left > 0) {
7256                 unsigned int entry = dirty_tx % NUM_TX_DESC;
7257                 struct ring_info *tx_skb = tp->tx_skb + entry;
7258                 u32 status;
7259
7260                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7261                 if (status & DescOwn)
7262                         break;
7263
7264                 /* This barrier is needed to keep us from reading
7265                  * any other fields out of the Tx descriptor until
7266                  * we know the status of DescOwn
7267                  */
7268                 dma_rmb();
7269
7270                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
7271                                      tp->TxDescArray + entry);
7272                 if (status & LastFrag) {
7273                         u64_stats_update_begin(&tp->tx_stats.syncp);
7274                         tp->tx_stats.packets++;
7275                         tp->tx_stats.bytes += tx_skb->skb->len;
7276                         u64_stats_update_end(&tp->tx_stats.syncp);
7277                         dev_consume_skb_any(tx_skb->skb);
7278                         tx_skb->skb = NULL;
7279                 }
7280                 dirty_tx++;
7281                 tx_left--;
7282         }
7283
7284         if (tp->dirty_tx != dirty_tx) {
7285                 tp->dirty_tx = dirty_tx;
7286                 /* Sync with rtl8169_start_xmit:
7287                  * - publish dirty_tx ring index (write barrier)
7288                  * - refresh cur_tx ring index and queue status (read barrier)
7289                  * May the current thread miss the stopped queue condition,
7290                  * a racing xmit thread can only have a right view of the
7291                  * ring status.
7292                  */
7293                 smp_mb();
7294                 if (netif_queue_stopped(dev) &&
7295                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7296                         netif_wake_queue(dev);
7297                 }
7298                 /*
7299                  * 8168 hack: TxPoll requests are lost when the Tx packets are
7300                  * too close. Let's kick an extra TxPoll request when a burst
7301                  * of start_xmit activity is detected (if it is not detected,
7302                  * it is slow enough). -- FR
7303                  */
7304                 if (tp->cur_tx != dirty_tx)
7305                         RTL_W8(tp, TxPoll, NPQ);
7306         }
7307 }
7308
7309 static inline int rtl8169_fragmented_frame(u32 status)
7310 {
7311         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7312 }
7313
7314 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7315 {
7316         u32 status = opts1 & RxProtoMask;
7317
7318         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7319             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7320                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7321         else
7322                 skb_checksum_none_assert(skb);
7323 }
7324
7325 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7326                                            struct rtl8169_private *tp,
7327                                            int pkt_size,
7328                                            dma_addr_t addr)
7329 {
7330         struct sk_buff *skb;
7331         struct device *d = tp_to_dev(tp);
7332
7333         data = rtl8169_align(data);
7334         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7335         prefetch(data);
7336         skb = napi_alloc_skb(&tp->napi, pkt_size);
7337         if (skb)
7338                 skb_copy_to_linear_data(skb, data, pkt_size);
7339         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7340
7341         return skb;
7342 }
7343
7344 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7345 {
7346         unsigned int cur_rx, rx_left;
7347         unsigned int count;
7348
7349         cur_rx = tp->cur_rx;
7350
7351         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7352                 unsigned int entry = cur_rx % NUM_RX_DESC;
7353                 struct RxDesc *desc = tp->RxDescArray + entry;
7354                 u32 status;
7355
7356                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7357                 if (status & DescOwn)
7358                         break;
7359
7360                 /* This barrier is needed to keep us from reading
7361                  * any other fields out of the Rx descriptor until
7362                  * we know the status of DescOwn
7363                  */
7364                 dma_rmb();
7365
7366                 if (unlikely(status & RxRES)) {
7367                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7368                                    status);
7369                         dev->stats.rx_errors++;
7370                         if (status & (RxRWT | RxRUNT))
7371                                 dev->stats.rx_length_errors++;
7372                         if (status & RxCRC)
7373                                 dev->stats.rx_crc_errors++;
7374                         if (status & RxFOVF) {
7375                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7376                                 dev->stats.rx_fifo_errors++;
7377                         }
7378                         if ((status & (RxRUNT | RxCRC)) &&
7379                             !(status & (RxRWT | RxFOVF)) &&
7380                             (dev->features & NETIF_F_RXALL))
7381                                 goto process_pkt;
7382                 } else {
7383                         struct sk_buff *skb;
7384                         dma_addr_t addr;
7385                         int pkt_size;
7386
7387 process_pkt:
7388                         addr = le64_to_cpu(desc->addr);
7389                         if (likely(!(dev->features & NETIF_F_RXFCS)))
7390                                 pkt_size = (status & 0x00003fff) - 4;
7391                         else
7392                                 pkt_size = status & 0x00003fff;
7393
7394                         /*
7395                          * The driver does not support incoming fragmented
7396                          * frames. They are seen as a symptom of over-mtu
7397                          * sized frames.
7398                          */
7399                         if (unlikely(rtl8169_fragmented_frame(status))) {
7400                                 dev->stats.rx_dropped++;
7401                                 dev->stats.rx_length_errors++;
7402                                 goto release_descriptor;
7403                         }
7404
7405                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7406                                                   tp, pkt_size, addr);
7407                         if (!skb) {
7408                                 dev->stats.rx_dropped++;
7409                                 goto release_descriptor;
7410                         }
7411
7412                         rtl8169_rx_csum(skb, status);
7413                         skb_put(skb, pkt_size);
7414                         skb->protocol = eth_type_trans(skb, dev);
7415
7416                         rtl8169_rx_vlan_tag(desc, skb);
7417
7418                         if (skb->pkt_type == PACKET_MULTICAST)
7419                                 dev->stats.multicast++;
7420
7421                         napi_gro_receive(&tp->napi, skb);
7422
7423                         u64_stats_update_begin(&tp->rx_stats.syncp);
7424                         tp->rx_stats.packets++;
7425                         tp->rx_stats.bytes += pkt_size;
7426                         u64_stats_update_end(&tp->rx_stats.syncp);
7427                 }
7428 release_descriptor:
7429                 desc->opts2 = 0;
7430                 rtl8169_mark_to_asic(desc);
7431         }
7432
7433         count = cur_rx - tp->cur_rx;
7434         tp->cur_rx = cur_rx;
7435
7436         return count;
7437 }
7438
7439 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7440 {
7441         struct net_device *dev = dev_instance;
7442         struct rtl8169_private *tp = netdev_priv(dev);
7443         int handled = 0;
7444         u16 status;
7445
7446         status = rtl_get_events(tp);
7447         if (status && status != 0xffff) {
7448                 status &= RTL_EVENT_NAPI | tp->event_slow;
7449                 if (status) {
7450                         handled = 1;
7451
7452                         rtl_irq_disable(tp);
7453                         napi_schedule_irqoff(&tp->napi);
7454                 }
7455         }
7456         return IRQ_RETVAL(handled);
7457 }
7458
7459 /*
7460  * Workqueue context.
7461  */
7462 static void rtl_slow_event_work(struct rtl8169_private *tp)
7463 {
7464         struct net_device *dev = tp->dev;
7465         u16 status;
7466
7467         status = rtl_get_events(tp) & tp->event_slow;
7468         rtl_ack_events(tp, status);
7469
7470         if (unlikely(status & RxFIFOOver)) {
7471                 switch (tp->mac_version) {
7472                 /* Work around for rx fifo overflow */
7473                 case RTL_GIGA_MAC_VER_11:
7474                         netif_stop_queue(dev);
7475                         /* XXX - Hack alert. See rtl_task(). */
7476                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7477                 default:
7478                         break;
7479                 }
7480         }
7481
7482         if (unlikely(status & SYSErr))
7483                 rtl8169_pcierr_interrupt(dev);
7484
7485         if (status & LinkChg)
7486                 rtl8169_check_link_status(dev, tp);
7487
7488         rtl_irq_enable_all(tp);
7489 }
7490
7491 static void rtl_task(struct work_struct *work)
7492 {
7493         static const struct {
7494                 int bitnr;
7495                 void (*action)(struct rtl8169_private *);
7496         } rtl_work[] = {
7497                 /* XXX - keep rtl_slow_event_work() as first element. */
7498                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
7499                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
7500                 { RTL_FLAG_TASK_PHY_PENDING,    rtl_phy_work }
7501         };
7502         struct rtl8169_private *tp =
7503                 container_of(work, struct rtl8169_private, wk.work);
7504         struct net_device *dev = tp->dev;
7505         int i;
7506
7507         rtl_lock_work(tp);
7508
7509         if (!netif_running(dev) ||
7510             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7511                 goto out_unlock;
7512
7513         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7514                 bool pending;
7515
7516                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7517                 if (pending)
7518                         rtl_work[i].action(tp);
7519         }
7520
7521 out_unlock:
7522         rtl_unlock_work(tp);
7523 }
7524
7525 static int rtl8169_poll(struct napi_struct *napi, int budget)
7526 {
7527         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7528         struct net_device *dev = tp->dev;
7529         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7530         int work_done= 0;
7531         u16 status;
7532
7533         status = rtl_get_events(tp);
7534         rtl_ack_events(tp, status & ~tp->event_slow);
7535
7536         if (status & RTL_EVENT_NAPI_RX)
7537                 work_done = rtl_rx(dev, tp, (u32) budget);
7538
7539         if (status & RTL_EVENT_NAPI_TX)
7540                 rtl_tx(dev, tp);
7541
7542         if (status & tp->event_slow) {
7543                 enable_mask &= ~tp->event_slow;
7544
7545                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7546         }
7547
7548         if (work_done < budget) {
7549                 napi_complete_done(napi, work_done);
7550
7551                 rtl_irq_enable(tp, enable_mask);
7552                 mmiowb();
7553         }
7554
7555         return work_done;
7556 }
7557
7558 static void rtl8169_rx_missed(struct net_device *dev)
7559 {
7560         struct rtl8169_private *tp = netdev_priv(dev);
7561
7562         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7563                 return;
7564
7565         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
7566         RTL_W32(tp, RxMissed, 0);
7567 }
7568
7569 static void rtl8169_down(struct net_device *dev)
7570 {
7571         struct rtl8169_private *tp = netdev_priv(dev);
7572
7573         del_timer_sync(&tp->timer);
7574
7575         napi_disable(&tp->napi);
7576         netif_stop_queue(dev);
7577
7578         rtl8169_hw_reset(tp);
7579         /*
7580          * At this point device interrupts can not be enabled in any function,
7581          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7582          * and napi is disabled (rtl8169_poll).
7583          */
7584         rtl8169_rx_missed(dev);
7585
7586         /* Give a racing hard_start_xmit a few cycles to complete. */
7587         synchronize_sched();
7588
7589         rtl8169_tx_clear(tp);
7590
7591         rtl8169_rx_clear(tp);
7592
7593         rtl_pll_power_down(tp);
7594 }
7595
7596 static int rtl8169_close(struct net_device *dev)
7597 {
7598         struct rtl8169_private *tp = netdev_priv(dev);
7599         struct pci_dev *pdev = tp->pci_dev;
7600
7601         pm_runtime_get_sync(&pdev->dev);
7602
7603         /* Update counters before going down */
7604         rtl8169_update_counters(dev);
7605
7606         rtl_lock_work(tp);
7607         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7608
7609         rtl8169_down(dev);
7610         rtl_unlock_work(tp);
7611
7612         cancel_work_sync(&tp->wk.work);
7613
7614         pci_free_irq(pdev, 0, dev);
7615
7616         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7617                           tp->RxPhyAddr);
7618         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7619                           tp->TxPhyAddr);
7620         tp->TxDescArray = NULL;
7621         tp->RxDescArray = NULL;
7622
7623         pm_runtime_put_sync(&pdev->dev);
7624
7625         return 0;
7626 }
7627
7628 #ifdef CONFIG_NET_POLL_CONTROLLER
7629 static void rtl8169_netpoll(struct net_device *dev)
7630 {
7631         struct rtl8169_private *tp = netdev_priv(dev);
7632
7633         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), dev);
7634 }
7635 #endif
7636
7637 static int rtl_open(struct net_device *dev)
7638 {
7639         struct rtl8169_private *tp = netdev_priv(dev);
7640         struct pci_dev *pdev = tp->pci_dev;
7641         int retval = -ENOMEM;
7642
7643         pm_runtime_get_sync(&pdev->dev);
7644
7645         /*
7646          * Rx and Tx descriptors needs 256 bytes alignment.
7647          * dma_alloc_coherent provides more.
7648          */
7649         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7650                                              &tp->TxPhyAddr, GFP_KERNEL);
7651         if (!tp->TxDescArray)
7652                 goto err_pm_runtime_put;
7653
7654         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7655                                              &tp->RxPhyAddr, GFP_KERNEL);
7656         if (!tp->RxDescArray)
7657                 goto err_free_tx_0;
7658
7659         retval = rtl8169_init_ring(tp);
7660         if (retval < 0)
7661                 goto err_free_rx_1;
7662
7663         INIT_WORK(&tp->wk.work, rtl_task);
7664
7665         smp_mb();
7666
7667         rtl_request_firmware(tp);
7668
7669         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, dev,
7670                                  dev->name);
7671         if (retval < 0)
7672                 goto err_release_fw_2;
7673
7674         rtl_lock_work(tp);
7675
7676         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7677
7678         napi_enable(&tp->napi);
7679
7680         rtl8169_init_phy(dev, tp);
7681
7682         __rtl8169_set_features(dev, dev->features);
7683
7684         rtl_pll_power_up(tp);
7685
7686         rtl_hw_start(tp);
7687
7688         if (!rtl8169_init_counter_offsets(dev))
7689                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7690
7691         netif_start_queue(dev);
7692
7693         rtl_unlock_work(tp);
7694
7695         tp->saved_wolopts = 0;
7696         pm_runtime_put_sync(&pdev->dev);
7697
7698         rtl8169_check_link_status(dev, tp);
7699 out:
7700         return retval;
7701
7702 err_release_fw_2:
7703         rtl_release_firmware(tp);
7704         rtl8169_rx_clear(tp);
7705 err_free_rx_1:
7706         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7707                           tp->RxPhyAddr);
7708         tp->RxDescArray = NULL;
7709 err_free_tx_0:
7710         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7711                           tp->TxPhyAddr);
7712         tp->TxDescArray = NULL;
7713 err_pm_runtime_put:
7714         pm_runtime_put_noidle(&pdev->dev);
7715         goto out;
7716 }
7717
7718 static void
7719 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7720 {
7721         struct rtl8169_private *tp = netdev_priv(dev);
7722         struct pci_dev *pdev = tp->pci_dev;
7723         struct rtl8169_counters *counters = tp->counters;
7724         unsigned int start;
7725
7726         pm_runtime_get_noresume(&pdev->dev);
7727
7728         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7729                 rtl8169_rx_missed(dev);
7730
7731         do {
7732                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7733                 stats->rx_packets = tp->rx_stats.packets;
7734                 stats->rx_bytes = tp->rx_stats.bytes;
7735         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7736
7737         do {
7738                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7739                 stats->tx_packets = tp->tx_stats.packets;
7740                 stats->tx_bytes = tp->tx_stats.bytes;
7741         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7742
7743         stats->rx_dropped       = dev->stats.rx_dropped;
7744         stats->tx_dropped       = dev->stats.tx_dropped;
7745         stats->rx_length_errors = dev->stats.rx_length_errors;
7746         stats->rx_errors        = dev->stats.rx_errors;
7747         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7748         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7749         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7750         stats->multicast        = dev->stats.multicast;
7751
7752         /*
7753          * Fetch additonal counter values missing in stats collected by driver
7754          * from tally counters.
7755          */
7756         if (pm_runtime_active(&pdev->dev))
7757                 rtl8169_update_counters(dev);
7758
7759         /*
7760          * Subtract values fetched during initalization.
7761          * See rtl8169_init_counter_offsets for a description why we do that.
7762          */
7763         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7764                 le64_to_cpu(tp->tc_offset.tx_errors);
7765         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7766                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7767         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7768                 le16_to_cpu(tp->tc_offset.tx_aborted);
7769
7770         pm_runtime_put_noidle(&pdev->dev);
7771 }
7772
7773 static void rtl8169_net_suspend(struct net_device *dev)
7774 {
7775         struct rtl8169_private *tp = netdev_priv(dev);
7776
7777         if (!netif_running(dev))
7778                 return;
7779
7780         netif_device_detach(dev);
7781         netif_stop_queue(dev);
7782
7783         rtl_lock_work(tp);
7784         napi_disable(&tp->napi);
7785         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7786         rtl_unlock_work(tp);
7787
7788         rtl_pll_power_down(tp);
7789 }
7790
7791 #ifdef CONFIG_PM
7792
7793 static int rtl8169_suspend(struct device *device)
7794 {
7795         struct pci_dev *pdev = to_pci_dev(device);
7796         struct net_device *dev = pci_get_drvdata(pdev);
7797
7798         rtl8169_net_suspend(dev);
7799
7800         return 0;
7801 }
7802
7803 static void __rtl8169_resume(struct net_device *dev)
7804 {
7805         struct rtl8169_private *tp = netdev_priv(dev);
7806
7807         netif_device_attach(dev);
7808
7809         rtl_pll_power_up(tp);
7810
7811         rtl_lock_work(tp);
7812         napi_enable(&tp->napi);
7813         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7814         rtl_unlock_work(tp);
7815
7816         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7817 }
7818
7819 static int rtl8169_resume(struct device *device)
7820 {
7821         struct pci_dev *pdev = to_pci_dev(device);
7822         struct net_device *dev = pci_get_drvdata(pdev);
7823         struct rtl8169_private *tp = netdev_priv(dev);
7824
7825         rtl8169_init_phy(dev, tp);
7826
7827         if (netif_running(dev))
7828                 __rtl8169_resume(dev);
7829
7830         return 0;
7831 }
7832
7833 static int rtl8169_runtime_suspend(struct device *device)
7834 {
7835         struct pci_dev *pdev = to_pci_dev(device);
7836         struct net_device *dev = pci_get_drvdata(pdev);
7837         struct rtl8169_private *tp = netdev_priv(dev);
7838
7839         if (!tp->TxDescArray) {
7840                 rtl_pll_power_down(tp);
7841                 return 0;
7842         }
7843
7844         rtl_lock_work(tp);
7845         tp->saved_wolopts = __rtl8169_get_wol(tp);
7846         __rtl8169_set_wol(tp, WAKE_ANY);
7847         rtl_unlock_work(tp);
7848
7849         rtl8169_net_suspend(dev);
7850
7851         /* Update counters before going runtime suspend */
7852         rtl8169_rx_missed(dev);
7853         rtl8169_update_counters(dev);
7854
7855         return 0;
7856 }
7857
7858 static int rtl8169_runtime_resume(struct device *device)
7859 {
7860         struct pci_dev *pdev = to_pci_dev(device);
7861         struct net_device *dev = pci_get_drvdata(pdev);
7862         struct rtl8169_private *tp = netdev_priv(dev);
7863         rtl_rar_set(tp, dev->dev_addr);
7864
7865         if (!tp->TxDescArray)
7866                 return 0;
7867
7868         rtl_lock_work(tp);
7869         __rtl8169_set_wol(tp, tp->saved_wolopts);
7870         tp->saved_wolopts = 0;
7871         rtl_unlock_work(tp);
7872
7873         rtl8169_init_phy(dev, tp);
7874
7875         __rtl8169_resume(dev);
7876
7877         return 0;
7878 }
7879
7880 static int rtl8169_runtime_idle(struct device *device)
7881 {
7882         struct pci_dev *pdev = to_pci_dev(device);
7883         struct net_device *dev = pci_get_drvdata(pdev);
7884
7885         if (!netif_running(dev) || !netif_carrier_ok(dev))
7886                 pm_schedule_suspend(device, 10000);
7887
7888         return -EBUSY;
7889 }
7890
7891 static const struct dev_pm_ops rtl8169_pm_ops = {
7892         .suspend                = rtl8169_suspend,
7893         .resume                 = rtl8169_resume,
7894         .freeze                 = rtl8169_suspend,
7895         .thaw                   = rtl8169_resume,
7896         .poweroff               = rtl8169_suspend,
7897         .restore                = rtl8169_resume,
7898         .runtime_suspend        = rtl8169_runtime_suspend,
7899         .runtime_resume         = rtl8169_runtime_resume,
7900         .runtime_idle           = rtl8169_runtime_idle,
7901 };
7902
7903 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7904
7905 #else /* !CONFIG_PM */
7906
7907 #define RTL8169_PM_OPS  NULL
7908
7909 #endif /* !CONFIG_PM */
7910
7911 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7912 {
7913         /* WoL fails with 8168b when the receiver is disabled. */
7914         switch (tp->mac_version) {
7915         case RTL_GIGA_MAC_VER_11:
7916         case RTL_GIGA_MAC_VER_12:
7917         case RTL_GIGA_MAC_VER_17:
7918                 pci_clear_master(tp->pci_dev);
7919
7920                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7921                 /* PCI commit */
7922                 RTL_R8(tp, ChipCmd);
7923                 break;
7924         default:
7925                 break;
7926         }
7927 }
7928
7929 static void rtl_shutdown(struct pci_dev *pdev)
7930 {
7931         struct net_device *dev = pci_get_drvdata(pdev);
7932         struct rtl8169_private *tp = netdev_priv(dev);
7933
7934         rtl8169_net_suspend(dev);
7935
7936         /* Restore original MAC address */
7937         rtl_rar_set(tp, dev->perm_addr);
7938
7939         rtl8169_hw_reset(tp);
7940
7941         if (system_state == SYSTEM_POWER_OFF) {
7942                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7943                         rtl_wol_suspend_quirk(tp);
7944                         rtl_wol_shutdown_quirk(tp);
7945                 }
7946
7947                 pci_wake_from_d3(pdev, true);
7948                 pci_set_power_state(pdev, PCI_D3hot);
7949         }
7950 }
7951
7952 static void rtl_remove_one(struct pci_dev *pdev)
7953 {
7954         struct net_device *dev = pci_get_drvdata(pdev);
7955         struct rtl8169_private *tp = netdev_priv(dev);
7956
7957         if (r8168_check_dash(tp))
7958                 rtl8168_driver_stop(tp);
7959
7960         netif_napi_del(&tp->napi);
7961
7962         unregister_netdev(dev);
7963
7964         rtl_release_firmware(tp);
7965
7966         if (pci_dev_run_wake(pdev))
7967                 pm_runtime_get_noresume(&pdev->dev);
7968
7969         /* restore original MAC address */
7970         rtl_rar_set(tp, dev->perm_addr);
7971 }
7972
7973 static const struct net_device_ops rtl_netdev_ops = {
7974         .ndo_open               = rtl_open,
7975         .ndo_stop               = rtl8169_close,
7976         .ndo_get_stats64        = rtl8169_get_stats64,
7977         .ndo_start_xmit         = rtl8169_start_xmit,
7978         .ndo_tx_timeout         = rtl8169_tx_timeout,
7979         .ndo_validate_addr      = eth_validate_addr,
7980         .ndo_change_mtu         = rtl8169_change_mtu,
7981         .ndo_fix_features       = rtl8169_fix_features,
7982         .ndo_set_features       = rtl8169_set_features,
7983         .ndo_set_mac_address    = rtl_set_mac_address,
7984         .ndo_do_ioctl           = rtl8169_ioctl,
7985         .ndo_set_rx_mode        = rtl_set_rx_mode,
7986 #ifdef CONFIG_NET_POLL_CONTROLLER
7987         .ndo_poll_controller    = rtl8169_netpoll,
7988 #endif
7989
7990 };
7991
7992 static const struct rtl_cfg_info {
7993         void (*hw_start)(struct rtl8169_private *tp);
7994         unsigned int region;
7995         u16 event_slow;
7996         unsigned int has_gmii:1;
7997         const struct rtl_coalesce_info *coalesce_info;
7998         u8 default_ver;
7999 } rtl_cfg_infos [] = {
8000         [RTL_CFG_0] = {
8001                 .hw_start       = rtl_hw_start_8169,
8002                 .region         = 1,
8003                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8004                 .has_gmii       = 1,
8005                 .coalesce_info  = rtl_coalesce_info_8169,
8006                 .default_ver    = RTL_GIGA_MAC_VER_01,
8007         },
8008         [RTL_CFG_1] = {
8009                 .hw_start       = rtl_hw_start_8168,
8010                 .region         = 2,
8011                 .event_slow     = SYSErr | LinkChg | RxOverflow,
8012                 .has_gmii       = 1,
8013                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8014                 .default_ver    = RTL_GIGA_MAC_VER_11,
8015         },
8016         [RTL_CFG_2] = {
8017                 .hw_start       = rtl_hw_start_8101,
8018                 .region         = 2,
8019                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8020                                   PCSTimeout,
8021                 .coalesce_info  = rtl_coalesce_info_8168_8136,
8022                 .default_ver    = RTL_GIGA_MAC_VER_13,
8023         }
8024 };
8025
8026 static int rtl_alloc_irq(struct rtl8169_private *tp)
8027 {
8028         unsigned int flags;
8029
8030         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
8031                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
8032                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
8033                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
8034                 flags = PCI_IRQ_LEGACY;
8035         } else {
8036                 flags = PCI_IRQ_ALL_TYPES;
8037         }
8038
8039         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
8040 }
8041
8042 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8043 {
8044         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
8045 }
8046
8047 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8048 {
8049         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8050 }
8051
8052 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8053 {
8054         u32 data;
8055
8056         tp->ocp_base = OCP_STD_PHY_BASE;
8057
8058         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
8059
8060         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8061                 return;
8062
8063         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8064                 return;
8065
8066         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8067         msleep(1);
8068         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
8069
8070         data = r8168_mac_ocp_read(tp, 0xe8de);
8071         data &= ~(1 << 14);
8072         r8168_mac_ocp_write(tp, 0xe8de, data);
8073
8074         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8075                 return;
8076
8077         data = r8168_mac_ocp_read(tp, 0xe8de);
8078         data |= (1 << 15);
8079         r8168_mac_ocp_write(tp, 0xe8de, data);
8080
8081         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8082                 return;
8083 }
8084
8085 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8086 {
8087         rtl8168ep_stop_cmac(tp);
8088         rtl_hw_init_8168g(tp);
8089 }
8090
8091 static void rtl_hw_initialize(struct rtl8169_private *tp)
8092 {
8093         switch (tp->mac_version) {
8094         case RTL_GIGA_MAC_VER_40:
8095         case RTL_GIGA_MAC_VER_41:
8096         case RTL_GIGA_MAC_VER_42:
8097         case RTL_GIGA_MAC_VER_43:
8098         case RTL_GIGA_MAC_VER_44:
8099         case RTL_GIGA_MAC_VER_45:
8100         case RTL_GIGA_MAC_VER_46:
8101         case RTL_GIGA_MAC_VER_47:
8102         case RTL_GIGA_MAC_VER_48:
8103                 rtl_hw_init_8168g(tp);
8104                 break;
8105         case RTL_GIGA_MAC_VER_49:
8106         case RTL_GIGA_MAC_VER_50:
8107         case RTL_GIGA_MAC_VER_51:
8108                 rtl_hw_init_8168ep(tp);
8109                 break;
8110         default:
8111                 break;
8112         }
8113 }
8114
8115 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8116 {
8117         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8118         const unsigned int region = cfg->region;
8119         struct rtl8169_private *tp;
8120         struct mii_if_info *mii;
8121         struct net_device *dev;
8122         int chipset, i;
8123         int rc;
8124
8125         if (netif_msg_drv(&debug)) {
8126                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8127                        MODULENAME, RTL8169_VERSION);
8128         }
8129
8130         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8131         if (!dev)
8132                 return -ENOMEM;
8133
8134         SET_NETDEV_DEV(dev, &pdev->dev);
8135         dev->netdev_ops = &rtl_netdev_ops;
8136         tp = netdev_priv(dev);
8137         tp->dev = dev;
8138         tp->pci_dev = pdev;
8139         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8140
8141         mii = &tp->mii;
8142         mii->dev = dev;
8143         mii->mdio_read = rtl_mdio_read;
8144         mii->mdio_write = rtl_mdio_write;
8145         mii->phy_id_mask = 0x1f;
8146         mii->reg_num_mask = 0x1f;
8147         mii->supports_gmii = cfg->has_gmii;
8148
8149         /* disable ASPM completely as that cause random device stop working
8150          * problems as well as full system hangs for some PCIe devices users */
8151         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8152                                      PCIE_LINK_STATE_CLKPM);
8153
8154         /* enable device (incl. PCI PM wakeup and hotplug setup) */
8155         rc = pcim_enable_device(pdev);
8156         if (rc < 0) {
8157                 netif_err(tp, probe, dev, "enable failure\n");
8158                 return rc;
8159         }
8160
8161         if (pcim_set_mwi(pdev) < 0)
8162                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8163
8164         /* make sure PCI base addr 1 is MMIO */
8165         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8166                 netif_err(tp, probe, dev,
8167                           "region #%d not an MMIO resource, aborting\n",
8168                           region);
8169                 return -ENODEV;
8170         }
8171
8172         /* check for weird/broken PCI region reporting */
8173         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8174                 netif_err(tp, probe, dev,
8175                           "Invalid PCI region size(s), aborting\n");
8176                 return -ENODEV;
8177         }
8178
8179         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
8180         if (rc < 0) {
8181                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8182                 return rc;
8183         }
8184
8185         tp->mmio_addr = pcim_iomap_table(pdev)[region];
8186
8187         if (!pci_is_pcie(pdev))
8188                 netif_info(tp, probe, dev, "not PCI Express\n");
8189
8190         /* Identify chip attached to board */
8191         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8192
8193         tp->cp_cmd = 0;
8194
8195         if ((sizeof(dma_addr_t) > 4) &&
8196             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8197                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8198             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8199             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8200
8201                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8202                 if (!pci_is_pcie(pdev))
8203                         tp->cp_cmd |= PCIDAC;
8204                 dev->features |= NETIF_F_HIGHDMA;
8205         } else {
8206                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8207                 if (rc < 0) {
8208                         netif_err(tp, probe, dev, "DMA configuration failed\n");
8209                         return rc;
8210                 }
8211         }
8212
8213         rtl_init_rxcfg(tp);
8214
8215         rtl_irq_disable(tp);
8216
8217         rtl_hw_initialize(tp);
8218
8219         rtl_hw_reset(tp);
8220
8221         rtl_ack_events(tp, 0xffff);
8222
8223         pci_set_master(pdev);
8224
8225         rtl_init_mdio_ops(tp);
8226         rtl_init_pll_power_ops(tp);
8227         rtl_init_jumbo_ops(tp);
8228         rtl_init_csi_ops(tp);
8229
8230         rtl8169_print_mac_version(tp);
8231
8232         chipset = tp->mac_version;
8233         tp->txd_version = rtl_chip_infos[chipset].txd_version;
8234
8235         rc = rtl_alloc_irq(tp);
8236         if (rc < 0) {
8237                 netif_err(tp, probe, dev, "Can't allocate interrupt\n");
8238                 return rc;
8239         }
8240
8241         /* override BIOS settings, use userspace tools to enable WOL */
8242         __rtl8169_set_wol(tp, 0);
8243
8244         if (rtl_tbi_enabled(tp)) {
8245                 tp->set_speed = rtl8169_set_speed_tbi;
8246                 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8247                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8248                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8249                 tp->link_ok = rtl8169_tbi_link_ok;
8250                 tp->do_ioctl = rtl_tbi_ioctl;
8251         } else {
8252                 tp->set_speed = rtl8169_set_speed_xmii;
8253                 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8254                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8255                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8256                 tp->link_ok = rtl8169_xmii_link_ok;
8257                 tp->do_ioctl = rtl_xmii_ioctl;
8258         }
8259
8260         mutex_init(&tp->wk.mutex);
8261         u64_stats_init(&tp->rx_stats.syncp);
8262         u64_stats_init(&tp->tx_stats.syncp);
8263
8264         /* Get MAC address */
8265         if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8266             tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8267             tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8268             tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8269             tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8270             tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8271             tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8272             tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8273             tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8274             tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8275             tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8276             tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8277             tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8278             tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8279             tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8280             tp->mac_version == RTL_GIGA_MAC_VER_51) {
8281                 u16 mac_addr[3];
8282
8283                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8284                 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8285
8286                 if (is_valid_ether_addr((u8 *)mac_addr))
8287                         rtl_rar_set(tp, (u8 *)mac_addr);
8288         }
8289         for (i = 0; i < ETH_ALEN; i++)
8290                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
8291
8292         dev->ethtool_ops = &rtl8169_ethtool_ops;
8293         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8294
8295         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
8296
8297         /* don't enable SG, IP_CSUM and TSO by default - it might not work
8298          * properly for all devices */
8299         dev->features |= NETIF_F_RXCSUM |
8300                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8301
8302         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8303                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8304                 NETIF_F_HW_VLAN_CTAG_RX;
8305         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8306                 NETIF_F_HIGHDMA;
8307
8308         tp->cp_cmd |= RxChkSum | RxVlan;
8309
8310         /*
8311          * Pretend we are using VLANs; This bypasses a nasty bug where
8312          * Interrupts stop flowing on high load on 8110SCd controllers.
8313          */
8314         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8315                 /* Disallow toggling */
8316                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8317
8318         if (tp->txd_version == RTL_TD_0)
8319                 tp->tso_csum = rtl8169_tso_csum_v1;
8320         else if (tp->txd_version == RTL_TD_1) {
8321                 tp->tso_csum = rtl8169_tso_csum_v2;
8322                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8323         } else
8324                 WARN_ON_ONCE(1);
8325
8326         dev->hw_features |= NETIF_F_RXALL;
8327         dev->hw_features |= NETIF_F_RXFCS;
8328
8329         /* MTU range: 60 - hw-specific max */
8330         dev->min_mtu = ETH_ZLEN;
8331         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8332
8333         tp->hw_start = cfg->hw_start;
8334         tp->event_slow = cfg->event_slow;
8335         tp->coalesce_info = cfg->coalesce_info;
8336
8337         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8338                 ~(RxBOVF | RxFOVF) : ~0;
8339
8340         timer_setup(&tp->timer, rtl8169_phy_timer, 0);
8341
8342         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8343
8344         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8345                                             &tp->counters_phys_addr,
8346                                             GFP_KERNEL);
8347         if (!tp->counters)
8348                 return -ENOMEM;
8349
8350         pci_set_drvdata(pdev, dev);
8351
8352         rc = register_netdev(dev);
8353         if (rc < 0)
8354                 return rc;
8355
8356         netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8357                    rtl_chip_infos[chipset].name, tp->mmio_addr, dev->dev_addr,
8358                    (u32)(RTL_R32(tp, TxConfig) & 0x9cf0f8ff),
8359                    pci_irq_vector(pdev, 0));
8360         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8361                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8362                            "tx checksumming: %s]\n",
8363                            rtl_chip_infos[chipset].jumbo_max,
8364                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8365         }
8366
8367         if (r8168_check_dash(tp))
8368                 rtl8168_driver_start(tp);
8369
8370         netif_carrier_off(dev);
8371
8372         if (pci_dev_run_wake(pdev))
8373                 pm_runtime_put_sync(&pdev->dev);
8374
8375         return 0;
8376 }
8377
8378 static struct pci_driver rtl8169_pci_driver = {
8379         .name           = MODULENAME,
8380         .id_table       = rtl8169_pci_tbl,
8381         .probe          = rtl_init_one,
8382         .remove         = rtl_remove_one,
8383         .shutdown       = rtl_shutdown,
8384         .driver.pm      = RTL8169_PM_OPS,
8385 };
8386
8387 module_pci_driver(rtl8169_pci_driver);