drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/ip.h>
  24 #include <linux/tcp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/prefetch.h>
  30 #include <linux/ipv6.h>
  31 #include <net/ip6_checksum.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  44 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  45 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  46 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  47 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  48 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  49 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  50 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  51 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  52 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  53 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  54 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  55 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 #define TX_SLOTS_AVAIL(tp) \
  63         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
  64
  65 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
  66 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
  67         (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
  68
  69 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  70    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  71 static const int multicast_filter_limit = 32;
  72
  73 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  74 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  75
  76 #define R8169_REGS_SIZE         256
  77 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  78 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  79 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  80 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  81 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  82
  83 #define RTL8169_TX_TIMEOUT      (6*HZ)
  84
  85 /* write/read MMIO register */
  86 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  87 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  88 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  89 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  90 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  91 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  92
  93 enum mac_version {
  94         RTL_GIGA_MAC_VER_01 = 0,
  95         RTL_GIGA_MAC_VER_02,
  96         RTL_GIGA_MAC_VER_03,
  97         RTL_GIGA_MAC_VER_04,
  98         RTL_GIGA_MAC_VER_05,
  99         RTL_GIGA_MAC_VER_06,
 100         RTL_GIGA_MAC_VER_07,
 101         RTL_GIGA_MAC_VER_08,
 102         RTL_GIGA_MAC_VER_09,
 103         RTL_GIGA_MAC_VER_10,
 104         RTL_GIGA_MAC_VER_11,
 105         RTL_GIGA_MAC_VER_12,
 106         RTL_GIGA_MAC_VER_13,
 107         RTL_GIGA_MAC_VER_14,
 108         RTL_GIGA_MAC_VER_15,
 109         RTL_GIGA_MAC_VER_16,
 110         RTL_GIGA_MAC_VER_17,
 111         RTL_GIGA_MAC_VER_18,
 112         RTL_GIGA_MAC_VER_19,
 113         RTL_GIGA_MAC_VER_20,
 114         RTL_GIGA_MAC_VER_21,
 115         RTL_GIGA_MAC_VER_22,
 116         RTL_GIGA_MAC_VER_23,
 117         RTL_GIGA_MAC_VER_24,
 118         RTL_GIGA_MAC_VER_25,
 119         RTL_GIGA_MAC_VER_26,
 120         RTL_GIGA_MAC_VER_27,
 121         RTL_GIGA_MAC_VER_28,
 122         RTL_GIGA_MAC_VER_29,
 123         RTL_GIGA_MAC_VER_30,
 124         RTL_GIGA_MAC_VER_31,
 125         RTL_GIGA_MAC_VER_32,
 126         RTL_GIGA_MAC_VER_33,
 127         RTL_GIGA_MAC_VER_34,
 128         RTL_GIGA_MAC_VER_35,
 129         RTL_GIGA_MAC_VER_36,
 130         RTL_GIGA_MAC_VER_37,
 131         RTL_GIGA_MAC_VER_38,
 132         RTL_GIGA_MAC_VER_39,
 133         RTL_GIGA_MAC_VER_40,
 134         RTL_GIGA_MAC_VER_41,
 135         RTL_GIGA_MAC_VER_42,
 136         RTL_GIGA_MAC_VER_43,
 137         RTL_GIGA_MAC_VER_44,
 138         RTL_GIGA_MAC_VER_45,
 139         RTL_GIGA_MAC_VER_46,
 140         RTL_GIGA_MAC_VER_47,
 141         RTL_GIGA_MAC_VER_48,
 142         RTL_GIGA_MAC_VER_49,
 143         RTL_GIGA_MAC_VER_50,
 144         RTL_GIGA_MAC_VER_51,
 145         RTL_GIGA_MAC_NONE   = 0xff,
 146 };
 147
 148 enum rtl_tx_desc_version {
 149         RTL_TD_0        = 0,
 150         RTL_TD_1        = 1,
 151 };
 152
 153 #define JUMBO_1K        ETH_DATA_LEN
 154 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 155 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 156 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 157 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 158
 159 #define _R(NAME,TD,FW,SZ) {     \
 160         .name = NAME,           \
 161         .txd_version = TD,      \
 162         .fw_name = FW,          \
 163         .jumbo_max = SZ,        \
 164 }
 165
 166 static const struct {
 167         const char *name;
 168         enum rtl_tx_desc_version txd_version;
 169         const char *fw_name;
 170         u16 jumbo_max;
 171 } rtl_chip_infos[] = {
 172         /* PCI devices. */
 173         [RTL_GIGA_MAC_VER_01] =
 174                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K),
 175         [RTL_GIGA_MAC_VER_02] =
 176                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K),
 177         [RTL_GIGA_MAC_VER_03] =
 178                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K),
 179         [RTL_GIGA_MAC_VER_04] =
 180                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K),
 181         [RTL_GIGA_MAC_VER_05] =
 182                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 183         [RTL_GIGA_MAC_VER_06] =
 184                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K),
 185         /* PCI-E devices. */
 186         [RTL_GIGA_MAC_VER_07] =
 187                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 188         [RTL_GIGA_MAC_VER_08] =
 189                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 190         [RTL_GIGA_MAC_VER_09] =
 191                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K),
 192         [RTL_GIGA_MAC_VER_10] =
 193                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 194         [RTL_GIGA_MAC_VER_11] =
 195                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 196         [RTL_GIGA_MAC_VER_12] =
 197                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 198         [RTL_GIGA_MAC_VER_13] =
 199                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 200         [RTL_GIGA_MAC_VER_14] =
 201                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 202         [RTL_GIGA_MAC_VER_15] =
 203                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K),
 204         [RTL_GIGA_MAC_VER_16] =
 205                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K),
 206         [RTL_GIGA_MAC_VER_17] =
 207                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K),
 208         [RTL_GIGA_MAC_VER_18] =
 209                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 210         [RTL_GIGA_MAC_VER_19] =
 211                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 212         [RTL_GIGA_MAC_VER_20] =
 213                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 214         [RTL_GIGA_MAC_VER_21] =
 215                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 216         [RTL_GIGA_MAC_VER_22] =
 217                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K),
 218         [RTL_GIGA_MAC_VER_23] =
 219                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 220         [RTL_GIGA_MAC_VER_24] =
 221                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K),
 222         [RTL_GIGA_MAC_VER_25] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1, JUMBO_9K),
 224         [RTL_GIGA_MAC_VER_26] =
 225                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2, JUMBO_9K),
 226         [RTL_GIGA_MAC_VER_27] =
 227                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 228         [RTL_GIGA_MAC_VER_28] =
 229                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 230         [RTL_GIGA_MAC_VER_29] =
 231                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 232         [RTL_GIGA_MAC_VER_30] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1, JUMBO_1K),
 234         [RTL_GIGA_MAC_VER_31] =
 235                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K),
 236         [RTL_GIGA_MAC_VER_32] =
 237                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1, JUMBO_9K),
 238         [RTL_GIGA_MAC_VER_33] =
 239                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2, JUMBO_9K),
 240         [RTL_GIGA_MAC_VER_34] =
 241                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3, JUMBO_9K),
 242         [RTL_GIGA_MAC_VER_35] =
 243                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1, JUMBO_9K),
 244         [RTL_GIGA_MAC_VER_36] =
 245                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2, JUMBO_9K),
 246         [RTL_GIGA_MAC_VER_37] =
 247                 _R("RTL8402",           RTL_TD_1, FIRMWARE_8402_1,  JUMBO_1K),
 248         [RTL_GIGA_MAC_VER_38] =
 249                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_1,  JUMBO_9K),
 250         [RTL_GIGA_MAC_VER_39] =
 251                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1, JUMBO_1K),
 252         [RTL_GIGA_MAC_VER_40] =
 253                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2, JUMBO_9K),
 254         [RTL_GIGA_MAC_VER_41] =
 255                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K),
 256         [RTL_GIGA_MAC_VER_42] =
 257                 _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3, JUMBO_9K),
 258         [RTL_GIGA_MAC_VER_43] =
 259                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2, JUMBO_1K),
 260         [RTL_GIGA_MAC_VER_44] =
 261                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,  JUMBO_9K),
 262         [RTL_GIGA_MAC_VER_45] =
 263                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1, JUMBO_9K),
 264         [RTL_GIGA_MAC_VER_46] =
 265                 _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2, JUMBO_9K),
 266         [RTL_GIGA_MAC_VER_47] =
 267                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1, JUMBO_1K),
 268         [RTL_GIGA_MAC_VER_48] =
 269                 _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2, JUMBO_1K),
 270         [RTL_GIGA_MAC_VER_49] =
 271                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 272         [RTL_GIGA_MAC_VER_50] =
 273                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 274         [RTL_GIGA_MAC_VER_51] =
 275                 _R("RTL8168ep/8111ep",  RTL_TD_1, NULL, JUMBO_9K),
 276 };
 277 #undef _R
 278
 279 enum cfg_version {
 280         RTL_CFG_0 = 0x00,
 281         RTL_CFG_1,
 282         RTL_CFG_2
 283 };
 284
 285 static const struct pci_device_id rtl8169_pci_tbl[] = {
 286         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 287         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 288         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8161), 0, 0, RTL_CFG_1 },
 289         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 290         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 291         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 292         { PCI_VENDOR_ID_DLINK,                  0x4300,
 293                 PCI_VENDOR_ID_DLINK, 0x4b10,             0, 0, RTL_CFG_1 },
 294         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 295         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 296         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 297         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 298         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 299                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 300         { 0x0001,                               0x8168,
 301                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 302         {0,},
 303 };
 304
 305 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 306
 307 static int use_dac = -1;
 308 static struct {
 309         u32 msg_enable;
 310 } debug = { -1 };
 311
 312 enum rtl_registers {
 313         MAC0            = 0,    /* Ethernet hardware address. */
 314         MAC4            = 4,
 315         MAR0            = 8,    /* Multicast filter. */
 316         CounterAddrLow          = 0x10,
 317         CounterAddrHigh         = 0x14,
 318         TxDescStartAddrLow      = 0x20,
 319         TxDescStartAddrHigh     = 0x24,
 320         TxHDescStartAddrLow     = 0x28,
 321         TxHDescStartAddrHigh    = 0x2c,
 322         FLASH           = 0x30,
 323         ERSR            = 0x36,
 324         ChipCmd         = 0x37,
 325         TxPoll          = 0x38,
 326         IntrMask        = 0x3c,
 327         IntrStatus      = 0x3e,
 328
 329         TxConfig        = 0x40,
 330 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 331 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 332
 333         RxConfig        = 0x44,
 334 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 335 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 336 #define RXCFG_FIFO_SHIFT                13
 337                                         /* No threshold before first PCI xfer */
 338 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 339 #define RX_EARLY_OFF                    (1 << 11)
 340 #define RXCFG_DMA_SHIFT                 8
 341                                         /* Unlimited maximum PCI burst. */
 342 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 343
 344         RxMissed        = 0x4c,
 345         Cfg9346         = 0x50,
 346         Config0         = 0x51,
 347         Config1         = 0x52,
 348         Config2         = 0x53,
 349 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 350
 351         Config3         = 0x54,
 352         Config4         = 0x55,
 353         Config5         = 0x56,
 354         MultiIntr       = 0x5c,
 355         PHYAR           = 0x60,
 356         PHYstatus       = 0x6c,
 357         RxMaxSize       = 0xda,
 358         CPlusCmd        = 0xe0,
 359         IntrMitigate    = 0xe2,
 360
 361 #define RTL_COALESCE_MASK       0x0f
 362 #define RTL_COALESCE_SHIFT      4
 363 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 364 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 365
 366         RxDescAddrLow   = 0xe4,
 367         RxDescAddrHigh  = 0xe8,
 368         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 369
 370 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 371
 372         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 373
 374 #define TxPacketMax     (8064 >> 7)
 375 #define EarlySize       0x27
 376
 377         FuncEvent       = 0xf0,
 378         FuncEventMask   = 0xf4,
 379         FuncPresetState = 0xf8,
 380         IBCR0           = 0xf8,
 381         IBCR2           = 0xf9,
 382         IBIMR0          = 0xfa,
 383         IBISR0          = 0xfb,
 384         FuncForceEvent  = 0xfc,
 385 };
 386
 387 enum rtl8168_8101_registers {
 388         CSIDR                   = 0x64,
 389         CSIAR                   = 0x68,
 390 #define CSIAR_FLAG                      0x80000000
 391 #define CSIAR_WRITE_CMD                 0x80000000
 392 #define CSIAR_BYTE_ENABLE               0x0000f000
 393 #define CSIAR_ADDR_MASK                 0x00000fff
 394         PMCH                    = 0x6f,
 395         EPHYAR                  = 0x80,
 396 #define EPHYAR_FLAG                     0x80000000
 397 #define EPHYAR_WRITE_CMD                0x80000000
 398 #define EPHYAR_REG_MASK                 0x1f
 399 #define EPHYAR_REG_SHIFT                16
 400 #define EPHYAR_DATA_MASK                0xffff
 401         DLLPR                   = 0xd0,
 402 #define PFM_EN                          (1 << 6)
 403 #define TX_10M_PS_EN                    (1 << 7)
 404         DBG_REG                 = 0xd1,
 405 #define FIX_NAK_1                       (1 << 4)
 406 #define FIX_NAK_2                       (1 << 3)
 407         TWSI                    = 0xd2,
 408         MCU                     = 0xd3,
 409 #define NOW_IS_OOB                      (1 << 7)
 410 #define TX_EMPTY                        (1 << 5)
 411 #define RX_EMPTY                        (1 << 4)
 412 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 413 #define EN_NDP                          (1 << 3)
 414 #define EN_OOB_RESET                    (1 << 2)
 415 #define LINK_LIST_RDY                   (1 << 1)
 416         EFUSEAR                 = 0xdc,
 417 #define EFUSEAR_FLAG                    0x80000000
 418 #define EFUSEAR_WRITE_CMD               0x80000000
 419 #define EFUSEAR_READ_CMD                0x00000000
 420 #define EFUSEAR_REG_MASK                0x03ff
 421 #define EFUSEAR_REG_SHIFT               8
 422 #define EFUSEAR_DATA_MASK               0xff
 423         MISC_1                  = 0xf2,
 424 #define PFM_D3COLD_EN                   (1 << 6)
 425 };
 426
 427 enum rtl8168_registers {
 428         LED_FREQ                = 0x1a,
 429         EEE_LED                 = 0x1b,
 430         ERIDR                   = 0x70,
 431         ERIAR                   = 0x74,
 432 #define ERIAR_FLAG                      0x80000000
 433 #define ERIAR_WRITE_CMD                 0x80000000
 434 #define ERIAR_READ_CMD                  0x00000000
 435 #define ERIAR_ADDR_BYTE_ALIGN           4
 436 #define ERIAR_TYPE_SHIFT                16
 437 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 438 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 439 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 440 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 441 #define ERIAR_MASK_SHIFT                12
 442 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 443 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 444 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 445 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 446 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 447         EPHY_RXER_NUM           = 0x7c,
 448         OCPDR                   = 0xb0, /* OCP GPHY access */
 449 #define OCPDR_WRITE_CMD                 0x80000000
 450 #define OCPDR_READ_CMD                  0x00000000
 451 #define OCPDR_REG_MASK                  0x7f
 452 #define OCPDR_GPHY_REG_SHIFT            16
 453 #define OCPDR_DATA_MASK                 0xffff
 454         OCPAR                   = 0xb4,
 455 #define OCPAR_FLAG                      0x80000000
 456 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 457 #define OCPAR_GPHY_READ_CMD             0x0000f060
 458         GPHY_OCP                = 0xb8,
 459         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 460         MISC                    = 0xf0, /* 8168e only. */
 461 #define TXPLA_RST                       (1 << 29)
 462 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 463 #define PWM_EN                          (1 << 22)
 464 #define RXDV_GATED_EN                   (1 << 19)
 465 #define EARLY_TALLY_EN                  (1 << 16)
 466 };
 467
 468 enum rtl_register_content {
 469         /* InterruptStatusBits */
 470         SYSErr          = 0x8000,
 471         PCSTimeout      = 0x4000,
 472         SWInt           = 0x0100,
 473         TxDescUnavail   = 0x0080,
 474         RxFIFOOver      = 0x0040,
 475         LinkChg         = 0x0020,
 476         RxOverflow      = 0x0010,
 477         TxErr           = 0x0008,
 478         TxOK            = 0x0004,
 479         RxErr           = 0x0002,
 480         RxOK            = 0x0001,
 481
 482         /* RxStatusDesc */
 483         RxBOVF  = (1 << 24),
 484         RxFOVF  = (1 << 23),
 485         RxRWT   = (1 << 22),
 486         RxRES   = (1 << 21),
 487         RxRUNT  = (1 << 20),
 488         RxCRC   = (1 << 19),
 489
 490         /* ChipCmdBits */
 491         StopReq         = 0x80,
 492         CmdReset        = 0x10,
 493         CmdRxEnb        = 0x08,
 494         CmdTxEnb        = 0x04,
 495         RxBufEmpty      = 0x01,
 496
 497         /* TXPoll register p.5 */
 498         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 499         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 500         FSWInt          = 0x01,         /* Forced software interrupt */
 501
 502         /* Cfg9346Bits */
 503         Cfg9346_Lock    = 0x00,
 504         Cfg9346_Unlock  = 0xc0,
 505
 506         /* rx_mode_bits */
 507         AcceptErr       = 0x20,
 508         AcceptRunt      = 0x10,
 509         AcceptBroadcast = 0x08,
 510         AcceptMulticast = 0x04,
 511         AcceptMyPhys    = 0x02,
 512         AcceptAllPhys   = 0x01,
 513 #define RX_CONFIG_ACCEPT_MASK           0x3f
 514
 515         /* TxConfigBits */
 516         TxInterFrameGapShift = 24,
 517         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 518
 519         /* Config1 register p.24 */
 520         LEDS1           = (1 << 7),
 521         LEDS0           = (1 << 6),
 522         Speed_down      = (1 << 4),
 523         MEMMAP          = (1 << 3),
 524         IOMAP           = (1 << 2),
 525         VPD             = (1 << 1),
 526         PMEnable        = (1 << 0),     /* Power Management Enable */
 527
 528         /* Config2 register p. 25 */
 529         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 530         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 531         PCI_Clock_66MHz = 0x01,
 532         PCI_Clock_33MHz = 0x00,
 533
 534         /* Config3 register p.25 */
 535         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 536         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 537         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 538         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 539         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 540
 541         /* Config4 register */
 542         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 543
 544         /* Config5 register p.27 */
 545         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 546         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 547         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 548         Spi_en          = (1 << 3),
 549         LanWake         = (1 << 1),     /* LanWake enable/disable */
 550         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 551         ASPM_en         = (1 << 0),     /* ASPM enable */
 552
 553         /* CPlusCmd p.31 */
 554         EnableBist      = (1 << 15),    // 8168 8101
 555         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 556         Normal_mode     = (1 << 13),    // unused
 557         Force_half_dup  = (1 << 12),    // 8168 8101
 558         Force_rxflow_en = (1 << 11),    // 8168 8101
 559         Force_txflow_en = (1 << 10),    // 8168 8101
 560         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 561         ASF             = (1 << 8),     // 8168 8101
 562         PktCntrDisable  = (1 << 7),     // 8168 8101
 563         Mac_dbgo_sel    = 0x001c,       // 8168
 564         RxVlan          = (1 << 6),
 565         RxChkSum        = (1 << 5),
 566         PCIDAC          = (1 << 4),
 567         PCIMulRW        = (1 << 3),
 568 #define INTT_MASK       GENMASK(1, 0)
 569         INTT_0          = 0x0000,       // 8168
 570         INTT_1          = 0x0001,       // 8168
 571         INTT_2          = 0x0002,       // 8168
 572         INTT_3          = 0x0003,       // 8168
 573
 574         /* rtl8169_PHYstatus */
 575         TBI_Enable      = 0x80,
 576         TxFlowCtrl      = 0x40,
 577         RxFlowCtrl      = 0x20,
 578         _1000bpsF       = 0x10,
 579         _100bps         = 0x08,
 580         _10bps          = 0x04,
 581         LinkStatus      = 0x02,
 582         FullDup         = 0x01,
 583
 584         /* _TBICSRBit */
 585         TBILinkOK       = 0x02000000,
 586
 587         /* ResetCounterCommand */
 588         CounterReset    = 0x1,
 589
 590         /* DumpCounterCommand */
 591         CounterDump     = 0x8,
 592
 593         /* magic enable v2 */
 594         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 595 };
 596
 597 enum rtl_desc_bit {
 598         /* First doubleword. */
 599         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 600         RingEnd         = (1 << 30), /* End of descriptor ring */
 601         FirstFrag       = (1 << 29), /* First segment of a packet */
 602         LastFrag        = (1 << 28), /* Final segment of a packet */
 603 };
 604
 605 /* Generic case. */
 606 enum rtl_tx_desc_bit {
 607         /* First doubleword. */
 608         TD_LSO          = (1 << 27),            /* Large Send Offload */
 609 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 610
 611         /* Second doubleword. */
 612         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 613 };
 614
 615 /* 8169, 8168b and 810x except 8102e. */
 616 enum rtl_tx_desc_bit_0 {
 617         /* First doubleword. */
 618 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 619         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 620         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 621         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 622 };
 623
 624 /* 8102e, 8168c and beyond. */
 625 enum rtl_tx_desc_bit_1 {
 626         /* First doubleword. */
 627         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 628         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 629 #define GTTCPHO_SHIFT                   18
 630 #define GTTCPHO_MAX                     0x7fU
 631
 632         /* Second doubleword. */
 633 #define TCPHO_SHIFT                     18
 634 #define TCPHO_MAX                       0x3ffU
 635 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 636         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 637         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 638         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 639         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 640 };
 641
 642 enum rtl_rx_desc_bit {
 643         /* Rx private */
 644         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 645         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 646
 647 #define RxProtoUDP      (PID1)
 648 #define RxProtoTCP      (PID0)
 649 #define RxProtoIP       (PID1 | PID0)
 650 #define RxProtoMask     RxProtoIP
 651
 652         IPFail          = (1 << 16), /* IP checksum failed */
 653         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 654         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 655         RxVlanTag       = (1 << 16), /* VLAN tag available */
 656 };
 657
 658 #define RsvdMask        0x3fffc000
 659 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 660
 661 struct TxDesc {
 662         __le32 opts1;
 663         __le32 opts2;
 664         __le64 addr;
 665 };
 666
 667 struct RxDesc {
 668         __le32 opts1;
 669         __le32 opts2;
 670         __le64 addr;
 671 };
 672
 673 struct ring_info {
 674         struct sk_buff  *skb;
 675         u32             len;
 676         u8              __pad[sizeof(void *) - sizeof(u32)];
 677 };
 678
 679 struct rtl8169_counters {
 680         __le64  tx_packets;
 681         __le64  rx_packets;
 682         __le64  tx_errors;
 683         __le32  rx_errors;
 684         __le16  rx_missed;
 685         __le16  align_errors;
 686         __le32  tx_one_collision;
 687         __le32  tx_multi_collision;
 688         __le64  rx_unicast;
 689         __le64  rx_broadcast;
 690         __le32  rx_multicast;
 691         __le16  tx_aborted;
 692         __le16  tx_underun;
 693 };
 694
 695 struct rtl8169_tc_offsets {
 696         bool    inited;
 697         __le64  tx_errors;
 698         __le32  tx_multi_collision;
 699         __le16  tx_aborted;
 700 };
 701
 702 enum rtl_flag {
 703         RTL_FLAG_TASK_ENABLED,
 704         RTL_FLAG_TASK_SLOW_PENDING,
 705         RTL_FLAG_TASK_RESET_PENDING,
 706         RTL_FLAG_MAX
 707 };
 708
 709 struct rtl8169_stats {
 710         u64                     packets;
 711         u64                     bytes;
 712         struct u64_stats_sync   syncp;
 713 };
 714
 715 struct rtl8169_private {
 716         void __iomem *mmio_addr;        /* memory map physical address */
 717         struct pci_dev *pci_dev;
 718         struct net_device *dev;
 719         struct napi_struct napi;
 720         u32 msg_enable;
 721         u16 mac_version;
 722         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 723         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 724         u32 dirty_tx;
 725         struct rtl8169_stats rx_stats;
 726         struct rtl8169_stats tx_stats;
 727         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 728         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 729         dma_addr_t TxPhyAddr;
 730         dma_addr_t RxPhyAddr;
 731         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 732         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 733         u16 cp_cmd;
 734
 735         u16 event_slow;
 736         const struct rtl_coalesce_info *coalesce_info;
 737
 738         struct mdio_ops {
 739                 void (*write)(struct rtl8169_private *, int, int);
 740                 int (*read)(struct rtl8169_private *, int);
 741         } mdio_ops;
 742
 743         struct jumbo_ops {
 744                 void (*enable)(struct rtl8169_private *);
 745                 void (*disable)(struct rtl8169_private *);
 746         } jumbo_ops;
 747
 748         void (*hw_start)(struct rtl8169_private *tp);
 749         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 750
 751         struct {
 752                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 753                 struct mutex mutex;
 754                 struct work_struct work;
 755         } wk;
 756
 757         struct mii_if_info mii;
 758         struct mii_bus *mii_bus;
 759         dma_addr_t counters_phys_addr;
 760         struct rtl8169_counters *counters;
 761         struct rtl8169_tc_offsets tc_offset;
 762         u32 saved_wolopts;
 763
 764         struct rtl_fw {
 765                 const struct firmware *fw;
 766
 767 #define RTL_VER_SIZE            32
 768
 769                 char version[RTL_VER_SIZE];
 770
 771                 struct rtl_fw_phy_action {
 772                         __le32 *code;
 773                         size_t size;
 774                 } phy_action;
 775         } *rtl_fw;
 776 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 777
 778         u32 ocp_base;
 779 };
 780
 781 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 782 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 783 module_param(use_dac, int, 0);
 784 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 785 module_param_named(debug, debug.msg_enable, int, 0);
 786 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 787 MODULE_LICENSE("GPL");
 788 MODULE_VERSION(RTL8169_VERSION);
 789 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 790 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 791 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 792 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 793 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 794 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 795 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 796 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 797 MODULE_FIRMWARE(FIRMWARE_8402_1);
 798 MODULE_FIRMWARE(FIRMWARE_8411_1);
 799 MODULE_FIRMWARE(FIRMWARE_8411_2);
 800 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 801 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 802 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 803 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 804 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 805 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 806 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 807 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 808
 809 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 810 {
 811         return &tp->pci_dev->dev;
 812 }
 813
 814 static void rtl_lock_work(struct rtl8169_private *tp)
 815 {
 816         mutex_lock(&tp->wk.mutex);
 817 }
 818
 819 static void rtl_unlock_work(struct rtl8169_private *tp)
 820 {
 821         mutex_unlock(&tp->wk.mutex);
 822 }
 823
 824 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 825 {
 826         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 827                                            PCI_EXP_DEVCTL_READRQ, force);
 828 }
 829
 830 struct rtl_cond {
 831         bool (*check)(struct rtl8169_private *);
 832         const char *msg;
 833 };
 834
 835 static void rtl_udelay(unsigned int d)
 836 {
 837         udelay(d);
 838 }
 839
 840 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 841                           void (*delay)(unsigned int), unsigned int d, int n,
 842                           bool high)
 843 {
 844         int i;
 845
 846         for (i = 0; i < n; i++) {
 847                 delay(d);
 848                 if (c->check(tp) == high)
 849                         return true;
 850         }
 851         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 852                   c->msg, !high, n, d);
 853         return false;
 854 }
 855
 856 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 857                                       const struct rtl_cond *c,
 858                                       unsigned int d, int n)
 859 {
 860         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 861 }
 862
 863 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 864                                      const struct rtl_cond *c,
 865                                      unsigned int d, int n)
 866 {
 867         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 868 }
 869
 870 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 871                                       const struct rtl_cond *c,
 872                                       unsigned int d, int n)
 873 {
 874         return rtl_loop_wait(tp, c, msleep, d, n, true);
 875 }
 876
 877 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 878                                      const struct rtl_cond *c,
 879                                      unsigned int d, int n)
 880 {
 881         return rtl_loop_wait(tp, c, msleep, d, n, false);
 882 }
 883
 884 #define DECLARE_RTL_COND(name)                          \
 885 static bool name ## _check(struct rtl8169_private *);   \
 886                                                         \
 887 static const struct rtl_cond name = {                   \
 888         .check  = name ## _check,                       \
 889         .msg    = #name                                 \
 890 };                                                      \
 891                                                         \
 892 static bool name ## _check(struct rtl8169_private *tp)
 893
 894 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 895 {
 896         if (reg & 0xffff0001) {
 897                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 898                 return true;
 899         }
 900         return false;
 901 }
 902
 903 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 904 {
 905         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 906 }
 907
 908 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 909 {
 910         if (rtl_ocp_reg_failure(tp, reg))
 911                 return;
 912
 913         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 914
 915         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 916 }
 917
 918 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 919 {
 920         if (rtl_ocp_reg_failure(tp, reg))
 921                 return 0;
 922
 923         RTL_W32(tp, GPHY_OCP, reg << 15);
 924
 925         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 926                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 927 }
 928
 929 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 930 {
 931         if (rtl_ocp_reg_failure(tp, reg))
 932                 return;
 933
 934         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 935 }
 936
 937 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 938 {
 939         if (rtl_ocp_reg_failure(tp, reg))
 940                 return 0;
 941
 942         RTL_W32(tp, OCPDR, reg << 15);
 943
 944         return RTL_R32(tp, OCPDR);
 945 }
 946
 947 #define OCP_STD_PHY_BASE        0xa400
 948
 949 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 950 {
 951         if (reg == 0x1f) {
 952                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 953                 return;
 954         }
 955
 956         if (tp->ocp_base != OCP_STD_PHY_BASE)
 957                 reg -= 0x10;
 958
 959         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 960 }
 961
 962 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 963 {
 964         if (tp->ocp_base != OCP_STD_PHY_BASE)
 965                 reg -= 0x10;
 966
 967         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 968 }
 969
 970 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 971 {
 972         if (reg == 0x1f) {
 973                 tp->ocp_base = value << 4;
 974                 return;
 975         }
 976
 977         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 978 }
 979
 980 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 981 {
 982         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 983 }
 984
 985 DECLARE_RTL_COND(rtl_phyar_cond)
 986 {
 987         return RTL_R32(tp, PHYAR) & 0x80000000;
 988 }
 989
 990 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 991 {
 992         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 993
 994         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 995         /*
 996          * According to hardware specs a 20us delay is required after write
 997          * complete indication, but before sending next command.
 998          */
 999         udelay(20);
1000 }
1001
1002 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1003 {
1004         int value;
1005
1006         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1007
1008         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1009                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
1010
1011         /*
1012          * According to hardware specs a 20us delay is required after read
1013          * complete indication, but before sending next command.
1014          */
1015         udelay(20);
1016
1017         return value;
1018 }
1019
1020 DECLARE_RTL_COND(rtl_ocpar_cond)
1021 {
1022         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1023 }
1024
1025 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1026 {
1027         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1028         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
1029         RTL_W32(tp, EPHY_RXER_NUM, 0);
1030
1031         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1032 }
1033
1034 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1035 {
1036         r8168dp_1_mdio_access(tp, reg,
1037                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1038 }
1039
1040 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1041 {
1042         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1043
1044         mdelay(1);
1045         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1046         RTL_W32(tp, EPHY_RXER_NUM, 0);
1047
1048         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1049                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
1050 }
1051
1052 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1053
1054 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1055 {
1056         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1057 }
1058
1059 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1060 {
1061         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1062 }
1063
1064 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 {
1066         r8168dp_2_mdio_start(tp);
1067
1068         r8169_mdio_write(tp, reg, value);
1069
1070         r8168dp_2_mdio_stop(tp);
1071 }
1072
1073 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1074 {
1075         int value;
1076
1077         r8168dp_2_mdio_start(tp);
1078
1079         value = r8169_mdio_read(tp, reg);
1080
1081         r8168dp_2_mdio_stop(tp);
1082
1083         return value;
1084 }
1085
1086 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1087 {
1088         tp->mdio_ops.write(tp, location, val);
1089 }
1090
1091 static int rtl_readphy(struct rtl8169_private *tp, int location)
1092 {
1093         return tp->mdio_ops.read(tp, location);
1094 }
1095
1096 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1097 {
1098         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1099 }
1100
1101 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1102 {
1103         int val;
1104
1105         val = rtl_readphy(tp, reg_addr);
1106         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1107 }
1108
1109 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1110                            int val)
1111 {
1112         struct rtl8169_private *tp = netdev_priv(dev);
1113
1114         rtl_writephy(tp, location, val);
1115 }
1116
1117 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1118 {
1119         struct rtl8169_private *tp = netdev_priv(dev);
1120
1121         return rtl_readphy(tp, location);
1122 }
1123
1124 DECLARE_RTL_COND(rtl_ephyar_cond)
1125 {
1126         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1127 }
1128
1129 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1130 {
1131         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1132                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1133
1134         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1135
1136         udelay(10);
1137 }
1138
1139 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1140 {
1141         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1142
1143         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1144                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1145 }
1146
1147 DECLARE_RTL_COND(rtl_eriar_cond)
1148 {
1149         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1150 }
1151
1152 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1153                           u32 val, int type)
1154 {
1155         BUG_ON((addr & 3) || (mask == 0));
1156         RTL_W32(tp, ERIDR, val);
1157         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1158
1159         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1160 }
1161
1162 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1163 {
1164         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1165
1166         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1167                 RTL_R32(tp, ERIDR) : ~0;
1168 }
1169
1170 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1171                          u32 m, int type)
1172 {
1173         u32 val;
1174
1175         val = rtl_eri_read(tp, addr, type);
1176         rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1177 }
1178
1179 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1180 {
1181         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1182         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1183                 RTL_R32(tp, OCPDR) : ~0;
1184 }
1185
1186 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1187 {
1188         return rtl_eri_read(tp, reg, ERIAR_OOB);
1189 }
1190
1191 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1192 {
1193         switch (tp->mac_version) {
1194         case RTL_GIGA_MAC_VER_27:
1195         case RTL_GIGA_MAC_VER_28:
1196         case RTL_GIGA_MAC_VER_31:
1197                 return r8168dp_ocp_read(tp, mask, reg);
1198         case RTL_GIGA_MAC_VER_49:
1199         case RTL_GIGA_MAC_VER_50:
1200         case RTL_GIGA_MAC_VER_51:
1201                 return r8168ep_ocp_read(tp, mask, reg);
1202         default:
1203                 BUG();
1204                 return ~0;
1205         }
1206 }
1207
1208 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1209                               u32 data)
1210 {
1211         RTL_W32(tp, OCPDR, data);
1212         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1213         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1214 }
1215
1216 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1217                               u32 data)
1218 {
1219         rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1220                       data, ERIAR_OOB);
1221 }
1222
1223 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1224 {
1225         switch (tp->mac_version) {
1226         case RTL_GIGA_MAC_VER_27:
1227         case RTL_GIGA_MAC_VER_28:
1228         case RTL_GIGA_MAC_VER_31:
1229                 r8168dp_ocp_write(tp, mask, reg, data);
1230                 break;
1231         case RTL_GIGA_MAC_VER_49:
1232         case RTL_GIGA_MAC_VER_50:
1233         case RTL_GIGA_MAC_VER_51:
1234                 r8168ep_ocp_write(tp, mask, reg, data);
1235                 break;
1236         default:
1237                 BUG();
1238                 break;
1239         }
1240 }
1241
1242 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1243 {
1244         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1245
1246         ocp_write(tp, 0x1, 0x30, 0x00000001);
1247 }
1248
1249 #define OOB_CMD_RESET           0x00
1250 #define OOB_CMD_DRIVER_START    0x05
1251 #define OOB_CMD_DRIVER_STOP     0x06
1252
1253 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1254 {
1255         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1256 }
1257
1258 DECLARE_RTL_COND(rtl_ocp_read_cond)
1259 {
1260         u16 reg;
1261
1262         reg = rtl8168_get_ocp_reg(tp);
1263
1264         return ocp_read(tp, 0x0f, reg) & 0x00000800;
1265 }
1266
1267 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1268 {
1269         return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1270 }
1271
1272 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1273 {
1274         return RTL_R8(tp, IBISR0) & 0x20;
1275 }
1276
1277 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1278 {
1279         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1280         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1281         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1282         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1283 }
1284
1285 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1286 {
1287         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1288         rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1289 }
1290
1291 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1292 {
1293         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1294         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1295         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1296 }
1297
1298 static void rtl8168_driver_start(struct rtl8169_private *tp)
1299 {
1300         switch (tp->mac_version) {
1301         case RTL_GIGA_MAC_VER_27:
1302         case RTL_GIGA_MAC_VER_28:
1303         case RTL_GIGA_MAC_VER_31:
1304                 rtl8168dp_driver_start(tp);
1305                 break;
1306         case RTL_GIGA_MAC_VER_49:
1307         case RTL_GIGA_MAC_VER_50:
1308         case RTL_GIGA_MAC_VER_51:
1309                 rtl8168ep_driver_start(tp);
1310                 break;
1311         default:
1312                 BUG();
1313                 break;
1314         }
1315 }
1316
1317 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1318 {
1319         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1320         rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1321 }
1322
1323 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1324 {
1325         rtl8168ep_stop_cmac(tp);
1326         ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1327         ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1328         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1329 }
1330
1331 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1332 {
1333         switch (tp->mac_version) {
1334         case RTL_GIGA_MAC_VER_27:
1335         case RTL_GIGA_MAC_VER_28:
1336         case RTL_GIGA_MAC_VER_31:
1337                 rtl8168dp_driver_stop(tp);
1338                 break;
1339         case RTL_GIGA_MAC_VER_49:
1340         case RTL_GIGA_MAC_VER_50:
1341         case RTL_GIGA_MAC_VER_51:
1342                 rtl8168ep_driver_stop(tp);
1343                 break;
1344         default:
1345                 BUG();
1346                 break;
1347         }
1348 }
1349
1350 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1351 {
1352         u16 reg = rtl8168_get_ocp_reg(tp);
1353
1354         return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1355 }
1356
1357 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1358 {
1359         return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1360 }
1361
1362 static bool r8168_check_dash(struct rtl8169_private *tp)
1363 {
1364         switch (tp->mac_version) {
1365         case RTL_GIGA_MAC_VER_27:
1366         case RTL_GIGA_MAC_VER_28:
1367         case RTL_GIGA_MAC_VER_31:
1368                 return r8168dp_check_dash(tp);
1369         case RTL_GIGA_MAC_VER_49:
1370         case RTL_GIGA_MAC_VER_50:
1371         case RTL_GIGA_MAC_VER_51:
1372                 return r8168ep_check_dash(tp);
1373         default:
1374                 return false;
1375         }
1376 }
1377
1378 struct exgmac_reg {
1379         u16 addr;
1380         u16 mask;
1381         u32 val;
1382 };
1383
1384 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1385                                    const struct exgmac_reg *r, int len)
1386 {
1387         while (len-- > 0) {
1388                 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1389                 r++;
1390         }
1391 }
1392
1393 DECLARE_RTL_COND(rtl_efusear_cond)
1394 {
1395         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1396 }
1397
1398 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1399 {
1400         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1401
1402         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1403                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1404 }
1405
1406 static u16 rtl_get_events(struct rtl8169_private *tp)
1407 {
1408         return RTL_R16(tp, IntrStatus);
1409 }
1410
1411 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1412 {
1413         RTL_W16(tp, IntrStatus, bits);
1414         mmiowb();
1415 }
1416
1417 static void rtl_irq_disable(struct rtl8169_private *tp)
1418 {
1419         RTL_W16(tp, IntrMask, 0);
1420         mmiowb();
1421 }
1422
1423 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1424 {
1425         RTL_W16(tp, IntrMask, bits);
1426 }
1427
1428 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1429 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1430 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1431
1432 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1433 {
1434         rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1435 }
1436
1437 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1438 {
1439         rtl_irq_disable(tp);
1440         rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1441         RTL_R8(tp, ChipCmd);
1442 }
1443
1444 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1445 {
1446         struct net_device *dev = tp->dev;
1447
1448         if (!netif_running(dev))
1449                 return;
1450
1451         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1452             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1453                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1454                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1455                                       ERIAR_EXGMAC);
1456                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1457                                       ERIAR_EXGMAC);
1458                 } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1459                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1460                                       ERIAR_EXGMAC);
1461                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1462                                       ERIAR_EXGMAC);
1463                 } else {
1464                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1465                                       ERIAR_EXGMAC);
1466                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1467                                       ERIAR_EXGMAC);
1468                 }
1469                 /* Reset packet filter */
1470                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1471                              ERIAR_EXGMAC);
1472                 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1473                              ERIAR_EXGMAC);
1474         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1475                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1476                 if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1477                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1478                                       ERIAR_EXGMAC);
1479                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1480                                       ERIAR_EXGMAC);
1481                 } else {
1482                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1483                                       ERIAR_EXGMAC);
1484                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1485                                       ERIAR_EXGMAC);
1486                 }
1487         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1488                 if (RTL_R8(tp, PHYstatus) & _10bps) {
1489                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1490                                       ERIAR_EXGMAC);
1491                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1492                                       ERIAR_EXGMAC);
1493                 } else {
1494                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1495                                       ERIAR_EXGMAC);
1496                 }
1497         }
1498 }
1499
1500 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1501
1502 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1503 {
1504         u8 options;
1505         u32 wolopts = 0;
1506
1507         options = RTL_R8(tp, Config1);
1508         if (!(options & PMEnable))
1509                 return 0;
1510
1511         options = RTL_R8(tp, Config3);
1512         if (options & LinkUp)
1513                 wolopts |= WAKE_PHY;
1514         switch (tp->mac_version) {
1515         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1516         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1517                 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1518                         wolopts |= WAKE_MAGIC;
1519                 break;
1520         default:
1521                 if (options & MagicPacket)
1522                         wolopts |= WAKE_MAGIC;
1523                 break;
1524         }
1525
1526         options = RTL_R8(tp, Config5);
1527         if (options & UWF)
1528                 wolopts |= WAKE_UCAST;
1529         if (options & BWF)
1530                 wolopts |= WAKE_BCAST;
1531         if (options & MWF)
1532                 wolopts |= WAKE_MCAST;
1533
1534         return wolopts;
1535 }
1536
1537 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1538 {
1539         struct rtl8169_private *tp = netdev_priv(dev);
1540
1541         rtl_lock_work(tp);
1542         wol->supported = WAKE_ANY;
1543         wol->wolopts = tp->saved_wolopts;
1544         rtl_unlock_work(tp);
1545 }
1546
1547 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1548 {
1549         unsigned int i, tmp;
1550         static const struct {
1551                 u32 opt;
1552                 u16 reg;
1553                 u8  mask;
1554         } cfg[] = {
1555                 { WAKE_PHY,   Config3, LinkUp },
1556                 { WAKE_UCAST, Config5, UWF },
1557                 { WAKE_BCAST, Config5, BWF },
1558                 { WAKE_MCAST, Config5, MWF },
1559                 { WAKE_ANY,   Config5, LanWake },
1560                 { WAKE_MAGIC, Config3, MagicPacket }
1561         };
1562         u8 options;
1563
1564         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1565
1566         switch (tp->mac_version) {
1567         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1568         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1569                 tmp = ARRAY_SIZE(cfg) - 1;
1570                 if (wolopts & WAKE_MAGIC)
1571                         rtl_w0w1_eri(tp,
1572                                      0x0dc,
1573                                      ERIAR_MASK_0100,
1574                                      MagicPacket_v2,
1575                                      0x0000,
1576                                      ERIAR_EXGMAC);
1577                 else
1578                         rtl_w0w1_eri(tp,
1579                                      0x0dc,
1580                                      ERIAR_MASK_0100,
1581                                      0x0000,
1582                                      MagicPacket_v2,
1583                                      ERIAR_EXGMAC);
1584                 break;
1585         default:
1586                 tmp = ARRAY_SIZE(cfg);
1587                 break;
1588         }
1589
1590         for (i = 0; i < tmp; i++) {
1591                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1592                 if (wolopts & cfg[i].opt)
1593                         options |= cfg[i].mask;
1594                 RTL_W8(tp, cfg[i].reg, options);
1595         }
1596
1597         switch (tp->mac_version) {
1598         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1599                 options = RTL_R8(tp, Config1) & ~PMEnable;
1600                 if (wolopts)
1601                         options |= PMEnable;
1602                 RTL_W8(tp, Config1, options);
1603                 break;
1604         default:
1605                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1606                 if (wolopts)
1607                         options |= PME_SIGNAL;
1608                 RTL_W8(tp, Config2, options);
1609                 break;
1610         }
1611
1612         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1613 }
1614
1615 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1616 {
1617         struct rtl8169_private *tp = netdev_priv(dev);
1618         struct device *d = tp_to_dev(tp);
1619
1620         if (wol->wolopts & ~WAKE_ANY)
1621                 return -EINVAL;
1622
1623         pm_runtime_get_noresume(d);
1624
1625         rtl_lock_work(tp);
1626
1627         tp->saved_wolopts = wol->wolopts;
1628
1629         if (pm_runtime_active(d))
1630                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1631
1632         rtl_unlock_work(tp);
1633
1634         device_set_wakeup_enable(d, tp->saved_wolopts);
1635
1636         pm_runtime_put_noidle(d);
1637
1638         return 0;
1639 }
1640
1641 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1642 {
1643         return rtl_chip_infos[tp->mac_version].fw_name;
1644 }
1645
1646 static void rtl8169_get_drvinfo(struct net_device *dev,
1647                                 struct ethtool_drvinfo *info)
1648 {
1649         struct rtl8169_private *tp = netdev_priv(dev);
1650         struct rtl_fw *rtl_fw = tp->rtl_fw;
1651
1652         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1653         strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1654         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1655         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1656         if (!IS_ERR_OR_NULL(rtl_fw))
1657                 strlcpy(info->fw_version, rtl_fw->version,
1658                         sizeof(info->fw_version));
1659 }
1660
1661 static int rtl8169_get_regs_len(struct net_device *dev)
1662 {
1663         return R8169_REGS_SIZE;
1664 }
1665
1666 static int rtl8169_set_speed_xmii(struct net_device *dev,
1667                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1668 {
1669         struct rtl8169_private *tp = netdev_priv(dev);
1670         int giga_ctrl, bmcr;
1671         int rc = -EINVAL;
1672
1673         rtl_writephy(tp, 0x1f, 0x0000);
1674
1675         if (autoneg == AUTONEG_ENABLE) {
1676                 int auto_nego;
1677
1678                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1679                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1680                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1681
1682                 if (adv & ADVERTISED_10baseT_Half)
1683                         auto_nego |= ADVERTISE_10HALF;
1684                 if (adv & ADVERTISED_10baseT_Full)
1685                         auto_nego |= ADVERTISE_10FULL;
1686                 if (adv & ADVERTISED_100baseT_Half)
1687                         auto_nego |= ADVERTISE_100HALF;
1688                 if (adv & ADVERTISED_100baseT_Full)
1689                         auto_nego |= ADVERTISE_100FULL;
1690
1691                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1692
1693                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1694                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1695
1696                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1697                 if (tp->mii.supports_gmii) {
1698                         if (adv & ADVERTISED_1000baseT_Half)
1699                                 giga_ctrl |= ADVERTISE_1000HALF;
1700                         if (adv & ADVERTISED_1000baseT_Full)
1701                                 giga_ctrl |= ADVERTISE_1000FULL;
1702                 } else if (adv & (ADVERTISED_1000baseT_Half |
1703                                   ADVERTISED_1000baseT_Full)) {
1704                         netif_info(tp, link, dev,
1705                                    "PHY does not support 1000Mbps\n");
1706                         goto out;
1707                 }
1708
1709                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1710
1711                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1712                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1713         } else {
1714                 if (speed == SPEED_10)
1715                         bmcr = 0;
1716                 else if (speed == SPEED_100)
1717                         bmcr = BMCR_SPEED100;
1718                 else
1719                         goto out;
1720
1721                 if (duplex == DUPLEX_FULL)
1722                         bmcr |= BMCR_FULLDPLX;
1723         }
1724
1725         rtl_writephy(tp, MII_BMCR, bmcr);
1726
1727         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1728             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1729                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1730                         rtl_writephy(tp, 0x17, 0x2138);
1731                         rtl_writephy(tp, 0x0e, 0x0260);
1732                 } else {
1733                         rtl_writephy(tp, 0x17, 0x2108);
1734                         rtl_writephy(tp, 0x0e, 0x0000);
1735                 }
1736         }
1737
1738         rc = 0;
1739 out:
1740         return rc;
1741 }
1742
1743 static int rtl8169_set_speed(struct net_device *dev,
1744                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1745 {
1746         return rtl8169_set_speed_xmii(dev, autoneg, speed, duplex, advertising);
1747 }
1748
1749 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1750         netdev_features_t features)
1751 {
1752         struct rtl8169_private *tp = netdev_priv(dev);
1753
1754         if (dev->mtu > TD_MSS_MAX)
1755                 features &= ~NETIF_F_ALL_TSO;
1756
1757         if (dev->mtu > JUMBO_1K &&
1758             tp->mac_version > RTL_GIGA_MAC_VER_06)
1759                 features &= ~NETIF_F_IP_CSUM;
1760
1761         return features;
1762 }
1763
1764 static int rtl8169_set_features(struct net_device *dev,
1765                                 netdev_features_t features)
1766 {
1767         struct rtl8169_private *tp = netdev_priv(dev);
1768         u32 rx_config;
1769
1770         rtl_lock_work(tp);
1771
1772         rx_config = RTL_R32(tp, RxConfig);
1773         if (features & NETIF_F_RXALL)
1774                 rx_config |= (AcceptErr | AcceptRunt);
1775         else
1776                 rx_config &= ~(AcceptErr | AcceptRunt);
1777
1778         RTL_W32(tp, RxConfig, rx_config);
1779
1780         if (features & NETIF_F_RXCSUM)
1781                 tp->cp_cmd |= RxChkSum;
1782         else
1783                 tp->cp_cmd &= ~RxChkSum;
1784
1785         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1786                 tp->cp_cmd |= RxVlan;
1787         else
1788                 tp->cp_cmd &= ~RxVlan;
1789
1790         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1791         RTL_R16(tp, CPlusCmd);
1792
1793         rtl_unlock_work(tp);
1794
1795         return 0;
1796 }
1797
1798 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1799 {
1800         return (skb_vlan_tag_present(skb)) ?
1801                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1802 }
1803
1804 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1805 {
1806         u32 opts2 = le32_to_cpu(desc->opts2);
1807
1808         if (opts2 & RxVlanTag)
1809                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1810 }
1811
1812 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1813                              void *p)
1814 {
1815         struct rtl8169_private *tp = netdev_priv(dev);
1816         u32 __iomem *data = tp->mmio_addr;
1817         u32 *dw = p;
1818         int i;
1819
1820         rtl_lock_work(tp);
1821         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1822                 memcpy_fromio(dw++, data++, 4);
1823         rtl_unlock_work(tp);
1824 }
1825
1826 static u32 rtl8169_get_msglevel(struct net_device *dev)
1827 {
1828         struct rtl8169_private *tp = netdev_priv(dev);
1829
1830         return tp->msg_enable;
1831 }
1832
1833 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1834 {
1835         struct rtl8169_private *tp = netdev_priv(dev);
1836
1837         tp->msg_enable = value;
1838 }
1839
1840 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1841         "tx_packets",
1842         "rx_packets",
1843         "tx_errors",
1844         "rx_errors",
1845         "rx_missed",
1846         "align_errors",
1847         "tx_single_collisions",
1848         "tx_multi_collisions",
1849         "unicast",
1850         "broadcast",
1851         "multicast",
1852         "tx_aborted",
1853         "tx_underrun",
1854 };
1855
1856 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1857 {
1858         switch (sset) {
1859         case ETH_SS_STATS:
1860                 return ARRAY_SIZE(rtl8169_gstrings);
1861         default:
1862                 return -EOPNOTSUPP;
1863         }
1864 }
1865
1866 DECLARE_RTL_COND(rtl_counters_cond)
1867 {
1868         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1869 }
1870
1871 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1872 {
1873         dma_addr_t paddr = tp->counters_phys_addr;
1874         u32 cmd;
1875
1876         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1877         RTL_R32(tp, CounterAddrHigh);
1878         cmd = (u64)paddr & DMA_BIT_MASK(32);
1879         RTL_W32(tp, CounterAddrLow, cmd);
1880         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1881
1882         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1883 }
1884
1885 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1886 {
1887         /*
1888          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1889          * tally counters.
1890          */
1891         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1892                 return true;
1893
1894         return rtl8169_do_counters(tp, CounterReset);
1895 }
1896
1897 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1898 {
1899         /*
1900          * Some chips are unable to dump tally counters when the receiver
1901          * is disabled.
1902          */
1903         if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1904                 return true;
1905
1906         return rtl8169_do_counters(tp, CounterDump);
1907 }
1908
1909 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1910 {
1911         struct rtl8169_counters *counters = tp->counters;
1912         bool ret = false;
1913
1914         /*
1915          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1916          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1917          * reset by a power cycle, while the counter values collected by the
1918          * driver are reset at every driver unload/load cycle.
1919          *
1920          * To make sure the HW values returned by @get_stats64 match the SW
1921          * values, we collect the initial values at first open(*) and use them
1922          * as offsets to normalize the values returned by @get_stats64.
1923          *
1924          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1925          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1926          * set at open time by rtl_hw_start.
1927          */
1928
1929         if (tp->tc_offset.inited)
1930                 return true;
1931
1932         /* If both, reset and update fail, propagate to caller. */
1933         if (rtl8169_reset_counters(tp))
1934                 ret = true;
1935
1936         if (rtl8169_update_counters(tp))
1937                 ret = true;
1938
1939         tp->tc_offset.tx_errors = counters->tx_errors;
1940         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1941         tp->tc_offset.tx_aborted = counters->tx_aborted;
1942         tp->tc_offset.inited = true;
1943
1944         return ret;
1945 }
1946
1947 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1948                                       struct ethtool_stats *stats, u64 *data)
1949 {
1950         struct rtl8169_private *tp = netdev_priv(dev);
1951         struct device *d = tp_to_dev(tp);
1952         struct rtl8169_counters *counters = tp->counters;
1953
1954         ASSERT_RTNL();
1955
1956         pm_runtime_get_noresume(d);
1957
1958         if (pm_runtime_active(d))
1959                 rtl8169_update_counters(tp);
1960
1961         pm_runtime_put_noidle(d);
1962
1963         data[0] = le64_to_cpu(counters->tx_packets);
1964         data[1] = le64_to_cpu(counters->rx_packets);
1965         data[2] = le64_to_cpu(counters->tx_errors);
1966         data[3] = le32_to_cpu(counters->rx_errors);
1967         data[4] = le16_to_cpu(counters->rx_missed);
1968         data[5] = le16_to_cpu(counters->align_errors);
1969         data[6] = le32_to_cpu(counters->tx_one_collision);
1970         data[7] = le32_to_cpu(counters->tx_multi_collision);
1971         data[8] = le64_to_cpu(counters->rx_unicast);
1972         data[9] = le64_to_cpu(counters->rx_broadcast);
1973         data[10] = le32_to_cpu(counters->rx_multicast);
1974         data[11] = le16_to_cpu(counters->tx_aborted);
1975         data[12] = le16_to_cpu(counters->tx_underun);
1976 }
1977
1978 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1979 {
1980         switch(stringset) {
1981         case ETH_SS_STATS:
1982                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1983                 break;
1984         }
1985 }
1986
1987 /*
1988  * Interrupt coalescing
1989  *
1990  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1991  * >     8169, 8168 and 810x line of chipsets
1992  *
1993  * 8169, 8168, and 8136(810x) serial chipsets support it.
1994  *
1995  * > 2 - the Tx timer unit at gigabit speed
1996  *
1997  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1998  * (0xe0) bit 1 and bit 0.
1999  *
2000  * For 8169
2001  * bit[1:0] \ speed        1000M           100M            10M
2002  * 0 0                     320ns           2.56us          40.96us
2003  * 0 1                     2.56us          20.48us         327.7us
2004  * 1 0                     5.12us          40.96us         655.4us
2005  * 1 1                     10.24us         81.92us         1.31ms
2006  *
2007  * For the other
2008  * bit[1:0] \ speed        1000M           100M            10M
2009  * 0 0                     5us             2.56us          40.96us
2010  * 0 1                     40us            20.48us         327.7us
2011  * 1 0                     80us            40.96us         655.4us
2012  * 1 1                     160us           81.92us         1.31ms
2013  */
2014
2015 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2016 struct rtl_coalesce_scale {
2017         /* Rx / Tx */
2018         u32 nsecs[2];
2019 };
2020
2021 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2022 struct rtl_coalesce_info {
2023         u32 speed;
2024         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
2025 };
2026
2027 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2028 #define rxtx_x1822(r, t) {              \
2029         {{(r),          (t)}},          \
2030         {{(r)*8,        (t)*8}},        \
2031         {{(r)*8*2,      (t)*8*2}},      \
2032         {{(r)*8*2*2,    (t)*8*2*2}},    \
2033 }
2034 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2035         /* speed        delays:     rx00   tx00 */
2036         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2037         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2038         { SPEED_1000,   rxtx_x1822(  320,   320)        },
2039         { 0 },
2040 };
2041
2042 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2043         /* speed        delays:     rx00   tx00 */
2044         { SPEED_10,     rxtx_x1822(40960, 40960)        },
2045         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
2046         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
2047         { 0 },
2048 };
2049 #undef rxtx_x1822
2050
2051 /* get rx/tx scale vector corresponding to current speed */
2052 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2053 {
2054         struct rtl8169_private *tp = netdev_priv(dev);
2055         struct ethtool_link_ksettings ecmd;
2056         const struct rtl_coalesce_info *ci;
2057         int rc;
2058
2059         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
2060         if (rc < 0)
2061                 return ERR_PTR(rc);
2062
2063         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2064                 if (ecmd.base.speed == ci->speed) {
2065                         return ci;
2066                 }
2067         }
2068
2069         return ERR_PTR(-ELNRNG);
2070 }
2071
2072 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2073 {
2074         struct rtl8169_private *tp = netdev_priv(dev);
2075         const struct rtl_coalesce_info *ci;
2076         const struct rtl_coalesce_scale *scale;
2077         struct {
2078                 u32 *max_frames;
2079                 u32 *usecs;
2080         } coal_settings [] = {
2081                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2082                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2083         }, *p = coal_settings;
2084         int i;
2085         u16 w;
2086
2087         memset(ec, 0, sizeof(*ec));
2088
2089         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2090         ci = rtl_coalesce_info(dev);
2091         if (IS_ERR(ci))
2092                 return PTR_ERR(ci);
2093
2094         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
2095
2096         /* read IntrMitigate and adjust according to scale */
2097         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2098                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2099                 w >>= RTL_COALESCE_SHIFT;
2100                 *p->usecs = w & RTL_COALESCE_MASK;
2101         }
2102
2103         for (i = 0; i < 2; i++) {
2104                 p = coal_settings + i;
2105                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2106
2107                 /*
2108                  * ethtool_coalesce says it is illegal to set both usecs and
2109                  * max_frames to 0.
2110                  */
2111                 if (!*p->usecs && !*p->max_frames)
2112                         *p->max_frames = 1;
2113         }
2114
2115         return 0;
2116 }
2117
2118 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2119 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2120                         struct net_device *dev, u32 nsec, u16 *cp01)
2121 {
2122         const struct rtl_coalesce_info *ci;
2123         u16 i;
2124
2125         ci = rtl_coalesce_info(dev);
2126         if (IS_ERR(ci))
2127                 return ERR_CAST(ci);
2128
2129         for (i = 0; i < 4; i++) {
2130                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2131                                         ci->scalev[i].nsecs[1]);
2132                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2133                         *cp01 = i;
2134                         return &ci->scalev[i];
2135                 }
2136         }
2137
2138         return ERR_PTR(-EINVAL);
2139 }
2140
2141 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2142 {
2143         struct rtl8169_private *tp = netdev_priv(dev);
2144         const struct rtl_coalesce_scale *scale;
2145         struct {
2146                 u32 frames;
2147                 u32 usecs;
2148         } coal_settings [] = {
2149                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2150                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2151         }, *p = coal_settings;
2152         u16 w = 0, cp01;
2153         int i;
2154
2155         scale = rtl_coalesce_choose_scale(dev,
2156                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2157         if (IS_ERR(scale))
2158                 return PTR_ERR(scale);
2159
2160         for (i = 0; i < 2; i++, p++) {
2161                 u32 units;
2162
2163                 /*
2164                  * accept max_frames=1 we returned in rtl_get_coalesce.
2165                  * accept it not only when usecs=0 because of e.g. the following scenario:
2166                  *
2167                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2168                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2169                  * - then user does `ethtool -C eth0 rx-usecs 100`
2170                  *
2171                  * since ethtool sends to kernel whole ethtool_coalesce
2172                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2173                  * we'll reject it below in `frames % 4 != 0`.
2174                  */
2175                 if (p->frames == 1) {
2176                         p->frames = 0;
2177                 }
2178
2179                 units = p->usecs * 1000 / scale->nsecs[i];
2180                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2181                         return -EINVAL;
2182
2183                 w <<= RTL_COALESCE_SHIFT;
2184                 w |= units;
2185                 w <<= RTL_COALESCE_SHIFT;
2186                 w |= p->frames >> 2;
2187         }
2188
2189         rtl_lock_work(tp);
2190
2191         RTL_W16(tp, IntrMitigate, swab16(w));
2192
2193         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2194         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2195         RTL_R16(tp, CPlusCmd);
2196
2197         rtl_unlock_work(tp);
2198
2199         return 0;
2200 }
2201
2202 static const struct ethtool_ops rtl8169_ethtool_ops = {
2203         .get_drvinfo            = rtl8169_get_drvinfo,
2204         .get_regs_len           = rtl8169_get_regs_len,
2205         .get_link               = ethtool_op_get_link,
2206         .get_coalesce           = rtl_get_coalesce,
2207         .set_coalesce           = rtl_set_coalesce,
2208         .get_msglevel           = rtl8169_get_msglevel,
2209         .set_msglevel           = rtl8169_set_msglevel,
2210         .get_regs               = rtl8169_get_regs,
2211         .get_wol                = rtl8169_get_wol,
2212         .set_wol                = rtl8169_set_wol,
2213         .get_strings            = rtl8169_get_strings,
2214         .get_sset_count         = rtl8169_get_sset_count,
2215         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2216         .get_ts_info            = ethtool_op_get_ts_info,
2217         .nway_reset             = phy_ethtool_nway_reset,
2218         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2219         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2220 };
2221
2222 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2223                                     u8 default_version)
2224 {
2225         /*
2226          * The driver currently handles the 8168Bf and the 8168Be identically
2227          * but they can be identified more specifically through the test below
2228          * if needed:
2229          *
2230          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2231          *
2232          * Same thing for the 8101Eb and the 8101Ec:
2233          *
2234          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2235          */
2236         static const struct rtl_mac_info {
2237                 u32 mask;
2238                 u32 val;
2239                 int mac_version;
2240         } mac_info[] = {
2241                 /* 8168EP family. */
2242                 { 0x7cf00000, 0x50200000,       RTL_GIGA_MAC_VER_51 },
2243                 { 0x7cf00000, 0x50100000,       RTL_GIGA_MAC_VER_50 },
2244                 { 0x7cf00000, 0x50000000,       RTL_GIGA_MAC_VER_49 },
2245
2246                 /* 8168H family. */
2247                 { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
2248                 { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
2249
2250                 /* 8168G family. */
2251                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
2252                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
2253                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
2254                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
2255
2256                 /* 8168F family. */
2257                 { 0x7c800000, 0x48800000,       RTL_GIGA_MAC_VER_38 },
2258                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
2259                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
2260
2261                 /* 8168E family. */
2262                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
2263                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
2264                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
2265
2266                 /* 8168D family. */
2267                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
2268                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
2269
2270                 /* 8168DP family. */
2271                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
2272                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
2273                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
2274
2275                 /* 8168C family. */
2276                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
2277                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
2278                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
2279                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
2280                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
2281                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
2282                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
2283
2284                 /* 8168B family. */
2285                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
2286                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
2287                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
2288
2289                 /* 8101 family. */
2290                 { 0x7c800000, 0x44800000,       RTL_GIGA_MAC_VER_39 },
2291                 { 0x7c800000, 0x44000000,       RTL_GIGA_MAC_VER_37 },
2292                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
2293                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
2294                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
2295                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
2296                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
2297                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
2298                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
2299                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
2300                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
2301                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
2302                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
2303                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
2304                 /* FIXME: where did these entries come from ? -- FR */
2305                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
2306                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
2307
2308                 /* 8110 family. */
2309                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
2310                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
2311                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
2312                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
2313                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
2314                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
2315
2316                 /* Catch-all */
2317                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
2318         };
2319         const struct rtl_mac_info *p = mac_info;
2320         u32 reg;
2321
2322         reg = RTL_R32(tp, TxConfig);
2323         while ((reg & p->mask) != p->val)
2324                 p++;
2325         tp->mac_version = p->mac_version;
2326
2327         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2328                 dev_notice(tp_to_dev(tp),
2329                            "unknown MAC, using family default\n");
2330                 tp->mac_version = default_version;
2331         } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2332                 tp->mac_version = tp->mii.supports_gmii ?
2333                                   RTL_GIGA_MAC_VER_42 :
2334                                   RTL_GIGA_MAC_VER_43;
2335         } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2336                 tp->mac_version = tp->mii.supports_gmii ?
2337                                   RTL_GIGA_MAC_VER_45 :
2338                                   RTL_GIGA_MAC_VER_47;
2339         } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2340                 tp->mac_version = tp->mii.supports_gmii ?
2341                                   RTL_GIGA_MAC_VER_46 :
2342                                   RTL_GIGA_MAC_VER_48;
2343         }
2344 }
2345
2346 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2347 {
2348         netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2349 }
2350
2351 struct phy_reg {
2352         u16 reg;
2353         u16 val;
2354 };
2355
2356 static void rtl_writephy_batch(struct rtl8169_private *tp,
2357                                const struct phy_reg *regs, int len)
2358 {
2359         while (len-- > 0) {
2360                 rtl_writephy(tp, regs->reg, regs->val);
2361                 regs++;
2362         }
2363 }
2364
2365 #define PHY_READ                0x00000000
2366 #define PHY_DATA_OR             0x10000000
2367 #define PHY_DATA_AND            0x20000000
2368 #define PHY_BJMPN               0x30000000
2369 #define PHY_MDIO_CHG            0x40000000
2370 #define PHY_CLEAR_READCOUNT     0x70000000
2371 #define PHY_WRITE               0x80000000
2372 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2373 #define PHY_COMP_EQ_SKIPN       0xa0000000
2374 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2375 #define PHY_WRITE_PREVIOUS      0xc0000000
2376 #define PHY_SKIPN               0xd0000000
2377 #define PHY_DELAY_MS            0xe0000000
2378
2379 struct fw_info {
2380         u32     magic;
2381         char    version[RTL_VER_SIZE];
2382         __le32  fw_start;
2383         __le32  fw_len;
2384         u8      chksum;
2385 } __packed;
2386
2387 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2388
2389 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2390 {
2391         const struct firmware *fw = rtl_fw->fw;
2392         struct fw_info *fw_info = (struct fw_info *)fw->data;
2393         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2394         char *version = rtl_fw->version;
2395         bool rc = false;
2396
2397         if (fw->size < FW_OPCODE_SIZE)
2398                 goto out;
2399
2400         if (!fw_info->magic) {
2401                 size_t i, size, start;
2402                 u8 checksum = 0;
2403
2404                 if (fw->size < sizeof(*fw_info))
2405                         goto out;
2406
2407                 for (i = 0; i < fw->size; i++)
2408                         checksum += fw->data[i];
2409                 if (checksum != 0)
2410                         goto out;
2411
2412                 start = le32_to_cpu(fw_info->fw_start);
2413                 if (start > fw->size)
2414                         goto out;
2415
2416                 size = le32_to_cpu(fw_info->fw_len);
2417                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2418                         goto out;
2419
2420                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2421
2422                 pa->code = (__le32 *)(fw->data + start);
2423                 pa->size = size;
2424         } else {
2425                 if (fw->size % FW_OPCODE_SIZE)
2426                         goto out;
2427
2428                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2429
2430                 pa->code = (__le32 *)fw->data;
2431                 pa->size = fw->size / FW_OPCODE_SIZE;
2432         }
2433         version[RTL_VER_SIZE - 1] = 0;
2434
2435         rc = true;
2436 out:
2437         return rc;
2438 }
2439
2440 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2441                            struct rtl_fw_phy_action *pa)
2442 {
2443         bool rc = false;
2444         size_t index;
2445
2446         for (index = 0; index < pa->size; index++) {
2447                 u32 action = le32_to_cpu(pa->code[index]);
2448                 u32 regno = (action & 0x0fff0000) >> 16;
2449
2450                 switch(action & 0xf0000000) {
2451                 case PHY_READ:
2452                 case PHY_DATA_OR:
2453                 case PHY_DATA_AND:
2454                 case PHY_MDIO_CHG:
2455                 case PHY_CLEAR_READCOUNT:
2456                 case PHY_WRITE:
2457                 case PHY_WRITE_PREVIOUS:
2458                 case PHY_DELAY_MS:
2459                         break;
2460
2461                 case PHY_BJMPN:
2462                         if (regno > index) {
2463                                 netif_err(tp, ifup, tp->dev,
2464                                           "Out of range of firmware\n");
2465                                 goto out;
2466                         }
2467                         break;
2468                 case PHY_READCOUNT_EQ_SKIP:
2469                         if (index + 2 >= pa->size) {
2470                                 netif_err(tp, ifup, tp->dev,
2471                                           "Out of range of firmware\n");
2472                                 goto out;
2473                         }
2474                         break;
2475                 case PHY_COMP_EQ_SKIPN:
2476                 case PHY_COMP_NEQ_SKIPN:
2477                 case PHY_SKIPN:
2478                         if (index + 1 + regno >= pa->size) {
2479                                 netif_err(tp, ifup, tp->dev,
2480                                           "Out of range of firmware\n");
2481                                 goto out;
2482                         }
2483                         break;
2484
2485                 default:
2486                         netif_err(tp, ifup, tp->dev,
2487                                   "Invalid action 0x%08x\n", action);
2488                         goto out;
2489                 }
2490         }
2491         rc = true;
2492 out:
2493         return rc;
2494 }
2495
2496 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2497 {
2498         struct net_device *dev = tp->dev;
2499         int rc = -EINVAL;
2500
2501         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2502                 netif_err(tp, ifup, dev, "invalid firmware\n");
2503                 goto out;
2504         }
2505
2506         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2507                 rc = 0;
2508 out:
2509         return rc;
2510 }
2511
2512 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2513 {
2514         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2515         struct mdio_ops org, *ops = &tp->mdio_ops;
2516         u32 predata, count;
2517         size_t index;
2518
2519         predata = count = 0;
2520         org.write = ops->write;
2521         org.read = ops->read;
2522
2523         for (index = 0; index < pa->size; ) {
2524                 u32 action = le32_to_cpu(pa->code[index]);
2525                 u32 data = action & 0x0000ffff;
2526                 u32 regno = (action & 0x0fff0000) >> 16;
2527
2528                 if (!action)
2529                         break;
2530
2531                 switch(action & 0xf0000000) {
2532                 case PHY_READ:
2533                         predata = rtl_readphy(tp, regno);
2534                         count++;
2535                         index++;
2536                         break;
2537                 case PHY_DATA_OR:
2538                         predata |= data;
2539                         index++;
2540                         break;
2541                 case PHY_DATA_AND:
2542                         predata &= data;
2543                         index++;
2544                         break;
2545                 case PHY_BJMPN:
2546                         index -= regno;
2547                         break;
2548                 case PHY_MDIO_CHG:
2549                         if (data == 0) {
2550                                 ops->write = org.write;
2551                                 ops->read = org.read;
2552                         } else if (data == 1) {
2553                                 ops->write = mac_mcu_write;
2554                                 ops->read = mac_mcu_read;
2555                         }
2556
2557                         index++;
2558                         break;
2559                 case PHY_CLEAR_READCOUNT:
2560                         count = 0;
2561                         index++;
2562                         break;
2563                 case PHY_WRITE:
2564                         rtl_writephy(tp, regno, data);
2565                         index++;
2566                         break;
2567                 case PHY_READCOUNT_EQ_SKIP:
2568                         index += (count == data) ? 2 : 1;
2569                         break;
2570                 case PHY_COMP_EQ_SKIPN:
2571                         if (predata == data)
2572                                 index += regno;
2573                         index++;
2574                         break;
2575                 case PHY_COMP_NEQ_SKIPN:
2576                         if (predata != data)
2577                                 index += regno;
2578                         index++;
2579                         break;
2580                 case PHY_WRITE_PREVIOUS:
2581                         rtl_writephy(tp, regno, predata);
2582                         index++;
2583                         break;
2584                 case PHY_SKIPN:
2585                         index += regno + 1;
2586                         break;
2587                 case PHY_DELAY_MS:
2588                         mdelay(data);
2589                         index++;
2590                         break;
2591
2592                 default:
2593                         BUG();
2594                 }
2595         }
2596
2597         ops->write = org.write;
2598         ops->read = org.read;
2599 }
2600
2601 static void rtl_release_firmware(struct rtl8169_private *tp)
2602 {
2603         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2604                 release_firmware(tp->rtl_fw->fw);
2605                 kfree(tp->rtl_fw);
2606         }
2607         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2608 }
2609
2610 static void rtl_apply_firmware(struct rtl8169_private *tp)
2611 {
2612         struct rtl_fw *rtl_fw = tp->rtl_fw;
2613
2614         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2615         if (!IS_ERR_OR_NULL(rtl_fw))
2616                 rtl_phy_write_fw(tp, rtl_fw);
2617 }
2618
2619 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2620 {
2621         if (rtl_readphy(tp, reg) != val)
2622                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2623         else
2624                 rtl_apply_firmware(tp);
2625 }
2626
2627 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2628 {
2629         static const struct phy_reg phy_reg_init[] = {
2630                 { 0x1f, 0x0001 },
2631                 { 0x06, 0x006e },
2632                 { 0x08, 0x0708 },
2633                 { 0x15, 0x4000 },
2634                 { 0x18, 0x65c7 },
2635
2636                 { 0x1f, 0x0001 },
2637                 { 0x03, 0x00a1 },
2638                 { 0x02, 0x0008 },
2639                 { 0x01, 0x0120 },
2640                 { 0x00, 0x1000 },
2641                 { 0x04, 0x0800 },
2642                 { 0x04, 0x0000 },
2643
2644                 { 0x03, 0xff41 },
2645                 { 0x02, 0xdf60 },
2646                 { 0x01, 0x0140 },
2647                 { 0x00, 0x0077 },
2648                 { 0x04, 0x7800 },
2649                 { 0x04, 0x7000 },
2650
2651                 { 0x03, 0x802f },
2652                 { 0x02, 0x4f02 },
2653                 { 0x01, 0x0409 },
2654                 { 0x00, 0xf0f9 },
2655                 { 0x04, 0x9800 },
2656                 { 0x04, 0x9000 },
2657
2658                 { 0x03, 0xdf01 },
2659                 { 0x02, 0xdf20 },
2660                 { 0x01, 0xff95 },
2661                 { 0x00, 0xba00 },
2662                 { 0x04, 0xa800 },
2663                 { 0x04, 0xa000 },
2664
2665                 { 0x03, 0xff41 },
2666                 { 0x02, 0xdf20 },
2667                 { 0x01, 0x0140 },
2668                 { 0x00, 0x00bb },
2669                 { 0x04, 0xb800 },
2670                 { 0x04, 0xb000 },
2671
2672                 { 0x03, 0xdf41 },
2673                 { 0x02, 0xdc60 },
2674                 { 0x01, 0x6340 },
2675                 { 0x00, 0x007d },
2676                 { 0x04, 0xd800 },
2677                 { 0x04, 0xd000 },
2678
2679                 { 0x03, 0xdf01 },
2680                 { 0x02, 0xdf20 },
2681                 { 0x01, 0x100a },
2682                 { 0x00, 0xa0ff },
2683                 { 0x04, 0xf800 },
2684                 { 0x04, 0xf000 },
2685
2686                 { 0x1f, 0x0000 },
2687                 { 0x0b, 0x0000 },
2688                 { 0x00, 0x9200 }
2689         };
2690
2691         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2692 }
2693
2694 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2695 {
2696         static const struct phy_reg phy_reg_init[] = {
2697                 { 0x1f, 0x0002 },
2698                 { 0x01, 0x90d0 },
2699                 { 0x1f, 0x0000 }
2700         };
2701
2702         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2703 }
2704
2705 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2706 {
2707         struct pci_dev *pdev = tp->pci_dev;
2708
2709         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2710             (pdev->subsystem_device != 0xe000))
2711                 return;
2712
2713         rtl_writephy(tp, 0x1f, 0x0001);
2714         rtl_writephy(tp, 0x10, 0xf01b);
2715         rtl_writephy(tp, 0x1f, 0x0000);
2716 }
2717
2718 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2719 {
2720         static const struct phy_reg phy_reg_init[] = {
2721                 { 0x1f, 0x0001 },
2722                 { 0x04, 0x0000 },
2723                 { 0x03, 0x00a1 },
2724                 { 0x02, 0x0008 },
2725                 { 0x01, 0x0120 },
2726                 { 0x00, 0x1000 },
2727                 { 0x04, 0x0800 },
2728                 { 0x04, 0x9000 },
2729                 { 0x03, 0x802f },
2730                 { 0x02, 0x4f02 },
2731                 { 0x01, 0x0409 },
2732                 { 0x00, 0xf099 },
2733                 { 0x04, 0x9800 },
2734                 { 0x04, 0xa000 },
2735                 { 0x03, 0xdf01 },
2736                 { 0x02, 0xdf20 },
2737                 { 0x01, 0xff95 },
2738                 { 0x00, 0xba00 },
2739                 { 0x04, 0xa800 },
2740                 { 0x04, 0xf000 },
2741                 { 0x03, 0xdf01 },
2742                 { 0x02, 0xdf20 },
2743                 { 0x01, 0x101a },
2744                 { 0x00, 0xa0ff },
2745                 { 0x04, 0xf800 },
2746                 { 0x04, 0x0000 },
2747                 { 0x1f, 0x0000 },
2748
2749                 { 0x1f, 0x0001 },
2750                 { 0x10, 0xf41b },
2751                 { 0x14, 0xfb54 },
2752                 { 0x18, 0xf5c7 },
2753                 { 0x1f, 0x0000 },
2754
2755                 { 0x1f, 0x0001 },
2756                 { 0x17, 0x0cc0 },
2757                 { 0x1f, 0x0000 }
2758         };
2759
2760         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2761
2762         rtl8169scd_hw_phy_config_quirk(tp);
2763 }
2764
2765 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2766 {
2767         static const struct phy_reg phy_reg_init[] = {
2768                 { 0x1f, 0x0001 },
2769                 { 0x04, 0x0000 },
2770                 { 0x03, 0x00a1 },
2771                 { 0x02, 0x0008 },
2772                 { 0x01, 0x0120 },
2773                 { 0x00, 0x1000 },
2774                 { 0x04, 0x0800 },
2775                 { 0x04, 0x9000 },
2776                 { 0x03, 0x802f },
2777                 { 0x02, 0x4f02 },
2778                 { 0x01, 0x0409 },
2779                 { 0x00, 0xf099 },
2780                 { 0x04, 0x9800 },
2781                 { 0x04, 0xa000 },
2782                 { 0x03, 0xdf01 },
2783                 { 0x02, 0xdf20 },
2784                 { 0x01, 0xff95 },
2785                 { 0x00, 0xba00 },
2786                 { 0x04, 0xa800 },
2787                 { 0x04, 0xf000 },
2788                 { 0x03, 0xdf01 },
2789                 { 0x02, 0xdf20 },
2790                 { 0x01, 0x101a },
2791                 { 0x00, 0xa0ff },
2792                 { 0x04, 0xf800 },
2793                 { 0x04, 0x0000 },
2794                 { 0x1f, 0x0000 },
2795
2796                 { 0x1f, 0x0001 },
2797                 { 0x0b, 0x8480 },
2798                 { 0x1f, 0x0000 },
2799
2800                 { 0x1f, 0x0001 },
2801                 { 0x18, 0x67c7 },
2802                 { 0x04, 0x2000 },
2803                 { 0x03, 0x002f },
2804                 { 0x02, 0x4360 },
2805                 { 0x01, 0x0109 },
2806                 { 0x00, 0x3022 },
2807                 { 0x04, 0x2800 },
2808                 { 0x1f, 0x0000 },
2809
2810                 { 0x1f, 0x0001 },
2811                 { 0x17, 0x0cc0 },
2812                 { 0x1f, 0x0000 }
2813         };
2814
2815         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2816 }
2817
2818 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2819 {
2820         static const struct phy_reg phy_reg_init[] = {
2821                 { 0x10, 0xf41b },
2822                 { 0x1f, 0x0000 }
2823         };
2824
2825         rtl_writephy(tp, 0x1f, 0x0001);
2826         rtl_patchphy(tp, 0x16, 1 << 0);
2827
2828         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2829 }
2830
2831 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2832 {
2833         static const struct phy_reg phy_reg_init[] = {
2834                 { 0x1f, 0x0001 },
2835                 { 0x10, 0xf41b },
2836                 { 0x1f, 0x0000 }
2837         };
2838
2839         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2840 }
2841
2842 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2843 {
2844         static const struct phy_reg phy_reg_init[] = {
2845                 { 0x1f, 0x0000 },
2846                 { 0x1d, 0x0f00 },
2847                 { 0x1f, 0x0002 },
2848                 { 0x0c, 0x1ec8 },
2849                 { 0x1f, 0x0000 }
2850         };
2851
2852         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2853 }
2854
2855 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2856 {
2857         static const struct phy_reg phy_reg_init[] = {
2858                 { 0x1f, 0x0001 },
2859                 { 0x1d, 0x3d98 },
2860                 { 0x1f, 0x0000 }
2861         };
2862
2863         rtl_writephy(tp, 0x1f, 0x0000);
2864         rtl_patchphy(tp, 0x14, 1 << 5);
2865         rtl_patchphy(tp, 0x0d, 1 << 5);
2866
2867         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2868 }
2869
2870 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2871 {
2872         static const struct phy_reg phy_reg_init[] = {
2873                 { 0x1f, 0x0001 },
2874                 { 0x12, 0x2300 },
2875                 { 0x1f, 0x0002 },
2876                 { 0x00, 0x88d4 },
2877                 { 0x01, 0x82b1 },
2878                 { 0x03, 0x7002 },
2879                 { 0x08, 0x9e30 },
2880                 { 0x09, 0x01f0 },
2881                 { 0x0a, 0x5500 },
2882                 { 0x0c, 0x00c8 },
2883                 { 0x1f, 0x0003 },
2884                 { 0x12, 0xc096 },
2885                 { 0x16, 0x000a },
2886                 { 0x1f, 0x0000 },
2887                 { 0x1f, 0x0000 },
2888                 { 0x09, 0x2000 },
2889                 { 0x09, 0x0000 }
2890         };
2891
2892         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2893
2894         rtl_patchphy(tp, 0x14, 1 << 5);
2895         rtl_patchphy(tp, 0x0d, 1 << 5);
2896         rtl_writephy(tp, 0x1f, 0x0000);
2897 }
2898
2899 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2900 {
2901         static const struct phy_reg phy_reg_init[] = {
2902                 { 0x1f, 0x0001 },
2903                 { 0x12, 0x2300 },
2904                 { 0x03, 0x802f },
2905                 { 0x02, 0x4f02 },
2906                 { 0x01, 0x0409 },
2907                 { 0x00, 0xf099 },
2908                 { 0x04, 0x9800 },
2909                 { 0x04, 0x9000 },
2910                 { 0x1d, 0x3d98 },
2911                 { 0x1f, 0x0002 },
2912                 { 0x0c, 0x7eb8 },
2913                 { 0x06, 0x0761 },
2914                 { 0x1f, 0x0003 },
2915                 { 0x16, 0x0f0a },
2916                 { 0x1f, 0x0000 }
2917         };
2918
2919         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2920
2921         rtl_patchphy(tp, 0x16, 1 << 0);
2922         rtl_patchphy(tp, 0x14, 1 << 5);
2923         rtl_patchphy(tp, 0x0d, 1 << 5);
2924         rtl_writephy(tp, 0x1f, 0x0000);
2925 }
2926
2927 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2928 {
2929         static const struct phy_reg phy_reg_init[] = {
2930                 { 0x1f, 0x0001 },
2931                 { 0x12, 0x2300 },
2932                 { 0x1d, 0x3d98 },
2933                 { 0x1f, 0x0002 },
2934                 { 0x0c, 0x7eb8 },
2935                 { 0x06, 0x5461 },
2936                 { 0x1f, 0x0003 },
2937                 { 0x16, 0x0f0a },
2938                 { 0x1f, 0x0000 }
2939         };
2940
2941         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2942
2943         rtl_patchphy(tp, 0x16, 1 << 0);
2944         rtl_patchphy(tp, 0x14, 1 << 5);
2945         rtl_patchphy(tp, 0x0d, 1 << 5);
2946         rtl_writephy(tp, 0x1f, 0x0000);
2947 }
2948
2949 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2950 {
2951         rtl8168c_3_hw_phy_config(tp);
2952 }
2953
2954 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2955 {
2956         static const struct phy_reg phy_reg_init_0[] = {
2957                 /* Channel Estimation */
2958                 { 0x1f, 0x0001 },
2959                 { 0x06, 0x4064 },
2960                 { 0x07, 0x2863 },
2961                 { 0x08, 0x059c },
2962                 { 0x09, 0x26b4 },
2963                 { 0x0a, 0x6a19 },
2964                 { 0x0b, 0xdcc8 },
2965                 { 0x10, 0xf06d },
2966                 { 0x14, 0x7f68 },
2967                 { 0x18, 0x7fd9 },
2968                 { 0x1c, 0xf0ff },
2969                 { 0x1d, 0x3d9c },
2970                 { 0x1f, 0x0003 },
2971                 { 0x12, 0xf49f },
2972                 { 0x13, 0x070b },
2973                 { 0x1a, 0x05ad },
2974                 { 0x14, 0x94c0 },
2975
2976                 /*
2977                  * Tx Error Issue
2978                  * Enhance line driver power
2979                  */
2980                 { 0x1f, 0x0002 },
2981                 { 0x06, 0x5561 },
2982                 { 0x1f, 0x0005 },
2983                 { 0x05, 0x8332 },
2984                 { 0x06, 0x5561 },
2985
2986                 /*
2987                  * Can not link to 1Gbps with bad cable
2988                  * Decrease SNR threshold form 21.07dB to 19.04dB
2989                  */
2990                 { 0x1f, 0x0001 },
2991                 { 0x17, 0x0cc0 },
2992
2993                 { 0x1f, 0x0000 },
2994                 { 0x0d, 0xf880 }
2995         };
2996
2997         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2998
2999         /*
3000          * Rx Error Issue
3001          * Fine Tune Switching regulator parameter
3002          */
3003         rtl_writephy(tp, 0x1f, 0x0002);
3004         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3005         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3006
3007         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3008                 static const struct phy_reg phy_reg_init[] = {
3009                         { 0x1f, 0x0002 },
3010                         { 0x05, 0x669a },
3011                         { 0x1f, 0x0005 },
3012                         { 0x05, 0x8330 },
3013                         { 0x06, 0x669a },
3014                         { 0x1f, 0x0002 }
3015                 };
3016                 int val;
3017
3018                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3019
3020                 val = rtl_readphy(tp, 0x0d);
3021
3022                 if ((val & 0x00ff) != 0x006c) {
3023                         static const u32 set[] = {
3024                                 0x0065, 0x0066, 0x0067, 0x0068,
3025                                 0x0069, 0x006a, 0x006b, 0x006c
3026                         };
3027                         int i;
3028
3029                         rtl_writephy(tp, 0x1f, 0x0002);
3030
3031                         val &= 0xff00;
3032                         for (i = 0; i < ARRAY_SIZE(set); i++)
3033                                 rtl_writephy(tp, 0x0d, val | set[i]);
3034                 }
3035         } else {
3036                 static const struct phy_reg phy_reg_init[] = {
3037                         { 0x1f, 0x0002 },
3038                         { 0x05, 0x6662 },
3039                         { 0x1f, 0x0005 },
3040                         { 0x05, 0x8330 },
3041                         { 0x06, 0x6662 }
3042                 };
3043
3044                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3045         }
3046
3047         /* RSET couple improve */
3048         rtl_writephy(tp, 0x1f, 0x0002);
3049         rtl_patchphy(tp, 0x0d, 0x0300);
3050         rtl_patchphy(tp, 0x0f, 0x0010);
3051
3052         /* Fine tune PLL performance */
3053         rtl_writephy(tp, 0x1f, 0x0002);
3054         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3055         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3056
3057         rtl_writephy(tp, 0x1f, 0x0005);
3058         rtl_writephy(tp, 0x05, 0x001b);
3059
3060         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3061
3062         rtl_writephy(tp, 0x1f, 0x0000);
3063 }
3064
3065 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3066 {
3067         static const struct phy_reg phy_reg_init_0[] = {
3068                 /* Channel Estimation */
3069                 { 0x1f, 0x0001 },
3070                 { 0x06, 0x4064 },
3071                 { 0x07, 0x2863 },
3072                 { 0x08, 0x059c },
3073                 { 0x09, 0x26b4 },
3074                 { 0x0a, 0x6a19 },
3075                 { 0x0b, 0xdcc8 },
3076                 { 0x10, 0xf06d },
3077                 { 0x14, 0x7f68 },
3078                 { 0x18, 0x7fd9 },
3079                 { 0x1c, 0xf0ff },
3080                 { 0x1d, 0x3d9c },
3081                 { 0x1f, 0x0003 },
3082                 { 0x12, 0xf49f },
3083                 { 0x13, 0x070b },
3084                 { 0x1a, 0x05ad },
3085                 { 0x14, 0x94c0 },
3086
3087                 /*
3088                  * Tx Error Issue
3089                  * Enhance line driver power
3090                  */
3091                 { 0x1f, 0x0002 },
3092                 { 0x06, 0x5561 },
3093                 { 0x1f, 0x0005 },
3094                 { 0x05, 0x8332 },
3095                 { 0x06, 0x5561 },
3096
3097                 /*
3098                  * Can not link to 1Gbps with bad cable
3099                  * Decrease SNR threshold form 21.07dB to 19.04dB
3100                  */
3101                 { 0x1f, 0x0001 },
3102                 { 0x17, 0x0cc0 },
3103
3104                 { 0x1f, 0x0000 },
3105                 { 0x0d, 0xf880 }
3106         };
3107
3108         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3109
3110         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3111                 static const struct phy_reg phy_reg_init[] = {
3112                         { 0x1f, 0x0002 },
3113                         { 0x05, 0x669a },
3114                         { 0x1f, 0x0005 },
3115                         { 0x05, 0x8330 },
3116                         { 0x06, 0x669a },
3117
3118                         { 0x1f, 0x0002 }
3119                 };
3120                 int val;
3121
3122                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3123
3124                 val = rtl_readphy(tp, 0x0d);
3125                 if ((val & 0x00ff) != 0x006c) {
3126                         static const u32 set[] = {
3127                                 0x0065, 0x0066, 0x0067, 0x0068,
3128                                 0x0069, 0x006a, 0x006b, 0x006c
3129                         };
3130                         int i;
3131
3132                         rtl_writephy(tp, 0x1f, 0x0002);
3133
3134                         val &= 0xff00;
3135                         for (i = 0; i < ARRAY_SIZE(set); i++)
3136                                 rtl_writephy(tp, 0x0d, val | set[i]);
3137                 }
3138         } else {
3139                 static const struct phy_reg phy_reg_init[] = {
3140                         { 0x1f, 0x0002 },
3141                         { 0x05, 0x2642 },
3142                         { 0x1f, 0x0005 },
3143                         { 0x05, 0x8330 },
3144                         { 0x06, 0x2642 }
3145                 };
3146
3147                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3148         }
3149
3150         /* Fine tune PLL performance */
3151         rtl_writephy(tp, 0x1f, 0x0002);
3152         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3153         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3154
3155         /* Switching regulator Slew rate */
3156         rtl_writephy(tp, 0x1f, 0x0002);
3157         rtl_patchphy(tp, 0x0f, 0x0017);
3158
3159         rtl_writephy(tp, 0x1f, 0x0005);
3160         rtl_writephy(tp, 0x05, 0x001b);
3161
3162         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3163
3164         rtl_writephy(tp, 0x1f, 0x0000);
3165 }
3166
3167 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3168 {
3169         static const struct phy_reg phy_reg_init[] = {
3170                 { 0x1f, 0x0002 },
3171                 { 0x10, 0x0008 },
3172                 { 0x0d, 0x006c },
3173
3174                 { 0x1f, 0x0000 },
3175                 { 0x0d, 0xf880 },
3176
3177                 { 0x1f, 0x0001 },
3178                 { 0x17, 0x0cc0 },
3179
3180                 { 0x1f, 0x0001 },
3181                 { 0x0b, 0xa4d8 },
3182                 { 0x09, 0x281c },
3183                 { 0x07, 0x2883 },
3184                 { 0x0a, 0x6b35 },
3185                 { 0x1d, 0x3da4 },
3186                 { 0x1c, 0xeffd },
3187                 { 0x14, 0x7f52 },
3188                 { 0x18, 0x7fc6 },
3189                 { 0x08, 0x0601 },
3190                 { 0x06, 0x4063 },
3191                 { 0x10, 0xf074 },
3192                 { 0x1f, 0x0003 },
3193                 { 0x13, 0x0789 },
3194                 { 0x12, 0xf4bd },
3195                 { 0x1a, 0x04fd },
3196                 { 0x14, 0x84b0 },
3197                 { 0x1f, 0x0000 },
3198                 { 0x00, 0x9200 },
3199
3200                 { 0x1f, 0x0005 },
3201                 { 0x01, 0x0340 },
3202                 { 0x1f, 0x0001 },
3203                 { 0x04, 0x4000 },
3204                 { 0x03, 0x1d21 },
3205                 { 0x02, 0x0c32 },
3206                 { 0x01, 0x0200 },
3207                 { 0x00, 0x5554 },
3208                 { 0x04, 0x4800 },
3209                 { 0x04, 0x4000 },
3210                 { 0x04, 0xf000 },
3211                 { 0x03, 0xdf01 },
3212                 { 0x02, 0xdf20 },
3213                 { 0x01, 0x101a },
3214                 { 0x00, 0xa0ff },
3215                 { 0x04, 0xf800 },
3216                 { 0x04, 0xf000 },
3217                 { 0x1f, 0x0000 },
3218
3219                 { 0x1f, 0x0007 },
3220                 { 0x1e, 0x0023 },
3221                 { 0x16, 0x0000 },
3222                 { 0x1f, 0x0000 }
3223         };
3224
3225         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3226 }
3227
3228 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3229 {
3230         static const struct phy_reg phy_reg_init[] = {
3231                 { 0x1f, 0x0001 },
3232                 { 0x17, 0x0cc0 },
3233
3234                 { 0x1f, 0x0007 },
3235                 { 0x1e, 0x002d },
3236                 { 0x18, 0x0040 },
3237                 { 0x1f, 0x0000 }
3238         };
3239
3240         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3241         rtl_patchphy(tp, 0x0d, 1 << 5);
3242 }
3243
3244 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3245 {
3246         static const struct phy_reg phy_reg_init[] = {
3247                 /* Enable Delay cap */
3248                 { 0x1f, 0x0005 },
3249                 { 0x05, 0x8b80 },
3250                 { 0x06, 0xc896 },
3251                 { 0x1f, 0x0000 },
3252
3253                 /* Channel estimation fine tune */
3254                 { 0x1f, 0x0001 },
3255                 { 0x0b, 0x6c20 },
3256                 { 0x07, 0x2872 },
3257                 { 0x1c, 0xefff },
3258                 { 0x1f, 0x0003 },
3259                 { 0x14, 0x6420 },
3260                 { 0x1f, 0x0000 },
3261
3262                 /* Update PFM & 10M TX idle timer */
3263                 { 0x1f, 0x0007 },
3264                 { 0x1e, 0x002f },
3265                 { 0x15, 0x1919 },
3266                 { 0x1f, 0x0000 },
3267
3268                 { 0x1f, 0x0007 },
3269                 { 0x1e, 0x00ac },
3270                 { 0x18, 0x0006 },
3271                 { 0x1f, 0x0000 }
3272         };
3273
3274         rtl_apply_firmware(tp);
3275
3276         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3277
3278         /* DCO enable for 10M IDLE Power */
3279         rtl_writephy(tp, 0x1f, 0x0007);
3280         rtl_writephy(tp, 0x1e, 0x0023);
3281         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3282         rtl_writephy(tp, 0x1f, 0x0000);
3283
3284         /* For impedance matching */
3285         rtl_writephy(tp, 0x1f, 0x0002);
3286         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3287         rtl_writephy(tp, 0x1f, 0x0000);
3288
3289         /* PHY auto speed down */
3290         rtl_writephy(tp, 0x1f, 0x0007);
3291         rtl_writephy(tp, 0x1e, 0x002d);
3292         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3293         rtl_writephy(tp, 0x1f, 0x0000);
3294         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3295
3296         rtl_writephy(tp, 0x1f, 0x0005);
3297         rtl_writephy(tp, 0x05, 0x8b86);
3298         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3299         rtl_writephy(tp, 0x1f, 0x0000);
3300
3301         rtl_writephy(tp, 0x1f, 0x0005);
3302         rtl_writephy(tp, 0x05, 0x8b85);
3303         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3304         rtl_writephy(tp, 0x1f, 0x0007);
3305         rtl_writephy(tp, 0x1e, 0x0020);
3306         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3307         rtl_writephy(tp, 0x1f, 0x0006);
3308         rtl_writephy(tp, 0x00, 0x5a00);
3309         rtl_writephy(tp, 0x1f, 0x0000);
3310         rtl_writephy(tp, 0x0d, 0x0007);
3311         rtl_writephy(tp, 0x0e, 0x003c);
3312         rtl_writephy(tp, 0x0d, 0x4007);
3313         rtl_writephy(tp, 0x0e, 0x0000);
3314         rtl_writephy(tp, 0x0d, 0x0000);
3315 }
3316
3317 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3318 {
3319         const u16 w[] = {
3320                 addr[0] | (addr[1] << 8),
3321                 addr[2] | (addr[3] << 8),
3322                 addr[4] | (addr[5] << 8)
3323         };
3324         const struct exgmac_reg e[] = {
3325                 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3326                 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3327                 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3328                 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3329         };
3330
3331         rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3332 }
3333
3334 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3335 {
3336         static const struct phy_reg phy_reg_init[] = {
3337                 /* Enable Delay cap */
3338                 { 0x1f, 0x0004 },
3339                 { 0x1f, 0x0007 },
3340                 { 0x1e, 0x00ac },
3341                 { 0x18, 0x0006 },
3342                 { 0x1f, 0x0002 },
3343                 { 0x1f, 0x0000 },
3344                 { 0x1f, 0x0000 },
3345
3346                 /* Channel estimation fine tune */
3347                 { 0x1f, 0x0003 },
3348                 { 0x09, 0xa20f },
3349                 { 0x1f, 0x0000 },
3350                 { 0x1f, 0x0000 },
3351
3352                 /* Green Setting */
3353                 { 0x1f, 0x0005 },
3354                 { 0x05, 0x8b5b },
3355                 { 0x06, 0x9222 },
3356                 { 0x05, 0x8b6d },
3357                 { 0x06, 0x8000 },
3358                 { 0x05, 0x8b76 },
3359                 { 0x06, 0x8000 },
3360                 { 0x1f, 0x0000 }
3361         };
3362
3363         rtl_apply_firmware(tp);
3364
3365         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3366
3367         /* For 4-corner performance improve */
3368         rtl_writephy(tp, 0x1f, 0x0005);
3369         rtl_writephy(tp, 0x05, 0x8b80);
3370         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3371         rtl_writephy(tp, 0x1f, 0x0000);
3372
3373         /* PHY auto speed down */
3374         rtl_writephy(tp, 0x1f, 0x0004);
3375         rtl_writephy(tp, 0x1f, 0x0007);
3376         rtl_writephy(tp, 0x1e, 0x002d);
3377         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3378         rtl_writephy(tp, 0x1f, 0x0002);
3379         rtl_writephy(tp, 0x1f, 0x0000);
3380         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3381
3382         /* improve 10M EEE waveform */
3383         rtl_writephy(tp, 0x1f, 0x0005);
3384         rtl_writephy(tp, 0x05, 0x8b86);
3385         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3386         rtl_writephy(tp, 0x1f, 0x0000);
3387
3388         /* Improve 2-pair detection performance */
3389         rtl_writephy(tp, 0x1f, 0x0005);
3390         rtl_writephy(tp, 0x05, 0x8b85);
3391         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3392         rtl_writephy(tp, 0x1f, 0x0000);
3393
3394         /* EEE setting */
3395         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3396         rtl_writephy(tp, 0x1f, 0x0005);
3397         rtl_writephy(tp, 0x05, 0x8b85);
3398         rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3399         rtl_writephy(tp, 0x1f, 0x0004);
3400         rtl_writephy(tp, 0x1f, 0x0007);
3401         rtl_writephy(tp, 0x1e, 0x0020);
3402         rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3403         rtl_writephy(tp, 0x1f, 0x0002);
3404         rtl_writephy(tp, 0x1f, 0x0000);
3405         rtl_writephy(tp, 0x0d, 0x0007);
3406         rtl_writephy(tp, 0x0e, 0x003c);
3407         rtl_writephy(tp, 0x0d, 0x4007);
3408         rtl_writephy(tp, 0x0e, 0x0006);
3409         rtl_writephy(tp, 0x0d, 0x0000);
3410
3411         /* Green feature */
3412         rtl_writephy(tp, 0x1f, 0x0003);
3413         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3414         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3415         rtl_writephy(tp, 0x1f, 0x0000);
3416         rtl_writephy(tp, 0x1f, 0x0005);
3417         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3418         rtl_writephy(tp, 0x1f, 0x0000);
3419
3420         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3421         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3422 }
3423
3424 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3425 {
3426         /* For 4-corner performance improve */
3427         rtl_writephy(tp, 0x1f, 0x0005);
3428         rtl_writephy(tp, 0x05, 0x8b80);
3429         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3430         rtl_writephy(tp, 0x1f, 0x0000);
3431
3432         /* PHY auto speed down */
3433         rtl_writephy(tp, 0x1f, 0x0007);
3434         rtl_writephy(tp, 0x1e, 0x002d);
3435         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3436         rtl_writephy(tp, 0x1f, 0x0000);
3437         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3438
3439         /* Improve 10M EEE waveform */
3440         rtl_writephy(tp, 0x1f, 0x0005);
3441         rtl_writephy(tp, 0x05, 0x8b86);
3442         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3443         rtl_writephy(tp, 0x1f, 0x0000);
3444 }
3445
3446 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3447 {
3448         static const struct phy_reg phy_reg_init[] = {
3449                 /* Channel estimation fine tune */
3450                 { 0x1f, 0x0003 },
3451                 { 0x09, 0xa20f },
3452                 { 0x1f, 0x0000 },
3453
3454                 /* Modify green table for giga & fnet */
3455                 { 0x1f, 0x0005 },
3456                 { 0x05, 0x8b55 },
3457                 { 0x06, 0x0000 },
3458                 { 0x05, 0x8b5e },
3459                 { 0x06, 0x0000 },
3460                 { 0x05, 0x8b67 },
3461                 { 0x06, 0x0000 },
3462                 { 0x05, 0x8b70 },
3463                 { 0x06, 0x0000 },
3464                 { 0x1f, 0x0000 },
3465                 { 0x1f, 0x0007 },
3466                 { 0x1e, 0x0078 },
3467                 { 0x17, 0x0000 },
3468                 { 0x19, 0x00fb },
3469                 { 0x1f, 0x0000 },
3470
3471                 /* Modify green table for 10M */
3472                 { 0x1f, 0x0005 },
3473                 { 0x05, 0x8b79 },
3474                 { 0x06, 0xaa00 },
3475                 { 0x1f, 0x0000 },
3476
3477                 /* Disable hiimpedance detection (RTCT) */
3478                 { 0x1f, 0x0003 },
3479                 { 0x01, 0x328a },
3480                 { 0x1f, 0x0000 }
3481         };
3482
3483         rtl_apply_firmware(tp);
3484
3485         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3486
3487         rtl8168f_hw_phy_config(tp);
3488
3489         /* Improve 2-pair detection performance */
3490         rtl_writephy(tp, 0x1f, 0x0005);
3491         rtl_writephy(tp, 0x05, 0x8b85);
3492         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3493         rtl_writephy(tp, 0x1f, 0x0000);
3494 }
3495
3496 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3497 {
3498         rtl_apply_firmware(tp);
3499
3500         rtl8168f_hw_phy_config(tp);
3501 }
3502
3503 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3504 {
3505         static const struct phy_reg phy_reg_init[] = {
3506                 /* Channel estimation fine tune */
3507                 { 0x1f, 0x0003 },
3508                 { 0x09, 0xa20f },
3509                 { 0x1f, 0x0000 },
3510
3511                 /* Modify green table for giga & fnet */
3512                 { 0x1f, 0x0005 },
3513                 { 0x05, 0x8b55 },
3514                 { 0x06, 0x0000 },
3515                 { 0x05, 0x8b5e },
3516                 { 0x06, 0x0000 },
3517                 { 0x05, 0x8b67 },
3518                 { 0x06, 0x0000 },
3519                 { 0x05, 0x8b70 },
3520                 { 0x06, 0x0000 },
3521                 { 0x1f, 0x0000 },
3522                 { 0x1f, 0x0007 },
3523                 { 0x1e, 0x0078 },
3524                 { 0x17, 0x0000 },
3525                 { 0x19, 0x00aa },
3526                 { 0x1f, 0x0000 },
3527
3528                 /* Modify green table for 10M */
3529                 { 0x1f, 0x0005 },
3530                 { 0x05, 0x8b79 },
3531                 { 0x06, 0xaa00 },
3532                 { 0x1f, 0x0000 },
3533
3534                 /* Disable hiimpedance detection (RTCT) */
3535                 { 0x1f, 0x0003 },
3536                 { 0x01, 0x328a },
3537                 { 0x1f, 0x0000 }
3538         };
3539
3540
3541         rtl_apply_firmware(tp);
3542
3543         rtl8168f_hw_phy_config(tp);
3544
3545         /* Improve 2-pair detection performance */
3546         rtl_writephy(tp, 0x1f, 0x0005);
3547         rtl_writephy(tp, 0x05, 0x8b85);
3548         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3549         rtl_writephy(tp, 0x1f, 0x0000);
3550
3551         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3552
3553         /* Modify green table for giga */
3554         rtl_writephy(tp, 0x1f, 0x0005);
3555         rtl_writephy(tp, 0x05, 0x8b54);
3556         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3557         rtl_writephy(tp, 0x05, 0x8b5d);
3558         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3559         rtl_writephy(tp, 0x05, 0x8a7c);
3560         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3561         rtl_writephy(tp, 0x05, 0x8a7f);
3562         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3563         rtl_writephy(tp, 0x05, 0x8a82);
3564         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3565         rtl_writephy(tp, 0x05, 0x8a85);
3566         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3567         rtl_writephy(tp, 0x05, 0x8a88);
3568         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3569         rtl_writephy(tp, 0x1f, 0x0000);
3570
3571         /* uc same-seed solution */
3572         rtl_writephy(tp, 0x1f, 0x0005);
3573         rtl_writephy(tp, 0x05, 0x8b85);
3574         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3575         rtl_writephy(tp, 0x1f, 0x0000);
3576
3577         /* eee setting */
3578         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3579         rtl_writephy(tp, 0x1f, 0x0005);
3580         rtl_writephy(tp, 0x05, 0x8b85);
3581         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3582         rtl_writephy(tp, 0x1f, 0x0004);
3583         rtl_writephy(tp, 0x1f, 0x0007);
3584         rtl_writephy(tp, 0x1e, 0x0020);
3585         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3586         rtl_writephy(tp, 0x1f, 0x0000);
3587         rtl_writephy(tp, 0x0d, 0x0007);
3588         rtl_writephy(tp, 0x0e, 0x003c);
3589         rtl_writephy(tp, 0x0d, 0x4007);
3590         rtl_writephy(tp, 0x0e, 0x0000);
3591         rtl_writephy(tp, 0x0d, 0x0000);
3592
3593         /* Green feature */
3594         rtl_writephy(tp, 0x1f, 0x0003);
3595         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3596         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3597         rtl_writephy(tp, 0x1f, 0x0000);
3598 }
3599
3600 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3601 {
3602         rtl_apply_firmware(tp);
3603
3604         rtl_writephy(tp, 0x1f, 0x0a46);
3605         if (rtl_readphy(tp, 0x10) & 0x0100) {
3606                 rtl_writephy(tp, 0x1f, 0x0bcc);
3607                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3608         } else {
3609                 rtl_writephy(tp, 0x1f, 0x0bcc);
3610                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3611         }
3612
3613         rtl_writephy(tp, 0x1f, 0x0a46);
3614         if (rtl_readphy(tp, 0x13) & 0x0100) {
3615                 rtl_writephy(tp, 0x1f, 0x0c41);
3616                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3617         } else {
3618                 rtl_writephy(tp, 0x1f, 0x0c41);
3619                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3620         }
3621
3622         /* Enable PHY auto speed down */
3623         rtl_writephy(tp, 0x1f, 0x0a44);
3624         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3625
3626         rtl_writephy(tp, 0x1f, 0x0bcc);
3627         rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3628         rtl_writephy(tp, 0x1f, 0x0a44);
3629         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3630         rtl_writephy(tp, 0x1f, 0x0a43);
3631         rtl_writephy(tp, 0x13, 0x8084);
3632         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3633         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3634
3635         /* EEE auto-fallback function */
3636         rtl_writephy(tp, 0x1f, 0x0a4b);
3637         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3638
3639         /* Enable UC LPF tune function */
3640         rtl_writephy(tp, 0x1f, 0x0a43);
3641         rtl_writephy(tp, 0x13, 0x8012);
3642         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3643
3644         rtl_writephy(tp, 0x1f, 0x0c42);
3645         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3646
3647         /* Improve SWR Efficiency */
3648         rtl_writephy(tp, 0x1f, 0x0bcd);
3649         rtl_writephy(tp, 0x14, 0x5065);
3650         rtl_writephy(tp, 0x14, 0xd065);
3651         rtl_writephy(tp, 0x1f, 0x0bc8);
3652         rtl_writephy(tp, 0x11, 0x5655);
3653         rtl_writephy(tp, 0x1f, 0x0bcd);
3654         rtl_writephy(tp, 0x14, 0x1065);
3655         rtl_writephy(tp, 0x14, 0x9065);
3656         rtl_writephy(tp, 0x14, 0x1065);
3657
3658         /* Check ALDPS bit, disable it if enabled */
3659         rtl_writephy(tp, 0x1f, 0x0a43);
3660         if (rtl_readphy(tp, 0x10) & 0x0004)
3661                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3662
3663         rtl_writephy(tp, 0x1f, 0x0000);
3664 }
3665
3666 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3667 {
3668         rtl_apply_firmware(tp);
3669 }
3670
3671 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3672 {
3673         u16 dout_tapbin;
3674         u32 data;
3675
3676         rtl_apply_firmware(tp);
3677
3678         /* CHN EST parameters adjust - giga master */
3679         rtl_writephy(tp, 0x1f, 0x0a43);
3680         rtl_writephy(tp, 0x13, 0x809b);
3681         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3682         rtl_writephy(tp, 0x13, 0x80a2);
3683         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3684         rtl_writephy(tp, 0x13, 0x80a4);
3685         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3686         rtl_writephy(tp, 0x13, 0x809c);
3687         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3688         rtl_writephy(tp, 0x1f, 0x0000);
3689
3690         /* CHN EST parameters adjust - giga slave */
3691         rtl_writephy(tp, 0x1f, 0x0a43);
3692         rtl_writephy(tp, 0x13, 0x80ad);
3693         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3694         rtl_writephy(tp, 0x13, 0x80b4);
3695         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3696         rtl_writephy(tp, 0x13, 0x80ac);
3697         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3698         rtl_writephy(tp, 0x1f, 0x0000);
3699
3700         /* CHN EST parameters adjust - fnet */
3701         rtl_writephy(tp, 0x1f, 0x0a43);
3702         rtl_writephy(tp, 0x13, 0x808e);
3703         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3704         rtl_writephy(tp, 0x13, 0x8090);
3705         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3706         rtl_writephy(tp, 0x13, 0x8092);
3707         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3708         rtl_writephy(tp, 0x1f, 0x0000);
3709
3710         /* enable R-tune & PGA-retune function */
3711         dout_tapbin = 0;
3712         rtl_writephy(tp, 0x1f, 0x0a46);
3713         data = rtl_readphy(tp, 0x13);
3714         data &= 3;
3715         data <<= 2;
3716         dout_tapbin |= data;
3717         data = rtl_readphy(tp, 0x12);
3718         data &= 0xc000;
3719         data >>= 14;
3720         dout_tapbin |= data;
3721         dout_tapbin = ~(dout_tapbin^0x08);
3722         dout_tapbin <<= 12;
3723         dout_tapbin &= 0xf000;
3724         rtl_writephy(tp, 0x1f, 0x0a43);
3725         rtl_writephy(tp, 0x13, 0x827a);
3726         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3727         rtl_writephy(tp, 0x13, 0x827b);
3728         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3729         rtl_writephy(tp, 0x13, 0x827c);
3730         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3731         rtl_writephy(tp, 0x13, 0x827d);
3732         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3733
3734         rtl_writephy(tp, 0x1f, 0x0a43);
3735         rtl_writephy(tp, 0x13, 0x0811);
3736         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3737         rtl_writephy(tp, 0x1f, 0x0a42);
3738         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3739         rtl_writephy(tp, 0x1f, 0x0000);
3740
3741         /* enable GPHY 10M */
3742         rtl_writephy(tp, 0x1f, 0x0a44);
3743         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3744         rtl_writephy(tp, 0x1f, 0x0000);
3745
3746         /* SAR ADC performance */
3747         rtl_writephy(tp, 0x1f, 0x0bca);
3748         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3749         rtl_writephy(tp, 0x1f, 0x0000);
3750
3751         rtl_writephy(tp, 0x1f, 0x0a43);
3752         rtl_writephy(tp, 0x13, 0x803f);
3753         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3754         rtl_writephy(tp, 0x13, 0x8047);
3755         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3756         rtl_writephy(tp, 0x13, 0x804f);
3757         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3758         rtl_writephy(tp, 0x13, 0x8057);
3759         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3760         rtl_writephy(tp, 0x13, 0x805f);
3761         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3762         rtl_writephy(tp, 0x13, 0x8067);
3763         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3764         rtl_writephy(tp, 0x13, 0x806f);
3765         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3766         rtl_writephy(tp, 0x1f, 0x0000);
3767
3768         /* disable phy pfm mode */
3769         rtl_writephy(tp, 0x1f, 0x0a44);
3770         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3771         rtl_writephy(tp, 0x1f, 0x0000);
3772
3773         /* Check ALDPS bit, disable it if enabled */
3774         rtl_writephy(tp, 0x1f, 0x0a43);
3775         if (rtl_readphy(tp, 0x10) & 0x0004)
3776                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3777
3778         rtl_writephy(tp, 0x1f, 0x0000);
3779 }
3780
3781 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3782 {
3783         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3784         u16 rlen;
3785         u32 data;
3786
3787         rtl_apply_firmware(tp);
3788
3789         /* CHIN EST parameter update */
3790         rtl_writephy(tp, 0x1f, 0x0a43);
3791         rtl_writephy(tp, 0x13, 0x808a);
3792         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3793         rtl_writephy(tp, 0x1f, 0x0000);
3794
3795         /* enable R-tune & PGA-retune function */
3796         rtl_writephy(tp, 0x1f, 0x0a43);
3797         rtl_writephy(tp, 0x13, 0x0811);
3798         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3799         rtl_writephy(tp, 0x1f, 0x0a42);
3800         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3801         rtl_writephy(tp, 0x1f, 0x0000);
3802
3803         /* enable GPHY 10M */
3804         rtl_writephy(tp, 0x1f, 0x0a44);
3805         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3806         rtl_writephy(tp, 0x1f, 0x0000);
3807
3808         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3809         data = r8168_mac_ocp_read(tp, 0xdd02);
3810         ioffset_p3 = ((data & 0x80)>>7);
3811         ioffset_p3 <<= 3;
3812
3813         data = r8168_mac_ocp_read(tp, 0xdd00);
3814         ioffset_p3 |= ((data & (0xe000))>>13);
3815         ioffset_p2 = ((data & (0x1e00))>>9);
3816         ioffset_p1 = ((data & (0x01e0))>>5);
3817         ioffset_p0 = ((data & 0x0010)>>4);
3818         ioffset_p0 <<= 3;
3819         ioffset_p0 |= (data & (0x07));
3820         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3821
3822         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3823             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3824                 rtl_writephy(tp, 0x1f, 0x0bcf);
3825                 rtl_writephy(tp, 0x16, data);
3826                 rtl_writephy(tp, 0x1f, 0x0000);
3827         }
3828
3829         /* Modify rlen (TX LPF corner frequency) level */
3830         rtl_writephy(tp, 0x1f, 0x0bcd);
3831         data = rtl_readphy(tp, 0x16);
3832         data &= 0x000f;
3833         rlen = 0;
3834         if (data > 3)
3835                 rlen = data - 3;
3836         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3837         rtl_writephy(tp, 0x17, data);
3838         rtl_writephy(tp, 0x1f, 0x0bcd);
3839         rtl_writephy(tp, 0x1f, 0x0000);
3840
3841         /* disable phy pfm mode */
3842         rtl_writephy(tp, 0x1f, 0x0a44);
3843         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3844         rtl_writephy(tp, 0x1f, 0x0000);
3845
3846         /* Check ALDPS bit, disable it if enabled */
3847         rtl_writephy(tp, 0x1f, 0x0a43);
3848         if (rtl_readphy(tp, 0x10) & 0x0004)
3849                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3850
3851         rtl_writephy(tp, 0x1f, 0x0000);
3852 }
3853
3854 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3855 {
3856         /* Enable PHY auto speed down */
3857         rtl_writephy(tp, 0x1f, 0x0a44);
3858         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3859         rtl_writephy(tp, 0x1f, 0x0000);
3860
3861         /* patch 10M & ALDPS */
3862         rtl_writephy(tp, 0x1f, 0x0bcc);
3863         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3864         rtl_writephy(tp, 0x1f, 0x0a44);
3865         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3866         rtl_writephy(tp, 0x1f, 0x0a43);
3867         rtl_writephy(tp, 0x13, 0x8084);
3868         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3869         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3870         rtl_writephy(tp, 0x1f, 0x0000);
3871
3872         /* Enable EEE auto-fallback function */
3873         rtl_writephy(tp, 0x1f, 0x0a4b);
3874         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3875         rtl_writephy(tp, 0x1f, 0x0000);
3876
3877         /* Enable UC LPF tune function */
3878         rtl_writephy(tp, 0x1f, 0x0a43);
3879         rtl_writephy(tp, 0x13, 0x8012);
3880         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3881         rtl_writephy(tp, 0x1f, 0x0000);
3882
3883         /* set rg_sel_sdm_rate */
3884         rtl_writephy(tp, 0x1f, 0x0c42);
3885         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3886         rtl_writephy(tp, 0x1f, 0x0000);
3887
3888         /* Check ALDPS bit, disable it if enabled */
3889         rtl_writephy(tp, 0x1f, 0x0a43);
3890         if (rtl_readphy(tp, 0x10) & 0x0004)
3891                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3892
3893         rtl_writephy(tp, 0x1f, 0x0000);
3894 }
3895
3896 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3897 {
3898         /* patch 10M & ALDPS */
3899         rtl_writephy(tp, 0x1f, 0x0bcc);
3900         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3901         rtl_writephy(tp, 0x1f, 0x0a44);
3902         rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3903         rtl_writephy(tp, 0x1f, 0x0a43);
3904         rtl_writephy(tp, 0x13, 0x8084);
3905         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3906         rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3907         rtl_writephy(tp, 0x1f, 0x0000);
3908
3909         /* Enable UC LPF tune function */
3910         rtl_writephy(tp, 0x1f, 0x0a43);
3911         rtl_writephy(tp, 0x13, 0x8012);
3912         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3913         rtl_writephy(tp, 0x1f, 0x0000);
3914
3915         /* Set rg_sel_sdm_rate */
3916         rtl_writephy(tp, 0x1f, 0x0c42);
3917         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3918         rtl_writephy(tp, 0x1f, 0x0000);
3919
3920         /* Channel estimation parameters */
3921         rtl_writephy(tp, 0x1f, 0x0a43);
3922         rtl_writephy(tp, 0x13, 0x80f3);
3923         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3924         rtl_writephy(tp, 0x13, 0x80f0);
3925         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3926         rtl_writephy(tp, 0x13, 0x80ef);
3927         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3928         rtl_writephy(tp, 0x13, 0x80f6);
3929         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3930         rtl_writephy(tp, 0x13, 0x80ec);
3931         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3932         rtl_writephy(tp, 0x13, 0x80ed);
3933         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3934         rtl_writephy(tp, 0x13, 0x80f2);
3935         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3936         rtl_writephy(tp, 0x13, 0x80f4);
3937         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3938         rtl_writephy(tp, 0x1f, 0x0a43);
3939         rtl_writephy(tp, 0x13, 0x8110);
3940         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3941         rtl_writephy(tp, 0x13, 0x810f);
3942         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3943         rtl_writephy(tp, 0x13, 0x8111);
3944         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3945         rtl_writephy(tp, 0x13, 0x8113);
3946         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3947         rtl_writephy(tp, 0x13, 0x8115);
3948         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3949         rtl_writephy(tp, 0x13, 0x810e);
3950         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3951         rtl_writephy(tp, 0x13, 0x810c);
3952         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3953         rtl_writephy(tp, 0x13, 0x810b);
3954         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3955         rtl_writephy(tp, 0x1f, 0x0a43);
3956         rtl_writephy(tp, 0x13, 0x80d1);
3957         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3958         rtl_writephy(tp, 0x13, 0x80cd);
3959         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3960         rtl_writephy(tp, 0x13, 0x80d3);
3961         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3962         rtl_writephy(tp, 0x13, 0x80d5);
3963         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3964         rtl_writephy(tp, 0x13, 0x80d7);
3965         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3966
3967         /* Force PWM-mode */
3968         rtl_writephy(tp, 0x1f, 0x0bcd);
3969         rtl_writephy(tp, 0x14, 0x5065);
3970         rtl_writephy(tp, 0x14, 0xd065);
3971         rtl_writephy(tp, 0x1f, 0x0bc8);
3972         rtl_writephy(tp, 0x12, 0x00ed);
3973         rtl_writephy(tp, 0x1f, 0x0bcd);
3974         rtl_writephy(tp, 0x14, 0x1065);
3975         rtl_writephy(tp, 0x14, 0x9065);
3976         rtl_writephy(tp, 0x14, 0x1065);
3977         rtl_writephy(tp, 0x1f, 0x0000);
3978
3979         /* Check ALDPS bit, disable it if enabled */
3980         rtl_writephy(tp, 0x1f, 0x0a43);
3981         if (rtl_readphy(tp, 0x10) & 0x0004)
3982                 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3983
3984         rtl_writephy(tp, 0x1f, 0x0000);
3985 }
3986
3987 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3988 {
3989         static const struct phy_reg phy_reg_init[] = {
3990                 { 0x1f, 0x0003 },
3991                 { 0x08, 0x441d },
3992                 { 0x01, 0x9100 },
3993                 { 0x1f, 0x0000 }
3994         };
3995
3996         rtl_writephy(tp, 0x1f, 0x0000);
3997         rtl_patchphy(tp, 0x11, 1 << 12);
3998         rtl_patchphy(tp, 0x19, 1 << 13);
3999         rtl_patchphy(tp, 0x10, 1 << 15);
4000
4001         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4002 }
4003
4004 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4005 {
4006         static const struct phy_reg phy_reg_init[] = {
4007                 { 0x1f, 0x0005 },
4008                 { 0x1a, 0x0000 },
4009                 { 0x1f, 0x0000 },
4010
4011                 { 0x1f, 0x0004 },
4012                 { 0x1c, 0x0000 },
4013                 { 0x1f, 0x0000 },
4014
4015                 { 0x1f, 0x0001 },
4016                 { 0x15, 0x7701 },
4017                 { 0x1f, 0x0000 }
4018         };
4019
4020         /* Disable ALDPS before ram code */
4021         rtl_writephy(tp, 0x1f, 0x0000);
4022         rtl_writephy(tp, 0x18, 0x0310);
4023         msleep(100);
4024
4025         rtl_apply_firmware(tp);
4026
4027         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4028 }
4029
4030 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4031 {
4032         /* Disable ALDPS before setting firmware */
4033         rtl_writephy(tp, 0x1f, 0x0000);
4034         rtl_writephy(tp, 0x18, 0x0310);
4035         msleep(20);
4036
4037         rtl_apply_firmware(tp);
4038
4039         /* EEE setting */
4040         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4041         rtl_writephy(tp, 0x1f, 0x0004);
4042         rtl_writephy(tp, 0x10, 0x401f);
4043         rtl_writephy(tp, 0x19, 0x7030);
4044         rtl_writephy(tp, 0x1f, 0x0000);
4045 }
4046
4047 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4048 {
4049         static const struct phy_reg phy_reg_init[] = {
4050                 { 0x1f, 0x0004 },
4051                 { 0x10, 0xc07f },
4052                 { 0x19, 0x7030 },
4053                 { 0x1f, 0x0000 }
4054         };
4055
4056         /* Disable ALDPS before ram code */
4057         rtl_writephy(tp, 0x1f, 0x0000);
4058         rtl_writephy(tp, 0x18, 0x0310);
4059         msleep(100);
4060
4061         rtl_apply_firmware(tp);
4062
4063         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4064         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4065
4066         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4067 }
4068
4069 static void rtl_hw_phy_config(struct net_device *dev)
4070 {
4071         struct rtl8169_private *tp = netdev_priv(dev);
4072
4073         rtl8169_print_mac_version(tp);
4074
4075         switch (tp->mac_version) {
4076         case RTL_GIGA_MAC_VER_01:
4077                 break;
4078         case RTL_GIGA_MAC_VER_02:
4079         case RTL_GIGA_MAC_VER_03:
4080                 rtl8169s_hw_phy_config(tp);
4081                 break;
4082         case RTL_GIGA_MAC_VER_04:
4083                 rtl8169sb_hw_phy_config(tp);
4084                 break;
4085         case RTL_GIGA_MAC_VER_05:
4086                 rtl8169scd_hw_phy_config(tp);
4087                 break;
4088         case RTL_GIGA_MAC_VER_06:
4089                 rtl8169sce_hw_phy_config(tp);
4090                 break;
4091         case RTL_GIGA_MAC_VER_07:
4092         case RTL_GIGA_MAC_VER_08:
4093         case RTL_GIGA_MAC_VER_09:
4094                 rtl8102e_hw_phy_config(tp);
4095                 break;
4096         case RTL_GIGA_MAC_VER_11:
4097                 rtl8168bb_hw_phy_config(tp);
4098                 break;
4099         case RTL_GIGA_MAC_VER_12:
4100                 rtl8168bef_hw_phy_config(tp);
4101                 break;
4102         case RTL_GIGA_MAC_VER_17:
4103                 rtl8168bef_hw_phy_config(tp);
4104                 break;
4105         case RTL_GIGA_MAC_VER_18:
4106                 rtl8168cp_1_hw_phy_config(tp);
4107                 break;
4108         case RTL_GIGA_MAC_VER_19:
4109                 rtl8168c_1_hw_phy_config(tp);
4110                 break;
4111         case RTL_GIGA_MAC_VER_20:
4112                 rtl8168c_2_hw_phy_config(tp);
4113                 break;
4114         case RTL_GIGA_MAC_VER_21:
4115                 rtl8168c_3_hw_phy_config(tp);
4116                 break;
4117         case RTL_GIGA_MAC_VER_22:
4118                 rtl8168c_4_hw_phy_config(tp);
4119                 break;
4120         case RTL_GIGA_MAC_VER_23:
4121         case RTL_GIGA_MAC_VER_24:
4122                 rtl8168cp_2_hw_phy_config(tp);
4123                 break;
4124         case RTL_GIGA_MAC_VER_25:
4125                 rtl8168d_1_hw_phy_config(tp);
4126                 break;
4127         case RTL_GIGA_MAC_VER_26:
4128                 rtl8168d_2_hw_phy_config(tp);
4129                 break;
4130         case RTL_GIGA_MAC_VER_27:
4131                 rtl8168d_3_hw_phy_config(tp);
4132                 break;
4133         case RTL_GIGA_MAC_VER_28:
4134                 rtl8168d_4_hw_phy_config(tp);
4135                 break;
4136         case RTL_GIGA_MAC_VER_29:
4137         case RTL_GIGA_MAC_VER_30:
4138                 rtl8105e_hw_phy_config(tp);
4139                 break;
4140         case RTL_GIGA_MAC_VER_31:
4141                 /* None. */
4142                 break;
4143         case RTL_GIGA_MAC_VER_32:
4144         case RTL_GIGA_MAC_VER_33:
4145                 rtl8168e_1_hw_phy_config(tp);
4146                 break;
4147         case RTL_GIGA_MAC_VER_34:
4148                 rtl8168e_2_hw_phy_config(tp);
4149                 break;
4150         case RTL_GIGA_MAC_VER_35:
4151                 rtl8168f_1_hw_phy_config(tp);
4152                 break;
4153         case RTL_GIGA_MAC_VER_36:
4154                 rtl8168f_2_hw_phy_config(tp);
4155                 break;
4156
4157         case RTL_GIGA_MAC_VER_37:
4158                 rtl8402_hw_phy_config(tp);
4159                 break;
4160
4161         case RTL_GIGA_MAC_VER_38:
4162                 rtl8411_hw_phy_config(tp);
4163                 break;
4164
4165         case RTL_GIGA_MAC_VER_39:
4166                 rtl8106e_hw_phy_config(tp);
4167                 break;
4168
4169         case RTL_GIGA_MAC_VER_40:
4170                 rtl8168g_1_hw_phy_config(tp);
4171                 break;
4172         case RTL_GIGA_MAC_VER_42:
4173         case RTL_GIGA_MAC_VER_43:
4174         case RTL_GIGA_MAC_VER_44:
4175                 rtl8168g_2_hw_phy_config(tp);
4176                 break;
4177         case RTL_GIGA_MAC_VER_45:
4178         case RTL_GIGA_MAC_VER_47:
4179                 rtl8168h_1_hw_phy_config(tp);
4180                 break;
4181         case RTL_GIGA_MAC_VER_46:
4182         case RTL_GIGA_MAC_VER_48:
4183                 rtl8168h_2_hw_phy_config(tp);
4184                 break;
4185
4186         case RTL_GIGA_MAC_VER_49:
4187                 rtl8168ep_1_hw_phy_config(tp);
4188                 break;
4189         case RTL_GIGA_MAC_VER_50:
4190         case RTL_GIGA_MAC_VER_51:
4191                 rtl8168ep_2_hw_phy_config(tp);
4192                 break;
4193
4194         case RTL_GIGA_MAC_VER_41:
4195         default:
4196                 break;
4197         }
4198 }
4199
4200 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4201 {
4202         if (!test_and_set_bit(flag, tp->wk.flags))
4203                 schedule_work(&tp->wk.work);
4204 }
4205
4206 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4207 {
4208         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4209                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4210 }
4211
4212 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4213 {
4214         rtl_hw_phy_config(dev);
4215
4216         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4217                 netif_dbg(tp, drv, dev,
4218                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4219                 RTL_W8(tp, 0x82, 0x01);
4220         }
4221
4222         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4223
4224         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4225                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4226
4227         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4228                 netif_dbg(tp, drv, dev,
4229                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4230                 RTL_W8(tp, 0x82, 0x01);
4231                 netif_dbg(tp, drv, dev,
4232                           "Set PHY Reg 0x0bh = 0x00h\n");
4233                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4234         }
4235
4236         genphy_soft_reset(dev->phydev);
4237
4238         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4239                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4240                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4241                           (tp->mii.supports_gmii ?
4242                            ADVERTISED_1000baseT_Half |
4243                            ADVERTISED_1000baseT_Full : 0));
4244 }
4245
4246 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4247 {
4248         rtl_lock_work(tp);
4249
4250         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4251
4252         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4253         RTL_R32(tp, MAC4);
4254
4255         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4256         RTL_R32(tp, MAC0);
4257
4258         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4259                 rtl_rar_exgmac_set(tp, addr);
4260
4261         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4262
4263         rtl_unlock_work(tp);
4264 }
4265
4266 static int rtl_set_mac_address(struct net_device *dev, void *p)
4267 {
4268         struct rtl8169_private *tp = netdev_priv(dev);
4269         struct device *d = tp_to_dev(tp);
4270         int ret;
4271
4272         ret = eth_mac_addr(dev, p);
4273         if (ret)
4274                 return ret;
4275
4276         pm_runtime_get_noresume(d);
4277
4278         if (pm_runtime_active(d))
4279                 rtl_rar_set(tp, dev->dev_addr);
4280
4281         pm_runtime_put_noidle(d);
4282
4283         return 0;
4284 }
4285
4286 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4287                           struct mii_ioctl_data *data, int cmd)
4288 {
4289         switch (cmd) {
4290         case SIOCGMIIPHY:
4291                 data->phy_id = 32; /* Internal PHY */
4292                 return 0;
4293
4294         case SIOCGMIIREG:
4295                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4296                 return 0;
4297
4298         case SIOCSMIIREG:
4299                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4300                 return 0;
4301         }
4302         return -EOPNOTSUPP;
4303 }
4304
4305 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4306 {
4307         struct rtl8169_private *tp = netdev_priv(dev);
4308         struct mii_ioctl_data *data = if_mii(ifr);
4309
4310         return netif_running(dev) ? rtl_xmii_ioctl(tp, data, cmd) : -ENODEV;
4311 }
4312
4313 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4314 {
4315         struct mdio_ops *ops = &tp->mdio_ops;
4316
4317         switch (tp->mac_version) {
4318         case RTL_GIGA_MAC_VER_27:
4319                 ops->write      = r8168dp_1_mdio_write;
4320                 ops->read       = r8168dp_1_mdio_read;
4321                 break;
4322         case RTL_GIGA_MAC_VER_28:
4323         case RTL_GIGA_MAC_VER_31:
4324                 ops->write      = r8168dp_2_mdio_write;
4325                 ops->read       = r8168dp_2_mdio_read;
4326                 break;
4327         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4328                 ops->write      = r8168g_mdio_write;
4329                 ops->read       = r8168g_mdio_read;
4330                 break;
4331         default:
4332                 ops->write      = r8169_mdio_write;
4333                 ops->read       = r8169_mdio_read;
4334                 break;
4335         }
4336 }
4337
4338 static void rtl_speed_down(struct rtl8169_private *tp)
4339 {
4340         u32 adv;
4341         int lpa;
4342
4343         rtl_writephy(tp, 0x1f, 0x0000);
4344         lpa = rtl_readphy(tp, MII_LPA);
4345
4346         if (lpa & (LPA_10HALF | LPA_10FULL))
4347                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4348         else if (lpa & (LPA_100HALF | LPA_100FULL))
4349                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4350                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4351         else
4352                 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4353                       ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4354                       (tp->mii.supports_gmii ?
4355                        ADVERTISED_1000baseT_Half |
4356                        ADVERTISED_1000baseT_Full : 0);
4357
4358         rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4359                           adv);
4360 }
4361
4362 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4363 {
4364         switch (tp->mac_version) {
4365         case RTL_GIGA_MAC_VER_25:
4366         case RTL_GIGA_MAC_VER_26:
4367         case RTL_GIGA_MAC_VER_29:
4368         case RTL_GIGA_MAC_VER_30:
4369         case RTL_GIGA_MAC_VER_32:
4370         case RTL_GIGA_MAC_VER_33:
4371         case RTL_GIGA_MAC_VER_34:
4372         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4373                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4374                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4375                 break;
4376         default:
4377                 break;
4378         }
4379 }
4380
4381 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4382 {
4383         if (!netif_running(tp->dev) || !__rtl8169_get_wol(tp))
4384                 return false;
4385
4386         rtl_speed_down(tp);
4387         rtl_wol_suspend_quirk(tp);
4388
4389         return true;
4390 }
4391
4392 static void r8168_pll_power_down(struct rtl8169_private *tp)
4393 {
4394         if (r8168_check_dash(tp))
4395                 return;
4396
4397         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4398             tp->mac_version == RTL_GIGA_MAC_VER_33)
4399                 rtl_ephy_write(tp, 0x19, 0xff64);
4400
4401         if (rtl_wol_pll_power_down(tp))
4402                 return;
4403
4404         switch (tp->mac_version) {
4405         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4406         case RTL_GIGA_MAC_VER_37:
4407         case RTL_GIGA_MAC_VER_39:
4408         case RTL_GIGA_MAC_VER_43:
4409         case RTL_GIGA_MAC_VER_44:
4410         case RTL_GIGA_MAC_VER_45:
4411         case RTL_GIGA_MAC_VER_46:
4412         case RTL_GIGA_MAC_VER_47:
4413         case RTL_GIGA_MAC_VER_48:
4414         case RTL_GIGA_MAC_VER_50:
4415         case RTL_GIGA_MAC_VER_51:
4416                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4417                 break;
4418         case RTL_GIGA_MAC_VER_40:
4419         case RTL_GIGA_MAC_VER_41:
4420         case RTL_GIGA_MAC_VER_49:
4421                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4422                              0xfc000000, ERIAR_EXGMAC);
4423                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4424                 break;
4425         }
4426 }
4427
4428 static void r8168_pll_power_up(struct rtl8169_private *tp)
4429 {
4430         switch (tp->mac_version) {
4431         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4432         case RTL_GIGA_MAC_VER_37:
4433         case RTL_GIGA_MAC_VER_39:
4434         case RTL_GIGA_MAC_VER_43:
4435                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4436                 break;
4437         case RTL_GIGA_MAC_VER_44:
4438         case RTL_GIGA_MAC_VER_45:
4439         case RTL_GIGA_MAC_VER_46:
4440         case RTL_GIGA_MAC_VER_47:
4441         case RTL_GIGA_MAC_VER_48:
4442         case RTL_GIGA_MAC_VER_50:
4443         case RTL_GIGA_MAC_VER_51:
4444                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4445                 break;
4446         case RTL_GIGA_MAC_VER_40:
4447         case RTL_GIGA_MAC_VER_41:
4448         case RTL_GIGA_MAC_VER_49:
4449                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4450                 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4451                              0x00000000, ERIAR_EXGMAC);
4452                 break;
4453         }
4454
4455         phy_resume(tp->dev->phydev);
4456         /* give MAC/PHY some time to resume */
4457         msleep(20);
4458 }
4459
4460 static void rtl_pll_power_down(struct rtl8169_private *tp)
4461 {
4462         switch (tp->mac_version) {
4463         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4464         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4465                 break;
4466         default:
4467                 r8168_pll_power_down(tp);
4468         }
4469 }
4470
4471 static void rtl_pll_power_up(struct rtl8169_private *tp)
4472 {
4473         switch (tp->mac_version) {
4474         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4475         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4476                 break;
4477         default:
4478                 r8168_pll_power_up(tp);
4479         }
4480 }
4481
4482 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4483 {
4484         switch (tp->mac_version) {
4485         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4486         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4487                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4488                 break;
4489         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4490         case RTL_GIGA_MAC_VER_34:
4491         case RTL_GIGA_MAC_VER_35:
4492                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4493                 break;
4494         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4495                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4496                 break;
4497         default:
4498                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4499                 break;
4500         }
4501 }
4502
4503 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4504 {
4505         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4506 }
4507
4508 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4509 {
4510         if (tp->jumbo_ops.enable) {
4511                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4512                 tp->jumbo_ops.enable(tp);
4513                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4514         }
4515 }
4516
4517 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4518 {
4519         if (tp->jumbo_ops.disable) {
4520                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4521                 tp->jumbo_ops.disable(tp);
4522                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4523         }
4524 }
4525
4526 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4527 {
4528         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4529         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4530         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4531 }
4532
4533 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4534 {
4535         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4536         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4537         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4538 }
4539
4540 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4541 {
4542         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4543 }
4544
4545 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4546 {
4547         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4548 }
4549
4550 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4551 {
4552         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4553         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4554         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4555         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4556 }
4557
4558 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4559 {
4560         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4561         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4562         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4563         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4564 }
4565
4566 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4567 {
4568         rtl_tx_performance_tweak(tp,
4569                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4570 }
4571
4572 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4573 {
4574         rtl_tx_performance_tweak(tp,
4575                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4576 }
4577
4578 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4579 {
4580         r8168b_0_hw_jumbo_enable(tp);
4581
4582         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4583 }
4584
4585 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4586 {
4587         r8168b_0_hw_jumbo_disable(tp);
4588
4589         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4590 }
4591
4592 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4593 {
4594         struct jumbo_ops *ops = &tp->jumbo_ops;
4595
4596         switch (tp->mac_version) {
4597         case RTL_GIGA_MAC_VER_11:
4598                 ops->disable    = r8168b_0_hw_jumbo_disable;
4599                 ops->enable     = r8168b_0_hw_jumbo_enable;
4600                 break;
4601         case RTL_GIGA_MAC_VER_12:
4602         case RTL_GIGA_MAC_VER_17:
4603                 ops->disable    = r8168b_1_hw_jumbo_disable;
4604                 ops->enable     = r8168b_1_hw_jumbo_enable;
4605                 break;
4606         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4607         case RTL_GIGA_MAC_VER_19:
4608         case RTL_GIGA_MAC_VER_20:
4609         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4610         case RTL_GIGA_MAC_VER_22:
4611         case RTL_GIGA_MAC_VER_23:
4612         case RTL_GIGA_MAC_VER_24:
4613         case RTL_GIGA_MAC_VER_25:
4614         case RTL_GIGA_MAC_VER_26:
4615                 ops->disable    = r8168c_hw_jumbo_disable;
4616                 ops->enable     = r8168c_hw_jumbo_enable;
4617                 break;
4618         case RTL_GIGA_MAC_VER_27:
4619         case RTL_GIGA_MAC_VER_28:
4620                 ops->disable    = r8168dp_hw_jumbo_disable;
4621                 ops->enable     = r8168dp_hw_jumbo_enable;
4622                 break;
4623         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4624         case RTL_GIGA_MAC_VER_32:
4625         case RTL_GIGA_MAC_VER_33:
4626         case RTL_GIGA_MAC_VER_34:
4627                 ops->disable    = r8168e_hw_jumbo_disable;
4628                 ops->enable     = r8168e_hw_jumbo_enable;
4629                 break;
4630
4631         /*
4632          * No action needed for jumbo frames with 8169.
4633          * No jumbo for 810x at all.
4634          */
4635         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4636         default:
4637                 ops->disable    = NULL;
4638                 ops->enable     = NULL;
4639                 break;
4640         }
4641 }
4642
4643 DECLARE_RTL_COND(rtl_chipcmd_cond)
4644 {
4645         return RTL_R8(tp, ChipCmd) & CmdReset;
4646 }
4647
4648 static void rtl_hw_reset(struct rtl8169_private *tp)
4649 {
4650         RTL_W8(tp, ChipCmd, CmdReset);
4651
4652         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4653 }
4654
4655 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4656 {
4657         struct rtl_fw *rtl_fw;
4658         const char *name;
4659         int rc = -ENOMEM;
4660
4661         name = rtl_lookup_firmware_name(tp);
4662         if (!name)
4663                 goto out_no_firmware;
4664
4665         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4666         if (!rtl_fw)
4667                 goto err_warn;
4668
4669         rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4670         if (rc < 0)
4671                 goto err_free;
4672
4673         rc = rtl_check_firmware(tp, rtl_fw);
4674         if (rc < 0)
4675                 goto err_release_firmware;
4676
4677         tp->rtl_fw = rtl_fw;
4678 out:
4679         return;
4680
4681 err_release_firmware:
4682         release_firmware(rtl_fw->fw);
4683 err_free:
4684         kfree(rtl_fw);
4685 err_warn:
4686         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4687                    name, rc);
4688 out_no_firmware:
4689         tp->rtl_fw = NULL;
4690         goto out;
4691 }
4692
4693 static void rtl_request_firmware(struct rtl8169_private *tp)
4694 {
4695         if (IS_ERR(tp->rtl_fw))
4696                 rtl_request_uncached_firmware(tp);
4697 }
4698
4699 static void rtl_rx_close(struct rtl8169_private *tp)
4700 {
4701         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4702 }
4703
4704 DECLARE_RTL_COND(rtl_npq_cond)
4705 {
4706         return RTL_R8(tp, TxPoll) & NPQ;
4707 }
4708
4709 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4710 {
4711         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4712 }
4713
4714 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4715 {
4716         /* Disable interrupts */
4717         rtl8169_irq_mask_and_ack(tp);
4718
4719         rtl_rx_close(tp);
4720
4721         switch (tp->mac_version) {
4722         case RTL_GIGA_MAC_VER_27:
4723         case RTL_GIGA_MAC_VER_28:
4724         case RTL_GIGA_MAC_VER_31:
4725                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4726                 break;
4727         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4728         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4729                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4730                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4731                 break;
4732         default:
4733                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4734                 udelay(100);
4735                 break;
4736         }
4737
4738         rtl_hw_reset(tp);
4739 }
4740
4741 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4742 {
4743         /* Set DMA burst size and Interframe Gap Time */
4744         RTL_W32(tp, TxConfig, (TX_DMA_BURST << TxDMAShift) |
4745                 (InterFrameGap << TxInterFrameGapShift));
4746 }
4747
4748 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4749 {
4750         /* Low hurts. Let's disable the filtering. */
4751         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4752 }
4753
4754 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4755 {
4756         /*
4757          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4758          * register to be written before TxDescAddrLow to work.
4759          * Switching from MMIO to I/O access fixes the issue as well.
4760          */
4761         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4762         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4763         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4764         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4765 }
4766
4767 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4768 {
4769         static const struct rtl_cfg2_info {
4770                 u32 mac_version;
4771                 u32 clk;
4772                 u32 val;
4773         } cfg2_info [] = {
4774                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4775                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4776                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4777                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4778         };
4779         const struct rtl_cfg2_info *p = cfg2_info;
4780         unsigned int i;
4781         u32 clk;
4782
4783         clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4784         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4785                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4786                         RTL_W32(tp, 0x7c, p->val);
4787                         break;
4788                 }
4789         }
4790 }
4791
4792 static void rtl_set_rx_mode(struct net_device *dev)
4793 {
4794         struct rtl8169_private *tp = netdev_priv(dev);
4795         u32 mc_filter[2];       /* Multicast hash filter */
4796         int rx_mode;
4797         u32 tmp = 0;
4798
4799         if (dev->flags & IFF_PROMISC) {
4800                 /* Unconditionally log net taps. */
4801                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4802                 rx_mode =
4803                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4804                     AcceptAllPhys;
4805                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4806         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4807                    (dev->flags & IFF_ALLMULTI)) {
4808                 /* Too many to filter perfectly -- accept all multicasts. */
4809                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4810                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4811         } else {
4812                 struct netdev_hw_addr *ha;
4813
4814                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4815                 mc_filter[1] = mc_filter[0] = 0;
4816                 netdev_for_each_mc_addr(ha, dev) {
4817                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4818                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4819                         rx_mode |= AcceptMulticast;
4820                 }
4821         }
4822
4823         if (dev->features & NETIF_F_RXALL)
4824                 rx_mode |= (AcceptErr | AcceptRunt);
4825
4826         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4827
4828         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4829                 u32 data = mc_filter[0];
4830
4831                 mc_filter[0] = swab32(mc_filter[1]);
4832                 mc_filter[1] = swab32(data);
4833         }
4834
4835         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4836                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4837
4838         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4839         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4840
4841         RTL_W32(tp, RxConfig, tmp);
4842 }
4843
4844 static void rtl_hw_start(struct  rtl8169_private *tp)
4845 {
4846         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4847
4848         tp->hw_start(tp);
4849
4850         rtl_set_rx_max_size(tp);
4851         rtl_set_rx_tx_desc_registers(tp);
4852         rtl_set_rx_tx_config_registers(tp);
4853         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4854
4855         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4856         RTL_R8(tp, IntrMask);
4857         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4858         rtl_set_rx_mode(tp->dev);
4859         /* no early-rx interrupts */
4860         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4861         rtl_irq_enable_all(tp);
4862 }
4863
4864 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4865 {
4866         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4867                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4868
4869         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4870
4871         tp->cp_cmd |= PCIMulRW;
4872
4873         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4874             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4875                 netif_dbg(tp, drv, tp->dev,
4876                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4877                 tp->cp_cmd |= (1 << 14);
4878         }
4879
4880         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4881
4882         rtl8169_set_magic_reg(tp, tp->mac_version);
4883
4884         /*
4885          * Undocumented corner. Supposedly:
4886          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4887          */
4888         RTL_W16(tp, IntrMitigate, 0x0000);
4889
4890         RTL_W32(tp, RxMissed, 0);
4891 }
4892
4893 DECLARE_RTL_COND(rtl_csiar_cond)
4894 {
4895         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4896 }
4897
4898 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4899 {
4900         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4901
4902         RTL_W32(tp, CSIDR, value);
4903         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4904                 CSIAR_BYTE_ENABLE | func << 16);
4905
4906         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4907 }
4908
4909 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4910 {
4911         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4912
4913         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4914                 CSIAR_BYTE_ENABLE);
4915
4916         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4917                 RTL_R32(tp, CSIDR) : ~0;
4918 }
4919
4920 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4921 {
4922         struct pci_dev *pdev = tp->pci_dev;
4923         u32 csi;
4924
4925         /* According to Realtek the value at config space address 0x070f
4926          * controls the L0s/L1 entrance latency. We try standard ECAM access
4927          * first and if it fails fall back to CSI.
4928          */
4929         if (pdev->cfg_size > 0x070f &&
4930             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4931                 return;
4932
4933         netdev_notice_once(tp->dev,
4934                 "No native access to PCI extended config space, falling back to CSI\n");
4935         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4936         rtl_csi_write(tp, 0x070c, csi | val << 24);
4937 }
4938
4939 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4940 {
4941         rtl_csi_access_enable(tp, 0x27);
4942 }
4943
4944 struct ephy_info {
4945         unsigned int offset;
4946         u16 mask;
4947         u16 bits;
4948 };
4949
4950 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4951                           int len)
4952 {
4953         u16 w;
4954
4955         while (len-- > 0) {
4956                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4957                 rtl_ephy_write(tp, e->offset, w);
4958                 e++;
4959         }
4960 }
4961
4962 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4963 {
4964         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4965                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4966 }
4967
4968 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4969 {
4970         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4971                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4972 }
4973
4974 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4975 {
4976         u8 data;
4977
4978         data = RTL_R8(tp, Config3);
4979
4980         if (enable)
4981                 data |= Rdy_to_L23;
4982         else
4983                 data &= ~Rdy_to_L23;
4984
4985         RTL_W8(tp, Config3, data);
4986 }
4987
4988 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4989 {
4990         if (enable) {
4991                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4992                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4993         } else {
4994                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4995                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4996         }
4997 }
4998
4999 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5000 {
5001         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5002
5003         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5004         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5005
5006         if (tp->dev->mtu <= ETH_DATA_LEN) {
5007                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
5008                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5009         }
5010 }
5011
5012 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5013 {
5014         rtl_hw_start_8168bb(tp);
5015
5016         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5017
5018         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5019 }
5020
5021 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5022 {
5023         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
5024
5025         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5026
5027         if (tp->dev->mtu <= ETH_DATA_LEN)
5028                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5029
5030         rtl_disable_clock_request(tp);
5031
5032         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5033         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5034 }
5035
5036 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5037 {
5038         static const struct ephy_info e_info_8168cp[] = {
5039                 { 0x01, 0,      0x0001 },
5040                 { 0x02, 0x0800, 0x1000 },
5041                 { 0x03, 0,      0x0042 },
5042                 { 0x06, 0x0080, 0x0000 },
5043                 { 0x07, 0,      0x2000 }
5044         };
5045
5046         rtl_set_def_aspm_entry_latency(tp);
5047
5048         rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5049
5050         __rtl_hw_start_8168cp(tp);
5051 }
5052
5053 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5054 {
5055         rtl_set_def_aspm_entry_latency(tp);
5056
5057         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5058
5059         if (tp->dev->mtu <= ETH_DATA_LEN)
5060                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5061
5062         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5063         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5064 }
5065
5066 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5067 {
5068         rtl_set_def_aspm_entry_latency(tp);
5069
5070         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5071
5072         /* Magic. */
5073         RTL_W8(tp, DBG_REG, 0x20);
5074
5075         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5076
5077         if (tp->dev->mtu <= ETH_DATA_LEN)
5078                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5079
5080         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5081         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5082 }
5083
5084 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5085 {
5086         static const struct ephy_info e_info_8168c_1[] = {
5087                 { 0x02, 0x0800, 0x1000 },
5088                 { 0x03, 0,      0x0002 },
5089                 { 0x06, 0x0080, 0x0000 }
5090         };
5091
5092         rtl_set_def_aspm_entry_latency(tp);
5093
5094         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5095
5096         rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5097
5098         __rtl_hw_start_8168cp(tp);
5099 }
5100
5101 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5102 {
5103         static const struct ephy_info e_info_8168c_2[] = {
5104                 { 0x01, 0,      0x0001 },
5105                 { 0x03, 0x0400, 0x0220 }
5106         };
5107
5108         rtl_set_def_aspm_entry_latency(tp);
5109
5110         rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5111
5112         __rtl_hw_start_8168cp(tp);
5113 }
5114
5115 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5116 {
5117         rtl_hw_start_8168c_2(tp);
5118 }
5119
5120 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5121 {
5122         rtl_set_def_aspm_entry_latency(tp);
5123
5124         __rtl_hw_start_8168cp(tp);
5125 }
5126
5127 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5128 {
5129         rtl_set_def_aspm_entry_latency(tp);
5130
5131         rtl_disable_clock_request(tp);
5132
5133         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5134
5135         if (tp->dev->mtu <= ETH_DATA_LEN)
5136                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5137
5138         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5139         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5140 }
5141
5142 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5143 {
5144         rtl_set_def_aspm_entry_latency(tp);
5145
5146         if (tp->dev->mtu <= ETH_DATA_LEN)
5147                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5148
5149         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5150
5151         rtl_disable_clock_request(tp);
5152 }
5153
5154 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5155 {
5156         static const struct ephy_info e_info_8168d_4[] = {
5157                 { 0x0b, 0x0000, 0x0048 },
5158                 { 0x19, 0x0020, 0x0050 },
5159                 { 0x0c, 0x0100, 0x0020 }
5160         };
5161
5162         rtl_set_def_aspm_entry_latency(tp);
5163
5164         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5165
5166         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5167
5168         rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
5169
5170         rtl_enable_clock_request(tp);
5171 }
5172
5173 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5174 {
5175         static const struct ephy_info e_info_8168e_1[] = {
5176                 { 0x00, 0x0200, 0x0100 },
5177                 { 0x00, 0x0000, 0x0004 },
5178                 { 0x06, 0x0002, 0x0001 },
5179                 { 0x06, 0x0000, 0x0030 },
5180                 { 0x07, 0x0000, 0x2000 },
5181                 { 0x00, 0x0000, 0x0020 },
5182                 { 0x03, 0x5800, 0x2000 },
5183                 { 0x03, 0x0000, 0x0001 },
5184                 { 0x01, 0x0800, 0x1000 },
5185                 { 0x07, 0x0000, 0x4000 },
5186                 { 0x1e, 0x0000, 0x2000 },
5187                 { 0x19, 0xffff, 0xfe6c },
5188                 { 0x0a, 0x0000, 0x0040 }
5189         };
5190
5191         rtl_set_def_aspm_entry_latency(tp);
5192
5193         rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5194
5195         if (tp->dev->mtu <= ETH_DATA_LEN)
5196                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5197
5198         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5199
5200         rtl_disable_clock_request(tp);
5201
5202         /* Reset tx FIFO pointer */
5203         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5204         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5205
5206         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5207 }
5208
5209 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5210 {
5211         static const struct ephy_info e_info_8168e_2[] = {
5212                 { 0x09, 0x0000, 0x0080 },
5213                 { 0x19, 0x0000, 0x0224 }
5214         };
5215
5216         rtl_set_def_aspm_entry_latency(tp);
5217
5218         rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5219
5220         if (tp->dev->mtu <= ETH_DATA_LEN)
5221                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5222
5223         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5224         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5225         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5226         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5227         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5228         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5229         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5230         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5231
5232         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5233
5234         rtl_disable_clock_request(tp);
5235
5236         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5237         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5238
5239         /* Adjust EEE LED frequency */
5240         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5241
5242         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5243         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5244         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5245
5246         rtl_hw_aspm_clkreq_enable(tp, true);
5247 }
5248
5249 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5250 {
5251         rtl_set_def_aspm_entry_latency(tp);
5252
5253         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5254
5255         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5256         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5257         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5258         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5259         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5260         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5261         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5262         rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5263         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5264         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5265
5266         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5267
5268         rtl_disable_clock_request(tp);
5269
5270         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5271         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5272         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5273         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5274         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5275 }
5276
5277 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5278 {
5279         static const struct ephy_info e_info_8168f_1[] = {
5280                 { 0x06, 0x00c0, 0x0020 },
5281                 { 0x08, 0x0001, 0x0002 },
5282                 { 0x09, 0x0000, 0x0080 },
5283                 { 0x19, 0x0000, 0x0224 }
5284         };
5285
5286         rtl_hw_start_8168f(tp);
5287
5288         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5289
5290         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5291
5292         /* Adjust EEE LED frequency */
5293         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5294 }
5295
5296 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5297 {
5298         static const struct ephy_info e_info_8168f_1[] = {
5299                 { 0x06, 0x00c0, 0x0020 },
5300                 { 0x0f, 0xffff, 0x5200 },
5301                 { 0x1e, 0x0000, 0x4000 },
5302                 { 0x19, 0x0000, 0x0224 }
5303         };
5304
5305         rtl_hw_start_8168f(tp);
5306         rtl_pcie_state_l2l3_enable(tp, false);
5307
5308         rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5309
5310         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5311 }
5312
5313 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5314 {
5315         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5316
5317         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5318         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5319         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5320         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5321
5322         rtl_set_def_aspm_entry_latency(tp);
5323
5324         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5325
5326         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5327         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5328         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5329
5330         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5331         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5332
5333         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5334         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5335
5336         /* Adjust EEE LED frequency */
5337         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5338
5339         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5340         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5341
5342         rtl_pcie_state_l2l3_enable(tp, false);
5343 }
5344
5345 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5346 {
5347         static const struct ephy_info e_info_8168g_1[] = {
5348                 { 0x00, 0x0000, 0x0008 },
5349                 { 0x0c, 0x37d0, 0x0820 },
5350                 { 0x1e, 0x0000, 0x0001 },
5351                 { 0x19, 0x8000, 0x0000 }
5352         };
5353
5354         rtl_hw_start_8168g(tp);
5355
5356         /* disable aspm and clock request before access ephy */
5357         rtl_hw_aspm_clkreq_enable(tp, false);
5358         rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5359         rtl_hw_aspm_clkreq_enable(tp, true);
5360 }
5361
5362 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5363 {
5364         static const struct ephy_info e_info_8168g_2[] = {
5365                 { 0x00, 0x0000, 0x0008 },
5366                 { 0x0c, 0x3df0, 0x0200 },
5367                 { 0x19, 0xffff, 0xfc00 },
5368                 { 0x1e, 0xffff, 0x20eb }
5369         };
5370
5371         rtl_hw_start_8168g(tp);
5372
5373         /* disable aspm and clock request before access ephy */
5374         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5375         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5376         rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5377 }
5378
5379 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5380 {
5381         static const struct ephy_info e_info_8411_2[] = {
5382                 { 0x00, 0x0000, 0x0008 },
5383                 { 0x0c, 0x3df0, 0x0200 },
5384                 { 0x0f, 0xffff, 0x5200 },
5385                 { 0x19, 0x0020, 0x0000 },
5386                 { 0x1e, 0x0000, 0x2000 }
5387         };
5388
5389         rtl_hw_start_8168g(tp);
5390
5391         /* disable aspm and clock request before access ephy */
5392         rtl_hw_aspm_clkreq_enable(tp, false);
5393         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5394         rtl_hw_aspm_clkreq_enable(tp, true);
5395 }
5396
5397 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5398 {
5399         int rg_saw_cnt;
5400         u32 data;
5401         static const struct ephy_info e_info_8168h_1[] = {
5402                 { 0x1e, 0x0800, 0x0001 },
5403                 { 0x1d, 0x0000, 0x0800 },
5404                 { 0x05, 0xffff, 0x2089 },
5405                 { 0x06, 0xffff, 0x5881 },
5406                 { 0x04, 0xffff, 0x154a },
5407                 { 0x01, 0xffff, 0x068b }
5408         };
5409
5410         /* disable aspm and clock request before access ephy */
5411         rtl_hw_aspm_clkreq_enable(tp, false);
5412         rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5413
5414         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5415
5416         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5417         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5418         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5419         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5420
5421         rtl_set_def_aspm_entry_latency(tp);
5422
5423         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5424
5425         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5426         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5427
5428         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5429
5430         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5431
5432         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5433
5434         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5435         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5436
5437         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5438         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5439
5440         /* Adjust EEE LED frequency */
5441         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5442
5443         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5444         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5445
5446         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5447
5448         rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5449
5450         rtl_pcie_state_l2l3_enable(tp, false);
5451
5452         rtl_writephy(tp, 0x1f, 0x0c42);
5453         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5454         rtl_writephy(tp, 0x1f, 0x0000);
5455         if (rg_saw_cnt > 0) {
5456                 u16 sw_cnt_1ms_ini;
5457
5458                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5459                 sw_cnt_1ms_ini &= 0x0fff;
5460                 data = r8168_mac_ocp_read(tp, 0xd412);
5461                 data &= ~0x0fff;
5462                 data |= sw_cnt_1ms_ini;
5463                 r8168_mac_ocp_write(tp, 0xd412, data);
5464         }
5465
5466         data = r8168_mac_ocp_read(tp, 0xe056);
5467         data &= ~0xf0;
5468         data |= 0x70;
5469         r8168_mac_ocp_write(tp, 0xe056, data);
5470
5471         data = r8168_mac_ocp_read(tp, 0xe052);
5472         data &= ~0x6000;
5473         data |= 0x8008;
5474         r8168_mac_ocp_write(tp, 0xe052, data);
5475
5476         data = r8168_mac_ocp_read(tp, 0xe0d6);
5477         data &= ~0x01ff;
5478         data |= 0x017f;
5479         r8168_mac_ocp_write(tp, 0xe0d6, data);
5480
5481         data = r8168_mac_ocp_read(tp, 0xd420);
5482         data &= ~0x0fff;
5483         data |= 0x047f;
5484         r8168_mac_ocp_write(tp, 0xd420, data);
5485
5486         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5487         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5488         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5489         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5490
5491         rtl_hw_aspm_clkreq_enable(tp, true);
5492 }
5493
5494 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5495 {
5496         rtl8168ep_stop_cmac(tp);
5497
5498         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5499
5500         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5501         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5502         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5503         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5504
5505         rtl_set_def_aspm_entry_latency(tp);
5506
5507         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5508
5509         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5510         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5511
5512         rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5513
5514         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5515
5516         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5517         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5518
5519         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5520         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5521
5522         /* Adjust EEE LED frequency */
5523         RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5524
5525         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5526
5527         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5528
5529         rtl_pcie_state_l2l3_enable(tp, false);
5530 }
5531
5532 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5533 {
5534         static const struct ephy_info e_info_8168ep_1[] = {
5535                 { 0x00, 0xffff, 0x10ab },
5536                 { 0x06, 0xffff, 0xf030 },
5537                 { 0x08, 0xffff, 0x2006 },
5538                 { 0x0d, 0xffff, 0x1666 },
5539                 { 0x0c, 0x3ff0, 0x0000 }
5540         };
5541
5542         /* disable aspm and clock request before access ephy */
5543         rtl_hw_aspm_clkreq_enable(tp, false);
5544         rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5545
5546         rtl_hw_start_8168ep(tp);
5547
5548         rtl_hw_aspm_clkreq_enable(tp, true);
5549 }
5550
5551 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5552 {
5553         static const struct ephy_info e_info_8168ep_2[] = {
5554                 { 0x00, 0xffff, 0x10a3 },
5555                 { 0x19, 0xffff, 0xfc00 },
5556                 { 0x1e, 0xffff, 0x20ea }
5557         };
5558
5559         /* disable aspm and clock request before access ephy */
5560         rtl_hw_aspm_clkreq_enable(tp, false);
5561         rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5562
5563         rtl_hw_start_8168ep(tp);
5564
5565         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5566         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5567
5568         rtl_hw_aspm_clkreq_enable(tp, true);
5569 }
5570
5571 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5572 {
5573         u32 data;
5574         static const struct ephy_info e_info_8168ep_3[] = {
5575                 { 0x00, 0xffff, 0x10a3 },
5576                 { 0x19, 0xffff, 0x7c00 },
5577                 { 0x1e, 0xffff, 0x20eb },
5578                 { 0x0d, 0xffff, 0x1666 }
5579         };
5580
5581         /* disable aspm and clock request before access ephy */
5582         rtl_hw_aspm_clkreq_enable(tp, false);
5583         rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5584
5585         rtl_hw_start_8168ep(tp);
5586
5587         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5588         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5589
5590         data = r8168_mac_ocp_read(tp, 0xd3e2);
5591         data &= 0xf000;
5592         data |= 0x0271;
5593         r8168_mac_ocp_write(tp, 0xd3e2, data);
5594
5595         data = r8168_mac_ocp_read(tp, 0xd3e4);
5596         data &= 0xff00;
5597         r8168_mac_ocp_write(tp, 0xd3e4, data);
5598
5599         data = r8168_mac_ocp_read(tp, 0xe860);
5600         data |= 0x0080;
5601         r8168_mac_ocp_write(tp, 0xe860, data);
5602
5603         rtl_hw_aspm_clkreq_enable(tp, true);
5604 }
5605
5606 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5607 {
5608         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5609
5610         tp->cp_cmd &= ~INTT_MASK;
5611         tp->cp_cmd |= PktCntrDisable | INTT_1;
5612         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5613
5614         RTL_W16(tp, IntrMitigate, 0x5151);
5615
5616         /* Work around for RxFIFO overflow. */
5617         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5618                 tp->event_slow |= RxFIFOOver | PCSTimeout;
5619                 tp->event_slow &= ~RxOverflow;
5620         }
5621
5622         switch (tp->mac_version) {
5623         case RTL_GIGA_MAC_VER_11:
5624                 rtl_hw_start_8168bb(tp);
5625                 break;
5626
5627         case RTL_GIGA_MAC_VER_12:
5628         case RTL_GIGA_MAC_VER_17:
5629                 rtl_hw_start_8168bef(tp);
5630                 break;
5631
5632         case RTL_GIGA_MAC_VER_18:
5633                 rtl_hw_start_8168cp_1(tp);
5634                 break;
5635
5636         case RTL_GIGA_MAC_VER_19:
5637                 rtl_hw_start_8168c_1(tp);
5638                 break;
5639
5640         case RTL_GIGA_MAC_VER_20:
5641                 rtl_hw_start_8168c_2(tp);
5642                 break;
5643
5644         case RTL_GIGA_MAC_VER_21:
5645                 rtl_hw_start_8168c_3(tp);
5646                 break;
5647
5648         case RTL_GIGA_MAC_VER_22:
5649                 rtl_hw_start_8168c_4(tp);
5650                 break;
5651
5652         case RTL_GIGA_MAC_VER_23:
5653                 rtl_hw_start_8168cp_2(tp);
5654                 break;
5655
5656         case RTL_GIGA_MAC_VER_24:
5657                 rtl_hw_start_8168cp_3(tp);
5658                 break;
5659
5660         case RTL_GIGA_MAC_VER_25:
5661         case RTL_GIGA_MAC_VER_26:
5662         case RTL_GIGA_MAC_VER_27:
5663                 rtl_hw_start_8168d(tp);
5664                 break;
5665
5666         case RTL_GIGA_MAC_VER_28:
5667                 rtl_hw_start_8168d_4(tp);
5668                 break;
5669
5670         case RTL_GIGA_MAC_VER_31:
5671                 rtl_hw_start_8168dp(tp);
5672                 break;
5673
5674         case RTL_GIGA_MAC_VER_32:
5675         case RTL_GIGA_MAC_VER_33:
5676                 rtl_hw_start_8168e_1(tp);
5677                 break;
5678         case RTL_GIGA_MAC_VER_34:
5679                 rtl_hw_start_8168e_2(tp);
5680                 break;
5681
5682         case RTL_GIGA_MAC_VER_35:
5683         case RTL_GIGA_MAC_VER_36:
5684                 rtl_hw_start_8168f_1(tp);
5685                 break;
5686
5687         case RTL_GIGA_MAC_VER_38:
5688                 rtl_hw_start_8411(tp);
5689                 break;
5690
5691         case RTL_GIGA_MAC_VER_40:
5692         case RTL_GIGA_MAC_VER_41:
5693                 rtl_hw_start_8168g_1(tp);
5694                 break;
5695         case RTL_GIGA_MAC_VER_42:
5696                 rtl_hw_start_8168g_2(tp);
5697                 break;
5698
5699         case RTL_GIGA_MAC_VER_44:
5700                 rtl_hw_start_8411_2(tp);
5701                 break;
5702
5703         case RTL_GIGA_MAC_VER_45:
5704         case RTL_GIGA_MAC_VER_46:
5705                 rtl_hw_start_8168h_1(tp);
5706                 break;
5707
5708         case RTL_GIGA_MAC_VER_49:
5709                 rtl_hw_start_8168ep_1(tp);
5710                 break;
5711
5712         case RTL_GIGA_MAC_VER_50:
5713                 rtl_hw_start_8168ep_2(tp);
5714                 break;
5715
5716         case RTL_GIGA_MAC_VER_51:
5717                 rtl_hw_start_8168ep_3(tp);
5718                 break;
5719
5720         default:
5721                 netif_err(tp, drv, tp->dev,
5722                           "unknown chipset (mac_version = %d)\n",
5723                           tp->mac_version);
5724                 break;
5725         }
5726 }
5727
5728 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5729 {
5730         static const struct ephy_info e_info_8102e_1[] = {
5731                 { 0x01, 0, 0x6e65 },
5732                 { 0x02, 0, 0x091f },
5733                 { 0x03, 0, 0xc2f9 },
5734                 { 0x06, 0, 0xafb5 },
5735                 { 0x07, 0, 0x0e00 },
5736                 { 0x19, 0, 0xec80 },
5737                 { 0x01, 0, 0x2e65 },
5738                 { 0x01, 0, 0x6e65 }
5739         };
5740         u8 cfg1;
5741
5742         rtl_set_def_aspm_entry_latency(tp);
5743
5744         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5745
5746         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5747
5748         RTL_W8(tp, Config1,
5749                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5750         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5751
5752         cfg1 = RTL_R8(tp, Config1);
5753         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5754                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5755
5756         rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5757 }
5758
5759 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5760 {
5761         rtl_set_def_aspm_entry_latency(tp);
5762
5763         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5764
5765         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5766         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5767 }
5768
5769 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5770 {
5771         rtl_hw_start_8102e_2(tp);
5772
5773         rtl_ephy_write(tp, 0x03, 0xc2f9);
5774 }
5775
5776 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5777 {
5778         static const struct ephy_info e_info_8105e_1[] = {
5779                 { 0x07, 0, 0x4000 },
5780                 { 0x19, 0, 0x0200 },
5781                 { 0x19, 0, 0x0020 },
5782                 { 0x1e, 0, 0x2000 },
5783                 { 0x03, 0, 0x0001 },
5784                 { 0x19, 0, 0x0100 },
5785                 { 0x19, 0, 0x0004 },
5786                 { 0x0a, 0, 0x0020 }
5787         };
5788
5789         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5790         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5791
5792         /* Disable Early Tally Counter */
5793         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5794
5795         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5796         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5797
5798         rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5799
5800         rtl_pcie_state_l2l3_enable(tp, false);
5801 }
5802
5803 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5804 {
5805         rtl_hw_start_8105e_1(tp);
5806         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5807 }
5808
5809 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5810 {
5811         static const struct ephy_info e_info_8402[] = {
5812                 { 0x19, 0xffff, 0xff64 },
5813                 { 0x1e, 0, 0x4000 }
5814         };
5815
5816         rtl_set_def_aspm_entry_latency(tp);
5817
5818         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5819         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5820
5821         RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | TXCFG_AUTO_FIFO);
5822         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5823
5824         rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5825
5826         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5827
5828         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5829         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5830         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5831         rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5832         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5833         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5834         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5835
5836         rtl_pcie_state_l2l3_enable(tp, false);
5837 }
5838
5839 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5840 {
5841         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5842         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5843
5844         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5845         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5846         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5847
5848         rtl_pcie_state_l2l3_enable(tp, false);
5849 }
5850
5851 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5852 {
5853         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5854                 tp->event_slow &= ~RxFIFOOver;
5855
5856         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5857             tp->mac_version == RTL_GIGA_MAC_VER_16)
5858                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5859                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5860
5861         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5862
5863         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5864         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5865
5866         switch (tp->mac_version) {
5867         case RTL_GIGA_MAC_VER_07:
5868                 rtl_hw_start_8102e_1(tp);
5869                 break;
5870
5871         case RTL_GIGA_MAC_VER_08:
5872                 rtl_hw_start_8102e_3(tp);
5873                 break;
5874
5875         case RTL_GIGA_MAC_VER_09:
5876                 rtl_hw_start_8102e_2(tp);
5877                 break;
5878
5879         case RTL_GIGA_MAC_VER_29:
5880                 rtl_hw_start_8105e_1(tp);
5881                 break;
5882         case RTL_GIGA_MAC_VER_30:
5883                 rtl_hw_start_8105e_2(tp);
5884                 break;
5885
5886         case RTL_GIGA_MAC_VER_37:
5887                 rtl_hw_start_8402(tp);
5888                 break;
5889
5890         case RTL_GIGA_MAC_VER_39:
5891                 rtl_hw_start_8106(tp);
5892                 break;
5893         case RTL_GIGA_MAC_VER_43:
5894                 rtl_hw_start_8168g_2(tp);
5895                 break;
5896         case RTL_GIGA_MAC_VER_47:
5897         case RTL_GIGA_MAC_VER_48:
5898                 rtl_hw_start_8168h_1(tp);
5899                 break;
5900         }
5901
5902         RTL_W16(tp, IntrMitigate, 0x0000);
5903 }
5904
5905 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5906 {
5907         struct rtl8169_private *tp = netdev_priv(dev);
5908
5909         if (new_mtu > ETH_DATA_LEN)
5910                 rtl_hw_jumbo_enable(tp);
5911         else
5912                 rtl_hw_jumbo_disable(tp);
5913
5914         dev->mtu = new_mtu;
5915         netdev_update_features(dev);
5916
5917         return 0;
5918 }
5919
5920 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5921 {
5922         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5923         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5924 }
5925
5926 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5927                                      void **data_buff, struct RxDesc *desc)
5928 {
5929         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5930                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5931
5932         kfree(*data_buff);
5933         *data_buff = NULL;
5934         rtl8169_make_unusable_by_asic(desc);
5935 }
5936
5937 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5938 {
5939         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5940
5941         /* Force memory writes to complete before releasing descriptor */
5942         dma_wmb();
5943
5944         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5945 }
5946
5947 static inline void *rtl8169_align(void *data)
5948 {
5949         return (void *)ALIGN((long)data, 16);
5950 }
5951
5952 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5953                                              struct RxDesc *desc)
5954 {
5955         void *data;
5956         dma_addr_t mapping;
5957         struct device *d = tp_to_dev(tp);
5958         int node = dev_to_node(d);
5959
5960         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5961         if (!data)
5962                 return NULL;
5963
5964         if (rtl8169_align(data) != data) {
5965                 kfree(data);
5966                 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5967                 if (!data)
5968                         return NULL;
5969         }
5970
5971         mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5972                                  DMA_FROM_DEVICE);
5973         if (unlikely(dma_mapping_error(d, mapping))) {
5974                 if (net_ratelimit())
5975                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5976                 goto err_out;
5977         }
5978
5979         desc->addr = cpu_to_le64(mapping);
5980         rtl8169_mark_to_asic(desc);
5981         return data;
5982
5983 err_out:
5984         kfree(data);
5985         return NULL;
5986 }
5987
5988 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5989 {
5990         unsigned int i;
5991
5992         for (i = 0; i < NUM_RX_DESC; i++) {
5993                 if (tp->Rx_databuff[i]) {
5994                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5995                                             tp->RxDescArray + i);
5996                 }
5997         }
5998 }
5999
6000 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6001 {
6002         desc->opts1 |= cpu_to_le32(RingEnd);
6003 }
6004
6005 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6006 {
6007         unsigned int i;
6008
6009         for (i = 0; i < NUM_RX_DESC; i++) {
6010                 void *data;
6011
6012                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6013                 if (!data) {
6014                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6015                         goto err_out;
6016                 }
6017                 tp->Rx_databuff[i] = data;
6018         }
6019
6020         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6021         return 0;
6022
6023 err_out:
6024         rtl8169_rx_clear(tp);
6025         return -ENOMEM;
6026 }
6027
6028 static int rtl8169_init_ring(struct rtl8169_private *tp)
6029 {
6030         rtl8169_init_ring_indexes(tp);
6031
6032         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
6033         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
6034
6035         return rtl8169_rx_fill(tp);
6036 }
6037
6038 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6039                                  struct TxDesc *desc)
6040 {
6041         unsigned int len = tx_skb->len;
6042
6043         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6044
6045         desc->opts1 = 0x00;
6046         desc->opts2 = 0x00;
6047         desc->addr = 0x00;
6048         tx_skb->len = 0;
6049 }
6050
6051 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6052                                    unsigned int n)
6053 {
6054         unsigned int i;
6055
6056         for (i = 0; i < n; i++) {
6057                 unsigned int entry = (start + i) % NUM_TX_DESC;
6058                 struct ring_info *tx_skb = tp->tx_skb + entry;
6059                 unsigned int len = tx_skb->len;
6060
6061                 if (len) {
6062                         struct sk_buff *skb = tx_skb->skb;
6063
6064                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6065                                              tp->TxDescArray + entry);
6066                         if (skb) {
6067                                 dev_consume_skb_any(skb);
6068                                 tx_skb->skb = NULL;
6069                         }
6070                 }
6071         }
6072 }
6073
6074 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6075 {
6076         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6077         tp->cur_tx = tp->dirty_tx = 0;
6078 }
6079
6080 static void rtl_reset_work(struct rtl8169_private *tp)
6081 {
6082         struct net_device *dev = tp->dev;
6083         int i;
6084
6085         napi_disable(&tp->napi);
6086         netif_stop_queue(dev);
6087         synchronize_sched();
6088
6089         rtl8169_hw_reset(tp);
6090
6091         for (i = 0; i < NUM_RX_DESC; i++)
6092                 rtl8169_mark_to_asic(tp->RxDescArray + i);
6093
6094         rtl8169_tx_clear(tp);
6095         rtl8169_init_ring_indexes(tp);
6096
6097         napi_enable(&tp->napi);
6098         rtl_hw_start(tp);
6099         netif_wake_queue(dev);
6100 }
6101
6102 static void rtl8169_tx_timeout(struct net_device *dev)
6103 {
6104         struct rtl8169_private *tp = netdev_priv(dev);
6105
6106         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6107 }
6108
6109 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6110                               u32 *opts)
6111 {
6112         struct skb_shared_info *info = skb_shinfo(skb);
6113         unsigned int cur_frag, entry;
6114         struct TxDesc *uninitialized_var(txd);
6115         struct device *d = tp_to_dev(tp);
6116
6117         entry = tp->cur_tx;
6118         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6119                 const skb_frag_t *frag = info->frags + cur_frag;
6120                 dma_addr_t mapping;
6121                 u32 status, len;
6122                 void *addr;
6123
6124                 entry = (entry + 1) % NUM_TX_DESC;
6125
6126                 txd = tp->TxDescArray + entry;
6127                 len = skb_frag_size(frag);
6128                 addr = skb_frag_address(frag);
6129                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6130                 if (unlikely(dma_mapping_error(d, mapping))) {
6131                         if (net_ratelimit())
6132                                 netif_err(tp, drv, tp->dev,
6133                                           "Failed to map TX fragments DMA!\n");
6134                         goto err_out;
6135                 }
6136
6137                 /* Anti gcc 2.95.3 bugware (sic) */
6138                 status = opts[0] | len |
6139                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
6140
6141                 txd->opts1 = cpu_to_le32(status);
6142                 txd->opts2 = cpu_to_le32(opts[1]);
6143                 txd->addr = cpu_to_le64(mapping);
6144
6145                 tp->tx_skb[entry].len = len;
6146         }
6147
6148         if (cur_frag) {
6149                 tp->tx_skb[entry].skb = skb;
6150                 txd->opts1 |= cpu_to_le32(LastFrag);
6151         }
6152
6153         return cur_frag;
6154
6155 err_out:
6156         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6157         return -EIO;
6158 }
6159
6160 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6161 {
6162         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6163 }
6164
6165 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6166                                       struct net_device *dev);
6167 /* r8169_csum_workaround()
6168  * The hw limites the value the transport offset. When the offset is out of the
6169  * range, calculate the checksum by sw.
6170  */
6171 static void r8169_csum_workaround(struct rtl8169_private *tp,
6172                                   struct sk_buff *skb)
6173 {
6174         if (skb_shinfo(skb)->gso_size) {
6175                 netdev_features_t features = tp->dev->features;
6176                 struct sk_buff *segs, *nskb;
6177
6178                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6179                 segs = skb_gso_segment(skb, features);
6180                 if (IS_ERR(segs) || !segs)
6181                         goto drop;
6182
6183                 do {
6184                         nskb = segs;
6185                         segs = segs->next;
6186                         nskb->next = NULL;
6187                         rtl8169_start_xmit(nskb, tp->dev);
6188                 } while (segs);
6189
6190                 dev_consume_skb_any(skb);
6191         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6192                 if (skb_checksum_help(skb) < 0)
6193                         goto drop;
6194
6195                 rtl8169_start_xmit(skb, tp->dev);
6196         } else {
6197                 struct net_device_stats *stats;
6198
6199 drop:
6200                 stats = &tp->dev->stats;
6201                 stats->tx_dropped++;
6202                 dev_kfree_skb_any(skb);
6203         }
6204 }
6205
6206 /* msdn_giant_send_check()
6207  * According to the document of microsoft, the TCP Pseudo Header excludes the
6208  * packet length for IPv6 TCP large packets.
6209  */
6210 static int msdn_giant_send_check(struct sk_buff *skb)
6211 {
6212         const struct ipv6hdr *ipv6h;
6213         struct tcphdr *th;
6214         int ret;
6215
6216         ret = skb_cow_head(skb, 0);
6217         if (ret)
6218                 return ret;
6219
6220         ipv6h = ipv6_hdr(skb);
6221         th = tcp_hdr(skb);
6222
6223         th->check = 0;
6224         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6225
6226         return ret;
6227 }
6228
6229 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6230                                 struct sk_buff *skb, u32 *opts)
6231 {
6232         u32 mss = skb_shinfo(skb)->gso_size;
6233
6234         if (mss) {
6235                 opts[0] |= TD_LSO;
6236                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6237         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6238                 const struct iphdr *ip = ip_hdr(skb);
6239
6240                 if (ip->protocol == IPPROTO_TCP)
6241                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6242                 else if (ip->protocol == IPPROTO_UDP)
6243                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6244                 else
6245                         WARN_ON_ONCE(1);
6246         }
6247
6248         return true;
6249 }
6250
6251 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6252                                 struct sk_buff *skb, u32 *opts)
6253 {
6254         u32 transport_offset = (u32)skb_transport_offset(skb);
6255         u32 mss = skb_shinfo(skb)->gso_size;
6256
6257         if (mss) {
6258                 if (transport_offset > GTTCPHO_MAX) {
6259                         netif_warn(tp, tx_err, tp->dev,
6260                                    "Invalid transport offset 0x%x for TSO\n",
6261                                    transport_offset);
6262                         return false;
6263                 }
6264
6265                 switch (vlan_get_protocol(skb)) {
6266                 case htons(ETH_P_IP):
6267                         opts[0] |= TD1_GTSENV4;
6268                         break;
6269
6270                 case htons(ETH_P_IPV6):
6271                         if (msdn_giant_send_check(skb))
6272                                 return false;
6273
6274                         opts[0] |= TD1_GTSENV6;
6275                         break;
6276
6277                 default:
6278                         WARN_ON_ONCE(1);
6279                         break;
6280                 }
6281
6282                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6283                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6284         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6285                 u8 ip_protocol;
6286
6287                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6288                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6289
6290                 if (transport_offset > TCPHO_MAX) {
6291                         netif_warn(tp, tx_err, tp->dev,
6292                                    "Invalid transport offset 0x%x\n",
6293                                    transport_offset);
6294                         return false;
6295                 }
6296
6297                 switch (vlan_get_protocol(skb)) {
6298                 case htons(ETH_P_IP):
6299                         opts[1] |= TD1_IPv4_CS;
6300                         ip_protocol = ip_hdr(skb)->protocol;
6301                         break;
6302
6303                 case htons(ETH_P_IPV6):
6304                         opts[1] |= TD1_IPv6_CS;
6305                         ip_protocol = ipv6_hdr(skb)->nexthdr;
6306                         break;
6307
6308                 default:
6309                         ip_protocol = IPPROTO_RAW;
6310                         break;
6311                 }
6312
6313                 if (ip_protocol == IPPROTO_TCP)
6314                         opts[1] |= TD1_TCP_CS;
6315                 else if (ip_protocol == IPPROTO_UDP)
6316                         opts[1] |= TD1_UDP_CS;
6317                 else
6318                         WARN_ON_ONCE(1);
6319
6320                 opts[1] |= transport_offset << TCPHO_SHIFT;
6321         } else {
6322                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6323                         return !eth_skb_pad(skb);
6324         }
6325
6326         return true;
6327 }
6328
6329 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6330                                       struct net_device *dev)
6331 {
6332         struct rtl8169_private *tp = netdev_priv(dev);
6333         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6334         struct TxDesc *txd = tp->TxDescArray + entry;
6335         struct device *d = tp_to_dev(tp);
6336         dma_addr_t mapping;
6337         u32 status, len;
6338         u32 opts[2];
6339         int frags;
6340
6341         if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6342                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6343                 goto err_stop_0;
6344         }
6345
6346         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6347                 goto err_stop_0;
6348
6349         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6350         opts[0] = DescOwn;
6351
6352         if (!tp->tso_csum(tp, skb, opts)) {
6353                 r8169_csum_workaround(tp, skb);
6354                 return NETDEV_TX_OK;
6355         }
6356
6357         len = skb_headlen(skb);
6358         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6359         if (unlikely(dma_mapping_error(d, mapping))) {
6360                 if (net_ratelimit())
6361                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6362                 goto err_dma_0;
6363         }
6364
6365         tp->tx_skb[entry].len = len;
6366         txd->addr = cpu_to_le64(mapping);
6367
6368         frags = rtl8169_xmit_frags(tp, skb, opts);
6369         if (frags < 0)
6370                 goto err_dma_1;
6371         else if (frags)
6372                 opts[0] |= FirstFrag;
6373         else {
6374                 opts[0] |= FirstFrag | LastFrag;
6375                 tp->tx_skb[entry].skb = skb;
6376         }
6377
6378         txd->opts2 = cpu_to_le32(opts[1]);
6379
6380         skb_tx_timestamp(skb);
6381
6382         /* Force memory writes to complete before releasing descriptor */
6383         dma_wmb();
6384
6385         /* Anti gcc 2.95.3 bugware (sic) */
6386         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6387         txd->opts1 = cpu_to_le32(status);
6388
6389         /* Force all memory writes to complete before notifying device */
6390         wmb();
6391
6392         tp->cur_tx += frags + 1;
6393
6394         RTL_W8(tp, TxPoll, NPQ);
6395
6396         mmiowb();
6397
6398         if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6399                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6400                  * not miss a ring update when it notices a stopped queue.
6401                  */
6402                 smp_wmb();
6403                 netif_stop_queue(dev);
6404                 /* Sync with rtl_tx:
6405                  * - publish queue status and cur_tx ring index (write barrier)
6406                  * - refresh dirty_tx ring index (read barrier).
6407                  * May the current thread have a pessimistic view of the ring
6408                  * status and forget to wake up queue, a racing rtl_tx thread
6409                  * can't.
6410                  */
6411                 smp_mb();
6412                 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6413                         netif_wake_queue(dev);
6414         }
6415
6416         return NETDEV_TX_OK;
6417
6418 err_dma_1:
6419         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6420 err_dma_0:
6421         dev_kfree_skb_any(skb);
6422         dev->stats.tx_dropped++;
6423         return NETDEV_TX_OK;
6424
6425 err_stop_0:
6426         netif_stop_queue(dev);
6427         dev->stats.tx_dropped++;
6428         return NETDEV_TX_BUSY;
6429 }
6430
6431 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6432 {
6433         struct rtl8169_private *tp = netdev_priv(dev);
6434         struct pci_dev *pdev = tp->pci_dev;
6435         u16 pci_status, pci_cmd;
6436
6437         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6438         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6439
6440         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6441                   pci_cmd, pci_status);
6442
6443         /*
6444          * The recovery sequence below admits a very elaborated explanation:
6445          * - it seems to work;
6446          * - I did not see what else could be done;
6447          * - it makes iop3xx happy.
6448          *
6449          * Feel free to adjust to your needs.
6450          */
6451         if (pdev->broken_parity_status)
6452                 pci_cmd &= ~PCI_COMMAND_PARITY;
6453         else
6454                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6455
6456         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6457
6458         pci_write_config_word(pdev, PCI_STATUS,
6459                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6460                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6461                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6462
6463         /* The infamous DAC f*ckup only happens at boot time */
6464         if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6465                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6466                 tp->cp_cmd &= ~PCIDAC;
6467                 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6468                 dev->features &= ~NETIF_F_HIGHDMA;
6469         }
6470
6471         rtl8169_hw_reset(tp);
6472
6473         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6474 }
6475
6476 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6477 {
6478         unsigned int dirty_tx, tx_left;
6479
6480         dirty_tx = tp->dirty_tx;
6481         smp_rmb();
6482         tx_left = tp->cur_tx - dirty_tx;
6483
6484         while (tx_left > 0) {
6485                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6486                 struct ring_info *tx_skb = tp->tx_skb + entry;
6487                 u32 status;
6488
6489                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6490                 if (status & DescOwn)
6491                         break;
6492
6493                 /* This barrier is needed to keep us from reading
6494                  * any other fields out of the Tx descriptor until
6495                  * we know the status of DescOwn
6496                  */
6497                 dma_rmb();
6498
6499                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6500                                      tp->TxDescArray + entry);
6501                 if (status & LastFrag) {
6502                         u64_stats_update_begin(&tp->tx_stats.syncp);
6503                         tp->tx_stats.packets++;
6504                         tp->tx_stats.bytes += tx_skb->skb->len;
6505                         u64_stats_update_end(&tp->tx_stats.syncp);
6506                         dev_consume_skb_any(tx_skb->skb);
6507                         tx_skb->skb = NULL;
6508                 }
6509                 dirty_tx++;
6510                 tx_left--;
6511         }
6512
6513         if (tp->dirty_tx != dirty_tx) {
6514                 tp->dirty_tx = dirty_tx;
6515                 /* Sync with rtl8169_start_xmit:
6516                  * - publish dirty_tx ring index (write barrier)
6517                  * - refresh cur_tx ring index and queue status (read barrier)
6518                  * May the current thread miss the stopped queue condition,
6519                  * a racing xmit thread can only have a right view of the
6520                  * ring status.
6521                  */
6522                 smp_mb();
6523                 if (netif_queue_stopped(dev) &&
6524                     TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6525                         netif_wake_queue(dev);
6526                 }
6527                 /*
6528                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6529                  * too close. Let's kick an extra TxPoll request when a burst
6530                  * of start_xmit activity is detected (if it is not detected,
6531                  * it is slow enough). -- FR
6532                  */
6533                 if (tp->cur_tx != dirty_tx)
6534                         RTL_W8(tp, TxPoll, NPQ);
6535         }
6536 }
6537
6538 static inline int rtl8169_fragmented_frame(u32 status)
6539 {
6540         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6541 }
6542
6543 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6544 {
6545         u32 status = opts1 & RxProtoMask;
6546
6547         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6548             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6549                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6550         else
6551                 skb_checksum_none_assert(skb);
6552 }
6553
6554 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6555                                            struct rtl8169_private *tp,
6556                                            int pkt_size,
6557                                            dma_addr_t addr)
6558 {
6559         struct sk_buff *skb;
6560         struct device *d = tp_to_dev(tp);
6561
6562         data = rtl8169_align(data);
6563         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6564         prefetch(data);
6565         skb = napi_alloc_skb(&tp->napi, pkt_size);
6566         if (skb)
6567                 skb_copy_to_linear_data(skb, data, pkt_size);
6568         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6569
6570         return skb;
6571 }
6572
6573 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6574 {
6575         unsigned int cur_rx, rx_left;
6576         unsigned int count;
6577
6578         cur_rx = tp->cur_rx;
6579
6580         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6581                 unsigned int entry = cur_rx % NUM_RX_DESC;
6582                 struct RxDesc *desc = tp->RxDescArray + entry;
6583                 u32 status;
6584
6585                 status = le32_to_cpu(desc->opts1);
6586                 if (status & DescOwn)
6587                         break;
6588
6589                 /* This barrier is needed to keep us from reading
6590                  * any other fields out of the Rx descriptor until
6591                  * we know the status of DescOwn
6592                  */
6593                 dma_rmb();
6594
6595                 if (unlikely(status & RxRES)) {
6596                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6597                                    status);
6598                         dev->stats.rx_errors++;
6599                         if (status & (RxRWT | RxRUNT))
6600                                 dev->stats.rx_length_errors++;
6601                         if (status & RxCRC)
6602                                 dev->stats.rx_crc_errors++;
6603                         /* RxFOVF is a reserved bit on later chip versions */
6604                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6605                             status & RxFOVF) {
6606                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6607                                 dev->stats.rx_fifo_errors++;
6608                         } else if (status & (RxRUNT | RxCRC) &&
6609                                    !(status & RxRWT) &&
6610                                    dev->features & NETIF_F_RXALL) {
6611                                 goto process_pkt;
6612                         }
6613                 } else {
6614                         struct sk_buff *skb;
6615                         dma_addr_t addr;
6616                         int pkt_size;
6617
6618 process_pkt:
6619                         addr = le64_to_cpu(desc->addr);
6620                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6621                                 pkt_size = (status & 0x00003fff) - 4;
6622                         else
6623                                 pkt_size = status & 0x00003fff;
6624
6625                         /*
6626                          * The driver does not support incoming fragmented
6627                          * frames. They are seen as a symptom of over-mtu
6628                          * sized frames.
6629                          */
6630                         if (unlikely(rtl8169_fragmented_frame(status))) {
6631                                 dev->stats.rx_dropped++;
6632                                 dev->stats.rx_length_errors++;
6633                                 goto release_descriptor;
6634                         }
6635
6636                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6637                                                   tp, pkt_size, addr);
6638                         if (!skb) {
6639                                 dev->stats.rx_dropped++;
6640                                 goto release_descriptor;
6641                         }
6642
6643                         rtl8169_rx_csum(skb, status);
6644                         skb_put(skb, pkt_size);
6645                         skb->protocol = eth_type_trans(skb, dev);
6646
6647                         rtl8169_rx_vlan_tag(desc, skb);
6648
6649                         if (skb->pkt_type == PACKET_MULTICAST)
6650                                 dev->stats.multicast++;
6651
6652                         napi_gro_receive(&tp->napi, skb);
6653
6654                         u64_stats_update_begin(&tp->rx_stats.syncp);
6655                         tp->rx_stats.packets++;
6656                         tp->rx_stats.bytes += pkt_size;
6657                         u64_stats_update_end(&tp->rx_stats.syncp);
6658                 }
6659 release_descriptor:
6660                 desc->opts2 = 0;
6661                 rtl8169_mark_to_asic(desc);
6662         }
6663
6664         count = cur_rx - tp->cur_rx;
6665         tp->cur_rx = cur_rx;
6666
6667         return count;
6668 }
6669
6670 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6671 {
6672         struct rtl8169_private *tp = dev_instance;
6673         int handled = 0;
6674         u16 status;
6675
6676         status = rtl_get_events(tp);
6677         if (status && status != 0xffff) {
6678                 status &= RTL_EVENT_NAPI | tp->event_slow;
6679                 if (status) {
6680                         handled = 1;
6681
6682                         rtl_irq_disable(tp);
6683                         napi_schedule_irqoff(&tp->napi);
6684                 }
6685         }
6686         return IRQ_RETVAL(handled);
6687 }
6688
6689 /*
6690  * Workqueue context.
6691  */
6692 static void rtl_slow_event_work(struct rtl8169_private *tp)
6693 {
6694         struct net_device *dev = tp->dev;
6695         u16 status;
6696
6697         status = rtl_get_events(tp) & tp->event_slow;
6698         rtl_ack_events(tp, status);
6699
6700         if (unlikely(status & RxFIFOOver)) {
6701                 switch (tp->mac_version) {
6702                 /* Work around for rx fifo overflow */
6703                 case RTL_GIGA_MAC_VER_11:
6704                         netif_stop_queue(dev);
6705                         /* XXX - Hack alert. See rtl_task(). */
6706                         set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6707                 default:
6708                         break;
6709                 }
6710         }
6711
6712         if (unlikely(status & SYSErr))
6713                 rtl8169_pcierr_interrupt(dev);
6714
6715         if (status & LinkChg)
6716                 phy_mac_interrupt(dev->phydev);
6717
6718         rtl_irq_enable_all(tp);
6719 }
6720
6721 static void rtl_task(struct work_struct *work)
6722 {
6723         static const struct {
6724                 int bitnr;
6725                 void (*action)(struct rtl8169_private *);
6726         } rtl_work[] = {
6727                 /* XXX - keep rtl_slow_event_work() as first element. */
6728                 { RTL_FLAG_TASK_SLOW_PENDING,   rtl_slow_event_work },
6729                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6730         };
6731         struct rtl8169_private *tp =
6732                 container_of(work, struct rtl8169_private, wk.work);
6733         struct net_device *dev = tp->dev;
6734         int i;
6735
6736         rtl_lock_work(tp);
6737
6738         if (!netif_running(dev) ||
6739             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6740                 goto out_unlock;
6741
6742         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6743                 bool pending;
6744
6745                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6746                 if (pending)
6747                         rtl_work[i].action(tp);
6748         }
6749
6750 out_unlock:
6751         rtl_unlock_work(tp);
6752 }
6753
6754 static int rtl8169_poll(struct napi_struct *napi, int budget)
6755 {
6756         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6757         struct net_device *dev = tp->dev;
6758         u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6759         int work_done= 0;
6760         u16 status;
6761
6762         status = rtl_get_events(tp);
6763         rtl_ack_events(tp, status & ~tp->event_slow);
6764
6765         if (status & RTL_EVENT_NAPI_RX)
6766                 work_done = rtl_rx(dev, tp, (u32) budget);
6767
6768         if (status & RTL_EVENT_NAPI_TX)
6769                 rtl_tx(dev, tp);
6770
6771         if (status & tp->event_slow) {
6772                 enable_mask &= ~tp->event_slow;
6773
6774                 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6775         }
6776
6777         if (work_done < budget) {
6778                 napi_complete_done(napi, work_done);
6779
6780                 rtl_irq_enable(tp, enable_mask);
6781                 mmiowb();
6782         }
6783
6784         return work_done;
6785 }
6786
6787 static void rtl8169_rx_missed(struct net_device *dev)
6788 {
6789         struct rtl8169_private *tp = netdev_priv(dev);
6790
6791         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6792                 return;
6793
6794         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6795         RTL_W32(tp, RxMissed, 0);
6796 }
6797
6798 static void r8169_phylink_handler(struct net_device *ndev)
6799 {
6800         struct rtl8169_private *tp = netdev_priv(ndev);
6801
6802         if (netif_carrier_ok(ndev)) {
6803                 rtl_link_chg_patch(tp);
6804                 pm_request_resume(&tp->pci_dev->dev);
6805         } else {
6806                 pm_runtime_idle(&tp->pci_dev->dev);
6807         }
6808
6809         if (net_ratelimit())
6810                 phy_print_status(ndev->phydev);
6811 }
6812
6813 static int r8169_phy_connect(struct rtl8169_private *tp)
6814 {
6815         struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6816         phy_interface_t phy_mode;
6817         int ret;
6818
6819         phy_mode = tp->mii.supports_gmii ? PHY_INTERFACE_MODE_GMII :
6820                    PHY_INTERFACE_MODE_MII;
6821
6822         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6823                                  phy_mode);
6824         if (ret)
6825                 return ret;
6826
6827         if (!tp->mii.supports_gmii)
6828                 phy_set_max_speed(phydev, SPEED_100);
6829
6830         /* Ensure to advertise everything, incl. pause */
6831         phydev->advertising = phydev->supported;
6832
6833         phy_attached_info(phydev);
6834
6835         return 0;
6836 }
6837
6838 static void rtl8169_down(struct net_device *dev)
6839 {
6840         struct rtl8169_private *tp = netdev_priv(dev);
6841
6842         phy_stop(dev->phydev);
6843
6844         napi_disable(&tp->napi);
6845         netif_stop_queue(dev);
6846
6847         rtl8169_hw_reset(tp);
6848         /*
6849          * At this point device interrupts can not be enabled in any function,
6850          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6851          * and napi is disabled (rtl8169_poll).
6852          */
6853         rtl8169_rx_missed(dev);
6854
6855         /* Give a racing hard_start_xmit a few cycles to complete. */
6856         synchronize_sched();
6857
6858         rtl8169_tx_clear(tp);
6859
6860         rtl8169_rx_clear(tp);
6861
6862         rtl_pll_power_down(tp);
6863 }
6864
6865 static int rtl8169_close(struct net_device *dev)
6866 {
6867         struct rtl8169_private *tp = netdev_priv(dev);
6868         struct pci_dev *pdev = tp->pci_dev;
6869
6870         pm_runtime_get_sync(&pdev->dev);
6871
6872         /* Update counters before going down */
6873         rtl8169_update_counters(tp);
6874
6875         rtl_lock_work(tp);
6876         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6877
6878         rtl8169_down(dev);
6879         rtl_unlock_work(tp);
6880
6881         cancel_work_sync(&tp->wk.work);
6882
6883         phy_disconnect(dev->phydev);
6884
6885         pci_free_irq(pdev, 0, tp);
6886
6887         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6888                           tp->RxPhyAddr);
6889         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6890                           tp->TxPhyAddr);
6891         tp->TxDescArray = NULL;
6892         tp->RxDescArray = NULL;
6893
6894         pm_runtime_put_sync(&pdev->dev);
6895
6896         return 0;
6897 }
6898
6899 #ifdef CONFIG_NET_POLL_CONTROLLER
6900 static void rtl8169_netpoll(struct net_device *dev)
6901 {
6902         struct rtl8169_private *tp = netdev_priv(dev);
6903
6904         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6905 }
6906 #endif
6907
6908 static int rtl_open(struct net_device *dev)
6909 {
6910         struct rtl8169_private *tp = netdev_priv(dev);
6911         struct pci_dev *pdev = tp->pci_dev;
6912         int retval = -ENOMEM;
6913
6914         pm_runtime_get_sync(&pdev->dev);
6915
6916         /*
6917          * Rx and Tx descriptors needs 256 bytes alignment.
6918          * dma_alloc_coherent provides more.
6919          */
6920         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6921                                              &tp->TxPhyAddr, GFP_KERNEL);
6922         if (!tp->TxDescArray)
6923                 goto err_pm_runtime_put;
6924
6925         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6926                                              &tp->RxPhyAddr, GFP_KERNEL);
6927         if (!tp->RxDescArray)
6928                 goto err_free_tx_0;
6929
6930         retval = rtl8169_init_ring(tp);
6931         if (retval < 0)
6932                 goto err_free_rx_1;
6933
6934         INIT_WORK(&tp->wk.work, rtl_task);
6935
6936         smp_mb();
6937
6938         rtl_request_firmware(tp);
6939
6940         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6941                                  dev->name);
6942         if (retval < 0)
6943                 goto err_release_fw_2;
6944
6945         retval = r8169_phy_connect(tp);
6946         if (retval)
6947                 goto err_free_irq;
6948
6949         rtl_lock_work(tp);
6950
6951         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6952
6953         napi_enable(&tp->napi);
6954
6955         rtl8169_init_phy(dev, tp);
6956
6957         rtl_pll_power_up(tp);
6958
6959         rtl_hw_start(tp);
6960
6961         if (!rtl8169_init_counter_offsets(tp))
6962                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6963
6964         phy_start(dev->phydev);
6965         netif_start_queue(dev);
6966
6967         rtl_unlock_work(tp);
6968
6969         pm_runtime_put_sync(&pdev->dev);
6970 out:
6971         return retval;
6972
6973 err_free_irq:
6974         pci_free_irq(pdev, 0, tp);
6975 err_release_fw_2:
6976         rtl_release_firmware(tp);
6977         rtl8169_rx_clear(tp);
6978 err_free_rx_1:
6979         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6980                           tp->RxPhyAddr);
6981         tp->RxDescArray = NULL;
6982 err_free_tx_0:
6983         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6984                           tp->TxPhyAddr);
6985         tp->TxDescArray = NULL;
6986 err_pm_runtime_put:
6987         pm_runtime_put_noidle(&pdev->dev);
6988         goto out;
6989 }
6990
6991 static void
6992 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6993 {
6994         struct rtl8169_private *tp = netdev_priv(dev);
6995         struct pci_dev *pdev = tp->pci_dev;
6996         struct rtl8169_counters *counters = tp->counters;
6997         unsigned int start;
6998
6999         pm_runtime_get_noresume(&pdev->dev);
7000
7001         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7002                 rtl8169_rx_missed(dev);
7003
7004         do {
7005                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7006                 stats->rx_packets = tp->rx_stats.packets;
7007                 stats->rx_bytes = tp->rx_stats.bytes;
7008         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7009
7010         do {
7011                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7012                 stats->tx_packets = tp->tx_stats.packets;
7013                 stats->tx_bytes = tp->tx_stats.bytes;
7014         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7015
7016         stats->rx_dropped       = dev->stats.rx_dropped;
7017         stats->tx_dropped       = dev->stats.tx_dropped;
7018         stats->rx_length_errors = dev->stats.rx_length_errors;
7019         stats->rx_errors        = dev->stats.rx_errors;
7020         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
7021         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
7022         stats->rx_missed_errors = dev->stats.rx_missed_errors;
7023         stats->multicast        = dev->stats.multicast;
7024
7025         /*
7026          * Fetch additonal counter values missing in stats collected by driver
7027          * from tally counters.
7028          */
7029         if (pm_runtime_active(&pdev->dev))
7030                 rtl8169_update_counters(tp);
7031
7032         /*
7033          * Subtract values fetched during initalization.
7034          * See rtl8169_init_counter_offsets for a description why we do that.
7035          */
7036         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
7037                 le64_to_cpu(tp->tc_offset.tx_errors);
7038         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
7039                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
7040         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
7041                 le16_to_cpu(tp->tc_offset.tx_aborted);
7042
7043         pm_runtime_put_noidle(&pdev->dev);
7044 }
7045
7046 static void rtl8169_net_suspend(struct net_device *dev)
7047 {
7048         struct rtl8169_private *tp = netdev_priv(dev);
7049
7050         if (!netif_running(dev))
7051                 return;
7052
7053         phy_stop(dev->phydev);
7054         netif_device_detach(dev);
7055         netif_stop_queue(dev);
7056
7057         rtl_lock_work(tp);
7058         napi_disable(&tp->napi);
7059         clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7060         rtl_unlock_work(tp);
7061
7062         rtl_pll_power_down(tp);
7063 }
7064
7065 #ifdef CONFIG_PM
7066
7067 static int rtl8169_suspend(struct device *device)
7068 {
7069         struct pci_dev *pdev = to_pci_dev(device);
7070         struct net_device *dev = pci_get_drvdata(pdev);
7071
7072         rtl8169_net_suspend(dev);
7073
7074         return 0;
7075 }
7076
7077 static void __rtl8169_resume(struct net_device *dev)
7078 {
7079         struct rtl8169_private *tp = netdev_priv(dev);
7080
7081         netif_device_attach(dev);
7082
7083         rtl_pll_power_up(tp);
7084         rtl8169_init_phy(dev, tp);
7085
7086         phy_start(tp->dev->phydev);
7087
7088         rtl_lock_work(tp);
7089         napi_enable(&tp->napi);
7090         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7091         rtl_unlock_work(tp);
7092
7093         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7094 }
7095
7096 static int rtl8169_resume(struct device *device)
7097 {
7098         struct pci_dev *pdev = to_pci_dev(device);
7099         struct net_device *dev = pci_get_drvdata(pdev);
7100
7101         if (netif_running(dev))
7102                 __rtl8169_resume(dev);
7103
7104         return 0;
7105 }
7106
7107 static int rtl8169_runtime_suspend(struct device *device)
7108 {
7109         struct pci_dev *pdev = to_pci_dev(device);
7110         struct net_device *dev = pci_get_drvdata(pdev);
7111         struct rtl8169_private *tp = netdev_priv(dev);
7112
7113         if (!tp->TxDescArray) {
7114                 rtl_pll_power_down(tp);
7115                 return 0;
7116         }
7117
7118         rtl_lock_work(tp);
7119         __rtl8169_set_wol(tp, WAKE_ANY);
7120         rtl_unlock_work(tp);
7121
7122         rtl8169_net_suspend(dev);
7123
7124         /* Update counters before going runtime suspend */
7125         rtl8169_rx_missed(dev);
7126         rtl8169_update_counters(tp);
7127
7128         return 0;
7129 }
7130
7131 static int rtl8169_runtime_resume(struct device *device)
7132 {
7133         struct pci_dev *pdev = to_pci_dev(device);
7134         struct net_device *dev = pci_get_drvdata(pdev);
7135         struct rtl8169_private *tp = netdev_priv(dev);
7136         rtl_rar_set(tp, dev->dev_addr);
7137
7138         if (!tp->TxDescArray)
7139                 return 0;
7140
7141         rtl_lock_work(tp);
7142         __rtl8169_set_wol(tp, tp->saved_wolopts);
7143         rtl_unlock_work(tp);
7144
7145         __rtl8169_resume(dev);
7146
7147         return 0;
7148 }
7149
7150 static int rtl8169_runtime_idle(struct device *device)
7151 {
7152         struct pci_dev *pdev = to_pci_dev(device);
7153         struct net_device *dev = pci_get_drvdata(pdev);
7154
7155         if (!netif_running(dev) || !netif_carrier_ok(dev))
7156                 pm_schedule_suspend(device, 10000);
7157
7158         return -EBUSY;
7159 }
7160
7161 static const struct dev_pm_ops rtl8169_pm_ops = {
7162         .suspend                = rtl8169_suspend,
7163         .resume                 = rtl8169_resume,
7164         .freeze                 = rtl8169_suspend,
7165         .thaw                   = rtl8169_resume,
7166         .poweroff               = rtl8169_suspend,
7167         .restore                = rtl8169_resume,
7168         .runtime_suspend        = rtl8169_runtime_suspend,
7169         .runtime_resume         = rtl8169_runtime_resume,
7170         .runtime_idle           = rtl8169_runtime_idle,
7171 };
7172
7173 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
7174
7175 #else /* !CONFIG_PM */
7176
7177 #define RTL8169_PM_OPS  NULL
7178
7179 #endif /* !CONFIG_PM */
7180
7181 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7182 {
7183         /* WoL fails with 8168b when the receiver is disabled. */
7184         switch (tp->mac_version) {
7185         case RTL_GIGA_MAC_VER_11:
7186         case RTL_GIGA_MAC_VER_12:
7187         case RTL_GIGA_MAC_VER_17:
7188                 pci_clear_master(tp->pci_dev);
7189
7190                 RTL_W8(tp, ChipCmd, CmdRxEnb);
7191                 /* PCI commit */
7192                 RTL_R8(tp, ChipCmd);
7193                 break;
7194         default:
7195                 break;
7196         }
7197 }
7198
7199 static void rtl_shutdown(struct pci_dev *pdev)
7200 {
7201         struct net_device *dev = pci_get_drvdata(pdev);
7202         struct rtl8169_private *tp = netdev_priv(dev);
7203
7204         rtl8169_net_suspend(dev);
7205
7206         /* Restore original MAC address */
7207         rtl_rar_set(tp, dev->perm_addr);
7208
7209         rtl8169_hw_reset(tp);
7210
7211         if (system_state == SYSTEM_POWER_OFF) {
7212                 if (tp->saved_wolopts) {
7213                         rtl_wol_suspend_quirk(tp);
7214                         rtl_wol_shutdown_quirk(tp);
7215                 }
7216
7217                 pci_wake_from_d3(pdev, true);
7218                 pci_set_power_state(pdev, PCI_D3hot);
7219         }
7220 }
7221
7222 static void rtl_remove_one(struct pci_dev *pdev)
7223 {
7224         struct net_device *dev = pci_get_drvdata(pdev);
7225         struct rtl8169_private *tp = netdev_priv(dev);
7226
7227         if (r8168_check_dash(tp))
7228                 rtl8168_driver_stop(tp);
7229
7230         netif_napi_del(&tp->napi);
7231
7232         unregister_netdev(dev);
7233         mdiobus_unregister(tp->mii_bus);
7234
7235         rtl_release_firmware(tp);
7236
7237         if (pci_dev_run_wake(pdev))
7238                 pm_runtime_get_noresume(&pdev->dev);
7239
7240         /* restore original MAC address */
7241         rtl_rar_set(tp, dev->perm_addr);
7242 }
7243
7244 static const struct net_device_ops rtl_netdev_ops = {
7245         .ndo_open               = rtl_open,
7246         .ndo_stop               = rtl8169_close,
7247         .ndo_get_stats64        = rtl8169_get_stats64,
7248         .ndo_start_xmit         = rtl8169_start_xmit,
7249         .ndo_tx_timeout         = rtl8169_tx_timeout,
7250         .ndo_validate_addr      = eth_validate_addr,
7251         .ndo_change_mtu         = rtl8169_change_mtu,
7252         .ndo_fix_features       = rtl8169_fix_features,
7253         .ndo_set_features       = rtl8169_set_features,
7254         .ndo_set_mac_address    = rtl_set_mac_address,
7255         .ndo_do_ioctl           = rtl8169_ioctl,
7256         .ndo_set_rx_mode        = rtl_set_rx_mode,
7257 #ifdef CONFIG_NET_POLL_CONTROLLER
7258         .ndo_poll_controller    = rtl8169_netpoll,
7259 #endif
7260
7261 };
7262
7263 static const struct rtl_cfg_info {
7264         void (*hw_start)(struct rtl8169_private *tp);
7265         u16 event_slow;
7266         unsigned int has_gmii:1;
7267         const struct rtl_coalesce_info *coalesce_info;
7268         u8 default_ver;
7269 } rtl_cfg_infos [] = {
7270         [RTL_CFG_0] = {
7271                 .hw_start       = rtl_hw_start_8169,
7272                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7273                 .has_gmii       = 1,
7274                 .coalesce_info  = rtl_coalesce_info_8169,
7275                 .default_ver    = RTL_GIGA_MAC_VER_01,
7276         },
7277         [RTL_CFG_1] = {
7278                 .hw_start       = rtl_hw_start_8168,
7279                 .event_slow     = SYSErr | LinkChg | RxOverflow,
7280                 .has_gmii       = 1,
7281                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7282                 .default_ver    = RTL_GIGA_MAC_VER_11,
7283         },
7284         [RTL_CFG_2] = {
7285                 .hw_start       = rtl_hw_start_8101,
7286                 .event_slow     = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7287                                   PCSTimeout,
7288                 .coalesce_info  = rtl_coalesce_info_8168_8136,
7289                 .default_ver    = RTL_GIGA_MAC_VER_13,
7290         }
7291 };
7292
7293 static int rtl_alloc_irq(struct rtl8169_private *tp)
7294 {
7295         unsigned int flags;
7296
7297         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7298                 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7299                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7300                 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7301                 flags = PCI_IRQ_LEGACY;
7302         } else {
7303                 flags = PCI_IRQ_ALL_TYPES;
7304         }
7305
7306         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7307 }
7308
7309 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7310 {
7311         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7312 }
7313
7314 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7315 {
7316         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7317 }
7318
7319 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7320 {
7321         struct rtl8169_private *tp = mii_bus->priv;
7322
7323         if (phyaddr > 0)
7324                 return -ENODEV;
7325
7326         return rtl_readphy(tp, phyreg);
7327 }
7328
7329 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7330                                 int phyreg, u16 val)
7331 {
7332         struct rtl8169_private *tp = mii_bus->priv;
7333
7334         if (phyaddr > 0)
7335                 return -ENODEV;
7336
7337         rtl_writephy(tp, phyreg, val);
7338
7339         return 0;
7340 }
7341
7342 static int r8169_mdio_register(struct rtl8169_private *tp)
7343 {
7344         struct pci_dev *pdev = tp->pci_dev;
7345         struct phy_device *phydev;
7346         struct mii_bus *new_bus;
7347         int ret;
7348
7349         new_bus = devm_mdiobus_alloc(&pdev->dev);
7350         if (!new_bus)
7351                 return -ENOMEM;
7352
7353         new_bus->name = "r8169";
7354         new_bus->priv = tp;
7355         new_bus->parent = &pdev->dev;
7356         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7357         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7358                  PCI_DEVID(pdev->bus->number, pdev->devfn));
7359
7360         new_bus->read = r8169_mdio_read_reg;
7361         new_bus->write = r8169_mdio_write_reg;
7362
7363         ret = mdiobus_register(new_bus);
7364         if (ret)
7365                 return ret;
7366
7367         phydev = mdiobus_get_phy(new_bus, 0);
7368         if (!phydev) {
7369                 mdiobus_unregister(new_bus);
7370                 return -ENODEV;
7371         }
7372
7373         /* PHY will be woken up in rtl_open() */
7374         phy_suspend(phydev);
7375
7376         tp->mii_bus = new_bus;
7377
7378         return 0;
7379 }
7380
7381 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7382 {
7383         u32 data;
7384
7385         tp->ocp_base = OCP_STD_PHY_BASE;
7386
7387         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7388
7389         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7390                 return;
7391
7392         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7393                 return;
7394
7395         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7396         msleep(1);
7397         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7398
7399         data = r8168_mac_ocp_read(tp, 0xe8de);
7400         data &= ~(1 << 14);
7401         r8168_mac_ocp_write(tp, 0xe8de, data);
7402
7403         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7404                 return;
7405
7406         data = r8168_mac_ocp_read(tp, 0xe8de);
7407         data |= (1 << 15);
7408         r8168_mac_ocp_write(tp, 0xe8de, data);
7409
7410         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7411                 return;
7412 }
7413
7414 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7415 {
7416         rtl8168ep_stop_cmac(tp);
7417         rtl_hw_init_8168g(tp);
7418 }
7419
7420 static void rtl_hw_initialize(struct rtl8169_private *tp)
7421 {
7422         switch (tp->mac_version) {
7423         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7424                 rtl_hw_init_8168g(tp);
7425                 break;
7426         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7427                 rtl_hw_init_8168ep(tp);
7428                 break;
7429         default:
7430                 break;
7431         }
7432 }
7433
7434 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7435 {
7436         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7437         struct rtl8169_private *tp;
7438         struct mii_if_info *mii;
7439         struct net_device *dev;
7440         int chipset, region, i;
7441         int rc;
7442
7443         if (netif_msg_drv(&debug)) {
7444                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
7445                        MODULENAME, RTL8169_VERSION);
7446         }
7447
7448         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7449         if (!dev)
7450                 return -ENOMEM;
7451
7452         SET_NETDEV_DEV(dev, &pdev->dev);
7453         dev->netdev_ops = &rtl_netdev_ops;
7454         tp = netdev_priv(dev);
7455         tp->dev = dev;
7456         tp->pci_dev = pdev;
7457         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7458
7459         mii = &tp->mii;
7460         mii->dev = dev;
7461         mii->mdio_read = rtl_mdio_read;
7462         mii->mdio_write = rtl_mdio_write;
7463         mii->phy_id_mask = 0x1f;
7464         mii->reg_num_mask = 0x1f;
7465         mii->supports_gmii = cfg->has_gmii;
7466
7467         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7468         rc = pcim_enable_device(pdev);
7469         if (rc < 0) {
7470                 dev_err(&pdev->dev, "enable failure\n");
7471                 return rc;
7472         }
7473
7474         if (pcim_set_mwi(pdev) < 0)
7475                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7476
7477         /* use first MMIO region */
7478         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7479         if (region < 0) {
7480                 dev_err(&pdev->dev, "no MMIO resource found\n");
7481                 return -ENODEV;
7482         }
7483
7484         /* check for weird/broken PCI region reporting */
7485         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7486                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7487                 return -ENODEV;
7488         }
7489
7490         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7491         if (rc < 0) {
7492                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7493                 return rc;
7494         }
7495
7496         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7497
7498         if (!pci_is_pcie(pdev))
7499                 dev_info(&pdev->dev, "not PCI Express\n");
7500
7501         /* Identify chip attached to board */
7502         rtl8169_get_mac_version(tp, cfg->default_ver);
7503
7504         if (rtl_tbi_enabled(tp)) {
7505                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7506                 return -ENODEV;
7507         }
7508
7509         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7510
7511         if ((sizeof(dma_addr_t) > 4) &&
7512             (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7513                               tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7514             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7515             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7516
7517                 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7518                 if (!pci_is_pcie(pdev))
7519                         tp->cp_cmd |= PCIDAC;
7520                 dev->features |= NETIF_F_HIGHDMA;
7521         } else {
7522                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7523                 if (rc < 0) {
7524                         dev_err(&pdev->dev, "DMA configuration failed\n");
7525                         return rc;
7526                 }
7527         }
7528
7529         rtl_init_rxcfg(tp);
7530
7531         rtl_irq_disable(tp);
7532
7533         rtl_hw_initialize(tp);
7534
7535         rtl_hw_reset(tp);
7536
7537         rtl_ack_events(tp, 0xffff);
7538
7539         pci_set_master(pdev);
7540
7541         rtl_init_mdio_ops(tp);
7542         rtl_init_jumbo_ops(tp);
7543
7544         rtl8169_print_mac_version(tp);
7545
7546         chipset = tp->mac_version;
7547
7548         rc = rtl_alloc_irq(tp);
7549         if (rc < 0) {
7550                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7551                 return rc;
7552         }
7553
7554         /* override BIOS settings, use userspace tools to enable WOL */
7555         __rtl8169_set_wol(tp, 0);
7556
7557         mutex_init(&tp->wk.mutex);
7558         u64_stats_init(&tp->rx_stats.syncp);
7559         u64_stats_init(&tp->tx_stats.syncp);
7560
7561         /* Get MAC address */
7562         switch (tp->mac_version) {
7563                 u8 mac_addr[ETH_ALEN] __aligned(4);
7564         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7565         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7566                 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7567                 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7568
7569                 if (is_valid_ether_addr(mac_addr))
7570                         rtl_rar_set(tp, mac_addr);
7571                 break;
7572         default:
7573                 break;
7574         }
7575         for (i = 0; i < ETH_ALEN; i++)
7576                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7577
7578         dev->ethtool_ops = &rtl8169_ethtool_ops;
7579         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7580
7581         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7582
7583         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7584          * properly for all devices */
7585         dev->features |= NETIF_F_RXCSUM |
7586                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7587
7588         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7589                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7590                 NETIF_F_HW_VLAN_CTAG_RX;
7591         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7592                 NETIF_F_HIGHDMA;
7593
7594         tp->cp_cmd |= RxChkSum | RxVlan;
7595
7596         /*
7597          * Pretend we are using VLANs; This bypasses a nasty bug where
7598          * Interrupts stop flowing on high load on 8110SCd controllers.
7599          */
7600         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7601                 /* Disallow toggling */
7602                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7603
7604         switch (rtl_chip_infos[chipset].txd_version) {
7605         case RTL_TD_0:
7606                 tp->tso_csum = rtl8169_tso_csum_v1;
7607                 break;
7608         case RTL_TD_1:
7609                 tp->tso_csum = rtl8169_tso_csum_v2;
7610                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7611                 break;
7612         default:
7613                 WARN_ON_ONCE(1);
7614         }
7615
7616         dev->hw_features |= NETIF_F_RXALL;
7617         dev->hw_features |= NETIF_F_RXFCS;
7618
7619         /* MTU range: 60 - hw-specific max */
7620         dev->min_mtu = ETH_ZLEN;
7621         dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
7622
7623         tp->hw_start = cfg->hw_start;
7624         tp->event_slow = cfg->event_slow;
7625         tp->coalesce_info = cfg->coalesce_info;
7626
7627         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7628
7629         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7630                                             &tp->counters_phys_addr,
7631                                             GFP_KERNEL);
7632         if (!tp->counters)
7633                 return -ENOMEM;
7634
7635         pci_set_drvdata(pdev, dev);
7636
7637         rc = r8169_mdio_register(tp);
7638         if (rc)
7639                 return rc;
7640
7641         rc = register_netdev(dev);
7642         if (rc)
7643                 goto err_mdio_unregister;
7644
7645         netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7646                    rtl_chip_infos[chipset].name, dev->dev_addr,
7647                    (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7648                    pci_irq_vector(pdev, 0));
7649         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
7650                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
7651                            "tx checksumming: %s]\n",
7652                            rtl_chip_infos[chipset].jumbo_max,
7653                           tp->mac_version <= RTL_GIGA_MAC_VER_06 ? "ok" : "ko");
7654         }
7655
7656         if (r8168_check_dash(tp))
7657                 rtl8168_driver_start(tp);
7658
7659         if (pci_dev_run_wake(pdev))
7660                 pm_runtime_put_sync(&pdev->dev);
7661
7662         return 0;
7663
7664 err_mdio_unregister:
7665         mdiobus_unregister(tp->mii_bus);
7666         return rc;
7667 }
7668
7669 static struct pci_driver rtl8169_pci_driver = {
7670         .name           = MODULENAME,
7671         .id_table       = rtl8169_pci_tbl,
7672         .probe          = rtl_init_one,
7673         .remove         = rtl_remove_one,
7674         .shutdown       = rtl_shutdown,
7675         .driver.pm      = RTL8169_PM_OPS,
7676 };
7677
7678 module_pci_driver(rtl8169_pci_driver);